From 6665071ebe1ffed44d1b0f507470a1f110d97fbb Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Thu, 6 Oct 2016 21:37:29 +0200 Subject: [PATCH] Improved speed on amiga cycles --- Logic/68030-68000-bus.vhd | 34 +- Logic/68030_TK.SVF | 2803 +++++++ Logic/68030_TK.cmi | 13 +- Logic/68030_TK.tcl | 6559 +++++++++++++++++ Logic/68030_tk.bl2 | 2536 +++---- Logic/68030_tk.bl3 | 777 +- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 272 +- Logic/68030_tk.fti | 180 +- Logic/68030_tk.grp | 37 +- Logic/68030_tk.ipr | 2 +- Logic/68030_tk.jed | 865 ++- Logic/68030_tk.lco | 114 +- Logic/68030_tk.out | 5649 +++++++------- Logic/68030_tk.plc | 117 +- Logic/68030_tk.prd | 1050 +-- Logic/68030_tk.rpt | 1042 +-- Logic/68030_tk.tal | 29 +- Logic/68030_tk.tt2 | 995 +-- Logic/68030_tk.tt3 | 995 +-- Logic/68030_tk.tt4 | 495 +- Logic/68030_tk.tte | 495 +- Logic/68030_tk.vcl | 93 +- Logic/68030_tk.vco | 114 +- Logic/68030_tk.xrf | 2 +- Logic/BUS68030.bl0 | 2641 ++++--- Logic/BUS68030.bl1 | 2540 +++---- Logic/BUS68030.cmd | 8 - Logic/BUS68030.edi | 5021 +++++++------ Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 5169 +++++++------ Logic/BUS68030.srr | 23 +- Logic/BUS68030.srs | Bin 12886 -> 12575 bytes Logic/Programming.xcf | 6 +- Logic/bus68030.exf | 901 +-- Logic/bus68030.srf | 11 +- Logic/lattice_cmd.rs2 | 2 +- Logic/run_options.txt | 2 +- Logic/synlog/BUS68030_multi_srs_gen.srr | 2 +- Logic/synlog/bus68030_fpga_mapper.srr | 12 +- .../report/BUS68030_compiler_errors.txt | 4 +- .../report/BUS68030_compiler_runstatus.xml | 6 +- .../report/BUS68030_compiler_warnings.txt | 5 +- .../report/BUS68030_fpga_mapper_runstatus.xml | 2 +- Logic/syntmp/BUS68030_srr.htm | 61 +- Logic/syntmp/BUS68030_toc.htm | 2 +- Logic/syntmp/run_option.xml | 2 +- Logic/syntmp/statusReport.html | 10 +- Logic/synwork/BUS68030_comp.fdep | 2 +- Logic/synwork/BUS68030_comp.fdeporig | 2 +- Logic/synwork/BUS68030_comp.srs | Bin 12517 -> 12332 bytes Logic/synwork/BUS68030_comp.tlg | 5 +- Logic/synwork/BUS68030_mult.srs | Bin 12886 -> 12575 bytes Logic/synwork/BUS68030_mult_srs/skeleton.srs | Bin 1221 -> 1226 bytes Logic/synwork/BUS68030_s.srs | Bin 12517 -> 12332 bytes 55 files changed, 25710 insertions(+), 16001 deletions(-) create mode 100644 Logic/68030_TK.SVF delete mode 100644 Logic/BUS68030.cmd diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index c921c89..4ddbdb3 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -161,8 +161,8 @@ begin --here the clock is selected - CLK_OUT_PRE_D <= CLK_OUT_PRE_25; - --CLK_OUT_PRE_D <= CLK_OUT_PRE_50; + --CLK_OUT_PRE_D <= CLK_OUT_PRE_25; + CLK_OUT_PRE_D <= CLK_OUT_PRE_50; -- the external clock to the processor is generated here CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool! @@ -278,7 +278,7 @@ begin -- as030-sampling and FPU-Select - if(AS_030_D0 ='1') then -- "async" reset of various signals + if(AS_030 ='1') then -- "async" reset of various signals AS_030_000_SYNC <= '1'; DSACK1_INT <= '1'; AS_000_INT <= '1'; @@ -320,14 +320,10 @@ begin --Amiga statemachine - --if(BERR='0')then --"async" reset on errors - -- SM_AMIGA<=IDLE_P; - --end if; - case (SM_AMIGA) is when IDLE_P => --68000:S0 wait for a falling edge RW_000_INT <= '1'; - if( CLK_000_D(1)='0' and CLK_000_D(2)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! + if( CLK_000_D(4)='0' and CLK_000_D(5)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! SM_AMIGA<=IDLE_N; --go to s1 end if; when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe @@ -353,7 +349,7 @@ begin when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA if( CLK_000_NE='1' and --falling edge ((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle - (VPA_D = '1' AND BERR='0') OR --Bus error + (BERR='0') OR --Bus error (VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle )then --go to s5 SM_AMIGA<=DATA_FETCH_N; @@ -367,7 +363,10 @@ begin -- (CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge -- DSACK1_INT <='0'; --end if; - if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge + + --go to s7 dsack is sampled at the falling edge of the 030-clock + if(CLK_000_D(2)='0' and CLK_000_D(3)='1')then + --if( CLK_000_NE ='1') then SM_AMIGA<=END_CYCLE_N; DSACK1_INT <='0'; end if; @@ -471,10 +470,10 @@ begin '1'; - AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE - '0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ + AMIGA_BUS_DATA_DIR <= not RW_000 WHEN (BGACK_030_INT ='1') ELSE --Amiga READ/WRITE + --'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ '1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space - '0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space + --'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space '0'; --Point towarts TK @@ -492,9 +491,7 @@ begin A(1) <= 'Z'; AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else x"00"; SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else - "10" when SIZE_DMA ="10" else - "01" when SIZE_DMA ="01" else - "00"; + SIZE_DMA; --rw RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' --tristate on CPU cycle else RW_000_DMA; --drive on DMA-Cycle @@ -545,8 +542,9 @@ begin else '1'; -- datastrobe not ready jet --dsack - DSACK1 <= 'Z' when nEXP_SPACE = '0' --tristate on expansionboard cycle - else DSACK1_INT; -- output on amiga cycle + DSACK1 <= 'Z' when nEXP_SPACE = '0' else --tristate on expansionboard cycle + DSACK1_INT when AS_030 = '0' else -- output on amiga cycle + '1'; end Behavioral; diff --git a/Logic/68030_TK.SVF b/Logic/68030_TK.SVF new file mode 100644 index 0000000..9f4a4c6 --- /dev/null +++ b/Logic/68030_TK.SVF @@ -0,0 +1,2803 @@ + + +! Lattice Semiconductor Corp. +! Serial Vector Format (.SVF) File. +! User information: +! File name: C:\USERS\MATZE\AMIGA\HARDWAREHACKS\68030-TK\GITHUB\LOGIC\68030_TK.SVF +! CREATED BY: ispVM System Version 18.1 +! CREATION DATE: Fri Sep 23 23:32:23 2016 +! Device: M4A5-128/64 Erase,Program,Verify C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed +! LATTICE_NOTE "Device" "M4A5-128/64" +! LATTICE_NOTE "Checksum" "D04F" + + + + + + +! Initialize + +! Row_Width :792 +! Address_Length :80 +HDR 0; +HIR 0; +TDR 0; +TIR 0; +ENDDR IDLE; +ENDIR IDLE; +FREQUENCY 9.00e+005 HZ; +STATE IDLE; + + +! Check the IDCODE + +! Shift in IDCODE(0x01) instruction +SIR 6 TDI (01); +SDR 32 TDI (00000000) + TDO (2756A157) + MASK (0FFFFFFF); + + +! Program Bscan register + +! Shift in Preload(0x02) instruction +SIR 6 TDI (02); +SDR 198 TDI (00000000000000000000000000000000000000000000000000); + + +! Enable the programming mode + +! Shift in PROGRAM MODE(0x0F) instruction +SIR 6 TDI (0F); +RUNTEST IDLE 3 TCK 2.00E-002 SEC; +! Shift in Password(0x08) +SDR 5 TDI (08); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000000); + + +! Erase the device + +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (FFFFFFFFFFFFFFFFFFFF); +! Shift in ERASE ALL(0x05) instruction +SIR 6 TDI (05); +RUNTEST IDLE 3 TCK 1.00E-001 SEC; + + +! Full Address Program Fuse Map + +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +! Prog Init/shift row all 0s +SDR 80 TDI (00000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Prog Init/shift col all 0s +SDR 792 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (80000000000000000000); +! Data Row = 1 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF800FFD703E003EF8210BFE7DFFFA7EF5E9FFFF7AF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FDF3BC2FC719FFF3FFFFFFFC3F3FF7BEFFE307FE7FEF81FFBE07FEF9DFFBDF7FCF8C7FFE7BCF + F8CF1BE7847DF9FFCFFFFE1FFFFFE5FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (40000000000000000000); +! Data Row = 2 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDE1BE77FEF8E109FE7DFFFA7F6BE9FF07B5F420FDCFF87F3E7FFD3FFEF7E7841FB9FF8FF + FC67FFF3FC1FC719F7F3FFFFFFFC3FBFF7FEFFE305FE7FEF8DFFBE37FEF99FFBFE3FCF8C7FFE3BCF + F8CF1BE7847FF9FFCFF7FF1FFFFBE7FFE0BD7F); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (20000000000000000000); +! Data Row = 3 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E109FE7DFFFA7FFFE9FFFFFFF420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC718EFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF7FCF8C3FFE7BCF + F8CF1BE7847EF9FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (10000000000000000000); +! Data Row = 4 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FB9FF8FF + FC67FFF3FC3FC7193FF3FFFFFFFC3FBFF7FEFFE307EE7FEF85FFBE37FEF9DFFBFF7F8F8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDF7); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (08000000000000000000); +! Data Row = 5 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFA7C7FFA7FFFE8FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FB9FF8DF + FC27FFF1FC3FC319FFB3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7F7E7BCF + F8CF1BE7847FB9FFCFFFFF1FFFFFE7FFE0BDF7); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (04000000000000000000); +! Data Row = 6 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BFE7DFFFA7FFFE9FFFFFFF420F7CFFC7F3E7FFD3FFEF7E5841FF9FF8FF + FC47FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE205FE7FEF8DFFBE17FEF9DFFBFF7ECF8C7FFE7BCF + F8CF1BE7847FF9FFCFEFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (02000000000000000000); +! Data Row = 7 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF3CEFFDF13E77FEF8E10B7E7DFF7A7FFFE9FFFFFFF420FF8FFC7F3E7FFC3FDEF3E7040DF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE305FE7FEF89FFBE37FEF9DFFBFF7FCF8C7FFE5BCB + F8CF1BE7845FF9FFCFFFFF1FFFFFE7FFE0BDFD); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (01000000000000000000); +! Data Row = 8 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF0FF + FC67FFF3FC3FC719FFB3FFFFFFFC3FBFF7FCFFE307FE7FEF8DFFBE27FEF9DFFBFF7BCF8C7FFE7BCF + F8CF1BE7847BF9FFCFFFFF1FBFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00800000000000000000); +! Data Row = 9 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFACEFFC90BE123EF8A10BFE7DFFFA77E7E9DF9FFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFD3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFFAFF7FCF8C2FFE79CF + F88D1BE6847FF9FFCFFFFF1FFFFFE1FFE03DDF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00400000000000000000); +! Data Row = 10 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFB88FFD71BE77FEF8E10AFE7DFFFA7BF9E9EFE7E0F420FECFFC7F3E7EFD333EF7E7841FF1FF8FF + FC67FFF3FC3FC701FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFB7F7F8F8C7FFE7B4F + F8CB1BE5847BF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00200000000000000000); +! Data Row = 11 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFA7C7FFA7FFFE8FFFFFFF420FF4FFC7F3E7FFD3FFEF7E7841FE9FF8FF + FC67FFF3FC3FC711FFD3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFF97F7FCF8C7FFE7BCF + F8CF1BE7847FE9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00100000000000000000); +! Data Row = 12 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF3CEFFDF1BE77FEF8E10BFE7DFFF87FBFE1FFFFFFF420FFCFFC7B3E7FFC3FDEF3E7040FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7BCF8C7FFE73CE + F8CF1BE7847FF9FFCFFFFF17FFFFE7FFE0BDBF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00080000000000000000); +! Data Row = 13 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FF4FFC773E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE207FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00040000000000000000); +! Data Row = 14 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA705FE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FD9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE1077E7FEF8DFFBE37FEF8DFFBFF77CF8C7FFE7BCF + F8CF1BE7843DF9FFCFFFFF1FFFFFE7FFE0A0FF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00020000000000000000); +! Data Row = 15 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10B7E7DFFFA7F75E9FFFFBAF420FF8FFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC647FF3FC3FC719FBF3FFFFFFFC3FBFF7FEFFE307DE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF0BE7847DF9FFC3FFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00010000000000000000); +! Data Row = 16 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7EEBE9FD8775F420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC7187FF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE79CF + F8CF13E7847FF9FFCFFFFF1FFFFFE7FFE08DDF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00008000000000000000); +! Data Row = 17 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7BE7E9EF9FFFF420FF4FFC7F3E3FFD3FFEF7E7841BF9FF8FF + FC67FFF3FC3FC711FFF3FFFFFFFC3FBFF7FEFFE301FE7FEF8DFFBE37FEF9DFFBBF5FCF8C7FFE7BC7 + F8CF1BE7847BF9FFCFFFFF1FFFFFE7FFE0BCFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00004000000000000000); +! Data Row = 18 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA77F9E9DFE3F0F420FFCFFC7F3E7FFD3C3EF7E3841FF9FF8FF + FC67FFF37C3FC519FBF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE3BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00002000000000000000); +! Data Row = 19 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E109FE7D9FFA7FFFE9FFFFFFF420FF8FFC3F3E7FFD3FFEF7E7841FF1FF8FF + FC67FFF2FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFAFF7ECF847FFE7BCF + F8CF1BE78477F9FFCDFFFF0FFFFFE7FFE0BDDF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00001000000000000000); +! Data Row = 20 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E00BFE7C7FFA7FFFE8FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFE3FFFFFFFC3FBFF7FEFFE305FE7FEF8DFFBE37FEF9DFF9FF7FCF887FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000800000000000000); +! Data Row = 21 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFB44FFD71BE77FEF8E10BFC7DDFFA5FFFE9FFFFFFF420FF8FFC7F3E7FFD3FFEF7E7841FF9FF85F + FC65FFF0FC3FC3117FE3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF3FCF8C7FFE7ACF + F8CB1BE5847FF1FFCFFFFF1FFFFFC3FFE09DFE); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000400000000000000); +! Data Row = 22 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFACEFFC90BE113EF8A10BFE7CFFFA3FFFE97FFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC63FFF3FC3FC718FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBDF7FCF8C1FFE79CF + F8871BE3847FF9FFC5FFFF0FFFFFE7FFE0B5FF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000200000000000000); +! Data Row = 23 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FF8FFC7F3E7FFD3FFEF7E7841DF9FF8FF + FC67FFF3FC2FC719FFE3FFFFFFFC3FBFF7FEFFE307EE7FEF8DFFBE37FEF8DFFBFF7ECF887FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFC0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000100000000000000); +! Data Row = 24 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7C7FFA7FFFE8FFFFFFF420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF95FFBFF7FCF847FFE7BCF + F8CF1BE7847FF1FFCFFFFF1FFFFFE7FFE0BDFE); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000080000000000000); +! Data Row = 25 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFD71BE77FEF8E10BFE7DFFFA4FFFE9FFFFFFF420FF4FFC7F3E7FFD3FFEF7E7841EF9FF8FF + FC63FFF3FC3FC718FFF3FFFFFFFC3FBFF7FEFFE307BE7FEF8DFFBE37FEF9DFFBFF7FCF8C4FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDDF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000040000000000000); +! Data Row = 26 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFC7DFFFA3FFFE9FFFFFFF420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC7197FD3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF1FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000020000000000000); +! Data Row = 27 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA3FFFE9BFFFFFF420FFCFFC7F3E7EFD3FFEF7E7841FE9FF8FF + FC63FFF3FC3FC718FFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFAFF7F4F8C7FFE7BCB + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000010000000000000); +! Data Row = 28 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7C5FFA6FFFE8FFFFFFF420DFCFFC7F3E7FFD333EF7E7841FF9FF89F + FC66FFF0FC3FC31977F3FFFFFFFC3FBFF7FEFFE307EE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FD9FFCFFFFF1FFFFFE7FFE0BDF7); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000008000000000000); +! Data Row = 29 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF400FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFEFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF95FFBFF7FCF8C7FFE7BCF + F8CF1BE7807FF9FFCFFFFF1FFFFFE7FFE0BDBF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000004000000000000); +! Data Row = 30 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420BFCFFC5F3E7FFD3FFEF7E6841BF9FF8FE + FC67FFF3FC3FC719FF73FFFFFFFC3FBFF7FEFFE3077E7FEF8DFFBE37FEF9DFFBFF7DCF8C7FFE7BCF + F8CF1BE78477F9FFCFFFFF1FFFF7E7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000002000000000000); +! Data Row = 31 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF9CEFFDF0BE67FEF8A10B7E7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE306FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FDFFFE7FFE0BDFD); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000001000000000000); +! Data Row = 32 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE37FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC718FEF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF8DFFBFF7ECF8C7FFE7BCF + F8CF1BE7847FF9FFCFF7FF1FFFFBE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000800000000000); +! Data Row = 33 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7D3E7FFD3FFEF7E7841FF9FF8FE + FC67FBF37C3FC719F7F3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBEF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE3FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000400000000000); +! Data Row = 34 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E101FE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841DF9FF8FF + FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE3077E7FEF8DFFBE37FEF9DFFBFF3FCF8C7FFE7BCF + F8C01BE08477F9FFCFFFFF1FBFFFE7FFE0BCFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000200000000000); +! Data Row = 35 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FBB6FCF420FBCFFC7F3E7FFD3FFEF7E7841DF9FF8FF + FC67FFF3FC3FC719EFF3FFFFFFFC3FBFF7FEFFE307EE7FEF8DFFBE37FEF8DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000100000000000); +! Data Row = 36 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFCF1BE73FEF8E109FE7DFFFA7DE1E9F7CDF3F420FFCFFC773E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC709FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7F4F8C7FFE7BCF + F8CF1BE7845F79FFCFFFFF1FFFFFE7FFE0BDFB); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000080000000000); +! Data Row = 37 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCCFFDF1BE74FEF8E10AFE7DFFF87FBFE1FFFFFFF420EFCFFC7F3E7FFD0CFEF7E7841FD9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE303BE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FBE7BCE + F8CF1BE7847DF9FFCFFFFE1FFFFBE7FFE0BDBF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000040000000000); +! Data Row = 38 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBC2FFDF1BE77FEF8E10BFE7DEFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC27FFF3FC3FC719FFB3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000020000000000); +! Data Row = 39 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFC81BE733EF8E10B7E7DDFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000010000000000); +! Data Row = 40 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFD71BE77FEF8E10BFE7D7FFA7FFFE9FFFFFFF420F7CFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3F3FF7FCFFE302FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03D7F); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000008000000000); +! Data Row = 41 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7F7D3FFEF7E4841FF9FF8FF + FC67FFF3FC3FC719FDF3FFFFFFFC3FBFF7FEFFC107FE7FEF85FFBE17FEF9DFFBFD7FCF8C7FFE5BCB + F8CF1BE7845FF9FFCFFFFF1FFFFFE7FFE081FE); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000004000000000); +! Data Row = 42 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF3CEFFDF1BE77FEF8E10AFE7DFFF87FBFE1FFFFFFF420DFCFFC6F3E7FFC001EF3E3000BF9FF8FF + FC47FBF3FC3FC719FFF3FFFFFFFC3FBFF7BEFFE206FE7FEF89FFBE27FEF9DFFBFF5FCF8C7FBE33C6 + F8C01BE0843BF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000002000000000); +! Data Row = 43 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9F7B5FCF420FFCFF87F3E6FFD003EF7E0841FF9FF01F + FC07FFF07C3FC100FFF3FFFFFFFC1FBFF7FEFFE307FA7FEF8DFFBE37FEF9DFFBFF7FCF8C0FFE7BCF + F8C01BE0841FF9FFC1FFFF07FFF7E7FFE081FF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000001000000000); +! Data Row = 44 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDB1BE777EF8E10AFE7DFFFA7FC1E9FBCEF3F420FECFFC7E3E7FBD3FFEF7E78417F9FF8FF + FC67FFF3FC3FC719AFF3FFFFFFFC3FBFF7FEFFE207FE7FEF8DFFBE37FEF9DFF87F6FCF8C7FFE6BCD + F8CF1BE78477F9FFCFFFFF1FFFFFE6FFE0BCFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000800000000); +! Data Row = 45 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF9CEFFDF0BE77FEF86109FE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFFBFB7FCF8C7FFE5BCF + F8CF1BE7847FF9FFCFEFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000400000000); +! Data Row = 46 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE57FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E6FFD3FFEF7E7841FD9FF8FF + FC67FFF3FC3FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBF77DCF8C7F7E7BCF + F8CF1BE7847FE9FFCFFFFF1FFFFFE7FFE0BDFD); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000200000000); +! Data Row = 47 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE93FFFFFF420FECFFC7F3E7DFD157EF7E7841FF9FF8FF + FC63FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFB7FCF8C7FFE7BCF + F84F13E7847FF9FFCFFFFF1FFFFFE7FFE09DFB); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000100000000); +! Data Row = 48 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BF67DFFFA7FFFE8FFFFFFF420FFCFFC7F3E7BFD2ABEF7E7841FB9FF8FF + FC677FF3FC3FC7187FB3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBF77DCF8C7FFE7BCF + F8CF0BE7847FD9FFCFFFFF1FFFFFE7FFE0ADFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000080000000); +! Data Row = 49 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBC2FFDF1BE77FEF8E10BBE7C1FFA7041E8010020F420FFCFFC7F3E3FFD3FFEF7E7841DF9FF8FF + FC63FFF3FC3FC718FFD3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBBF6FCF8C7FFE79CF + F88F1BE7847FE9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000040000000); +! Data Row = 50 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420BFCFFC7F3E7FFD03FEF7E3841FF9FF8FF + FC677FF3FC3FC7197FF3FFFFFFFC3FBFF7FEFFE307F67FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7B8F + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000020000000); +! Data Row = 51 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FF90EFFDF0BE17FEF8A10BBE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF1FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FA7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000010000000); +! Data Row = 52 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFACEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFD3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE09DFD); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000008000000); +! Data Row = 53 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E5FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE3077E7FEF85FFBE17FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDBF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000004000000); +! Data Row = 54 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD003EF7E78417F9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF5FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000002000000); +! Data Row = 55 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FDCFFC773E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFBFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7A0F + F88F13E7847FF9FFC9FFFF0FFFFFE7FFE0B9FF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000001000000); +! Data Row = 56 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BFA7DFFFA7FFFE9FFF82FF420FFCFFC7F3E7FFD3FFEF7E7841FB9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE306FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE79CF + F8CF0BE7847FE9FFCFFFFF1FFFFFE3FFE09D7F); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000800000); +! Data Row = 57 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FECFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719EFF3FFFFFFFC3FBFF7FEFFE307FA7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000400000); +! Data Row = 58 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9C17FFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC519FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000200000); +! Data Row = 59 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF83F + FC67FFF3FC3FC719FDF3FFFFDFFC2FBFF7FEFFE306FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000100000); +! Data Row = 60 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000080000); +! Data Row = 61 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFCB1BE737EF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC033E7FFD3FFEF7E7841FF1FF8FF + FC67FDF3BC3FC719FBF3FFFFFFFC3FBFF7FEFFC3077E7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000040000); +! Data Row = 62 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDD1BE77BEF8E10BDE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CF1BE7847FF9FFCFFFFF17FFFFE7FFE0BDBF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000020000); +! Data Row = 63 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7841FF9FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE3077E7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CB1BE2847FF9FFCFFFFF1FFFFFE7FFE0BDBF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000010000); +! Data Row = 64 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E103DE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7FFD3FFEF7E7801FF1FF8FF + FC67FFF3FC3FC719FFF3FFFFFFFC3FBFF7FEFFE303FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CE1BE5847FB9FFCFFFFF1FFFFFE7FFE03DFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000008000); +! Data Row = 65 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7DFD2ABEF7E7841FF9FF8FF + FC67FFF3FC1FC719FFF3FFFFDFFC2FBFF7FEFFE307FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8C41BE7847FF9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000004000); +! Data Row = 66 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (3FFBCEFFDF1BE77FEF8E10BFE7DFFFA7FFFE9FFFFFFF420FFCFFC7F3E7BFD157EF7E7841FB9FF8FF + FC67FFF3FC3FC719FFB3FFFFFFFC3FBFF7FEFFE305FE7FEF8DFFBE37FEF9DFFBFF7FCF8C7FFE7BCF + F8CB1BE7847FB9FFCFFFFF1FFFFFE7FFE0BDFF); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000002000); +! Data Row = 67 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300600C0180200400C000000040000180200600C010000000080100200400C00003000000010020 + 060080180100600C0000300000C0100300000C0100000600C0180300600C0180100000C010030060 + 08018030020000180200600801001004004000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000001000); +! Data Row = 68 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300000C00002000008008000040000100200400C0100000000C0000300000800003004000018010 + 06004010000060080000300000C0080300600C0000000600C0180300600801802000008000020000 + 08000020020000180000600C0180000400C000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000800); +! Data Row = 69 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (020060080180300600C018000060040180300600C000030000080100300600C00803006000010030 + 0600C0180100600C000020020080180200200801800006004018010060040100300000C018030060 + 0C018030060000100300400C0100100400C000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000400); +! Data Row = 70 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300000C000000020000000000000401801006000018000000040080100200800800000000008010 + 00004000000000000000300200C0080300200C000000060000180000600001802000000008000000 + 00000000000000180100600400800002000000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000200); +! Data Row = 71 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (01000008000020000080000000000401000004000010000000080080000200000802004000000010 + 04000010030000000000200200400000002004010000040080080200400801800000008000020000 + 00008000000000100100400400000004008000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000100); +! Data Row = 72 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (01006000018010040040100000200C0080200200C0100200000C0100100600400003004000008030 + 020080080100200C0000300400401801006000010000060040080100400400803000004010030060 + 04018010060000000300000C00803002004000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000080); +! Data Row = 73 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300600C0180300600C0180000600C0180300600C0180300000C0180300600C01803006000018030 + 0600C0180300600C0000300600C0180300600C0180000600C0180300600C0180300000C018030060 + 0C018030060000180300600C0180300600C000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000040); +! Data Row = 74 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300000C010020020080080000400401001004000018010000080080200200801802006000010010 + 04004010030040040000300200C0100300200C018000060080180200600801800000008008020000 + 08008020000000180100600401000004008000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000020); +! Data Row = 75 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300000C000020020080080000400401001004000018010000080080200200801802006000010010 + 04004010030040000000300200C0100300200C018000060080180200600801800000008008020000 + 08008020000000180100600401000004008000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000010); +! Data Row = 76 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300600C0180300600C0180020600C0180300600C0180300040C0180300600C01803006000818030 + 0600C0180300600C0010300600C0180300600C0180020600C0180300600C0180300040C018030060 + 0C018030060008180300600C0180300600C001); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000008); +! Data Row = 77 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0200000000000002008008000040000000000600C010030000080080300000000001000000000030 + 000000000300400800003004008010020060000000000600C0180100200400801000008000000000 + 00008020060000180000000C00002000004000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000004); +! Data Row = 78 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (030000000000000000C0000000400000800006008018020000080000300000400001000000000020 + 000000080200600800003004008010020040040000000600C0180100200400801000008000010000 + 00000030040000180000200800802000004000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000002); +! Data Row = 79 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (02004008010020040080100000600801802004008010020000080100300400C01002004000010030 + 0400C0100200400800002004008010020040080100000600C0180300600C01803000008018020040 + 08010020040000100200600801002004008000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000001); +! Data Row = 80 +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Data +SDR 792 TDI (0300000C0100300000C0100000600001802000008018020004080180200600001000004000018000 + 06000010030040000000200600800002006000010000000080180000600001000000008018020000 + 08018020000000100300400001800006000000); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; + + +! Program Efuse row + +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +! Prog Init/shift row all 0s +SDR 80 TDI (00000000000000000000); +! Shift in PROGRAM MODE(0x0F) instruction +SIR 6 TDI (0F); +! Shift in Password(0x09) +SDR 5 TDI (09); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +! Shift in Efuse Data Row = 1 +SDR 792 TDI (00080100200400801002004000010020040080100200400800002004008010020040080100000400 + 80100200400801002000008010020040080100200400001002004008010020040080000200400801 + 00200400801000004008010020040080100200); +! Shift in PROGRAM(0x06) instruction +SIR 6 TDI (06); +RUNTEST IDLE 3 TCK 5.00E-002 SEC; + + +! Full Address Verify Fuse Map + +! Shift in PROGRAM MODE(0x0F) instruction +SIR 6 TDI (0F); +RUNTEST IDLE 3 TCK 2.00E-002 SEC; +! Shift in Password(0x08) +SDR 5 TDI (08); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (80000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 1 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFA7FFFFF87FFFF3FF9FBE21E7D8F31FF3DE7FFE31F3FEFBDFFB9F7FE07DFF81F7FE7FE0C7 + FF7DEFFCFC3FFFFFFFCFFF98E3F43DCFBFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042F5EFFF + F97AF7E5FFFBE7FD0841F7C007C0EBFF001FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (40000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 2 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FEBD07FFE7DFFFF8FFEFF3FF9FFE21E7D8F31FF3DC7FFE31F3FC7FDFF99F7FEC7DFFB1F7FE7FA0C7 + FF7FEFFDFC3FFFFFFFCFEF98E3F83FCFFFE63FFF1FF9DF821E7EF7FFCBFFE7CFE1FF3BF042FADE0F + F97D6FE5FFFBE7F90871F7FEE7D87BFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (20000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 3 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF9F7E21E7D8F31FF3DE7FFC31F3FEFFDFFB9F7FEC7DFFB1F7FE7FC0C7 + FF7FEFFDFC3FFFFFFFCFF718E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FFFFFF + F97FFFE5FFFBE7F90871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (10000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 4 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (EFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F1FEFFDFFB9F7FEC7DFFA1F7FE77E0C7 + FF7FEFFDFC3FFFFFFFCFFC98E3FC3FCFFFE63FFF1FF9DF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7DEE7D8BBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (08000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 5 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (EFBD07FFE7FFFFF8FFFFF3FF9DFE21E7D8F31FF3DE7EFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCDFF98C3FC3F8FFFE43FFB1FF9DF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F17FFFE5FFE3E5FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (04000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 6 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFF7F3FF9FFE21E7D8F31FF3DE7FFE31F37EFFDFFB9F7FE87DFFB1F7FE7FA047 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE23FFF1FF9FF821A7EF7FFCBFFE7CFE3FF3EF042FFFFFF + F97FFFE5FFFBE7FD0871F7DEE7D8BBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (02000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 7 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (BFBD07FFE7FFFFF8FFFFF3FF9FFA21E7D8F31FD3DA7FFE31F3FEFFDFFB9F7FEC7DFF91F7FE7FA0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FB020E7CF7BFC3FFE7CFE3FF1FF042FFFFFF + F97FFFE5EFFBE7ED0871F7FEE7C8FBFF73CFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (01000000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 8 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFDF8FFFFF3FF9FDE21E7D8F31FF3DE7FFE31F3DEFFDFFB9F7FE47DFFB1F7FE7FE0C7 + FF3FEFFDFC3FFFFFFFCDFF98E3FC3FCFFFE63FFF0FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00800000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 9 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FBBC07FF87FFFFF8FFFFF3FF9FFE2167D8B11FF39E7FF431F3FEFF5FFB9F7FEC7DFFB1F7FE6FE0C7 + FF7FEFFDFC3FFFFFFFCBFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFF9F + B97E7EE5FFFBE7FD0851F7C487D093FF735FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00400000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 10 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FDE21A7D8D31FF2DE7FFE31F1FEFEDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF80E3FC3FCFFFE63FFF1FF8FF821E7EF7CCCBF7E7CFE3FF37F042F07E7F + 7979FDE5FFFBE7F50871F7FEE7D8EBFF11DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00200000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 11 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF97FE21E7D8F31FF3DE7FFE31F3FEFE9FFB9F7FEC7DFFB1F7FE6FE0C7 + FF7FEFFDFC3FFFFFFFCBFF88E3FC3FCFFFE63FFF1FF97F821E7EF7FFCBFFE7CFE3FF2FF042FFFFFF + F17FFFE5FFE3E5FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00100000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 12 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FDBD07FFE7FFFFE8FFFFF3FF9FFE21E7D8F31F73CE7FFE31F3DEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF020E7CF7BFC3FFE7CDE3FF3FF042FFFFFF + F87FDFE1FFFBE7FD0871F7FEE7D8FBFF73CFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00080000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 13 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE047 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF2FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00040000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 14 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FF0507FFE7FFFFF8FFFFF3FF9FBC21E7D8F31FF3DE7FFE31F3EEFFDFFB1F7FEC7DFFB1F7FE7EE087 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9BF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FA0E5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00020000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 15 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFC3FF9FBE21E7D0F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7BE0C7 + FF7FEFFDFC3FFFFFFFCFDF98E3FC3FCFFE263FFF1FF9FF821E7EF7FFCBFFE7CFE3FF1FF042F5DFFF + F97AEFE5FFFBE7ED0871F7DEE7D8BBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00010000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 16 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FBB107FFE7FFFFF8FFFFF3FF9FFE21E7C8F31FF39E7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFE18E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FAEE1B + F97D77E5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00008000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 17 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FF3D07FFE7FFFFF8FFFFF3FF9FDE21E7D8F31FE3DE7FFE31F3FAFDDFFB9F7FEC7DFFB1F7FE7F80C7 + FF7FEFFDFC3FFFFFFFCFFF88E3FC3FCFFFE63FFF1FF9FD821E7EF7FFCBFFC7CFE3FF2FF042FFFF9F + 797E7DE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00004000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 18 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DC7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFDF98A3FC3ECFFFE63FFF1FF9FF821C7EF7C3CBFFE7CFE3FF3FF042F0FC7F + B979FEE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00002000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 19 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FBBD07FFE7FFFFF0FFFFB3FF9FEE21E7D8F31FF3DE7FFE21F37EFF5FFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF98E3FC3F4FFFE63FFF1FF8FF821E7EF7FFCBFFE7CFC3FF1FF042FFFFFF + F97FFFE5FF9BE7F90871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00001000000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 20 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE11F3FEFF9FFB9F7FEC7DFFB1F7FE7FA0C7 + FF7FEFFDFC3FFFFFFFC7FF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F17FFFE5FFE3E7FD0071F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000800000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 21 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (7FB907FFC3FFFFF8FFFFF3FF8FFE21A7D8D31FF35E7FFE31F3FCFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFC7FE88C3FC3F0FFFA63FFA1FF9FF821E7EF7FFCBFFE7CFE3FF1FF042FFFFFF + F97FFFA5FFBBE3FD0871F7FEE7D8EBFF22DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000400000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 22 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFAD07FFE7FFFFF0FFFFA3FF9FFE21C7D8E11FF39E7FF831F3FEFBDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFFF18E3FC3FCFFFC63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + E97FFFC5FFF3E7FD0851F7C887D093FF735FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000200000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 23 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD03FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE11F37EFFDFFB1F7FEC7DFFB1F7FE77E0C7 + FF7FEFFDFC3FFFFFFFC7FF98E3F43FCFFFE63FFF1FF9FB821E7EF7FFCBFFE7CFE3FF1FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000100000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 24 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (7FBD07FFE7FFFFF8FFFFF3FF8FFE21E7D8F31FF3DE7FFE21F3FEFFDFFA9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FFFFFF + F17FFFE5FFE3E7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000080000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 25 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FBBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FF231F3FEFFDFFB9F7FEC7DFFB1F7FE7DE0C7 + FF7FEFFDFC3FFFFFFFCFFF18E3FC3FCFFFC63FFF1FF9F7821E7EF7FFCBFFE7CFE3FF2FF042FFFFFF + F97FFF25FFFBE7FD0871F7FEE7D8EBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000040000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 26 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF8FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FC0C7 + FF7FEFFDFC3FFFFFFFCBFE98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FFFFFF + F97FFFC5FFFBE3FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000020000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 27 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FD3DE7FFE31F2FEFF5FFB9F7FEC7DFFB1F7FE7FC0C7 + FF7FEFFDFC3FFFFFFFCFFF18E3FC3FCFFFC63FFF1FF97F821E7EF7FFCBF7E7CFE3FF3FF042FFFFFF + D97FFFC5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000010000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 28 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (EFBD07FFE7FFFFF8FFFFF3FF9BFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE77E0C7 + FF7FEFFDFC3FFFFFFFCFEE98C3FC3F0FFF663FF91FF9FF821E7EF7CCCBFFE7CFE3FF3FB042FFFFFF + F17FFF65FFA3E7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000008000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 29 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FDBD07FFE7FFFFF8FFFFF3FF9FFE01E7D8F31FF3DE7FFE31F3FEFFDFFA9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FF7FFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF002FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000004000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 30 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7EFFFF8FFFFF3FF9FEE21E7D8F31FF3DE7FFE31F3BEFFDFFB9F7FEC7DFFB1F7FE7EE0C7 + FF7FEFFDFC3FFFFFFFCEFF98E3FC3FCFFFE63F7F1FF9FD82167EF7FFCBFFE7CFA3FF3FD042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000002000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 31 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (BFBD07FFE7FFFBF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F60C7 + FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7ED0851F7FE67D0FBFF739FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000001000000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 32 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7DFFFF8FFEFF3FF9FFE21E7D8F31FF3DE7FFE31F37EFFDFFB1F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCF7F18E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEC7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000800000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 33 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFC7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEF7DFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFEF98E3FC3ECFDFE63F7F1FF9FF821E7EF7FFCBFFE7CBE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000400000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 34 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FF3D07FFE7FFFDF8FFFFF3FF9FEE2107D8031FF3DE7FFE31F3FCFFDFFB9F7FEC7DFFB1F7FE7EE0C7 + FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9FB821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7F80871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000200000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 35 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB1F7FEC7DFFB1F7FE77E0C7 + FF7FEFFDFC3FFFFFFFCFF798E3FC3FCFFFE63FFF1FF9FB821E7EF7FFCBFFE7CFE3FF3DF042F3F6DD + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000100000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 36 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (DFBD07FFE7FFFFF8FFFFF3FF9EFA21E7D8F31FF3DE7FFE31F2FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF90E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3FF042FCFB3E + F9787BE5FFFBE7F90871F7FCE7D8F3FF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000080000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 37 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FDBD07FFE7DFFFF87FFFF3FF9FBE21E7D8F31F73DE7DFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7DC0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9BF821E7EF7F30BFFE7CFE3FF3F7042FFFFFF + F87FDFE1FFFBE7F50871F7F2E7D8FBFF33DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000040000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 38 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCDFF98E3FC3FCFFFE43FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FF7BE7FD0871F7FEE7D8FBFF43DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000020000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 39 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFBBE7ED0871F7CCE7D813FF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000010000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 40 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FEBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F40C7 + FF3FEFFCFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3EF042FFFFFF + F97FFFE5FFEBE7FD0871F7FEE7D8EBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000008000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 41 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (7F8107FFE7FFFFF8FFFFF3FF9FFA21E7D8F31FD3DA7FFE31F3FEBFDFFB9F7FE87DFFA1F7FE7FE083 + FF7FEFFDFC3FFFFFFFCFBF98E3FC3FCFFFE63FFF1FF9FF82127EF7FFCBEFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000004000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 42 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FDC2107D8031F63CC7DFE31F3FAFFDFFB9F7FE47DFF91F7FE7F6047 + FF7DEFFDFC3FFFFFFFCFFF98E3FC3FCFDFE23FFF1FF9FD000C7CF78003FFE7CF63FF3FB042FFFFFF + F87FDFE1FFFBE7F50871F7FEE7D8FBFF73CFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000002000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 43 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FF8107FFE7EFFFE0FFFF83FF9FF82107D8031FF3DE7FF031F3FEFFDFFB9F7FEC7DFFB1F7FE5FE0C7 + FF7FEFFDF83FFFFFFFCFFF0083FC3E0FFFE03FF80FF9FF82107EF7C00BFF67CFE1FF3FF042F3FADE + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000001000000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 44 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FF3D07FF67FFFFF8FFFFF3FF9FEE21E7D8F31FB3D67FFE31F3F6FE1FFB9F7FEC7DFFB1F7FE7FE047 + FF7FEFFDFC3FFFFFFFCFF598E3FC3FCFFFE63FFF1FF9FE821E7EF7FFCBDFE7C7E3FF37F042FCF73D + F9783FE5FFFBE7F50871F7EEE7D8DBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000800000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 45 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFF7F3FF9FFE21E7D8F31FF3DA7FFE31F3FEDFDFFB9F7FEC7DFFB1F7FE6FE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7F90861F7FEE7D0FBFF739FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000400000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 46 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (BFBD07FFE7FFFFF8FFFFF3FF97FE21E7D8F31FF3DE7EFE31F3BEEFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF98E3FC3FCFFFE63FFF1FF9BF821E7EF7FFCBFF67CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEA7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000200000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 47 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (DFB907FFE7FFFFF8FFFFF3FF9FFE21E7C8F21FF3DE7FFE31F3FEDFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFC63FFF1FF9FF821E7EF7EA8BFBE7CFE3FF37F042FFFFFF + C97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000100000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 48 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFB507FFE7FFFFF8FFFFF3FF9BFE21E7D0F31FF3DE7FFE31F3BEEFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCDFE18E3FC3FCFFEE63FFF1FF9DF821E7EF7D54BFDE7CFE3FF3FF042FFFFFF + F17FFFE5FFFBE6FD0871F7DEE7D8BBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000080000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 49 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF97FE21E7D8F11FF39E7FFE31F3F6FDDFFB9F7FEC7DFFB1F7FE7FC0C7 + FF7FEFFDFC3FFFFFFFCBFF18E3FC3FCFFFC63FFF1FF9FB821E7EF7FFCBFFC7CFE3FF3FF042F04008 + 017820E5FF83E7DD0871F7FEE7D8FBFF43DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000040000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 50 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF1DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE6FE0C7 + FF7FEFFDFC3FFFFFFFCFFE98E3FC3FCFFEE63FFF1FF9FF821C7EF7FC0BFFE7CFE3FF3FD042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000020000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 51 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE5FE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3F8FFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7DD0851F7FE87D0FBFF709FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000010000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 52 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (BFB907FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCBFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF735FFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000008000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 53 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FDBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FE87DFFA1F7FE7EE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFA7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000004000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 54 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FAFFDFFB9F7FEC7DFFB1F7FE7FC0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FE821E7EF7C00BFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000002000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 55 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FF9D07FFE7FFFFF0FFFF93FF9FFE21E7C8F11FF05E7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFDFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CEE3FF3BF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000001000000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 56 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FEB907FFC7FFFFF8FFFFF3FF97FE21E7D0F31FF39E7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F60C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9DF821E7EF7FFCBFFE7CFE3FF3FF042FF41FF + F97FFFE5FFFBE5FD0871F7DEE7D8BBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000800000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 57 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE5FE0C7 + FF7FEFFDFC3FFFFFFFCFF798E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF37F042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000400000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 58 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF98A3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFE8 + 397FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000200000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 59 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7F60C7 + FF7FEFFDF43FFBFFFFCFBF98E3FC3FCFFFE63FFC1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000100000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 60 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000080000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 61 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7EE0C3 + FF7FEFFDFC3FFFFFFFCFDF98E3FC3DCFBFE63FFF1FF8FF821E7EF7FFCBFFE7CC03FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7ECE7D8D3FF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000040000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 62 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FDBD07FFE7FFFFE8FFFFF3FF9FFE21E7D8F31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7BD0871F7DEE7D8BBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000020000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 63 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FDBD07FFE7FFFFF8FFFFF3FF9FFE2147D8D31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7EE0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF9FF821E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000010000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 64 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBC07FFE7FFFFF8FFFFF3FF9DFE21A7D8731FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FC0C7 + FF7FEFFDFC3FFFFFFFCFFF98E3FC3FCFFFE63FFF1FF8FF801E7EF7FFCBFFE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7BC0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000008000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 65 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9FFE21E7D8231FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FE0C7 + FF7FEFFDF43FFBFFFFCFFF98E3F83FCFFFE63FFF1FF9FF821E7EF7D54BFBE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000004000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 66 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (FFBD07FFE7FFFFF8FFFFF3FF9DFE21E7D8D31FF3DE7FFE31F3FEFFDFFB9F7FEC7DFFB1F7FE7FA0C7 + FF7FEFFDFC3FFFFFFFCDFF98E3FC3FCFFFE63FFF1FF9DF821E7EF7EA8BFDE7CFE3FF3FF042FFFFFF + F97FFFE5FFFBE7FD0871F7FEE7D8FBFF73DFFC) + MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000002000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 67 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00020002080008010420041080004008410801042084008210000801082104208410821042000008 + 21000084008210000840002104208010801042004008000000840002100200400801000000008210 + 42004108000020000002100200410821042084) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000001000); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 68 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00021002000108210420001080004000400001000004000010000041080104208410821042000000 + 21042084100210000840000104200000820042080108000020840000100008400021000000008210 + 02004008000020001000100000400021000084) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000800); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 69 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00021002080008210020840080004208410821042084108210000840082004208010820042000108 + 01040004108010400040002104208010821042084008000420841002104208400801000084000210 + 42084108200420001082104208410801042004) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000400); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 70 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00000040000100200420801080000000000000000000100000000041080004200010800042000000 + 21040084100210400840000000000000020000080100000000001000104008010020000000108000 + 42080108200000000000004000000021000084) + MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 + 21042084108210420848002104208410821042084109000420841082104208410821200084108210 + 42084108210424001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000200); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 71 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00001002000000200020800080000000010000000004000010000001080100200410001002000008 + 20040000000200400040000000008400800002080000000020041000004000010001000000008000 + 02000008200000000000100000400001000080) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000100); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 72 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00020040084100210000840000004208010820042084008200000841002000208010020042000008 + 00042080108200020840002104008010001040084100000020840002004208000821000004008210 + 40004100210400000082000208010800042080) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000080); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 73 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000040); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 74 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00001002000008200420801080000000410001000004100010000001080104200410801042000108 + 21040084008210400840002000208400820002080008000420041080104000410001000080108000 + 02080008200020001000104000400821000084) + MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 + 21042084108210420848002104208410821042084109000420841082104208410821200084108210 + 42084108210424001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000020); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 75 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00001002000008200420801080000000410001000004100010000001080104200410801042000108 + 21040084008210400840000000208400820002080008000420041080104000410001000080108000 + 02080008200020001000104000400021000084) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000010); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 76 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (80021042084108210420841090004208410821042084108212000841082104208410821042400108 + 21042084108210420848002104208410821042084109000420841082104208410821200084108210 + 42084108210424001082104208410821042084) + MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 + 21042084108210420848002104208410821042084109000420841082104208410821200084108210 + 42084108210424001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000008); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 77 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00020000004000210000001080004200410000000000000010000801002004008010821042000000 + 00042004008010020840000100208400000000084000000000800000000008410001000084008210 + 42000000000020001000104000000000000004) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000004); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 78 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00020000004100010400001080000208400000000080000010000801002004008010821042000000 + 20002004008010020840000104200410000000004000000000800002000008400001000004108010 + 42000100000020000002100000000000000084) + MASK (80021042084108210420841090004208410821042084108212000841082104208410821042400108 + 21042084108210420848002104208410821042084109000420841082104208410821200084108210 + 42084108210424001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000002); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 79 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00001002004008010420040080000200400801002004108010000841082104208410821042000008 + 01002004008010020040000100200400821002084008000020040082100208400801000004008010 + 02004108010420000080100200400801002004) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821000084108210 + 42084108210420001082104208410821042084); +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +SDR 80 TDI (00000000000000000001); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift Out Data Row = 80 +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00000042000108000020840080000000410801000004108010000000080004200010801000000008 + 00042004000010420040000000208400800042000108000020000080004200410801200004108010 + 00004108000420000082100008400821000084) + MASK (00021042084108210420841080004208410821042084108210000841082104208410821042000108 + 21042084108210420840002104208410821042084108000420841082104208410821200084108210 + 42084108210420001082104208410821042084); + + +! Verify Efuse row + +! Shift in ROW(0x03) instruction +SIR 6 TDI (03); +! Prog Init/shift row all 0s +SDR 80 TDI (00000000000000000000); +! Shift in PROGRAM MODE(0x0F) instruction +SIR 6 TDI (0F); +! Shift in Password(0x09) +SDR 5 TDI (09); +! Shift in COLUMN(0x04) instruction +SIR 6 TDI (04); +SDR 792 TDI (80000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000); +! Shift in VERIFY(0x07) instruction +SIR 6 TDI (07); +! Shift in Efuse Data Row = 1 +SDR 792 TDI (00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000 + 00000000000000000000000000000000000000) + TDO (00400801002004008010020000080100200400801002004000010020040080100200400800002004 + 00801002004008010000040080100200400801002000008010020040080100200400001002004008 + 01002004008000020040080100200400801000) + MASK (00400801002004008010020020080100200400801002004004010020040080100200400800802004 + 00801002004008010010040080100200400801002002008010020040080100200400601002004008 + 01002004008008020040080100200400801001); + + +!Verify USERCODE + +! Shift in PROGRAM MODE(0x0F) instruction +SIR 6 TDI (0F); +! Shift in Password(0x0C) +SDR 5 TDI (0C); +! Shift in READ USERCODE(0x10) instruction +SIR 6 TDI (10); +RUNTEST IDLE 3 TCK 1.00E-003 SEC; +! Shift in READ USERCODE(0x10) instruction +SDR 32 TDI (00000000) + TDO (00000000) + MASK (FFFFFFFF); + + +! Exit the programming mode + +STATE IDLE; diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi index 1437f74..8e924d6 100644 --- a/Logic/68030_TK.cmi +++ b/Logic/68030_TK.cmi @@ -1,14 +1,17 @@ [WINDOWS] MAIN_WINDOW_POSITION=0,0,967,1167 LEFT_PANE_WIDTH=245 -CHILD_FRAME_STATE=Maximal -CHILD_WINDOW_SIZE=967,941 -CHILD_WINDOW_POS=-8,-31 +CHILD_FRAME_STATE=Normal +CHILD_WINDOW_SIZE=473,867 +CHILD_WINDOW_POS=473,0 +PV_FRAME_STATE=Normal +PV_WINDOW_SIZE=473,867 +PV_WINDOW_POS=0,0 [GUI SETTING] Remember_Setting=1 Open_PV_Opt=2 -Open_PV=0 -PV_IS_ACTIVE=0 +Open_PV=1 +PV_IS_ACTIVE=1 ACTIVE_SHEET=Pin Attributes Show_Def_Opt=2 Show_Def_Val=1 diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 0a5444b..ac379f4 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -400939,3 +400939,6562 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 09/14/16 23:54:13 ########### + +########## Tcl recorder starts at 09/30/16 23:16:17 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/30/16 23:16:17 ########### + + +########## Tcl recorder starts at 10/05/16 21:40:23 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:40:23 ########### + + +########## Tcl recorder starts at 10/05/16 21:40:23 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:40:23 ########### + + +########## Tcl recorder starts at 10/05/16 21:42:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:42:17 ########### + + +########## Tcl recorder starts at 10/05/16 21:42:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:42:17 ########### + + +########## Tcl recorder starts at 10/05/16 21:44:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:44:35 ########### + + +########## Tcl recorder starts at 10/05/16 21:44:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:44:36 ########### + + +########## Tcl recorder starts at 10/05/16 21:44:57 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:44:57 ########### + + +########## Tcl recorder starts at 10/05/16 21:44:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:44:58 ########### + + +########## Tcl recorder starts at 10/05/16 21:45:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:45:32 ########### + + +########## Tcl recorder starts at 10/05/16 21:45:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:45:32 ########### + + +########## Tcl recorder starts at 10/05/16 21:46:06 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:46:06 ########### + + +########## Tcl recorder starts at 10/05/16 21:47:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:47:12 ########### + + +########## Tcl recorder starts at 10/05/16 21:47:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:47:12 ########### + + +########## Tcl recorder starts at 10/05/16 21:54:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:54:47 ########### + + +########## Tcl recorder starts at 10/05/16 21:54:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/05/16 21:54:47 ########### + + +########## Tcl recorder starts at 10/06/16 15:25:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 15:25:26 ########### + + +########## Tcl recorder starts at 10/06/16 16:42:55 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:42:55 ########### + + +########## Tcl recorder starts at 10/06/16 16:42:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:42:55 ########### + + +########## Tcl recorder starts at 10/06/16 16:43:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:43:39 ########### + + +########## Tcl recorder starts at 10/06/16 16:43:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:43:39 ########### + + +########## Tcl recorder starts at 10/06/16 16:44:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:44:35 ########### + + +########## Tcl recorder starts at 10/06/16 16:44:35 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:44:35 ########### + + +########## Tcl recorder starts at 10/06/16 16:48:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:48:08 ########### + + +########## Tcl recorder starts at 10/06/16 16:48:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 16:48:08 ########### + + +########## Tcl recorder starts at 10/06/16 20:17:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:17:43 ########### + + +########## Tcl recorder starts at 10/06/16 20:17:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:17:43 ########### + + +########## Tcl recorder starts at 10/06/16 20:19:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:19:42 ########### + + +########## Tcl recorder starts at 10/06/16 20:19:42 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:19:42 ########### + + +########## Tcl recorder starts at 10/06/16 20:21:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:21:06 ########### + + +########## Tcl recorder starts at 10/06/16 20:21:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:21:06 ########### + + +########## Tcl recorder starts at 10/06/16 20:21:55 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:21:55 ########### + + +########## Tcl recorder starts at 10/06/16 20:21:56 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:21:56 ########### + + +########## Tcl recorder starts at 10/06/16 20:23:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:23:32 ########### + + +########## Tcl recorder starts at 10/06/16 20:23:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:23:32 ########### + + +########## Tcl recorder starts at 10/06/16 20:24:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:24:30 ########### + + +########## Tcl recorder starts at 10/06/16 20:24:30 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:24:30 ########### + + +########## Tcl recorder starts at 10/06/16 20:28:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:28:01 ########### + + +########## Tcl recorder starts at 10/06/16 20:28:01 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:28:01 ########### + + +########## Tcl recorder starts at 10/06/16 20:29:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:29:58 ########### + + +########## Tcl recorder starts at 10/06/16 20:29:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:29:58 ########### + + +########## Tcl recorder starts at 10/06/16 20:58:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:58:19 ########### + + +########## Tcl recorder starts at 10/06/16 20:58:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 20:58:19 ########### + + +########## Tcl recorder starts at 10/06/16 21:00:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:00:11 ########### + + +########## Tcl recorder starts at 10/06/16 21:00:11 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:00:11 ########### + + +########## Tcl recorder starts at 10/06/16 21:06:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:06:08 ########### + + +########## Tcl recorder starts at 10/06/16 21:06:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:06:08 ########### + + +########## Tcl recorder starts at 10/06/16 21:08:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:08:03 ########### + + +########## Tcl recorder starts at 10/06/16 21:08:03 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:08:03 ########### + + +########## Tcl recorder starts at 10/06/16 21:10:51 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:10:51 ########### + + +########## Tcl recorder starts at 10/06/16 21:10:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:10:54 ########### + + +########## Tcl recorder starts at 10/06/16 21:12:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:12:08 ########### + + +########## Tcl recorder starts at 10/06/16 21:12:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:12:08 ########### + + +########## Tcl recorder starts at 10/06/16 21:15:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:15:04 ########### + + +########## Tcl recorder starts at 10/06/16 21:15:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:15:04 ########### + + +########## Tcl recorder starts at 10/06/16 21:17:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:17:58 ########### + + +########## Tcl recorder starts at 10/06/16 21:17:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:17:58 ########### + + +########## Tcl recorder starts at 10/06/16 21:19:05 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:19:05 ########### + + +########## Tcl recorder starts at 10/06/16 21:19:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:19:05 ########### + + +########## Tcl recorder starts at 10/06/16 21:23:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:23:19 ########### + + +########## Tcl recorder starts at 10/06/16 21:23:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:23:20 ########### + + +########## Tcl recorder starts at 10/06/16 21:26:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:26:32 ########### + + +########## Tcl recorder starts at 10/06/16 21:26:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:26:32 ########### + + +########## Tcl recorder starts at 10/06/16 21:28:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:28:04 ########### + + +########## Tcl recorder starts at 10/06/16 21:28:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:28:04 ########### + + +########## Tcl recorder starts at 10/06/16 21:29:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:29:26 ########### + + +########## Tcl recorder starts at 10/06/16 21:29:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:29:26 ########### + + +########## Tcl recorder starts at 10/06/16 21:30:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:30:32 ########### + + +########## Tcl recorder starts at 10/06/16 21:30:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:30:32 ########### + + +########## Tcl recorder starts at 10/06/16 21:34:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:34:26 ########### + + +########## Tcl recorder starts at 10/06/16 21:34:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/06/16 21:34:26 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index cc17c64..fcada08 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,112 +1,113 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE 68030_tk #$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ -# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \ -# SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ CLK_EXP AHIGH_28_ FPU_CS AHIGH_27_ \ -# FPU_SENSE AHIGH_26_ DSACK1 AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ \ -# VPA A_DECODE_20_ VMA A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ RW A_DECODE_16_ \ -# AMIGA_ADDR_ENABLE A_DECODE_15_ AMIGA_BUS_DATA_DIR A_DECODE_14_ \ -# AMIGA_BUS_ENABLE_LOW A_DECODE_13_ AMIGA_BUS_ENABLE_HIGH A_DECODE_12_ CIIN \ -# A_DECODE_11_ A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ \ -# A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ \ -# IPL_0_ FC_0_ A_1_ -#$ NODES 602 N_130_i pos_clk_un6_bgack_000_0_n N_131_i DTACK_c_i CLK_030_H_i N_56_0 \ -# RW_000_i VPA_c_i a_i_1__n N_55_0 RESET_OUT_i N_6_i AS_030_i N_47_0 FPU_SENSE_i N_26_i \ -# inst_BGACK_030_INTreg sm_amiga_i_i_7__n N_34_0 vcc_n_n a_decode_i_16__n BG_030_c_i \ -# inst_VMA_INTreg AS_030_D0_i pos_clk_un6_bg_030_i_n gnd_n_n size_dma_i_0__n \ -# pos_clk_un9_bg_030_0_n un1_amiga_bus_enable_low size_dma_i_1__n N_25_i un6_as_030 \ -# a_decode_i_18__n N_35_0 un3_size a_decode_i_19__n N_24_i un4_size ahigh_i_30__n \ -# N_36_0 un1_LDS_000_INT ahigh_i_31__n N_17_i un1_UDS_000_INT ahigh_i_28__n N_43_0 \ -# un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_29__n N_4_i un1_DS_000_ENABLE_0_sqmuxa \ -# ahigh_i_26__n N_49_0 un4_as_000 ahigh_i_27__n N_3_i un10_ciin ahigh_i_24__n N_50_0 \ -# un21_fpu_cs ahigh_i_25__n N_215_i un21_berr N_210_i N_216_i un6_ds_030 N_211_i N_301_0 \ -# cpu_est_2_ N_212_i N_243_0 cpu_est_3_ N_266_i cpu_est_0_ un6_ds_030_i N_249_i \ -# cpu_est_1_ un4_as_000_i AMIGA_BUS_DATA_DIR_c_0 inst_AS_000_INT AS_000_INT_i N_268_i \ -# inst_AMIGA_BUS_ENABLE_DMA_LOW un6_as_030_i pos_clk_ds_000_dma_4_0_n \ -# inst_AS_030_D0 AS_030_c CLK_030_c_i inst_AS_030_000_SYNC N_236_0 \ -# inst_BGACK_030_INT_D AS_000_c un1_as_000_i inst_AS_000_DMA N_297_i inst_DS_000_DMA \ -# RW_000_c N_160_i CYCLE_DMA_0_ pos_clk_un21_bgack_030_int_i_0_i_n CYCLE_DMA_1_ \ -# N_100_i SIZE_DMA_0_ UDS_000_c N_186_0 SIZE_DMA_1_ N_183_0 inst_VPA_D LDS_000_c N_182_0 \ -# CLK_000_D_1_ N_181_0 inst_DTACK_D0 size_c_0__n N_228_i inst_RESET_OUT N_176_0 \ -# CLK_000_D_0_ size_c_1__n LDS_000_c_i inst_CLK_OUT_PRE_50 UDS_000_c_i \ -# inst_CLK_OUT_PRE_25 ahigh_c_24__n N_173_i inst_CLK_OUT_PRE_D N_304_i IPL_D0_0_ \ -# ahigh_c_25__n AS_030_000_SYNC_i IPL_D0_1_ N_157_i IPL_D0_2_ ahigh_c_26__n N_110_0 \ -# CLK_000_D_2_ RW_c_i pos_clk_un6_bg_030_n ahigh_c_27__n N_106_0 \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_284_i inst_DSACK1_INTreg ahigh_c_28__n \ -# pos_clk_ipl_n N_334_i inst_LDS_000_INT ahigh_c_29__n inst_DS_000_ENABLE N_278_i \ -# inst_UDS_000_INT ahigh_c_30__n N_279_i SM_AMIGA_6_ SM_AMIGA_4_ ahigh_c_31__n N_332_i \ -# SM_AMIGA_1_ N_237_0 SM_AMIGA_0_ un1_SM_AMIGA_0_sqmuxa_1_0 inst_RW_000_INT N_247_i \ -# inst_RW_000_DMA N_248_i RST_DLY_0_ RST_DLY_1_ N_246_i RST_DLY_2_ inst_A0_DMA \ -# pos_clk_a0_dma_3_n un10_ciin_i inst_CLK_030_H N_241_0 SM_AMIGA_5_ \ -# un1_DS_000_ENABLE_0_sqmuxa_i SM_AMIGA_3_ N_242_0 SM_AMIGA_2_ N_48_i N_227_i N_9 \ -# N_225_i N_224_i N_15 N_223_i N_16 N_22 N_218_i CLK_OUT_PRE_25_0 \ -# pos_clk_size_dma_6_0_1__n N_217_i pos_clk_size_dma_6_0_0__n N_213_i N_319_i N_300_0 \ -# N_15_i a_decode_c_16__n N_45_0 N_16_i a_decode_c_17__n N_44_0 N_22_i a_decode_c_18__n \ -# N_38_0 pos_clk_un21_bgack_030_int_i_0_i_1_n a_decode_c_19__n \ -# pos_clk_un21_bgack_030_int_i_0_i_2_n N_238_i_1 a_decode_c_20__n N_238_i_2 \ -# N_239_i_1 a_decode_c_21__n N_239_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_22__n \ -# un10_ciin_1 un10_ciin_2 a_decode_c_23__n un10_ciin_3 un10_ciin_4 a_c_0__n \ -# un10_ciin_5 un10_ciin_6 SM_AMIGA_i_7_ a_c_1__n un10_ciin_7 pos_clk_size_dma_6_0__n \ -# un10_ciin_8 pos_clk_size_dma_6_1__n nEXP_SPACE_c un10_ciin_9 G_107 un10_ciin_10 \ -# G_108 BERR_c un10_ciin_11 G_109 N_357_1 pos_clk_un21_bgack_030_int_i_0_n BG_030_c \ -# N_357_2 N_237 N_357_3 N_241 BG_000DFFreg N_357_4 N_242 N_304_i_1 un21_fpu_cs_1 N_283 \ -# BGACK_000_c un21_berr_1_0 N_294 N_266_1 N_300 CLK_030_c N_266_2 N_67_i_1 N_106 N_67_i_2 \ -# N_314_1 N_134 CLK_OSZI_c N_314_2 N_138 N_318_1 N_156 N_318_2 N_160 CLK_OUT_INTreg \ -# N_341_1 N_167 N_341_2 N_172 N_151_i_1 N_173 FPU_SENSE_c N_143_i_1 N_181 N_141_i_1 N_182 \ -# IPL_030DFF_0_reg N_237_0_1 N_183 N_240_i_1 N_191 IPL_030DFF_1_reg N_60_i_1 N_199 \ -# N_64_i_1 N_205 IPL_030DFF_2_reg N_155_i_1 N_209 N_147_i_1 N_319 ipl_c_0__n N_145_i_1 \ -# N_213 N_139_i_1 N_216 ipl_c_1__n pos_clk_un6_bg_030_1_n N_217 N_220_1 N_218 ipl_c_2__n \ -# N_216_1 N_220 N_205_1 N_223 N_199_1 N_224 DTACK_c pos_clk_ipl_1_n N_225 \ -# uds_000_int_0_un3_n N_227 uds_000_int_0_un1_n N_228 uds_000_int_0_un0_n N_246 VPA_c \ -# as_000_int_0_un3_n N_247 as_000_int_0_un1_n N_248 as_000_int_0_un0_n N_332 RST_c \ -# dsack1_int_0_un3_n N_278 dsack1_int_0_un1_n N_279 dsack1_int_0_un0_n N_334 RW_c \ -# vma_int_0_un3_n N_284 vma_int_0_un1_n N_343 fc_c_0__n vma_int_0_un0_n \ -# pos_clk_CYCLE_DMA_5_1_i_0_x2 lds_000_int_0_un3_n un21_berr_1 fc_c_1__n \ -# lds_000_int_0_un1_n N_357 lds_000_int_0_un0_n N_266 ipl_030_0_1__un3_n N_186 \ -# AMIGA_BUS_DATA_DIR_c ipl_030_0_1__un1_n pos_clk_un21_bgack_030_int_i_0_o2_2_x2 \ -# ipl_030_0_1__un0_n N_297 ipl_030_0_0__un3_n N_236 ipl_030_0_0__un1_n \ -# pos_clk_ds_000_dma_4_n ipl_030_0_0__un0_n N_268 UDS_000_INT_i cpu_est_0_3__un3_n \ -# N_249 un1_UDS_000_INT_0 cpu_est_0_3__un1_n N_243 LDS_000_INT_i cpu_est_0_3__un0_n \ -# N_215 un1_LDS_000_INT_0 cpu_est_0_2__un3_n N_130 N_23_i cpu_est_0_2__un1_n N_131 \ -# N_37_0 cpu_est_0_2__un0_n N_3 N_21_i cpu_est_0_1__un3_n N_4 N_39_0 cpu_est_0_1__un1_n \ -# N_17 N_20_i cpu_est_0_1__un0_n N_24 N_40_0 ipl_030_0_2__un3_n N_25 N_19_i \ -# ipl_030_0_2__un1_n pos_clk_un9_bg_030_n N_41_0 ipl_030_0_2__un0_n N_6 N_14_i \ -# amiga_bus_enable_dma_low_0_un3_n pos_clk_un6_bgack_000_n N_46_0 \ -# amiga_bus_enable_dma_low_0_un1_n N_26 ipl_c_i_0__n \ -# amiga_bus_enable_dma_low_0_un0_n N_208 N_52_0 rw_000_dma_0_un3_n N_207 ipl_c_i_1__n \ -# rw_000_dma_0_un1_n N_349 N_53_0 rw_000_dma_0_un0_n N_314 ipl_c_i_2__n \ -# as_000_dma_0_un3_n N_318 N_54_0 as_000_dma_0_un1_n N_348 N_27_i as_000_dma_0_un0_n \ -# N_201 N_31_0 ds_000_dma_0_un3_n N_200 N_28_i ds_000_dma_0_un1_n N_203 N_32_0 \ -# ds_000_dma_0_un0_n N_204 N_29_i bgack_030_int_0_un3_n N_185 N_33_0 \ -# bgack_030_int_0_un1_n N_184 a_c_i_0__n bgack_030_int_0_un0_n N_180 size_c_i_1__n \ -# bg_000_0_un3_n N_179 pos_clk_un10_sm_amiga_i_n bg_000_0_un1_n N_178 N_256_0 \ -# bg_000_0_un0_n N_171 N_318_i amiga_bus_enable_dma_high_0_un3_n N_341 N_314_i \ -# amiga_bus_enable_dma_high_0_un1_n N_342 pos_clk_un9_clk_000_pe_0_n \ -# amiga_bus_enable_dma_high_0_un0_n N_169 N_219_i \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n N_154 N_220_i \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n N_165 cpu_est_2_0_1__n \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n N_162 N_221_i \ -# size_dma_0_0__un3_n N_299 N_348_i size_dma_0_0__un1_n N_153 cpu_est_2_0_2__n \ -# size_dma_0_0__un0_n N_142 N_222_i size_dma_0_1__un3_n N_298 N_196_i \ -# size_dma_0_1__un1_n N_80 N_226_i size_dma_0_1__un0_n N_232 ds_000_enable_0_un3_n \ -# N_233 N_231_i ds_000_enable_0_un1_n N_229 N_229_i ds_000_enable_0_un0_n N_231 N_302_i \ -# as_030_000_sync_0_un3_n N_226 N_233_i as_030_000_sync_0_un1_n N_221 N_232_i \ -# as_030_000_sync_0_un0_n N_222 rw_000_int_0_un3_n cpu_est_2_2__n N_80_0 \ -# rw_000_int_0_un1_n cpu_est_2_1__n N_343_i rw_000_int_0_un0_n N_219 N_214_0 \ -# a0_dma_0_un3_n pos_clk_un9_clk_000_pe_n N_166_i a0_dma_0_un1_n N_256 N_134_i \ -# a0_dma_0_un0_n N_29 N_298_i a_decode_15__n N_28 N_142_0 N_27 N_153_i a_decode_14__n \ -# N_14 N_154_0 N_19 N_156_i a_decode_13__n N_20 N_305_i N_21 N_299_i a_decode_12__n N_23 \ -# N_162_0 un1_amiga_bus_enable_low_i N_165_0 a_decode_11__n un21_fpu_cs_i N_169_i \ -# cpu_est_i_1__n VMA_INT_i a_decode_10__n rst_dly_i_2__n N_341_i rst_dly_i_1__n \ -# N_342_i a_decode_9__n cpu_est_i_0__n N_171_i cpu_est_i_2__n N_172_i a_decode_8__n \ -# sm_amiga_i_0__n N_178_0 sm_amiga_i_3__n N_179_0 a_decode_7__n sm_amiga_i_4__n \ -# N_180_0 sm_amiga_i_5__n N_184_0 a_decode_6__n rst_dly_i_0__n N_185_0 sm_amiga_i_2__n \ -# N_203_i a_decode_5__n sm_amiga_i_1__n N_204_i VPA_D_i N_205_i a_decode_4__n \ -# clk_000_d_i_1__n cpu_est_i_3__n N_200_i a_decode_3__n sm_amiga_i_6__n N_199_i \ -# clk_000_d_i_0__n N_201_i a_decode_2__n BGACK_030_INT_i AS_000_i AS_000_DMA_i N_208_i \ -# nEXP_SPACE_i N_207_i cycle_dma_i_0__n N_167_i DS_000_DMA_i N_138_i \ -# AMIGA_BUS_ENABLE_DMA_LOW_i N_349_i +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 SIZE_0_ \ +# CLK_000 AHIGH_30_ CLK_OSZI AHIGH_29_ CLK_DIV_OUT AHIGH_28_ CLK_EXP AHIGH_27_ FPU_CS \ +# AHIGH_26_ FPU_SENSE AHIGH_25_ DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E \ +# A_DECODE_20_ VPA A_DECODE_19_ VMA A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ RW \ +# A_DECODE_15_ AMIGA_ADDR_ENABLE A_DECODE_14_ AMIGA_BUS_DATA_DIR A_DECODE_13_ \ +# AMIGA_BUS_ENABLE_LOW A_DECODE_12_ AMIGA_BUS_ENABLE_HIGH A_DECODE_11_ CIIN \ +# A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ \ +# A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 601 nEXP_SPACE_i N_171_i CLK_030_H_i FPU_SENSE_i N_121_i AS_030_i N_255_0 \ +# AS_000_DMA_i un1_SM_AMIGA_0_sqmuxa_1_0 AS_000_i N_48_0 AS_000_INT_i N_125_i \ +# DSACK1_INT_i N_126_i inst_BGACK_030_INTreg clk_000_d_i_0__n vcc_n_n \ +# clk_000_d_i_3__n N_127_i un5_e clk_000_d_i_1__n N_128_i inst_VMA_INTreg \ +# cpu_est_i_2__n gnd_n_n cpu_est_i_3__n RW_c_i un1_amiga_bus_enable_low \ +# a_decode_i_16__n pos_clk_rw_000_int_5_0_n un7_as_030 a_decode_i_18__n N_129_i \ +# un1_UDS_000_INT a_decode_i_19__n un1_LDS_000_INT ahigh_i_30__n \ +# un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_31__n un10_ciin_i un1_DS_000_ENABLE_0_sqmuxa \ +# ahigh_i_28__n N_261_0 un10_ciin ahigh_i_29__n N_65_0 un21_fpu_cs ahigh_i_26__n \ +# N_134_i un21_berr ahigh_i_27__n N_153_i un6_ds_030 ahigh_i_24__n N_67_0 cpu_est_3_ \ +# ahigh_i_25__n un2_as_030_i cpu_est_0_ N_206_i N_263_i cpu_est_1_ N_207_i N_265_i \ +# cpu_est_2_ N_208_i AS_030_000_SYNC_i inst_AMIGA_BUS_ENABLE_DMA_LOW N_84_0 \ +# inst_AS_030_D0 clk_000_d_i_2__n inst_AS_030_000_SYNC N_81_i N_85_i \ +# inst_BGACK_030_INT_D un6_ds_030_i N_141_i inst_AS_000_DMA DS_000_DMA_i \ +# un1_DS_000_ENABLE_0_sqmuxa_i inst_DS_000_DMA N_147_i \ +# pos_clk_un21_bgack_030_int_i_0_i_n CYCLE_DMA_0_ N_145_i N_269_i CYCLE_DMA_1_ \ +# un7_as_030_i N_90_i inst_VPA_D RESET_OUT_i N_270_i CLK_000_D_2_ AS_030_c N_271_0 \ +# CLK_000_D_3_ N_96_0 inst_DTACK_D0 AS_000_c N_97_0 inst_RESET_OUT N_98_0 CLK_000_D_1_ \ +# RW_000_c N_282_i CLK_000_D_0_ N_284_i inst_CLK_OUT_PRE_50 \ +# pos_clk_un14_clk_000_ne_i_n inst_CLK_OUT_PRE_D UDS_000_c un5_e_0 IPL_D0_0_ N_285_i \ +# IPL_D0_1_ LDS_000_c N_291_i IPL_D0_2_ N_292_i CLK_000_D_4_ size_c_0__n N_192_i \ +# pos_clk_un6_bg_030_n N_17_i inst_AMIGA_BUS_ENABLE_DMA_HIGH size_c_1__n \ +# cpu_est_2_0_2__n pos_clk_ipl_n N_286_i SM_AMIGA_1_ ahigh_c_24__n N_288_i \ +# AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa cpu_est_2_0_1__n inst_UDS_000_INT \ +# ahigh_c_25__n N_289_i inst_DS_000_ENABLE N_290_i inst_LDS_000_INT ahigh_c_26__n \ +# pos_clk_un9_clk_000_pe_0_n SM_AMIGA_6_ N_280_i SM_AMIGA_4_ ahigh_c_27__n \ +# pos_clk_un10_sm_amiga_i_n SM_AMIGA_0_ a_c_i_0__n SIZE_DMA_0_ ahigh_c_28__n \ +# size_c_i_1__n SIZE_DMA_1_ N_27_i inst_RW_000_INT ahigh_c_29__n N_30_0 \ +# inst_RW_000_DMA N_26_i RST_DLY_0_ ahigh_c_30__n N_29_0 RST_DLY_1_ N_25_i RST_DLY_2_ \ +# ahigh_c_31__n N_28_0 inst_A0_DMA ipl_c_i_2__n pos_clk_un9_clk_000_pe_n N_51_0 \ +# inst_CLK_030_H ipl_c_i_1__n pos_clk_rw_000_int_5_n N_50_0 inst_DSACK1_INT \ +# ipl_c_i_0__n inst_AS_000_INT N_49_0 SM_AMIGA_5_ N_4_i SM_AMIGA_3_ N_44_0 SM_AMIGA_2_ \ +# N_14_i N_4 N_41_0 N_15_i N_40_0 N_9 N_16_i N_39_0 N_18_i N_37_0 N_14 N_21_i N_15 N_34_0 N_16 \ +# N_23_i N_18 N_32_0 N_21 LDS_000_INT_i N_23 un1_LDS_000_INT_0 N_25 UDS_000_INT_i N_26 \ +# un1_UDS_000_INT_0 N_27 N_96_0_1 N_96_0_2 N_96_0_3 \ +# pos_clk_un21_bgack_030_int_i_0_i_1_n N_84_0_1 a_decode_c_16__n N_84_0_2 N_240_0_1 \ +# a_decode_c_17__n pos_clk_un10_sm_amiga_i_1_n N_289_1 a_decode_c_18__n N_289_2 \ +# N_290_1 a_decode_c_19__n N_290_2 pos_clk_un14_clk_000_ne_1_n a_decode_c_20__n \ +# pos_clk_un14_clk_000_ne_2_n N_153_1 a_decode_c_21__n N_153_2 N_153_3 \ +# a_decode_c_22__n N_153_4 N_153_5 a_decode_c_23__n un10_ciin_1 un10_ciin_2 a_c_0__n \ +# un10_ciin_3 un10_ciin_4 a_c_1__n un10_ciin_5 un10_ciin_6 SM_AMIGA_i_7_ nEXP_SPACE_c \ +# un10_ciin_7 cpu_est_2_1__n un10_ciin_8 cpu_est_2_2__n BERR_c un10_ciin_9 G_107 \ +# un10_ciin_10 G_108 BG_030_c un10_ciin_11 G_109 N_260_i_1 \ +# pos_clk_un21_bgack_030_int_i_0_n BG_000DFFreg N_260_i_2 N_81 N_233_i_1 N_94 \ +# N_233_i_2 N_254 BGACK_000_c N_232_i_1 N_255 N_232_i_2 N_261 CLK_030_c N_247_1 N_65 \ +# N_77_1 N_67 N_83_1 N_269 N_88_1 N_108 CLK_OSZI_c N_142_i_1 N_135 N_146_i_1 N_136 \ +# N_234_i_1 N_145 CLK_OUT_INTreg pos_clk_un6_bg_030_1_n N_278 N_124_1 N_147 un21_berr_1 \ +# N_58 FPU_SENSE_c un21_fpu_cs_1 N_110 N_140_i_1 N_239 IPL_030DFF_0_reg N_154_i_1 N_90 \ +# N_152_i_1 N_265 IPL_030DFF_1_reg N_150_i_1 pos_clk_CYCLE_DMA_5_1_i_x2 N_148_i_1 \ +# pos_clk_un21_bgack_030_int_i_0_x2 IPL_030DFF_2_reg N_144_i_1 \ +# pos_clk_un19_bgack_030_int_n N_255_0_1 N_280 ipl_c_0__n N_258_i_1 N_263 N_259_i_1 \ +# N_247 ipl_c_1__n N_282_1 N_77 N_284_1 N_289 ipl_c_2__n N_288_1 N_291 un5_e_0_1 N_290 \ +# N_192_i_1 N_286 DTACK_c pos_clk_ipl_1_n N_288 bg_000_0_un3_n N_285 bg_000_0_un1_n N_17 \ +# bg_000_0_un0_n N_292 VPA_c amiga_bus_enable_dma_low_0_un3_n \ +# pos_clk_un14_clk_000_ne_n amiga_bus_enable_dma_low_0_un1_n N_282 \ +# amiga_bus_enable_dma_low_0_un0_n N_284 RST_c a0_dma_0_un3_n N_98 a0_dma_0_un1_n N_97 \ +# a0_dma_0_un0_n N_84 RW_c rw_000_dma_0_un3_n N_96 rw_000_dma_0_un1_n N_271 fc_c_0__n \ +# rw_000_dma_0_un0_n N_117 bgack_030_int_0_un3_n N_141 fc_c_1__n \ +# bgack_030_int_0_un1_n N_134 bgack_030_int_0_un0_n N_153 ds_000_dma_0_un3_n N_129 \ +# AMIGA_BUS_DATA_DIR_c ds_000_dma_0_un1_n N_127 ds_000_dma_0_un0_n N_128 \ +# size_dma_0_1__un3_n N_125 size_dma_0_1__un1_n N_126 size_dma_0_1__un0_n N_124 \ +# BG_030_c_i size_dma_0_0__un3_n N_121 pos_clk_un6_bg_030_i_n size_dma_0_0__un1_n \ +# N_171 pos_clk_un9_bg_030_0_n size_dma_0_0__un0_n N_120 N_24_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_119 N_31_0 \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_118 N_22_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_116 N_33_0 cpu_est_0_1__un3_n N_114 \ +# N_20_i cpu_est_0_1__un1_n N_115 N_35_0 cpu_est_0_1__un0_n N_243 N_19_i \ +# cpu_est_0_2__un3_n N_240 N_36_0 cpu_est_0_2__un1_n N_88 N_8_i cpu_est_0_2__un0_n N_89 \ +# N_42_0 cpu_est_0_3__un3_n N_82 N_3_i cpu_est_0_3__un1_n N_83 N_45_0 \ +# cpu_est_0_3__un0_n N_78 VPA_c_i ipl_030_0_0__un3_n N_79 N_52_0 ipl_030_0_0__un1_n \ +# N_91 DTACK_c_i ipl_030_0_0__un0_n N_244 N_53_0 ipl_030_0_1__un3_n N_62 \ +# ipl_030_0_1__un1_n N_64 N_249_i ipl_030_0_1__un0_n N_59 N_248_i ipl_030_0_2__un3_n \ +# N_61 N_247_i ipl_030_0_2__un1_n N_163 ipl_030_0_2__un0_n N_245 N_77_i \ +# uds_000_int_0_un3_n N_242 N_251_i uds_000_int_0_un1_n N_246 N_76_i \ +# uds_000_int_0_un0_n N_248 amiga_bus_enable_dma_high_0_un3_n N_236 N_131_i \ +# amiga_bus_enable_dma_high_0_un1_n N_249 N_130_i amiga_bus_enable_dma_high_0_un0_n \ +# N_92 N_264_i as_000_dma_0_un3_n N_251 N_170_i as_000_dma_0_un1_n N_76 \ +# pos_clk_un6_bgack_000_0_n as_000_dma_0_un0_n N_80 pos_clk_rw_000_dma_3_0_n \ +# ds_000_enable_0_un3_n pos_clk_a0_dma_3_n N_123_i ds_000_enable_0_un1_n \ +# SIZE_DMA_3_sqmuxa N_124_i ds_000_enable_0_un0_n N_87 AMIGA_BUS_DATA_DIR_c_0 \ +# lds_000_int_0_un3_n pos_clk_size_dma_6_1__n N_122_i lds_000_int_0_un1_n \ +# pos_clk_size_dma_6_0__n pos_clk_ds_000_dma_4_0_n lds_000_int_0_un0_n N_170 N_242_i \ +# as_030_000_sync_0_un3_n N_122 N_239_i as_030_000_sync_0_un1_n N_123 N_87_i \ +# as_030_000_sync_0_un0_n N_130 N_236_0 rw_000_int_0_un3_n pos_clk_ds_000_dma_4_n \ +# N_246_i rw_000_int_0_un1_n pos_clk_rw_000_dma_3_n pos_clk_size_dma_6_0_0__n \ +# rw_000_int_0_un0_n pos_clk_un6_bgack_000_n N_245_i vma_int_0_un3_n N_131 \ +# pos_clk_size_dma_6_0_1__n vma_int_0_un1_n N_3 N_91_i vma_int_0_un0_n N_8 N_210_i \ +# a_decode_15__n N_19 pos_clk_un19_bgack_030_int_i_n N_20 N_163_0 a_decode_14__n N_22 \ +# N_59_i N_24 N_61_i a_decode_13__n pos_clk_un9_bg_030_n un1_amiga_bus_enable_low_i \ +# N_62_i a_decode_12__n un21_fpu_cs_i N_64_i BGACK_030_INT_i a_decode_11__n \ +# AMIGA_BUS_ENABLE_DMA_LOW_i N_244_i N_80_i a_decode_10__n cycle_dma_i_0__n N_78_i_0 \ +# RW_000_i N_79_i a_decode_9__n rst_dly_i_0__n rst_dly_i_1__n N_82_i a_decode_8__n \ +# rst_dly_i_2__n N_83_i LDS_000_i N_55_0 a_decode_7__n UDS_000_i N_88_i sm_amiga_i_2__n \ +# N_89_i a_decode_6__n N_58_i N_240_0 sm_amiga_i_3__n N_243_0 a_decode_5__n \ +# cpu_est_i_1__n CLK_030_c_i cpu_est_i_0__n N_254_0 a_decode_4__n sm_amiga_i_1__n \ +# N_114_i N_110_i N_115_i a_decode_3__n a_i_1__n VMA_INT_i N_116_i a_decode_2__n VPA_D_i \ +# N_117_i DTACK_D0_i AS_030_D0_i N_118_i sm_amiga_i_0__n sm_amiga_i_i_7__n N_119_i \ +# sm_amiga_i_6__n sm_amiga_i_5__n N_120_i sm_amiga_i_4__n .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -119,155 +120,157 @@ A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ -AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_130_i.BLIF \ -pos_clk_un6_bgack_000_0_n.BLIF N_131_i.BLIF DTACK_c_i.BLIF CLK_030_H_i.BLIF \ -N_56_0.BLIF RW_000_i.BLIF VPA_c_i.BLIF a_i_1__n.BLIF N_55_0.BLIF \ -RESET_OUT_i.BLIF N_6_i.BLIF AS_030_i.BLIF N_47_0.BLIF FPU_SENSE_i.BLIF \ -N_26_i.BLIF inst_BGACK_030_INTreg.BLIF sm_amiga_i_i_7__n.BLIF N_34_0.BLIF \ -vcc_n_n.BLIF a_decode_i_16__n.BLIF BG_030_c_i.BLIF inst_VMA_INTreg.BLIF \ -AS_030_D0_i.BLIF pos_clk_un6_bg_030_i_n.BLIF gnd_n_n.BLIF size_dma_i_0__n.BLIF \ -pos_clk_un9_bg_030_0_n.BLIF un1_amiga_bus_enable_low.BLIF size_dma_i_1__n.BLIF \ -N_25_i.BLIF un6_as_030.BLIF a_decode_i_18__n.BLIF N_35_0.BLIF un3_size.BLIF \ -a_decode_i_19__n.BLIF N_24_i.BLIF un4_size.BLIF ahigh_i_30__n.BLIF N_36_0.BLIF \ -un1_LDS_000_INT.BLIF ahigh_i_31__n.BLIF N_17_i.BLIF un1_UDS_000_INT.BLIF \ -ahigh_i_28__n.BLIF N_43_0.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_29__n.BLIF \ -N_4_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF ahigh_i_26__n.BLIF N_49_0.BLIF \ -un4_as_000.BLIF ahigh_i_27__n.BLIF N_3_i.BLIF un10_ciin.BLIF \ -ahigh_i_24__n.BLIF N_50_0.BLIF un21_fpu_cs.BLIF ahigh_i_25__n.BLIF \ -N_215_i.BLIF un21_berr.BLIF N_210_i.BLIF N_216_i.BLIF un6_ds_030.BLIF \ -N_211_i.BLIF N_301_0.BLIF cpu_est_2_.BLIF N_212_i.BLIF N_243_0.BLIF \ -cpu_est_3_.BLIF N_266_i.BLIF cpu_est_0_.BLIF un6_ds_030_i.BLIF N_249_i.BLIF \ -cpu_est_1_.BLIF un4_as_000_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ -inst_AS_000_INT.BLIF AS_000_INT_i.BLIF N_268_i.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un6_as_030_i.BLIF \ -pos_clk_ds_000_dma_4_0_n.BLIF inst_AS_030_D0.BLIF AS_030_c.BLIF \ -CLK_030_c_i.BLIF inst_AS_030_000_SYNC.BLIF N_236_0.BLIF \ -inst_BGACK_030_INT_D.BLIF AS_000_c.BLIF un1_as_000_i.BLIF inst_AS_000_DMA.BLIF \ -N_297_i.BLIF inst_DS_000_DMA.BLIF RW_000_c.BLIF N_160_i.BLIF CYCLE_DMA_0_.BLIF \ -pos_clk_un21_bgack_030_int_i_0_i_n.BLIF CYCLE_DMA_1_.BLIF N_100_i.BLIF \ -SIZE_DMA_0_.BLIF UDS_000_c.BLIF N_186_0.BLIF SIZE_DMA_1_.BLIF N_183_0.BLIF \ -inst_VPA_D.BLIF LDS_000_c.BLIF N_182_0.BLIF CLK_000_D_1_.BLIF N_181_0.BLIF \ -inst_DTACK_D0.BLIF size_c_0__n.BLIF N_228_i.BLIF inst_RESET_OUT.BLIF \ -N_176_0.BLIF CLK_000_D_0_.BLIF size_c_1__n.BLIF LDS_000_c_i.BLIF \ -inst_CLK_OUT_PRE_50.BLIF UDS_000_c_i.BLIF inst_CLK_OUT_PRE_25.BLIF \ -ahigh_c_24__n.BLIF N_173_i.BLIF inst_CLK_OUT_PRE_D.BLIF N_304_i.BLIF \ -IPL_D0_0_.BLIF ahigh_c_25__n.BLIF AS_030_000_SYNC_i.BLIF IPL_D0_1_.BLIF \ -N_157_i.BLIF IPL_D0_2_.BLIF ahigh_c_26__n.BLIF N_110_0.BLIF CLK_000_D_2_.BLIF \ -RW_c_i.BLIF pos_clk_un6_bg_030_n.BLIF ahigh_c_27__n.BLIF N_106_0.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_284_i.BLIF inst_DSACK1_INTreg.BLIF \ -ahigh_c_28__n.BLIF pos_clk_ipl_n.BLIF N_334_i.BLIF inst_LDS_000_INT.BLIF \ -ahigh_c_29__n.BLIF inst_DS_000_ENABLE.BLIF N_278_i.BLIF inst_UDS_000_INT.BLIF \ -ahigh_c_30__n.BLIF N_279_i.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF \ -ahigh_c_31__n.BLIF N_332_i.BLIF SM_AMIGA_1_.BLIF N_237_0.BLIF SM_AMIGA_0_.BLIF \ -un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_RW_000_INT.BLIF N_247_i.BLIF \ -inst_RW_000_DMA.BLIF N_248_i.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_246_i.BLIF \ -RST_DLY_2_.BLIF inst_A0_DMA.BLIF pos_clk_a0_dma_3_n.BLIF un10_ciin_i.BLIF \ -inst_CLK_030_H.BLIF N_241_0.BLIF SM_AMIGA_5_.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_3_.BLIF N_242_0.BLIF \ -SM_AMIGA_2_.BLIF N_48_i.BLIF N_227_i.BLIF N_9.BLIF N_225_i.BLIF N_224_i.BLIF \ -N_15.BLIF N_223_i.BLIF N_16.BLIF N_22.BLIF N_218_i.BLIF CLK_OUT_PRE_25_0.BLIF \ -pos_clk_size_dma_6_0_1__n.BLIF N_217_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ -N_213_i.BLIF N_319_i.BLIF N_300_0.BLIF N_15_i.BLIF a_decode_c_16__n.BLIF \ -N_45_0.BLIF N_16_i.BLIF a_decode_c_17__n.BLIF N_44_0.BLIF N_22_i.BLIF \ -a_decode_c_18__n.BLIF N_38_0.BLIF pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ -a_decode_c_19__n.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n.BLIF N_238_i_1.BLIF \ -a_decode_c_20__n.BLIF N_238_i_2.BLIF N_239_i_1.BLIF a_decode_c_21__n.BLIF \ -N_239_i_2.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_22__n.BLIF \ -un10_ciin_1.BLIF un10_ciin_2.BLIF a_decode_c_23__n.BLIF un10_ciin_3.BLIF \ -un10_ciin_4.BLIF a_c_0__n.BLIF un10_ciin_5.BLIF un10_ciin_6.BLIF \ -SM_AMIGA_i_7_.BLIF a_c_1__n.BLIF un10_ciin_7.BLIF pos_clk_size_dma_6_0__n.BLIF \ -un10_ciin_8.BLIF pos_clk_size_dma_6_1__n.BLIF nEXP_SPACE_c.BLIF \ -un10_ciin_9.BLIF G_107.BLIF un10_ciin_10.BLIF G_108.BLIF BERR_c.BLIF \ -un10_ciin_11.BLIF G_109.BLIF N_357_1.BLIF \ -pos_clk_un21_bgack_030_int_i_0_n.BLIF BG_030_c.BLIF N_357_2.BLIF N_237.BLIF \ -N_357_3.BLIF N_241.BLIF BG_000DFFreg.BLIF N_357_4.BLIF N_242.BLIF \ -N_304_i_1.BLIF un21_fpu_cs_1.BLIF N_283.BLIF BGACK_000_c.BLIF \ -un21_berr_1_0.BLIF N_294.BLIF N_266_1.BLIF N_300.BLIF CLK_030_c.BLIF \ -N_266_2.BLIF N_67_i_1.BLIF N_106.BLIF N_67_i_2.BLIF N_314_1.BLIF N_134.BLIF \ -CLK_OSZI_c.BLIF N_314_2.BLIF N_138.BLIF N_318_1.BLIF N_156.BLIF N_318_2.BLIF \ -N_160.BLIF CLK_OUT_INTreg.BLIF N_341_1.BLIF N_167.BLIF N_341_2.BLIF N_172.BLIF \ -N_151_i_1.BLIF N_173.BLIF FPU_SENSE_c.BLIF N_143_i_1.BLIF N_181.BLIF \ -N_141_i_1.BLIF N_182.BLIF IPL_030DFF_0_reg.BLIF N_237_0_1.BLIF N_183.BLIF \ -N_240_i_1.BLIF N_191.BLIF IPL_030DFF_1_reg.BLIF N_60_i_1.BLIF N_199.BLIF \ -N_64_i_1.BLIF N_205.BLIF IPL_030DFF_2_reg.BLIF N_155_i_1.BLIF N_209.BLIF \ -N_147_i_1.BLIF N_319.BLIF ipl_c_0__n.BLIF N_145_i_1.BLIF N_213.BLIF \ -N_139_i_1.BLIF N_216.BLIF ipl_c_1__n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ -N_217.BLIF N_220_1.BLIF N_218.BLIF ipl_c_2__n.BLIF N_216_1.BLIF N_220.BLIF \ -N_205_1.BLIF N_223.BLIF N_199_1.BLIF N_224.BLIF DTACK_c.BLIF \ -pos_clk_ipl_1_n.BLIF N_225.BLIF uds_000_int_0_un3_n.BLIF N_227.BLIF \ -uds_000_int_0_un1_n.BLIF N_228.BLIF uds_000_int_0_un0_n.BLIF N_246.BLIF \ -VPA_c.BLIF as_000_int_0_un3_n.BLIF N_247.BLIF as_000_int_0_un1_n.BLIF \ -N_248.BLIF as_000_int_0_un0_n.BLIF N_332.BLIF RST_c.BLIF \ -dsack1_int_0_un3_n.BLIF N_278.BLIF dsack1_int_0_un1_n.BLIF N_279.BLIF \ -dsack1_int_0_un0_n.BLIF N_334.BLIF RW_c.BLIF vma_int_0_un3_n.BLIF N_284.BLIF \ -vma_int_0_un1_n.BLIF N_343.BLIF fc_c_0__n.BLIF vma_int_0_un0_n.BLIF \ -pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF lds_000_int_0_un3_n.BLIF un21_berr_1.BLIF \ -fc_c_1__n.BLIF lds_000_int_0_un1_n.BLIF N_357.BLIF lds_000_int_0_un0_n.BLIF \ -N_266.BLIF ipl_030_0_1__un3_n.BLIF N_186.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -ipl_030_0_1__un1_n.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.BLIF \ -ipl_030_0_1__un0_n.BLIF N_297.BLIF ipl_030_0_0__un3_n.BLIF N_236.BLIF \ -ipl_030_0_0__un1_n.BLIF pos_clk_ds_000_dma_4_n.BLIF ipl_030_0_0__un0_n.BLIF \ -N_268.BLIF UDS_000_INT_i.BLIF cpu_est_0_3__un3_n.BLIF N_249.BLIF \ -un1_UDS_000_INT_0.BLIF cpu_est_0_3__un1_n.BLIF N_243.BLIF LDS_000_INT_i.BLIF \ -cpu_est_0_3__un0_n.BLIF N_215.BLIF un1_LDS_000_INT_0.BLIF \ -cpu_est_0_2__un3_n.BLIF N_130.BLIF N_23_i.BLIF cpu_est_0_2__un1_n.BLIF \ -N_131.BLIF N_37_0.BLIF cpu_est_0_2__un0_n.BLIF N_3.BLIF N_21_i.BLIF \ -cpu_est_0_1__un3_n.BLIF N_4.BLIF N_39_0.BLIF cpu_est_0_1__un1_n.BLIF N_17.BLIF \ -N_20_i.BLIF cpu_est_0_1__un0_n.BLIF N_24.BLIF N_40_0.BLIF \ -ipl_030_0_2__un3_n.BLIF N_25.BLIF N_19_i.BLIF ipl_030_0_2__un1_n.BLIF \ -pos_clk_un9_bg_030_n.BLIF N_41_0.BLIF ipl_030_0_2__un0_n.BLIF N_6.BLIF \ -N_14_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ -N_46_0.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_26.BLIF ipl_c_i_0__n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_208.BLIF N_52_0.BLIF \ -rw_000_dma_0_un3_n.BLIF N_207.BLIF ipl_c_i_1__n.BLIF rw_000_dma_0_un1_n.BLIF \ -N_349.BLIF N_53_0.BLIF rw_000_dma_0_un0_n.BLIF N_314.BLIF ipl_c_i_2__n.BLIF \ -as_000_dma_0_un3_n.BLIF N_318.BLIF N_54_0.BLIF as_000_dma_0_un1_n.BLIF \ -N_348.BLIF N_27_i.BLIF as_000_dma_0_un0_n.BLIF N_201.BLIF N_31_0.BLIF \ -ds_000_dma_0_un3_n.BLIF N_200.BLIF N_28_i.BLIF ds_000_dma_0_un1_n.BLIF \ -N_203.BLIF N_32_0.BLIF ds_000_dma_0_un0_n.BLIF N_204.BLIF N_29_i.BLIF \ -bgack_030_int_0_un3_n.BLIF N_185.BLIF N_33_0.BLIF bgack_030_int_0_un1_n.BLIF \ -N_184.BLIF a_c_i_0__n.BLIF bgack_030_int_0_un0_n.BLIF N_180.BLIF \ -size_c_i_1__n.BLIF bg_000_0_un3_n.BLIF N_179.BLIF \ -pos_clk_un10_sm_amiga_i_n.BLIF bg_000_0_un1_n.BLIF N_178.BLIF N_256_0.BLIF \ -bg_000_0_un0_n.BLIF N_171.BLIF N_318_i.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF N_341.BLIF N_314_i.BLIF \ -amiga_bus_enable_dma_high_0_un1_n.BLIF N_342.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF \ -N_169.BLIF N_219_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n.BLIF \ -N_154.BLIF N_220_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n.BLIF \ -N_165.BLIF cpu_est_2_0_1__n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n.BLIF N_162.BLIF N_221_i.BLIF \ -size_dma_0_0__un3_n.BLIF N_299.BLIF N_348_i.BLIF size_dma_0_0__un1_n.BLIF \ -N_153.BLIF cpu_est_2_0_2__n.BLIF size_dma_0_0__un0_n.BLIF N_142.BLIF \ -N_222_i.BLIF size_dma_0_1__un3_n.BLIF N_298.BLIF N_196_i.BLIF \ -size_dma_0_1__un1_n.BLIF N_80.BLIF N_226_i.BLIF size_dma_0_1__un0_n.BLIF \ -N_232.BLIF ds_000_enable_0_un3_n.BLIF N_233.BLIF N_231_i.BLIF \ -ds_000_enable_0_un1_n.BLIF N_229.BLIF N_229_i.BLIF ds_000_enable_0_un0_n.BLIF \ -N_231.BLIF N_302_i.BLIF as_030_000_sync_0_un3_n.BLIF N_226.BLIF N_233_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_221.BLIF N_232_i.BLIF \ -as_030_000_sync_0_un0_n.BLIF N_222.BLIF rw_000_int_0_un3_n.BLIF \ -cpu_est_2_2__n.BLIF N_80_0.BLIF rw_000_int_0_un1_n.BLIF cpu_est_2_1__n.BLIF \ -N_343_i.BLIF rw_000_int_0_un0_n.BLIF N_219.BLIF N_214_0.BLIF \ -a0_dma_0_un3_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_166_i.BLIF \ -a0_dma_0_un1_n.BLIF N_256.BLIF N_134_i.BLIF a0_dma_0_un0_n.BLIF N_29.BLIF \ -N_298_i.BLIF a_decode_15__n.BLIF N_28.BLIF N_142_0.BLIF N_27.BLIF N_153_i.BLIF \ -a_decode_14__n.BLIF N_14.BLIF N_154_0.BLIF N_19.BLIF N_156_i.BLIF \ -a_decode_13__n.BLIF N_20.BLIF N_305_i.BLIF N_21.BLIF N_299_i.BLIF \ -a_decode_12__n.BLIF N_23.BLIF N_162_0.BLIF un1_amiga_bus_enable_low_i.BLIF \ -N_165_0.BLIF a_decode_11__n.BLIF un21_fpu_cs_i.BLIF N_169_i.BLIF \ -cpu_est_i_1__n.BLIF VMA_INT_i.BLIF a_decode_10__n.BLIF rst_dly_i_2__n.BLIF \ -N_341_i.BLIF rst_dly_i_1__n.BLIF N_342_i.BLIF a_decode_9__n.BLIF \ -cpu_est_i_0__n.BLIF N_171_i.BLIF cpu_est_i_2__n.BLIF N_172_i.BLIF \ -a_decode_8__n.BLIF sm_amiga_i_0__n.BLIF N_178_0.BLIF sm_amiga_i_3__n.BLIF \ -N_179_0.BLIF a_decode_7__n.BLIF sm_amiga_i_4__n.BLIF N_180_0.BLIF \ -sm_amiga_i_5__n.BLIF N_184_0.BLIF a_decode_6__n.BLIF rst_dly_i_0__n.BLIF \ -N_185_0.BLIF sm_amiga_i_2__n.BLIF N_203_i.BLIF a_decode_5__n.BLIF \ -sm_amiga_i_1__n.BLIF N_204_i.BLIF VPA_D_i.BLIF N_205_i.BLIF a_decode_4__n.BLIF \ -clk_000_d_i_1__n.BLIF cpu_est_i_3__n.BLIF N_200_i.BLIF a_decode_3__n.BLIF \ -sm_amiga_i_6__n.BLIF N_199_i.BLIF clk_000_d_i_0__n.BLIF N_201_i.BLIF \ -a_decode_2__n.BLIF BGACK_030_INT_i.BLIF AS_000_i.BLIF AS_000_DMA_i.BLIF \ -N_208_i.BLIF nEXP_SPACE_i.BLIF N_207_i.BLIF cycle_dma_i_0__n.BLIF N_167_i.BLIF \ -DS_000_DMA_i.BLIF N_138_i.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_349_i.BLIF \ +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF nEXP_SPACE_i.BLIF N_171_i.BLIF \ +CLK_030_H_i.BLIF FPU_SENSE_i.BLIF N_121_i.BLIF AS_030_i.BLIF N_255_0.BLIF \ +AS_000_DMA_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF AS_000_i.BLIF N_48_0.BLIF \ +AS_000_INT_i.BLIF N_125_i.BLIF DSACK1_INT_i.BLIF N_126_i.BLIF \ +inst_BGACK_030_INTreg.BLIF clk_000_d_i_0__n.BLIF vcc_n_n.BLIF \ +clk_000_d_i_3__n.BLIF N_127_i.BLIF un5_e.BLIF clk_000_d_i_1__n.BLIF \ +N_128_i.BLIF inst_VMA_INTreg.BLIF cpu_est_i_2__n.BLIF gnd_n_n.BLIF \ +cpu_est_i_3__n.BLIF RW_c_i.BLIF un1_amiga_bus_enable_low.BLIF \ +a_decode_i_16__n.BLIF pos_clk_rw_000_int_5_0_n.BLIF un7_as_030.BLIF \ +a_decode_i_18__n.BLIF N_129_i.BLIF un1_UDS_000_INT.BLIF a_decode_i_19__n.BLIF \ +un1_LDS_000_INT.BLIF ahigh_i_30__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +ahigh_i_31__n.BLIF un10_ciin_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ +ahigh_i_28__n.BLIF N_261_0.BLIF un10_ciin.BLIF ahigh_i_29__n.BLIF N_65_0.BLIF \ +un21_fpu_cs.BLIF ahigh_i_26__n.BLIF N_134_i.BLIF un21_berr.BLIF \ +ahigh_i_27__n.BLIF N_153_i.BLIF un6_ds_030.BLIF ahigh_i_24__n.BLIF N_67_0.BLIF \ +cpu_est_3_.BLIF ahigh_i_25__n.BLIF un2_as_030_i.BLIF cpu_est_0_.BLIF \ +N_206_i.BLIF N_263_i.BLIF cpu_est_1_.BLIF N_207_i.BLIF N_265_i.BLIF \ +cpu_est_2_.BLIF N_208_i.BLIF AS_030_000_SYNC_i.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_84_0.BLIF inst_AS_030_D0.BLIF \ +clk_000_d_i_2__n.BLIF inst_AS_030_000_SYNC.BLIF N_81_i.BLIF N_85_i.BLIF \ +inst_BGACK_030_INT_D.BLIF un6_ds_030_i.BLIF N_141_i.BLIF inst_AS_000_DMA.BLIF \ +DS_000_DMA_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF inst_DS_000_DMA.BLIF \ +N_147_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF CYCLE_DMA_0_.BLIF \ +N_145_i.BLIF N_269_i.BLIF CYCLE_DMA_1_.BLIF un7_as_030_i.BLIF N_90_i.BLIF \ +inst_VPA_D.BLIF RESET_OUT_i.BLIF N_270_i.BLIF CLK_000_D_2_.BLIF AS_030_c.BLIF \ +N_271_0.BLIF CLK_000_D_3_.BLIF N_96_0.BLIF inst_DTACK_D0.BLIF AS_000_c.BLIF \ +N_97_0.BLIF inst_RESET_OUT.BLIF N_98_0.BLIF CLK_000_D_1_.BLIF RW_000_c.BLIF \ +N_282_i.BLIF CLK_000_D_0_.BLIF N_284_i.BLIF inst_CLK_OUT_PRE_50.BLIF \ +pos_clk_un14_clk_000_ne_i_n.BLIF inst_CLK_OUT_PRE_D.BLIF UDS_000_c.BLIF \ +un5_e_0.BLIF IPL_D0_0_.BLIF N_285_i.BLIF IPL_D0_1_.BLIF LDS_000_c.BLIF \ +N_291_i.BLIF IPL_D0_2_.BLIF N_292_i.BLIF CLK_000_D_4_.BLIF size_c_0__n.BLIF \ +N_192_i.BLIF pos_clk_un6_bg_030_n.BLIF N_17_i.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF size_c_1__n.BLIF cpu_est_2_0_2__n.BLIF \ +pos_clk_ipl_n.BLIF N_286_i.BLIF SM_AMIGA_1_.BLIF ahigh_c_24__n.BLIF \ +N_288_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF cpu_est_2_0_1__n.BLIF \ +inst_UDS_000_INT.BLIF ahigh_c_25__n.BLIF N_289_i.BLIF inst_DS_000_ENABLE.BLIF \ +N_290_i.BLIF inst_LDS_000_INT.BLIF ahigh_c_26__n.BLIF \ +pos_clk_un9_clk_000_pe_0_n.BLIF SM_AMIGA_6_.BLIF N_280_i.BLIF SM_AMIGA_4_.BLIF \ +ahigh_c_27__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_0_.BLIF \ +a_c_i_0__n.BLIF SIZE_DMA_0_.BLIF ahigh_c_28__n.BLIF size_c_i_1__n.BLIF \ +SIZE_DMA_1_.BLIF N_27_i.BLIF inst_RW_000_INT.BLIF ahigh_c_29__n.BLIF \ +N_30_0.BLIF inst_RW_000_DMA.BLIF N_26_i.BLIF RST_DLY_0_.BLIF \ +ahigh_c_30__n.BLIF N_29_0.BLIF RST_DLY_1_.BLIF N_25_i.BLIF RST_DLY_2_.BLIF \ +ahigh_c_31__n.BLIF N_28_0.BLIF inst_A0_DMA.BLIF ipl_c_i_2__n.BLIF \ +pos_clk_un9_clk_000_pe_n.BLIF N_51_0.BLIF inst_CLK_030_H.BLIF \ +ipl_c_i_1__n.BLIF pos_clk_rw_000_int_5_n.BLIF N_50_0.BLIF inst_DSACK1_INT.BLIF \ +ipl_c_i_0__n.BLIF inst_AS_000_INT.BLIF N_49_0.BLIF SM_AMIGA_5_.BLIF N_4_i.BLIF \ +SM_AMIGA_3_.BLIF N_44_0.BLIF SM_AMIGA_2_.BLIF N_14_i.BLIF N_4.BLIF N_41_0.BLIF \ +N_15_i.BLIF N_40_0.BLIF N_9.BLIF N_16_i.BLIF N_39_0.BLIF N_18_i.BLIF \ +N_37_0.BLIF N_14.BLIF N_21_i.BLIF N_15.BLIF N_34_0.BLIF N_16.BLIF N_23_i.BLIF \ +N_18.BLIF N_32_0.BLIF N_21.BLIF LDS_000_INT_i.BLIF N_23.BLIF \ +un1_LDS_000_INT_0.BLIF N_25.BLIF UDS_000_INT_i.BLIF N_26.BLIF \ +un1_UDS_000_INT_0.BLIF N_27.BLIF N_96_0_1.BLIF N_96_0_2.BLIF N_96_0_3.BLIF \ +pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF N_84_0_1.BLIF a_decode_c_16__n.BLIF \ +N_84_0_2.BLIF N_240_0_1.BLIF a_decode_c_17__n.BLIF \ +pos_clk_un10_sm_amiga_i_1_n.BLIF N_289_1.BLIF a_decode_c_18__n.BLIF \ +N_289_2.BLIF N_290_1.BLIF a_decode_c_19__n.BLIF N_290_2.BLIF \ +pos_clk_un14_clk_000_ne_1_n.BLIF a_decode_c_20__n.BLIF \ +pos_clk_un14_clk_000_ne_2_n.BLIF N_153_1.BLIF a_decode_c_21__n.BLIF \ +N_153_2.BLIF N_153_3.BLIF a_decode_c_22__n.BLIF N_153_4.BLIF N_153_5.BLIF \ +a_decode_c_23__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF a_c_0__n.BLIF \ +un10_ciin_3.BLIF un10_ciin_4.BLIF a_c_1__n.BLIF un10_ciin_5.BLIF \ +un10_ciin_6.BLIF SM_AMIGA_i_7_.BLIF nEXP_SPACE_c.BLIF un10_ciin_7.BLIF \ +cpu_est_2_1__n.BLIF un10_ciin_8.BLIF cpu_est_2_2__n.BLIF BERR_c.BLIF \ +un10_ciin_9.BLIF G_107.BLIF un10_ciin_10.BLIF G_108.BLIF BG_030_c.BLIF \ +un10_ciin_11.BLIF G_109.BLIF N_260_i_1.BLIF \ +pos_clk_un21_bgack_030_int_i_0_n.BLIF BG_000DFFreg.BLIF N_260_i_2.BLIF \ +N_81.BLIF N_233_i_1.BLIF N_94.BLIF N_233_i_2.BLIF N_254.BLIF BGACK_000_c.BLIF \ +N_232_i_1.BLIF N_255.BLIF N_232_i_2.BLIF N_261.BLIF CLK_030_c.BLIF \ +N_247_1.BLIF N_65.BLIF N_77_1.BLIF N_67.BLIF N_83_1.BLIF N_269.BLIF \ +N_88_1.BLIF N_108.BLIF CLK_OSZI_c.BLIF N_142_i_1.BLIF N_135.BLIF \ +N_146_i_1.BLIF N_136.BLIF N_234_i_1.BLIF N_145.BLIF CLK_OUT_INTreg.BLIF \ +pos_clk_un6_bg_030_1_n.BLIF N_278.BLIF N_124_1.BLIF N_147.BLIF \ +un21_berr_1.BLIF N_58.BLIF FPU_SENSE_c.BLIF un21_fpu_cs_1.BLIF N_110.BLIF \ +N_140_i_1.BLIF N_239.BLIF IPL_030DFF_0_reg.BLIF N_154_i_1.BLIF N_90.BLIF \ +N_152_i_1.BLIF N_265.BLIF IPL_030DFF_1_reg.BLIF N_150_i_1.BLIF \ +pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_148_i_1.BLIF \ +pos_clk_un21_bgack_030_int_i_0_x2.BLIF IPL_030DFF_2_reg.BLIF N_144_i_1.BLIF \ +pos_clk_un19_bgack_030_int_n.BLIF N_255_0_1.BLIF N_280.BLIF ipl_c_0__n.BLIF \ +N_258_i_1.BLIF N_263.BLIF N_259_i_1.BLIF N_247.BLIF ipl_c_1__n.BLIF \ +N_282_1.BLIF N_77.BLIF N_284_1.BLIF N_289.BLIF ipl_c_2__n.BLIF N_288_1.BLIF \ +N_291.BLIF un5_e_0_1.BLIF N_290.BLIF N_192_i_1.BLIF N_286.BLIF DTACK_c.BLIF \ +pos_clk_ipl_1_n.BLIF N_288.BLIF bg_000_0_un3_n.BLIF N_285.BLIF \ +bg_000_0_un1_n.BLIF N_17.BLIF bg_000_0_un0_n.BLIF N_292.BLIF VPA_c.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_un14_clk_000_ne_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF N_282.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_284.BLIF RST_c.BLIF \ +a0_dma_0_un3_n.BLIF N_98.BLIF a0_dma_0_un1_n.BLIF N_97.BLIF \ +a0_dma_0_un0_n.BLIF N_84.BLIF RW_c.BLIF rw_000_dma_0_un3_n.BLIF N_96.BLIF \ +rw_000_dma_0_un1_n.BLIF N_271.BLIF fc_c_0__n.BLIF rw_000_dma_0_un0_n.BLIF \ +N_117.BLIF bgack_030_int_0_un3_n.BLIF N_141.BLIF fc_c_1__n.BLIF \ +bgack_030_int_0_un1_n.BLIF N_134.BLIF bgack_030_int_0_un0_n.BLIF N_153.BLIF \ +ds_000_dma_0_un3_n.BLIF N_129.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +ds_000_dma_0_un1_n.BLIF N_127.BLIF ds_000_dma_0_un0_n.BLIF N_128.BLIF \ +size_dma_0_1__un3_n.BLIF N_125.BLIF size_dma_0_1__un1_n.BLIF N_126.BLIF \ +size_dma_0_1__un0_n.BLIF N_124.BLIF BG_030_c_i.BLIF size_dma_0_0__un3_n.BLIF \ +N_121.BLIF pos_clk_un6_bg_030_i_n.BLIF size_dma_0_0__un1_n.BLIF N_171.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF size_dma_0_0__un0_n.BLIF N_120.BLIF N_24_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_119.BLIF N_31_0.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_118.BLIF N_22_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_116.BLIF N_33_0.BLIF \ +cpu_est_0_1__un3_n.BLIF N_114.BLIF N_20_i.BLIF cpu_est_0_1__un1_n.BLIF \ +N_115.BLIF N_35_0.BLIF cpu_est_0_1__un0_n.BLIF N_243.BLIF N_19_i.BLIF \ +cpu_est_0_2__un3_n.BLIF N_240.BLIF N_36_0.BLIF cpu_est_0_2__un1_n.BLIF \ +N_88.BLIF N_8_i.BLIF cpu_est_0_2__un0_n.BLIF N_89.BLIF N_42_0.BLIF \ +cpu_est_0_3__un3_n.BLIF N_82.BLIF N_3_i.BLIF cpu_est_0_3__un1_n.BLIF N_83.BLIF \ +N_45_0.BLIF cpu_est_0_3__un0_n.BLIF N_78.BLIF VPA_c_i.BLIF \ +ipl_030_0_0__un3_n.BLIF N_79.BLIF N_52_0.BLIF ipl_030_0_0__un1_n.BLIF \ +N_91.BLIF DTACK_c_i.BLIF ipl_030_0_0__un0_n.BLIF N_244.BLIF N_53_0.BLIF \ +ipl_030_0_1__un3_n.BLIF N_62.BLIF ipl_030_0_1__un1_n.BLIF N_64.BLIF \ +N_249_i.BLIF ipl_030_0_1__un0_n.BLIF N_59.BLIF N_248_i.BLIF \ +ipl_030_0_2__un3_n.BLIF N_61.BLIF N_247_i.BLIF ipl_030_0_2__un1_n.BLIF \ +N_163.BLIF ipl_030_0_2__un0_n.BLIF N_245.BLIF N_77_i.BLIF \ +uds_000_int_0_un3_n.BLIF N_242.BLIF N_251_i.BLIF uds_000_int_0_un1_n.BLIF \ +N_246.BLIF N_76_i.BLIF uds_000_int_0_un0_n.BLIF N_248.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF N_236.BLIF N_131_i.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF N_249.BLIF N_130_i.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_92.BLIF N_264_i.BLIF \ +as_000_dma_0_un3_n.BLIF N_251.BLIF N_170_i.BLIF as_000_dma_0_un1_n.BLIF \ +N_76.BLIF pos_clk_un6_bgack_000_0_n.BLIF as_000_dma_0_un0_n.BLIF N_80.BLIF \ +pos_clk_rw_000_dma_3_0_n.BLIF ds_000_enable_0_un3_n.BLIF \ +pos_clk_a0_dma_3_n.BLIF N_123_i.BLIF ds_000_enable_0_un1_n.BLIF \ +SIZE_DMA_3_sqmuxa.BLIF N_124_i.BLIF ds_000_enable_0_un0_n.BLIF N_87.BLIF \ +AMIGA_BUS_DATA_DIR_c_0.BLIF lds_000_int_0_un3_n.BLIF \ +pos_clk_size_dma_6_1__n.BLIF N_122_i.BLIF lds_000_int_0_un1_n.BLIF \ +pos_clk_size_dma_6_0__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +lds_000_int_0_un0_n.BLIF N_170.BLIF N_242_i.BLIF as_030_000_sync_0_un3_n.BLIF \ +N_122.BLIF N_239_i.BLIF as_030_000_sync_0_un1_n.BLIF N_123.BLIF N_87_i.BLIF \ +as_030_000_sync_0_un0_n.BLIF N_130.BLIF N_236_0.BLIF rw_000_int_0_un3_n.BLIF \ +pos_clk_ds_000_dma_4_n.BLIF N_246_i.BLIF rw_000_int_0_un1_n.BLIF \ +pos_clk_rw_000_dma_3_n.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ +rw_000_int_0_un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_245_i.BLIF \ +vma_int_0_un3_n.BLIF N_131.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +vma_int_0_un1_n.BLIF N_3.BLIF N_91_i.BLIF vma_int_0_un0_n.BLIF N_8.BLIF \ +N_210_i.BLIF a_decode_15__n.BLIF N_19.BLIF pos_clk_un19_bgack_030_int_i_n.BLIF \ +N_20.BLIF N_163_0.BLIF a_decode_14__n.BLIF N_22.BLIF N_59_i.BLIF N_24.BLIF \ +N_61_i.BLIF a_decode_13__n.BLIF pos_clk_un9_bg_030_n.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_62_i.BLIF a_decode_12__n.BLIF \ +un21_fpu_cs_i.BLIF N_64_i.BLIF BGACK_030_INT_i.BLIF a_decode_11__n.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_244_i.BLIF N_80_i.BLIF a_decode_10__n.BLIF \ +cycle_dma_i_0__n.BLIF N_78_i_0.BLIF RW_000_i.BLIF N_79_i.BLIF \ +a_decode_9__n.BLIF rst_dly_i_0__n.BLIF rst_dly_i_1__n.BLIF N_82_i.BLIF \ +a_decode_8__n.BLIF rst_dly_i_2__n.BLIF N_83_i.BLIF LDS_000_i.BLIF N_55_0.BLIF \ +a_decode_7__n.BLIF UDS_000_i.BLIF N_88_i.BLIF sm_amiga_i_2__n.BLIF N_89_i.BLIF \ +a_decode_6__n.BLIF N_58_i.BLIF N_240_0.BLIF sm_amiga_i_3__n.BLIF N_243_0.BLIF \ +a_decode_5__n.BLIF cpu_est_i_1__n.BLIF CLK_030_c_i.BLIF cpu_est_i_0__n.BLIF \ +N_254_0.BLIF a_decode_4__n.BLIF sm_amiga_i_1__n.BLIF N_114_i.BLIF N_110_i.BLIF \ +N_115_i.BLIF a_decode_3__n.BLIF a_i_1__n.BLIF VMA_INT_i.BLIF N_116_i.BLIF \ +a_decode_2__n.BLIF VPA_D_i.BLIF N_117_i.BLIF DTACK_D0_i.BLIF AS_030_D0_i.BLIF \ +N_118_i.BLIF sm_amiga_i_0__n.BLIF sm_amiga_i_i_7__n.BLIF N_119_i.BLIF \ +sm_amiga_i_6__n.BLIF sm_amiga_i_5__n.BLIF N_120_i.BLIF sm_amiga_i_4__n.BLIF \ AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ @@ -275,162 +278,163 @@ AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ -SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \ -IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ -IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D \ -SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C CLK_000_D_2_.D CLK_000_D_2_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ -cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D \ -RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \ -inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ +IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ +IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ +SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ +CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ +CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D \ +SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ +cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ +RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D \ +inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ -inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 \ -UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_130_i pos_clk_un6_bgack_000_0_n N_131_i \ -DTACK_c_i CLK_030_H_i N_56_0 RW_000_i VPA_c_i a_i_1__n N_55_0 RESET_OUT_i \ -N_6_i AS_030_i N_47_0 FPU_SENSE_i N_26_i sm_amiga_i_i_7__n N_34_0 vcc_n_n \ -a_decode_i_16__n BG_030_c_i AS_030_D0_i pos_clk_un6_bg_030_i_n gnd_n_n \ -size_dma_i_0__n pos_clk_un9_bg_030_0_n un1_amiga_bus_enable_low \ -size_dma_i_1__n N_25_i un6_as_030 a_decode_i_18__n N_35_0 un3_size \ -a_decode_i_19__n N_24_i un4_size ahigh_i_30__n N_36_0 un1_LDS_000_INT \ -ahigh_i_31__n N_17_i un1_UDS_000_INT ahigh_i_28__n N_43_0 \ -un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_29__n N_4_i un1_DS_000_ENABLE_0_sqmuxa \ -ahigh_i_26__n N_49_0 un4_as_000 ahigh_i_27__n N_3_i un10_ciin ahigh_i_24__n \ -N_50_0 un21_fpu_cs ahigh_i_25__n N_215_i un21_berr N_210_i N_216_i un6_ds_030 \ -N_211_i N_301_0 N_212_i N_243_0 N_266_i un6_ds_030_i N_249_i un4_as_000_i \ -AMIGA_BUS_DATA_DIR_c_0 AS_000_INT_i N_268_i un6_as_030_i \ -pos_clk_ds_000_dma_4_0_n AS_030_c CLK_030_c_i N_236_0 AS_000_c un1_as_000_i \ -N_297_i RW_000_c N_160_i pos_clk_un21_bgack_030_int_i_0_i_n N_100_i UDS_000_c \ -N_186_0 N_183_0 LDS_000_c N_182_0 N_181_0 size_c_0__n N_228_i N_176_0 \ -size_c_1__n LDS_000_c_i UDS_000_c_i ahigh_c_24__n N_173_i N_304_i \ -ahigh_c_25__n AS_030_000_SYNC_i N_157_i ahigh_c_26__n N_110_0 RW_c_i \ -pos_clk_un6_bg_030_n ahigh_c_27__n N_106_0 N_284_i ahigh_c_28__n pos_clk_ipl_n \ -N_334_i ahigh_c_29__n N_278_i ahigh_c_30__n N_279_i ahigh_c_31__n N_332_i \ -N_237_0 un1_SM_AMIGA_0_sqmuxa_1_0 N_247_i N_248_i N_246_i pos_clk_a0_dma_3_n \ -un10_ciin_i N_241_0 un1_DS_000_ENABLE_0_sqmuxa_i N_242_0 N_48_i N_227_i N_9 \ -N_225_i N_224_i N_15 N_223_i N_16 N_22 N_218_i pos_clk_size_dma_6_0_1__n \ -N_217_i pos_clk_size_dma_6_0_0__n N_213_i N_319_i N_300_0 N_15_i \ -a_decode_c_16__n N_45_0 N_16_i a_decode_c_17__n N_44_0 N_22_i a_decode_c_18__n \ -N_38_0 pos_clk_un21_bgack_030_int_i_0_i_1_n a_decode_c_19__n \ -pos_clk_un21_bgack_030_int_i_0_i_2_n N_238_i_1 a_decode_c_20__n N_238_i_2 \ -N_239_i_1 a_decode_c_21__n N_239_i_2 pos_clk_un10_sm_amiga_i_1_n \ -a_decode_c_22__n un10_ciin_1 un10_ciin_2 a_decode_c_23__n un10_ciin_3 \ -un10_ciin_4 a_c_0__n un10_ciin_5 un10_ciin_6 a_c_1__n un10_ciin_7 \ -pos_clk_size_dma_6_0__n un10_ciin_8 pos_clk_size_dma_6_1__n nEXP_SPACE_c \ -un10_ciin_9 un10_ciin_10 BERR_c un10_ciin_11 N_357_1 \ -pos_clk_un21_bgack_030_int_i_0_n BG_030_c N_357_2 N_237 N_357_3 N_241 N_357_4 \ -N_242 N_304_i_1 un21_fpu_cs_1 N_283 BGACK_000_c un21_berr_1_0 N_294 N_266_1 \ -N_300 CLK_030_c N_266_2 N_67_i_1 N_106 N_67_i_2 N_314_1 N_134 CLK_OSZI_c \ -N_314_2 N_138 N_318_1 N_156 N_318_2 N_160 N_341_1 N_167 N_341_2 N_172 \ -N_151_i_1 N_173 FPU_SENSE_c N_143_i_1 N_181 N_141_i_1 N_182 N_237_0_1 N_183 \ -N_240_i_1 N_191 N_60_i_1 N_199 N_64_i_1 N_205 N_155_i_1 N_209 N_147_i_1 N_319 \ -ipl_c_0__n N_145_i_1 N_213 N_139_i_1 N_216 ipl_c_1__n pos_clk_un6_bg_030_1_n \ -N_217 N_220_1 N_218 ipl_c_2__n N_216_1 N_220 N_205_1 N_223 N_199_1 N_224 \ -DTACK_c pos_clk_ipl_1_n N_225 uds_000_int_0_un3_n N_227 uds_000_int_0_un1_n \ -N_228 uds_000_int_0_un0_n N_246 VPA_c as_000_int_0_un3_n N_247 \ -as_000_int_0_un1_n N_248 as_000_int_0_un0_n N_332 RST_c dsack1_int_0_un3_n \ -N_278 dsack1_int_0_un1_n N_279 dsack1_int_0_un0_n N_334 RW_c vma_int_0_un3_n \ -N_284 vma_int_0_un1_n N_343 fc_c_0__n vma_int_0_un0_n lds_000_int_0_un3_n \ -un21_berr_1 fc_c_1__n lds_000_int_0_un1_n N_357 lds_000_int_0_un0_n N_266 \ -ipl_030_0_1__un3_n N_186 AMIGA_BUS_DATA_DIR_c ipl_030_0_1__un1_n \ -ipl_030_0_1__un0_n N_297 ipl_030_0_0__un3_n N_236 ipl_030_0_0__un1_n \ -pos_clk_ds_000_dma_4_n ipl_030_0_0__un0_n N_268 UDS_000_INT_i \ -cpu_est_0_3__un3_n N_249 un1_UDS_000_INT_0 cpu_est_0_3__un1_n N_243 \ -LDS_000_INT_i cpu_est_0_3__un0_n N_215 un1_LDS_000_INT_0 cpu_est_0_2__un3_n \ -N_130 N_23_i cpu_est_0_2__un1_n N_131 N_37_0 cpu_est_0_2__un0_n N_3 N_21_i \ -cpu_est_0_1__un3_n N_4 N_39_0 cpu_est_0_1__un1_n N_17 N_20_i \ -cpu_est_0_1__un0_n N_24 N_40_0 ipl_030_0_2__un3_n N_25 N_19_i \ -ipl_030_0_2__un1_n pos_clk_un9_bg_030_n N_41_0 ipl_030_0_2__un0_n N_6 N_14_i \ -amiga_bus_enable_dma_low_0_un3_n pos_clk_un6_bgack_000_n N_46_0 \ -amiga_bus_enable_dma_low_0_un1_n N_26 ipl_c_i_0__n \ -amiga_bus_enable_dma_low_0_un0_n N_208 N_52_0 rw_000_dma_0_un3_n N_207 \ -ipl_c_i_1__n rw_000_dma_0_un1_n N_349 N_53_0 rw_000_dma_0_un0_n N_314 \ -ipl_c_i_2__n as_000_dma_0_un3_n N_318 N_54_0 as_000_dma_0_un1_n N_348 N_27_i \ -as_000_dma_0_un0_n N_201 N_31_0 ds_000_dma_0_un3_n N_200 N_28_i \ -ds_000_dma_0_un1_n N_203 N_32_0 ds_000_dma_0_un0_n N_204 N_29_i \ -bgack_030_int_0_un3_n N_185 N_33_0 bgack_030_int_0_un1_n N_184 a_c_i_0__n \ -bgack_030_int_0_un0_n N_180 size_c_i_1__n bg_000_0_un3_n N_179 \ -pos_clk_un10_sm_amiga_i_n bg_000_0_un1_n N_178 N_256_0 bg_000_0_un0_n N_171 \ -N_318_i amiga_bus_enable_dma_high_0_un3_n N_341 N_314_i \ -amiga_bus_enable_dma_high_0_un1_n N_342 pos_clk_un9_clk_000_pe_0_n \ -amiga_bus_enable_dma_high_0_un0_n N_169 N_219_i \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n N_154 N_220_i \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n N_165 cpu_est_2_0_1__n \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n N_162 N_221_i \ -size_dma_0_0__un3_n N_299 N_348_i size_dma_0_0__un1_n N_153 cpu_est_2_0_2__n \ -size_dma_0_0__un0_n N_142 N_222_i size_dma_0_1__un3_n N_298 N_196_i \ -size_dma_0_1__un1_n N_80 N_226_i size_dma_0_1__un0_n N_232 \ -ds_000_enable_0_un3_n N_233 N_231_i ds_000_enable_0_un1_n N_229 N_229_i \ -ds_000_enable_0_un0_n N_231 N_302_i as_030_000_sync_0_un3_n N_226 N_233_i \ -as_030_000_sync_0_un1_n N_221 N_232_i as_030_000_sync_0_un0_n N_222 \ -rw_000_int_0_un3_n cpu_est_2_2__n N_80_0 rw_000_int_0_un1_n cpu_est_2_1__n \ -N_343_i rw_000_int_0_un0_n N_219 N_214_0 a0_dma_0_un3_n \ -pos_clk_un9_clk_000_pe_n N_166_i a0_dma_0_un1_n N_256 N_134_i a0_dma_0_un0_n \ -N_29 N_298_i a_decode_15__n N_28 N_142_0 N_27 N_153_i a_decode_14__n N_14 \ -N_154_0 N_19 N_156_i a_decode_13__n N_20 N_305_i N_21 N_299_i a_decode_12__n \ -N_23 N_162_0 un1_amiga_bus_enable_low_i N_165_0 a_decode_11__n un21_fpu_cs_i \ -N_169_i cpu_est_i_1__n VMA_INT_i a_decode_10__n rst_dly_i_2__n N_341_i \ -rst_dly_i_1__n N_342_i a_decode_9__n cpu_est_i_0__n N_171_i cpu_est_i_2__n \ -N_172_i a_decode_8__n sm_amiga_i_0__n N_178_0 sm_amiga_i_3__n N_179_0 \ -a_decode_7__n sm_amiga_i_4__n N_180_0 sm_amiga_i_5__n N_184_0 a_decode_6__n \ -rst_dly_i_0__n N_185_0 sm_amiga_i_2__n N_203_i a_decode_5__n sm_amiga_i_1__n \ -N_204_i VPA_D_i N_205_i a_decode_4__n clk_000_d_i_1__n cpu_est_i_3__n N_200_i \ -a_decode_3__n sm_amiga_i_6__n N_199_i clk_000_d_i_0__n N_201_i a_decode_2__n \ -BGACK_030_INT_i AS_000_i AS_000_DMA_i N_208_i nEXP_SPACE_i N_207_i \ -cycle_dma_i_0__n N_167_i DS_000_DMA_i N_138_i AMIGA_BUS_ENABLE_DMA_LOW_i \ -N_349_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ -AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ -DSACK1.OE RESET.OE CIIN.OE CLK_OUT_PRE_25_0 G_107 G_108 G_109 \ -pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2 -.names N_145_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ +inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ +AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ \ +AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ nEXP_SPACE_i \ +N_171_i CLK_030_H_i FPU_SENSE_i N_121_i AS_030_i N_255_0 AS_000_DMA_i \ +un1_SM_AMIGA_0_sqmuxa_1_0 AS_000_i N_48_0 AS_000_INT_i N_125_i DSACK1_INT_i \ +N_126_i clk_000_d_i_0__n vcc_n_n clk_000_d_i_3__n N_127_i un5_e \ +clk_000_d_i_1__n N_128_i cpu_est_i_2__n gnd_n_n cpu_est_i_3__n RW_c_i \ +un1_amiga_bus_enable_low a_decode_i_16__n pos_clk_rw_000_int_5_0_n un7_as_030 \ +a_decode_i_18__n N_129_i un1_UDS_000_INT a_decode_i_19__n un1_LDS_000_INT \ +ahigh_i_30__n un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_31__n un10_ciin_i \ +un1_DS_000_ENABLE_0_sqmuxa ahigh_i_28__n N_261_0 un10_ciin ahigh_i_29__n \ +N_65_0 un21_fpu_cs ahigh_i_26__n N_134_i un21_berr ahigh_i_27__n N_153_i \ +un6_ds_030 ahigh_i_24__n N_67_0 ahigh_i_25__n un2_as_030_i N_206_i N_263_i \ +N_207_i N_265_i N_208_i AS_030_000_SYNC_i N_84_0 clk_000_d_i_2__n N_81_i \ +N_85_i un6_ds_030_i N_141_i DS_000_DMA_i un1_DS_000_ENABLE_0_sqmuxa_i N_147_i \ +pos_clk_un21_bgack_030_int_i_0_i_n N_145_i N_269_i un7_as_030_i N_90_i \ +RESET_OUT_i N_270_i AS_030_c N_271_0 N_96_0 AS_000_c N_97_0 N_98_0 RW_000_c \ +N_282_i N_284_i pos_clk_un14_clk_000_ne_i_n UDS_000_c un5_e_0 N_285_i \ +LDS_000_c N_291_i N_292_i size_c_0__n N_192_i pos_clk_un6_bg_030_n N_17_i \ +size_c_1__n cpu_est_2_0_2__n pos_clk_ipl_n N_286_i ahigh_c_24__n N_288_i \ +AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa cpu_est_2_0_1__n ahigh_c_25__n N_289_i \ +N_290_i ahigh_c_26__n pos_clk_un9_clk_000_pe_0_n N_280_i ahigh_c_27__n \ +pos_clk_un10_sm_amiga_i_n a_c_i_0__n ahigh_c_28__n size_c_i_1__n N_27_i \ +ahigh_c_29__n N_30_0 N_26_i ahigh_c_30__n N_29_0 N_25_i ahigh_c_31__n N_28_0 \ +ipl_c_i_2__n pos_clk_un9_clk_000_pe_n N_51_0 ipl_c_i_1__n \ +pos_clk_rw_000_int_5_n N_50_0 ipl_c_i_0__n N_49_0 N_4_i N_44_0 N_14_i N_4 \ +N_41_0 N_15_i N_40_0 N_9 N_16_i N_39_0 N_18_i N_37_0 N_14 N_21_i N_15 N_34_0 \ +N_16 N_23_i N_18 N_32_0 N_21 LDS_000_INT_i N_23 un1_LDS_000_INT_0 N_25 \ +UDS_000_INT_i N_26 un1_UDS_000_INT_0 N_27 N_96_0_1 N_96_0_2 N_96_0_3 \ +pos_clk_un21_bgack_030_int_i_0_i_1_n N_84_0_1 a_decode_c_16__n N_84_0_2 \ +N_240_0_1 a_decode_c_17__n pos_clk_un10_sm_amiga_i_1_n N_289_1 \ +a_decode_c_18__n N_289_2 N_290_1 a_decode_c_19__n N_290_2 \ +pos_clk_un14_clk_000_ne_1_n a_decode_c_20__n pos_clk_un14_clk_000_ne_2_n \ +N_153_1 a_decode_c_21__n N_153_2 N_153_3 a_decode_c_22__n N_153_4 N_153_5 \ +a_decode_c_23__n un10_ciin_1 un10_ciin_2 a_c_0__n un10_ciin_3 un10_ciin_4 \ +a_c_1__n un10_ciin_5 un10_ciin_6 nEXP_SPACE_c un10_ciin_7 cpu_est_2_1__n \ +un10_ciin_8 cpu_est_2_2__n BERR_c un10_ciin_9 un10_ciin_10 BG_030_c \ +un10_ciin_11 N_260_i_1 pos_clk_un21_bgack_030_int_i_0_n N_260_i_2 N_81 \ +N_233_i_1 N_94 N_233_i_2 N_254 BGACK_000_c N_232_i_1 N_255 N_232_i_2 N_261 \ +CLK_030_c N_247_1 N_65 N_77_1 N_67 N_83_1 N_269 N_88_1 N_108 CLK_OSZI_c \ +N_142_i_1 N_135 N_146_i_1 N_136 N_234_i_1 N_145 pos_clk_un6_bg_030_1_n N_278 \ +N_124_1 N_147 un21_berr_1 N_58 FPU_SENSE_c un21_fpu_cs_1 N_110 N_140_i_1 N_239 \ +N_154_i_1 N_90 N_152_i_1 N_265 N_150_i_1 N_148_i_1 N_144_i_1 \ +pos_clk_un19_bgack_030_int_n N_255_0_1 N_280 ipl_c_0__n N_258_i_1 N_263 \ +N_259_i_1 N_247 ipl_c_1__n N_282_1 N_77 N_284_1 N_289 ipl_c_2__n N_288_1 N_291 \ +un5_e_0_1 N_290 N_192_i_1 N_286 DTACK_c pos_clk_ipl_1_n N_288 bg_000_0_un3_n \ +N_285 bg_000_0_un1_n N_17 bg_000_0_un0_n N_292 VPA_c \ +amiga_bus_enable_dma_low_0_un3_n pos_clk_un14_clk_000_ne_n \ +amiga_bus_enable_dma_low_0_un1_n N_282 amiga_bus_enable_dma_low_0_un0_n N_284 \ +RST_c a0_dma_0_un3_n N_98 a0_dma_0_un1_n N_97 a0_dma_0_un0_n N_84 RW_c \ +rw_000_dma_0_un3_n N_96 rw_000_dma_0_un1_n N_271 fc_c_0__n rw_000_dma_0_un0_n \ +N_117 bgack_030_int_0_un3_n N_141 fc_c_1__n bgack_030_int_0_un1_n N_134 \ +bgack_030_int_0_un0_n N_153 ds_000_dma_0_un3_n N_129 AMIGA_BUS_DATA_DIR_c \ +ds_000_dma_0_un1_n N_127 ds_000_dma_0_un0_n N_128 size_dma_0_1__un3_n N_125 \ +size_dma_0_1__un1_n N_126 size_dma_0_1__un0_n N_124 BG_030_c_i \ +size_dma_0_0__un3_n N_121 pos_clk_un6_bg_030_i_n size_dma_0_0__un1_n N_171 \ +pos_clk_un9_bg_030_0_n size_dma_0_0__un0_n N_120 N_24_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_119 N_31_0 \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_118 N_22_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_116 N_33_0 cpu_est_0_1__un3_n \ +N_114 N_20_i cpu_est_0_1__un1_n N_115 N_35_0 cpu_est_0_1__un0_n N_243 N_19_i \ +cpu_est_0_2__un3_n N_240 N_36_0 cpu_est_0_2__un1_n N_88 N_8_i \ +cpu_est_0_2__un0_n N_89 N_42_0 cpu_est_0_3__un3_n N_82 N_3_i \ +cpu_est_0_3__un1_n N_83 N_45_0 cpu_est_0_3__un0_n N_78 VPA_c_i \ +ipl_030_0_0__un3_n N_79 N_52_0 ipl_030_0_0__un1_n N_91 DTACK_c_i \ +ipl_030_0_0__un0_n N_244 N_53_0 ipl_030_0_1__un3_n N_62 ipl_030_0_1__un1_n \ +N_64 N_249_i ipl_030_0_1__un0_n N_59 N_248_i ipl_030_0_2__un3_n N_61 N_247_i \ +ipl_030_0_2__un1_n N_163 ipl_030_0_2__un0_n N_245 N_77_i uds_000_int_0_un3_n \ +N_242 N_251_i uds_000_int_0_un1_n N_246 N_76_i uds_000_int_0_un0_n N_248 \ +amiga_bus_enable_dma_high_0_un3_n N_236 N_131_i \ +amiga_bus_enable_dma_high_0_un1_n N_249 N_130_i \ +amiga_bus_enable_dma_high_0_un0_n N_92 N_264_i as_000_dma_0_un3_n N_251 \ +N_170_i as_000_dma_0_un1_n N_76 pos_clk_un6_bgack_000_0_n as_000_dma_0_un0_n \ +N_80 pos_clk_rw_000_dma_3_0_n ds_000_enable_0_un3_n pos_clk_a0_dma_3_n N_123_i \ +ds_000_enable_0_un1_n SIZE_DMA_3_sqmuxa N_124_i ds_000_enable_0_un0_n N_87 \ +AMIGA_BUS_DATA_DIR_c_0 lds_000_int_0_un3_n pos_clk_size_dma_6_1__n N_122_i \ +lds_000_int_0_un1_n pos_clk_size_dma_6_0__n pos_clk_ds_000_dma_4_0_n \ +lds_000_int_0_un0_n N_170 N_242_i as_030_000_sync_0_un3_n N_122 N_239_i \ +as_030_000_sync_0_un1_n N_123 N_87_i as_030_000_sync_0_un0_n N_130 N_236_0 \ +rw_000_int_0_un3_n pos_clk_ds_000_dma_4_n N_246_i rw_000_int_0_un1_n \ +pos_clk_rw_000_dma_3_n pos_clk_size_dma_6_0_0__n rw_000_int_0_un0_n \ +pos_clk_un6_bgack_000_n N_245_i vma_int_0_un3_n N_131 \ +pos_clk_size_dma_6_0_1__n vma_int_0_un1_n N_3 N_91_i vma_int_0_un0_n N_8 \ +N_210_i a_decode_15__n N_19 pos_clk_un19_bgack_030_int_i_n N_20 N_163_0 \ +a_decode_14__n N_22 N_59_i N_24 N_61_i a_decode_13__n pos_clk_un9_bg_030_n \ +un1_amiga_bus_enable_low_i N_62_i a_decode_12__n un21_fpu_cs_i N_64_i \ +BGACK_030_INT_i a_decode_11__n AMIGA_BUS_ENABLE_DMA_LOW_i N_244_i N_80_i \ +a_decode_10__n cycle_dma_i_0__n N_78_i_0 RW_000_i N_79_i a_decode_9__n \ +rst_dly_i_0__n rst_dly_i_1__n N_82_i a_decode_8__n rst_dly_i_2__n N_83_i \ +LDS_000_i N_55_0 a_decode_7__n UDS_000_i N_88_i sm_amiga_i_2__n N_89_i \ +a_decode_6__n N_58_i N_240_0 sm_amiga_i_3__n N_243_0 a_decode_5__n \ +cpu_est_i_1__n CLK_030_c_i cpu_est_i_0__n N_254_0 a_decode_4__n \ +sm_amiga_i_1__n N_114_i N_110_i N_115_i a_decode_3__n a_i_1__n VMA_INT_i \ +N_116_i a_decode_2__n VPA_D_i N_117_i DTACK_D0_i AS_030_D0_i N_118_i \ +sm_amiga_i_0__n sm_amiga_i_i_7__n N_119_i sm_amiga_i_6__n sm_amiga_i_5__n \ +N_120_i sm_amiga_i_4__n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE \ +SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE \ +AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE \ +DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_107 G_108 G_109 \ +pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_0_x2 +.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names N_143_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +.names N_150_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 -.names N_141_i_1.BLIF N_279_i.BLIF SM_AMIGA_1_.D +.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 -.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D 11 1 -.names N_31_0.BLIF IPL_030DFF_0_reg.D +.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +11 1 +.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +11 1 +.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +11 1 +.names N_28_0.BLIF IPL_030DFF_0_reg.D 0 1 -.names N_32_0.BLIF IPL_030DFF_1_reg.D +.names N_29_0.BLIF IPL_030DFF_1_reg.D 0 1 -.names N_33_0.BLIF IPL_030DFF_2_reg.D +.names N_30_0.BLIF IPL_030DFF_2_reg.D 0 1 -.names N_52_0.BLIF IPL_D0_0_.D +.names N_49_0.BLIF IPL_D0_0_.D 0 1 -.names N_53_0.BLIF IPL_D0_1_.D +.names N_50_0.BLIF IPL_D0_1_.D 0 1 -.names N_54_0.BLIF IPL_D0_2_.D +.names N_51_0.BLIF IPL_D0_2_.D 0 1 -.names N_155_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +.names N_154_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_151_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +.names N_260_i_1.BLIF N_260_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_166_i.BLIF N_226_i.BLIF SM_AMIGA_5_.D -11 1 -.names N_147_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_67_i_1.BLIF N_67_i_2.BLIF CYCLE_DMA_0_.D -11 1 -.names N_64_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF CYCLE_DMA_1_.D +.names N_259_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -438,7 +442,7 @@ pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 -.names N_232_i.BLIF N_233_i.BLIF cpu_est_0_.D +.names N_59_i.BLIF N_61_i.BLIF cpu_est_0_.D 11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 @@ -449,352 +453,406 @@ pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D 1- 1 -1 1 -.names N_240_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names N_234_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_239_i_1.BLIF N_239_i_2.BLIF RST_DLY_1_.D +.names N_233_i_1.BLIF N_233_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_2_.D +.names N_232_i_1.BLIF N_232_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_44_0.BLIF inst_RW_000_INT.D -0 1 -.names N_45_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_46_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_47_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names N_49_0.BLIF inst_AS_000_DMA.D -0 1 -.names N_50_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_110_0.BLIF inst_AS_030_D0.D -0 1 -.names N_55_0.BLIF inst_VPA_D.D -0 1 -.names N_56_0.BLIF inst_DTACK_D0.D -0 1 -.names N_60_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +.names N_127_i.BLIF N_128_i.BLIF inst_DSACK1_INT.D 11 1 -.names N_301_0.BLIF inst_RESET_OUT.D +.names N_125_i.BLIF N_126_i.BLIF inst_AS_000_INT.D +11 1 +.names N_48_0.BLIF inst_AS_030_D0.D +0 1 +.names N_52_0.BLIF inst_VPA_D.D +0 1 +.names N_53_0.BLIF inst_DTACK_D0.D +0 1 +.names N_258_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +11 1 +.names N_55_0.BLIF inst_RESET_OUT.D 0 1 .names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names N_34_0.BLIF BG_000DFFreg.D +.names N_31_0.BLIF BG_000DFFreg.D 0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +.names N_33_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_37_0.BLIF inst_UDS_000_INT.D +.names N_34_0.BLIF inst_UDS_000_INT.D 0 1 -.names N_38_0.BLIF inst_A0_DMA.D +.names N_35_0.BLIF inst_A0_DMA.D 0 1 -.names N_39_0.BLIF inst_AS_000_INT.D +.names N_36_0.BLIF inst_RW_000_DMA.D 0 1 -.names N_40_0.BLIF inst_DSACK1_INTreg.D +.names N_37_0.BLIF inst_VMA_INTreg.D 0 1 -.names N_41_0.BLIF inst_VMA_INTreg.D +.names N_39_0.BLIF inst_RW_000_INT.D 0 1 -.names N_43_0.BLIF inst_RW_000_DMA.D +.names N_40_0.BLIF inst_AS_030_000_SYNC.D 0 1 -.names N_100_i.BLIF inst_BGACK_030_INT_D.D +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_44_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_45_0.BLIF inst_DS_000_DMA.D +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_130.BLIF N_130_i +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names BGACK_000_c.BLIF N_349_i.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names N_131.BLIF N_131_i -0 1 -.names DTACK_c.BLIF DTACK_c_i +.names N_171.BLIF N_171_i 0 1 .names inst_CLK_030_H.BLIF CLK_030_H_i 0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_56_0 -11 1 -.names RW_000_c.BLIF RW_000_i +.names FPU_SENSE_c.BLIF FPU_SENSE_i 0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_55_0 -11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_6.BLIF N_6_i +.names N_121.BLIF N_121_i 0 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names N_6_i.BLIF RST_c.BLIF N_47_0 +.names N_255_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_255_0 11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i +.names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names N_26.BLIF N_26_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_26_i.BLIF RST_c.BLIF N_34_0 +.names N_265.BLIF N_270_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 11 1 -.names vcc_n_n - 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n +.names AS_000_c.BLIF AS_000_i 0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names gnd_n_n -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ -un1_amiga_bus_enable_low -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_25.BLIF N_25_i -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_25_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_24.BLIF N_24_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names N_24_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names N_17.BLIF N_17_i -0 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT -0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_17_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names N_4.BLIF N_4_i -0 1 -.names N_138_i.BLIF N_162.BLIF un1_DS_000_ENABLE_0_sqmuxa -11 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_4_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names N_3.BLIF N_3_i -0 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_3_i.BLIF RST_c.BLIF N_50_0 -11 1 -.names un21_fpu_cs_1.BLIF N_357.BLIF un21_fpu_cs -11 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_215.BLIF N_215_i -0 1 -.names un21_berr_1_0.BLIF N_357.BLIF un21_berr -11 1 -.names G_107.BLIF N_210_i -0 1 -.names N_216.BLIF N_216_i -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names G_108.BLIF N_211_i -0 1 -.names N_215_i.BLIF N_216_i.BLIF N_301_0 -11 1 -.names G_109.BLIF N_212_i -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_243_0 -11 1 -.names N_266.BLIF N_266_i -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_249.BLIF N_249_i -0 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names N_249_i.BLIF N_266_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +.names AS_030_i.BLIF RST_c.BLIF N_48_0 11 1 .names inst_AS_000_INT.BLIF AS_000_INT_i 0 1 -.names N_268.BLIF N_268_i +.names N_125.BLIF N_125_i 0 1 -.names un6_as_030.BLIF un6_as_030_i +.names inst_DSACK1_INT.BLIF DSACK1_INT_i 0 1 -.names N_268_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF \ -pos_clk_ds_000_dma_4_0_n -11 1 -.names CLK_030_c.BLIF CLK_030_c_i +.names N_126.BLIF N_126_i 0 1 -.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_236_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names N_297.BLIF N_297_i +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n 0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_160_i -11 1 -.names pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ -pos_clk_un21_bgack_030_int_i_0_i_2_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_n -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_100_i -11 1 -.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_186_0 -11 1 -.names N_157_i.BLIF N_304_i.BLIF N_183_0 -11 1 -.names N_304_i.BLIF nEXP_SPACE_c.BLIF N_182_0 -11 1 -.names N_157_i.BLIF N_160_i.BLIF N_181_0 -11 1 -.names N_228.BLIF N_228_i +.names vcc_n_n + 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n 0 1 -.names N_228_i.BLIF SM_AMIGA_i_7_.BLIF N_176_0 -11 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names N_127.BLIF N_127_i 0 1 -.names UDS_000_c.BLIF UDS_000_c_i +.names un5_e_0.BLIF un5_e 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_173_i -11 1 -.names N_304_i_1.BLIF CLK_000_D_2_.BLIF N_304_i -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names N_128.BLIF N_128_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names gnd_n_n +.names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 -.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_157_i -11 1 -.names AS_030_i.BLIF RST_c.BLIF N_110_0 -11 1 .names RW_c.BLIF RW_c_i 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low 11 1 -.names N_176_0.BLIF RW_c_i.BLIF N_106_0 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_270_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n 11 1 -.names N_284.BLIF N_284_i -0 1 -.names pos_clk_ipl_1_n.BLIF N_211_i.BLIF pos_clk_ipl_n +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 11 1 -.names N_334.BLIF N_334_i +.names a_decode_c_18__n.BLIF a_decode_i_18__n 0 1 -.names N_278.BLIF N_278_i +.names N_129.BLIF N_129_i 0 1 -.names N_279.BLIF N_279_i +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names N_332.BLIF N_332_i +.names a_decode_c_19__n.BLIF a_decode_i_19__n 0 1 -.names N_237_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_237_0 -11 1 -.names N_167.BLIF N_176_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 -11 1 -.names N_247.BLIF N_247_i +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names N_248.BLIF N_248_i +.names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 -.names N_246.BLIF N_246_i +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 .names un10_ciin.BLIF un10_ciin_i 0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_241_0 -11 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 -.names AS_030_D0_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_242_0 -11 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_48_i -11 1 -.names N_227.BLIF N_227_i +.names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_261_0 +11 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_65_0 +11 1 +.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_134.BLIF N_134_i +0 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names N_153.BLIF N_153_i +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_134_i.BLIF N_153_i.BLIF N_67_0 +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF un2_as_030_i +11 1 +.names G_107.BLIF N_206_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_263_i +11 1 +.names G_108.BLIF N_207_i +0 1 +.names N_263_i.BLIF SM_AMIGA_6_.BLIF N_265_i +11 1 +.names G_109.BLIF N_208_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0 +11 1 +.names CLK_000_D_2_.BLIF clk_000_d_i_2__n +0 1 +.names N_81.BLIF N_81_i +0 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_2__n.BLIF N_85_i +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_141.BLIF N_141_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_110_i.BLIF N_141_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +11 1 +.names N_147.BLIF N_147_i +0 1 +.names pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ +pos_clk_un19_bgack_030_int_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_n +11 1 +.names N_145.BLIF N_145_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_269_i +11 1 +.names un7_as_030.BLIF un7_as_030_i +0 1 +.names N_85_i.BLIF SM_AMIGA_1_.BLIF N_90_i +11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names N_117_i.BLIF SM_AMIGA_i_7_.BLIF N_270_i +11 1 +.names N_269_i.BLIF SM_AMIGA_5_.BLIF N_271_0 +11 1 +.names N_96_0_3.BLIF nEXP_SPACE_c.BLIF N_96_0 +11 1 +.names N_84_0.BLIF sm_amiga_i_i_7__n.BLIF N_97_0 +11 1 +.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_98_0 +11 1 +.names N_282.BLIF N_282_i +0 1 +.names N_284.BLIF N_284_i +0 1 +.names pos_clk_un14_clk_000_ne_n.BLIF pos_clk_un14_clk_000_ne_i_n +0 1 +.names un5_e_0_1.BLIF N_284_i.BLIF un5_e_0 +11 1 +.names N_285.BLIF N_285_i +0 1 +.names N_291.BLIF N_291_i +0 1 +.names N_292.BLIF N_292_i +0 1 +.names N_192_i_1.BLIF N_292_i.BLIF N_192_i +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names N_17.BLIF N_17_i +0 1 +.names N_17_i.BLIF N_285_i.BLIF cpu_est_2_0_2__n +11 1 +.names pos_clk_ipl_1_n.BLIF N_207_i.BLIF pos_clk_ipl_n +11 1 +.names N_286.BLIF N_286_i +0 1 +.names N_288.BLIF N_288_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +11 1 +.names N_286_i.BLIF N_288_i.BLIF cpu_est_2_0_1__n +11 1 +.names N_289.BLIF N_289_i +0 1 +.names N_290.BLIF N_290_i +0 1 +.names N_289_i.BLIF N_290_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_280_i +11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_27.BLIF N_27_i +0 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_26.BLIF N_26_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names N_25.BLIF N_25_i +0 1 +.names N_25_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_4_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names N_14.BLIF N_14_i +0 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_15.BLIF N_15_i +0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 1- 1 -1 1 -.names N_225.BLIF N_225_i +.names N_16.BLIF N_16_i 0 1 -.names N_224.BLIF N_224_i +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names N_18.BLIF N_18_i +0 1 +.names N_18_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names N_21.BLIF N_21_i 0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_223.BLIF N_223_i -0 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 1- 1 -1 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_22 +.names N_23.BLIF N_23_i +0 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names N_218.BLIF N_218_i -0 1 -.names N_218_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names N_23_i.BLIF RST_c.BLIF N_32_0 11 1 -.names N_217.BLIF N_217_i +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names N_217_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 +1- 1 +-1 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names N_213.BLIF N_213_i +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_25 +1- 1 +-1 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names N_319.BLIF N_319_i -0 1 -.names N_213_i.BLIF N_319_i.BLIF N_300_0 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_26 +1- 1 +-1 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names N_15.BLIF N_15_i -0 1 -.names N_15_i.BLIF RST_c.BLIF N_45_0 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_27 +1- 1 +-1 1 +.names inst_BGACK_030_INT_D.BLIF inst_BGACK_030_INTreg.BLIF N_96_0_1 11 1 -.names N_16.BLIF N_16_i -0 1 -.names N_16_i.BLIF RST_c.BLIF N_44_0 +.names AS_030_D0_i.BLIF sm_amiga_i_i_7__n.BLIF N_96_0_2 11 1 -.names N_22.BLIF N_22_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_38_0 +.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0_3 11 1 -.names AS_000_i.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.BLIF \ +.names pos_clk_un21_bgack_030_int_i_0_x2.BLIF N_264_i.BLIF \ pos_clk_un21_bgack_030_int_i_0_i_1_n 11 1 -.names BGACK_030_INT_i.BLIF N_297_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n +.names CLK_000_D_4_.BLIF clk_000_d_i_3__n.BLIF N_84_0_1 11 1 -.names N_199_i.BLIF N_200_i.BLIF N_238_i_1 +.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF N_84_0_2 11 1 -.names N_201_i.BLIF RST_c.BLIF N_238_i_2 +.names BERR_c.BLIF N_88_i.BLIF N_240_0_1 11 1 -.names N_203_i.BLIF N_204_i.BLIF N_239_i_1 +.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_205_i.BLIF RST_c.BLIF N_239_i_2 +.names N_263_i.BLIF N_291.BLIF N_289_1 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_289_2 +11 1 +.names N_269_i.BLIF N_280_i.BLIF N_290_1 +11 1 +.names N_291.BLIF VPA_D_i.BLIF N_290_2 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF pos_clk_un14_clk_000_ne_1_n +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF pos_clk_un14_clk_000_ne_2_n +11 1 +.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_153_1 +11 1 +.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_153_2 +11 1 +.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_153_3 +11 1 +.names N_153_1.BLIF N_153_2.BLIF N_153_4 +11 1 +.names N_153_3.BLIF fc_c_0__n.BLIF N_153_5 11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 @@ -810,11 +868,11 @@ pos_clk_un21_bgack_030_int_i_0_i_1_n 11 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 @@ -822,703 +880,642 @@ pos_clk_un21_bgack_030_int_i_0_i_1_n 11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_357_1 +.names N_130_i.BLIF N_131_i.BLIF N_260_i_1 11 1 .names pos_clk_un21_bgack_030_int_i_0_i_n.BLIF \ pos_clk_un21_bgack_030_int_i_0_n 0 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_357_2 +.names N_264_i.BLIF RST_c.BLIF N_260_i_2 11 1 -.names N_237_0.BLIF N_237 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_81 +11 1 +.names N_76_i.BLIF N_77_i.BLIF N_233_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_94 +11 1 +.names N_251_i.BLIF RST_c.BLIF N_233_i_2 +11 1 +.names N_254_0.BLIF N_254 0 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_357_3 +.names N_247_i.BLIF N_248_i.BLIF N_232_i_1 11 1 -.names N_241_0.BLIF N_241 +.names N_255_0.BLIF N_255 0 1 -.names N_357_1.BLIF N_357_2.BLIF N_357_4 +.names N_249_i.BLIF RST_c.BLIF N_232_i_2 11 1 -.names N_242_0.BLIF N_242 +.names N_261_0.BLIF N_261 0 1 -.names clk_000_d_i_1__n.BLIF AS_030_000_SYNC_i.BLIF N_304_i_1 +.names N_210_i.BLIF N_239.BLIF N_247_1 11 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 -11 1 -.names N_294.BLIF nEXP_SPACE_i.BLIF N_283 -11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 -11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_294 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_266_1 -11 1 -.names N_300_0.BLIF N_300 +.names N_65_0.BLIF N_65 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_266_2 +.names N_210_i.BLIF rst_dly_i_0__n.BLIF N_77_1 11 1 -.names AS_000_i.BLIF N_100_i.BLIF N_67_i_1 -11 1 -.names N_106_0.BLIF N_106 +.names N_67_0.BLIF N_67 0 1 -.names N_207_i.BLIF N_208_i.BLIF N_67_i_2 +.names N_91.BLIF N_269_i.BLIF N_83_1 11 1 -.names N_138_i.BLIF N_305_i.BLIF N_314_1 -11 1 -.names N_134_i.BLIF N_134 +.names N_269_i.BLIF N_269 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_314_2 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_88_1 11 1 -.names N_138_i.BLIF N_138 -0 1 -.names N_134_i.BLIF N_348.BLIF N_318_1 -11 1 -.names N_156_i.BLIF N_156 -0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_318_2 -11 1 -.names N_160_i.BLIF N_160 -0 1 -.names N_154_0.BLIF N_305_i.BLIF N_341_1 -11 1 -.names N_167_i.BLIF N_167 -0 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_341_2 -11 1 -.names N_172_i.BLIF N_172 -0 1 -.names N_167.BLIF N_284_i.BLIF N_151_i_1 -11 1 -.names N_173_i.BLIF N_173 -0 1 -.names N_138.BLIF N_334_i.BLIF N_143_i_1 -11 1 -.names N_181_0.BLIF N_181 -0 1 -.names N_166_i.BLIF N_278_i.BLIF N_141_i_1 -11 1 -.names N_182_0.BLIF N_182 -0 1 -.names N_332_i.BLIF RW_000_i.BLIF N_237_0_1 -11 1 -.names N_183_0.BLIF N_183 -0 1 -.names N_247_i.BLIF N_248_i.BLIF N_240_i_1 -11 1 -.names un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n.BLIF N_191 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_108 1- 1 -1 1 -.names N_246_i.BLIF RST_c.BLIF N_60_i_1 +.names N_62_i.BLIF N_64_i.BLIF N_142_i_1 11 1 -.names N_199_1.BLIF rst_dly_i_2__n.BLIF N_199 +.names N_278.BLIF nEXP_SPACE_i.BLIF N_135 11 1 -.names AS_000_i.BLIF N_100_i.BLIF N_64_i_1 +.names N_58_i.BLIF N_244_i.BLIF N_146_i_1 11 1 -.names N_205_1.BLIF rst_dly_i_1__n.BLIF N_205 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF N_136 11 1 -.names N_227_i.BLIF N_228_i.BLIF N_155_i_1 +.names N_78_i_0.BLIF N_79_i.BLIF N_234_i_1 11 1 -.names N_160_i.BLIF RST_c.BLIF N_209 -11 1 -.names N_138.BLIF N_225_i.BLIF N_147_i_1 -11 1 -.names AS_030_D0_i.BLIF N_181.BLIF N_319 -11 1 -.names N_172.BLIF N_224_i.BLIF N_145_i_1 -11 1 -.names AS_030_D0_i.BLIF N_357.BLIF N_213 -11 1 -.names N_138.BLIF N_223_i.BLIF N_139_i_1 -11 1 -.names N_216_1.BLIF RST_c.BLIF N_216 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_145 11 1 .names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 -.names BGACK_030_INT_i.BLIF N_173.BLIF N_217 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_278 11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_220_1 +.names N_264_i.BLIF RW_000_c.BLIF N_124_1 11 1 -.names BGACK_030_INT_i.BLIF N_173_i.BLIF N_218 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_147 11 1 -.names N_134_i.BLIF N_343.BLIF N_216_1 +.names N_153.BLIF BGACK_000_c.BLIF un21_berr_1 11 1 -.names N_220_1.BLIF cpu_est_i_3__n.BLIF N_220 +.names N_240.BLIF N_269_i.BLIF N_58 11 1 -.names N_214_0.BLIF rst_dly_i_0__n.BLIF N_205_1 +.names N_153.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 11 1 -.names N_169.BLIF sm_amiga_i_0__n.BLIF N_223 +.names N_263_i.BLIF SM_AMIGA_4_.BLIF N_110 11 1 -.names N_156.BLIF N_214_0.BLIF N_199_1 +.names N_114_i.BLIF N_115_i.BLIF N_140_i_1 11 1 -.names N_180.BLIF sm_amiga_i_3__n.BLIF N_224 -11 1 -.names N_212_i.BLIF N_210_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_185.BLIF sm_amiga_i_4__n.BLIF N_225 -11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +.names N_239_i.BLIF N_239 0 1 -.names N_182.BLIF sm_amiga_i_i_7__n.BLIF N_227 +.names N_116_i.BLIF N_117_i.BLIF N_154_i_1 11 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names N_138_i.BLIF SM_AMIGA_0_.BLIF N_228 -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CLK_030_H_i.BLIF N_186.BLIF N_246 -11 1 -.names N_80.BLIF as_000_int_0_un3_n +.names N_90_i.BLIF N_90 0 1 -.names N_142.BLIF RST_DLY_0_.BLIF N_247 +.names N_118_i.BLIF N_265.BLIF N_152_i_1 11 1 -.names N_167.BLIF N_80.BLIF as_000_int_0_un1_n -11 1 -.names N_166_i.BLIF rst_dly_i_0__n.BLIF N_248 -11 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_332 -11 1 -.names N_256.BLIF dsack1_int_0_un3_n +.names N_265_i.BLIF N_265 0 1 -.names N_138.BLIF SM_AMIGA_2_.BLIF N_278 +.names N_119_i.BLIF N_269.BLIF N_150_i_1 11 1 -.names N_169.BLIF N_256.BLIF dsack1_int_0_un1_n +.names N_120_i.BLIF N_263.BLIF N_148_i_1 11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_279 +.names N_171_i.BLIF N_263.BLIF N_144_i_1 11 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names N_179.BLIF sm_amiga_i_2__n.BLIF N_334 -11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +.names pos_clk_un19_bgack_030_int_i_n.BLIF pos_clk_un19_bgack_030_int_n 0 1 -.names N_183.BLIF sm_amiga_i_6__n.BLIF N_284 +.names N_121_i.BLIF RW_000_i.BLIF N_255_0_1 11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names N_156_i.BLIF RST_DLY_2_.BLIF N_343 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +.names N_280_i.BLIF N_280 0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_129_i.BLIF RST_c.BLIF N_258_i_1 11 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names N_357_4.BLIF N_357_3.BLIF N_357 -11 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names N_266_1.BLIF N_266_2.BLIF N_266 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names N_263_i.BLIF N_263 0 1 -.names N_186_0.BLIF N_186 -0 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_264_i.BLIF N_259_i_1 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_247_1.BLIF rst_dly_i_2__n.BLIF N_247 11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_297 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_282_1 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names N_236_0.BLIF N_236 -0 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +.names N_77_1.BLIF rst_dly_i_1__n.BLIF N_77 11 1 -.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n -0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names N_292.BLIF cpu_est_3_.BLIF N_284_1 11 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_268 +.names N_289_1.BLIF N_289_2.BLIF N_289 11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names N_134.BLIF cpu_est_0_3__un3_n -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_249 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_288_1 11 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_291 11 1 -.names cpu_est_3_.BLIF N_134.BLIF cpu_est_0_3__un1_n +.names pos_clk_un14_clk_000_ne_i_n.BLIF N_282_i.BLIF un5_e_0_1 11 1 -.names N_243_0.BLIF N_243 -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_196_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names N_290_1.BLIF N_290_2.BLIF N_290 11 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_215 +.names N_285_i.BLIF N_291_i.BLIF N_192_i_1 11 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_286 11 1 -.names N_134.BLIF cpu_est_0_2__un3_n -0 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_130 +.names N_208_i.BLIF N_206_i.BLIF pos_clk_ipl_1_n 11 1 -.names N_23.BLIF N_23_i -0 1 -.names cpu_est_2_.BLIF N_134.BLIF cpu_est_0_2__un1_n +.names N_288_1.BLIF cpu_est_i_3__n.BLIF N_288 11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_131 -11 1 -.names N_23_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_21.BLIF N_21_i -0 1 -.names N_134.BLIF cpu_est_0_1__un3_n -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_21_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names cpu_est_1_.BLIF N_134.BLIF cpu_est_0_1__un1_n -11 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names N_20.BLIF N_20_i -0 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 -1- 1 --1 1 -.names N_20_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 -1- 1 --1 1 -.names N_19.BLIF N_19_i -0 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names N_19_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_14.BLIF N_14_i -0 1 -.names N_160.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names N_14_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_130_i.BLIF N_160.BLIF amiga_bus_enable_dma_low_0_un1_n -11 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names CYCLE_DMA_0_.BLIF N_138_i.BLIF N_208 -11 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 -11 1 -.names N_160.BLIF rw_000_dma_0_un3_n -0 1 -.names cycle_dma_i_0__n.BLIF N_138.BLIF N_207 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names N_243.BLIF N_160.BLIF rw_000_dma_0_un1_n -11 1 -.names AS_000_c.BLIF N_138_i.BLIF N_349 -11 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_314_1.BLIF N_314_2.BLIF N_314 -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names N_236.BLIF as_000_dma_0_un3_n -0 1 -.names N_318_1.BLIF N_318_2.BLIF N_318 -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 -11 1 -.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_236.BLIF as_000_dma_0_un1_n -11 1 -.names N_153_i.BLIF cpu_est_i_2__n.BLIF N_348 -11 1 -.names N_27.BLIF N_27_i -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names N_134.BLIF rst_dly_i_2__n.BLIF N_201 -11 1 -.names N_27_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names N_237.BLIF ds_000_dma_0_un3_n -0 1 -.names N_142.BLIF N_343.BLIF N_200 -11 1 -.names N_28.BLIF N_28_i -0 1 -.names pos_clk_ds_000_dma_4_n.BLIF N_237.BLIF ds_000_dma_0_un1_n -11 1 -.names N_142.BLIF N_156_i.BLIF N_203 -11 1 -.names N_28_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names N_166_i.BLIF rst_dly_i_1__n.BLIF N_204 -11 1 -.names N_29.BLIF N_29_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_185_0.BLIF N_185 -0 1 -.names N_29_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names N_184_0.BLIF N_184 -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names N_180_0.BLIF N_180 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 .names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names N_179_0.BLIF N_179 -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n +.names N_280.BLIF cpu_est_2_.BLIF N_285 11 1 .names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names N_178_0.BLIF N_178 -0 1 -.names AS_030_D0_i.BLIF N_169.BLIF N_256_0 +.names N_280_i.BLIF cpu_est_i_2__n.BLIF N_17 11 1 .names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names N_171_i.BLIF N_171 -0 1 -.names N_318.BLIF N_318_i -0 1 -.names N_160.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names N_341_1.BLIF N_341_2.BLIF N_341 +.names cpu_est_0_.BLIF cpu_est_i_2__n.BLIF N_292 11 1 -.names N_314.BLIF N_314_i +.names N_94.BLIF amiga_bus_enable_dma_low_0_un3_n 0 1 -.names N_131_i.BLIF N_160.BLIF amiga_bus_enable_dma_high_0_un1_n +.names pos_clk_un14_clk_000_ne_1_n.BLIF pos_clk_un14_clk_000_ne_2_n.BLIF \ +pos_clk_un14_clk_000_ne_n 11 1 -.names N_165.BLIF inst_VPA_D.BLIF N_342 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_94.BLIF \ +amiga_bus_enable_dma_low_0_un1_n 11 1 -.names N_314_i.BLIF N_318_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names N_282_1.BLIF cpu_est_i_3__n.BLIF N_282 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +.names N_80_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n 11 1 -.names N_169_i.BLIF N_169 -0 1 -.names N_219.BLIF N_219_i -0 1 -.names inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n -0 1 -.names N_154_0.BLIF N_154 -0 1 -.names N_220.BLIF N_220_i -0 1 -.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n +.names N_284_1.BLIF cpu_est_i_1__n.BLIF N_284 11 1 -.names N_165_0.BLIF N_165 +.names N_94.BLIF a0_dma_0_un3_n 0 1 -.names N_219_i.BLIF N_220_i.BLIF cpu_est_2_0_1__n +.names N_98_0.BLIF N_98 +0 1 +.names inst_A0_DMA.BLIF N_94.BLIF a0_dma_0_un1_n 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n +.names N_97_0.BLIF N_97 +0 1 +.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names N_162_0.BLIF N_162 +.names N_84_0.BLIF N_84 0 1 -.names N_221.BLIF N_221_i +.names N_94.BLIF rw_000_dma_0_un3_n 0 1 -.names N_209.BLIF size_dma_0_0__un3_n +.names N_96_0.BLIF N_96 0 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF N_299 +.names inst_RW_000_DMA.BLIF N_94.BLIF rw_000_dma_0_un1_n 11 1 -.names N_348.BLIF N_348_i +.names N_271_0.BLIF N_271 0 1 -.names SIZE_DMA_0_.BLIF N_209.BLIF size_dma_0_0__un1_n +.names pos_clk_rw_000_dma_3_n.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n 11 1 -.names N_153_i.BLIF N_153 +.names N_263_i.BLIF SM_AMIGA_0_.BLIF N_117 +11 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_221_i.BLIF N_348_i.BLIF cpu_est_2_0_2__n +.names N_265_i.BLIF RW_c.BLIF N_141 +11 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names AS_030_i.BLIF N_96.BLIF N_134 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names N_153_4.BLIF N_153_5.BLIF N_153 +11 1 +.names N_255.BLIF ds_000_dma_0_un3_n +0 1 +.names CLK_030_H_i.BLIF N_98.BLIF N_129 +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_255.BLIF ds_000_dma_0_un1_n +11 1 +.names N_147.BLIF RST_c.BLIF N_127 +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names N_90_i.BLIF RST_c.BLIF N_128 +11 1 +.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un3_n +0 1 +.names N_145.BLIF RST_c.BLIF N_125 +11 1 +.names SIZE_DMA_1_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un1_n +11 1 +.names N_265_i.BLIF RST_c.BLIF N_126 +11 1 +.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ +size_dma_0_1__un0_n +11 1 +.names N_124_1.BLIF nEXP_SPACE_i.BLIF N_124 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un3_n +0 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_121 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names SIZE_DMA_0_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un1_n +11 1 +.names N_163.BLIF sm_amiga_i_2__n.BLIF N_171 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 .names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \ size_dma_0_0__un0_n 11 1 -.names N_142_0.BLIF N_142 +.names N_271.BLIF sm_amiga_i_4__n.BLIF N_120 +11 1 +.names N_24.BLIF N_24_i 0 1 -.names N_222.BLIF N_222_i +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names N_209.BLIF size_dma_0_1__un3_n +.names N_265.BLIF sm_amiga_i_5__n.BLIF N_119 +11 1 +.names N_24_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names N_97.BLIF sm_amiga_i_6__n.BLIF N_118 +11 1 +.names N_22.BLIF N_22_i 0 1 -.names N_134_i.BLIF N_214_0.BLIF N_298 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n 11 1 -.names N_221_i.BLIF N_222_i.BLIF N_196_i +.names N_84.BLIF sm_amiga_i_i_7__n.BLIF N_116 11 1 -.names SIZE_DMA_1_.BLIF N_209.BLIF size_dma_0_1__un1_n +.names N_22_i.BLIF RST_c.BLIF N_33_0 11 1 -.names N_80_0.BLIF N_80 +.names N_269.BLIF cpu_est_0_1__un3_n 0 1 -.names N_226.BLIF N_226_i +.names N_90.BLIF sm_amiga_i_0__n.BLIF N_114 +11 1 +.names N_20.BLIF N_20_i 0 1 -.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ -size_dma_0_1__un0_n +.names cpu_est_1_.BLIF N_269.BLIF cpu_est_0_1__un1_n 11 1 -.names N_134.BLIF cpu_est_i_0__n.BLIF N_232 +.names N_263_i.BLIF sm_amiga_i_1__n.BLIF N_115 11 1 -.names N_242.BLIF ds_000_enable_0_un3_n +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_243_0.BLIF N_243 0 1 -.names N_134_i.BLIF cpu_est_0_.BLIF N_233 -11 1 -.names N_231.BLIF N_231_i +.names N_19.BLIF N_19_i 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_242.BLIF ds_000_enable_0_un1_n +.names N_269.BLIF cpu_est_0_2__un3_n +0 1 +.names N_240_0.BLIF N_240 +0 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 11 1 -.names N_184.BLIF cpu_est_i_2__n.BLIF N_229 +.names cpu_est_2_.BLIF N_269.BLIF cpu_est_0_2__un1_n 11 1 -.names N_229.BLIF N_229_i +.names N_88_1.BLIF pos_clk_un14_clk_000_ne_n.BLIF N_88 +11 1 +.names N_8.BLIF N_8_i +0 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_89 +11 1 +.names N_8_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names N_269.BLIF cpu_est_0_3__un3_n +0 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_82 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names cpu_est_3_.BLIF N_269.BLIF cpu_est_0_3__un1_n +11 1 +.names N_83_1.BLIF RST_c.BLIF N_83 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_192_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_236.BLIF RST_DLY_0_.BLIF N_78 +11 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_92.BLIF rst_dly_i_0__n.BLIF N_79 +11 1 +.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names N_239_i.BLIF RST_DLY_2_.BLIF N_91 +11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_110_i.BLIF sm_amiga_i_3__n.BLIF N_244 +11 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_243.BLIF sm_amiga_i_1__n.BLIF N_62 +11 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_85_i.BLIF sm_amiga_i_2__n.BLIF N_64 +11 1 +.names N_249.BLIF N_249_i +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_269.BLIF cpu_est_i_0__n.BLIF N_59 +11 1 +.names N_248.BLIF N_248_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names N_269_i.BLIF cpu_est_0_.BLIF N_61 +11 1 +.names N_247.BLIF N_247_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names N_163_0.BLIF N_163 +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names BGACK_030_INT_i.BLIF N_242_i.BLIF N_245 +11 1 +.names N_77.BLIF N_77_i +0 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +0 1 +.names N_242_i.BLIF N_242 +0 1 +.names N_251.BLIF N_251_i +0 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names BGACK_030_INT_i.BLIF N_242.BLIF N_246 +11 1 +.names N_76.BLIF N_76_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_91.BLIF N_236.BLIF N_248 +11 1 +.names N_94.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names N_236_0.BLIF N_236 +0 1 +.names N_131.BLIF N_131_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_94.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names N_269.BLIF rst_dly_i_2__n.BLIF N_249 +11 1 +.names N_130.BLIF N_130_i +0 1 +.names N_81_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n +11 1 +.names N_269.BLIF RST_c.BLIF N_92 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_264_i +11 1 +.names N_254.BLIF as_000_dma_0_un3_n +0 1 +.names N_236.BLIF N_239_i.BLIF N_251 +11 1 +.names N_170.BLIF N_170_i +0 1 +.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_254.BLIF as_000_dma_0_un1_n +11 1 +.names N_92.BLIF rst_dly_i_1__n.BLIF N_76 +11 1 +.names BGACK_000_c.BLIF N_170_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_80 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n +11 1 +.names N_65.BLIF ds_000_enable_0_un3_n +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names N_123.BLIF N_123_i +0 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_65.BLIF ds_000_enable_0_un1_n +11 1 +.names N_94.BLIF RST_c.BLIF SIZE_DMA_3_sqmuxa +11 1 +.names N_124.BLIF N_124_i 0 1 .names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ ds_000_enable_0_un0_n 11 1 -.names N_178.BLIF cpu_est_2_.BLIF N_231 +.names N_210_i.BLIF N_269_i.BLIF N_87 11 1 -.names N_229_i.BLIF N_231_i.BLIF N_302_i +.names N_123_i.BLIF N_124_i.BLIF AMIGA_BUS_DATA_DIR_c_0 11 1 -.names N_300.BLIF as_030_000_sync_0_un3_n +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names N_167.BLIF sm_amiga_i_5__n.BLIF N_226 -11 1 -.names N_233.BLIF N_233_i +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n 0 1 -.names inst_AS_030_000_SYNC.BLIF N_300.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_153.BLIF cpu_est_2_.BLIF N_221 -11 1 -.names N_232.BLIF N_232_i +.names N_122.BLIF N_122_i 0 1 -.names inst_AS_030_D0.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names N_154.BLIF cpu_est_i_2__n.BLIF N_222 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names N_122_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names AS_000_c.BLIF N_263_i.BLIF N_170 +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_242_i +11 1 +.names N_67.BLIF as_030_000_sync_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_122 +11 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_239_i +11 1 +.names inst_AS_030_000_SYNC.BLIF N_67.BLIF as_030_000_sync_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_123 +11 1 +.names N_87.BLIF N_87_i +0 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names cycle_dma_i_0__n.BLIF N_263.BLIF N_130 +11 1 +.names N_87_i.BLIF RST_c.BLIF N_236_0 11 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n 0 1 -.names AS_030_D0_i.BLIF N_167.BLIF N_80_0 +.names N_246.BLIF N_246_i +0 1 +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +rw_000_int_0_un1_n 11 1 -.names N_106.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n +0 1 +.names N_246_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names N_343.BLIF N_343_i -0 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_219 -11 1 -.names N_343_i.BLIF RST_c.BLIF N_214_0 -11 1 -.names N_160.BLIF a0_dma_0_un3_n +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +.names N_245.BLIF N_245_i 0 1 -.names N_134.BLIF RST_c.BLIF N_166_i -11 1 -.names pos_clk_a0_dma_3_n.BLIF N_160.BLIF a0_dma_0_un1_n -11 1 -.names N_256_0.BLIF N_256 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_134_i +.names CYCLE_DMA_0_.BLIF N_263_i.BLIF N_131 11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +.names N_245_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_298.BLIF N_298_i +.names N_91.BLIF N_91_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 -1- 1 --1 1 -.names N_298_i.BLIF RST_c.BLIF N_142_0 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 1- 1 -1 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_153_i +.names N_91_i.BLIF RST_c.BLIF N_210_i 11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_154_0 +.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un19_bgack_030_int_i_n 11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_19 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 1- 1 -1 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_156_i +.names N_58.BLIF SM_AMIGA_3_.BLIF N_163_0 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_20 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_22 1- 1 -1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_305_i -11 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_299.BLIF N_299_i +.names N_59.BLIF N_59_i 0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_23 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_24 1- 1 -1 1 -.names N_299_i.BLIF sm_amiga_i_4__n.BLIF N_162_0 -11 1 +.names N_61.BLIF N_61_i +0 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names BERR_c.BLIF inst_DTACK_D0.BLIF N_165_0 -11 1 +.names N_62.BLIF N_62_i +0 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names N_134_i.BLIF SM_AMIGA_1_.BLIF N_169_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_341.BLIF N_341_i -0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names N_342.BLIF N_342_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_341_i.BLIF N_342_i.BLIF N_171_i -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_134_i.BLIF N_171.BLIF N_172_i -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_178_0 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_172_i.BLIF SM_AMIGA_3_.BLIF N_179_0 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names N_138_i.BLIF SM_AMIGA_4_.BLIF N_180_0 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_184_0 -11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_134_i.BLIF SM_AMIGA_5_.BLIF N_185_0 -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_203.BLIF N_203_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_204.BLIF N_204_i -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_205.BLIF N_205_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_200.BLIF N_200_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_199.BLIF N_199_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_201.BLIF N_201_i +.names N_64.BLIF N_64_i 0 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names AS_000_c.BLIF AS_000_i +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i 0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i +.names N_244.BLIF N_244_i 0 1 -.names N_208.BLIF N_208_i -0 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_207.BLIF N_207_i +.names N_80.BLIF N_80_i 0 1 .names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 -.names N_138_i.BLIF SM_AMIGA_6_.BLIF N_167_i +.names N_78.BLIF N_78_i_0 +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_79.BLIF N_79_i +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names N_82.BLIF N_82_i +0 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_83.BLIF N_83_i +0 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names N_82_i.BLIF N_83_i.BLIF N_55_0 11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names UDS_000_c.BLIF UDS_000_i 0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_138_i +.names N_88.BLIF N_88_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_89.BLIF N_89_i +0 1 +.names N_58.BLIF N_58_i +0 1 +.names N_240_0_1.BLIF N_89_i.BLIF N_240_0 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names N_349.BLIF N_349_i +.names N_263_i.BLIF SM_AMIGA_2_.BLIF N_243_0 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_254_0 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_114.BLIF N_114_i +0 1 +.names N_110.BLIF N_110_i +0 1 +.names N_115.BLIF N_115_i +0 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_116.BLIF N_116_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_117.BLIF N_117_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_118.BLIF N_118_i +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_119.BLIF N_119_i +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_120.BLIF N_120_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0 -01 1 -10 1 -11 0 -00 0 .names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_107 01 1 10 1 @@ -1534,13 +1531,12 @@ as_030_000_sync_0_un0_n 10 1 11 0 00 0 -.names CYCLE_DMA_1_.BLIF N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2 +.names CYCLE_DMA_1_.BLIF N_131.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un21_bgack_030_int_i_0_o2_2_x2 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un21_bgack_030_int_i_0_x2 01 1 10 1 11 0 @@ -1566,13 +1562,13 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names inst_DSACK1_INTreg.BLIF DSACK1 +.names N_147_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_302_i.BLIF E +.names un5_e.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1590,7 +1586,7 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_191.BLIF AMIGA_BUS_ENABLE_HIGH +.names N_108.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 .names un10_ciin.BLIF CIIN @@ -1602,6 +1598,15 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 0 0 @@ -1635,13 +1640,10 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C 1 1 0 0 .names CLK_000_D_1_.BLIF CLK_000_D_2_.D @@ -1650,6 +1652,18 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names CLK_OSZI_c.BLIF CLK_000_D_2_.C 1 1 0 0 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +0 0 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -1689,28 +1703,10 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 0 0 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_AS_030_D0.C @@ -1731,12 +1727,6 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C -1 1 -0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -1752,46 +1742,58 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -0 0 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names un3_size.BLIF SIZE_1_ +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 0 0 .names gnd_n_n.BLIF AHIGH_31_ 1 1 0 0 -.names un6_as_030_i.BLIF AS_030 +.names un7_as_030_i.BLIF AS_030 1 1 0 0 -.names un4_as_000_i.BLIF AS_000 +.names N_145_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1809,7 +1811,7 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names inst_RW_000_DMA.BLIF RW 1 1 0 0 -.names un4_size.BLIF SIZE_0_ +.names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 .names gnd_n_n.BLIF AHIGH_30_ @@ -2001,61 +2003,61 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 -.names N_283.BLIF AS_030.OE +.names N_135.BLIF AS_030.OE 1 1 0 0 -.names un1_as_000_i.BLIF AS_000.OE +.names N_136.BLIF AS_000.OE 1 1 0 0 -.names un1_as_000_i.BLIF RW_000.OE +.names N_136.BLIF RW_000.OE 1 1 0 0 -.names un1_as_000_i.BLIF UDS_000.OE +.names N_136.BLIF UDS_000.OE 1 1 0 0 -.names un1_as_000_i.BLIF LDS_000.OE +.names N_136.BLIF LDS_000.OE 1 1 0 0 -.names N_48_i.BLIF SIZE_0_.OE +.names un2_as_030_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_48_i.BLIF SIZE_1_.OE +.names un2_as_030_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_24_.OE +.names N_135.BLIF AHIGH_24_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_25_.OE +.names N_135.BLIF AHIGH_25_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_26_.OE +.names N_135.BLIF AHIGH_26_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_27_.OE +.names N_135.BLIF AHIGH_27_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_28_.OE +.names N_135.BLIF AHIGH_28_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_29_.OE +.names N_135.BLIF AHIGH_29_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_30_.OE +.names N_135.BLIF AHIGH_30_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_31_.OE +.names N_135.BLIF AHIGH_31_.OE 1 1 0 0 -.names N_283.BLIF A_0_.OE +.names N_135.BLIF A_0_.OE 1 1 0 0 .names un21_berr.BLIF BERR.OE 1 1 0 0 -.names N_294.BLIF RW.OE +.names N_278.BLIF RW.OE 1 1 0 0 -.names N_283.BLIF DS_030.OE +.names N_135.BLIF DS_030.OE 1 1 0 0 .names nEXP_SPACE_c.BLIF DSACK1.OE @@ -2064,7 +2066,7 @@ pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_241.BLIF CIIN.OE +.names N_261.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index e28fcf4..7bbbb3b 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,79 +1,80 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE 68030_tk #$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ -# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \ -# SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ CLK_EXP AHIGH_28_ FPU_CS AHIGH_27_ \ -# FPU_SENSE AHIGH_26_ DSACK1 AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ \ -# VPA A_DECODE_20_ VMA A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ RW A_DECODE_16_ \ +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 SIZE_0_ \ +# CLK_000 AHIGH_30_ CLK_OSZI AHIGH_29_ CLK_DIV_OUT AHIGH_28_ CLK_EXP AHIGH_27_ FPU_CS \ +# AHIGH_26_ FPU_SENSE AHIGH_25_ DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E \ +# A_DECODE_20_ VPA A_DECODE_19_ VMA A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ RW \ # AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ # CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ -#$ NODES 54 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ cpu_est_0_ \ -# cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \ -# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \ -# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ \ -# inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 \ -# inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg inst_LDS_000_INT \ -# inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ \ -# inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_A0_DMA \ -# inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg \ -# CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg +#$ NODES 55 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_3_ cpu_est_0_ cpu_est_1_ \ +# cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC \ +# inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ \ +# inst_VPA_D CLK_000_D_2_ CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ \ +# CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \ +# CLK_000_D_4_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ inst_UDS_000_INT \ +# inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ SIZE_DMA_0_ \ +# SIZE_DMA_1_ inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ \ +# inst_A0_DMA inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ \ +# SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \ +# IPL_030DFF_1_reg IPL_030DFF_2_reg .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ -inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \ -SIZE_DMA_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF inst_DTACK_D0.BLIF \ -inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF \ -inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \ -IPL_D0_2_.BLIF CLK_000_D_2_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -inst_DSACK1_INTreg.BLIF inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \ -inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF \ +inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_VPA_D.BLIF \ +CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF \ +inst_CLK_OUT_PRE_D.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +CLK_000_D_4_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF SM_AMIGA_1_.BLIF \ +inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF inst_LDS_000_INT.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_0_.BLIF SIZE_DMA_0_.BLIF \ +SIZE_DMA_1_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF \ RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \ -BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \ -IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ -AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +inst_DSACK1_INT.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF \ +SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF \ +IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF \ +AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ +AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ +AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ +BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.C SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ -IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ -IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \ -IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ -SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \ -CLK_000_D_2_.D CLK_000_D_2_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ -CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ -cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.C cpu_est_3_.D \ -cpu_est_3_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ -inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 \ -UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ +SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \ +IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ +IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.C \ +CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ +CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.C \ +cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.D \ +RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C \ +inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ +RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE \ AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE \ @@ -81,46 +82,81 @@ BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE cpu_est_2_.D.X1 \ cpu_est_2_.D.X2 RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 inst_CLK_030_H.D.X1 \ inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 \ SM_AMIGA_i_7_.D.X2 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ -inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_i_7_.BLIF SM_AMIGA_6_.D +1100--100 1 +-1---0-1- 1 +-1--1--1- 1 +----01-1- 0 +------00- 0 +---1---0- 0 +--1----0- 0 +0------0- 0 +-0------- 0 +-------01 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +1011- 1 +1-1-1 1 +10--1 1 +-10-- 0 +0---- 0 +---00 0 +--0-0 0 +-1--0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_4_.D +1-01- 1 +11-1- 1 +110-1 1 +-01-- 0 +--10- 0 +-0-0- 0 +0---- 0 +---00 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ BERR.PIN.BLIF SM_AMIGA_2_.D -10010001-01-- 1 -1-----11001-- 1 -1-----11-01-0 1 +1010000-101-- 1 +1-----10101-- 1 +1-------101-0 1 1--------0-1- 1 -1------1---1- 1 -------1-1--01 0 ------10----0- 0 -----1-0----0- 0 ----0--0----0- 0 ---1---0----0- 0 --1----0----0- 0 --------0-1--- 0 +1-------1--1- 1 +------11---01 0 +--------01--- 0 +-----10----01 0 +----1-0----01 0 +---1--0----01 0 +--0---0----01 0 +-1----0----01 0 ----------00- 0 ---------1-0- 0 --------0---0- 0 +--------0--0- 0 0------------ 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_2_.BLIF SM_AMIGA_1_.D -101-1 1 -1-110 1 -10-10 1 --10-- 0 ----00 0 -0---- 0 ---0-1 0 --1--1 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_0_.BLIF SM_AMIGA_0_.D -1101- 1 -1-0-1 1 -11--1 1 --01-- 0 -0---- 0 ----00 0 ---1-0 0 --0--0 0 +.names RST.BLIF CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D +1--01-1 1 +1-0--1- 1 +11---1- 1 +1----11 1 +-01---0 0 +----00- 0 +---1-0- 0 +0------ 0 +-----00 0 +.names RST.BLIF CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +101--1- 1 +1---0-1 1 +1--1--1 1 +1----11 1 +---010- 0 +0------ 0 +--0---0 0 +-1----0 0 +-----00 0 .names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D 0-01100- 1 @@ -202,39 +238,6 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D 1- 1 -0 1 01 0 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF CLK_000_D_2_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF \ -SM_AMIGA_6_.D -1100-100 1 --1--0-1- 1 --1-1--1- 1 ----01-1- 0 ------00- 0 ----1--0- 0 ---1---0- 0 -0-----0- 0 --0------ 0 -------01 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -1011- 1 -1-1-1 1 -10--1 1 --10-- 0 -0---- 0 ----00 0 ---0-0 0 --1--0 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_4_.D -1-01- 1 -11-1- 1 -110-1 1 --01-- 0 ---10- 0 --0-0- 0 -0---- 0 ----00 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D 100010 1 @@ -295,18 +298,18 @@ CLK_000_D_0_.BLIF cpu_est_1_.D --00- 0 -00-- 0 --0-1 0 -.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ +.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D -1-1110 1 -010--- 1 --1--0- 1 --1---1 1 ---1010 0 --00--- 0 -1-0-10 0 -0-1-10 0 --0--0- 0 --0---1 0 +-11110 1 +10-0-- 1 +1---0- 1 +1----1 1 +0--0-- 0 +-10-10 0 +-1-010 0 +-0-110 0 +0---0- 0 +0----1 0 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D 1--111 1 @@ -327,12 +330,139 @@ RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D ---0-0 0 --1--0 0 -0---0 0 +.names RST.BLIF CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF SM_AMIGA_1_.BLIF \ +inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D +---01- 1 +--0-1- 1 +-1--1- 1 +0----- 1 +---0-1 1 +--0--1 1 +-1---1 1 +1011-- 0 +1---00 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D +---01- 1 +--0-1- 1 +-1--1- 1 +0----- 1 +---0-1 1 +--0--1 1 +-1---1 1 +1011-- 0 +1---00 0 +.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D +0- 1 +-1 1 +10 0 +.names VPA.BLIF RST.BLIF inst_VPA_D.D +1- 1 +-0 1 +01 0 +.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D +1- 1 +-0 1 +01 0 +.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ +RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D +1-10111 1 +11----- 1 +0------ 0 +-0---0- 0 +-0--0-- 0 +-0-1--- 0 +-00---- 0 +-0----0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_DS_000_ENABLE.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF RW.PIN.BLIF \ +inst_DS_000_ENABLE.D +101--1-- 1 +101-1--1 1 +1--1--0- 1 +----001- 0 +---000-- 0 +-----010 0 +--0---1- 0 +-1----1- 0 +---0-0-0 0 +--00---- 0 +-1-0---- 0 +0------- 0 +.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ +CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D +--0--- 1 +-1---- 1 +----01 1 +---0-1 1 +0----1 1 +10111- 0 +-01--0 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +--10- 1 +-10-- 1 +0---- 1 +--1-1 1 +1-110 0 +100-- 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D +--11- 1 +-00-- 1 +--1-0 1 +0---- 1 +1-101 0 +110-- 0 +.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ +inst_UDS_000_INT.D +-10- 1 +0--- 1 +--11 1 +100- 0 +1-10 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +-111- 1 +0---- 1 +-0--1 1 +11-0- 0 +110-- 0 +10--0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1-1- 1 +-10-- 1 +0---- 1 +-0--1 1 +1110- 0 +10--0 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF inst_VMA_INTreg.D +--0000-01 1 +-1----1-- 1 +-1------1 1 +-1-----0- 1 +-1---1--- 1 +-1--0---- 1 +-1-0----- 1 +-11------ 1 +0-------- 1 +1-0110010 0 +10---1--- 0 +101------ 0 +10-----1- 0 +10--1---- 0 +10-1----- 0 +10------0 0 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \ inst_RW_000_INT.D +---0-1-- 1 -01-1--- 1 -011---1 1 ----0-1-- 1 --0--1-- 1 -1---1-- 1 ------0- 1 @@ -344,21 +474,22 @@ inst_RW_000_INT.D .names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ -SM_AMIGA_i_7_.BLIF inst_AS_030_000_SYNC.D -1--00101--1-- 1 -----------10- 1 ---------0-1-- 1 --0--------1-- 1 -----------1-1 1 ----------1--- 1 ---0---------- 1 --11----010-10 0 --11---1-10-10 0 --11--0--10-10 0 --11-1---10-10 0 --111----10-10 0 -011-----10-10 0 ---1------00-- 0 +SM_AMIGA_i_7_.BLIF AS_030.PIN.BLIF inst_AS_030_000_SYNC.D +1--00101--1--- 1 +----------1-1- 1 +----------10-- 1 +---------11--- 1 +--------0-1--- 1 +-0--------1--- 1 +--0----------- 1 +-------------1 1 +-11----010-100 0 +-11---1-10-100 0 +-11--0--10-100 0 +-11-1---10-100 0 +-111----10-100 0 +011-----10-100 0 +--1-------0--0 0 .names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D --1100 1 @@ -424,133 +555,6 @@ inst_DS_000_DMA.D -10--01-010- 0 -10--10-01-0 0 -10--01-01-0 0 -.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D -0- 1 --1 1 -10 0 -.names VPA.BLIF RST.BLIF inst_VPA_D.D -1- 1 --0 1 -01 0 -.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D -1- 1 --0 1 -01 0 -.names RST.BLIF CLK_000_D_1_.BLIF inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF \ -RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D -11-0111 1 -1-1---- 1 -0------ 0 ---0--0- 0 ---0-0-- 0 ---01--- 0 --00---- 0 ---0---0 0 -.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ -inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF RW.PIN.BLIF \ -inst_DS_000_ENABLE.D -1-01--1- 1 -1-01-1-1 1 -10--1--- 1 -----000- 0 --1---00- 0 -----0-00 0 --1----00 0 ----00--- 0 ---1-0--- 0 --1-0---- 0 --11----- 0 -0------- 0 -.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ -CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D -----01 1 ----0-1 1 -0----1 1 ---0--- 1 --1---- 1 -10111- 0 --01--0 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D ---1-1 1 --10-- 1 ---10- 1 -0---- 1 -1-110 0 -100-- 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D ---11- 1 --00-- 1 ---1-0 1 -0---- 1 -1-101 0 -110-- 0 -.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ -inst_UDS_000_INT.D --10- 1 -0--- 1 ---11 1 -100- 0 -1-10 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D --111- 1 -0---- 1 --0--1 1 -11-0- 0 -110-- 0 -10--0 0 -.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INT.D ---1-0- 1 --1--0- 1 ---11-- 1 --1-1-- 1 -0----- 1 ---1--0 1 --1---0 1 -1--011 0 -100--- 0 -.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ -inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF inst_DSACK1_INTreg.D ----11- 1 ---0-1- 1 --1-1-- 1 --10--- 1 -0----- 1 -----10 1 --1---0 1 -1-10-1 0 -10--0- 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF inst_VMA_INTreg.D ---0000-01 1 --1----1-- 1 --1-1----- 1 --11------ 1 -0-------- 1 --1-----0- 1 --1---0--- 1 --1--0---- 1 --1------1 1 -1-0011010 0 -10-1----- 0 -101------ 0 -10-----1- 0 -10---1--- 0 -10--1---- 0 -10------0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1-1- 1 --10-- 1 -0---- 1 --0--1 1 -1110- 0 -10--0 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -590,16 +594,17 @@ AS_030.PIN.BLIF FPU_CS 0-------- 1 --------1 1 110001010 0 -.names inst_DSACK1_INTreg.BLIF DSACK1 -1 1 -0 0 +.names inst_DSACK1_INT.BLIF AS_030.PIN.BLIF DSACK1 +1- 1 +-1 1 +00 0 .names AVEC 1 -.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_1_.BLIF E -010 1 -101 1 --00 0 -0-1 0 +.names cpu_est_3_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF E +100 1 +011 1 +0-0 0 +-01 0 11- 0 .names inst_VMA_INTreg.BLIF VMA 1 1 @@ -651,6 +656,15 @@ AHIGH_31_.PIN.BLIF CIIN .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_4_.C +1 1 +0 0 .names CLK_OSZI.BLIF SM_AMIGA_3_.C 1 1 0 0 @@ -684,13 +698,10 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF SM_AMIGA_i_7_.C 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SM_AMIGA_4_.C +.names CLK_OSZI.BLIF CLK_000_D_1_.C 1 1 0 0 .names CLK_000_D_1_.BLIF CLK_000_D_2_.D @@ -699,6 +710,18 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_D_2_.C 1 1 0 0 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_3_.C +1 1 +0 0 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_4_.C +1 1 +0 0 .names CLK_OSZI.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -738,28 +761,10 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_D_0_.C 1 1 0 0 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +.names CLK_OSZI.BLIF inst_DSACK1_INT.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_000_D_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DS_000_DMA.C +.names CLK_OSZI.BLIF inst_AS_000_INT.C 1 1 0 0 .names CLK_OSZI.BLIF inst_AS_030_D0.C @@ -780,14 +785,6 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D -10 1 -01 1 -00 0 -11 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_25.C -1 1 -0 0 .names CLK_OSZI.BLIF BG_000DFFreg.C 1 1 0 0 @@ -803,40 +800,51 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_A0_DMA.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_AS_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C +.names CLK_OSZI.BLIF inst_RW_000_DMA.C 1 1 0 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_RW_000_DMA.C +.names CLK_OSZI.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_000_DMA.C 1 1 0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C -1 1 -0 0 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_ -01 1 -1- 0 --0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names SIZE_DMA_1_.BLIF SIZE_1_ +1 1 +0 0 .names AHIGH_31_ 0 .names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030 @@ -850,23 +858,22 @@ AHIGH_31_.PIN.BLIF CIIN .names inst_RW_000_INT.BLIF RW_000 1 1 0 0 -.names inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF UDS_000 -0- 1 --1 1 -10 0 -.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000 +.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000 1- 1 -0 1 01 0 +.names inst_DS_000_ENABLE.BLIF inst_LDS_000_INT.BLIF LDS_000 +0- 1 +-1 1 +10 0 .names BERR 0 .names inst_RW_000_DMA.BLIF RW 1 1 0 0 -.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_0_ -10 1 -0- 0 --1 0 +.names SIZE_DMA_0_.BLIF SIZE_0_ +1 1 +0 0 .names AHIGH_30_ 0 .names AHIGH_29_ @@ -1018,11 +1025,11 @@ AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE .names cpu_est_2_.BLIF cpu_est_2_.D.X1 1 1 0 0 -.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \ +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF cpu_est_2_.D.X2 --1110 1 +11-10 1 +0---- 0 -0--- 0 ---0-- 0 ---0- 0 ----1 0 .names RST_DLY_1_.BLIF RST_DLY_1_.D.X1 @@ -1068,42 +1075,44 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2 11 1 0- 0 -0 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ -inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ BERR.PIN.BLIF SM_AMIGA_3_.D.X2 -1------0-110- 1 -10010001-0-1- 1 -1-----1100-1- 1 -1-----11-0-10 1 +1-------0110- 1 +1-------10-10 1 +1010000-10-1- 1 +1-----1010-1- 1 0------------ 0 --------1-1--- 0 --------0-0--- 0 --------0--0-- 0 --------0---1- 0 --------1---0- 0 --1----01----- 0 ---1---01----- 0 ----0--01----- 0 -----1-01----- 0 ------101----- 0 +--------11--- 0 +--------00--- 0 +--------0-0-- 0 +--------0--1- 0 +--------1--0- 0 +-1----0-1---1 0 +--0---0-1---1 0 +---1--0-1---1 0 +----1-0-1---1 0 +-----10-1---1 0 ------111---1 0 .names RST.BLIF SM_AMIGA_i_7_.BLIF SM_AMIGA_i_7_.D.X1 11 1 0- 0 -0 0 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF CLK_000_D_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_i_7_.BLIF \ -SM_AMIGA_i_7_.D.X2 -110001-0 1 -1100-100 1 --1-01-11 1 --0------ 0 ----1---- 0 -----0--1 0 -------01 0 -0------0 0 ---1----0 0 ------0-0 0 -----1-10 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_i_7_.BLIF SM_AMIGA_i_7_.D.X2 +11001-1-0 1 +1100-01-0 1 +1100--100 1 +-1--01-11 1 +-0------- 0 +----1---1 0 +-----0--1 0 +-------01 0 +0-------0 0 +--1-----0 0 +---1----0 0 +------0-0 0 +----01-10 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index b70f5f3..a882976 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Wed Sep 14 23:54:26 2016 +// Design '68030_tk' created Thu Oct 06 21:34:55 2016 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 8ef776e..23c47af 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,13 +2,11 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Wed Sep 14 23:54:26 2016 +Design bus68030 created Thu Oct 06 21:34:55 2016 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- - 1 2 1 Pin SIZE_1_ - 1 2 1 Pin SIZE_1_.OE 0 0 1 Pin AHIGH_31_ 1 3 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- @@ -23,23 +21,23 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 1 2 1 Pin LDS_000.OE 0 0 1 Pin BERR 1 9 1 Pin BERR.OE - 1 2 1 Pin SIZE_0_ - 1 2 1 Pin SIZE_0_.OE 0 0 1 Pin AHIGH_30_ 1 3 1 Pin AHIGH_30_.OE - 1 1 1 Pin CLK_DIV_OUT.D - 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_29_ 1 3 1 Pin AHIGH_29_.OE + 1 1 1 Pin CLK_DIV_OUT.D + 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_28_ 1 3 1 Pin AHIGH_28_.OE - 1 9 1 Pin FPU_CS- 0 0 1 Pin AHIGH_27_ 1 3 1 Pin AHIGH_27_.OE + 1 9 1 Pin FPU_CS- 0 0 1 Pin AHIGH_26_ 1 3 1 Pin AHIGH_26_.OE 0 0 1 Pin AHIGH_25_ 1 3 1 Pin AHIGH_25_.OE + 1 2 1 Pin DSACK1- + 1 1 1 Pin DSACK1.OE 0 0 1 Pin AHIGH_24_ 1 3 1 Pin AHIGH_24_.OE 1 0 1 Pin AVEC @@ -52,6 +50,9 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_1_.OE + 3 6 1 Pin SIZE_1_.D + 1 1 1 Pin SIZE_1_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -61,11 +62,11 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 1 1 1 Pin BG_000.C 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C + 1 2 1 Pin SIZE_0_.OE + 3 6 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C - 1 1 1 Pin DSACK1.OE - 2 6 1 Pin DSACK1.D- - 1 1 1 Pin DSACK1.C 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C 1 2 1 Pin RW.OE @@ -78,22 +79,20 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 1 1 1 Pin IPL_030_1_.C 10 8 1 Pin IPL_030_0_.D- 1 1 1 Pin IPL_030_0_.C - 1 1 1 NodeX1 cpu_est_2_.D.X1 - 1 4 1 NodeX2 cpu_est_2_.D.X2 - 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 2 6 1 Node inst_AS_000_INT.D- - 1 1 1 Node inst_AS_000_INT.C + 1 4 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 + 1 1 1 Node cpu_est_2_.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C - 7 13 1 Node inst_AS_030_000_SYNC.D + 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C 1 2 1 Node inst_BGACK_030_INT_D.D- 1 1 1 Node inst_BGACK_030_INT_D.C @@ -105,24 +104,22 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 1 1 1 Node CYCLE_DMA_0_.C 4 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C - 3 6 1 Node SIZE_DMA_0_.D- - 1 1 1 Node SIZE_DMA_0_.C - 3 6 1 Node SIZE_DMA_1_.D - 1 1 1 Node SIZE_DMA_1_.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C - 1 1 1 Node CLK_000_D_1_.D - 1 1 1 Node CLK_000_D_1_.C + 1 1 1 Node CLK_000_D_2_.D + 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_3_.D + 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 7 1 Node inst_RESET_OUT.D 1 1 1 Node inst_RESET_OUT.C + 1 1 1 Node CLK_000_D_1_.D + 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C - 2 2 1 Node inst_CLK_OUT_PRE_25.D - 1 1 1 Node inst_CLK_OUT_PRE_25.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C 1 2 1 Node IPL_D0_0_.D- @@ -131,23 +128,23 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C - 1 1 1 Node CLK_000_D_2_.D - 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_4_.D + 1 1 1 Node CLK_000_D_4_.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 3 6 1 Node inst_LDS_000_INT.D - 1 1 1 Node inst_LDS_000_INT.C - 3 8 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C + 4 7 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 2 4 1 Node inst_UDS_000_INT.D- 1 1 1 Node inst_UDS_000_INT.C - 3 8 1 Node SM_AMIGA_6_.D + 3 8 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 3 6 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.C + 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C - 3 5 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 3 5 1 Node SM_AMIGA_0_.D + 4 7 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 4 6 1 Node RST_DLY_0_.D 1 1 1 Node RST_DLY_0_.C @@ -158,18 +155,22 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 1 1 1 Node RST_DLY_2_.C 8 10 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C + 2 6 1 Node inst_DSACK1_INT.D- + 1 1 1 Node inst_DSACK1_INT.C + 2 6 1 Node inst_AS_000_INT.D- + 1 1 1 Node inst_AS_000_INT.C 3 5 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C 5 13 1 Node SM_AMIGA_3_.T 1 1 1 Node SM_AMIGA_3_.C 5 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C - 3 8 1 NodeX1 SM_AMIGA_i_7_.D.X1 - 1 5 1 NodeX2 SM_AMIGA_i_7_.D.X2 + 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 + 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 272 P-Term Total: 272 + 274 P-Term Total: 274 Total Pins: 61 Total Nodes: 44 Average P-Term/Output: 2 @@ -177,10 +178,6 @@ Design bus68030 created Wed Sep 14 23:54:26 2016 Equations: -SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); - -SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); - AHIGH_31_ = (0); AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -197,11 +194,11 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); -!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); +!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); @@ -209,32 +206,28 @@ BERR = (0); BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); -SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); - -SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); - AHIGH_30_ = (0); AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_DIV_OUT.C = (CLK_OSZI); - AHIGH_29_ = (0); AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_DIV_OUT.C = (CLK_OSZI); + AHIGH_28_ = (0); AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); - AHIGH_27_ = (0); AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); + AHIGH_26_ = (0); AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -243,14 +236,18 @@ AHIGH_25_ = (0); AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); + +DSACK1.OE = (nEXP_SPACE); + AHIGH_24_ = (0); AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); AVEC = (1); -E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q); +E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q); RESET = (0); @@ -270,6 +267,14 @@ CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030 CIIN.OE = (CIIN_0); +SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +SIZE_1_.D = (!RST + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_1_.Q + # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_1_.C = (CLK_OSZI); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -303,20 +308,21 @@ BGACK_030.D = (!RST BGACK_030.C = (CLK_OSZI); +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q + # RST & BGACK_030.Q & !SIZE_0_.Q + # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_0_.C = (CLK_OSZI); + CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); -DSACK1.OE = (nEXP_SPACE); - -!DSACK1.D = (RST & !inst_AS_030_D0.Q & !DSACK1.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); - -DSACK1.C = (CLK_OSZI); - VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q - # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + # !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q + # RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); VMA.C = (CLK_OSZI); @@ -361,16 +367,10 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (cpu_est_2_.Q); - -cpu_est_2_.D.X2 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -cpu_est_2_.C = (CLK_OSZI); - cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q # cpu_est_3_.Q & CLK_000_D_0_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q - # cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + # cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q + # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_3_.C = (CLK_OSZI); @@ -387,10 +387,11 @@ cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q cpu_est_1_.C = (CLK_OSZI); -!inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); +cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); -inst_AS_000_INT.C = (CLK_OSZI); +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.C = (CLK_OSZI); !inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); @@ -401,13 +402,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); inst_AS_030_D0.C = (CLK_OSZI); -inst_AS_030_000_SYNC.D = (!RST - # inst_AS_030_D0.Q - # !nEXP_SPACE & inst_AS_030_000_SYNC.Q - # !BGACK_030.Q & inst_AS_030_000_SYNC.Q - # inst_AS_030_000_SYNC.Q & !inst_BGACK_030_INT_D.Q - # inst_AS_030_000_SYNC.Q & SM_AMIGA_i_7_.Q - # FC_1_ & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); +!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_000_SYNC.Q & !AS_030.PIN + # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); @@ -450,25 +451,17 @@ CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_00 CYCLE_DMA_1_.C = (CLK_OSZI); -!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q - # RST & BGACK_030.Q & !SIZE_DMA_0_.Q - # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_DMA_0_.C = (CLK_OSZI); - -SIZE_DMA_1_.D = (!RST - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q - # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_DMA_1_.C = (CLK_OSZI); - !inst_VPA_D.D = (!VPA & RST); inst_VPA_D.C = (CLK_OSZI); -CLK_000_D_1_.D = (CLK_000_D_0_.Q); +CLK_000_D_2_.D = (CLK_000_D_1_.Q); -CLK_000_D_1_.C = (CLK_OSZI); +CLK_000_D_2_.C = (CLK_OSZI); + +CLK_000_D_3_.D = (CLK_000_D_2_.Q); + +CLK_000_D_3_.C = (CLK_OSZI); !inst_DTACK_D0.D = (!DTACK & RST); @@ -479,6 +472,10 @@ inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q inst_RESET_OUT.C = (CLK_OSZI); +CLK_000_D_1_.D = (CLK_000_D_0_.Q); + +CLK_000_D_1_.C = (CLK_OSZI); + CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); @@ -487,12 +484,7 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); -inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q - # inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q); - -inst_CLK_OUT_PRE_25.C = (CLK_OSZI); - -inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q); +inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); @@ -508,35 +500,42 @@ IPL_D0_1_.C = (CLK_OSZI); IPL_D0_2_.C = (CLK_OSZI); -CLK_000_D_2_.D = (CLK_000_D_1_.Q); +CLK_000_D_4_.D = (CLK_000_D_3_.Q); -CLK_000_D_2_.C = (CLK_OSZI); +CLK_000_D_4_.C = (CLK_OSZI); !inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); +SM_AMIGA_1_.D = (RST & CLK_000_D_2_.Q & SM_AMIGA_1_.Q + # RST & !CLK_000_D_3_.Q & SM_AMIGA_1_.Q + # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + +!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); + +inst_UDS_000_INT.C = (CLK_OSZI); + +inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); inst_LDS_000_INT.C = (CLK_OSZI); -inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); - -inst_DS_000_ENABLE.C = (CLK_OSZI); - -!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A_0_.PIN); - -inst_UDS_000_INT.C = (CLK_OSZI); - SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -546,15 +545,10 @@ SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q SM_AMIGA_4_.C = (CLK_OSZI); -SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q - # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); + # RST & SM_AMIGA_1_.Q & SM_AMIGA_0_.Q + # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); @@ -588,6 +582,16 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); +!inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN + # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); + +inst_DSACK1_INT.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !AS_030.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); + +inst_AS_000_INT.C = (CLK_OSZI); + SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q # RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); @@ -595,26 +599,26 @@ SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q SM_AMIGA_5_.C = (CLK_OSZI); SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q - # inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q + # CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN - # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q - # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q - # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN - # RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_i_7_.D.X1 = (RST & SM_AMIGA_i_7_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & !CLK_000_D_0_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); +SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); -SM_AMIGA_i_7_.D.X2 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q); +SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_4_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 5966a04..b3f4edc 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -34,18 +34,20 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT -DATA LOCATION CIIN_0:E_9 // NOD +DATA LOCATION CIIN_0:E_5 // NOD DATA LOCATION CLK_000:*_*_11 // INP DATA LOCATION CLK_000_D_0_:B_13 // NOD DATA LOCATION CLK_000_D_1_:H_5 // NOD -DATA LOCATION CLK_000_D_2_:E_13 // NOD +DATA LOCATION CLK_000_D_2_:H_2 // NOD +DATA LOCATION CLK_000_D_3_:D_9 // NOD +DATA LOCATION CLK_000_D_4_:D_10 // NOD DATA LOCATION CLK_030:*_*_64 // INP DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CYCLE_DMA_0_:G_2 // NOD -DATA LOCATION CYCLE_DMA_1_:G_5 // NOD -DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1} +DATA LOCATION CYCLE_DMA_0_:A_1 // NOD +DATA LOCATION CYCLE_DMA_1_:G_10 // NOD +DATA LOCATION DSACK1:H_9_81 // OUT DATA LOCATION DS_030:A_0_98 // OUT DATA LOCATION DTACK:D_*_30 // INP DATA LOCATION E:G_4_66 // OUT @@ -59,64 +61,63 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:C_14 // NOD -DATA LOCATION IPL_D0_1_:D_14 // NOD -DATA LOCATION IPL_D0_2_:C_10 // NOD +DATA LOCATION IPL_D0_0_:D_14 // NOD +DATA LOCATION IPL_D0_1_:B_14 // NOD +DATA LOCATION IPL_D0_2_:G_14 // NOD DATA LOCATION LDS_000:D_12_31 // IO DATA LOCATION RESET:B_2_3 // OUT DATA LOCATION RN_A_0_:G_8 // NOD {A_0_} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} -DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1} DATA LOCATION RN_IPL_030_0_:B_5 // NOD {IPL_030_0_} DATA LOCATION RN_IPL_030_1_:B_9 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} DATA LOCATION RN_RW:G_0 // NOD {RW} DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} +DATA LOCATION RN_SIZE_0_:G_12 // NOD {SIZE_0_} +DATA LOCATION RN_SIZE_1_:H_12 // NOD {SIZE_1_} DATA LOCATION RN_VMA:D_0 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RST_DLY_0_:A_13 // NOD -DATA LOCATION RST_DLY_1_:A_6 // NOD -DATA LOCATION RST_DLY_2_:A_2 // NOD +DATA LOCATION RST_DLY_0_:C_9 // NOD +DATA LOCATION RST_DLY_1_:A_13 // NOD +DATA LOCATION RST_DLY_2_:A_9 // NOD DATA LOCATION RW:G_0_71 // IO {RN_RW} DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} -DATA LOCATION SIZE_0_:G_12_70 // IO -DATA LOCATION SIZE_1_:H_12_79 // IO -DATA LOCATION SIZE_DMA_0_:C_2 // NOD -DATA LOCATION SIZE_DMA_1_:G_10 // NOD -DATA LOCATION SM_AMIGA_0_:H_13 // NOD -DATA LOCATION SM_AMIGA_1_:A_12 // NOD -DATA LOCATION SM_AMIGA_2_:A_5 // NOD -DATA LOCATION SM_AMIGA_3_:A_9 // NOD -DATA LOCATION SM_AMIGA_4_:G_13 // NOD -DATA LOCATION SM_AMIGA_5_:D_13 // NOD -DATA LOCATION SM_AMIGA_6_:B_6 // NOD -DATA LOCATION SM_AMIGA_i_7_:B_14 // NOD +DATA LOCATION SIZE_0_:G_12_70 // IO {RN_SIZE_0_} +DATA LOCATION SIZE_1_:H_12_79 // IO {RN_SIZE_1_} +DATA LOCATION SM_AMIGA_0_:A_12 // NOD +DATA LOCATION SM_AMIGA_1_:C_13 // NOD +DATA LOCATION SM_AMIGA_2_:C_6 // NOD +DATA LOCATION SM_AMIGA_3_:C_10 // NOD +DATA LOCATION SM_AMIGA_4_:C_2 // NOD +DATA LOCATION SM_AMIGA_5_:D_6 // NOD +DATA LOCATION SM_AMIGA_6_:F_0 // NOD +DATA LOCATION SM_AMIGA_i_7_:F_8 // NOD DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:B_10 // NOD -DATA LOCATION cpu_est_1_:G_9 // NOD -DATA LOCATION cpu_est_2_:G_6 // NOD -DATA LOCATION cpu_est_3_:D_9 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:F_8 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:F_12 // NOD -DATA LOCATION inst_AS_000_DMA:C_9 // NOD -DATA LOCATION inst_AS_000_INT:D_2 // NOD -DATA LOCATION inst_AS_030_000_SYNC:C_13 // NOD -DATA LOCATION inst_AS_030_D0:E_8 // NOD -DATA LOCATION inst_BGACK_030_INT_D:E_5 // NOD -DATA LOCATION inst_CLK_030_H:C_6 // NOD -DATA LOCATION inst_CLK_OUT_PRE_25:G_14 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:A_1 // NOD -DATA LOCATION inst_CLK_OUT_PRE_D:H_2 // NOD -DATA LOCATION inst_DS_000_DMA:F_0 // NOD -DATA LOCATION inst_DS_000_ENABLE:D_6 // NOD -DATA LOCATION inst_DTACK_D0:H_6 // NOD -DATA LOCATION inst_LDS_000_INT:F_4 // NOD +DATA LOCATION cpu_est_0_:G_9 // NOD +DATA LOCATION cpu_est_1_:G_5 // NOD +DATA LOCATION cpu_est_2_:D_2 // NOD +DATA LOCATION cpu_est_3_:D_13 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:A_2 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:A_6 // NOD +DATA LOCATION inst_AS_000_DMA:G_2 // NOD +DATA LOCATION inst_AS_000_INT:F_1 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_4 // NOD +DATA LOCATION inst_AS_030_D0:H_6 // NOD +DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD +DATA LOCATION inst_CLK_030_H:G_6 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:E_9 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD +DATA LOCATION inst_DSACK1_INT:A_5 // NOD +DATA LOCATION inst_DS_000_DMA:G_13 // NOD +DATA LOCATION inst_DS_000_ENABLE:F_12 // NOD +DATA LOCATION inst_DTACK_D0:C_14 // NOD +DATA LOCATION inst_LDS_000_INT:B_6 // NOD DATA LOCATION inst_RESET_OUT:A_8 // NOD -DATA LOCATION inst_UDS_000_INT:D_10 // NOD -DATA LOCATION inst_VPA_D:F_1 // NOD +DATA LOCATION inst_UDS_000_INT:B_10 // NOD +DATA LOCATION inst_VPA_D:A_10 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AHIGH_24_:BI DATA IO_DIR AHIGH_25_:BI @@ -180,8 +181,6 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL SIZE_1_:1 -DATA SLEW SIZE_1_:0 DATA PW_LEVEL AHIGH_31_:1 DATA SLEW AHIGH_31_:0 DATA PW_LEVEL A_DECODE_23_:1 @@ -209,51 +208,51 @@ DATA PW_LEVEL BGACK_000:1 DATA SLEW BGACK_000:1 DATA SLEW CLK_030:1 DATA SLEW CLK_000:1 -DATA PW_LEVEL SIZE_0_:1 -DATA SLEW SIZE_0_:0 -DATA SLEW CLK_OSZI:1 DATA PW_LEVEL AHIGH_30_:1 DATA SLEW AHIGH_30_:0 -DATA PW_LEVEL CLK_DIV_OUT:1 -DATA SLEW CLK_DIV_OUT:0 +DATA SLEW CLK_OSZI:1 DATA PW_LEVEL AHIGH_29_:1 DATA SLEW AHIGH_29_:0 +DATA PW_LEVEL CLK_DIV_OUT:1 +DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL AHIGH_28_:1 DATA SLEW AHIGH_28_:0 -DATA PW_LEVEL FPU_CS:1 -DATA SLEW FPU_CS:0 DATA PW_LEVEL AHIGH_27_:1 DATA SLEW AHIGH_27_:0 -DATA PW_LEVEL FPU_SENSE:1 -DATA SLEW FPU_SENSE:1 +DATA PW_LEVEL FPU_CS:1 +DATA SLEW FPU_CS:0 DATA PW_LEVEL AHIGH_26_:1 DATA SLEW AHIGH_26_:0 +DATA PW_LEVEL FPU_SENSE:1 +DATA SLEW FPU_SENSE:1 DATA PW_LEVEL AHIGH_25_:1 DATA SLEW AHIGH_25_:0 -DATA PW_LEVEL DTACK:1 -DATA SLEW DTACK:1 +DATA PW_LEVEL DSACK1:1 +DATA SLEW DSACK1:0 DATA PW_LEVEL AHIGH_24_:1 DATA SLEW AHIGH_24_:0 -DATA PW_LEVEL AVEC:1 -DATA SLEW AVEC:0 +DATA PW_LEVEL DTACK:1 +DATA SLEW DTACK:1 DATA PW_LEVEL A_DECODE_22_:1 DATA SLEW A_DECODE_22_:1 -DATA PW_LEVEL E:1 -DATA SLEW E:0 +DATA PW_LEVEL AVEC:1 +DATA SLEW AVEC:0 DATA PW_LEVEL A_DECODE_21_:1 DATA SLEW A_DECODE_21_:1 -DATA SLEW VPA:1 +DATA PW_LEVEL E:1 +DATA SLEW E:0 DATA PW_LEVEL A_DECODE_20_:1 DATA SLEW A_DECODE_20_:1 +DATA SLEW VPA:1 DATA PW_LEVEL A_DECODE_19_:1 DATA SLEW A_DECODE_19_:1 -DATA SLEW RST:1 DATA PW_LEVEL A_DECODE_18_:1 DATA SLEW A_DECODE_18_:1 -DATA PW_LEVEL RESET:1 -DATA SLEW RESET:0 +DATA SLEW RST:1 DATA PW_LEVEL A_DECODE_17_:1 DATA SLEW A_DECODE_17_:1 +DATA PW_LEVEL RESET:1 +DATA SLEW RESET:0 DATA PW_LEVEL A_DECODE_16_:1 DATA SLEW A_DECODE_16_:1 DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 @@ -274,6 +273,8 @@ DATA PW_LEVEL FC_0_:1 DATA SLEW FC_0_:1 DATA PW_LEVEL A_1_:1 DATA SLEW A_1_:1 +DATA PW_LEVEL SIZE_1_:1 +DATA SLEW SIZE_1_:0 DATA PW_LEVEL IPL_030_2_:1 DATA SLEW IPL_030_2_:0 DATA PW_LEVEL RW_000:1 @@ -282,10 +283,10 @@ DATA PW_LEVEL BG_000:1 DATA SLEW BG_000:0 DATA PW_LEVEL BGACK_030:1 DATA SLEW BGACK_030:0 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:0 DATA PW_LEVEL CLK_EXP:1 DATA SLEW CLK_EXP:0 -DATA PW_LEVEL DSACK1:1 -DATA SLEW DSACK1:0 DATA PW_LEVEL VMA:1 DATA SLEW VMA:0 DATA PW_LEVEL RW:1 @@ -296,16 +297,14 @@ DATA PW_LEVEL IPL_030_1_:1 DATA SLEW IPL_030_1_:0 DATA PW_LEVEL IPL_030_0_:1 DATA SLEW IPL_030_0_:0 -DATA PW_LEVEL cpu_est_2_:1 -DATA SLEW cpu_est_2_:1 DATA PW_LEVEL cpu_est_3_:1 DATA SLEW cpu_est_3_:1 DATA PW_LEVEL cpu_est_0_:1 DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:1 DATA SLEW cpu_est_1_:1 -DATA PW_LEVEL inst_AS_000_INT:1 -DATA SLEW inst_AS_000_INT:1 +DATA PW_LEVEL cpu_est_2_:1 +DATA SLEW cpu_est_2_:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA PW_LEVEL inst_AS_030_D0:1 @@ -322,24 +321,22 @@ DATA PW_LEVEL CYCLE_DMA_0_:1 DATA SLEW CYCLE_DMA_0_:1 DATA PW_LEVEL CYCLE_DMA_1_:1 DATA SLEW CYCLE_DMA_1_:1 -DATA PW_LEVEL SIZE_DMA_0_:1 -DATA SLEW SIZE_DMA_0_:1 -DATA PW_LEVEL SIZE_DMA_1_:1 -DATA SLEW SIZE_DMA_1_:1 DATA PW_LEVEL inst_VPA_D:1 DATA SLEW inst_VPA_D:1 -DATA PW_LEVEL CLK_000_D_1_:1 -DATA SLEW CLK_000_D_1_:1 +DATA PW_LEVEL CLK_000_D_2_:1 +DATA SLEW CLK_000_D_2_:1 +DATA PW_LEVEL CLK_000_D_3_:1 +DATA SLEW CLK_000_D_3_:1 DATA PW_LEVEL inst_DTACK_D0:1 DATA SLEW inst_DTACK_D0:1 DATA PW_LEVEL inst_RESET_OUT:1 DATA SLEW inst_RESET_OUT:1 +DATA PW_LEVEL CLK_000_D_1_:1 +DATA SLEW CLK_000_D_1_:1 DATA PW_LEVEL CLK_000_D_0_:1 DATA SLEW CLK_000_D_0_:1 DATA PW_LEVEL inst_CLK_OUT_PRE_50:1 DATA SLEW inst_CLK_OUT_PRE_50:1 -DATA PW_LEVEL inst_CLK_OUT_PRE_25:1 -DATA SLEW inst_CLK_OUT_PRE_25:1 DATA PW_LEVEL inst_CLK_OUT_PRE_D:1 DATA SLEW inst_CLK_OUT_PRE_D:1 DATA PW_LEVEL IPL_D0_0_:1 @@ -348,22 +345,22 @@ DATA PW_LEVEL IPL_D0_1_:1 DATA SLEW IPL_D0_1_:1 DATA PW_LEVEL IPL_D0_2_:1 DATA SLEW IPL_D0_2_:1 -DATA PW_LEVEL CLK_000_D_2_:1 -DATA SLEW CLK_000_D_2_:1 +DATA PW_LEVEL CLK_000_D_4_:1 +DATA SLEW CLK_000_D_4_:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 -DATA PW_LEVEL inst_LDS_000_INT:1 -DATA SLEW inst_LDS_000_INT:1 -DATA PW_LEVEL inst_DS_000_ENABLE:1 -DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL SM_AMIGA_1_:1 +DATA SLEW SM_AMIGA_1_:1 DATA PW_LEVEL inst_UDS_000_INT:1 DATA SLEW inst_UDS_000_INT:1 +DATA PW_LEVEL inst_DS_000_ENABLE:1 +DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL inst_LDS_000_INT:1 +DATA SLEW inst_LDS_000_INT:1 DATA PW_LEVEL SM_AMIGA_6_:1 DATA SLEW SM_AMIGA_6_:1 DATA PW_LEVEL SM_AMIGA_4_:1 DATA SLEW SM_AMIGA_4_:1 -DATA PW_LEVEL SM_AMIGA_1_:1 -DATA SLEW SM_AMIGA_1_:1 DATA PW_LEVEL SM_AMIGA_0_:1 DATA SLEW SM_AMIGA_0_:1 DATA PW_LEVEL RST_DLY_0_:1 @@ -374,6 +371,10 @@ DATA PW_LEVEL RST_DLY_2_:1 DATA SLEW RST_DLY_2_:1 DATA PW_LEVEL inst_CLK_030_H:1 DATA SLEW inst_CLK_030_H:1 +DATA PW_LEVEL inst_DSACK1_INT:1 +DATA SLEW inst_DSACK1_INT:1 +DATA PW_LEVEL inst_AS_000_INT:1 +DATA SLEW inst_AS_000_INT:1 DATA PW_LEVEL SM_AMIGA_5_:1 DATA SLEW SM_AMIGA_5_:1 DATA PW_LEVEL SM_AMIGA_3_:1 @@ -384,11 +385,12 @@ DATA PW_LEVEL SM_AMIGA_i_7_:1 DATA SLEW SM_AMIGA_i_7_:1 DATA PW_LEVEL CIIN_0:1 DATA SLEW CIIN_0:1 +DATA PW_LEVEL RN_SIZE_1_:1 DATA PW_LEVEL RN_IPL_030_2_:1 DATA PW_LEVEL RN_RW_000:1 DATA PW_LEVEL RN_BG_000:1 DATA PW_LEVEL RN_BGACK_030:1 -DATA PW_LEVEL RN_DSACK1:1 +DATA PW_LEVEL RN_SIZE_0_:1 DATA PW_LEVEL RN_VMA:1 DATA PW_LEVEL RN_RW:1 DATA PW_LEVEL RN_A_0_:1 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index feb2ec9..063576b 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,22 +1,23 @@ -GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ SM_AMIGA_3_ inst_RESET_OUT RST_DLY_0_ - RST_DLY_1_ RST_DLY_2_ SM_AMIGA_1_ inst_CLK_OUT_PRE_50 -GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET SM_AMIGA_i_7_ - SM_AMIGA_6_ cpu_est_0_ CLK_000_D_0_ -GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW - inst_AS_030_000_SYNC inst_CLK_030_H inst_AS_000_DMA SIZE_DMA_0_ IPL_D0_0_ - IPL_D0_2_ -GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH - AMIGA_ADDR_ENABLE inst_DS_000_ENABLE cpu_est_3_ inst_AS_000_INT SM_AMIGA_5_ - inst_UDS_000_INT IPL_D0_1_ -GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_AS_030_D0 - inst_BGACK_030_INT_D CLK_000_D_2_ -GROUP MACH_SEG_F inst_DS_000_DMA inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW +GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_0_ inst_RESET_OUT inst_DSACK1_INT + RST_DLY_1_ RST_DLY_2_ CYCLE_DMA_0_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_VPA_D -GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW SIZE_0_ E CLK_DIV_OUT CYCLE_DMA_1_ - SIZE_DMA_1_ CYCLE_DMA_0_ cpu_est_2_ cpu_est_1_ SM_AMIGA_4_ inst_CLK_OUT_PRE_25 +GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ + RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP RESET inst_LDS_000_INT + inst_UDS_000_INT IPL_D0_1_ CLK_000_D_0_ +GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW + SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_1_ RST_DLY_0_ SM_AMIGA_4_ inst_DTACK_D0 -GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS DSACK1 RN_DSACK1 BGACK_030 RN_BGACK_030 - AS_030 SIZE_1_ SM_AMIGA_0_ inst_DTACK_D0 inst_CLK_OUT_PRE_D CLK_000_D_1_ +GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH + AMIGA_ADDR_ENABLE cpu_est_3_ cpu_est_2_ SM_AMIGA_5_ IPL_D0_0_ CLK_000_D_3_ + CLK_000_D_4_ +GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_CLK_OUT_PRE_50 + inst_CLK_OUT_PRE_D +GROUP MACH_SEG_F inst_AS_030_000_SYNC SM_AMIGA_i_7_ SM_AMIGA_6_ inst_DS_000_ENABLE + inst_AS_000_INT +GROUP MACH_SEG_G SIZE_0_ RN_SIZE_0_ A_0_ RN_A_0_ RW RN_RW E CLK_DIV_OUT + inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA CYCLE_DMA_1_ cpu_est_1_ + cpu_est_0_ IPL_D0_2_ +GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS SIZE_1_ RN_SIZE_1_ BGACK_030 RN_BGACK_030 + AS_030 DSACK1 inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_D_2_ CLK_000_D_1_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 38f3532..9a7d65c 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -6723==5O39`{> \ No newline at end of file +5861<2358=g \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index e4b0ab0..4140a07 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Wed Sep 14 23:54:30 2016 +DATE: Thu Oct 06 21:35:00 2016 ABEL mach447a * @@ -31,71 +31,70 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS SIZE_1_:79 AHIGH_31_:4 A_DECODE_23_:85 IPL_2_:68* -NOTE PINS FC_1_:58 AS_030:82 AS_000:42 DS_030:98 UDS_000:32* -NOTE PINS LDS_000:31 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28* -NOTE PINS CLK_030:64 CLK_000:11 SIZE_0_:70 CLK_OSZI:61 AHIGH_30_:5* -NOTE PINS CLK_DIV_OUT:65 AHIGH_29_:6 AHIGH_28_:15 FPU_CS:78* -NOTE PINS AHIGH_27_:16 FPU_SENSE:91 AHIGH_26_:17 AHIGH_25_:18* -NOTE PINS DTACK:30 AHIGH_24_:19 AVEC:92 A_DECODE_22_:84 E:66* -NOTE PINS A_DECODE_21_:94 VPA:36 A_DECODE_20_:93 A_DECODE_19_:97* -NOTE PINS RST:86 A_DECODE_18_:95 RESET:3 A_DECODE_17_:59* -NOTE PINS A_DECODE_16_:96 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48* -NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* -NOTE PINS CIIN:47 IPL_1_:56 IPL_0_:67 FC_0_:57 A_1_:60 IPL_030_2_:9* -NOTE PINS RW_000:80 BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81* -NOTE PINS VMA:35 RW:71 A_0_:69 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS AHIGH_31_:4 A_DECODE_23_:85 IPL_2_:68 FC_1_:58* +NOTE PINS AS_030:82 AS_000:42 DS_030:98 UDS_000:32 LDS_000:31* +NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28 CLK_030:64* +NOTE PINS CLK_000:11 AHIGH_30_:5 CLK_OSZI:61 AHIGH_29_:6* +NOTE PINS CLK_DIV_OUT:65 AHIGH_28_:15 AHIGH_27_:16 FPU_CS:78* +NOTE PINS AHIGH_26_:17 FPU_SENSE:91 AHIGH_25_:18 DSACK1:81* +NOTE PINS AHIGH_24_:19 DTACK:30 A_DECODE_22_:84 AVEC:92 A_DECODE_21_:94* +NOTE PINS E:66 A_DECODE_20_:93 VPA:36 A_DECODE_19_:97 A_DECODE_18_:95* +NOTE PINS RST:86 A_DECODE_17_:59 RESET:3 A_DECODE_16_:96* +NOTE PINS AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20* +NOTE PINS AMIGA_BUS_ENABLE_HIGH:34 CIIN:47 IPL_1_:56 IPL_0_:67* +NOTE PINS FC_0_:57 A_1_:60 SIZE_1_:79 IPL_030_2_:9 RW_000:80* +NOTE PINS BG_000:29 BGACK_030:83 SIZE_0_:70 CLK_EXP:10 VMA:35* +NOTE PINS RW:71 A_0_:69 IPL_030_1_:7 IPL_030_0_:8 * NOTE Table of node names and numbers* -NOTE NODES RN_SIZE_1_:287 RN_AHIGH_31_:143 RN_AS_030:281 * -NOTE NODES RN_AS_000:203 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * -NOTE NODES RN_SIZE_0_:263 RN_AHIGH_30_:125 RN_AHIGH_29_:137 * -NOTE NODES RN_AHIGH_28_:149 RN_AHIGH_27_:157 RN_AHIGH_26_:155 * -NOTE NODES RN_AHIGH_25_:167 RN_AHIGH_24_:161 RN_IPL_030_2_:131 * -NOTE NODES RN_RW_000:269 RN_BG_000:175 RN_BGACK_030:275 * -NOTE NODES RN_DSACK1:283 RN_VMA:173 RN_RW:245 RN_A_0_:257 * -NOTE NODES RN_IPL_030_1_:139 RN_IPL_030_0_:133 cpu_est_2_:254 * -NOTE NODES cpu_est_3_:187 cpu_est_0_:140 cpu_est_1_:259 * -NOTE NODES inst_AS_000_INT:176 inst_AMIGA_BUS_ENABLE_DMA_LOW:239 * -NOTE NODES inst_AS_030_D0:209 inst_AS_030_000_SYNC:169 inst_BGACK_030_INT_D:205 * -NOTE NODES inst_AS_000_DMA:163 inst_DS_000_DMA:221 CYCLE_DMA_0_:248 * -NOTE NODES CYCLE_DMA_1_:253 SIZE_DMA_0_:152 SIZE_DMA_1_:260 * -NOTE NODES inst_VPA_D:223 CLK_000_D_1_:277 inst_DTACK_D0:278 * -NOTE NODES inst_RESET_OUT:113 CLK_000_D_0_:145 inst_CLK_OUT_PRE_50:103 * -NOTE NODES inst_CLK_OUT_PRE_25:266 inst_CLK_OUT_PRE_D:272 * -NOTE NODES IPL_D0_0_:170 IPL_D0_1_:194 IPL_D0_2_:164 CLK_000_D_2_:217 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:233 inst_LDS_000_INT:227 * -NOTE NODES inst_DS_000_ENABLE:182 inst_UDS_000_INT:188 SM_AMIGA_6_:134 * -NOTE NODES SM_AMIGA_4_:265 SM_AMIGA_1_:119 SM_AMIGA_0_:289 * -NOTE NODES RST_DLY_0_:121 RST_DLY_1_:110 RST_DLY_2_:104 * -NOTE NODES inst_CLK_030_H:158 SM_AMIGA_5_:193 SM_AMIGA_3_:115 * -NOTE NODES SM_AMIGA_2_:109 SM_AMIGA_i_7_:146 CIIN_0:211 * +NOTE NODES RN_AHIGH_31_:143 RN_AS_030:281 RN_AS_000:203 * +NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 RN_AHIGH_30_:125 * +NOTE NODES RN_AHIGH_29_:137 RN_AHIGH_28_:149 RN_AHIGH_27_:157 * +NOTE NODES RN_AHIGH_26_:155 RN_AHIGH_25_:167 RN_AHIGH_24_:161 * +NOTE NODES RN_SIZE_1_:287 RN_IPL_030_2_:131 RN_RW_000:269 * +NOTE NODES RN_BG_000:175 RN_BGACK_030:275 RN_SIZE_0_:263 * +NOTE NODES RN_VMA:173 RN_RW:245 RN_A_0_:257 RN_IPL_030_1_:139 * +NOTE NODES RN_IPL_030_0_:133 cpu_est_3_:193 cpu_est_0_:259 * +NOTE NODES cpu_est_1_:253 cpu_est_2_:176 inst_AMIGA_BUS_ENABLE_DMA_LOW:110 * +NOTE NODES inst_AS_030_D0:278 inst_AS_030_000_SYNC:227 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:248 inst_DS_000_DMA:265 CYCLE_DMA_0_:103 * +NOTE NODES CYCLE_DMA_1_:260 inst_VPA_D:116 CLK_000_D_2_:272 * +NOTE NODES CLK_000_D_3_:187 inst_DTACK_D0:170 inst_RESET_OUT:113 * +NOTE NODES CLK_000_D_1_:277 CLK_000_D_0_:145 inst_CLK_OUT_PRE_50:211 * +NOTE NODES inst_CLK_OUT_PRE_D:209 IPL_D0_0_:194 IPL_D0_1_:146 * +NOTE NODES IPL_D0_2_:266 CLK_000_D_4_:188 inst_AMIGA_BUS_ENABLE_DMA_HIGH:104 * +NOTE NODES SM_AMIGA_1_:169 inst_UDS_000_INT:140 inst_DS_000_ENABLE:239 * +NOTE NODES inst_LDS_000_INT:134 SM_AMIGA_6_:221 SM_AMIGA_4_:152 * +NOTE NODES SM_AMIGA_0_:119 RST_DLY_0_:163 RST_DLY_1_:121 * +NOTE NODES RST_DLY_2_:115 inst_CLK_030_H:254 inst_DSACK1_INT:109 * +NOTE NODES inst_AS_000_INT:223 SM_AMIGA_5_:182 SM_AMIGA_3_:164 * +NOTE NODES SM_AMIGA_2_:158 SM_AMIGA_i_7_:233 CIIN_0:205 * NOTE BLOCK 0 * L000000 - 111111111111111111110111101111111111111111111111111111111111111111 - 111101111101111111111111111111111111111111111111111111101111111111 - 111111111111111111111111111111111111111111111110111111111111111111 + 111111111111111111110111111111111111111111111111111011111111011111 + 111111011101111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111101011 - 111111111111111111111111111111111111111111111111010111111111111111 - 111111011111110111111111111111011111110111111111111111111111111111 - 111111111011111111111111111111111111011110101111111111111111111111 - 100111111111111111011111111111111010111111110111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111110111111111111111111111111111111111111111111 + 011111111111111111111111111111111111111011111111011111111111111111 + 111111111111110111111111111111011111011111111111111111111101111111 + 111101111111111111101111111111111111111110111111111111101111111111 + 111111111011111111111111010111111011111111100111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111111111111111111111111111111011111111111111111111111111111011* +L000660 111111111111111111111111111111111011111111111111111011111111111111* L000726 000000000000000000000000000000000000000000000000000000000000000000* L000792 000000000000000000000000000000000000000000000000000000000000000000* L000858 000000000000000000000000000000000000000000000000000000000000000000* L000924 000000000000000000000000000000000000000000000000000000000000000000* -L000990 111111111111111111101111111111111111111111111111111111111111111111* -L001056 000000000000000000000000000000000000000000000000000000000000000000* -L001122 000000000000000000000000000000000000000000000000000000000000000000* +L000990 111111111111111111111111011111111011111110011111111111011111111111* +L001056 111111111111111111110111101111111011111110011111111111101111111111* +L001122 111111111111111111111011011111111011111110011111111111111111111111* L001188 000000000000000000000000000000000000000000000000000000000000000000* L001254 000000000000000000000000000000000000000000000000000000000000000000* L001320 111111111111111111111111111111111111111111111111111111111111111111* -L001386 011111110111111111111011111111011111111111111111110111111111111111* -L001452 011111111111111111111111111111111111111111110111111111111111111111* +L001386 111111111111111111111110111111111111111110011111111111111111111111* +L001452 111111111111111111111111111111111111110101011011111111111111111111* L001518 000000000000000000000000000000000000000000000000000000000000000000* L001584 000000000000000000000000000000000000000000000000000000000000000000* L001650 000000000000000000000000000000000000000000000000000000000000000000* @@ -111,16 +110,16 @@ L002178 111111111111111111111111111111111111111111111111111111111111111111* L002244 111111111111111111111111111111111111111111111111111111111111111111* L002310 111111111111111111111111111111111111111111111111111111111111111111* L002376 111111111111111111111111111111111111111111111111111111111111111111* -L002442 011010110111110111111011111111111111110111111110111111101111101111* -L002508 011111110111111111111011111111111111110111101111111111111111011111* -L002574 011111110111111111111111111111111111011111111111111111111111111111* -L002640 011111111111111111111011111111111111011111111111111111111111111111* -L002706 011111110111111111111011111111111110110111111111111111111111011111* +L002442 111111111011110111111111111111111111111111011111111111111111011111* +L002508 111110111111111111101111111111111111111111011111111111111111111111* +L002574 000000000000000000000000000000000000000000000000000000000000000000* +L002640 000000000000000000000000000000000000000000000000000000000000000000* +L002706 000000000000000000000000000000000000000000000000000000000000000000* L002772 000000000000000000000000000000000000000000000000000000000000000000* -L002838 011111111111111111111111111111011111111111111111111111111111111111* -L002904 011111110111111111111011111111111111111111111011110111111111111111* -L002970 011111110111111111111011111111101111111111111111110111111111111111* +L002838 111111111111111111111101111111111111111110011111111111111111111111* +L002904 111111111111111111111111111111101111110101011111111111111111111111* +L002970 000000000000000000000000000000000000000000000000000000000000000000* L003036 000000000000000000000000000000000000000000000000000000000000000000* L003102 000000000000000000000000000000000000000000000000000000000000000000* L003168 111111111111111111111111111111111111111111111111111111111111111111* @@ -130,19 +129,19 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 011111011111111111111111111111111111111111111111111111111111111111* -L003630 011111110111111111111011111111011111111111110111110111111111111111* +L003564 111111111111111111111111111111111111011111011111111111111111111111* +L003630 011111011111111111111011111111111111111111011111111111011101111111* L003696 000000000000000000000000000000000000000000000000000000000000000000* L003762 000000000000000000000000000000000000000000000000000000000000000000* L003828 000000000000000000000000000000000000000000000000000000000000000000* -L003894 101111111111111111111111111111111111110111111111111111111111111111* -L003960 111010110111110111111011111111111111110111111110111111101111101111* -L004026 111111110111111111111011111111111111110111101111111111111111011111* -L004092 011111111011111111110111011111111111111011111111111111111111111111* -L004158 111111110111111111111011111111111110110111111111111111111111011111* +L003894 011111011111111111111011111111111111111111011111111111011111111111* +L003960 111111111111111111111111111111111111111111011111111111111101111111* +L004026 000000000000000000000000000000000000000000000000000000000000000000* +L004092 000000000000000000000000000000000000000000000000000000000000000000* +L004158 000000000000000000000000000000000000000000000000000000000000000000* L004224 000000000000000000000000000000000000000000000000000000000000000000* -L004290 111111111111111111111111111111111111111111111111111111111111111111* +L004290 111111111111111111111111111011111111111111011111111111111111111111* L004356 111111111111111111111111111111111111111111111111111111111111111111* L004422 111111111111111111111111111111111111111111111111111111111111111111* L004488 111111111111111111111111111111111111111111111111111111111111111111* @@ -154,18 +153,18 @@ L004818 111111111111111111111111111111111111111111111111111111111111111111* L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 011111111011111111110111111111111111011111111111111111111111111111* -L005082 011111111011111111111111111111111111101111111111011111111111111111* -L005148 011111111111111111110111111111111111101111111111011111111111111111* -L005214 000000000000000000000000000000000000000000000000000000000000000000* +L005016 111111111011110111111111111111111111111111011111111111111111011111* +L005082 111111111111111111111111111111111111111111011111011111011111111111* +L005148 111111111111111111111011111111111111111111011111011111111111111111* +L005214 111111111111111111111111111111111111111111011111011111111111011111* L005280 000000000000000000000000000000000000000000000000000000000000000000* -L005346 011111111011111111111111111111111111111111111111110111111111111111* -L005412 011111111111111111110111111111111111111111111111110111111111111111* -L005478 011111110111111111111011111111111111111111111111111011111111111111* -L005544 011111111111111111111111111111011111111111110111110111111111111111* +L005346 011111111111111111111111111111111111111111011111111111111111111111* +L005412 111111011111111111111011111111111111111111011111111111011110111111* +L005478 101111011111111111111011111111111111111111011111111111011111111111* +L005544 000000000000000000000000000000000000000000000000000000000000000000* L005610 000000000000000000000000000000000000000000000000000000000000000000* L005676 - 111111011110111111111111111111111111111110111111111111111111111111* + 111111111110111111111111111111111111011110111111111111111111111111* L005742 111111111111111111111111111111111111111111111111111111111111111111* L005808 111111111111111111111111111111111111111111111111111111111111111111* L005874 111111111111111111111111111111111111111111111111111111111111111111* @@ -181,32 +180,32 @@ L006402 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* L006538 01100011111000* -L006552 00100110010011* -L006566 10100110010101* +L006552 10100110010011* +L006566 11100110010101* L006580 11101011111111* L006594 00110011111000* -L006608 10100110010010* -L006622 00100110010001* +L006608 11100110010010* +L006622 11100110010001* L006636 11101011110011* L006650 10100110010000* -L006664 10100111010011* -L006678 11010011110001* -L006692 11111011110011* +L006664 10100110010011* +L006678 01010110010001* +L006692 11100011110011* L006706 10100110010000* -L006720 10100110010010* -L006734 11011111110101* -L006748 11110011111111* +L006720 00100110010010* +L006734 11011011110101* +L006748 11111111111111* NOTE BLOCK 1 * L006762 - 111111011111110111010101111111111111111111111111111111111111111111 - 111111111101011101111111011111111111111111111111111111111111111111 - 111111111011111111111111111111111111111111101101111111110111111111 + 111111011111111111011110111111111111111111111111111111111111111111 + 111101111101111111111111111110110111111111111111111111111111111111 + 111111111011111111111111111111101111111111101101111111110111111111 101111111111111111111111111111111111111111111111111111011111111111 - 111111111111111111111111111111111101111111111111111111111111111111 - 111110111111111111111111111111111111111011111111111111111111111111 - 111111111111111111111111111111111111011111111111111111111111111111 - 111111111111111111111111111011111111111110111111111111111111111111 - 111111111111111111111111111110111111111111111111101111111111111111* + 111111111111111111110111111111111111111111111111111011111111111111 + 111111111111101111111111111111111111111111111111111111111111111111 + 111111111111111110111111111111111111011111111111111111111111111111 + 111111111111111111111111111111111111111110111111111111111111111111 + 111111111111111111111111111111111111111111111111101111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* L007422 000000000000000000000000000000000000000000000000000000000000000000* @@ -214,7 +213,7 @@ L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* L007686 000000000000000000000000000000000000000000000000000000000000000000* -L007752 111111111111111111111111111101111111111111111111111111111111111111* +L007752 111111111111111101111111111111111111111111111111111111111111111111* L007818 000000000000000000000000000000000000000000000000000000000000000000* L007884 000000000000000000000000000000000000000000000000000000000000000000* L007950 000000000000000000000000000000000000000000000000000000000000000000* @@ -226,66 +225,66 @@ L008214 111111111111111111111111111111111111111111111111111111111111111111* L008280 111111111111111111111111111111111111111111111111111111111111111111* L008346 111111111111111111111111111111111111111111111111111111111111111111* L008412 111111111111111111111111111111111111111111111111111111111111111111* -L008478 011111111011110110111111111111111101111111011111011111111111111111* -L008544 101111111011111010111111111111111101111111011111011111111111111111* -L008610 011111111011110110111111111111111110111111101111011111111111111111* -L008676 101111111011111010111111111111111110111111101111011111111111111111* +L008478 011111111011111111010110111111111111111111011111011111111111111111* +L008544 101111111011111111011010111111111111111111011111011111111111111111* +L008610 011111111011111111100110111111111111111111101111011111111111111111* +L008676 101111111011111111101010111111111111111111101111011111111111111111* L008742 111111111011111111111111111111111111111111111111011111101111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 101111111111110111111111111111111111111111111111011111101111111111* -L008940 011111111111111011111111111111111111111111111111011111101111111111* -L009006 111111111111111111111111111111111101111111101111011111101111111111* -L009072 111111111111111111111111111111111110111111011111011111101111111111* -L009138 111111111111111110111111111111111111111111111111011111101111111111* -L009204 101111111011111010111111111111111101111111011111011111111111111111* -L009270 101111111011111010111111111111111110111111101111011111111111111111* -L009336 101111110111111001111111111111111110111111101111011111111111111111* -L009402 101111110111111001111111111111111101111111011111011111111111111111* +L008874 101111111111111111110111111111111111111111111111011111101111111111* +L008940 011111111111111111111011111111111111111111111111011111101111111111* +L009006 111111111111111111011111111111111111111111101111011111101111111111* +L009072 111111111111111111101111111111111111111111011111011111101111111111* +L009138 111111111111111111111110111111111111111111111111011111101111111111* +L009204 101111111011111111011010111111111111111111011111011111111111111111* +L009270 101111111011111111101010111111111111111111101111011111111111111111* +L009336 101111110111111111101001111111111111111111101111011111111111111111* +L009402 101111110111111111011001111111111111111111011111011111111111111111* L009468 101111111111111111111111111111111111111111111111011111111011111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111111111111011111111111111111111111111111111011111111011111111* -L009666 111111111111111111111111111111111101111111101111011111111011111111* -L009732 111111111111111111111111111111111110111111011111011111111011111111* -L009798 111111111011111101111111111111111111111111111111011111111011111111* -L009864 111111110111111110111111111111111111111111111111011111111011111111* -L009930 111111111111111111111111110111111111111111111101011111111111111111* -L009996 111111111111111111111011111111111111111111111101011111111111111111* -L010062 111101111101111111101110111011111111111111111110011111111111111111* -L010128 000000000000000000000000000000000000000000000000000000000000000000* -L010194 000000000000000000000000000000000000000000000000000000000000000000* +L009600 111111111111111111111011111111111111111111111111011111111011111111* +L009666 111111111111111111011111111111111111111111101111011111111011111111* +L009732 111111111111111111101111111111111111111111011111011111111011111111* +L009798 111111111011111111111101111111111111111111111111011111111011111111* +L009864 111111110111111111111110111111111111111111111111011111111011111111* +L009930 111111111111111111111111111111111111111111111111111111111111111111* +L009996 111111111111111111111111111111111111111111111111111111111111111111* +L010062 111111111111111111111111111111111111111111111111111111111111111111* +L010128 111111111111111111111111111111111111111111111111111111111111111111* +L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 111111111110111111111111111111111111011110111111111111111111111111* L010326 000000000000000000000000000000000000000000000000000000000000000000* -L010392 111111111111111111111111111111111111111111111111111111111111111111* -L010458 111111111111111111111111111111111111111111111111111111111111111111* -L010524 111111111111111111111111111111111111111111111111111111111111111111* -L010590 111111111111111111111111111111111111111111111111111111111111111111* -L010656 011111111011110110111111111111111110111111101111011111111111111111* -L010722 101111111011111010111111111111111110111111101111011111111111111111* -L010788 011111110111110101111111111111111110111111101111011111111111111111* -L010854 101111110111111001111111111111111110111111101111011111111111111111* -L010920 111111111111101111111111111111111111111111101111011111111111111111* +L010392 111111111111111111111111111111111111111111111111101111111111111111* +L010458 111111111111111111111111111111111111111111111101111011111111111111* +L010524 111111111111101111111111111101101111111111111111110111111111111111* +L010590 000000000000000000000000000000000000000000000000000000000000000000* +L010656 011111111011111111100110111111111111111111101111011111111111111111* +L010722 101111111011111111101010111111111111111111101111011111111111111111* +L010788 011111110111111111100101111111111111111111101111011111111111111111* +L010854 101111110111111111101001111111111111111111101111011111111111111111* +L010920 111111111111111111111111111111111011111111101111011111111111111111* L010986 111111111110111111111111111111111111011110111111111111111111111111* -L011052 101111111111100111111111111111111111111111111111011111111111111111* -L011118 011111111111101011111111111111111111111111111111011111111111111111* -L011184 111111111111101111111111111111111110111111111111011111111111111111* -L011250 111111111011101101111111111111111111111111111111011111111111111111* -L011316 111111110111101110111111111111111111111111111111011111111111111111* -L011382 111111111111111111111111011011111111111111111111111111111111111111* -L011448 111111111111111111110111011111111111111111111111111111111111111111* -L011514 111111111111111111111011100111111111111111111111111111111111111111* -L011580 000000000000000000000000000000000000000000000000000000000000000000* -L011646 000000000000000000000000000000000000000000000000000000000000000000* +L011052 101111111111111111110111111111111011111111111111011111111111111111* +L011118 011111111111111111111011111111111011111111111111011111111111111111* +L011184 111111111111111111101111111111111011111111111111011111111111111111* +L011250 111111111011111111111101111111111011111111111111011111111111111111* +L011316 111111110111111111111110111111111011111111111111011111111111111111* +L011382 111111111111111111111111111111111111111111111111111111111111111111* +L011448 111111111111111111111111111111111111111111111111111111111111111111* +L011514 111111111111111111111111111111111111111111111111111111111111111111* +L011580 111111111111111111111111111111111111111111111111111111111111111111* +L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 111111111110111111111111111111111111011110111111111111111111111111* L011778 000000000000000000000000000000000000000000000000000000000000000000* -L011844 111111111111111111111111111111111111111111111111111111111111111111* -L011910 111111111111111111111111111111111111111111111111111111111111111111* -L011976 111111111111111111111111111111111111111111111111111111111111111111* -L012042 111111111111111111111111111111111111111111111111111111111111111111* +L011844 111110111111111111111111111111111111111111111111011011111111111111* +L011910 111111111111111111111111111111101111111111111111010111111111111111* +L011976 000000000000000000000000000000000000000000000000000000000000000000* +L012042 000000000000000000000000000000000000000000000000000000000000000000* L012108 111111011111111111111111111111111111111111111111111111111111111111* L012174 111111111111111111111111111111111111111111111111111111111111111111* L012240 111111111111111111111111111111111111111111111111111111111111111111* @@ -293,11 +292,11 @@ L012306 111111111111111111111111111111111111111111111111111111111111111111* L012372 111111111111111111111111111111111111111111111111111111111111111111* L012438 111111111111111111111111111111111111101111111111111111111111111111* -L012504 111111111111111111010111111011111111110111111111011111111111111111* -L012570 111111111111111111011111111111111111111111111111011111111111111111* -L012636 111101111101111111101110111011111111111011111111011111111111111111* -L012702 111101111101111111101010111011111111111111111111011111111111111111* -L012768 000000000000000000000000000000000000000000000000000000000000000000* +L012504 111111111111111111111111111111111111111111101111011111111111111111* +L012570 111111111111111111111111111111111111111111111111111111111111111111* +L012636 111111111111111111111111111111111111111111111111111111111111111111* +L012702 111111111111111111111111111111111111111111111111111111111111111111* +L012768 111111111111111111111111111111111111111111111111111111111111111111* L012834 111111111111111111111111111111111111111111111111111111111111111111* L012900 111111111111111111111111111111111111111111111111111111111111111111* L012966 111111111111111111111111111111111111111111111111111111111111111111* @@ -314,43 +313,43 @@ L013342 11011111111111* L013356 11100110011000* L013370 11100110011111* L013384 10110110011100* -L013398 11111011111110* -L013412 00110011110000* +L013398 11101011111110* +L013412 00000011110000* L013426 11100110010011* -L013440 10110110010111* -L013454 11111011110011* -L013468 00111111110000* +L013440 11110110010111* +L013454 11101011110011* +L013468 00001111110000* L013482 00000110010010* -L013496 00100110010011* +L013496 01010110010011* L013510 11100011111111* NOTE BLOCK 2 * L013524 - 111111111011111111011111111111111111111111111111111111111111011011 - 111111111101111111111111110111111111111111111111111111111111111111 - 111111111111101111111111111111111111011111111011111111111111111111 - 101001111111111111111111111111111111111111111110111111101111111110 + 111111111111111111110101111111111111011111111111111111111111111111 + 111111011101111111111111101111111111111111111111111101111111111111 + 111111111111111111011111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111110111111111111111111110 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111111111111111111111111111111111 - 111111011111111111111101111111111001111111111111011111111111111111 - 111111111111111101111111111110111111111110111111111111111111111111 - 111111111111111111111111111111111111111111101111111110111111111111* + 111111111111111101111111111111111111111111011111110111111111111111 + 111101111111110111111111111101011111111111111111111111111111011111 + 111111110111111111111111111011111111111110111111111111111111111111 + 100111111111111111111111111111110110111111111111111111111011111111* L014118 - 111111011110111111111111111111111111111110111111111111111111111111* + 111111111110111111111111111111111111111110111111111111111111011111* L014184 000000000000000000000000000000000000000000000000000000000000000000* L014250 000000000000000000000000000000000000000000000000000000000000000000* L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 111111111111111111111111111111111111111110111111111111111111111011* +L014514 111111111111111111111111111111101111111110111111111111111111111111* L014580 000000000000000000000000000000000000000000000000000000000000000000* L014646 000000000000000000000000000000000000000000000000000000000000000000* L014712 000000000000000000000000000000000000000000000000000000000000000000* L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 - 111111011110111111111111111111111111111110111111111111111111111111* -L014910 111111111111111111111111111110111111111101011111111111111111111111* -L014976 111110111111111111111111111111111111111101011111111111111111111111* -L015042 111111111111111110111111111111111111111110011111101111111111111111* + 111111111110111111111111111111111111111110111111111111111111011111* +L014910 011111111111111111111111110111111111111111110111111111111111111111* +L014976 011111111111111111111011111111111111111111110111111111111111111111* +L015042 011111110111111111111011110111111111111111111111111111111111111111* L015108 000000000000000000000000000000000000000000000000000000000000000000* L015174 000000000000000000000000000000000000000000000000000000000000000000* L015240 111111111111111111111111111111111111111111111111111111111111111111* @@ -359,7 +358,7 @@ L015372 111111111111111111111111111111111111111111111111111111111111111111* L015438 111111111111111111111111111111111111111111111111111111111111111111* L015504 111111111111111111111111111111111111111111111111111111111111111111* L015570 - 111111011110111111111111111111111111111110111111111111111111111111* + 111111111110111111111111111111111111111110111111111111111111011111* L015636 000000000000000000000000000000000000000000000000000000000000000000* L015702 111111111111111111111111111111111111111111111111111111111111111111* L015768 111111111111111111111111111111111111111111111111111111111111111111* @@ -371,36 +370,36 @@ L016098 111111111111111111111111111111111111111111111111111111111111111111* L016164 111111111111111111111111111111111111111111111111111111111111111111* L016230 111111111111111111111111111111111111111111111111111111111111111111* L016296 - 111111011110111111111111111111111111111110111111111111111111111111* -L016362 111111111011111110111111111011111111111110011110111110111111111101* -L016428 111111111011111110111111111011111111111110011101111110111111111110* -L016494 111111111111111110111111111111111111011110011110111110111111111101* -L016560 111111111111111110111111111111111111011110011101111110111111111110* -L016626 111111111011111111111111111011111111111110011110101110111111111101* -L016692 111111111011111111111111111011111111111110011101101110111111111110* -L016758 111111111111111111111111111111111111011110011110101110111111111101* -L016824 111111111111111111111111111111111111011110011101101110111111111110* -L016890 000000000000000000000000000000000000000000000000000000000000000000* -L016956 000000000000000000000000000000000000000000000000000000000000000000* + 111111111110111111111111111111111111111110111111111111111111011111* +L016362 011011111111111110111011100111111011111111011111111101111111111110* +L016428 011111111111111101111011110111111111101111111111111101111111111111* +L016494 011111111111111111011111110111111111111111111111111111111111111111* +L016560 011111111111111111011011111111111111111111111111111111111111111111* +L016626 011111111111111111111011110111111110111111111111111101111111111111* +L016692 111111111111111111111111111111111111111111111111111111111111111111* +L016758 111111111111111111111111111111111111111111111111111111111111111111* +L016824 111111111111111111111111111111111111111111111111111111111111111111* +L016890 111111111111111111111111111111111111111111111111111111111111111111* +L016956 111111111111111111111111111111111111111111111111111111111111111111* L017022 - 111111011110111111111111111111111111111110111111111111111111111111* + 111111111110111111111111111111111111111110111111111111111111011111* L017088 000000000000000000000000000000000000000000000000000000000000000000* L017154 111111111111111111111111111111111111111111111111111111111111111111* L017220 111111111111111111111111111111111111111111111111111111111111111111* L017286 111111111111111111111111111111111111111111111111111111111111111111* L017352 111111111111111111111111111111111111111111111111111111111111111111* -L017418 111111111111111111111111111111111111111111101111111111111111111111* -L017484 111111111111111111111111111111111111111101111111111111111111111111* -L017550 111111111011111111111111110111111111111111111111111111111111111111* -L017616 111111111111111111111111111111111111111111111101111111111111111101* -L017682 111111111111111111111111111111111111111111111110111111111111111110* +L017418 011111011111111111111111111011111111111111111111111111111111111111* +L017484 011111011111111111110111111111111111111111111111111111111111111111* +L017550 011111101111111111111011110111111111111111111111111111111111111111* +L017616 011101011111111111111111111111111111111111111111110111111111111111* +L017682 000000000000000000000000000000000000000000000000000000000000000000* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 111111111111111111111111111111111111111111011011111111111111111111* -L017880 111111111111111111111111111111111111111111111111111101111111111111* -L017946 111111111111111101111111111111111111111111111111011111111111111111* -L018012 000000000000000000000000000000000000000000000000000000000000000000* -L018078 000000000000000000000000000000000000000000000000000000000000000000* +L017814 101111111111111111111111111111111111111111111111111101111111111111* +L017880 111011111111111110111011100111111011111111011111111101111111111110* +L017946 111111111111111101111011110111111111101111111111111101111111111111* +L018012 011111111111111111110111111011111111111111110111111110111111111111* +L018078 111111111111111111111011110111111110111111111111111101111111111111* L018144 111111111111111111111111111111111111111111111111111111111111111111* L018210 111111111111111111111111111111111111111111111111111111111111111111* L018276 111111111111111111111111111111111111111111111111111111111111111111* @@ -409,18 +408,18 @@ L018408 111111111111111111111111111111111111111111111111111111111111111111* L018474 000000000000000000000000000000000000000000000000000000000000000000* L018540 000000000000000000000000000000000000000000000000000000000000000000* -L018606 111111111111111111111111111111111111111111101111111111111111111111* -L018672 111111111111111111111111111111110111111111111111111111111111111111* -L018738 111111111110111111111111111111111111111111111111111111111111011111* -L018804 110111111111011111111110101111111110111111111111111111011111011111* -L018870 111111111111111111111111111111111111111110111111111111111111011111* -L018936 111111111111111111111111111110111111111111111111111111111111011111* -L019002 111111111111111111011111111111111111111111111111111111111111011111* -L019068 000000000000000000000000000000000000000000000000000000000000000000* +L018606 111111111111111111111111111111111111111111111111111111111111111111* +L018672 111111111111111111111111111111111111111111111111111111111111111111* +L018738 111111111111111111111111111111111111111111111111111111111111111111* +L018804 111111111111111111111111111111111111111111111111111111111111111111* +L018870 011111111111111111111101111111111111111111111111111111110111111111* +L018936 011111111111111011111101111111111111111111111111111111111111111111* +L019002 011111111111111111010111111011111111111111111111111111111111111111* +L019068 011111111111111111011101111111111111111111111111111111111111111111* L019134 000000000000000000000000000000000000000000000000000000000000000000* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 101111111111111111111111111111111111111111011111111111111111111111* +L019266 011111111111111111111111111110111111111111111111111111111111111111* L019332 111111111111111111111111111111111111111111111111111111111111111111* L019398 111111111111111111111111111111111111111111111111111111111111111111* L019464 111111111111111111111111111111111111111111111111111111111111111111* @@ -436,47 +435,47 @@ L019926 L020058 0010* L020062 00100011110000* L020076 01101111110011* -L020090 11100110011100* +L020090 10100110011100* L020104 11101111110010* L020118 00111011110000* L020132 00000011110011* L020146 10100110010110* -L020160 11110011110010* +L020160 11100011110010* L020174 00111111110001* L020188 10100110010011* -L020202 01110110011110* +L020202 10100111011110* L020216 11100011111111* -L020230 00011011111001* +L020230 00111011111001* L020244 10100110010011* L020258 01010110010000* L020272 11101111111111* NOTE BLOCK 3 * L020286 - 111111111111111111100101111111111111111111111111111111111111111111 - 111111110101111111111111101111111111111111111111011011111111111111 - 111101101111111111111111111111111111101111111110111111111111111110 - 111111111111111111111111111110111111111111111111111111111111111111 - 111111111111111111111111111111101111111111111111111111111111111111 - 111111111111111111111111111111111111111101111111111111111101111111 - 111111111111110110111111111111111111111111111111111111111111011111 - 101111111111111111111111111011110111111111111111111111111111111111 - 110111111111111111111111111111111101111111101111111111110111111111* + 111011111111111111111111111111111111111111111111111111110111111111 + 111111110101111111111111011111111111111111111111111111101111111111 + 111111111111111111111101111111111111111111111111111111111111111111 + 101111111111111111111011111111111111111111111111111111111111111110 + 111111111111111111111111111111111111111111111111111111111111111011 + 111111111111111101111111111111111111111111111111111111111101111111 + 111111111111111111111111111111111111111111111111110111111111011111 + 111111111111111011111111111011110111111110111111111111111111111111 + 111101011111111111111111111110111111011111100111111111111111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111011111111111111111111111111111111111111101111111111111111111111* -L021012 111011111111111011110111101011111111111111111110101111111111111111* -L021078 110111111111111011111011010111101111111111011110011111111111111111* +L020946 111111111111111111111111111111111111101111101111111111111111111111* +L021012 111111101111111111111111111011111111101111111111111111100110111110* +L021078 111111101111111110111111110111111111011111011111111111011010111101* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111111001111101110111111111111111111111011111111111111111111111* -L021342 111111111011111111111111111111111110111111011111111111111111111111* +L021276 111111111001110111111111111111111111111111011111111111110111111111* +L021342 111110111011111111111111111111111111111111011111111111111111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111111111111110111111111111111111111111011111111111111011111111* -L021738 111101111111111111110111111011111111111111011111111111111111111111* +L021672 111111011111111111111111111111111111111111111111111111111111111111* +L021738 111111111111111111111111110111111111111111111111111111011011111101* L021804 000000000000000000000000000000000000000000000000000000000000000000* L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* @@ -487,8 +486,8 @@ L022200 111111111111111111111111111111111111111111111111111111111111111111* L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 011111111111111111111101111111111111111111111111111111111111111111* -L022464 101111111111111111111111111111111111111111111111111111111111111101* +L022398 111111111111111111110111111111111111111101111111111111111111111111* +L022464 111111111111111111111111111111111111111110110111111111111111111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* @@ -498,10 +497,10 @@ L022860 111111111111111111111111111111111111111111111111111111111111111111* L022926 111111111111111111111111111111111111111111111111111111111111111111* L022992 111111111111111111111111111111111111111111111111111111111111111111* L023058 - 011111111111111111111111111111111111111111111111111111111111011111* -L023124 111111111111111110111111111111110111111111011111111111111111111111* -L023190 111111111111111111010111111011111111111111011111111111111111111111* -L023256 111101111111111111110111111011111111111111011111110111111111111111* + 111111111111111111111111111111111111111101111111111111111111011111* +L023124 111111111111111111111111111011111111111111011111111111110111110111* +L023190 111111111111111111111111111011110111111111011111111111111111111111* +L023256 111111111111111111111111111111110111111111011111111111110111111111* L023322 000000000000000000000000000000000000000000000000000000000000000000* L023388 000000000000000000000000000000000000000000000000000000000000000000* L023454 111111111111111111111111111111111111111111111111111111111111111111* @@ -510,24 +509,24 @@ L023586 111111111111111111111111111111111111111111111111111111111111111111* L023652 111111111111111111111111111111111111111111111111111111111111111111* L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 011111111111111111111111111111111111111111111111111111111111011111* -L023850 111111111111111111111111111111110111111110111111111111111111111111* + 111111111111111111111111111111111111111101111111111111111111011111* +L023850 110111111111111111111111101111111111111111111111111111111111111111* L023916 111111111111111111111111111111111111111111111111111111111111111111* L023982 111111111111111111111111111111111111111111111111111111111111111111* L024048 111111111111111111111111111111111111111111111111111111111111111111* L024114 111111111111111111111111111111111111111111111111111111111111111111* -L024180 111111111111110111111111111111111111111111111110101111111111111111* -L024246 111111111111110111111111111011111111111111111111111111111111111111* -L024312 111111111111110111110111111111111111111111111111111111111111111111* -L024378 111111111111111111111011010111111111111111111101011111111111111111* -L024444 000000000000000000000000000000000000000000000000000000000000000000* +L024180 111111111111111111111111111101111111111111111111111111111111111111* +L024246 111111111111111111111111111111111111111111111111111111111111111111* +L024312 111111111111111111111111111111111111111111111111111111111111111111* +L024378 111111111111111111111111111111111111111111111111111111111111111111* +L024444 111111111111111111111111111111111111111111111111111111111111111111* L024510 000000000000000000000000000000000000000000000000000000000000000000* -L024576 111110111111111111111111111111111111111110011111111111111111111111* -L024642 111101111111111111111111111111111111101111011111111111111111111111* -L024708 000000000000000000000000000000000000000000000000000000000000000000* -L024774 000000000000000000000000000000000000000000000000000000000000000000* -L024840 000000000000000000000000000000000000000000000000000000000000000000* +L024576 111111111111111111111111111111111111111111111111110111111111111111* +L024642 111111111111111111111111111111111111111111111111111111111111111111* +L024708 111111111111111111111111111111111111111111111111111111111111111111* +L024774 111111111111111111111111111111111111111111111111111111111111111111* +L024840 111111111111111111111111111111111111111111111111111111111111111111* L024906 111111111111111111111111111111111111111111111111111111111111111111* L024972 111111111111111111111111111111111111111111111111111111111111111111* L025038 111111111111111111111111111111111111111111111111111111111111111111* @@ -535,19 +534,19 @@ L025104 111111111111111111111111111111111111111111111111111111111111111111* L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111111111111111111110110111111111111111111111111111111111* +L025302 110111111111111111111110111111111111111111111111111111111111111111* L025368 111111111111111111111111111111111111111111111111111111111111111111* L025434 111111111111111111111111111111111111111111111111111111111111111111* L025500 111111111111111111111111111111111111111111111111111111111111111111* L025566 111111111111111111111111111111111111111111111111111111111111111111* -L025632 111101111111111111110111111011111111111111011111111111111111111111* -L025698 111111111111111111111111111011111111111111011111111111111101111111* -L025764 111111111111111111110111111111111111111111011111111111111101111111* -L025830 000000000000000000000000000000000000000000000000000000000000000000* +L025632 111111101111111111111111111111111111111111111111111111101101111111* +L025698 111111111111111111111111111011111111111111111111111111111101111111* +L025764 111111111111111111111111111111111111111111111111111111110101111111* +L025830 111111011111111111111111110111111111111111111111111111011011111101* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111101111111111111111111111111111111111011111111111111111111111* +L026028 101111111111111111111111111111111111111111011111111111111111111111* L026094 111111111111111111111111111111111111111111111111111111111111111111* L026160 111111111111111111111111111111111111111111111111111111111111111111* L026226 111111111111111111111111111111111111111111111111111111111111111111* @@ -563,15 +562,15 @@ L026688 L026820 0010* L026824 10100111010000* L026838 11100110011110* -L026852 11100110010100* +L026852 00100110010100* L026866 11100011111111* L026880 10101111111001* L026894 00001011111111* L026908 10100110010100* L026922 11101011110011* L026936 01110011110010* -L026950 10100110010010* -L026964 11100110010001* +L026950 00000110010010* +L026964 00010110010001* L026978 11101011110011* L026992 01111111111010* L027006 10100110011110* @@ -580,28 +579,28 @@ L027034 11100011110011* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111011111110111110111111111 - 111111110101111111111111111111111111111111110111101111111111111111 - 111011111111111111111101111011111101111111111111111111111111111111 - 111111111111110111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111011111111111111111111111111111 - 111111111111101111111111111110111011111111111111111101111111010111 - 111111111111111111111111111111011111111010111111111111101101111111 - 101110011111111101101111111111111111111111111111111111111111111110* + 111111111111111111111111111111011111110111111111110111111111111111 + 111111111111111111111111110111111111111101110111101111111111111111 + 111011111111111111011111111111111111111111011111111111101111111111 + 111111111111111111111011111101111111111111111111111111111111111111 + 111111110111111111111111011111111111111111111111111111111111111111 + 111110111111011111111111111111111101111111111111111111111011011111 + 101111011101111011111111111111111111111111111111111110111111111110 + 111111111111111101111110111111111011101111111111111111111111111111* L027642 - 110111111111111101111111100111111111011011111111011110111111111011* + 110111110111101101111111101111111110111111111111011111011111111110* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 111110111111011111111111111111111111111110101111111111111111111111* -L028104 111111111111101111111111111111111111111101111111111111111111111111* +L028038 101111111111111111111111111111101011111111111111111111110111111111* +L028104 011111111111111111111111111111111111111111111111111111111011111111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 111111111111111111111111111111111111111101111111111111111111011111* + 011111111111111111111111111111111111111111111111111111111111011111* L028434 111111111111111111111111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* @@ -614,16 +613,16 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111101111111111111111111111111111111011111111111111111111111111* +L029160 111111111111111111111011111111111111111111111111111111111111111110* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 011111111111111111111111111111111111111110111111111111111111111111* -L029556 111111111111111111111111111111111111111111111111111111111111111111* -L029622 111111111111111111111111111111111111111111111111111111111111111111* -L029688 111111111111111111111111111111111111111111111111111111111111111111* -L029754 111111111111111111111111111111111111111111111111111111111111111111* +L029490 111111111111111111111111111111011111111111111111111111111111111111* +L029556 111111011101111011101101111010111111011010101011111011111111111111* +L029622 000000000000000000000000000000000000000000000000000000000000000000* +L029688 000000000000000000000000000000000000000000000000000000000000000000* +L029754 000000000000000000000000000000000000000000000000000000000000000000* L029820 000000000000000000000000000000000000000000000000000000000000000000* L029886 111111111111111111111111111111111111111111111111111111111111111111* @@ -638,16 +637,16 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 011111111111111111111111111111111111111011111111111111111111111111* +L030612 111101111111111111111111111111111111111111111111111111111111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111111111010111011011110111111011010111111111011111011111001111101* -L031008 111111111111111111111111111111111111111111011111111111111111111111* -L031074 000000000000000000000000000000000000000000000000000000000000000000* -L031140 000000000000000000000000000000000000000000000000000000000000000000* -L031206 000000000000000000000000000000000000000000000000000000000000000000* +L030942 111110111111111111111111111111111111111111111111111111111111111111* +L031008 111111111111111111111111111111111111111111111111111111111111111111* +L031074 111111111111111111111111111111111111111111111111111111111111111111* +L031140 111111111111111111111111111111111111111111111111111111111111111111* +L031206 111111111111111111111111111111111111111111111111111111111111111111* L031272 000000000000000000000000000000000000000000000000000000000000000000* L031338 111111111111111111111111111111111111111111111111111111111111111111* @@ -661,13 +660,13 @@ L031800 111111111111111111111111111111111111111111111111111111111111111111* L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 - 111111111111111111111111111101111111111111111111111111111111111111* -L032064 111111111010111011011110111111011010111111111011111011111001111101* + 111111111111111111111111111111111111111111111111111101111111111111* +L032064 111111011101111011101101111010111111011010101011111011111111111111* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* L032328 111111111111111111111111111111111111111111111111111111111111111111* -L032394 111111111111111111111111111111111111111111111111111111011111111111* +L032394 111111111111111111111111111111111111111111111111111111111111111111* L032460 111111111111111111111111111111111111111111111111111111111111111111* L032526 111111111111111111111111111111111111111111111111111111111111111111* L032592 111111111111111111111111111111111111111111111111111111111111111111* @@ -692,41 +691,41 @@ L033586 00100011110000* L033600 10101111110011* L033614 11011011110100* L033628 11110011110010* -L033642 01111111111001* -L033656 01000110011111* +L033642 01110111111001* +L033656 10100011111111* L033670 11010111110000* L033684 11110011111111* -L033698 01110110010000* -L033712 10100111111110* -L033726 11011111110000* -L033740 11110011111111* -L033754 00111011110001* -L033768 00000110011111* -L033782 11010111111100* +L033698 00110110010001* +L033712 00000110011111* +L033726 11010111110000* +L033740 11111111111111* +L033754 00110011110001* +L033768 11001011111111* +L033782 11110111111100* L033796 11111111111111* NOTE BLOCK 5 * L033810 - 111011111011111111111111111111111111111111111111111111111111111111 - 111111111111111111111111110111111110111111111111111111111111111111 - 111110111111111111011101111111101111111111111111111111111111111111 - 111111111111111111111111111110111111111111111010111111111111111111 - 111111101110111111111111111111111111111111111111111111111111111111 - 111111111111101111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111101111011111111111111111 - 111111111111111101111111111111111111111110111111111110111111111111 - 101111111111111111110111111111111011111111111111111111111111111111* + 111011111111111111111111111111111111111111011111111111111111111111 + 111111111101111110111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111110111111101111111111111111 + 111111111111111111111111101010111111111111110111111111111111111111 + 111111111111111111111011111111111111111111111111111111111111111011 + 111101111111011111011111111111111111111011111111111111111111111111 + 111111111111111111111101111111111101111111111111110111111111111111 + 111111111011111011111111111111111111111111111110111111111111111110 + 101111111111111111111111111111111111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 101111111111111111111111111111111111111111111111111111111111111111* -L034536 111111111111111111111111111111111111111101111111111111111111111111* -L034602 111111111111111111111111111111111111111111110101111111111111111111* -L034668 111111111111111111111111111111111111111111111010111111111111111111* -L034734 111111111111111111111111111111110111111111111111111111111111111111* -L034800 011111111111111111111011111111111111111111111111111111111111111111* -L034866 111111111111111101111111111111111111111111111111011111111111111111* -L034932 111111111001111111111111111111111111111111101111111111111111111111* -L034998 111111110111111111011111110111111111111111101111111111111111111111* -L035064 111111111101111111101111111111111111111111101111111111111111111111* +L034470 011111110111111111111111111111111111111111111111111111111111110111* +L034536 011111111111111111111111111111111111111111101111111111111111110111* +L034602 011101111101111111111111111110111111111110111111111011111111111011* +L034668 000000000000000000000000000000000000000000000000000000000000000000* +L034734 000000000000000000000000000000000000000000000000000000000000000000* +L034800 011111111011111111111111111111111111111111011111111111111111110111* +L034866 011111111111111111111011111111111111111111111111111111111111111110* +L034932 000000000000000000000000000000000000000000000000000000000000000000* +L034998 000000000000000000000000000000000000000000000000000000000000000000* +L035064 000000000000000000000000000000000000000000000000000000000000000000* L035130 000000000000000000000000000000000000000000000000000000000000000000* L035196 111111111111111111111111111111111111111111111111111111111111111111* @@ -741,16 +740,16 @@ L035724 111111111111111111111111111111111111111111111111111111111111111111* L035790 111111111111111111111111111111111111111111111111111111111111111111* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 101111111111111111111111111111111111111111111111111111111111111111* -L035988 111111111111111111111110111101111111111111111111111111111111111111* -L036054 111111111111101111111101111111101101111111111111111111111111111111* -L036120 000000000000000000000000000000000000000000000000000000000000000000* -L036186 000000000000000000000000000000000000000000000000000000000000000000* -L036252 111111111111111111111111111111111111111111111111111111111111111111* -L036318 111111111111111111111111111111111111111111111111111111111111111111* -L036384 111111111111111111111111111111111111111111111111111111111111111111* -L036450 111111111111111111111111111111111111111111111111111111111111111111* -L036516 111111111111111111111111111111111111111111111111111111111111111111* +L035922 011111111111111111111111111110111111111111111111111111111111111110* +L035988 011111111101111011111111101111111111110110111101111111111111111110* +L036054 011111111101011011111111111111111111110110111101111111111111111110* +L036120 011111111101111011111111111111111101110110111101111111111111111110* +L036186 011111111101111011111111111011111111110110111101111111111111111110* +L036252 011111111101111011111101111111111111110110111101111111111111111110* +L036318 011111111101111011111111111111111111110110111101101111111111111110* +L036384 000000000000000000000000000000000000000000000000000000000000000000* +L036450 000000000000000000000000000000000000000000000000000000000000000000* +L036516 000000000000000000000000000000000000000000000000000000000000000000* L036582 000000000000000000000000000000000000000000000000000000000000000000* L036648 111111111111111111111111111111111111111111111111111111111111111111* @@ -765,10 +764,10 @@ L037176 111111111111111111111111111111111111111111111111111111111111111111* L037242 111111111111111111111111111111111111111111111111111111111111111111* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 011111101111111111111111111111111111111110111111111111111111111111* -L037440 011110111111111111111111111111111111111101111111111101111111111111* -L037506 000000000000000000000000000000000000000000000000000000000000000000* -L037572 000000000000000000000000000000000000000000000000000000000000000000* +L037374 011101111001111111011111111110111111111110011111111011111111111111* +L037440 101111111111111111111111111111111111111101111111111111111111111111* +L037506 011111111011111111011111111111111111111101011111111111111111111111* +L037572 011101111101111111111111111110111111111110111111111011111111111111* L037638 000000000000000000000000000000000000000000000000000000000000000000* L037704 111111111111111111111111111111111111111111111111111111111111111111* L037770 111111111111111111111111111111111111111111111111111111111111111111* @@ -789,9 +788,9 @@ L038628 111111111111111111111111111111111111111111111111111111111111111111* L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 011111011111111111111111111111111111111110111111111111111111111111* -L038892 011011111111111111111111111111111111111101111111111101111111111111* -L038958 000000000000000000000000000000000000000000000000000000000000000000* +L038826 011111111011111111111111111111111111111111010111111111111111111111* +L038892 010111111111111111111111111111111111111111111111111111111111111110* +L038958 011111111011111101111111111111111111111111011111111111111111110111* L039024 000000000000000000000000000000000000000000000000000000000000000000* L039090 000000000000000000000000000000000000000000000000000000000000000000* L039156 111111111111111111111111111111111111111111111111111111111111111111* @@ -816,49 +815,49 @@ L040212 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* L040348 10100110011110* -L040362 01110110010010* +L040362 11100110010010* L040376 11011111111110* L040390 11111011110011* -L040404 10100110011110* -L040418 11001011110010* +L040404 11100110011110* +L040418 11111011110010* L040432 11110011111111* L040446 11111111110011* -L040460 11100110011110* +L040460 00100111011110* L040474 11001011110010* L040488 11111111111111* L040502 11110011111111* -L040516 11100110011110* +L040516 10100110011110* L040530 11001011111111* L040544 11110111111110* L040558 11111111111110* NOTE BLOCK 6 * L040572 - 111111111111111111110110101111111111111111111111111111111111111111 - 111111111101111111111111111111111111111111111011011111101111111111 - 111111111111111111111111111011111111111111111110111111111111111111 - 111101111111111111111111111111111111111111111111111111111111111010 + 111111111011111011111111101111111111111111011111111111111111111111 + 111111111101111111111111111111111111111111111111111111101011111111 + 111111111111111111111011111111111111111111111010111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111010 111111111111111111111111111111111110111111111111111111111111111111 - 110111111111111111111111111111111111111111111111111111111111111111 - 011111111111100111111111111111111111011111111111111111111111111111 - 111111101011111101111111111111111111111110111111111111111111111111 - 111111111111111111011111111110111011111111101111111111111111111111* + 110111111111111111111111111111111111111011111111111111111111111111 + 111111111111101111111111111111111011011111111111011111111111111111 + 111111111111111101111111111011111111111110111111111111111111111111 + 101110011111111111011111111111111111111111111111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 111111011111111111111111111111111110111101011111111111111111111111* -L041298 111111111111101111111111111111111111111110011111111111111111111111* +L041232 011111111111111111111111111111111110110101111111111111111111111111* +L041298 011111111111101111111111111111111111111110111111111111111111111111* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111111111111111111111111111101111111111111111111111111111111111111* -L041628 000000000000000000000000000000000000000000000000000000000000000000* -L041694 000000000000000000000000000000000000000000000000000000000000000000* -L041760 000000000000000000000000000000000000000000000000000000000000000000* -L041826 000000000000000000000000000000000000000000000000000000000000000000* +L041562 111111111111111111111111111111110111111111111111111111111111111111* +L041628 101111111111111111111111111111111111111111111111111111111111111111* +L041694 111111111111111111111111111111111111111101111111111111111111111111* +L041760 111111111011111111111111111111111111111111111111111111111111110111* +L041826 111111111111111111011111111111111111111111111111111111110111111111* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111111110111111111111111111111111011111110011111111111111111110111* -L042024 111111111011111111110111111111111011111110011111111111111111111011* -L042090 111111111111111111111011111111111011111110011111111111111111110111* +L041958 111111111111111111101111111111111111111111111111111111111011111111* +L042024 111101111111111111111111111111111111111111111111111111111111111111* +L042090 111111111111111101111111111111111111111111111111011111111111111111* L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* L042288 111111111111111111111111111111111111111111111111111111111111111111* @@ -868,46 +867,46 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111111111111011111111111111111111111111111101111111011111111111* -L042750 111111111111110111111111111111111111111111111110111111101111111111* +L042684 111011011111111111111111111111111111111111111111111111111111111101* +L042750 110111101111111111111111111111111111111111111111111111111111111110* L042816 000000000000000000000000000000000000000000000000000000000000000000* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111111111111111111111111111111111011111110011111111111111111111001* -L043080 111111110111111111111111111111111011111110011111111111111111111101* -L043146 111111111011111111110111111111111011111110011111111111111111110110* -L043212 111111111111111111111011111111111011111110011111111111111111111101* +L043014 111111111111111111111111111111111111111111111111111111101111111101* +L043080 111111111111111111111111111011111111111111111111111111111111111101* +L043146 111111111111111111111111111111111111111111011111111111111111111101* +L043212 111011111111111111111111110111111111111111101111111111011111111110* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 111111110111111111111011111111111111111111111111011111011111111111* -L043476 111111111111111111111111111111111111111111111101111111111111111111* -L043542 000000000000000000000000000000000000000000000000000000000000000000* -L043608 000000000000000000000000000000000000000000000000000000000000000000* -L043674 000000000000000000000000000000000000000000000000000000000000000000* -L043740 111111111111111111111111111111111111111111111111111111111111111111* -L043806 111111111111111111111111111111111111111111111111111111111111111111* -L043872 111111111111111111111111111111111111111111111111111111111111111111* -L043938 111111111111111111111111111111111111111111111111111111111111111111* -L044004 111111111111111111111111111111111111111111111111111111111111111111* +L043410 011110111011111110101111111111111111111110111111111111110111111011* +L043476 011110111011111110011111111111111111111110111111111111111011111011* +L043542 011110111111111110101111111111111111111110111101111111110111111111* +L043608 011110111111111110011111111111111111111110111101111111111011111111* +L043674 011110111011111111101111111111111111111110111111101111110111111011* +L043740 011110111011111111011111111111111111111110111111101111111011111011* +L043806 011110111111111111101111111111111111111110111101101111110111111111* +L043872 011110111111111111011111111111111111111110111101101111111011111111* +L043938 000000000000000000000000000000000000000000000000000000000000000000* +L044004 000000000000000000000000000000000000000000000000000000000000000000* L044070 111111111110111111111111111111111111011110111111111111111111111111* -L044136 111111111111111111111111111111111111111111101111111111111111111111* -L044202 111111011111111111111111110111111111111101111111111111111111111111* +L044136 101111111111111111111111111111111111111111111111111111111111111111* +L044202 111111111111111111110111111111111111110101111111111111111111111111* L044268 111111111111111101111111111111111111111110111111111111111111111111* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 111111111111111111111111111111111111111111111111101111011111111111* -L044532 111111111011111111111111111111111111111111111111111111011111111111* -L044598 111111111111111111110111111111111111111111111111111111011111111111* -L044664 111111110111111011111011111111111111111111111111011111101111111111* +L044466 111111111111111111111111111011111111111111111111111111011111111111* +L044532 111111111111111111111111111111111111111111011111111111011111111111* +L044598 111111111111111111111111110111111111111111101111111111101111111111* +L044664 000000000000000000000000000000000000000000000000000000000000000000* L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 111111111110111111111111111111111111111110111111111111111111111111* -L044862 111111111111111111111111111111111111111111101111111111111111111111* -L044928 111111011111111111111111111111111111111101110111111111111111111111* -L044994 101111111111111110111111111111111111111110111111111111111111111111* -L045060 000000000000000000000000000000000000000000000000000000000000000000* +L044862 011110111111111111101111111111111111111110111111111111110111111111* +L044928 011110111111111111111111110111111111111110111111111111110111111111* +L044994 011110111111111111011111111011111111111110011111111111111011111111* +L045060 011110111111111111111111111111111111111110101111111111110111111111* L045126 000000000000000000000000000000000000000000000000000000000000000000* L045192 111111111111111111111111111111111111111111111111111111111111111111* L045258 111111111111111111111111111111111111111111111111111111111111111111* @@ -916,23 +915,23 @@ L045390 111111111111111111111111111111111111111111111111111111111111111111* L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 111111111111111111111111111111111111011110111111111111111111111111* -L045588 111101111111111111111111111111111111111111111011111111111111111111* -L045654 111111111111111111111111111111111111111111111111111111111111111111* -L045720 111111111111111111111111111111111111111111111111111111111111111111* -L045786 111111111111111111111111111111111111111111111111111111111111111111* -L045852 111111111111111111111111111111111111111111111111111111111111111111* -L045918 111111110111111111111111011111111111111111011111111111111111111111* -L045984 111111111111111111111011011111111111111111011111111111111111111111* -L046050 110111110111111111111011111111111111111111011111111111111111111111* -L046116 000000000000000000000000000000000000000000000000000000000000000000* -L046182 000000000000000000000000000000000000000000000000000000000000000000* +L045588 011111111111111111111111111111111111111001111111111111111111111111* +L045654 011111111111111011111111111111111111111101111111111111111111111111* +L045720 011111111111111110111111111111111111111110111111101111111111111111* +L045786 000000000000000000000000000000000000000000000000000000000000000000* +L045852 000000000000000000000000000000000000000000000000000000000000000000* +L045918 101111111111111111111111111111111111111111111111111111111111111111* +L045984 111111111111111111111111111111111111111101111111111111111111111111* +L046050 111111111111111111011111111111111111111111111111111111110111111111* +L046116 111111111111111111101111111111111111111111111111111111111011111111* +L046182 111101111111111111111111111111111111111111111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111101101111111111111111111111111111111111111111111* -L046380 111111111111111111011110111111111111111111111111111111111111111111* -L046446 000000000000000000000000000000000000000000000000000000000000000000* -L046512 000000000000000000000000000000000000000000000000000000000000000000* -L046578 000000000000000000000000000000000000000000000000000000000000000000* +L046314 011111111111111111111111111111111111111111111011111111111111111111* +L046380 111111111111111101111111111111111111111111111111011111111111111111* +L046446 111111111011101111111111011111111111111111111111111111111111111111* +L046512 111111110111101111111111111111111111111111111101111111111111110111* +L046578 111111111111101111111111011111111111111111111110111111111111111111* L046644 111111111111111111111111111111111111111111111111111111111111111111* L046710 111111111111111111111111111111111111111111111111111111111111111111* L046776 111111111111111111111111111111111111111111111111111111111111111111* @@ -943,47 +942,47 @@ L046974 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* L047110 11100110011000* -L047124 00100110011110* +L047124 00010110011110* L047138 10100110010100* L047152 11100011111111* L047166 10101111111001* L047180 10100110010011* -L047194 00100110010000* -L047208 11100011110011* +L047194 10100110010000* +L047208 11110011110011* L047222 10100110010000* L047236 10100110010010* L047250 10100110010100* L047264 11101111110011* -L047278 00110011110011* +L047278 11100110010011* L047292 10100110010011* -L047306 10100110010000* -L047320 11101011111111* +L047306 01110110010000* +L047320 11100011111111* NOTE BLOCK 7 * L047334 - 111111111111111111110110111111111111111101111111111111111111111111 - 111111011111111111111111111111011111111111111011111011111111111111 - 111111111111111111111111111111111110111111111101111111111111111111 - 111001111111111111111111111011111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111110111111011011111011111111111111111111111111111111111111111 - 111111111110111111111111111101111111011111111111111101111111100111 - 101111111111111111111111111111111111111011111111111111101111111111 - 111111111111101101111111111111111011111111101111111111111111111111* + 111111111111111111110111111111111111111111111111111111111111111111 + 111111111101111110111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111110111110111111111111111111111111 + 111011111111111111111111111011111111111111111111111111111111111011 + 111111111111111111111111111111111111111111111111111011111111111111 + 111111111111011011111111111111011111011111111111111111111110111111 + 111111010111111111111101111111111111111111111111011111111111111111 + 101101111111111111101111011111111111111111111111111111101111111111 + 111111111111111111111111111111111011110111101110111111111111111111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 111111111111101111111111111111111111111101011111111111011111111111* -L048060 111111111111101111111011111111111111111101011111111111111111111111* -L048126 111111111111101011111111111111111111111101011110111111111111111111* -L048192 111111111111111011110111111111111111111101011101111011101111111111* +L047994 111111111111111111111111111111111111111101011110111111011111111111* +L048060 111111111111111111111011111111111111111101011110111111111111111111* +L048126 111111111111111111111111111111101111111101011110111011111111111111* +L048192 111111111111111110110111111111101111111101011111110111101111111111* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 110111110111111110111111100111111101111011111111111110111111111011* +L048324 110111111011101111101110110111111101011011111111111111111111111111* L048390 000000000000000000000000000000000000000000000000000000000000000000* L048456 000000000000000000000000000000000000000000000000000000000000000000* L048522 000000000000000000000000000000000000000000000000000000000000000000* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111101111111111111111111111111111111111111111111* +L048720 111111111111111111111111111111111111111111111111111111011111111111* L048786 111111111111111111111111111111111111111111111111111111111111111111* L048852 111111111111111111111111111111111111111111111111111111111111111111* L048918 111111111111111111111111111111111111111111111111111111111111111111* @@ -996,8 +995,8 @@ L049314 111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* L049446 111111111111111111111111111111111111111111101111111111111111111111* -L049512 011111110111111111111111111111111111111111111111111111111111111111* -L049578 111111110111111111110111111111110111111111111111111111101111111111* +L049512 011111111111111111111111111111111111011111111111111111111111111111* +L049578 111111111111111111110111111111110111011111111111111111101111111111* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* L049776 111111111111111111110111111111111111111111111111111111111111111111* @@ -1006,8 +1005,8 @@ L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 - 101111111111111111111111111111101111011111111111111111111111111111* -L050172 111111111111111111111111111110111111111111011111111111111111111111* + 101111011110111111111111111111111111111111111111111111111111111111* +L050172 111111111111111111101111111111111111111111011111111111111111111111* L050238 111111111111111111111111111111111111111111111111111111111111111111* L050304 111111111111111111111111111111111111111111111111111111111111111111* L050370 111111111111111111111111111111111111111111111111111111111111111111* @@ -1018,19 +1017,19 @@ L050634 111111111111111111111111111111111111111111111111111111111111111111* L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 - 111111111111111111111111111111011111111111111111111111111111111111* -L050898 111111101111111111111111111111111011111111111111111111111111111111* + 111111111101111111111111111111111111111111111111111111111111111111* +L050898 111111111111111111111111111111111011111111111111111111111111111011* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111111111110111111111111111111111111111111011111111111111111101111* -L051294 111111111111111111011011111111111111111111011111111111011111111111* -L051360 000000000000000000000000000000000000000000000000000000000000000000* -L051426 000000000000000000000000000000000000000000000000000000000000000000* -L051492 000000000000000000000000000000000000000000000000000000000000000000* +L051228 111110111111111111101111111111111111111111111111111111111111111111* +L051294 111111111111111111111111111111111111111111111111111111111111111111* +L051360 111111111111111111111111111111111111111111111111111111111111111111* +L051426 111111111111111111111111111111111111111111111111111111111111111111* +L051492 111111111111111111111111111111111111111111111111111111111111111111* L051558 - 011111111111111111111111111111111111011111111111111111111111111111* + 011111011111111111111111111111111111111111111111111111111111111111* L051624 111111111111111111111111111111111111111111111111111111111111111111* L051690 111111111111111111111111111111111111111111111111111111111111111111* L051756 111111111111111111111111111111111111111111111111111111111111111111* @@ -1042,17 +1041,17 @@ L052086 111111111111111111111111111111111111111111111111111111111111111111* L052152 111111111111111111111111111111111111111111111111111111111111111111* L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 - 101111111111111111111111111111101111111111111111111111111111111111* -L052350 111110111111111111111111111111111111111111110111111111111111111111* -L052416 111111111111111111111111111111111111111111111111111111111111111111* -L052482 111111111111111111111111111111111111111111111111111111111111111111* -L052548 111111111111111111111111111111111111111111111111111111111111111111* -L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 111111111111111111011011111111111111111111011111111111011111111111* -L052746 111111111111110111111111111111111111111111011111111111011111111111* -L052812 111111111111110111111011111111111111111111011111111111111111111111* -L052878 000000000000000000000000000000000000000000000000000000000000000000* -L052944 000000000000000000000000000000000000000000000000000000000000000000* + 101111111110111111111111111111111111111111111111111111111111111111* +L052350 111111111111111111111111111111111111111111101111111111111111111111* +L052416 011111111111110111111111111111111111111111111111111111111101111111* +L052482 101111111111111111111111101111111111111111111111101111111111111111* +L052548 000000000000000000000000000000000000000000000000000000000000000000* +L052614 000000000000000000000000000000000000000000000000000000000000000000* +L052680 101111111111111111111111111111111111111111011111111111111111111111* +L052746 111111111111111111111111111111111111111111111111111111111111111111* +L052812 111111111111111111111111111111111111111111111111111111111111111111* +L052878 111111111111111111111111111111111111111111111111111111111111111111* +L052944 111111111111111111111111111111111111111111111111111111111111111111* L053010 111111111111111111111111111111111111111111111111111111111111111111* L053076 111111111111111111111111111111111111111111111111111111111111111111* @@ -1078,11 +1077,11 @@ L053942 00000110011110* L053956 01010110010101* L053970 11100011110011* L053984 01111111111000* -L053998 11100110011110* -L054012 11010011110110* -L054026 11111011110011* -L054040 00111111110001* -L054054 10100110010011* +L053998 01000011111110* +L054012 11011011110110* +L054026 11111111110011* +L054040 10100110010001* +L054054 01000110010011* L054068 11010011111100* L054082 11111011111111* E1 @@ -1104,6 +1103,6 @@ E1 00000000 1 * -CD04F* +C3764* U00000000000000000000000000000000* -9B79 +96E3 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 7251cb9..56356b5 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 9/14/16; -TIME = 23:54:30; +DATE = 10/6/16; +TIME = 21:35:00; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,7 +76,6 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -SIZE_1_ = pin,79,-,H,-; AHIGH_31_ = pin,4,-,B,-; A_DECODE_23_ = pin,85,-,H,-; IPL_2_ = pin,68,-,G,-; @@ -92,30 +91,30 @@ BG_030 = pin,21,-,C,-; BGACK_000 = pin,28,-,D,-; CLK_030 = pin,64,-,-,-; CLK_000 = pin,11,-,-,-; -SIZE_0_ = pin,70,-,G,-; -CLK_OSZI = pin,61,-,-,-; AHIGH_30_ = pin,5,-,B,-; -CLK_DIV_OUT = pin,65,-,G,-; +CLK_OSZI = pin,61,-,-,-; AHIGH_29_ = pin,6,-,B,-; +CLK_DIV_OUT = pin,65,-,G,-; AHIGH_28_ = pin,15,-,C,-; -FPU_CS = pin,78,-,H,-; AHIGH_27_ = pin,16,-,C,-; -FPU_SENSE = pin,91,-,A,-; +FPU_CS = pin,78,-,H,-; AHIGH_26_ = pin,17,-,C,-; +FPU_SENSE = pin,91,-,A,-; AHIGH_25_ = pin,18,-,C,-; -DTACK = pin,30,-,D,-; +DSACK1 = pin,81,-,H,-; AHIGH_24_ = pin,19,-,C,-; -AVEC = pin,92,-,A,-; +DTACK = pin,30,-,D,-; A_DECODE_22_ = pin,84,-,H,-; -E = pin,66,-,G,-; +AVEC = pin,92,-,A,-; A_DECODE_21_ = pin,94,-,A,-; -VPA = pin,36,-,-,-; +E = pin,66,-,G,-; A_DECODE_20_ = pin,93,-,A,-; +VPA = pin,36,-,-,-; A_DECODE_19_ = pin,97,-,A,-; -RST = pin,86,-,-,-; A_DECODE_18_ = pin,95,-,A,-; -RESET = pin,3,-,B,-; +RST = pin,86,-,-,-; A_DECODE_17_ = pin,59,-,F,-; +RESET = pin,3,-,B,-; A_DECODE_16_ = pin,96,-,A,-; AMIGA_ADDR_ENABLE = pin,33,-,D,-; AMIGA_BUS_DATA_DIR = pin,48,-,E,-; @@ -126,61 +125,62 @@ IPL_1_ = pin,56,-,F,-; IPL_0_ = pin,67,-,G,-; FC_0_ = pin,57,-,F,-; A_1_ = pin,60,-,F,-; +SIZE_1_ = pin,79,-,H,-; IPL_030_2_ = pin,9,-,B,-; RW_000 = pin,80,-,H,-; BG_000 = pin,29,-,D,-; BGACK_030 = pin,83,-,H,-; +SIZE_0_ = pin,70,-,G,-; CLK_EXP = pin,10,-,B,-; -DSACK1 = pin,81,-,H,-; VMA = pin,35,-,D,-; RW = pin,71,-,G,-; A_0_ = pin,69,-,G,-; IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; -cpu_est_2_ = node,-,-,G,6; -cpu_est_3_ = node,-,-,D,9; -cpu_est_0_ = node,-,-,B,10; -cpu_est_1_ = node,-,-,G,9; -inst_AS_000_INT = node,-,-,D,2; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,F,12; -inst_AS_030_D0 = node,-,-,E,8; -inst_AS_030_000_SYNC = node,-,-,C,13; -inst_BGACK_030_INT_D = node,-,-,E,5; -inst_AS_000_DMA = node,-,-,C,9; -inst_DS_000_DMA = node,-,-,F,0; -CYCLE_DMA_0_ = node,-,-,G,2; -CYCLE_DMA_1_ = node,-,-,G,5; -SIZE_DMA_0_ = node,-,-,C,2; -SIZE_DMA_1_ = node,-,-,G,10; -inst_VPA_D = node,-,-,F,1; -CLK_000_D_1_ = node,-,-,H,5; -inst_DTACK_D0 = node,-,-,H,6; +cpu_est_3_ = node,-,-,D,13; +cpu_est_0_ = node,-,-,G,9; +cpu_est_1_ = node,-,-,G,5; +cpu_est_2_ = node,-,-,D,2; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,A,6; +inst_AS_030_D0 = node,-,-,H,6; +inst_AS_030_000_SYNC = node,-,-,F,4; +inst_BGACK_030_INT_D = node,-,-,H,13; +inst_AS_000_DMA = node,-,-,G,2; +inst_DS_000_DMA = node,-,-,G,13; +CYCLE_DMA_0_ = node,-,-,A,1; +CYCLE_DMA_1_ = node,-,-,G,10; +inst_VPA_D = node,-,-,A,10; +CLK_000_D_2_ = node,-,-,H,2; +CLK_000_D_3_ = node,-,-,D,9; +inst_DTACK_D0 = node,-,-,C,14; inst_RESET_OUT = node,-,-,A,8; +CLK_000_D_1_ = node,-,-,H,5; CLK_000_D_0_ = node,-,-,B,13; -inst_CLK_OUT_PRE_50 = node,-,-,A,1; -inst_CLK_OUT_PRE_25 = node,-,-,G,14; -inst_CLK_OUT_PRE_D = node,-,-,H,2; -IPL_D0_0_ = node,-,-,C,14; -IPL_D0_1_ = node,-,-,D,14; -IPL_D0_2_ = node,-,-,C,10; -CLK_000_D_2_ = node,-,-,E,13; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,F,8; -inst_LDS_000_INT = node,-,-,F,4; -inst_DS_000_ENABLE = node,-,-,D,6; -inst_UDS_000_INT = node,-,-,D,10; -SM_AMIGA_6_ = node,-,-,B,6; -SM_AMIGA_4_ = node,-,-,G,13; -SM_AMIGA_1_ = node,-,-,A,12; -SM_AMIGA_0_ = node,-,-,H,13; -RST_DLY_0_ = node,-,-,A,13; -RST_DLY_1_ = node,-,-,A,6; -RST_DLY_2_ = node,-,-,A,2; -inst_CLK_030_H = node,-,-,C,6; -SM_AMIGA_5_ = node,-,-,D,13; -SM_AMIGA_3_ = node,-,-,A,9; -SM_AMIGA_2_ = node,-,-,A,5; -SM_AMIGA_i_7_ = node,-,-,B,14; -CIIN_0 = node,-,-,E,9; +inst_CLK_OUT_PRE_50 = node,-,-,E,9; +inst_CLK_OUT_PRE_D = node,-,-,E,8; +IPL_D0_0_ = node,-,-,D,14; +IPL_D0_1_ = node,-,-,B,14; +IPL_D0_2_ = node,-,-,G,14; +CLK_000_D_4_ = node,-,-,D,10; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,A,2; +SM_AMIGA_1_ = node,-,-,C,13; +inst_UDS_000_INT = node,-,-,B,10; +inst_DS_000_ENABLE = node,-,-,F,12; +inst_LDS_000_INT = node,-,-,B,6; +SM_AMIGA_6_ = node,-,-,F,0; +SM_AMIGA_4_ = node,-,-,C,2; +SM_AMIGA_0_ = node,-,-,A,12; +RST_DLY_0_ = node,-,-,C,9; +RST_DLY_1_ = node,-,-,A,13; +RST_DLY_2_ = node,-,-,A,9; +inst_CLK_030_H = node,-,-,G,6; +inst_DSACK1_INT = node,-,-,A,5; +inst_AS_000_INT = node,-,-,F,1; +SM_AMIGA_5_ = node,-,-,D,6; +SM_AMIGA_3_ = node,-,-,C,10; +SM_AMIGA_2_ = node,-,-,C,6; +SM_AMIGA_i_7_ = node,-,-,F,8; +CIIN_0 = node,-,-,E,5; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 76c05b7..99880f4 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -1,143 +1,20 @@ -117 "number of signals after reading design file" +113 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21 - 79 RW_000 5 340 7 3 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 346 6 2 2 6 68 -1 3 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 - 80 DSACK1 5 343 7 0 80 -1 5 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 315 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 316 CLK_000_D_1_ 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 6 0 1 3 4 5 7 -1 -1 1 0 21 - 326 SM_AMIGA_6_ 3 -1 1 5 1 2 5 6 7 -1 -1 3 0 21 - 317 CLK_000_D_0_ 3 -1 1 5 0 1 3 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 4 0 1 3 5 -1 -1 7 0 21 - 337 SM_AMIGA_i_7_ 3 -1 5 3 0 1 7 -1 -1 13 1 21 - 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 6 3 0 2 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 333 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 325 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 310 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 319 inst_CLK_OUT_PRE_25 3 -1 6 2 4 6 -1 -1 2 0 21 - 309 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 318 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21 - 312 CLK_000_D_2_ 3 -1 4 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 332 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 343 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 335 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 329 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 334 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 327 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 323 CLK_000_D_4_ 3 -1 7 1 7 -1 -1 1 0 21 - 322 IPL_D0_2_ 3 -1 4 1 1 -1 -1 1 0 21 - 321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 320 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 - 313 CLK_000_D_3_ 3 -1 1 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 4 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 63 CLK_030 1 -1 -1 2 2 7 63 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -121 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21 - 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 - 68 A_0_ 5 350 6 2 0 1 68 -1 3 0 21 - 70 RW 5 349 6 2 5 7 70 -1 2 0 21 + 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 + 70 RW 5 341 6 2 5 7 70 -1 2 0 21 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -146,16 +23,16 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21 - 80 DSACK1 5 347 7 0 80 -1 5 0 21 - 82 BGACK_030 5 346 7 0 82 -1 3 0 21 - 34 VMA 5 348 3 0 34 -1 3 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 340 3 0 34 -1 3 0 21 + 80 DSACK1 5 339 7 0 80 -1 2 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 345 3 0 28 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 77 FPU_CS 0 7 0 77 -1 1 0 21 @@ -165,106 +42,98 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 - 317 CLK_000_D_0_ 3 -1 4 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 315 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 316 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 330 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 - 295 cpu_est_1_ 3 -1 5 4 0 3 5 6 -1 -1 4 0 21 - 296 cpu_est_2_ 3 -1 0 4 0 3 5 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 3 0 1 6 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 5 -1 -1 3 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 2 6 -1 -1 1 0 21 - 341 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 + 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 4 0 21 - 348 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 337 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 332 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 309 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 318 inst_CLK_OUT_PRE_50 3 -1 2 2 2 3 -1 -1 1 0 21 - 312 CLK_000_D_6_ 3 -1 2 2 0 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 - 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 347 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 333 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 331 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 349 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 335 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 334 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 319 inst_CLK_OUT_PRE_25 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 327 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21 - 326 CLK_000_D_5_ 3 -1 3 1 2 -1 -1 1 0 21 - 325 CLK_000_D_4_ 3 -1 3 1 3 -1 -1 1 0 21 - 324 CLK_000_D_3_ 3 -1 4 1 3 -1 -1 1 0 21 - 323 CLK_000_D_2_ 3 -1 1 1 4 -1 -1 1 0 21 - 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 320 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 - 313 CLK_000_D_7_ 3 -1 0 1 7 -1 -1 1 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 + 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 63 CLK_030 1 -1 -1 2 0 7 63 -1 - 59 A_1_ 1 -1 -1 2 0 2 59 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 + 35 VPA 1 -1 -1 1 7 35 -1 29 DTACK 1 -1 -1 1 5 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -122 "number of signals after reading design file" + 10 CLK_000 1 -1 -1 1 1 10 -1 +114 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 79 RW_000 5 345 7 3 1 4 6 79 -1 4 0 21 - 40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21 - 68 A_0_ 5 351 6 2 2 6 68 -1 3 0 21 - 70 RW 5 350 6 2 5 7 70 -1 2 0 21 + 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 + 79 RW_000 5 337 7 3 4 5 6 79 -1 4 0 21 + 70 RW 5 342 6 2 0 7 70 -1 2 0 21 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 + 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 3 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -273,16 +142,16 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21 - 80 DSACK1 5 348 7 0 80 -1 5 0 21 - 82 BGACK_030 5 347 7 0 82 -1 3 0 21 - 34 VMA 5 349 3 0 34 -1 3 0 21 + 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 + 82 BGACK_030 5 339 7 0 82 -1 3 0 21 + 34 VMA 5 341 3 0 34 -1 3 0 21 + 80 DSACK1 5 340 7 0 80 -1 2 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 346 3 0 28 -1 2 0 21 + 28 BG_000 5 338 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 77 FPU_CS 0 7 0 77 -1 1 0 21 @@ -292,200 +161,62 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 - 347 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 315 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 331 SM_AMIGA_6_ 3 -1 0 5 0 2 5 6 7 -1 -1 3 0 21 - 317 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 - 316 CLK_000_D_1_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 295 cpu_est_1_ 3 -1 2 4 2 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 4 2 3 5 6 -1 -1 4 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 - 294 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 342 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 2 1 2 -1 -1 4 0 21 - 349 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 338 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 333 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 330 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 310 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 339 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 6 0 1 2 3 4 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 0 4 0 1 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 + 334 SM_AMIGA_i_7_ 3 -1 0 3 0 2 7 -1 -1 3 1 21 + 304 CYCLE_DMA_0_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 331 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 - 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 319 inst_CLK_OUT_PRE_25 3 -1 2 2 2 4 -1 -1 2 0 21 - 309 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 318 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21 - 312 CLK_000_D_7_ 3 -1 3 2 4 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 1 2 0 6 -1 -1 1 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 337 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 348 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 341 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 340 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 332 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 343 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 328 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21 - 327 CLK_000_D_6_ 3 -1 4 1 3 -1 -1 1 0 21 - 326 CLK_000_D_5_ 3 -1 3 1 4 -1 -1 1 0 21 - 325 CLK_000_D_4_ 3 -1 3 1 3 -1 -1 1 0 21 - 324 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21 - 323 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 322 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 321 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 320 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 313 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 + 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 330 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 333 SM_AMIGA_2_ 3 -1 3 1 3 -1 -1 5 0 21 + 332 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 + 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 327 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 + 328 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 318 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 63 CLK_030 1 -1 -1 2 1 7 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -124 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 3 4 6 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 347 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 353 6 2 0 5 68 -1 3 0 21 - 70 RW 5 352 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 31 UDS_000 5 -1 3 1 6 31 -1 1 0 20 - 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 - 80 DSACK1 5 350 7 0 80 -1 5 0 21 - 82 BGACK_030 5 349 7 0 82 -1 3 0 21 - 34 VMA 5 351 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 348 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 315 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 317 CLK_000_D_0_ 3 -1 5 6 0 2 3 5 6 7 -1 -1 1 0 21 - 316 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21 - 332 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 - 295 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 - 297 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 1 1 21 - 344 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21 - 304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 341 SM_AMIGA_5_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 340 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 334 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 333 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 331 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 310 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 - 338 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 319 inst_CLK_OUT_PRE_25 3 -1 1 2 0 1 -1 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 318 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 - 313 CLK_000_D_8_ 3 -1 4 2 3 7 -1 -1 1 0 21 - 312 CLK_000_D_7_ 3 -1 5 2 4 7 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 - 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 339 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 350 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 335 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 - 306 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21 - 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 - 336 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 - 330 inst_UDS_000_e 3 -1 3 1 3 -1 -1 1 0 20 - 328 CLK_000_D_9_ 3 -1 3 1 7 -1 -1 1 0 21 - 327 CLK_000_D_6_ 3 -1 4 1 5 -1 -1 1 0 21 - 326 CLK_000_D_5_ 3 -1 0 1 4 -1 -1 1 0 21 - 325 CLK_000_D_4_ 3 -1 2 1 0 -1 -1 1 0 21 - 324 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21 - 323 CLK_000_D_2_ 3 -1 0 1 3 -1 -1 1 0 21 - 322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 320 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 293 un1_as_000 3 -1 7 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 @@ -494,35 +225,35 @@ 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 63 CLK_030 1 -1 -1 2 6 7 63 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 + 63 CLK_030 1 -1 -1 1 5 63 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -122 "number of signals after reading design file" + 10 CLK_000 1 -1 -1 1 6 10 -1 +113 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 79 RW_000 5 345 7 3 1 4 6 79 -1 4 0 21 - 40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21 - 68 A_0_ 5 351 6 2 2 6 68 -1 3 0 21 - 70 RW 5 350 6 2 5 7 70 -1 2 0 21 + 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 + 70 RW 5 341 6 2 5 7 70 -1 2 0 21 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -531,16 +262,16 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21 - 80 DSACK1 5 348 7 0 80 -1 5 0 21 - 82 BGACK_030 5 347 7 0 82 -1 3 0 21 - 34 VMA 5 349 3 0 34 -1 3 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 340 3 0 34 -1 3 0 21 + 80 DSACK1 5 339 7 0 80 -1 2 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 346 3 0 28 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 77 FPU_CS 0 7 0 77 -1 1 0 21 @@ -550,1349 +281,217 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 - 347 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 313 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 331 SM_AMIGA_6_ 3 -1 0 5 0 2 5 6 7 -1 -1 3 0 21 - 315 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 - 314 CLK_000_D_1_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 - 296 cpu_est_1_ 3 -1 3 4 2 3 5 6 -1 -1 4 0 21 - 293 cpu_est_2_ 3 -1 2 4 2 3 5 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 295 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21 - 309 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 - 342 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 2 1 2 -1 -1 4 0 21 - 349 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 338 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 333 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 328 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 - 330 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 317 inst_CLK_OUT_PRE_25 3 -1 2 2 2 4 -1 -1 2 0 21 + 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21 - 310 CLK_000_D_7_ 3 -1 3 2 4 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 1 2 0 6 -1 -1 1 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 337 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 348 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 341 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 340 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 332 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 343 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 326 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21 - 325 CLK_000_D_6_ 3 -1 4 1 3 -1 -1 1 0 21 - 324 CLK_000_D_5_ 3 -1 3 1 4 -1 -1 1 0 21 - 323 CLK_000_D_4_ 3 -1 3 1 3 -1 -1 1 0 21 - 322 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21 - 321 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 320 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 319 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 318 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 311 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 + 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 63 CLK_030 1 -1 -1 2 1 7 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -123 "number of signals after reading design file" + 10 CLK_000 1 -1 -1 1 1 10 -1 +113 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 + 70 RW 5 341 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 340 3 0 34 -1 3 0 21 + 80 DSACK1 5 339 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 + 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 + 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +114 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 346 7 3 2 4 6 79 -1 4 0 21 + 79 RW_000 5 337 7 3 2 4 6 79 -1 4 0 21 81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21 - 40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21 - 68 A_0_ 5 352 6 2 1 3 68 -1 3 0 21 - 70 RW 5 351 6 2 5 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 345 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 354 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 - 80 DSACK1 5 349 7 0 80 -1 5 0 21 - 82 BGACK_030 5 348 7 0 82 -1 3 0 21 - 34 VMA 5 350 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 347 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 348 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 315 CLK_000_D_0_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21 - 314 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 332 SM_AMIGA_6_ 3 -1 0 5 0 1 3 5 7 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 3 5 0 3 4 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 309 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 5 3 0 2 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 343 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 350 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 339 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 330 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 329 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 317 inst_CLK_OUT_PRE_25 3 -1 0 2 0 1 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 311 CLK_000_D_9_ 3 -1 7 2 5 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 - 354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 345 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 338 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 349 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 342 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 341 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 335 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 352 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 333 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 351 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 336 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 331 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 327 CLK_000_D_10_ 3 -1 5 1 7 -1 -1 1 0 21 - 326 CLK_000_D_7_ 3 -1 4 1 4 -1 -1 1 0 21 - 325 CLK_000_D_6_ 3 -1 1 1 4 -1 -1 1 0 21 - 324 CLK_000_D_5_ 3 -1 1 1 1 -1 -1 1 0 21 - 323 CLK_000_D_4_ 3 -1 3 1 1 -1 -1 1 0 21 - 322 CLK_000_D_3_ 3 -1 4 1 3 -1 -1 1 0 21 - 321 CLK_000_D_2_ 3 -1 7 1 4 -1 -1 1 0 21 - 320 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 318 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 316 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 - 312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 310 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 63 CLK_030 1 -1 -1 2 2 7 63 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -121 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 - 79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 - 70 RW 5 349 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21 - 68 A_0_ 5 350 6 1 0 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21 - 80 DSACK1 5 347 7 0 80 -1 5 0 21 - 82 BGACK_030 5 346 7 0 82 -1 3 0 21 - 34 VMA 5 348 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 345 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 315 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 314 CLK_000_D_1_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 4 1 2 3 5 -1 -1 7 0 21 - 330 SM_AMIGA_6_ 3 -1 1 4 0 1 5 7 -1 -1 3 0 21 - 341 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21 - 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 337 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 - 332 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 309 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 3 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 348 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 328 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 - 311 CLK_000_D_7_ 3 -1 7 2 4 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 - 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 347 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 333 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 331 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 349 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 335 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 334 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 - 317 inst_CLK_OUT_PRE_25 3 -1 2 1 2 -1 -1 2 0 21 - 325 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21 - 324 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21 - 323 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 - 322 CLK_000_D_3_ 3 -1 4 1 6 -1 -1 1 0 21 - 321 CLK_000_D_2_ 3 -1 5 1 4 -1 -1 1 0 21 - 320 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 318 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 310 CLK_000_D_6_ 3 -1 3 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 63 CLK_030 1 -1 -1 2 0 7 63 -1 - 59 A_1_ 1 -1 -1 2 3 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -121 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 - 79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 - 70 RW 5 349 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21 - 68 A_0_ 5 350 6 1 0 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21 - 80 DSACK1 5 347 7 0 80 -1 5 0 21 - 82 BGACK_030 5 346 7 0 82 -1 3 0 21 - 34 VMA 5 348 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 345 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 315 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 314 CLK_000_D_1_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 4 1 2 3 5 -1 -1 7 0 21 - 330 SM_AMIGA_6_ 3 -1 1 4 0 1 5 7 -1 -1 3 0 21 - 341 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21 - 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 337 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 - 332 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 309 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 3 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 348 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 328 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 - 311 CLK_000_D_7_ 3 -1 7 2 4 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 - 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 347 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 333 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 331 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 349 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 335 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 334 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 - 317 inst_CLK_OUT_PRE_25 3 -1 2 1 2 -1 -1 2 0 21 - 325 CLK_000_D_8_ 3 -1 4 1 7 -1 -1 1 0 21 - 324 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21 - 323 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 - 322 CLK_000_D_3_ 3 -1 4 1 6 -1 -1 1 0 21 - 321 CLK_000_D_2_ 3 -1 5 1 4 -1 -1 1 0 21 - 320 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 318 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 310 CLK_000_D_6_ 3 -1 3 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 63 CLK_030 1 -1 -1 2 0 7 63 -1 - 59 A_1_ 1 -1 -1 2 3 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -119 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 2 4 6 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21 - 79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21 - 70 RW 5 347 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 - 68 A_0_ 5 348 6 1 2 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 350 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 349 1 0 6 -1 10 0 21 - 80 DSACK1 5 345 7 0 80 -1 5 0 21 - 82 BGACK_030 5 344 7 0 82 -1 3 0 21 - 34 VMA 5 346 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 343 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 344 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 314 CLK_000_D_1_ 3 -1 3 7 0 2 3 4 5 6 7 -1 -1 1 0 21 - 315 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 4 0 1 3 5 -1 -1 7 0 21 - 328 SM_AMIGA_6_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 0 1 3 6 -1 -1 1 0 21 - 339 SM_AMIGA_i_7_ 3 -1 5 3 0 1 7 -1 -1 13 1 21 - 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 309 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 331 RST_DLY_0_ 3 -1 6 2 0 6 -1 -1 4 0 21 - 346 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 335 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 330 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 329 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 326 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 325 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 2 2 6 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 333 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 332 RST_DLY_1_ 3 -1 6 2 0 6 -1 -1 2 1 21 - 327 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 310 CLK_000_D_4_ 3 -1 0 2 0 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 - 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 334 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 345 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 338 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 337 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 336 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 - 317 inst_CLK_OUT_PRE_25 3 -1 4 1 4 -1 -1 2 0 21 - 323 CLK_000_D_6_ 3 -1 7 1 7 -1 -1 1 0 21 - 322 CLK_000_D_3_ 3 -1 3 1 0 -1 -1 1 0 21 - 321 CLK_000_D_2_ 3 -1 4 1 3 -1 -1 1 0 21 - 320 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 319 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 318 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 312 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 - 311 CLK_000_D_5_ 3 -1 0 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 63 CLK_030 1 -1 -1 2 2 7 63 -1 - 59 A_1_ 1 -1 -1 2 0 3 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -125 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 348 7 3 2 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21 - 70 RW 5 353 6 2 2 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 - 68 A_0_ 5 354 6 1 1 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 356 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 355 1 0 6 -1 10 0 21 - 80 DSACK1 5 351 7 0 80 -1 5 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 352 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 313 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 315 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 314 CLK_000_D_1_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 - 334 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 0 5 0 2 3 4 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 2 4 0 2 3 6 -1 -1 1 0 21 - 345 SM_AMIGA_i_7_ 3 -1 5 3 0 5 7 -1 -1 13 1 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 309 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 352 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 342 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 341 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 336 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 331 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 333 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 311 CLK_000_D_11_ 3 -1 7 2 1 7 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 - 356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 340 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 351 RN_DSACK1 3 80 7 1 7 80 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 344 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 343 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 337 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 - 354 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 353 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 339 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 338 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 - 317 inst_CLK_OUT_PRE_25 3 -1 4 1 4 -1 -1 2 0 21 - 329 CLK_000_D_12_ 3 -1 1 1 7 -1 -1 1 0 21 - 328 CLK_000_D_9_ 3 -1 3 1 5 -1 -1 1 0 21 - 327 CLK_000_D_8_ 3 -1 4 1 3 -1 -1 1 0 21 - 326 CLK_000_D_7_ 3 -1 1 1 4 -1 -1 1 0 21 - 325 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21 - 324 CLK_000_D_5_ 3 -1 1 1 6 -1 -1 1 0 21 - 323 CLK_000_D_4_ 3 -1 5 1 1 -1 -1 1 0 21 - 322 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21 - 321 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 320 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 319 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 318 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 312 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 - 310 CLK_000_D_10_ 3 -1 5 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 63 CLK_030 1 -1 -1 2 2 7 63 -1 - 59 A_1_ 1 -1 -1 2 3 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21 - 68 A_0_ 5 341 6 2 3 5 68 -1 3 0 21 - 70 RW 5 346 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 80 DSACK1 5 344 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21 - 335 SM_AMIGA_i_7_ 3 -1 0 2 2 7 -1 -1 13 1 21 - 304 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 306 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 328 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 - 341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 2 0 21 - 336 CIIN_0 3 -1 6 1 4 -1 -1 1 0 21 - 319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 318 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 - 317 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 6 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21 - 68 A_0_ 5 341 6 2 3 5 68 -1 3 0 21 - 70 RW 5 346 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 80 DSACK1 5 344 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21 - 335 SM_AMIGA_i_7_ 3 -1 0 2 2 7 -1 -1 13 1 21 - 304 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 306 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 328 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 - 341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 2 0 21 - 336 CIIN_0 3 -1 6 1 4 -1 -1 1 0 21 - 319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 318 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 - 317 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 6 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 - 79 RW_000 5 337 7 2 4 6 79 -1 4 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 80 DSACK1 5 343 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 - 297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 - 342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21 - 68 A_0_ 5 341 6 2 3 5 68 -1 3 0 21 - 70 RW 5 346 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 80 DSACK1 5 344 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21 - 335 SM_AMIGA_i_7_ 3 -1 0 2 2 7 -1 -1 13 1 21 - 304 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 306 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 316 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 328 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 - 341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 2 0 21 - 336 CIIN_0 3 -1 6 1 4 -1 -1 1 0 21 - 319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 318 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 - 317 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 6 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 - 79 RW_000 5 337 7 2 4 6 79 -1 4 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 80 DSACK1 5 343 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 - 297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 - 342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -111 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 334 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 70 RW 5 342 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 68 A_0_ 5 336 6 1 1 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 5 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -1901,489 +500,15 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 333 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 339 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 338 1 0 6 -1 10 0 21 - 82 BGACK_030 5 337 7 0 82 -1 3 0 21 + 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 + 82 BGACK_030 5 339 7 0 82 -1 3 0 21 34 VMA 5 341 3 0 34 -1 3 0 21 80 DSACK1 5 340 7 0 80 -1 2 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 335 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 337 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 312 CLK_000_D_0_ 3 -1 3 6 0 2 3 4 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 311 CLK_000_D_1_ 3 -1 4 5 0 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 331 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 330 SM_AMIGA_2_ 3 -1 5 2 5 7 -1 -1 4 0 21 - 341 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 328 SM_AMIGA_5_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 316 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 338 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 333 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 327 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 324 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 336 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 335 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 332 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 63 CLK_030 1 -1 -1 2 0 1 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 - 79 RW_000 5 337 7 2 4 6 79 -1 4 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 80 DSACK1 5 343 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 - 297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 - 342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -111 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 334 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 70 RW 5 342 6 2 0 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 68 A_0_ 5 336 6 1 1 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 333 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 339 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 338 1 0 6 -1 10 0 21 - 82 BGACK_030 5 337 7 0 82 -1 3 0 21 - 34 VMA 5 341 3 0 34 -1 3 0 21 - 80 DSACK1 5 340 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 335 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 337 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 312 CLK_000_D_0_ 3 -1 3 6 0 2 3 4 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 311 CLK_000_D_1_ 3 -1 4 5 0 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 331 SM_AMIGA_i_7_ 3 -1 5 2 2 7 -1 -1 13 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 330 SM_AMIGA_2_ 3 -1 5 2 5 7 -1 -1 4 0 21 - 341 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 328 SM_AMIGA_5_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 316 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 338 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 333 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 327 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 324 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 336 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 335 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 332 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 63 CLK_030 1 -1 -1 2 0 1 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 - 79 RW_000 5 337 7 2 4 6 79 -1 4 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 - 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 341 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 80 DSACK1 5 343 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 338 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 313 CLK_000_D_0_ 3 -1 6 5 0 1 3 5 7 -1 -1 1 0 21 - 312 CLK_000_D_1_ 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21 - 300 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 - 301 inst_AS_030_000_SYNC 3 -1 2 4 0 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 2 5 7 -1 -1 13 1 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 331 SM_AMIGA_5_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 323 SM_AMIGA_6_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 304 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 303 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 306 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 305 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 - 297 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 329 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 309 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 - 342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 330 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 4 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 1 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 335 CIIN_0 3 -1 5 1 4 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 293 un10_ciin_i 3 -1 4 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21 - 79 RW_000 5 337 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 2 6 30 -1 1 0 21 - 70 RW 5 345 6 2 1 7 70 -1 2 0 21 - 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 68 A_0_ 5 340 6 1 0 68 -1 3 0 21 - 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 339 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 80 DSACK1 5 341 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 28 BG_000 5 338 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 @@ -2396,57 +521,899 @@ 2 RESET 0 1 0 2 -1 1 0 21 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 311 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 1 2 3 4 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 5 4 0 1 5 7 -1 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 13 1 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 307 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 327 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 331 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 5 2 1 5 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 329 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 2 1 21 - 322 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 309 CLK_000_D_1_ 3 -1 7 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 312 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 3 5 0 1 3 4 7 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 0 4 0 3 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 3 0 1 3 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 334 SM_AMIGA_i_7_ 3 -1 0 3 0 1 7 -1 -1 3 1 21 + 326 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 320 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 333 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 5 0 21 + 341 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 331 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 323 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 322 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 314 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 308 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 333 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 327 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 329 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 328 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 318 CLK_000_D_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 4 0 2 5 7 63 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 +113 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 6 0 1 4 5 6 7 41 -1 1 0 21 + 79 RW_000 5 336 7 3 4 5 6 79 -1 4 0 21 + 68 A_0_ 5 342 6 2 2 3 68 -1 3 0 21 + 70 RW 5 341 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 340 3 0 34 -1 3 0 21 + 80 DSACK1 5 339 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 2 6 0 1 2 3 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 333 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 4 0 21 + 323 SM_AMIGA_6_ 3 -1 3 4 0 2 3 7 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 4 1 2 5 6 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 304 CYCLE_DMA_0_ 3 -1 6 3 1 5 6 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 305 CYCLE_DMA_1_ 3 -1 1 2 1 5 -1 -1 4 0 21 + 340 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 1 2 0 3 -1 -1 1 0 21 + 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 332 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 331 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 330 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 5 7 63 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +113 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 + 70 RW 5 341 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 340 3 0 34 -1 3 0 21 + 80 DSACK1 5 339 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 + 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 + 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +113 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 336 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 342 6 2 0 2 68 -1 3 0 21 + 70 RW 5 341 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 344 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 343 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 340 3 0 34 -1 3 0 21 + 80 DSACK1 5 339 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 + 333 SM_AMIGA_i_7_ 3 -1 3 4 2 3 5 7 -1 -1 4 0 21 + 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 323 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 332 SM_AMIGA_2_ 3 -1 2 2 2 3 -1 -1 5 0 21 + 326 RST_DLY_0_ 3 -1 5 2 5 6 -1 -1 4 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 330 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 321 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 328 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 + 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 344 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_68 3 -1 4 1 4 -1 -1 2 0 21 + 317 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +114 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 + 79 RW_000 5 337 7 3 4 5 6 79 -1 4 0 21 + 70 RW 5 342 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 + 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 3 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 + 82 BGACK_030 5 339 7 0 82 -1 3 0 21 + 34 VMA 5 341 3 0 34 -1 3 0 21 + 80 DSACK1 5 340 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 338 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 339 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 6 0 1 2 3 4 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 0 4 0 1 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 + 334 SM_AMIGA_i_7_ 3 -1 0 3 0 2 7 -1 -1 3 1 21 + 304 CYCLE_DMA_0_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 331 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 + 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 330 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 333 SM_AMIGA_2_ 3 -1 3 1 3 -1 -1 5 0 21 + 332 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 + 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 327 RST_DLY_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 342 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 + 328 RST_DLY_1_ 3 -1 2 1 2 -1 -1 2 1 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 318 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 5 63 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +115 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 344 6 2 1 5 68 -1 3 0 21 + 70 RW 5 343 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 + 82 BGACK_030 5 340 7 0 82 -1 3 0 21 + 34 VMA 5 342 3 0 34 -1 3 0 21 + 80 DSACK1 5 341 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 339 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 313 CLK_000_D_0_ 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 0 5 2 3 4 5 7 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 + 328 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 342 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 332 SM_AMIGA_5_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 323 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 330 RST_DLY_2_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 0 2 0 3 -1 -1 2 1 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 309 CLK_000_D_2_ 3 -1 7 2 5 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 319 CLK_000_D_3_ 3 -1 7 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 5 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 5 6 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 313 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 2 4 2 5 6 7 -1 -1 3 0 21 + 302 inst_AS_000_DMA 3 -1 0 3 0 5 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 336 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 + 326 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 6 3 0 5 6 -1 -1 3 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 332 inst_CLK_030_H 3 -1 0 2 0 5 -1 -1 8 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 + 327 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 322 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 2 2 1 2 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 309 CLK_000_D_3_ 3 -1 5 2 1 2 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 4 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 0 5 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 4 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 313 CLK_000_D_0_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 + 326 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 + 327 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 + 319 CLK_000_D_2_ 3 -1 7 3 4 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 + 329 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 324 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 331 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 2 2 2 6 -1 -1 2 1 21 + 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 + 310 CLK_000_D_3_ 3 -1 4 2 5 6 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 332 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 311 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 @@ -2457,36 +1424,1012 @@ 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" +116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 41 AS_000 5 -1 4 5 0 1 3 4 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 338 7 3 1 4 6 79 -1 4 0 21 - 68 A_0_ 5 341 6 2 2 6 68 -1 3 0 21 - 70 RW 5 346 6 2 2 7 70 -1 2 0 21 + 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 + 68 A_0_ 5 345 6 2 3 5 68 -1 3 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 + 31 UDS_000 5 -1 3 2 5 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 5 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 314 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 313 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 326 SM_AMIGA_6_ 3 -1 2 5 1 2 3 5 7 -1 -1 3 0 21 + 310 CLK_000_D_3_ 3 -1 7 5 1 2 4 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 1 2 3 4 7 -1 -1 1 0 21 + 328 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 4 0 21 + 322 SM_AMIGA_1_ 3 -1 5 3 1 5 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 309 CLK_000_D_2_ 3 -1 7 3 1 5 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 2 0 5 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 336 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 + 333 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 327 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 324 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 316 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 332 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 N_264 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 4 1 2 -1 -1 1 0 21 + 319 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 318 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 317 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 311 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 5 63 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 313 CLK_000_D_0_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 + 326 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 + 327 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 + 319 CLK_000_D_2_ 3 -1 7 3 4 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 + 329 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 324 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 331 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 2 2 2 6 -1 -1 2 1 21 + 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 + 310 CLK_000_D_3_ 3 -1 4 2 5 6 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 332 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 311 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 4 1 4 5 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 0 5 68 -1 3 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 + 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 333 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 321 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 305 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 318 CLK_000_D_2_ 3 -1 7 2 6 7 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 + 309 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 + 307 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 319 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 59 A_1_ 1 -1 -1 2 5 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 6 2 3 4 5 6 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 2 68 -1 3 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 312 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 313 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 327 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 3 0 21 + 321 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 + 319 CLK_000_D_2_ 3 -1 2 3 2 3 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 1 5 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 + 328 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 326 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 3 2 3 5 -1 -1 2 1 21 + 322 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 310 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 311 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 7 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 0 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 341 7 3 0 4 6 79 -1 4 0 21 + 70 RW 5 346 6 3 0 3 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 347 6 1 5 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 340 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 339 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 338 1 0 6 -1 10 0 21 + 82 BGACK_030 5 343 7 0 82 -1 3 0 21 + 34 VMA 5 345 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 80 DSACK1 5 344 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 342 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 312 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 313 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 5 4 0 5 6 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 1 5 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 5 0 21 + 328 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 + 345 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 333 SM_AMIGA_5_ 3 -1 6 2 2 6 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 321 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 2 1 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 319 CLK_000_D_2_ 3 -1 7 2 1 7 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 310 CLK_000_D_3_ 3 -1 7 2 0 5 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 338 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 311 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 59 A_1_ 1 -1 -1 2 1 6 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 4 1 4 5 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 0 5 68 -1 3 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 + 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 333 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 321 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 305 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 318 CLK_000_D_2_ 3 -1 7 2 6 7 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 + 309 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 + 307 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 319 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 59 A_1_ 1 -1 -1 2 5 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 4 1 4 5 7 81 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 0 5 68 -1 3 0 21 + 70 RW 5 344 6 2 1 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 312 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 + 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 333 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 321 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 305 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 318 CLK_000_D_2_ 3 -1 7 2 6 7 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 + 309 CLK_000_D_3_ 3 -1 7 2 1 5 -1 -1 1 0 21 + 307 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 2 5 6 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 319 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 59 A_1_ 1 -1 -1 2 5 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 312 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 313 CLK_000_D_0_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 + 326 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 + 327 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 + 319 CLK_000_D_2_ 3 -1 7 3 4 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 + 329 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 324 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 331 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 + 330 RST_DLY_1_ 3 -1 2 2 2 6 -1 -1 2 1 21 + 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 321 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 + 310 CLK_000_D_3_ 3 -1 4 2 5 6 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 332 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 311 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 6 68 -1 3 0 21 + 70 RW 5 344 6 2 3 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -2496,11 +2439,11 @@ 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 345 3 0 34 -1 3 0 21 - 80 DSACK1 5 344 7 0 80 -1 2 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -2515,62 +2458,307 @@ 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 340 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 324 SM_AMIGA_6_ 3 -1 0 5 0 2 5 6 7 -1 -1 3 0 21 - 312 CLK_000_D_0_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 2 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 0 7 -1 -1 13 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 3 2 1 3 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 323 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_25 3 -1 2 2 2 4 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 319 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 6 2 2 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 310 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 + 307 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 5 5 2 3 5 6 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 7 4 1 3 5 7 -1 -1 7 0 21 + 317 CLK_000_D_2_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 4 3 4 5 7 -1 -1 1 0 21 + 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 334 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 + 326 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 1 3 0 1 3 -1 -1 3 0 21 + 320 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 331 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 321 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 + 308 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 6 7 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 331 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 334 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 - 333 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 - 328 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 346 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 327 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 322 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 4 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 + 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 328 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +117 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 70 RW 5 345 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 346 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 344 3 0 34 -1 3 0 21 + 80 DSACK1 5 343 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 307 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 327 SM_AMIGA_0_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 1 3 0 1 2 -1 -1 3 0 21 + 321 SM_AMIGA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 317 CLK_000_D_2_ 3 -1 0 3 2 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 + 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 + 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 343 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 319 CLK_000_D_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 318 CLK_000_D_3_ 3 -1 7 1 3 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 + 308 CLK_000_D_4_ 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +115 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 337 7 3 2 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 4 6 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 + 70 RW 5 343 6 2 0 7 70 -1 2 0 21 + 78 SIZE_1_ 5 335 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 344 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 5 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 336 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 + 82 BGACK_030 5 339 7 0 82 -1 3 0 21 + 34 VMA 5 342 3 0 34 -1 3 0 21 + 80 DSACK1 5 341 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 338 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 339 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 307 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 0 4 0 3 5 7 -1 -1 3 0 21 + 308 CLK_000_D_2_ 3 -1 7 4 0 1 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 6 4 0 3 4 7 -1 -1 1 0 21 + 326 RST_DLY_0_ 3 -1 0 3 0 1 2 -1 -1 4 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 325 SM_AMIGA_0_ 3 -1 6 3 0 6 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 + 328 RST_DLY_2_ 3 -1 2 3 0 1 2 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 1 3 0 1 2 -1 -1 2 1 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 0 6 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 0 2 0 3 -1 -1 7 0 21 + 332 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 5 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 342 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 333 SM_AMIGA_i_7_ 3 -1 0 2 0 7 -1 -1 3 1 21 + 330 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 336 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 331 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 337 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 335 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 338 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 317 CLK_000_D_3_ 3 -1 7 1 0 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 @@ -2578,277 +2766,35 @@ 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 4 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21 - 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 3 4 5 7 81 -1 1 0 21 - 40 BERR 5 -1 4 3 1 5 7 40 -1 1 0 21 - 68 A_0_ 5 344 6 2 1 2 68 -1 3 0 21 - 70 RW 5 343 6 2 1 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 342 3 0 34 -1 3 0 21 - 80 DSACK1 5 341 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 0 5 0 1 2 5 7 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 5 5 1 3 4 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 342 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_25 3 -1 0 2 0 4 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 3 2 5 6 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 - 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 319 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 59 A_1_ 1 -1 -1 2 5 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 7 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 - 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21 - 68 A_0_ 5 344 6 2 2 3 68 -1 3 0 21 - 70 RW 5 343 6 2 2 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 342 3 0 34 -1 3 0 21 - 80 DSACK1 5 341 7 0 80 -1 2 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 312 CLK_000_D_0_ 3 -1 4 6 0 1 2 3 5 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 3 5 2 3 4 5 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 - 328 RST_DLY_0_ 3 -1 5 2 1 5 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 4 0 21 - 342 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 327 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 5 2 1 5 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 5 2 1 5 -1 -1 2 1 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 6 2 1 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 5 2 5 6 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 - 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 319 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 4 10 -1 -115 "number of signals after reading design file" +116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 338 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 5 6 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 5 6 30 -1 1 0 21 - 68 A_0_ 5 344 6 2 3 5 68 -1 3 0 21 - 70 RW 5 343 6 2 3 7 70 -1 2 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 6 68 -1 3 0 21 + 70 RW 5 344 6 2 3 7 70 -1 2 0 21 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 @@ -2859,11 +2805,11 @@ 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 342 3 0 34 -1 3 0 21 - 80 DSACK1 5 341 7 0 80 -1 2 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 80 DSACK1 5 342 7 0 80 -1 2 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -2877,81 +2823,448 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 3 4 6 7 -1 -1 1 0 21 - 312 CLK_000_D_0_ 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 1 4 1 3 5 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 1 4 0 1 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 4 2 3 4 7 -1 -1 1 0 21 - 302 inst_AS_000_DMA 3 -1 2 3 2 5 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 6 3 2 5 6 -1 -1 4 0 21 - 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 325 SM_AMIGA_4_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 306 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 3 2 5 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 2 5 6 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 331 inst_CLK_030_H 3 -1 2 2 2 5 -1 -1 8 0 21 - 342 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 3 2 3 6 -1 -1 3 0 21 - 327 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 326 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 320 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_25 3 -1 6 2 6 7 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 313 inst_CLK_OUT_PRE_50 3 -1 0 2 0 6 -1 -1 1 0 21 - 308 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 340 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 + 307 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 5 5 2 3 5 6 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 7 4 1 3 5 7 -1 -1 7 0 21 + 317 CLK_000_D_2_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 4 3 4 5 7 -1 -1 1 0 21 + 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 334 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 + 326 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 1 3 0 1 3 -1 -1 3 0 21 + 320 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 331 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 323 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 321 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 + 308 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 2 6 7 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 330 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 333 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 327 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 322 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 342 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 323 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 319 CLK_000_D_2_ 3 -1 4 1 1 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 310 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 328 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 63 CLK_030 1 -1 -1 2 2 5 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 7 29 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 70 RW 5 344 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 310 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 + 307 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 5 0 2 3 4 5 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 1 4 0 1 5 7 -1 -1 3 0 21 + 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 + 326 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 317 CLK_000_D_2_ 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 2 2 0 2 -1 -1 5 0 21 + 327 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 323 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 322 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 320 SM_AMIGA_1_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 330 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 328 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 2 1 21 + 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 6 2 5 6 -1 -1 1 0 21 + 308 CLK_000_D_3_ 3 -1 6 2 1 7 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 331 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 318 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 309 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 4 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 + 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 + 70 RW 5 344 6 2 2 7 70 -1 2 0 21 + 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 341 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 310 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 306 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 + 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 + 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +116 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 4 0 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 79 RW_000 5 339 7 2 4 6 79 -1 4 0 21 + 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 + 69 SIZE_0_ 5 342 6 1 1 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 341 7 0 82 -1 3 0 21 + 34 VMA 5 343 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 340 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 311 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 + 307 CLK_000_D_3_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 + 300 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 306 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 302 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 + 301 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 + 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 + 319 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 + 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 332 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 303 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 + 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 + 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 + 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 304 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 317 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 6 63 -1 + 59 A_1_ 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 1 10 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index e59fe0e..298c090 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,10 +8,9 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Wed Sep 14 23:54:30 2016 +; DATE Thu Oct 06 21:35:00 2016 -Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 Pin 85 A_DECODE_23_ Pin 68 IPL_2_ @@ -27,30 +26,30 @@ Pin 21 BG_030 Pin 28 BGACK_000 Pin 64 CLK_030 Pin 11 CLK_000 -Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 -Pin 61 CLK_OSZI Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 -Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247 +Pin 61 CLK_OSZI Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137 +Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247 Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 -Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157 -Pin 91 FPU_SENSE +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155 +Pin 91 FPU_SENSE Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 -Pin 30 DTACK +Pin 81 DSACK1 Comb ; S6=1 S9=1 Pair 283 Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 30 DTACK Pin 84 A_DECODE_22_ -Pin 66 E Comb ; S6=1 S9=1 Pair 251 +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 94 A_DECODE_21_ -Pin 36 VPA +Pin 66 E Comb ; S6=1 S9=1 Pair 251 Pin 93 A_DECODE_20_ +Pin 36 VPA Pin 97 A_DECODE_19_ -Pin 86 RST Pin 95 A_DECODE_18_ -Pin 3 RESET Comb ; S6=1 S9=1 Pair 128 +Pin 86 RST Pin 59 A_DECODE_17_ +Pin 3 RESET Comb ; S6=1 S9=1 Pair 128 Pin 96 A_DECODE_16_ Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 @@ -61,25 +60,24 @@ Pin 56 IPL_1_ Pin 67 IPL_0_ Pin 57 FC_0_ Pin 60 A_1_ +Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 287 Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 +Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127 -Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283 Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257 Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133 -Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1 Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1 Node 281 RN_AS_030 Comb ; S6=1 S9=1 Node 203 RN_AS_000 Comb ; S6=1 S9=1 Node 185 RN_UDS_000 Comb ; S6=1 S9=1 Node 191 RN_LDS_000 Comb ; S6=1 S9=1 Node 197 RN_BERR Comb ; S6=1 S9=1 -Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1 Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1 Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1 @@ -87,59 +85,60 @@ Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1 Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1 Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1 Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1 +Node 287 RN_SIZE_1_ Reg ; S6=1 S9=1 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 269 RN_RW_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 -Node 283 RN_DSACK1 Reg ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 Node 173 RN_VMA Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 Node 257 RN_A_0_ Reg ; S6=1 S9=1 Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1 -Node 254 cpu_est_2_ Reg ; S6=1 S9=1 -Node 187 cpu_est_3_ Reg ; S6=1 S9=1 -Node 140 cpu_est_0_ Reg ; S6=1 S9=1 -Node 259 cpu_est_1_ Reg ; S6=1 S9=1 -Node 176 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 239 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 -Node 209 inst_AS_030_D0 Reg ; S6=1 S9=1 -Node 169 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 205 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 163 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 221 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 248 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 253 CYCLE_DMA_1_ Reg ; S6=1 S9=1 -Node 152 SIZE_DMA_0_ Reg ; S6=1 S9=1 -Node 260 SIZE_DMA_1_ Reg ; S6=1 S9=1 -Node 223 inst_VPA_D Reg ; S6=1 S9=1 -Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1 -Node 278 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 193 cpu_est_3_ Reg ; S6=1 S9=1 +Node 259 cpu_est_0_ Reg ; S6=1 S9=1 +Node 253 cpu_est_1_ Reg ; S6=1 S9=1 +Node 176 cpu_est_2_ Reg ; S6=1 S9=1 +Node 110 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 278 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 227 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 +Node 248 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 265 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 103 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 260 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 116 inst_VPA_D Reg ; S6=1 S9=1 +Node 272 CLK_000_D_2_ Reg ; S6=1 S9=1 +Node 187 CLK_000_D_3_ Reg ; S6=1 S9=1 +Node 170 inst_DTACK_D0 Reg ; S6=1 S9=1 Node 113 inst_RESET_OUT Reg ; S6=1 S9=1 +Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1 Node 145 CLK_000_D_0_ Reg ; S6=1 S9=1 -Node 103 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 266 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1 -Node 272 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 170 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 194 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 164 IPL_D0_2_ Reg ; S6=1 S9=1 -Node 217 CLK_000_D_2_ Reg ; S6=1 S9=1 -Node 233 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 227 inst_LDS_000_INT Reg ; S6=1 S9=1 -Node 182 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 188 inst_UDS_000_INT Reg ; S6=1 S9=1 -Node 134 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 265 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 119 SM_AMIGA_1_ Reg ; S6=1 S9=1 -Node 289 SM_AMIGA_0_ Reg ; S6=1 S9=1 -Node 121 RST_DLY_0_ Reg ; S6=1 S9=1 -Node 110 RST_DLY_1_ Reg ; S6=1 S9=1 -Node 104 RST_DLY_2_ Reg ; S6=1 S9=1 -Node 158 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 193 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 115 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 109 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 146 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 -Node 211 CIIN_0 Comb ; S6=1 S9=1 +Node 211 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 194 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 146 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 266 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 188 CLK_000_D_4_ Reg ; S6=1 S9=1 +Node 104 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 169 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 140 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 239 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 134 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 221 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 152 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 119 SM_AMIGA_0_ Reg ; S6=1 S9=1 +Node 163 RST_DLY_0_ Reg ; S6=1 S9=1 +Node 121 RST_DLY_1_ Reg ; S6=1 S9=1 +Node 115 RST_DLY_2_ Reg ; S6=1 S9=1 +Node 254 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 109 inst_DSACK1_INT Reg ; S6=1 S9=1 +Node 223 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 182 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 164 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 158 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 233 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 205 CIIN_0 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 739fedf..48159d7 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Wed Sep 14 23:54:30 2016 -End : Wed Sep 14 23:54:30 2016 $$$ Elapsed time: 00:00:00 +Start: Thu Oct 06 21:35:00 2016 +End : Thu Oct 06 21:35:00 2016 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 24 => 72% - 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 23 => 69% + 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 23 => 69% + 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 21 => 63% 2 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 26 => 78% - 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 27 => 81% - 4 | 16 | 8 | 8 => 100% | 8 | 4 => 50% | 33 | 31 => 93% - 5 | 16 | 5 | 5 => 100% | 8 | 5 => 62% | 33 | 22 => 66% + 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 25 => 75% + 4 | 16 | 7 | 7 => 100% | 8 | 4 => 50% | 33 | 30 => 90% + 5 | 16 | 5 | 5 => 100% | 8 | 5 => 62% | 33 | 24 => 72% 6 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 26 => 78% - 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 29 => 87% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 27 => 81% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 26.00 => 78% + | Avg number of array inputs in used blocks : 25.25 => 76% * Input/Clock Signal count: 24 -> placed: 24 = 100% @@ -42,12 +42,12 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 8 => 100% Macrocells : 128 81 => 63% - PT Clusters : 128 52 => 40% - - Single PT Clusters : 128 36 => 28% + PT Clusters : 128 51 => 39% + - Single PT Clusters : 128 37 => 28% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 115] Route [ 0] +* Attempts: Place [ 116] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -69,21 +69,21 @@ ___|__|__|____|____________________________________________________________ 10| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 13| 4| IO| 42|=> 0.2.|4567| AS_000 - 14| 7| IO| 82|=> ....|4..7| AS_030 + 13| 4| IO| 42|=> 0...|4.67| AS_000 + 14| 7| IO| 82|=> 0...|45.7| AS_030 15| 0|OUT| 92|=> ....|....| AVEC - 16| 6| IO| 69|=> ...3|.5..| A_0_ + 16| 6| IO| 69|=> .1..|....| A_0_ |=> Paired w/: RN_A_0_ - 17| 5|INP| 60|=> ....|.5..| A_1_ - 18| 0|INP| 96|=> ..2.|4..7| A_DECODE_16_ - 19| 5|INP| 59|=> ..2.|4..7| A_DECODE_17_ - 20| 0|INP| 95|=> ..2.|4..7| A_DECODE_18_ - 21| 0|INP| 97|=> ..2.|4..7| A_DECODE_19_ + 17| 5|INP| 60|=> 0...|....| A_1_ + 18| 0|INP| 96|=> ....|45.7| A_DECODE_16_ + 19| 5|INP| 59|=> ....|45.7| A_DECODE_17_ + 20| 0|INP| 95|=> ....|45.7| A_DECODE_18_ + 21| 0|INP| 97|=> ....|45.7| A_DECODE_19_ 22| 0|INP| 93|=> ....|4...| A_DECODE_20_ 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ - 26| 4| IO| 41|=> 0...|....| BERR + 26| 4| IO| 41|=> ..2.|....| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 @@ -93,105 +93,108 @@ ___|__|__|____|____________________________________________________________ 31| 4|OUT| 47|=> ....|....| CIIN 32| 4|NOD| . |=> ....|4...| CIIN_0 33| +|INP| 11|=> .1..|....| CLK_000 - 34| 1|NOD| . |=> 01.3|..67| CLK_000_D_0_ - 35| 7|NOD| . |=> 01.3|4.67| CLK_000_D_1_ - 36| 4|NOD| . |=> .1..|....| CLK_000_D_2_ - 37| +|INP| 64|=> ..2.|.5..| CLK_030 - 38| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 39| 1|OUT| 10|=> ....|....| CLK_EXP - 40| +|Cin| 61|=> ....|....| CLK_OSZI - 41| 6|NOD| . |=> ..2.|.56.| CYCLE_DMA_0_ - 42| 6|NOD| . |=> ..2.|.56.| CYCLE_DMA_1_ - 43| 7| IO| 81|=> ....|....| DSACK1 - |=> Paired w/: RN_DSACK1 - 44| 0|OUT| 98|=> ....|....| DS_030 - 45| 3|INP| 30|=> ....|...7| DTACK - 46| 6|OUT| 66|=> ....|....| E - 47| 5|INP| 57|=> ..2.|4..7| FC_0_ - 48| 5|INP| 58|=> ..2.|4..7| FC_1_ - 49| 7|OUT| 78|=> ....|....| FPU_CS - 50| 0|INP| 91|=> ....|4..7| FPU_SENSE - 51| 1| IO| 8|=> ....|....| IPL_030_0_ + 34| 1|NOD| . |=> 0.23|.567| CLK_000_D_0_ + 35| 7|NOD| . |=> 0.23|.567| CLK_000_D_1_ + 36| 7|NOD| . |=> 0.23|....| CLK_000_D_2_ + 37| 3|NOD| . |=> 0.23|.5..| CLK_000_D_3_ + 38| 3|NOD| . |=> ....|.5..| CLK_000_D_4_ + 39| +|INP| 64|=> ....|..6.| CLK_030 + 40| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 41| 1|OUT| 10|=> ....|....| CLK_EXP + 42| +|Cin| 61|=> ....|....| CLK_OSZI + 43| 0|NOD| . |=> 0...|..6.| CYCLE_DMA_0_ + 44| 6|NOD| . |=> ....|..6.| CYCLE_DMA_1_ + 45| 7|OUT| 81|=> ....|....| DSACK1 + 46| 0|OUT| 98|=> ....|....| DS_030 + 47| 3|INP| 30|=> ..2.|....| DTACK + 48| 6|OUT| 66|=> ....|....| E + 49| 5|INP| 57|=> ....|45.7| FC_0_ + 50| 5|INP| 58|=> ....|45.7| FC_1_ + 51| 7|OUT| 78|=> ....|....| FPU_CS + 52| 0|INP| 91|=> ....|4..7| FPU_SENSE + 53| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 52| 1| IO| 7|=> ....|....| IPL_030_1_ + 54| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 53| 1| IO| 9|=> ....|....| IPL_030_2_ + 55| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 54| 6|INP| 67|=> .12.|....| IPL_0_ - 55| 5|INP| 56|=> .1.3|....| IPL_1_ - 56| 6|INP| 68|=> .12.|....| IPL_2_ - 57| 2|NOD| . |=> .1..|....| IPL_D0_0_ - 58| 3|NOD| . |=> .1..|....| IPL_D0_1_ - 59| 2|NOD| . |=> .1..|....| IPL_D0_2_ - 60| 3| IO| 31|=> ..2.|.56.| LDS_000 - 61| 1|OUT| 3|=> ....|....| RESET - 62| 6|NOD| . |=> ....|..6.| RN_A_0_ + 56| 6|INP| 67|=> .1.3|....| IPL_0_ + 57| 5|INP| 56|=> .1..|....| IPL_1_ + 58| 6|INP| 68|=> .1..|..6.| IPL_2_ + 59| 3|NOD| . |=> .1..|....| IPL_D0_0_ + 60| 1|NOD| . |=> .1..|....| IPL_D0_1_ + 61| 6|NOD| . |=> .1..|....| IPL_D0_2_ + 62| 3| IO| 31|=> ....|..67| LDS_000 + 63| 1|OUT| 3|=> ....|....| RESET + 64| 6|NOD| . |=> ....|..6.| RN_A_0_ |=> Paired w/: A_0_ - 63| 7|NOD| . |=> 0123|4567| RN_BGACK_030 + 65| 7|NOD| . |=> 0123|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 - 64| 3|NOD| . |=> ...3|....| RN_BG_000 + 66| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 65| 7|NOD| . |=> ....|...7| RN_DSACK1 - |=> Paired w/: DSACK1 - 66| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 67| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 67| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 68| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 68| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 69| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 69| 6|NOD| . |=> ....|..6.| RN_RW + 70| 6|NOD| . |=> ....|..6.| RN_RW |=> Paired w/: RW - 70| 7|NOD| . |=> ....|...7| RN_RW_000 + 71| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 71| 3|NOD| . |=> 0..3|....| RN_VMA + 72| 6|NOD| . |=> ....|..6.| RN_SIZE_0_ + |=> Paired w/: SIZE_0_ + 73| 7|NOD| . |=> ....|...7| RN_SIZE_1_ + |=> Paired w/: SIZE_1_ + 74| 3|NOD| . |=> ..23|....| RN_VMA |=> Paired w/: VMA - 72| +|INP| 86|=> 0123|4567| RST - 73| 0|NOD| . |=> 0...|....| RST_DLY_0_ - 74| 0|NOD| . |=> 0...|....| RST_DLY_1_ - 75| 0|NOD| . |=> 0...|....| RST_DLY_2_ - 76| 6| IO| 71|=> ...3|...7| RW + 75| +|INP| 86|=> 0123|.567| RST + 76| 2|NOD| . |=> 0.2.|....| RST_DLY_0_ + 77| 0|NOD| . |=> 0.2.|....| RST_DLY_1_ + 78| 0|NOD| . |=> 0.2.|....| RST_DLY_2_ + 79| 6| IO| 71|=> ....|.5.7| RW |=> Paired w/: RN_RW - 77| 7| IO| 80|=> ....|456.| RW_000 + 80| 7| IO| 80|=> ....|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 78| 6| IO| 70|=> ....|.5..| SIZE_0_ - 79| 7| IO| 79|=> ....|.5..| SIZE_1_ - 80| 2|NOD| . |=> ..2.|..67| SIZE_DMA_0_ - 81| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ - 82| 7|NOD| . |=> .1..|...7| SM_AMIGA_0_ - 83| 0|NOD| . |=> 0...|...7| SM_AMIGA_1_ - 84| 0|NOD| . |=> 0...|....| SM_AMIGA_2_ - 85| 0|NOD| . |=> 0...|....| SM_AMIGA_3_ - 86| 6|NOD| . |=> 0..3|..6.| SM_AMIGA_4_ - 87| 3|NOD| . |=> ...3|..6.| SM_AMIGA_5_ - 88| 1|NOD| . |=> .1.3|.5.7| SM_AMIGA_6_ - 89| 1|NOD| . |=> .12.|...7| SM_AMIGA_i_7_ - 90| 3| IO| 32|=> ..2.|.56.| UDS_000 - 91| 3| IO| 35|=> ....|....| VMA + 81| 6| IO| 70|=> .1..|....| SIZE_0_ + |=> Paired w/: RN_SIZE_0_ + 82| 7| IO| 79|=> .1..|....| SIZE_1_ + |=> Paired w/: RN_SIZE_1_ + 83| 0|NOD| . |=> 0...|.5.7| SM_AMIGA_0_ + 84| 2|NOD| . |=> 0.2.|....| SM_AMIGA_1_ + 85| 2|NOD| . |=> ..2.|....| SM_AMIGA_2_ + 86| 2|NOD| . |=> ..2.|....| SM_AMIGA_3_ + 87| 2|NOD| . |=> ..2.|.5..| SM_AMIGA_4_ + 88| 3|NOD| . |=> ..23|....| SM_AMIGA_5_ + 89| 5|NOD| . |=> .1.3|.5.7| SM_AMIGA_6_ + 90| 5|NOD| . |=> ....|.5.7| SM_AMIGA_i_7_ + 91| 3| IO| 32|=> ....|..67| UDS_000 + 92| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 92| +|INP| 36|=> ....|.5..| VPA - 93| 1|NOD| . |=> 01.3|..6.| cpu_est_0_ - 94| 6|NOD| . |=> 0..3|..6.| cpu_est_1_ - 95| 6|NOD| . |=> 0..3|..6.| cpu_est_2_ - 96| 3|NOD| . |=> 0..3|..6.| cpu_est_3_ - 97| 5|NOD| . |=> ...3|.5..| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 98| 5|NOD| . |=> ..2.|.5..| inst_AMIGA_BUS_ENABLE_DMA_LOW - 99| 2|NOD| . |=> ..2.|.5.7| inst_AS_000_DMA - 100| 3|NOD| . |=> ...3|4...| inst_AS_000_INT - 101| 2|NOD| . |=> .123|....| inst_AS_030_000_SYNC - 102| 4|NOD| . |=> ..23|4..7| inst_AS_030_D0 - 103| 4|NOD| . |=> ..2.|.56.| inst_BGACK_030_INT_D - 104| 2|NOD| . |=> ..2.|.5..| inst_CLK_030_H - 105| 6|NOD| . |=> ....|..67| inst_CLK_OUT_PRE_25 - 106| 0|NOD| . |=> 0...|..6.| inst_CLK_OUT_PRE_50 - 107| 7|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_D - 108| 5|NOD| . |=> 0...|.5..| inst_DS_000_DMA - 109| 3|NOD| . |=> ...3|....| inst_DS_000_ENABLE - 110| 7|NOD| . |=> 0...|....| inst_DTACK_D0 - 111| 5|NOD| . |=> ...3|.5..| inst_LDS_000_INT - 112| 0|NOD| . |=> 0123|4.67| inst_RESET_OUT - 113| 3|NOD| . |=> ...3|....| inst_UDS_000_INT - 114| 5|NOD| . |=> 0..3|....| inst_VPA_D - 115| +|INP| 14|=> 0123|4.67| nEXP_SPACE + 93| +|INP| 36|=> 0...|....| VPA + 94| 6|NOD| . |=> ..23|..6.| cpu_est_0_ + 95| 6|NOD| . |=> ..23|..6.| cpu_est_1_ + 96| 3|NOD| . |=> ..23|..6.| cpu_est_2_ + 97| 3|NOD| . |=> ..23|..6.| cpu_est_3_ + 98| 0|NOD| . |=> 0..3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 99| 0|NOD| . |=> 0.2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 100| 6|NOD| . |=> ....|..67| inst_AS_000_DMA + 101| 5|NOD| . |=> ....|45..| inst_AS_000_INT + 102| 5|NOD| . |=> ...3|.5..| inst_AS_030_000_SYNC + 103| 7|NOD| . |=> ...3|45..| inst_AS_030_D0 + 104| 7|NOD| . |=> 0...|.567| inst_BGACK_030_INT_D + 105| 6|NOD| . |=> ....|..6.| inst_CLK_030_H + 106| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 + 107| 4|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_D + 108| 0|NOD| . |=> 0...|...7| inst_DSACK1_INT + 109| 6|NOD| . |=> 0...|..6.| inst_DS_000_DMA + 110| 5|NOD| . |=> ...3|.5..| inst_DS_000_ENABLE + 111| 2|NOD| . |=> ..2.|....| inst_DTACK_D0 + 112| 1|NOD| . |=> .1.3|....| inst_LDS_000_INT + 113| 0|NOD| . |=> 0123|4.67| inst_RESET_OUT + 114| 1|NOD| . |=> .1.3|....| inst_UDS_000_INT + 115| 0|NOD| . |=> ..23|....| inst_VPA_D + 116| +|INP| 14|=> 0123|4567| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -312,19 +315,19 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| RST_DLY_2_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 1| CYCLE_DMA_0_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| RST_DLY_1_|NOD| | S | 2 :+: 1| 4 to [ 6]| 1 XOR to [ 6] + 5|inst_DSACK1_INT|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8|inst_RESET_OUT|NOD| | S | 2 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| | ? | | S | | 4 free | 1 XOR free + 9| RST_DLY_2_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free -12| SM_AMIGA_1_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13| RST_DLY_0_|NOD| | S | 4 | 4 to [13]| 1 XOR free +12| SM_AMIGA_0_|NOD| | S | 4 | 4 to [12]| 1 XOR free +13| RST_DLY_1_|NOD| | S | 2 :+: 1| 4 to [13]| 1 XOR to [13] 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -338,20 +341,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DS_030|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 0| DS_030|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| CYCLE_DMA_0_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 9] logic PT(s) 4| AVEC|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 5| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 14] logic PT(s) - 6| RST_DLY_1_|NOD| | S | 2 :+: 1|=> can support up to [ 9] logic PT(s) + 5|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 6|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) - 9| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 10] logic PT(s) -12| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) -13| RST_DLY_0_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 8|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 9| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) +10| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) +13| RST_DLY_1_|NOD| | S | 2 :+: 1|=> can support up to [ 14] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -364,19 +367,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1|inst_CLK_OUT_PRE_50|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2| RST_DLY_2_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1| CYCLE_DMA_0_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6| RST_DLY_1_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 5|inst_DSACK1_INT|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 8|inst_RESET_OUT|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 92 93 94 95 -10| | | | => | 2 3 4 5 | 93 94 95 96 + 9| RST_DLY_2_|NOD| | => | 1 2 3 4 | 92 93 94 95 +10| inst_VPA_D|NOD| | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 -12| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 94 95 96 97 -13| RST_DLY_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 +12| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 +13| RST_DLY_1_|NOD| | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- @@ -428,37 +431,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] - [MCell 1 |103|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 1 |103|NOD CYCLE_DMA_0_| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD RST_DLY_2_| |*] + [MCell 2 |104|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] [MCell 3 |106| -| | ] 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD SM_AMIGA_2_| |*] + [MCell 5 |109|NOD inst_DSACK1_INT| |*] 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD RST_DLY_1_| |*] + [MCell 6 |110|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] [MCell 8 |113|NOD inst_RESET_OUT| |*] - [MCell 9 |115|NOD SM_AMIGA_3_| |*] + [MCell 9 |115|NOD RST_DLY_2_| |*] 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116| -| | ] + [MCell 10 |116|NOD inst_VPA_D| |*] [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119|NOD SM_AMIGA_1_| |*] - [MCell 13 |121|NOD RST_DLY_0_| |*] + [MCell 12 |119|NOD SM_AMIGA_0_| |*] + [MCell 13 |121|NOD RST_DLY_1_| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] @@ -471,38 +474,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 0 ( 173)| RN_VMA -Mux02| Mcel 1 10 ( 140)| cpu_est_0_ -Mux03| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux04| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux00| Mcel 0 13 ( 121)| RST_DLY_1_ +Mux01| ... | ... +Mux02| Mcel 0 5 ( 109)| inst_DSACK1_INT +Mux03| Mcel 2 9 ( 163)| RST_DLY_0_ +Mux04| Mcel 7 2 ( 272)| CLK_000_D_2_ Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| ... | ... -Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux07| Mcel 3 9 ( 187)| CLK_000_D_3_ Mux08| ... | ... -Mux09| Mcel 0 1 ( 103)| inst_CLK_OUT_PRE_50 +Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| Mcel 1 13 ( 145)| CLK_000_D_0_ -Mux11| ... | ... -Mux12| Mcel 6 13 ( 265)| SM_AMIGA_4_ -Mux13| ... | ... +Mux11| IOPin 5 0 ( 60)| A_1_ +Mux12| Mcel 0 1 ( 103)| CYCLE_DMA_0_ +Mux13| Input Pin ( 36)| VPA Mux14| ... | ... -Mux15| Mcel 0 6 ( 110)| RST_DLY_1_ +Mux15| Mcel 0 6 ( 110)| inst_AMIGA_BUS_ENABLE_DMA_LOW Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 4 0 ( 41)| BERR -Mux18| Mcel 0 5 ( 109)| SM_AMIGA_2_ -Mux19| Mcel 0 9 ( 115)| SM_AMIGA_3_ +Mux17| ... | ... +Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 7 6 ( 278)| inst_DTACK_D0 -Mux22| Mcel 0 2 ( 104)| RST_DLY_2_ -Mux23| Mcel 6 6 ( 254)| cpu_est_2_ -Mux24| Mcel 0 12 ( 119)| SM_AMIGA_1_ -Mux25| Mcel 0 13 ( 121)| RST_DLY_0_ +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 0 2 ( 104)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux23| ... | ... +Mux24| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux25| Mcel 6 13 ( 265)| inst_DS_000_DMA Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| cpu_est_1_ +Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... -Mux29| ... | ... -Mux30| Mcel 5 1 ( 223)| inst_VPA_D -Mux31| Mcel 5 0 ( 221)| inst_DS_000_DMA +Mux29| Mcel 0 9 ( 115)| RST_DLY_2_ +Mux30| Mcel 2 13 ( 169)| SM_AMIGA_1_ +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -521,15 +524,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 3| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT 5| IPL_030_0_| IO| | S |10 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 7| | ? | | S | | 4 to [ 6]| 1 XOR free - 8| AHIGH_29_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 6|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 7| | ? | | S | | 4 free | 1 XOR free + 8| AHIGH_29_| IO| | S | 1 | 4 to [ 6]| 1 XOR to [ 8] for 1 PT sig 9| IPL_030_1_| IO| | S |10 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| cpu_est_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -11| | ? | | S | | 4 to [10]| 1 XOR free -12| AHIGH_31_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +10|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +11| | ? | | S | | 4 free | 1 XOR free +12| AHIGH_31_| IO| | S | 1 | 4 to [10]| 1 XOR to [12] for 1 PT sig 13| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [14]| 1 XOR to [14] +14| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -547,17 +550,17 @@ _|_________________|__|__|___|_____|_______________________________________ 2| RESET|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) 3| | ? | | S | |=> can support up to [ 4] logic PT(s) 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 10] logic PT(s) - 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 10] logic PT(s) - 6| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 15] logic PT(s) + 6|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 14] logic PT(s) -10| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 6] logic PT(s) + 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 15] logic PT(s) +10|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) 11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) +12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) 13| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) -14| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 13] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) +14| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments @@ -573,15 +576,15 @@ _|_________________|__|_____|____________________|________________________ 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) - 6| SM_AMIGA_6_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 6|inst_LDS_000_INT|NOD| | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| AHIGH_29_| IO| | => | 1 2 3 ( 4)| 9 8 7 ( 6) 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 -10| cpu_est_0_|NOD| | => | 2 3 4 5 | 8 7 6 5 +10|inst_UDS_000_INT|NOD| | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) 13| CLK_000_D_0_|NOD| | => | 3 4 5 6 | 7 6 5 4 -14| SM_AMIGA_i_7_|NOD| | => | 4 5 6 7 | 6 5 4 3 +14| IPL_D0_1_|NOD| | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== @@ -649,7 +652,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD SM_AMIGA_6_| |*] + [MCell 6 |134|NOD inst_LDS_000_INT| |*] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] @@ -659,7 +662,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 5| IO AHIGH_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD cpu_est_0_| |*] + [MCell 10 |140|NOD inst_UDS_000_INT| |*] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] @@ -669,7 +672,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD SM_AMIGA_i_7_| |*] + [MCell 14 |146|NOD IPL_D0_1_| |*] [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -680,30 +683,30 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ Mux01| ... | ... -Mux02| Mcel 4 13 ( 217)| CLK_000_D_2_ +Mux02| Mcel 1 10 ( 140)| inst_UDS_000_INT Mux03| Input Pin ( 11)| CLK_000 Mux04| IOPin 6 3 ( 68)| IPL_2_ Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ -Mux07| Mcel 2 14 ( 170)| IPL_D0_0_ -Mux08| Mcel 2 10 ( 164)| IPL_D0_2_ -Mux09| Mcel 1 14 ( 146)| SM_AMIGA_i_7_ -Mux10| Mcel 1 13 ( 145)| CLK_000_D_0_ -Mux11| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC -Mux12| Mcel 1 10 ( 140)| cpu_est_0_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 7 2 ( 272)| inst_CLK_OUT_PRE_D -Mux15| ... | ... -Mux16| ... | ... -Mux17| Mcel 3 14 ( 194)| IPL_D0_1_ +Mux06| IOPin 7 6 ( 79)| SIZE_1_ +Mux07| ... | ... +Mux08| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux09| Mcel 1 14 ( 146)| IPL_D0_1_ +Mux10| Mcel 3 14 ( 194)| IPL_D0_0_ +Mux11| Mcel 6 14 ( 266)| IPL_D0_2_ +Mux12| ... | ... +Mux13| ... | ... +Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux15| IOPin 6 4 ( 69)| A_0_ +Mux16| Mcel 1 9 ( 139)| RN_IPL_030_1_ +Mux17| ... | ... Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux19| Mcel 7 13 ( 289)| SM_AMIGA_0_ +Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| IOPin 5 4 ( 56)| IPL_1_ Mux22| ... | ... -Mux23| Mcel 1 6 ( 134)| SM_AMIGA_6_ +Mux23| Mcel 1 6 ( 134)| inst_LDS_000_INT Mux24| Input Pin ( 86)| RST -Mux25| ... | ... +Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ Mux28| Mcel 1 5 ( 133)| RN_IPL_030_0_ @@ -724,19 +727,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| SIZE_DMA_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 2| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 6]| 1 XOR to [ 6] as logic PT - 7| | ? | | S | | 4 to [ 6]| 1 XOR free + 6| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 6]| 1 XOR to [ 6] as logic PT + 7| | ? | | S | | 4 free | 1 XOR free 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_AS_000_DMA|NOD| | S | 7 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| IPL_D0_2_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig + 9| RST_DLY_0_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free +10| SM_AMIGA_3_|NOD| | S | 5 | 4 to [10]| 1 XOR to [10] as logic PT 11| | ? | | S | | 4 free | 1 XOR free -12| AHIGH_25_| IO| | S | 1 | 4 to [13]| 1 XOR to [12] for 1 PT sig -13|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [13]| 1 XOR to [13] as logic PT -14| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| SM_AMIGA_1_|NOD| | S | 4 | 4 to [13]| 1 XOR free +14| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -751,19 +754,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 2| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| AHIGH_26_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 6|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 9|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 18] logic PT(s) -10| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) -13|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 18] logic PT(s) -14| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 6| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) + 9| RST_DLY_0_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) +10| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13| SM_AMIGA_1_|NOD| | S | 4 |=> can support up to [ 18] logic PT(s) +14| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -776,19 +779,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2| SIZE_DMA_0_|NOD| | => | 6 7 0 1 | 21 22 15 16 + 2| SM_AMIGA_4_|NOD| | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 4| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) 5| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 - 6|inst_CLK_030_H|NOD| | => | 0 1 2 3 | 15 16 17 18 + 6| SM_AMIGA_2_|NOD| | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) - 9|inst_AS_000_DMA|NOD| | => | 1 2 3 4 | 16 17 18 19 -10| IPL_D0_2_|NOD| | => | 2 3 4 5 | 17 18 19 20 + 9| RST_DLY_0_|NOD| | => | 1 2 3 4 | 16 17 18 19 +10| SM_AMIGA_3_|NOD| | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 -13|inst_AS_030_000_SYNC|NOD| | => | 3 4 5 6 | 18 19 20 21 -14| IPL_D0_0_|NOD| | => | 4 5 6 7 | 19 20 21 22 +13| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 18 19 20 21 +14| inst_DTACK_D0|NOD| | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== @@ -843,7 +846,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD SIZE_DMA_0_| |*] + [MCell 2 |152|NOD SM_AMIGA_4_| |*] [MCell 3 |154| -| | ] 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] @@ -853,27 +856,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158|NOD inst_CLK_030_H| |*] + [MCell 6 |158|NOD SM_AMIGA_2_| |*] [MCell 7 |160| -| | ] 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] [MCell 8 |161| IO AHIGH_24_| | ] - [MCell 9 |163|NOD inst_AS_000_DMA| |*] + [MCell 9 |163|NOD RST_DLY_0_| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164|NOD IPL_D0_2_| |*] + [MCell 10 |164|NOD SM_AMIGA_3_| |*] [MCell 11 |166| -| | ] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] [MCell 12 |167| IO AHIGH_25_| | ] - [MCell 13 |169|NOD inst_AS_030_000_SYNC| |*] + [MCell 13 |169|NOD SM_AMIGA_1_| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] - [MCell 14 |170|NOD IPL_D0_0_| |*] + [MCell 14 |170|NOD inst_DTACK_D0| |*] [MCell 15 |172| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -882,39 +885,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 2 2 ( 152)| SIZE_DMA_0_ -Mux03| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux04| Input Pin ( 64)| CLK_030 +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 3 0 ( 173)| RN_VMA +Mux02| Mcel 0 9 ( 115)| RST_DLY_2_ +Mux03| Mcel 2 9 ( 163)| RST_DLY_0_ +Mux04| Mcel 3 6 ( 182)| SM_AMIGA_5_ Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| ... | ... -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 1 14 ( 146)| SM_AMIGA_i_7_ -Mux10| ... | ... -Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| Mcel 2 9 ( 163)| inst_AS_000_DMA -Mux14| Mcel 4 5 ( 205)| inst_BGACK_030_INT_D -Mux15| ... | ... -Mux16| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux18| Mcel 2 6 ( 158)| inst_CLK_030_H +Mux06| ... | ... +Mux07| Mcel 3 9 ( 187)| CLK_000_D_3_ +Mux08| Mcel 0 10 ( 116)| inst_VPA_D +Mux09| Mcel 2 6 ( 158)| SM_AMIGA_2_ +Mux10| Mcel 1 13 ( 145)| CLK_000_D_0_ +Mux11| Mcel 2 13 ( 169)| SM_AMIGA_1_ +Mux12| Mcel 6 9 ( 259)| cpu_est_0_ +Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux14| IOPin 3 5 ( 30)| DTACK +Mux15| Mcel 0 6 ( 110)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 2 14 ( 170)| inst_DTACK_D0 Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 86)| RST -Mux22| IOPin 6 3 ( 68)| IPL_2_ -Mux23| Mcel 6 2 ( 248)| CYCLE_DMA_0_ -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| ... | ... -Mux26| IOPin 4 1 ( 42)| AS_000 -Mux27| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux28| ... | ... +Mux21| Mcel 3 13 ( 193)| cpu_est_3_ +Mux22| Mcel 2 2 ( 152)| SM_AMIGA_4_ +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 0 13 ( 121)| RST_DLY_1_ +Mux26| Mcel 2 10 ( 164)| SM_AMIGA_3_ +Mux27| ... | ... +Mux28| Mcel 7 2 ( 272)| CLK_000_D_2_ Mux29| ... | ... -Mux30| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC -Mux31| Mcel 5 12 ( 239)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux32| Mcel 6 5 ( 253)| CYCLE_DMA_1_ +Mux30| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux31| ... | ... +Mux32| Mcel 6 5 ( 253)| cpu_est_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Macrocell (MCell) Cluster Assignments @@ -928,19 +931,19 @@ Mux32| Mcel 6 5 ( 253)| CYCLE_DMA_1_ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 2| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [ 2]| 1 XOR to [ 2] 3| | ? | | S | | 4 free | 1 XOR free 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 6]| 1 XOR free + 6| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| cpu_est_3_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free -10|inst_UDS_000_INT|NOD| | S | 2 | 4 to [10]| 1 XOR free + 9| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| SM_AMIGA_5_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +13| cpu_est_3_|NOD| | S | 4 | 4 to [13]| 1 XOR free +14| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -955,19 +958,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) 1| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 2|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 2| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 9] logic PT(s) 3| | ? | | S | |=> can support up to [ 9] logic PT(s) 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 6|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| UDS_000| IO| | S | 1 |=> can support up to [ 10] logic PT(s) - 9| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) -10|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) + 6| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 18] logic PT(s) + 9| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +10| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) 12| LDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) -13| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) -14| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +13| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 18] logic PT(s) +14| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -980,19 +983,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2|inst_AS_000_INT|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6|inst_DS_000_ENABLE|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6| SM_AMIGA_5_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 - 9| cpu_est_3_|NOD| | => | 1 2 3 4 | 34 33 32 31 -10|inst_UDS_000_INT|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9| CLK_000_D_3_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10| CLK_000_D_4_|NOD| | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| IPL_D0_1_|NOD| | => | 4 5 6 7 | 31 30 29 28 +13| cpu_est_3_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| IPL_D0_0_|NOD| | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -1049,7 +1052,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD inst_AS_000_INT| |*] + [MCell 2 |176|NOD cpu_est_2_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] @@ -1059,27 +1062,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD inst_DS_000_ENABLE| |*] + [MCell 6 |182|NOD SM_AMIGA_5_| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] - [MCell 9 |187|NOD cpu_est_3_| |*] + [MCell 9 |187|NOD CLK_000_D_3_| |*] 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD inst_UDS_000_INT| |*] + [MCell 10 |188|NOD CLK_000_D_4_| |*] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD SM_AMIGA_5_| |*] + [MCell 13 |193|NOD cpu_est_3_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD IPL_D0_1_| |*] + [MCell 14 |194|NOD IPL_D0_0_| |*] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1088,39 +1091,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| Mcel 3 0 ( 173)| RN_VMA -Mux02| Mcel 1 6 ( 134)| SM_AMIGA_6_ -Mux03| IOPin 5 4 ( 56)| IPL_1_ +Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux01| Mcel 5 12 ( 239)| inst_DS_000_ENABLE +Mux02| Mcel 3 1 ( 175)| RN_BG_000 +Mux03| Mcel 3 2 ( 176)| cpu_est_2_ Mux04| IOPin 2 6 ( 21)| BG_030 Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| ... | ... -Mux07| Mcel 3 9 ( 187)| cpu_est_3_ -Mux08| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux09| Mcel 6 13 ( 265)| SM_AMIGA_4_ -Mux10| Mcel 1 13 ( 145)| CLK_000_D_0_ -Mux11| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC -Mux12| Mcel 6 9 ( 259)| cpu_est_1_ +Mux07| Mcel 7 6 ( 278)| inst_AS_030_D0 +Mux08| Mcel 0 10 ( 116)| inst_VPA_D +Mux09| ... | ... +Mux10| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC +Mux11| Mcel 1 6 ( 134)| inst_LDS_000_INT +Mux12| Mcel 1 10 ( 140)| inst_UDS_000_INT Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 5 4 ( 227)| inst_LDS_000_INT -Mux15| Mcel 5 1 ( 223)| inst_VPA_D -Mux16| Mcel 3 6 ( 182)| inst_DS_000_ENABLE -Mux17| Mcel 3 1 ( 175)| RN_BG_000 -Mux18| IOPin 6 4 ( 69)| A_0_ +Mux14| Mcel 7 2 ( 272)| CLK_000_D_2_ +Mux15| ... | ... +Mux16| Mcel 3 6 ( 182)| SM_AMIGA_5_ +Mux17| ... | ... +Mux18| Mcel 3 0 ( 173)| RN_VMA Mux19| ... | ... -Mux20| Mcel 3 10 ( 188)| inst_UDS_000_INT +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST -Mux22| ... | ... -Mux23| Mcel 6 6 ( 254)| cpu_est_2_ -Mux24| Mcel 1 10 ( 140)| cpu_est_0_ -Mux25| IOPin 6 6 ( 71)| RW +Mux22| Mcel 0 2 ( 104)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 3 9 ( 187)| CLK_000_D_3_ Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 3 2 ( 176)| inst_AS_000_INT -Mux29| Mcel 3 13 ( 193)| SM_AMIGA_5_ +Mux27| Mcel 6 9 ( 259)| cpu_est_0_ +Mux28| Mcel 1 13 ( 145)| CLK_000_D_0_ +Mux29| Mcel 3 13 ( 193)| cpu_est_3_ Mux30| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux31| ... | ... -Mux32| Mcel 5 8 ( 233)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux31| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux32| Mcel 6 5 ( 253)| cpu_est_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1137,15 +1140,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| CIIN_0|NOD| | S | 2 | 4 to [ 9]| 1 XOR free + 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1162,18 +1165,18 @@ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 18] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) - 5|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 14] logic PT(s) - 8|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) - 9| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 18] logic PT(s) -12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) -13| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 18] logic PT(s) + 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 19] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1189,15 +1192,15 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5|inst_BGACK_030_INT_D|NOD| | => | 7 0 1 2 | 48 41 42 43 + 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8|inst_AS_030_D0|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9| CIIN_0|NOD| | => | 1 2 3 4 | 42 43 44 45 + 8|inst_CLK_OUT_PRE_D|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) -13| CLK_000_D_2_|NOD| | => | 3 4 5 6 | 44 45 46 47 +13| | | | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 --------------------------------------------------------------------------- @@ -1259,7 +1262,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD inst_BGACK_030_INT_D| |*] + [MCell 5 |205|NOD CIIN_0| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1268,8 +1271,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD inst_AS_030_D0| |*] - [MCell 9 |211|NOD CIIN_0| |*] + [MCell 8 |209|NOD inst_CLK_OUT_PRE_D| |*] + [MCell 9 |211|NOD inst_CLK_OUT_PRE_50| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1279,7 +1282,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] [MCell 12 |215|OUT CIIN| | ] - [MCell 13 |217|NOD CLK_000_D_2_| |*] + [MCell 13 |217| -| | ] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] [RegIn 7 |219| -| | ] @@ -1292,39 +1295,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| IOPin 4 1 ( 42)| AS_000 -Mux03| Mcel 3 2 ( 176)| inst_AS_000_INT -Mux04| IOPin 1 4 ( 6)| AHIGH_29_ -Mux05| IOPin 2 4 ( 19)| AHIGH_24_ -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| IOPin 2 0 ( 15)| AHIGH_28_ +Mux02| Mcel 4 9 ( 211)| inst_CLK_OUT_PRE_50 +Mux03| IOPin 0 2 ( 93)| A_DECODE_20_ +Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux05| IOPin 0 3 ( 94)| A_DECODE_21_ +Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux07| Mcel 7 6 ( 278)| inst_AS_030_D0 Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| IOPin 7 1 ( 84)| A_DECODE_22_ -Mux10| ... | ... -Mux11| IOPin 2 1 ( 16)| AHIGH_27_ +Mux09| IOPin 2 2 ( 17)| AHIGH_26_ +Mux10| Mcel 5 1 ( 223)| inst_AS_000_INT +Mux11| IOPin 7 1 ( 84)| A_DECODE_22_ Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| Mcel 4 9 ( 211)| CIIN_0 -Mux15| IOPin 0 3 ( 94)| A_DECODE_21_ -Mux16| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux17| IOPin 2 2 ( 17)| AHIGH_26_ -Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 14)| nEXP_SPACE +Mux13| IOPin 1 4 ( 6)| AHIGH_29_ +Mux14| IOPin 2 0 ( 15)| AHIGH_28_ +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux18| IOPin 7 0 ( 85)| A_DECODE_23_ +Mux19| IOPin 1 5 ( 5)| AHIGH_30_ +Mux20| IOPin 2 4 ( 19)| AHIGH_24_ +Mux21| IOPin 2 1 ( 16)| AHIGH_27_ Mux22| IOPin 2 3 ( 18)| AHIGH_25_ Mux23| ... | ... Mux24| IOPin 5 3 ( 57)| FC_0_ Mux25| IOPin 1 6 ( 4)| AHIGH_31_ -Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux28| IOPin 1 5 ( 5)| AHIGH_30_ -Mux29| IOPin 0 2 ( 93)| A_DECODE_20_ +Mux26| Mcel 4 5 ( 205)| CIIN_0 +Mux27| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux28| IOPin 7 5 ( 80)| RW_000 +Mux29| ... | ... Mux30| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux31| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ +Mux31| ... | ... +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Macrocell (MCell) Cluster Assignments @@ -1336,19 +1339,19 @@ Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| inst_VPA_D|NOD| | S | 1 | 4 to [ 0]| 1 XOR to [ 1] for 1 PT sig + 0| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 0]| 1 XOR free + 1|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 1]| 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 4]| 1 XOR free - 5| | ? | | S | | 4 free | 1 XOR free + 4|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5| | ? | | S | | 4 to [ 4]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 8]| 1 XOR free + 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 8]| 1 XOR to [ 8] 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [12]| 1 XOR free +12|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [12]| 1 XOR free 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -1363,19 +1366,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 14] logic PT(s) - 1| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) + 0| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) + 1|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 2| | ? | | S | |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 15] logic PT(s) - 4|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 15] logic PT(s) - 6| | ? | | S | |=> can support up to [ 15] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 11] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) 7| | ? | | S | |=> can support up to [ 15] logic PT(s) - 8|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 20] logic PT(s) + 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 19] logic PT(s) 9| | ? | | S | |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 15] logic PT(s) 11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 20] logic PT(s) +12|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) @@ -1388,19 +1391,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0|inst_DS_000_DMA|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1| inst_VPA_D|NOD| | => | 5 6 7 0 | 55 54 53 60 + 0| SM_AMIGA_6_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1|inst_AS_000_INT|NOD| | => | 5 6 7 0 | 55 54 53 60 2| | | | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 - 4|inst_LDS_000_INT|NOD| | => | 7 0 1 2 | 53 60 59 58 + 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 53 60 59 58 5| | | | => | 7 0 1 2 | 53 60 59 58 6| | | | => | 0 1 2 3 | 60 59 58 57 7| | | | => | 0 1 2 3 | 60 59 58 57 - 8|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 1 2 3 4 | 59 58 57 56 + 8| SM_AMIGA_i_7_|NOD| | => | 1 2 3 4 | 59 58 57 56 9| | | | => | 1 2 3 4 | 59 58 57 56 10| | | | => | 2 3 4 5 | 58 57 56 55 11| | | | => | 2 3 4 5 | 58 57 56 55 -12|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 3 4 5 6 | 57 56 55 54 +12|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 57 56 55 54 13| | | | => | 3 4 5 6 | 57 56 55 54 14| | | | => | 4 5 6 7 | 56 55 54 53 15| | | | => | 4 5 6 7 | 56 55 54 53 @@ -1452,8 +1455,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD inst_DS_000_DMA| |*] - [MCell 1 |223|NOD inst_VPA_D| |*] + [MCell 0 |221|NOD SM_AMIGA_6_| |*] + [MCell 1 |223|NOD inst_AS_000_INT| |*] 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] [RegIn 1 |225| -| | ] @@ -1462,7 +1465,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD inst_LDS_000_INT| |*] + [MCell 4 |227|NOD inst_AS_030_000_SYNC| |*] [MCell 5 |229| -| | ] 3 [IOpin 3 | 57|INP FC_0_|*|*] @@ -1472,7 +1475,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 8 |233|NOD SM_AMIGA_i_7_| |*] [MCell 9 |235| -| | ] 5 [IOpin 5 | 55| -| | ] @@ -1482,7 +1485,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 12 |239|NOD inst_DS_000_ENABLE| |*] [MCell 13 |241| -| | ] 7 [IOpin 7 | 53| -| | ] @@ -1497,38 +1500,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| Mcel 5 12 ( 239)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux02| Mcel 5 8 ( 233)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux03| IOPin 5 0 ( 60)| A_1_ -Mux04| Input Pin ( 64)| CLK_030 -Mux05| Mcel 5 0 ( 221)| inst_DS_000_DMA -Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| ... | ... -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 2 6 ( 158)| inst_CLK_030_H -Mux10| Input Pin ( 36)| VPA -Mux11| Mcel 1 6 ( 134)| SM_AMIGA_6_ -Mux12| ... | ... -Mux13| Mcel 2 9 ( 163)| inst_AS_000_DMA -Mux14| Mcel 5 4 ( 227)| inst_LDS_000_INT -Mux15| IOPin 6 4 ( 69)| A_0_ -Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 6 5 ( 70)| SIZE_0_ +Mux01| Mcel 5 12 ( 239)| inst_DS_000_ENABLE +Mux02| Mcel 3 10 ( 188)| CLK_000_D_4_ +Mux03| ... | ... +Mux04| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux07| Mcel 7 6 ( 278)| inst_AS_030_D0 +Mux08| IOPin 6 6 ( 71)| RW +Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux10| Mcel 5 1 ( 223)| inst_AS_000_INT +Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux12| IOPin 5 2 ( 58)| FC_1_ +Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux14| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC +Mux15| ... | ... +Mux16| ... | ... +Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ Mux18| ... | ... -Mux19| ... | ... -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| IOPin 7 5 ( 80)| RW_000 -Mux22| Mcel 6 5 ( 253)| CYCLE_DMA_1_ -Mux23| Mcel 6 2 ( 248)| CYCLE_DMA_0_ -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| ... | ... -Mux26| Mcel 4 5 ( 205)| inst_BGACK_030_INT_D +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ +Mux21| Mcel 1 13 ( 145)| CLK_000_D_0_ +Mux22| Mcel 2 2 ( 152)| SM_AMIGA_4_ +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux25| Mcel 3 9 ( 187)| CLK_000_D_3_ +Mux26| ... | ... Mux27| ... | ... Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... -Mux31| ... | ... -Mux32| ... | ... +Mux31| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments @@ -1541,20 +1544,20 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free - 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| CYCLE_DMA_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 1| CLK_DIV_OUT|OUT| | S | 1 | 4 to [ 2]| 1 XOR to [ 1] for 1 PT sig + 2|inst_AS_000_DMA|NOD| | S | 7 | 4 to [ 2]| 1 XOR to [ 2] as logic PT 3| | ? | | S | | 4 free | 1 XOR free 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free - 5| CYCLE_DMA_1_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free - 6| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [ 6]| 1 XOR to [ 6] - 7| | ? | | S | | 4 free | 1 XOR free + 5| cpu_est_1_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 6|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 6]| 1 XOR to [ 6] as logic PT + 7| | ? | | S | | 4 to [ 6]| 1 XOR free 8| A_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| cpu_est_1_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free -10| SIZE_DMA_1_|NOD| | S | 3 | 4 to [10]| 1 XOR free + 9| cpu_est_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10| CYCLE_DMA_1_|NOD| | S | 4 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| SM_AMIGA_4_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14|inst_CLK_OUT_PRE_25|NOD| | S | 2 | 4 to [14]| 1 XOR free +12| SIZE_0_| IO| | S | 3 | 4 to [12]| 1 XOR free +13|inst_DS_000_DMA|NOD| | S | 9 | 4 to [13]| 1 XOR to [13] as logic PT +14| IPL_D0_2_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1567,21 +1570,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 2| CYCLE_DMA_0_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 0| RW| IO| | S | 2 |=> can support up to [ 5] logic PT(s) + 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 6] logic PT(s) + 2|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) 4| E|OUT| | S | 2 |=> can support up to [ 10] logic PT(s) - 5| CYCLE_DMA_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) - 6| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 9] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| A_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 9| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) -10| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| SIZE_0_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) -13| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) -14|inst_CLK_OUT_PRE_25|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) + 5| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 6|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 1] logic PT(s) + 8| A_0_| IO| | S | 3 |=> can support up to [ 5] logic PT(s) + 9| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +10| CYCLE_DMA_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| SIZE_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) +13|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 14] logic PT(s) +14| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) 15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1594,19 +1597,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 2| CYCLE_DMA_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 2|inst_AS_000_DMA|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5| CYCLE_DMA_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| cpu_est_2_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 5| cpu_est_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|inst_CLK_030_H|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9| cpu_est_1_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10| SIZE_DMA_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 + 9| cpu_est_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10| CYCLE_DMA_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 68 69 70 71 -14|inst_CLK_OUT_PRE_25|NOD| | => | 4 5 6 7 | 69 70 71 72 +13|inst_DS_000_DMA|NOD| | => | 3 4 5 6 | 68 69 70 71 +14| IPL_D0_2_|NOD| | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== @@ -1643,6 +1646,7 @@ _|_________________|__|___|_____|__________________________________________ 4| A_0_| IO|*| 69| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_A_0_] 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_SIZE_0_] 6| RW| IO|*| 71| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_RW] 7| | | | 72| => | Input macrocell [ -] @@ -1663,37 +1667,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 66|OUT E|*| ] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD CYCLE_DMA_0_| |*] + [MCell 2 |248|NOD inst_AS_000_DMA| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|OUT E| | ] - [MCell 5 |253|NOD CYCLE_DMA_1_| |*] + [MCell 5 |253|NOD cpu_est_1_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD cpu_est_2_| |*] + [MCell 6 |254|NOD inst_CLK_030_H| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69| IO A_0_|*|*] paired w/[ RN_A_0_] [RegIn 4 |258| -| | ] [MCell 8 |257|NOD RN_A_0_| |*] paired w/[ A_0_] - [MCell 9 |259|NOD cpu_est_1_| |*] + [MCell 9 |259|NOD cpu_est_0_| |*] - 5 [IOpin 5 | 70| IO SIZE_0_|*|*] + 5 [IOpin 5 | 70| IO SIZE_0_|*|*] paired w/[ RN_SIZE_0_] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD SIZE_DMA_1_| |*] + [MCell 10 |260|NOD CYCLE_DMA_1_| |*] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] [RegIn 6 |264| -| | ] - [MCell 12 |263| IO SIZE_0_| | ] - [MCell 13 |265|NOD SM_AMIGA_4_| |*] + [MCell 12 |263|NOD RN_SIZE_0_| |*] paired w/[ SIZE_0_] + [MCell 13 |265|NOD inst_DS_000_DMA| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD inst_CLK_OUT_PRE_25| |*] + [MCell 14 |266|NOD IPL_D0_2_| |*] [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1702,39 +1706,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 3 4 ( 31)| LDS_000 -Mux01| Mcel 3 13 ( 193)| SM_AMIGA_5_ -Mux02| Mcel 2 2 ( 152)| SIZE_DMA_0_ -Mux03| Mcel 4 5 ( 205)| inst_BGACK_030_INT_D -Mux04| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 3 13 ( 193)| cpu_est_3_ +Mux02| IOPin 4 1 ( 42)| AS_000 +Mux03| Mcel 3 2 ( 176)| cpu_est_2_ +Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux07| Mcel 6 12 ( 263)| RN_SIZE_0_ Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 0 1 ( 103)| inst_CLK_OUT_PRE_50 -Mux10| Mcel 1 13 ( 145)| CLK_000_D_0_ -Mux11| Mcel 6 14 ( 266)| inst_CLK_OUT_PRE_25 -Mux12| Mcel 6 13 ( 265)| SM_AMIGA_4_ -Mux13| Mcel 6 8 ( 257)| RN_A_0_ -Mux14| Mcel 7 2 ( 272)| inst_CLK_OUT_PRE_D +Mux09| Mcel 0 1 ( 103)| CYCLE_DMA_0_ +Mux10| Mcel 6 8 ( 257)| RN_A_0_ +Mux11| ... | ... +Mux12| Mcel 6 13 ( 265)| inst_DS_000_DMA +Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux14| ... | ... Mux15| ... | ... -Mux16| IOPin 4 1 ( 42)| AS_000 +Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D Mux17| Mcel 6 0 ( 245)| RN_RW Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux19| ... | ... +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 10 ( 260)| SIZE_DMA_1_ -Mux23| Mcel 6 6 ( 254)| cpu_est_2_ -Mux24| Mcel 1 10 ( 140)| cpu_est_0_ +Mux21| Mcel 1 13 ( 145)| CLK_000_D_0_ +Mux22| IOPin 6 3 ( 68)| IPL_2_ +Mux23| Mcel 6 6 ( 254)| inst_CLK_030_H +Mux24| IOPin 3 4 ( 31)| LDS_000 Mux25| ... | ... Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| cpu_est_1_ -Mux28| ... | ... +Mux27| Mcel 6 9 ( 259)| cpu_est_0_ +Mux28| Mcel 6 10 ( 260)| CYCLE_DMA_1_ Mux29| ... | ... Mux30| ... | ... -Mux31| Mcel 6 2 ( 248)| CYCLE_DMA_0_ -Mux32| Mcel 6 5 ( 253)| CYCLE_DMA_1_ +Mux31| Mcel 6 2 ( 248)| inst_AS_000_DMA +Mux32| Mcel 6 5 ( 253)| cpu_est_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1748,18 +1752,18 @@ Mux32| Mcel 6 5 ( 253)| CYCLE_DMA_1_ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW_000| IO| | S | 4 | 4 to [ 0]| 1 XOR free 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free 5| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 6|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| DSACK1| IO| | S | 2 | 4 to [ 9]| 1 XOR free + 9| DSACK1|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SIZE_1_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| SM_AMIGA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free +12| SIZE_1_| IO| | S | 3 | 4 to [12]| 1 XOR free +13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1775,19 +1779,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| RW_000| IO| | S | 4 |=> can support up to [ 13] logic PT(s) 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) 5| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 6| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 13] logic PT(s) - 8| AS_030| IO| | S | 1 |=> can support up to [ 15] logic PT(s) - 9| DSACK1| IO| | S | 2 |=> can support up to [ 19] logic PT(s) + 6|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 17] logic PT(s) + 8| AS_030| IO| | S | 1 |=> can support up to [ 19] logic PT(s) + 9| DSACK1|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12| SIZE_1_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) -13| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| SIZE_1_| IO| | S | 3 |=> can support up to [ 19] logic PT(s) +13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1800,18 +1804,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 2|inst_CLK_OUT_PRE_D|NOD| | => | 6 7 0 1 | 79 78 85 84 + 2| CLK_000_D_2_|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) 5| CLK_000_D_1_|NOD| | => | 7 0 1 2 | 78 85 84 83 - 6| inst_DTACK_D0|NOD| | => | 0 1 2 3 | 85 84 83 82 + 6|inst_AS_030_D0|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 - 9| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) + 9| DSACK1|OUT| | => | 1 2 3 ( 4)| 84 83 82 ( 81) 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) -13| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 82 81 80 79 +13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1828,7 +1832,7 @@ _|_________________|__|___|_____|___________________________________________ 1| A_DECODE_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 - 4| DSACK1| IO|*| 81| => | 8 ( 9) 10 11 12 13 14 15 + 4| DSACK1|OUT|*| 81| => | 8 ( 9) 10 11 12 13 14 15 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 6| SIZE_1_| IO|*| 79| => | (12) 13 14 15 0 1 2 3 7| FPU_CS|OUT|*| 78| => | 14 15 0 ( 1) 2 3 4 5 @@ -1847,11 +1851,11 @@ _|_________________|__|___|_____|__________________________________________ 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BGACK_030] 3| AS_030| IO|*| 82| => | Input macrocell [ -] - 4| DSACK1| IO|*| 81| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_DSACK1] + 4| DSACK1|OUT|*| 81| => | Input macrocell [ -] 5| RW_000| IO|*| 80| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_RW_000] 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_SIZE_1_] 7| FPU_CS|OUT|*| 78| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -1870,7 +1874,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD inst_CLK_OUT_PRE_D| |*] + [MCell 2 |272|NOD CLK_000_D_2_| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] @@ -1880,23 +1884,23 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 82| IO AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD inst_DTACK_D0| |*] + [MCell 6 |278|NOD inst_AS_030_D0| |*] [MCell 7 |280| -| | ] - 4 [IOpin 4 | 81| IO DSACK1|*| ] paired w/[ RN_DSACK1] + 4 [IOpin 4 | 81|OUT DSACK1|*| ] [RegIn 4 |282| -| | ] [MCell 8 |281| IO AS_030| | ] - [MCell 9 |283|NOD RN_DSACK1| |*] paired w/[ DSACK1] + [MCell 9 |283|OUT DSACK1| | ] 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] [RegIn 5 |285| -| | ] [MCell 10 |284| -| | ] [MCell 11 |286| -| | ] - 6 [IOpin 6 | 79| IO SIZE_1_|*|*] + 6 [IOpin 6 | 79| IO SIZE_1_|*|*] paired w/[ RN_SIZE_1_] [RegIn 6 |288| -| | ] - [MCell 12 |287| IO SIZE_1_| | ] - [MCell 13 |289|NOD SM_AMIGA_0_| |*] + [MCell 12 |287|NOD RN_SIZE_1_| |*] paired w/[ SIZE_1_] + [MCell 13 |289|NOD inst_BGACK_030_INT_D| |*] 7 [IOpin 7 | 78|OUT FPU_CS|*| ] [RegIn 7 |291| -| | ] @@ -1911,35 +1915,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 2 2 ( 152)| SIZE_DMA_0_ -Mux03| Mcel 2 9 ( 163)| inst_AS_000_DMA -Mux04| IOPin 3 7 ( 28)| BGACK_000 -Mux05| Mcel 7 9 ( 283)| RN_DSACK1 -Mux06| Mcel 7 0 ( 269)| RN_RW_000 -Mux07| Mcel 7 13 ( 289)| SM_AMIGA_0_ -Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| Mcel 0 12 ( 119)| SM_AMIGA_1_ +Mux02| Mcel 0 5 ( 109)| inst_DSACK1_INT +Mux03| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux08| IOPin 6 6 ( 71)| RW +Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| Mcel 1 13 ( 145)| CLK_000_D_0_ -Mux11| Mcel 6 14 ( 266)| inst_CLK_OUT_PRE_25 -Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux12| IOPin 3 3 ( 32)| UDS_000 Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| IOPin 3 5 ( 30)| DTACK -Mux15| Input Pin ( 14)| nEXP_SPACE +Mux14| ... | ... +Mux15| Mcel 0 12 ( 119)| SM_AMIGA_0_ Mux16| IOPin 4 1 ( 42)| AS_000 Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 1 14 ( 146)| SM_AMIGA_i_7_ +Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux19| IOPin 0 0 ( 91)| FPU_SENSE +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 10 ( 260)| SIZE_DMA_1_ -Mux23| Mcel 1 6 ( 134)| SM_AMIGA_6_ -Mux24| ... | ... -Mux25| IOPin 6 6 ( 71)| RW -Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux22| ... | ... +Mux23| Mcel 7 0 ( 269)| RN_RW_000 +Mux24| IOPin 3 4 ( 31)| LDS_000 +Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux26| ... | ... Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... -Mux29| ... | ... -Mux30| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux31| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux29| Mcel 7 12 ( 287)| RN_SIZE_1_ +Mux30| ... | ... +Mux31| Mcel 6 2 ( 248)| inst_AS_000_DMA Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 3f03e3c..9c50a20 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic -Project Fitted on : Wed Sep 14 23:54:30 2016 +Project Fitted on : Thu Oct 06 21:35:00 2016 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 24 Total Output Pins : 19 Total Bidir I/O Pins : 18 - Total Flip-Flops : 55 - Total Product Terms : 203 + Total Flip-Flops : 56 + Total Product Terms : 204 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -58,9 +58,9 @@ Logic Macrocells 128 81 47 --> 63% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 208 56 --> 78% -Logical Product Terms 640 206 434 --> 32% -Product Term Clusters 128 52 76 --> 40% +CSM Outputs/Total Block Inputs 264 202 62 --> 76% +Logical Product Terms 640 207 433 --> 32% +Product Term Clusters 128 51 77 --> 39%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 24 8 0 10 0 6 27 9 Lo -Block B 23 8 0 12 0 4 46 7 Lo -Block C 26 7 0 12 0 4 33 9 Lo -Block D 27 8 0 12 0 4 25 8 Lo -Block E 31 4 0 8 0 8 10 14 Lo -Block F 22 5 0 5 0 11 17 11 Lo -Block G 26 7 0 12 0 4 30 6 Lo -Block H 29 8 0 10 0 6 18 12 Lo +Block A 23 8 0 11 0 5 23 8 Lo +Block B 21 8 0 12 0 4 42 8 Lo +Block C 26 7 0 12 0 4 28 11 Lo +Block D 25 8 0 12 0 4 22 10 Lo +Block E 30 4 0 7 0 9 9 14 Lo +Block F 24 5 0 5 0 11 19 10 Lo +Block G 26 7 0 12 0 4 47 3 Lo +Block H 27 8 0 10 0 6 17 13 Lo --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,30 +287,30 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O -----F-- Low Slow A_1_ - 96 A . I/O --C-E--H Low Slow A_DECODE_16_ - 59 F . I/O --C-E--H Low Slow A_DECODE_17_ - 95 A . I/O --C-E--H Low Slow A_DECODE_18_ - 97 A . I/O --C-E--H Low Slow A_DECODE_19_ + 60 F . I/O A------- Low Slow A_1_ + 96 A . I/O ----EF-H Low Slow A_DECODE_16_ + 59 F . I/O ----EF-H Low Slow A_DECODE_17_ + 95 A . I/O ----EF-H Low Slow A_DECODE_18_ + 97 A . I/O ----EF-H Low Slow A_DECODE_19_ 93 A . I/O ----E--- Low Slow A_DECODE_20_ 94 A . I/O ----E--- Low Slow A_DECODE_21_ 84 H . I/O ----E--- Low Slow A_DECODE_22_ 85 H . I/O ----E--- Low Slow A_DECODE_23_ 28 D . I/O ----E--H Low Slow BGACK_000 21 C . I/O ---D---- Low Slow BG_030 - 30 D . I/O -------H Low Slow DTACK - 57 F . I/O --C-E--H Low Slow FC_0_ - 58 F . I/O --C-E--H Low Slow FC_1_ + 30 D . I/O --C----- Low Slow DTACK + 57 F . I/O ----EF-H Low Slow FC_0_ + 58 F . I/O ----EF-H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O -BC----- Low Slow IPL_0_ - 56 F . I/O -B-D---- Low Slow IPL_1_ - 68 G . I/O -BC----- Low Slow IPL_2_ + 67 G . I/O -B-D---- Low Slow IPL_0_ + 56 F . I/O -B------ Low Slow IPL_1_ + 68 G . I/O -B----G- Low Slow IPL_2_ 11 . . Ck/I -B------ - Slow CLK_000 - 14 . . Ck/I ABCDE-GH - Slow nEXP_SPACE - 36 . . Ded -----F-- - Slow VPA + 14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE + 36 . . Ded A------- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI - 64 . . Ck/I --C--F-- - Slow CLK_030 - 86 . . Ded ABCDEFGH - Slow RST + 64 . . Ck/I ------G- - Slow CLK_030 + 86 . . Ded ABCD-FGH - Slow RST ---------------------------------------------------------------------- Power : Hi = High @@ -336,7 +336,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 47 E 1 COM -------- Low Fast CIIN 65 G 1 DFF -------- Low Fast CLK_DIV_OUT 10 B 1 DFF -------- Low Fast CLK_EXP - 81 H 2 DFF -------- Low Fast DSACK1 + 81 H 1 COM -------- Low Fast DSACK1 98 A 1 COM -------- Low Fast DS_030 66 G 2 COM -------- Low Fast E 78 H 1 COM -------- Low Fast FPU_CS @@ -368,16 +368,16 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B 1 COM ----E--- Low Fast AHIGH_29_ 5 B 1 COM ----E--- Low Fast AHIGH_30_ 4 B 1 COM ----E--- Low Fast AHIGH_31_ - 42 E 1 COM A-C-EFGH Low Fast AS_000 - 82 H 1 COM ----E--H Low Fast AS_030 - 69 G 3 DFF ---D-F-- Low Fast A_0_ - 41 E 1 COM A------- Low Fast BERR - 31 D 1 COM --C--FG- Low Fast LDS_000 - 71 G 2 DFF ---D---H Low Fast RW - 80 H 4 DFF ----EFG- Low Fast RW_000 - 70 G 1 COM -----F-- Low Fast SIZE_0_ - 79 H 1 COM -----F-- Low Fast SIZE_1_ - 32 D 1 COM --C--FG- Low Fast UDS_000 + 42 E 1 COM A---E-GH Low Fast AS_000 + 82 H 1 COM A---EF-H Low Fast AS_030 + 69 G 3 DFF -B------ Low Fast A_0_ + 41 E 1 COM --C----- Low Fast BERR + 31 D 1 COM ------GH Low Fast LDS_000 + 71 G 2 DFF -----F-H Low Fast RW + 80 H 4 DFF ----E-G- Low Fast RW_000 + 70 G 3 DFF -B------ Low Fast SIZE_0_ + 79 H 3 DFF -B------ Low Fast SIZE_1_ + 32 D 1 COM ------GH Low Fast UDS_000 ---------------------------------------------------------------------- Power : Hi = High @@ -393,60 +393,61 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - E9 E 2 COM ----E--- Low Slow CIIN_0 - B13 B 1 DFF AB-D--GH Low Slow CLK_000_D_0_ - H5 H 1 DFF AB-DE-GH Low Slow CLK_000_D_1_ - E13 E 1 DFF -B------ Low Slow CLK_000_D_2_ - G2 G 3 DFF --C--FG- Low Slow CYCLE_DMA_0_ - G5 G 4 DFF --C--FG- Low Slow CYCLE_DMA_1_ - C14 C 1 DFF -B------ Low Slow IPL_D0_0_ - D14 D 1 DFF -B------ Low Slow IPL_D0_1_ - C10 C 1 DFF -B------ Low Slow IPL_D0_2_ + E5 E 2 COM ----E--- Low Slow CIIN_0 + B13 B 1 DFF A-CD-FGH Low Slow CLK_000_D_0_ + H5 H 1 DFF A-CD-FGH Low Slow CLK_000_D_1_ + H2 H 1 DFF A-CD---- Low Slow CLK_000_D_2_ + D9 D 1 DFF A-CD-F-- Low Slow CLK_000_D_3_ + D10 D 1 DFF -----F-- Low Slow CLK_000_D_4_ + A1 A 3 DFF A-----G- Low Slow CYCLE_DMA_0_ + G10 G 4 DFF ------G- Low Slow CYCLE_DMA_1_ + D14 D 1 DFF -B------ Low Slow IPL_D0_0_ + B14 B 1 DFF -B------ Low Slow IPL_D0_1_ + G14 G 1 DFF -B------ Low Slow IPL_D0_2_ G8 G 3 DFF ------G- Low - RN_A_0_ --> A_0_ H4 H 3 DFF ABCDEFGH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF ---D---- Low - RN_BG_000 --> BG_000 - H9 H 2 DFF -------H Low - RN_DSACK1 --> DSACK1 B5 B 10 DFF -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ B9 B 10 DFF -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ B4 B 10 DFF -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ G0 G 2 DFF ------G- Low - RN_RW --> RW H0 H 4 DFF -------H Low - RN_RW_000 --> RW_000 - D0 D 3 TFF A--D---- Low - RN_VMA --> VMA - A13 A 4 DFF A------- Low Slow RST_DLY_0_ - A6 A 2 DFF A------- Low Slow RST_DLY_1_ - A2 A 2 DFF A------- Low Slow RST_DLY_2_ - C2 C 3 DFF --C---GH Low Slow SIZE_DMA_0_ - G10 G 3 DFF ------GH Low Slow SIZE_DMA_1_ - H13 H 3 DFF -B-----H Low Slow SM_AMIGA_0_ - A12 A 3 DFF A------H Low Slow SM_AMIGA_1_ - A5 A 5 DFF A------- Low Slow SM_AMIGA_2_ - A9 A 5 TFF A------- Low Slow SM_AMIGA_3_ - G13 G 3 DFF A--D--G- Low Slow SM_AMIGA_4_ - D13 D 3 DFF ---D--G- Low Slow SM_AMIGA_5_ - B6 B 3 DFF -B-D-F-H Low Slow SM_AMIGA_6_ - B14 B 3 DFF -BC----H Low Slow SM_AMIGA_i_7_ - B10 B 3 DFF AB-D--G- Low Slow cpu_est_0_ - G9 G 4 DFF A--D--G- Low Slow cpu_est_1_ - G6 G 1 DFF A--D--G- Low Slow cpu_est_2_ - D9 D 4 DFF A--D--G- Low Slow cpu_est_3_ - F8 F 2 DFF ---D-F-- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - F12 F 2 DFF --C--F-- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW - C9 C 7 DFF --C--F-H Low Slow inst_AS_000_DMA - D2 D 2 DFF ---DE--- Low Slow inst_AS_000_INT - C13 C 7 DFF -BCD---- Low Slow inst_AS_030_000_SYNC - E8 E 1 DFF --CDE--H Low Slow inst_AS_030_D0 - E5 E 1 DFF --C--FG- Low Slow inst_BGACK_030_INT_D - C6 C 8 DFF --C--F-- Low Slow inst_CLK_030_H - G14 G 2 DFF ------GH Low Slow inst_CLK_OUT_PRE_25 - A1 A 1 DFF A-----G- Low Slow inst_CLK_OUT_PRE_50 - H2 H 1 DFF -B----G- Low Slow inst_CLK_OUT_PRE_D - F0 F 9 DFF A----F-- Low Slow inst_DS_000_DMA - D6 D 3 DFF ---D---- Low Slow inst_DS_000_ENABLE - H6 H 1 DFF A------- Low Slow inst_DTACK_D0 - F4 F 3 DFF ---D-F-- Low Slow inst_LDS_000_INT + G12 G 3 DFF ------G- Low - RN_SIZE_0_ --> SIZE_0_ + H12 H 3 DFF -------H Low - RN_SIZE_1_ --> SIZE_1_ + D0 D 3 TFF --CD---- Low - RN_VMA --> VMA + C9 C 4 DFF A-C----- Low Slow RST_DLY_0_ + A13 A 2 DFF A-C----- Low Slow RST_DLY_1_ + A9 A 2 DFF A-C----- Low Slow RST_DLY_2_ + A12 A 4 DFF A----F-H Low Slow SM_AMIGA_0_ + C13 C 4 DFF A-C----- Low Slow SM_AMIGA_1_ + C6 C 5 DFF --C----- Low Slow SM_AMIGA_2_ + C10 C 5 TFF --C----- Low Slow SM_AMIGA_3_ + C2 C 3 DFF --C--F-- Low Slow SM_AMIGA_4_ + D6 D 3 DFF --CD---- Low Slow SM_AMIGA_5_ + F0 F 3 DFF -B-D-F-H Low Slow SM_AMIGA_6_ + F8 F 3 TFF -----F-H Low Slow SM_AMIGA_i_7_ + G9 G 3 DFF --CD--G- Low Slow cpu_est_0_ + G5 G 4 DFF --CD--G- Low Slow cpu_est_1_ + D2 D 1 DFF --CD--G- Low Slow cpu_est_2_ + D13 D 4 DFF --CD--G- Low Slow cpu_est_3_ + A2 A 2 DFF A--D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + A6 A 2 DFF A-C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + G2 G 7 DFF ------GH Low Slow inst_AS_000_DMA + F1 F 2 DFF ----EF-- Low Slow inst_AS_000_INT + F4 F 7 DFF ---D-F-- Low Slow inst_AS_030_000_SYNC + H6 H 1 DFF ---DEF-- Low Slow inst_AS_030_D0 + H13 H 1 DFF A----FGH Low Slow inst_BGACK_030_INT_D + G6 G 8 DFF ------G- Low Slow inst_CLK_030_H + E9 E 1 DFF ----E--- Low Slow inst_CLK_OUT_PRE_50 + E8 E 1 DFF -B----G- Low Slow inst_CLK_OUT_PRE_D + A5 A 2 DFF A------H Low Slow inst_DSACK1_INT + G13 G 9 DFF A-----G- Low Slow inst_DS_000_DMA + F12 F 3 DFF ---D-F-- Low Slow inst_DS_000_ENABLE + C14 C 1 DFF --C----- Low Slow inst_DTACK_D0 + B6 B 3 DFF -B-D---- Low Slow inst_LDS_000_INT A8 A 2 DFF ABCDE-GH Low Slow inst_RESET_OUT - D10 D 2 DFF ---D---- Low Slow inst_UDS_000_INT - F1 F 1 DFF A--D---- Low Slow inst_VPA_D + B10 B 2 DFF -B-D---- Low Slow inst_UDS_000_INT + A10 A 1 DFF --CD---- Low Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -461,179 +462,181 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - SIZE_1_{ I}:inst_LDS_000_INT{ F} AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E} A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E} IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_2_{ C} - FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + : IPL_D0_2_{ G} + FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} - : inst_AS_030_D0{ E} + : DSACK1{ H} inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ F} + :inst_DS_000_ENABLE{ F}inst_DSACK1_INT{ A}inst_AS_000_INT{ F} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} - : BGACK_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} - : CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} inst_CLK_030_H{ C} - UDS_000{ E}: A_0_{ G}inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} - : SIZE_DMA_0_{ C} SIZE_DMA_1_{ G} inst_CLK_030_H{ C} - LDS_000{ E}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} SIZE_DMA_0_{ C} - : SIZE_DMA_1_{ G} inst_CLK_030_H{ C} - nEXP_SPACE{. }: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H} - : DS_030{ A} SIZE_0_{ G} AHIGH_30_{ B} - : AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C} - : AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C} - :AMIGA_BUS_DATA_DIR{ E} BG_000{ D} DSACK1{ H} - : A_0_{ G}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ B} - : SM_AMIGA_i_7_{ B} CIIN_0{ E} - BERR{ F}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + : BGACK_030{ H}inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ G} inst_CLK_030_H{ G} + UDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G} A_0_{ G} + :inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} inst_CLK_030_H{ G} + LDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G}inst_AS_000_DMA{ G} + :inst_DS_000_DMA{ G} inst_CLK_030_H{ G} + nEXP_SPACE{. }: AHIGH_31_{ B} AS_030{ H} DS_030{ A} + : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} + : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} + : DSACK1{ H} AHIGH_24_{ C}AMIGA_BUS_DATA_DIR{ E} + : SIZE_1_{ H} BG_000{ D} SIZE_0_{ G} + : A_0_{ G}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_i_7_{ F} CIIN_0{ E} + BERR{ F}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} BG_030{ D}: BG_000{ D} BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} - CLK_030{. }:inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} inst_CLK_030_H{ C} + CLK_030{. }:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} inst_CLK_030_H{ G} CLK_000{. }: CLK_000_D_0_{ B} - SIZE_0_{ H}:inst_LDS_000_INT{ F} AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E} AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E} AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E} AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E} - FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E} + FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E} - DTACK{ E}: inst_DTACK_D0{ H} AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E} + DTACK{ E}: inst_DTACK_D0{ C} A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E} A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E} - VPA{. }: inst_VPA_D{ F} A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E} -A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - RST{. }: IPL_030_2_{ B} RW_000{ H} BG_000{ D} - : BGACK_030{ H} DSACK1{ H} VMA{ D} - : RW{ G} A_0_{ G} IPL_030_1_{ B} - : IPL_030_0_{ B}inst_AS_000_INT{ D}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} - : inst_AS_030_D0{ E}inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ E} - :inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} CYCLE_DMA_0_{ G} - : CYCLE_DMA_1_{ G} SIZE_DMA_0_{ C} SIZE_DMA_1_{ G} - : inst_VPA_D{ F} inst_DTACK_D0{ H} inst_RESET_OUT{ A} - : IPL_D0_0_{ C} IPL_D0_1_{ D} IPL_D0_2_{ C} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F}inst_LDS_000_INT{ F}inst_DS_000_ENABLE{ D} - :inst_UDS_000_INT{ D} SM_AMIGA_6_{ B} SM_AMIGA_4_{ G} - : SM_AMIGA_1_{ A} SM_AMIGA_0_{ H} RST_DLY_0_{ A} - : RST_DLY_1_{ A} RST_DLY_2_{ A} inst_CLK_030_H{ C} - : SM_AMIGA_5_{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : SM_AMIGA_i_7_{ B} -A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} -A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} -A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + VPA{. }: inst_VPA_D{ A} +A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} +A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + RST{. }: SIZE_1_{ H} IPL_030_2_{ B} RW_000{ H} + : BG_000{ D} BGACK_030{ H} SIZE_0_{ G} + : VMA{ D} RW{ G} A_0_{ G} + : IPL_030_1_{ B} IPL_030_0_{ B}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} + : inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ F}inst_BGACK_030_INT_D{ H} + :inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ G} inst_VPA_D{ A} inst_DTACK_D0{ C} + : inst_RESET_OUT{ A} IPL_D0_0_{ D} IPL_D0_1_{ B} + : IPL_D0_2_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} SM_AMIGA_1_{ C} + :inst_UDS_000_INT{ B}inst_DS_000_ENABLE{ F}inst_LDS_000_INT{ B} + : SM_AMIGA_6_{ F} SM_AMIGA_4_{ C} SM_AMIGA_0_{ A} + : RST_DLY_0_{ C} RST_DLY_1_{ A} RST_DLY_2_{ A} + : inst_CLK_030_H{ G}inst_DSACK1_INT{ A}inst_AS_000_INT{ F} + : SM_AMIGA_5_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + : SM_AMIGA_i_7_{ F} +A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} +A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_1_{ D} + : IPL_D0_1_{ B} IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_0_{ C} - FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F} + : IPL_D0_0_{ D} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} + SIZE_1_{ I}:inst_LDS_000_INT{ B} + RN_SIZE_1_{ I}: SIZE_1_{ H} RN_IPL_030_2_{ C}: IPL_030_2_{ B} - RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ F} + RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ G} RN_RW_000{ I}: RW_000{ H} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H} - : AS_000{ E} DS_030{ A} UDS_000{ D} - : LDS_000{ D} SIZE_0_{ G} AHIGH_30_{ B} - : AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C} - : AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C} - :AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} - : RW_000{ H} BGACK_030{ H} RW{ G} - : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F}inst_AS_030_000_SYNC{ C} - :inst_BGACK_030_INT_D{ E}inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} - : CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} SIZE_DMA_0_{ C} - : SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F} inst_CLK_030_H{ C} - RN_DSACK1{ I}: DSACK1{ H} - RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ D} +RN_BGACK_030{ I}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} + : DS_030{ A} UDS_000{ D} LDS_000{ D} + : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} + : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} + : AHIGH_24_{ C}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} + :AMIGA_BUS_ENABLE_HIGH{ D} SIZE_1_{ H} RW_000{ H} + : BGACK_030{ H} SIZE_0_{ G} RW{ G} + : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AS_030_000_SYNC{ F} + :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} + : inst_CLK_030_H{ G} + SIZE_0_{ H}:inst_LDS_000_INT{ B} + RN_SIZE_0_{ H}: SIZE_0_{ G} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ F} RN_RW{ H}: RW{ G} - A_0_{ H}:inst_LDS_000_INT{ F}inst_UDS_000_INT{ D} + A_0_{ H}:inst_UDS_000_INT{ B}inst_LDS_000_INT{ B} RN_A_0_{ H}: A_0_{ G} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_2_{ G} - : cpu_est_3_{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_3_{ D} - : cpu_est_1_{ G} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - cpu_est_0_{ C}: VMA{ D} cpu_est_2_{ G} cpu_est_3_{ D} - : cpu_est_0_{ B} cpu_est_1_{ G} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} - cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_2_{ G} - : cpu_est_3_{ D} cpu_est_1_{ G} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} -inst_AS_000_INT{ E}: AS_000{ E}inst_AS_000_INT{ D} -inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} -inst_AS_030_D0{ F}: CIIN{ E} BG_000{ D} DSACK1{ H} - :inst_AS_000_INT{ D}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ D} + : cpu_est_1_{ G} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + cpu_est_0_{ H}: VMA{ D} cpu_est_3_{ D} cpu_est_0_{ G} + : cpu_est_1_{ G} cpu_est_2_{ D} SM_AMIGA_3_{ C} + : SM_AMIGA_2_{ C} + cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_3_{ D} + : cpu_est_1_{ G} cpu_est_2_{ D} SM_AMIGA_3_{ C} + : SM_AMIGA_2_{ C} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_3_{ D} + : cpu_est_2_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} +inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D}inst_AS_030_000_SYNC{ F} : CIIN_0{ E} -inst_AS_030_000_SYNC{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ B} - : SM_AMIGA_i_7_{ B} -inst_BGACK_030_INT_D{ F}: RW{ G} A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} - :inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ C} SIZE_DMA_1_{ G} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F} -inst_AS_000_DMA{ D}: AS_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} - : inst_CLK_030_H{ C} -inst_DS_000_DMA{ G}: DS_030{ A}inst_DS_000_DMA{ F} -CYCLE_DMA_0_{ H}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} CYCLE_DMA_0_{ G} - : CYCLE_DMA_1_{ G} inst_CLK_030_H{ C} -CYCLE_DMA_1_{ H}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ F} CYCLE_DMA_1_{ G} - : inst_CLK_030_H{ C} -SIZE_DMA_0_{ D}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ C} -SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G} - inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} DSACK1{ H} - : VMA{ D} cpu_est_2_{ G} cpu_est_3_{ D} - : cpu_est_0_{ B} cpu_est_1_{ G}inst_AS_000_INT{ D} - : CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} inst_RESET_OUT{ A} - : CLK_000_D_2_{ E}inst_DS_000_ENABLE{ D} SM_AMIGA_6_{ B} - : SM_AMIGA_4_{ G} SM_AMIGA_1_{ A} SM_AMIGA_0_{ H} - : RST_DLY_0_{ A} RST_DLY_1_{ A} RST_DLY_2_{ A} - : SM_AMIGA_5_{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : SM_AMIGA_i_7_{ B} -inst_DTACK_D0{ I}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +inst_AS_030_000_SYNC{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_i_7_{ F} +inst_BGACK_030_INT_D{ I}: SIZE_1_{ H} SIZE_0_{ G} RW{ G} + : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AS_030_000_SYNC{ F} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} +inst_AS_000_DMA{ H}: AS_030{ H}inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} + : inst_CLK_030_H{ G} +inst_DS_000_DMA{ H}: DS_030{ A}inst_DS_000_DMA{ G} +CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ G} inst_CLK_030_H{ G} +CYCLE_DMA_1_{ H}:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} CYCLE_DMA_1_{ G} + : inst_CLK_030_H{ G} + inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +CLK_000_D_2_{ I}: CLK_000_D_3_{ D} SM_AMIGA_1_{ C} SM_AMIGA_0_{ A} + :inst_DSACK1_INT{ A} +CLK_000_D_3_{ E}: CLK_000_D_4_{ D} SM_AMIGA_1_{ C} SM_AMIGA_6_{ F} + : SM_AMIGA_0_{ A}inst_DSACK1_INT{ A} SM_AMIGA_i_7_{ F} +inst_DTACK_D0{ D}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} inst_RESET_OUT{ B}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} : DS_030{ A} UDS_000{ D} LDS_000{ D} : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} : AHIGH_24_{ C} RESET{ B} RW_000{ H} : RW{ G} A_0_{ G} inst_RESET_OUT{ A} +CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} VMA{ D} + : cpu_est_3_{ D} cpu_est_0_{ G} cpu_est_1_{ G} + : cpu_est_2_{ D} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ G} + : CLK_000_D_2_{ H} inst_RESET_OUT{ A} SM_AMIGA_1_{ C} + :inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ F} SM_AMIGA_4_{ C} + : SM_AMIGA_0_{ A} RST_DLY_0_{ C} RST_DLY_1_{ A} + : RST_DLY_2_{ A}inst_AS_000_INT{ F} SM_AMIGA_5_{ D} + : SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} SM_AMIGA_i_7_{ F} CLK_000_D_0_{ C}: RW_000{ H} BG_000{ D} BGACK_030{ H} - : DSACK1{ H} VMA{ D} cpu_est_2_{ G} - : cpu_est_3_{ D} cpu_est_0_{ B} cpu_est_1_{ G} - :inst_AS_000_INT{ D} CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} - : CLK_000_D_1_{ H} inst_RESET_OUT{ A}inst_DS_000_ENABLE{ D} - : SM_AMIGA_6_{ B} SM_AMIGA_4_{ G} SM_AMIGA_1_{ A} - : SM_AMIGA_0_{ H} RST_DLY_0_{ A} RST_DLY_1_{ A} - : RST_DLY_2_{ A} SM_AMIGA_5_{ D} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} SM_AMIGA_i_7_{ B} -inst_CLK_OUT_PRE_50{ B}:inst_CLK_OUT_PRE_50{ A}inst_CLK_OUT_PRE_25{ G} -inst_CLK_OUT_PRE_25{ H}:inst_CLK_OUT_PRE_25{ G}inst_CLK_OUT_PRE_D{ H} -inst_CLK_OUT_PRE_D{ I}: CLK_DIV_OUT{ G} CLK_EXP{ B} - IPL_D0_0_{ D}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_2_{ D}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} -CLK_000_D_2_{ F}: SM_AMIGA_6_{ B} SM_AMIGA_i_7_{ B} -inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F} -inst_LDS_000_INT{ G}: LDS_000{ D}inst_LDS_000_INT{ F} -inst_DS_000_ENABLE{ E}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ D} -inst_UDS_000_INT{ E}: UDS_000{ D}inst_UDS_000_INT{ D} -SM_AMIGA_6_{ C}: RW_000{ H}inst_AS_000_INT{ D}inst_LDS_000_INT{ F} - :inst_DS_000_ENABLE{ D}inst_UDS_000_INT{ D} SM_AMIGA_6_{ B} + : VMA{ D} cpu_est_3_{ D} cpu_est_0_{ G} + : cpu_est_1_{ G} cpu_est_2_{ D} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ G} inst_RESET_OUT{ A} CLK_000_D_1_{ H} + : SM_AMIGA_1_{ C}inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_4_{ C} SM_AMIGA_0_{ A} RST_DLY_0_{ C} + : RST_DLY_1_{ A} RST_DLY_2_{ A}inst_AS_000_INT{ F} + : SM_AMIGA_5_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + : SM_AMIGA_i_7_{ F} +inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_D{ E} +inst_CLK_OUT_PRE_D{ F}: CLK_DIV_OUT{ G} CLK_EXP{ B} + IPL_D0_0_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +CLK_000_D_4_{ E}: SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} +SM_AMIGA_1_{ D}: SM_AMIGA_1_{ C} SM_AMIGA_0_{ A}inst_DSACK1_INT{ A} +inst_UDS_000_INT{ C}: UDS_000{ D}inst_UDS_000_INT{ B} +inst_DS_000_ENABLE{ G}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ F} +inst_LDS_000_INT{ C}: LDS_000{ D}inst_LDS_000_INT{ B} +SM_AMIGA_6_{ G}: RW_000{ H}inst_UDS_000_INT{ B}inst_DS_000_ENABLE{ F} + :inst_LDS_000_INT{ B} SM_AMIGA_6_{ F}inst_AS_000_INT{ F} : SM_AMIGA_5_{ D} -SM_AMIGA_4_{ H}:inst_DS_000_ENABLE{ D} SM_AMIGA_4_{ G} SM_AMIGA_3_{ A} -SM_AMIGA_1_{ B}: DSACK1{ H} SM_AMIGA_1_{ A} SM_AMIGA_0_{ H} -SM_AMIGA_0_{ I}: RW_000{ H} SM_AMIGA_0_{ H} SM_AMIGA_i_7_{ B} - RST_DLY_0_{ B}: inst_RESET_OUT{ A} RST_DLY_0_{ A} RST_DLY_1_{ A} +SM_AMIGA_4_{ D}:inst_DS_000_ENABLE{ F} SM_AMIGA_4_{ C} SM_AMIGA_3_{ C} +SM_AMIGA_0_{ B}: RW_000{ H} SM_AMIGA_0_{ A} SM_AMIGA_i_7_{ F} + RST_DLY_0_{ D}: inst_RESET_OUT{ A} RST_DLY_0_{ C} RST_DLY_1_{ A} : RST_DLY_2_{ A} - RST_DLY_1_{ B}: inst_RESET_OUT{ A} RST_DLY_0_{ A} RST_DLY_1_{ A} + RST_DLY_1_{ B}: inst_RESET_OUT{ A} RST_DLY_0_{ C} RST_DLY_1_{ A} : RST_DLY_2_{ A} - RST_DLY_2_{ B}: inst_RESET_OUT{ A} RST_DLY_0_{ A} RST_DLY_1_{ A} + RST_DLY_2_{ B}: inst_RESET_OUT{ A} RST_DLY_0_{ C} RST_DLY_1_{ A} : RST_DLY_2_{ A} -inst_CLK_030_H{ D}:inst_DS_000_DMA{ F} inst_CLK_030_H{ C} -SM_AMIGA_5_{ E}: SM_AMIGA_4_{ G} SM_AMIGA_5_{ D} -SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -SM_AMIGA_2_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_2_{ A} -SM_AMIGA_i_7_{ C}: RW_000{ H}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ B} - : SM_AMIGA_i_7_{ B} +inst_CLK_030_H{ H}:inst_DS_000_DMA{ G} inst_CLK_030_H{ G} +inst_DSACK1_INT{ B}: DSACK1{ H}inst_DSACK1_INT{ A} +inst_AS_000_INT{ G}: AS_000{ E}inst_AS_000_INT{ F} +SM_AMIGA_5_{ E}: SM_AMIGA_4_{ C} SM_AMIGA_5_{ D} +SM_AMIGA_3_{ D}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +SM_AMIGA_2_{ D}: SM_AMIGA_1_{ C} SM_AMIGA_2_{ C} +SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_i_7_{ F} CIIN_0{ F}: CIIN{ E} ----------------------------------------------------------------------------- @@ -653,13 +656,14 @@ Equations : | | | | | DS_030 | | | | | AVEC | * | S | BS | BR | inst_RESET_OUT -| * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | inst_CLK_OUT_PRE_50 -| * | S | BS | BR | SM_AMIGA_2_ -| * | S | BS | BR | SM_AMIGA_3_ -| * | S | BS | BR | RST_DLY_0_ +| * | S | BS | BR | SM_AMIGA_0_ +| * | S | BS | BR | CYCLE_DMA_0_ +| * | S | BS | BR | inst_DSACK1_INT | * | S | BS | BR | RST_DLY_2_ | * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW +| * | S | BS | BR | inst_VPA_D | | | | | A_DECODE_19_ | | | | | A_DECODE_16_ | | | | | A_DECODE_18_ @@ -684,12 +688,12 @@ Equations : | * | S | BS | BR | CLK_EXP | | | | | RESET | * | S | BS | BR | CLK_000_D_0_ -| * | S | BS | BR | SM_AMIGA_6_ -| * | S | BS | BR | cpu_est_0_ -| * | S | BS | BR | SM_AMIGA_i_7_ +| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | inst_UDS_000_INT | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ +| * | S | BS | BR | IPL_D0_1_ Block C @@ -705,12 +709,12 @@ Equations : | | | | | AHIGH_27_ | | | | | AHIGH_28_ | | | | | AMIGA_BUS_ENABLE_LOW -| * | S | BS | BR | inst_AS_000_DMA -| * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | SIZE_DMA_0_ -| * | S | BS | BR | inst_CLK_030_H -| * | S | BS | BR | IPL_D0_2_ -| * | S | BS | BR | IPL_D0_0_ +| * | S | BS | BR | RST_DLY_0_ +| * | S | BS | BR | SM_AMIGA_1_ +| * | S | BS | BR | SM_AMIGA_4_ +| * | S | BS | BR | SM_AMIGA_2_ +| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | inst_DTACK_D0 | | | | | BG_030 @@ -727,14 +731,14 @@ Equations : | | | | | AMIGA_BUS_ENABLE_HIGH | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE +| * | S | BS | BR | CLK_000_D_3_ | * | S | BS | BR | cpu_est_3_ +| * | S | BS | BR | cpu_est_2_ | * | S | BS | BR | RN_VMA | * | S | BS | BR | SM_AMIGA_5_ -| * | S | BS | BR | inst_AS_000_INT -| * | S | BS | BR | inst_DS_000_ENABLE | * | S | BS | BR | RN_BG_000 -| * | S | BS | BR | inst_UDS_000_INT -| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | IPL_D0_0_ | | | | | BGACK_000 | | | | | DTACK @@ -750,10 +754,9 @@ Equations : | | | | | BERR | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN -| * | S | BS | BR | inst_AS_030_D0 -| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BS | BR | inst_CLK_OUT_PRE_D | | | | | CIIN_0 -| * | S | BS | BR | CLK_000_D_2_ +| * | S | BS | BR | inst_CLK_OUT_PRE_50 Block F @@ -763,16 +766,16 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | inst_DS_000_DMA -| * | S | BS | BR | inst_LDS_000_INT -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW -| * | S | BS | BR | inst_VPA_D +| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | inst_AS_030_000_SYNC +| * | S | BS | BR | SM_AMIGA_i_7_ +| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | inst_AS_000_INT | | | | | A_DECODE_17_ | | | | | FC_1_ | | | | | FC_0_ -| | | | | IPL_1_ | | | | | A_1_ +| | | | | IPL_1_ Block G @@ -782,20 +785,21 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | A_0_ | * | S | BS | BR | RW -| | | | | SIZE_0_ +| * | S | BS | BR | SIZE_0_ +| * | S | BS | BR | A_0_ | | | | | E | * | S | BS | BR | CLK_DIV_OUT -| * | S | BS | BR | CYCLE_DMA_1_ | * | S | BS | BR | cpu_est_1_ -| * | S | BS | BR | SM_AMIGA_4_ -| * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | SIZE_DMA_1_ -| * | S | BS | BR | inst_CLK_OUT_PRE_25 +| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | inst_DS_000_DMA +| * | S | BS | BR | inst_AS_000_DMA +| * | S | BS | BR | inst_CLK_030_H +| * | S | BS | BR | CYCLE_DMA_1_ | * | S | BS | BR | RN_A_0_ +| * | S | BS | BR | RN_SIZE_0_ | * | S | BS | BR | RN_RW +| * | S | BS | BR | IPL_D0_2_ | | | | | IPL_2_ | | | | | IPL_0_ @@ -807,19 +811,19 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | RW_000 | | | | | AS_030 -| | | | | SIZE_1_ +| * | S | BS | BR | RW_000 +| * | S | BS | BR | SIZE_1_ | * | S | BS | BR | BGACK_030 -| * | S | BS | BR | DSACK1 +| | | | | DSACK1 | | | | | FPU_CS | * | S | BS | BR | RN_BGACK_030 | * | S | BS | BR | CLK_000_D_1_ -| * | S | BS | BR | SM_AMIGA_0_ -| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BS | BR | CLK_000_D_2_ +| * | S | BS | BR | inst_AS_030_D0 | * | S | BS | BR | RN_RW_000 -| * | S | BS | BR | RN_DSACK1 -| * | S | BS | BR | inst_DTACK_D0 +| * | S | BS | BR | RN_SIZE_1_ | | | | | A_DECODE_23_ | | | | | A_DECODE_22_ @@ -838,22 +842,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 RST pin 86 mx A17 BERR pin 41 -mx A1 RN_VMA mcell D0 mx A18 SM_AMIGA_2_ mcell A5 -mx A2 cpu_est_0_ mcell B10 mx A19 SM_AMIGA_3_ mcell A9 -mx A3 inst_RESET_OUT mcell A8 mx A20 RN_BGACK_030 mcell H4 -mx A4 CLK_000_D_1_ mcell H5 mx A21 inst_DTACK_D0 mcell H6 -mx A5 nEXP_SPACE pin 14 mx A22 RST_DLY_2_ mcell A2 -mx A6 ... ... mx A23 cpu_est_2_ mcell G6 -mx A7 cpu_est_3_ mcell D9 mx A24 SM_AMIGA_1_ mcell A12 -mx A8 ... ... mx A25 RST_DLY_0_ mcell A13 -mx A9inst_CLK_OUT_PRE_50 mcell A1 mx A26 ... ... -mx A10 CLK_000_D_0_ mcell B13 mx A27 cpu_est_1_ mcell G9 -mx A11 ... ... mx A28 ... ... -mx A12 SM_AMIGA_4_ mcell G13 mx A29 ... ... -mx A13 ... ... mx A30 inst_VPA_D mcell F1 -mx A14 ... ... mx A31 inst_DS_000_DMA mcell F0 -mx A15 RST_DLY_1_ mcell A6 mx A32 ... ... +mx A0 RST_DLY_1_ mcell A13 mx A17 ... ... +mx A1 ... ... mx A18 inst_RESET_OUT mcell A8 +mx A2 inst_DSACK1_INT mcell A5 mx A19inst_BGACK_030_INT_D mcell H13 +mx A3 RST_DLY_0_ mcell C9 mx A20 RN_BGACK_030 mcell H4 +mx A4 CLK_000_D_2_ mcell H2 mx A21 RST pin 86 +mx A5 nEXP_SPACE pin 14 mx A22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell A2 +mx A6 ... ... mx A23 ... ... +mx A7 CLK_000_D_3_ mcell D9 mx A24 SM_AMIGA_0_ mcell A12 +mx A8 ... ... mx A25 inst_DS_000_DMA mcell G13 +mx A9 AS_030 pin 82 mx A26 ... ... +mx A10 CLK_000_D_0_ mcell B13 mx A27 CLK_000_D_1_ mcell H5 +mx A11 A_1_ pin 60 mx A28 ... ... +mx A12 CYCLE_DMA_0_ mcell A1 mx A29 RST_DLY_2_ mcell A9 +mx A13 VPA pin 36 mx A30 SM_AMIGA_1_ mcell C13 +mx A14 ... ... mx A31 ... ... +mx A15inst_AMIGA_BUS_ENABLE_DMA_LOW mcell A6 mx A32 ... ... mx A16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -862,23 +866,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 IPL_0_ pin 67 mx B17 IPL_D0_1_ mcell D14 +mx B0 IPL_0_ pin 67 mx B17 ... ... mx B1 ... ... mx B18 inst_RESET_OUT mcell A8 -mx B2 CLK_000_D_2_ mcell E13 mx B19 SM_AMIGA_0_ mcell H13 +mx B2inst_UDS_000_INT mcell B10 mx B19 ... ... mx B3 CLK_000 pin 11 mx B20 RN_BGACK_030 mcell H4 mx B4 IPL_2_ pin 68 mx B21 IPL_1_ pin 56 mx B5 nEXP_SPACE pin 14 mx B22 ... ... -mx B6 RN_IPL_030_1_ mcell B9 mx B23 SM_AMIGA_6_ mcell B6 -mx B7 IPL_D0_0_ mcell C14 mx B24 RST pin 86 -mx B8 IPL_D0_2_ mcell C10 mx B25 ... ... -mx B9 SM_AMIGA_i_7_ mcell B14 mx B26 ... ... -mx B10 CLK_000_D_0_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 -mx B11inst_AS_030_000_SYNC mcell C13 mx B28 RN_IPL_030_0_ mcell B5 -mx B12 cpu_est_0_ mcell B10 mx B29 ... ... -mx B13 CLK_000_D_1_ mcell H5 mx B30 ... ... -mx B14inst_CLK_OUT_PRE_D mcell H2 mx B31 ... ... -mx B15 ... ... mx B32 ... ... -mx B16 ... ... +mx B6 SIZE_1_ pin 79 mx B23inst_LDS_000_INT mcell B6 +mx B7 ... ... mx B24 RST pin 86 +mx B8inst_CLK_OUT_PRE_D mcell E8 mx B25 SM_AMIGA_6_ mcell F0 +mx B9 IPL_D0_1_ mcell B14 mx B26 ... ... +mx B10 IPL_D0_0_ mcell D14 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 IPL_D0_2_ mcell G14 mx B28 RN_IPL_030_0_ mcell B5 +mx B12 ... ... mx B29 ... ... +mx B13 ... ... mx B30 ... ... +mx B14 SIZE_0_ pin 70 mx B31 ... ... +mx B15 A_0_ pin 69 mx B32 ... ... +mx B16 RN_IPL_030_1_ mcell B9 ---------------------------------------------------------------------------- @@ -886,23 +890,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 IPL_0_ pin 67 mx C17 A_DECODE_18_ pin 95 -mx C1 FC_1_ pin 58 mx C18 inst_CLK_030_H mcell C6 -mx C2 SIZE_DMA_0_ mcell C2 mx C19 ... ... -mx C3 inst_RESET_OUT mcell A8 mx C20 RN_BGACK_030 mcell H4 -mx C4 CLK_030 pin 64 mx C21 RST pin 86 -mx C5 nEXP_SPACE pin 14 mx C22 IPL_2_ pin 68 -mx C6 FC_0_ pin 57 mx C23 CYCLE_DMA_0_ mcell G2 -mx C7 ... ... mx C24 LDS_000 pin 31 -mx C8 UDS_000 pin 32 mx C25 ... ... -mx C9 SM_AMIGA_i_7_ mcell B14 mx C26 AS_000 pin 42 -mx C10 ... ... mx C27 A_DECODE_17_ pin 59 -mx C11 A_DECODE_16_ pin 96 mx C28 ... ... -mx C12 A_DECODE_19_ pin 97 mx C29 ... ... -mx C13 inst_AS_000_DMA mcell C9 mx C30inst_AS_030_000_SYNC mcell C13 -mx C14inst_BGACK_030_INT_D mcell E5 mx C31inst_AMIGA_BUS_ENABLE_DMA_LOW mcell F12 -mx C15 ... ... mx C32 CYCLE_DMA_1_ mcell G5 -mx C16 inst_AS_030_D0 mcell E8 +mx C0 RST pin 86 mx C17 BERR pin 41 +mx C1 RN_VMA mcell D0 mx C18 inst_DTACK_D0 mcell C14 +mx C2 RST_DLY_2_ mcell A9 mx C19 ... ... +mx C3 RST_DLY_0_ mcell C9 mx C20 RN_BGACK_030 mcell H4 +mx C4 SM_AMIGA_5_ mcell D6 mx C21 cpu_est_3_ mcell D13 +mx C5 nEXP_SPACE pin 14 mx C22 SM_AMIGA_4_ mcell C2 +mx C6 ... ... mx C23 ... ... +mx C7 CLK_000_D_3_ mcell D9 mx C24 ... ... +mx C8 inst_VPA_D mcell A10 mx C25 RST_DLY_1_ mcell A13 +mx C9 SM_AMIGA_2_ mcell C6 mx C26 SM_AMIGA_3_ mcell C10 +mx C10 CLK_000_D_0_ mcell B13 mx C27 ... ... +mx C11 SM_AMIGA_1_ mcell C13 mx C28 CLK_000_D_2_ mcell H2 +mx C12 cpu_est_0_ mcell G9 mx C29 ... ... +mx C13 CLK_000_D_1_ mcell H5 mx C30 inst_RESET_OUT mcell A8 +mx C14 DTACK pin 30 mx C31 ... ... +mx C15inst_AMIGA_BUS_ENABLE_DMA_LOW mcell A6 mx C32 cpu_est_1_ mcell G5 +mx C16 cpu_est_2_ mcell D2 ---------------------------------------------------------------------------- @@ -910,23 +914,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RN_BGACK_030 mcell H4 mx D17 RN_BG_000 mcell D1 -mx D1 RN_VMA mcell D0 mx D18 A_0_ pin 69 -mx D2 SM_AMIGA_6_ mcell B6 mx D19 ... ... -mx D3 IPL_1_ pin 56 mx D20inst_UDS_000_INT mcell D10 +mx D0 IPL_0_ pin 67 mx D17 ... ... +mx D1inst_DS_000_ENABLE mcell F12 mx D18 RN_VMA mcell D0 +mx D2 RN_BG_000 mcell D1 mx D19 ... ... +mx D3 cpu_est_2_ mcell D2 mx D20 RN_BGACK_030 mcell H4 mx D4 BG_030 pin 21 mx D21 RST pin 86 -mx D5 nEXP_SPACE pin 14 mx D22 ... ... -mx D6 ... ... mx D23 cpu_est_2_ mcell G6 -mx D7 cpu_est_3_ mcell D9 mx D24 cpu_est_0_ mcell B10 -mx D8 inst_AS_030_D0 mcell E8 mx D25 RW pin 71 -mx D9 SM_AMIGA_4_ mcell G13 mx D26 ... ... -mx D10 CLK_000_D_0_ mcell B13 mx D27 ... ... -mx D11inst_AS_030_000_SYNC mcell C13 mx D28 inst_AS_000_INT mcell D2 -mx D12 cpu_est_1_ mcell G9 mx D29 SM_AMIGA_5_ mcell D13 +mx D5 nEXP_SPACE pin 14 mx D22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell A2 +mx D6 ... ... mx D23 ... ... +mx D7 inst_AS_030_D0 mcell H6 mx D24 ... ... +mx D8 inst_VPA_D mcell A10 mx D25 CLK_000_D_3_ mcell D9 +mx D9 ... ... mx D26 ... ... +mx D10inst_AS_030_000_SYNC mcell F4 mx D27 cpu_est_0_ mcell G9 +mx D11inst_LDS_000_INT mcell B6 mx D28 CLK_000_D_0_ mcell B13 +mx D12inst_UDS_000_INT mcell B10 mx D29 cpu_est_3_ mcell D13 mx D13 CLK_000_D_1_ mcell H5 mx D30 inst_RESET_OUT mcell A8 -mx D14inst_LDS_000_INT mcell F4 mx D31 ... ... -mx D15 inst_VPA_D mcell F1 mx D32inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell F8 -mx D16inst_DS_000_ENABLE mcell D6 +mx D14 CLK_000_D_2_ mcell H2 mx D31 SM_AMIGA_6_ mcell F0 +mx D15 ... ... mx D32 cpu_est_1_ mcell G5 +mx D16 SM_AMIGA_5_ mcell D6 ---------------------------------------------------------------------------- @@ -934,23 +938,23 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 RST pin 86 mx E17 AHIGH_26_ pin 17 -mx E1 FC_1_ pin 58 mx E18 BGACK_000 pin 28 -mx E2 AS_000 pin 42 mx E19 AS_030 pin 82 -mx E3 inst_AS_000_INT mcell D2 mx E20 RN_BGACK_030 mcell H4 -mx E4 AHIGH_29_ pin 6 mx E21 nEXP_SPACE pin 14 -mx E5 AHIGH_24_ pin 19 mx E22 AHIGH_25_ pin 18 -mx E6 RW_000 pin 80 mx E23 ... ... -mx E7 AHIGH_28_ pin 15 mx E24 FC_0_ pin 57 +mx E0 RN_BGACK_030 mcell H4 mx E17 A_DECODE_18_ pin 95 +mx E1 FC_1_ pin 58 mx E18 A_DECODE_23_ pin 85 +mx E2inst_CLK_OUT_PRE_50 mcell E9 mx E19 AHIGH_30_ pin 5 +mx E3 A_DECODE_20_ pin 93 mx E20 AHIGH_24_ pin 19 +mx E4 BGACK_000 pin 28 mx E21 AHIGH_27_ pin 16 +mx E5 A_DECODE_21_ pin 94 mx E22 AHIGH_25_ pin 18 +mx E6 A_DECODE_16_ pin 96 mx E23 ... ... +mx E7 inst_AS_030_D0 mcell H6 mx E24 FC_0_ pin 57 mx E8 FPU_SENSE pin 91 mx E25 AHIGH_31_ pin 4 -mx E9 A_DECODE_22_ pin 84 mx E26 A_DECODE_16_ pin 96 -mx E10 ... ... mx E27 CLK_000_D_1_ mcell H5 -mx E11 AHIGH_27_ pin 16 mx E28 AHIGH_30_ pin 5 -mx E12 A_DECODE_19_ pin 97 mx E29 A_DECODE_20_ pin 93 -mx E13 A_DECODE_17_ pin 59 mx E30 inst_RESET_OUT mcell A8 -mx E14 CIIN_0 mcell E9 mx E31 A_DECODE_18_ pin 95 -mx E15 A_DECODE_21_ pin 94 mx E32 A_DECODE_23_ pin 85 -mx E16 inst_AS_030_D0 mcell E8 +mx E9 AHIGH_26_ pin 17 mx E26 CIIN_0 mcell E5 +mx E10 inst_AS_000_INT mcell F1 mx E27 A_DECODE_17_ pin 59 +mx E11 A_DECODE_22_ pin 84 mx E28 RW_000 pin 80 +mx E12 A_DECODE_19_ pin 97 mx E29 ... ... +mx E13 AHIGH_29_ pin 6 mx E30 inst_RESET_OUT mcell A8 +mx E14 AHIGH_28_ pin 15 mx E31 ... ... +mx E15 nEXP_SPACE pin 14 mx E32 AS_030 pin 82 +mx E16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -958,23 +962,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0 RST pin 86 mx F17 SIZE_0_ pin 70 -mx F1inst_AMIGA_BUS_ENABLE_DMA_LOW mcell F12 mx F18 ... ... -mx F2inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell F8 mx F19 ... ... -mx F3 A_1_ pin 60 mx F20 RN_BGACK_030 mcell H4 -mx F4 CLK_030 pin 64 mx F21 RW_000 pin 80 -mx F5 inst_DS_000_DMA mcell F0 mx F22 CYCLE_DMA_1_ mcell G5 -mx F6 SIZE_1_ pin 79 mx F23 CYCLE_DMA_0_ mcell G2 -mx F7 ... ... mx F24 LDS_000 pin 31 -mx F8 UDS_000 pin 32 mx F25 ... ... -mx F9 inst_CLK_030_H mcell C6 mx F26inst_BGACK_030_INT_D mcell E5 -mx F10 VPA pin 36 mx F27 ... ... -mx F11 SM_AMIGA_6_ mcell B6 mx F28 ... ... -mx F12 ... ... mx F29 ... ... -mx F13 inst_AS_000_DMA mcell C9 mx F30 ... ... -mx F14inst_LDS_000_INT mcell F4 mx F31 ... ... -mx F15 A_0_ pin 69 mx F32 ... ... -mx F16 AS_000 pin 42 +mx F0 RST pin 86 mx F17 A_DECODE_18_ pin 95 +mx F1inst_DS_000_ENABLE mcell F12 mx F18 ... ... +mx F2 CLK_000_D_4_ mcell D10 mx F19inst_BGACK_030_INT_D mcell H13 +mx F3 ... ... mx F20 SM_AMIGA_i_7_ mcell F8 +mx F4 CLK_000_D_1_ mcell H5 mx F21 CLK_000_D_0_ mcell B13 +mx F5 nEXP_SPACE pin 14 mx F22 SM_AMIGA_4_ mcell C2 +mx F6 A_DECODE_19_ pin 97 mx F23 RN_BGACK_030 mcell H4 +mx F7 inst_AS_030_D0 mcell H6 mx F24 FC_0_ pin 57 +mx F8 RW pin 71 mx F25 CLK_000_D_3_ mcell D9 +mx F9 SM_AMIGA_0_ mcell A12 mx F26 ... ... +mx F10 inst_AS_000_INT mcell F1 mx F27 ... ... +mx F11 A_DECODE_16_ pin 96 mx F28 ... ... +mx F12 FC_1_ pin 58 mx F29 ... ... +mx F13 A_DECODE_17_ pin 59 mx F30 ... ... +mx F14inst_AS_030_000_SYNC mcell F4 mx F31 SM_AMIGA_6_ mcell F0 +mx F15 ... ... mx F32 AS_030 pin 82 +mx F16 ... ... ---------------------------------------------------------------------------- @@ -982,23 +986,23 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 LDS_000 pin 31 mx G17 RN_RW mcell G0 -mx G1 SM_AMIGA_5_ mcell D13 mx G18 inst_RESET_OUT mcell A8 -mx G2 SIZE_DMA_0_ mcell C2 mx G19 ... ... -mx G3inst_BGACK_030_INT_D mcell E5 mx G20 RN_BGACK_030 mcell H4 -mx G4 CLK_000_D_1_ mcell H5 mx G21 RST pin 86 -mx G5 nEXP_SPACE pin 14 mx G22 SIZE_DMA_1_ mcell G10 -mx G6 RW_000 pin 80 mx G23 cpu_est_2_ mcell G6 -mx G7 cpu_est_3_ mcell D9 mx G24 cpu_est_0_ mcell B10 +mx G0 RST pin 86 mx G17 RN_RW mcell G0 +mx G1 cpu_est_3_ mcell D13 mx G18 inst_RESET_OUT mcell A8 +mx G2 AS_000 pin 42 mx G19inst_BGACK_030_INT_D mcell H13 +mx G3 cpu_est_2_ mcell D2 mx G20 RN_BGACK_030 mcell H4 +mx G4 CLK_030 pin 64 mx G21 CLK_000_D_0_ mcell B13 +mx G5 nEXP_SPACE pin 14 mx G22 IPL_2_ pin 68 +mx G6 RW_000 pin 80 mx G23 inst_CLK_030_H mcell G6 +mx G7 RN_SIZE_0_ mcell G12 mx G24 LDS_000 pin 31 mx G8 UDS_000 pin 32 mx G25 ... ... -mx G9inst_CLK_OUT_PRE_50 mcell A1 mx G26 ... ... -mx G10 CLK_000_D_0_ mcell B13 mx G27 cpu_est_1_ mcell G9 -mx G11inst_CLK_OUT_PRE_25 mcell G14 mx G28 ... ... -mx G12 SM_AMIGA_4_ mcell G13 mx G29 ... ... -mx G13 RN_A_0_ mcell G8 mx G30 ... ... -mx G14inst_CLK_OUT_PRE_D mcell H2 mx G31 CYCLE_DMA_0_ mcell G2 -mx G15 ... ... mx G32 CYCLE_DMA_1_ mcell G5 -mx G16 AS_000 pin 42 +mx G9 CYCLE_DMA_0_ mcell A1 mx G26 ... ... +mx G10 RN_A_0_ mcell G8 mx G27 cpu_est_0_ mcell G9 +mx G11 ... ... mx G28 CYCLE_DMA_1_ mcell G10 +mx G12 inst_DS_000_DMA mcell G13 mx G29 ... ... +mx G13 CLK_000_D_1_ mcell H5 mx G30 ... ... +mx G14 ... ... mx G31 inst_AS_000_DMA mcell G2 +mx G15 ... ... mx G32 cpu_est_1_ mcell G5 +mx G16inst_CLK_OUT_PRE_D mcell E8 ---------------------------------------------------------------------------- @@ -1007,21 +1011,21 @@ BLOCK_H_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RN_BGACK_030 mcell H4 mx H17 FC_0_ pin 57 -mx H1 FC_1_ pin 58 mx H18 inst_RESET_OUT mcell A8 -mx H2 SIZE_DMA_0_ mcell C2 mx H19 AS_030 pin 82 -mx H3 inst_AS_000_DMA mcell C9 mx H20 SM_AMIGA_i_7_ mcell B14 -mx H4 BGACK_000 pin 28 mx H21 RST pin 86 -mx H5 RN_DSACK1 mcell H9 mx H22 SIZE_DMA_1_ mcell G10 -mx H6 RN_RW_000 mcell H0 mx H23 SM_AMIGA_6_ mcell B6 -mx H7 SM_AMIGA_0_ mcell H13 mx H24 ... ... -mx H8 FPU_SENSE pin 91 mx H25 RW pin 71 -mx H9 SM_AMIGA_1_ mcell A12 mx H26 A_DECODE_16_ pin 96 +mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 +mx H2 inst_DSACK1_INT mcell A5 mx H19 FPU_SENSE pin 91 +mx H3 inst_RESET_OUT mcell A8 mx H20 SM_AMIGA_i_7_ mcell F8 +mx H4 A_DECODE_18_ pin 95 mx H21 RST pin 86 +mx H5 nEXP_SPACE pin 14 mx H22 ... ... +mx H6 A_DECODE_19_ pin 97 mx H23 RN_RW_000 mcell H0 +mx H7inst_BGACK_030_INT_D mcell H13 mx H24 LDS_000 pin 31 +mx H8 RW pin 71 mx H25 SM_AMIGA_6_ mcell F0 +mx H9 AS_030 pin 82 mx H26 ... ... mx H10 CLK_000_D_0_ mcell B13 mx H27 CLK_000_D_1_ mcell H5 -mx H11inst_CLK_OUT_PRE_25 mcell G14 mx H28 ... ... -mx H12 A_DECODE_19_ pin 97 mx H29 ... ... -mx H13 A_DECODE_17_ pin 59 mx H30 inst_AS_030_D0 mcell E8 -mx H14 DTACK pin 30 mx H31 A_DECODE_18_ pin 95 -mx H15 nEXP_SPACE pin 14 mx H32 ... ... +mx H11 A_DECODE_16_ pin 96 mx H28 ... ... +mx H12 UDS_000 pin 32 mx H29 RN_SIZE_1_ mcell H12 +mx H13 A_DECODE_17_ pin 59 mx H30 ... ... +mx H14 ... ... mx H31 inst_AS_000_DMA mcell G2 +mx H15 SM_AMIGA_0_ mcell A12 mx H32 ... ... mx H16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -1037,8 +1041,6 @@ PostFit_Equations P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- - 1 2 1 Pin SIZE_1_ - 1 2 1 Pin SIZE_1_.OE 0 0 1 Pin AHIGH_31_ 1 3 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- @@ -1053,23 +1055,23 @@ PostFit_Equations 1 2 1 Pin LDS_000.OE 0 0 1 Pin BERR 1 9 1 Pin BERR.OE - 1 2 1 Pin SIZE_0_ - 1 2 1 Pin SIZE_0_.OE 0 0 1 Pin AHIGH_30_ 1 3 1 Pin AHIGH_30_.OE - 1 1 1 Pin CLK_DIV_OUT.D - 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_29_ 1 3 1 Pin AHIGH_29_.OE + 1 1 1 Pin CLK_DIV_OUT.D + 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_28_ 1 3 1 Pin AHIGH_28_.OE - 1 9 1 Pin FPU_CS- 0 0 1 Pin AHIGH_27_ 1 3 1 Pin AHIGH_27_.OE + 1 9 1 Pin FPU_CS- 0 0 1 Pin AHIGH_26_ 1 3 1 Pin AHIGH_26_.OE 0 0 1 Pin AHIGH_25_ 1 3 1 Pin AHIGH_25_.OE + 1 2 1 Pin DSACK1- + 1 1 1 Pin DSACK1.OE 0 0 1 Pin AHIGH_24_ 1 3 1 Pin AHIGH_24_.OE 1 0 1 Pin AVEC @@ -1082,6 +1084,9 @@ PostFit_Equations 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_1_.OE + 3 6 1 Pin SIZE_1_.D + 1 1 1 Pin SIZE_1_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -1091,11 +1096,11 @@ PostFit_Equations 1 1 1 Pin BG_000.C 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C + 1 2 1 Pin SIZE_0_.OE + 3 6 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C - 1 1 1 Pin DSACK1.OE - 2 6 1 Pin DSACK1.D- - 1 1 1 Pin DSACK1.C 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C 1 2 1 Pin RW.OE @@ -1108,22 +1113,20 @@ PostFit_Equations 1 1 1 Pin IPL_030_1_.C 10 8 1 Pin IPL_030_0_.D- 1 1 1 Pin IPL_030_0_.C - 1 1 1 NodeX1 cpu_est_2_.D.X1 - 1 4 1 NodeX2 cpu_est_2_.D.X2 - 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 2 6 1 Node inst_AS_000_INT.D- - 1 1 1 Node inst_AS_000_INT.C + 1 4 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 + 1 1 1 Node cpu_est_2_.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C - 7 13 1 Node inst_AS_030_000_SYNC.D + 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C 1 2 1 Node inst_BGACK_030_INT_D.D- 1 1 1 Node inst_BGACK_030_INT_D.C @@ -1135,24 +1138,22 @@ PostFit_Equations 1 1 1 Node CYCLE_DMA_0_.C 4 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C - 3 6 1 Node SIZE_DMA_0_.D- - 1 1 1 Node SIZE_DMA_0_.C - 3 6 1 Node SIZE_DMA_1_.D - 1 1 1 Node SIZE_DMA_1_.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C - 1 1 1 Node CLK_000_D_1_.D - 1 1 1 Node CLK_000_D_1_.C + 1 1 1 Node CLK_000_D_2_.D + 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_3_.D + 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 7 1 Node inst_RESET_OUT.D 1 1 1 Node inst_RESET_OUT.C + 1 1 1 Node CLK_000_D_1_.D + 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C - 2 2 1 Node inst_CLK_OUT_PRE_25.D - 1 1 1 Node inst_CLK_OUT_PRE_25.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C 1 2 1 Node IPL_D0_0_.D- @@ -1161,23 +1162,23 @@ PostFit_Equations 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C - 1 1 1 Node CLK_000_D_2_.D - 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_4_.D + 1 1 1 Node CLK_000_D_4_.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 3 6 1 Node inst_LDS_000_INT.D - 1 1 1 Node inst_LDS_000_INT.C - 3 8 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C + 4 7 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 2 4 1 Node inst_UDS_000_INT.D- 1 1 1 Node inst_UDS_000_INT.C - 3 8 1 Node SM_AMIGA_6_.D + 3 8 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 3 6 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.C + 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C - 3 5 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 3 5 1 Node SM_AMIGA_0_.D + 4 7 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C 4 6 1 Node RST_DLY_0_.D 1 1 1 Node RST_DLY_0_.C @@ -1188,18 +1189,22 @@ PostFit_Equations 1 1 1 Node RST_DLY_2_.C 8 10 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C + 2 6 1 Node inst_DSACK1_INT.D- + 1 1 1 Node inst_DSACK1_INT.C + 2 6 1 Node inst_AS_000_INT.D- + 1 1 1 Node inst_AS_000_INT.C 3 5 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C 5 13 1 Node SM_AMIGA_3_.T 1 1 1 Node SM_AMIGA_3_.C 5 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C - 3 8 1 NodeX1 SM_AMIGA_i_7_.D.X1 - 1 5 1 NodeX2 SM_AMIGA_i_7_.D.X2 + 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 + 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 272 P-Term Total: 272 + 274 P-Term Total: 274 Total Pins: 61 Total Nodes: 44 Average P-Term/Output: 2 @@ -1207,10 +1212,6 @@ PostFit_Equations Equations: -SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); - -SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); - AHIGH_31_ = (0); AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -1227,11 +1228,11 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); -!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); +!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); @@ -1239,32 +1240,28 @@ BERR = (0); BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); -SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); - -SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); - AHIGH_30_ = (0); AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_DIV_OUT.C = (CLK_OSZI); - AHIGH_29_ = (0); AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_DIV_OUT.C = (CLK_OSZI); + AHIGH_28_ = (0); AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); - AHIGH_27_ = (0); AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); + AHIGH_26_ = (0); AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -1273,14 +1270,18 @@ AHIGH_25_ = (0); AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); + +DSACK1.OE = (nEXP_SPACE); + AHIGH_24_ = (0); AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); AVEC = (1); -E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q); +E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q); RESET = (0); @@ -1300,6 +1301,14 @@ CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030 CIIN.OE = (CIIN_0); +SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +SIZE_1_.D = (!RST + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_1_.Q + # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_1_.C = (CLK_OSZI); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -1333,20 +1342,21 @@ BGACK_030.D = (!RST BGACK_030.C = (CLK_OSZI); +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q + # RST & BGACK_030.Q & !SIZE_0_.Q + # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_0_.C = (CLK_OSZI); + CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); -DSACK1.OE = (nEXP_SPACE); - -!DSACK1.D = (RST & !inst_AS_030_D0.Q & !DSACK1.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); - -DSACK1.C = (CLK_OSZI); - VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q - # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + # !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q + # RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); VMA.C = (CLK_OSZI); @@ -1391,16 +1401,10 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (cpu_est_2_.Q); - -cpu_est_2_.D.X2 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -cpu_est_2_.C = (CLK_OSZI); - cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q # cpu_est_3_.Q & CLK_000_D_0_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q - # cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + # cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q + # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_3_.C = (CLK_OSZI); @@ -1417,10 +1421,11 @@ cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q cpu_est_1_.C = (CLK_OSZI); -!inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); +cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); -inst_AS_000_INT.C = (CLK_OSZI); +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.C = (CLK_OSZI); !inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); @@ -1431,13 +1436,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); inst_AS_030_D0.C = (CLK_OSZI); -inst_AS_030_000_SYNC.D = (!RST - # inst_AS_030_D0.Q - # !nEXP_SPACE & inst_AS_030_000_SYNC.Q - # !BGACK_030.Q & inst_AS_030_000_SYNC.Q - # inst_AS_030_000_SYNC.Q & !inst_BGACK_030_INT_D.Q - # inst_AS_030_000_SYNC.Q & SM_AMIGA_i_7_.Q - # FC_1_ & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); +!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_000_SYNC.Q & !AS_030.PIN + # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); @@ -1480,25 +1485,17 @@ CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_00 CYCLE_DMA_1_.C = (CLK_OSZI); -!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q - # RST & BGACK_030.Q & !SIZE_DMA_0_.Q - # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_DMA_0_.C = (CLK_OSZI); - -SIZE_DMA_1_.D = (!RST - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q - # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_DMA_1_.C = (CLK_OSZI); - !inst_VPA_D.D = (!VPA & RST); inst_VPA_D.C = (CLK_OSZI); -CLK_000_D_1_.D = (CLK_000_D_0_.Q); +CLK_000_D_2_.D = (CLK_000_D_1_.Q); -CLK_000_D_1_.C = (CLK_OSZI); +CLK_000_D_2_.C = (CLK_OSZI); + +CLK_000_D_3_.D = (CLK_000_D_2_.Q); + +CLK_000_D_3_.C = (CLK_OSZI); !inst_DTACK_D0.D = (!DTACK & RST); @@ -1509,6 +1506,10 @@ inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q inst_RESET_OUT.C = (CLK_OSZI); +CLK_000_D_1_.D = (CLK_000_D_0_.Q); + +CLK_000_D_1_.C = (CLK_OSZI); + CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); @@ -1517,12 +1518,7 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); -inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q - # inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q); - -inst_CLK_OUT_PRE_25.C = (CLK_OSZI); - -inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q); +inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); @@ -1538,35 +1534,42 @@ IPL_D0_1_.C = (CLK_OSZI); IPL_D0_2_.C = (CLK_OSZI); -CLK_000_D_2_.D = (CLK_000_D_1_.Q); +CLK_000_D_4_.D = (CLK_000_D_3_.Q); -CLK_000_D_2_.C = (CLK_OSZI); +CLK_000_D_4_.C = (CLK_OSZI); !inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); +SM_AMIGA_1_.D = (RST & CLK_000_D_2_.Q & SM_AMIGA_1_.Q + # RST & !CLK_000_D_3_.Q & SM_AMIGA_1_.Q + # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + +!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); + +inst_UDS_000_INT.C = (CLK_OSZI); + +inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); inst_LDS_000_INT.C = (CLK_OSZI); -inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN); - -inst_DS_000_ENABLE.C = (CLK_OSZI); - -!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A_0_.PIN); - -inst_UDS_000_INT.C = (CLK_OSZI); - SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -1576,15 +1579,10 @@ SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q SM_AMIGA_4_.C = (CLK_OSZI); -SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q - # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); + # RST & SM_AMIGA_1_.Q & SM_AMIGA_0_.Q + # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); SM_AMIGA_0_.C = (CLK_OSZI); @@ -1618,6 +1616,16 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); +!inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN + # RST & !CLK_000_D_2_.Q & CLK_000_D_3_.Q & SM_AMIGA_1_.Q); + +inst_DSACK1_INT.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !AS_030.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); + +inst_AS_000_INT.C = (CLK_OSZI); + SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q # RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q); @@ -1625,26 +1633,26 @@ SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q SM_AMIGA_5_.C = (CLK_OSZI); SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q - # inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q + # CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN - # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q - # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q - # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN - # RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_i_7_.D.X1 = (RST & SM_AMIGA_i_7_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & !CLK_000_D_0_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); +SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); -SM_AMIGA_i_7_.D.X2 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q); +SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_4_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 53c78bb..4f5e839 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -32,34 +32,37 @@ TCR, Clocked Output-to-Register Time, TSU TCO TPD TCR #passes #passes #passes #passes SIGNAL NAME min max min max min max min max - inst_AS_000_INT 1 1 1 3 .. .. 2 3 inst_AS_000_DMA 1 2 1 3 .. .. 1 3 + inst_AS_000_INT 1 2 1 3 .. .. 2 3 DS_030 .. .. .. .. 1 2 .. .. FPU_CS .. .. .. .. 1 2 .. .. + DSACK1 .. .. .. .. 1 2 .. .. AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. BGACK_030 1 2 0 1 .. .. 1 1 RN_BGACK_030 1 2 0 1 .. .. 1 1 inst_AS_030_D0 1 2 1 1 .. .. 1 1 +inst_AS_030_000_SYNC 1 2 1 1 .. .. 1 1 inst_DS_000_DMA 1 2 1 1 .. .. .. .. CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1 - SIZE_DMA_0_ 1 1 1 1 .. .. 2 2 - SIZE_DMA_1_ 1 1 1 1 .. .. 2 2 -inst_LDS_000_INT 1 1 1 1 .. .. 2 2 -inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 +inst_DS_000_ENABLE 1 2 1 1 .. .. 2 2 +inst_LDS_000_INT 1 1 1 1 .. .. 2 2 inst_CLK_030_H 1 2 .. .. .. .. 1 1 + inst_DSACK1_INT 1 2 1 1 .. .. .. .. AS_030 .. .. .. .. 1 1 .. .. AS_000 .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. + SIZE_1_ 1 1 0 0 .. .. 1 1 + RN_SIZE_1_ 1 1 0 0 .. .. 1 1 IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 RW_000 1 1 0 0 .. .. 1 1 RN_RW_000 1 1 0 0 .. .. 1 1 BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 - DSACK1 1 1 0 0 .. .. 1 1 - RN_DSACK1 1 1 0 0 .. .. 1 1 + SIZE_0_ 1 1 0 0 .. .. 1 1 + RN_SIZE_0_ 1 1 0 0 .. .. 1 1 VMA 1 1 0 0 .. .. 1 1 RN_VMA 1 1 0 0 .. .. 1 1 RW 1 1 0 0 .. .. 1 1 @@ -70,29 +73,29 @@ inst_UDS_000_INT 1 1 1 1 .. .. 2 2 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 - cpu_est_2_ .. .. 1 1 .. .. 1 1 cpu_est_3_ .. .. 1 1 .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. 1 1 .. .. 1 1 + cpu_est_2_ .. .. 1 1 .. .. 1 1 inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. -inst_AS_030_000_SYNC 1 1 1 1 .. .. 1 1 inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 - CLK_000_D_1_ .. .. .. .. .. .. 1 1 + CLK_000_D_2_ .. .. .. .. .. .. 1 1 + CLK_000_D_3_ .. .. .. .. .. .. 1 1 inst_DTACK_D0 1 1 .. .. .. .. 1 1 inst_RESET_OUT 1 1 .. .. .. .. .. .. + CLK_000_D_1_ .. .. .. .. .. .. 1 1 CLK_000_D_0_ 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 -inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 IPL_D0_0_ 1 1 .. .. .. .. 1 1 IPL_D0_1_ 1 1 .. .. .. .. 1 1 IPL_D0_2_ 1 1 .. .. .. .. 1 1 - CLK_000_D_2_ .. .. .. .. .. .. 1 1 + CLK_000_D_4_ .. .. .. .. .. .. 1 1 inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. + SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 SM_AMIGA_4_ 1 1 .. .. .. .. 1 1 - SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 SM_AMIGA_0_ 1 1 .. .. .. .. 1 1 RST_DLY_0_ 1 1 .. .. .. .. 1 1 RST_DLY_1_ 1 1 .. .. .. .. 1 1 diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 3165bf7..2200c29 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,500 +1,503 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE 68030_tk -#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_ AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 43 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 AHIGH_30_ CLK_OSZI AHIGH_29_ CLK_DIV_OUT AHIGH_28_ AHIGH_27_ FPU_CS AHIGH_26_ FPU_SENSE AHIGH_25_ DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E A_DECODE_20_ VPA A_DECODE_19_ A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 43 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_2_ CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_4_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 95 -.o 157 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C CLK_000_D_2_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C inst_CLK_OUT_PRE_25.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C inst_AS_000_INT.C DSACK1.C VMA.C RW.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.C CLK_EXP.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D CLK_000_D_1_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 488 ------------------------------------------------------------------------------------------------ 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----0--------------------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------------1--------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0---------------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------------------------1-------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0----------------------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------------------------1------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-----------------------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------------------------------1------ ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0------------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------------------1----- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------------1---- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------------------1--- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0---------------------------------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------1---------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------1---------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -------------1----------------------------1-1--------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------1-1---------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------1--------------------------0----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------0--0----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -------------1-----------------------------0--1------------1--0----------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +.i 96 +.o 158 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_4_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS DSACK1 AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_0_.C SIZE_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_BGACK_030_INT_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_VPA_D.D CLK_000_D_2_.D CLK_000_D_3_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_4_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D SM_AMIGA_1_.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 491 +------------------------------------------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0--------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----0------------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1--------------------------------------------------------------------------------------- ~~~~~~~~~~~1111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0----------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~111111~~1~~1~~~~~111~1~1~1~~~1111~~~1~11~~~~1~111 +----------------1------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0----------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------------------0--0-------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------01-----------1-0--------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0--------------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index dfe7143..65f08fa 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,500 +1,503 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE 68030_tk -#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_ AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 43 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 AHIGH_30_ CLK_OSZI AHIGH_29_ CLK_DIV_OUT AHIGH_28_ AHIGH_27_ FPU_CS AHIGH_26_ FPU_SENSE AHIGH_25_ DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E A_DECODE_20_ VPA A_DECODE_19_ A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 43 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_2_ CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_4_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 95 -.o 157 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C CLK_000_D_2_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C inst_CLK_OUT_PRE_25.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C inst_AS_000_INT.C DSACK1.C VMA.C RW.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.C CLK_EXP.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D CLK_000_D_1_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 488 ------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1--------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0-------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1------------------------------------------------------------------------------------------- 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-------------1-----------0-------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------1-----------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------1------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------1---------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------------1--------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0---------------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------------------------1-------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0----------------------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------------------------1------- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-----------------------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------------------------------1------ ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0------------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------------------1----- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------------1---- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------------------1--- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0---------------------------------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------1---------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------1---------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -------------1----------------------------1-1--------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------1-1---------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------1--------------------------0----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------0--0----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -------------1-----------------------------0--1------------1--0----------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +.i 96 +.o 158 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_4_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS DSACK1 AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_0_.C SIZE_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_BGACK_030_INT_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_VPA_D.D CLK_000_D_2_.D CLK_000_D_3_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_4_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D SM_AMIGA_1_.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 491 +------------------------------------------------------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0--------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+--------------------------------------1--1------------------------------0---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------------------0--0-------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------01-----------1-0--------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0--------------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 9fd93a9..fbc1da2 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,257 +1,260 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE BUS68030 -#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 - UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ - CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE - AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA - A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_ - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH - CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 - VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT +#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 + LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 AHIGH_30_ CLK_OSZI + AHIGH_29_ CLK_DIV_OUT AHIGH_28_ AHIGH_27_ FPU_CS AHIGH_26_ FPU_SENSE AHIGH_25_ + DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E A_DECODE_20_ VPA + A_DECODE_19_ A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ + FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ CLK_EXP VMA RW + A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 44 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ - SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT - CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D - IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH - inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ - SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H - SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 + inst_VPA_D CLK_000_D_2_ CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ + CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ + IPL_D0_2_ CLK_000_D_4_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ + inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ + SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT + inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f -.i 96 -.o 161 +.i 97 +.o 162 .ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ - BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q - inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q - inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q - inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q - inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q - inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q - IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q - inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q - SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q - RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q - SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q - AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN - AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN - AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 -.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% - AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE - SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_29_ - AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE FPU_CS% AHIGH_27_ AHIGH_27_.OE AHIGH_26_ - AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH - CIIN CIIN.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C RW_000.OE BG_000.D% - BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D% DSACK1.C - DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D% - IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 - cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D - cpu_est_1_.C inst_AS_000_INT.D% inst_AS_000_INT.C - inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C - inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C - inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D - inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D - CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C - SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C CLK_000_D_1_.D - CLK_000_D_1_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D - inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D - inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% - IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C - inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - inst_LDS_000_INT.D inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C - inst_UDS_000_INT.D% inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D - SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C + BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q + inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q + inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q + CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_3_.Q inst_DTACK_D0.Q + inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q + inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_4_.Q + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q + inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q + SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q + RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q + SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q + IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN + LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN + AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN + BERR.PIN RW.PIN CIIN_0 +.ob AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE + UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE AHIGH_30_ AHIGH_30_.OE + AHIGH_29_ AHIGH_29_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_28_ AHIGH_28_.OE + AHIGH_27_ AHIGH_27_.OE FPU_CS% AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE + DSACK1% DSACK1.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE + SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C + RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D% SIZE_0_.C + SIZE_0_.OE CLK_EXP.D CLK_EXP.C VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C + A_0_.OE IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C cpu_est_3_.D + cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1 + cpu_est_2_.D.X2 cpu_est_2_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C + inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% + inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D + inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C + inst_VPA_D.D% inst_VPA_D.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D + CLK_000_D_3_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D + inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C + inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C + IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_4_.D CLK_000_D_4_.C + inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_1_.D + SM_AMIGA_1_.C inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_DS_000_ENABLE.D + inst_DS_000_ENABLE.C inst_LDS_000_INT.D inst_LDS_000_INT.C SM_AMIGA_6_.D + SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_0_.D SM_AMIGA_0_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C - RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_5_.D + RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_DSACK1_INT.D% + inst_DSACK1_INT.C inst_AS_000_INT.D% inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C - SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 SM_AMIGA_i_7_.C CIIN_0 -.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 183 ----------------------------------------01------------------------------------------------------- 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------0------------------------------------------------------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +------------1------------------------------01-------------1--------------1----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1-------------------0-------0---------1----------------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1-------------------0-------0--01-----1-------1--------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 48e0d6d..cbf1968 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,257 +1,260 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE BUS68030 -#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 - UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ - CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE - AHIGH_26_ AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA - A_DECODE_20_ A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ A_DECODE_16_ - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH - CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 - VMA RW A_0_ IPL_030_1_ IPL_030_0_ -#$ NODES 44 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT +#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 + LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 AHIGH_30_ CLK_OSZI + AHIGH_29_ CLK_DIV_OUT AHIGH_28_ AHIGH_27_ FPU_CS AHIGH_26_ FPU_SENSE AHIGH_25_ + DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E A_DECODE_20_ VPA + A_DECODE_19_ A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ + FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ CLK_EXP VMA RW + A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 44 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ - SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D CLK_000_D_1_ inst_DTACK_D0 inst_RESET_OUT - CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_OUT_PRE_D - IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ inst_AMIGA_BUS_ENABLE_DMA_HIGH - inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ - SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H - SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 + inst_VPA_D CLK_000_D_2_ CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ + CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ + IPL_D0_2_ CLK_000_D_4_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_1_ + inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ + SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT + inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f -.i 96 -.o 161 +.i 97 +.o 162 .ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ - BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q - inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q - inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q - inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q - inst_VPA_D.Q CLK_000_D_1_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q - inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q - IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q - inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q - SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q - RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q - SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q - AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN - AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN - AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 -.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- - AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE - SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_29_ - AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE FPU_CS- AHIGH_27_ AHIGH_27_.OE AHIGH_26_ - AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH - CIIN CIIN.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE BG_000.D- - BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D- DSACK1.C - DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D- - IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 - cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D - cpu_est_1_.C inst_AS_000_INT.D- inst_AS_000_INT.C - inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C - inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C - inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D - inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D - CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C - SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C CLK_000_D_1_.D - CLK_000_D_1_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D - inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D - inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- - IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C - inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - inst_LDS_000_INT.D inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C - inst_UDS_000_INT.D- inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D - SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C + BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q + inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q + inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q + CYCLE_DMA_1_.Q inst_VPA_D.Q CLK_000_D_2_.Q CLK_000_D_3_.Q inst_DTACK_D0.Q + inst_RESET_OUT.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q + inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_4_.Q + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q SM_AMIGA_1_.Q inst_UDS_000_INT.Q + inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q + SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q + RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q + SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q + IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN + LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN + AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN + BERR.PIN RW.PIN CIIN_0 +.ob AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE + UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE AHIGH_30_ AHIGH_30_.OE + AHIGH_29_ AHIGH_29_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AHIGH_28_ AHIGH_28_.OE + AHIGH_27_ AHIGH_27_.OE FPU_CS- AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE + DSACK1- DSACK1.OE AHIGH_24_ AHIGH_24_.OE AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE + SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C + RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D- SIZE_0_.C + SIZE_0_.OE CLK_EXP.D CLK_EXP.C VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C + A_0_.OE IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C cpu_est_3_.D + cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1 + cpu_est_2_.D.X2 cpu_est_2_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C + inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- + inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D + inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C + inst_VPA_D.D- inst_VPA_D.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D + CLK_000_D_3_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D + inst_RESET_OUT.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C + inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C + IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_4_.D 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1--------1-------------------0-------0--01-----1-------1--------------0----------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 27d58e5..614fcef 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 9/14/16; -TIME = 23:54:30; +DATE = 10/6/16; +TIME = 21:35:00; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -141,15 +141,15 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF +AS_030 = OUTPUT,82,7,-; AS_000 = OUTPUT,42,4,-; RW_000 = BIDIR,80,7,-; +RW = BIDIR,71,6,-; UDS_000 = OUTPUT,32,3,-; LDS_000 = OUTPUT,31,3,-; +SIZE_1_ = BIDIR,79,7,-; +SIZE_0_ = BIDIR,70,6,-; A_0_ = BIDIR,69,6,-; -RW = BIDIR,71,6,-; -AS_030 = OUTPUT,82,7,-; -SIZE_1_ = OUTPUT,79,7,-; -SIZE_0_ = OUTPUT,70,6,-; BERR = OUTPUT,41,4,-; AHIGH_24_ = OUTPUT,19,2,-; AHIGH_25_ = OUTPUT,18,2,-; @@ -164,13 +164,13 @@ IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; BGACK_030 = OUTPUT,83,7,-; VMA = OUTPUT,35,3,-; -DSACK1 = OUTPUT,81,7,-; E = OUTPUT,66,6,-; AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; BG_000 = OUTPUT,29,3,-; DS_030 = OUTPUT,98,0,-; AVEC = OUTPUT,92,0,-; +DSACK1 = OUTPUT,81,7,-; FPU_CS = OUTPUT,78,7,-; CLK_DIV_OUT = OUTPUT,65,6,-; CIIN = OUTPUT,47,4,-; @@ -180,56 +180,57 @@ CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; RN_BGACK_030 = NODE,-1,7,-; inst_RESET_OUT = NODE,*,0,-; -CLK_000_D_1_ = NODE,*,7,-; CLK_000_D_0_ = NODE,*,1,-; -SM_AMIGA_6_ = NODE,*,1,-; -cpu_est_0_ = NODE,*,1,-; -inst_AS_030_D0 = NODE,*,4,-; -inst_AS_000_DMA = NODE,*,2,-; -inst_AS_030_000_SYNC = NODE,*,2,-; -CYCLE_DMA_1_ = NODE,*,6,-; +CLK_000_D_1_ = NODE,*,7,-; +SM_AMIGA_6_ = NODE,*,5,-; +CLK_000_D_3_ = NODE,*,3,-; +inst_BGACK_030_INT_D = NODE,*,7,-; +SM_AMIGA_0_ = NODE,*,0,-; cpu_est_1_ = NODE,*,6,-; cpu_est_3_ = NODE,*,3,-; -SM_AMIGA_i_7_ = NODE,*,1,-; -SM_AMIGA_4_ = NODE,*,6,-; -SIZE_DMA_0_ = NODE,*,2,-; -CYCLE_DMA_0_ = NODE,*,6,-; -inst_BGACK_030_INT_D = NODE,*,4,-; -cpu_est_2_ = NODE,*,6,-; -inst_DS_000_DMA = NODE,*,5,-; -inst_CLK_030_H = NODE,*,2,-; +cpu_est_0_ = NODE,*,6,-; +CLK_000_D_2_ = NODE,*,7,-; +inst_AS_030_D0 = NODE,*,7,-; +cpu_est_2_ = NODE,*,3,-; +inst_DS_000_DMA = NODE,*,6,-; +inst_AS_000_DMA = NODE,*,6,-; +inst_AS_030_000_SYNC = NODE,*,5,-; +RST_DLY_0_ = NODE,*,2,-; +SM_AMIGA_1_ = NODE,*,2,-; RN_VMA = NODE,-1,3,-; +SM_AMIGA_i_7_ = NODE,*,5,-; SM_AMIGA_5_ = NODE,*,3,-; -SM_AMIGA_0_ = NODE,*,7,-; -SM_AMIGA_1_ = NODE,*,0,-; -inst_LDS_000_INT = NODE,*,5,-; -SIZE_DMA_1_ = NODE,*,6,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,5,-; -inst_CLK_OUT_PRE_25 = NODE,*,6,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,5,-; -inst_AS_000_INT = NODE,*,3,-; -inst_CLK_OUT_PRE_D = NODE,*,7,-; -inst_CLK_OUT_PRE_50 = NODE,*,0,-; -inst_VPA_D = NODE,*,5,-; +SM_AMIGA_4_ = NODE,*,2,-; +inst_LDS_000_INT = NODE,*,1,-; +inst_DS_000_ENABLE = NODE,*,5,-; +CYCLE_DMA_0_ = NODE,*,0,-; +inst_AS_000_INT = NODE,*,5,-; +inst_DSACK1_INT = NODE,*,0,-; +RST_DLY_2_ = NODE,*,0,-; +RST_DLY_1_ = NODE,*,0,-; +inst_UDS_000_INT = NODE,*,1,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,0,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,0,-; +inst_CLK_OUT_PRE_D = NODE,*,4,-; +inst_VPA_D = NODE,*,0,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; -SM_AMIGA_2_ = NODE,*,0,-; -SM_AMIGA_3_ = NODE,*,0,-; +inst_CLK_030_H = NODE,*,6,-; +SM_AMIGA_2_ = NODE,*,2,-; +SM_AMIGA_3_ = NODE,*,2,-; RN_RW_000 = NODE,-1,7,-; -RST_DLY_0_ = NODE,*,0,-; +CYCLE_DMA_1_ = NODE,*,6,-; RN_A_0_ = NODE,-1,6,-; -inst_DS_000_ENABLE = NODE,*,3,-; +RN_SIZE_0_ = NODE,-1,6,-; +RN_SIZE_1_ = NODE,-1,7,-; RN_RW = NODE,-1,6,-; -RN_DSACK1 = NODE,-1,7,-; RN_BG_000 = NODE,-1,3,-; CIIN_0 = NODE,*,4,-; -RST_DLY_2_ = NODE,*,0,-; -RST_DLY_1_ = NODE,*,0,-; -inst_UDS_000_INT = NODE,*,3,-; -CLK_000_D_2_ = NODE,*,4,-; -IPL_D0_2_ = NODE,*,2,-; -IPL_D0_1_ = NODE,*,3,-; -IPL_D0_0_ = NODE,*,2,-; -inst_DTACK_D0 = NODE,*,7,-; +CLK_000_D_4_ = NODE,*,3,-; +IPL_D0_2_ = NODE,*,6,-; +IPL_D0_1_ = NODE,*,1,-; +IPL_D0_0_ = NODE,*,3,-; +inst_CLK_OUT_PRE_50 = NODE,*,4,-; +inst_DTACK_D0 = NODE,*,2,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 09330e5..e7b9250 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 9/14/16; -TIME = 23:54:30; +DATE = 10/6/16; +TIME = 21:35:00; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -141,7 +141,6 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; -SIZE_1_ = BIDIR,79, H,-; AHIGH_31_ = BIDIR,4, B,-; A_DECODE_23_ = INPUT,85, H,-; IPL_2_ = INPUT,68, G,-; @@ -157,30 +156,30 @@ BG_030 = INPUT,21, C,-; BGACK_000 = INPUT,28, D,-; CLK_030 = INPUT,64,-,-; CLK_000 = INPUT,11,-,-; -SIZE_0_ = BIDIR,70, G,-; -CLK_OSZI = INPUT,61,-,-; AHIGH_30_ = BIDIR,5, B,-; -CLK_DIV_OUT = OUTPUT,65, G,-; +CLK_OSZI = INPUT,61,-,-; AHIGH_29_ = BIDIR,6, B,-; +CLK_DIV_OUT = OUTPUT,65, G,-; AHIGH_28_ = BIDIR,15, C,-; -FPU_CS = OUTPUT,78, H,-; AHIGH_27_ = BIDIR,16, C,-; -FPU_SENSE = INPUT,91, A,-; +FPU_CS = OUTPUT,78, H,-; AHIGH_26_ = BIDIR,17, C,-; +FPU_SENSE = INPUT,91, A,-; AHIGH_25_ = BIDIR,18, C,-; -DTACK = INPUT,30, D,-; +DSACK1 = OUTPUT,81, H,-; AHIGH_24_ = BIDIR,19, C,-; -AVEC = OUTPUT,92, A,-; +DTACK = INPUT,30, D,-; A_DECODE_22_ = INPUT,84, H,-; -E = OUTPUT,66, G,-; +AVEC = OUTPUT,92, A,-; A_DECODE_21_ = INPUT,94, A,-; -VPA = INPUT,36,-,-; +E = OUTPUT,66, G,-; A_DECODE_20_ = INPUT,93, A,-; +VPA = INPUT,36,-,-; A_DECODE_19_ = INPUT,97, A,-; -RST = INPUT,86,-,-; A_DECODE_18_ = INPUT,95, A,-; -RESET = OUTPUT,3, B,-; +RST = INPUT,86,-,-; A_DECODE_17_ = INPUT,59, F,-; +RESET = OUTPUT,3, B,-; A_DECODE_16_ = INPUT,96, A,-; AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; @@ -191,58 +190,59 @@ IPL_1_ = INPUT,56, F,-; IPL_0_ = INPUT,67, G,-; FC_0_ = INPUT,57, F,-; A_1_ = INPUT,60, F,-; +SIZE_1_ = BIDIR,79, H,-; IPL_030_2_ = OUTPUT,9, B,-; RW_000 = BIDIR,80, H,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; +SIZE_0_ = BIDIR,70, G,-; CLK_EXP = OUTPUT,10, B,-; -DSACK1 = OUTPUT,81, H,-; VMA = OUTPUT,35, D,-; RW = BIDIR,71, G,-; A_0_ = BIDIR,69, G,-; IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; -cpu_est_2_ = NODE,6, G,-; -cpu_est_3_ = NODE,9, D,-; -cpu_est_0_ = NODE,10, B,-; -cpu_est_1_ = NODE,9, G,-; -inst_AS_000_INT = NODE,2, D,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,12, F,-; -inst_AS_030_D0 = NODE,8, E,-; -inst_AS_030_000_SYNC = NODE,13, C,-; -inst_BGACK_030_INT_D = NODE,5, E,-; -inst_AS_000_DMA = NODE,9, C,-; -inst_DS_000_DMA = NODE,0, F,-; -CYCLE_DMA_0_ = NODE,2, G,-; -CYCLE_DMA_1_ = NODE,5, G,-; -SIZE_DMA_0_ = NODE,2, C,-; -SIZE_DMA_1_ = NODE,10, G,-; -inst_VPA_D = NODE,1, F,-; -CLK_000_D_1_ = NODE,5, H,-; -inst_DTACK_D0 = NODE,6, H,-; +cpu_est_3_ = NODE,13, D,-; +cpu_est_0_ = NODE,9, G,-; +cpu_est_1_ = NODE,5, G,-; +cpu_est_2_ = NODE,2, D,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,6, A,-; +inst_AS_030_D0 = NODE,6, H,-; +inst_AS_030_000_SYNC = NODE,4, F,-; +inst_BGACK_030_INT_D = NODE,13, H,-; +inst_AS_000_DMA = NODE,2, G,-; +inst_DS_000_DMA = NODE,13, G,-; +CYCLE_DMA_0_ = NODE,1, A,-; +CYCLE_DMA_1_ = NODE,10, G,-; +inst_VPA_D = NODE,10, A,-; +CLK_000_D_2_ = NODE,2, H,-; +CLK_000_D_3_ = NODE,9, D,-; +inst_DTACK_D0 = NODE,14, C,-; inst_RESET_OUT = NODE,8, A,-; +CLK_000_D_1_ = NODE,5, H,-; CLK_000_D_0_ = NODE,13, B,-; -inst_CLK_OUT_PRE_50 = NODE,1, A,-; -inst_CLK_OUT_PRE_25 = NODE,14, G,-; -inst_CLK_OUT_PRE_D = NODE,2, H,-; -IPL_D0_0_ = NODE,14, C,-; -IPL_D0_1_ = NODE,14, D,-; -IPL_D0_2_ = NODE,10, C,-; -CLK_000_D_2_ = NODE,13, E,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,8, F,-; -inst_LDS_000_INT = NODE,4, F,-; -inst_DS_000_ENABLE = NODE,6, D,-; -inst_UDS_000_INT = NODE,10, D,-; -SM_AMIGA_6_ = NODE,6, B,-; -SM_AMIGA_4_ = NODE,13, G,-; -SM_AMIGA_1_ = NODE,12, A,-; -SM_AMIGA_0_ = NODE,13, H,-; -RST_DLY_0_ = NODE,13, A,-; -RST_DLY_1_ = NODE,6, A,-; -RST_DLY_2_ = NODE,2, A,-; -inst_CLK_030_H = NODE,6, C,-; -SM_AMIGA_5_ = NODE,13, D,-; -SM_AMIGA_3_ = NODE,9, A,-; -SM_AMIGA_2_ = NODE,5, A,-; -SM_AMIGA_i_7_ = NODE,14, B,-; -CIIN_0 = NODE,9, E,-; +inst_CLK_OUT_PRE_50 = NODE,9, E,-; +inst_CLK_OUT_PRE_D = NODE,8, E,-; +IPL_D0_0_ = NODE,14, D,-; +IPL_D0_1_ = NODE,14, B,-; +IPL_D0_2_ = NODE,14, G,-; +CLK_000_D_4_ = NODE,10, D,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,2, A,-; +SM_AMIGA_1_ = NODE,13, C,-; +inst_UDS_000_INT = NODE,10, B,-; +inst_DS_000_ENABLE = NODE,12, F,-; +inst_LDS_000_INT = NODE,6, B,-; +SM_AMIGA_6_ = NODE,0, F,-; +SM_AMIGA_4_ = NODE,2, C,-; +SM_AMIGA_0_ = NODE,12, A,-; +RST_DLY_0_ = NODE,9, C,-; +RST_DLY_1_ = NODE,13, A,-; +RST_DLY_2_ = NODE,9, A,-; +inst_CLK_030_H = NODE,6, G,-; +inst_DSACK1_INT = NODE,5, A,-; +inst_AS_000_INT = NODE,1, F,-; +SM_AMIGA_5_ = NODE,6, D,-; +SM_AMIGA_3_ = NODE,10, C,-; +SM_AMIGA_2_ = NODE,6, C,-; +SM_AMIGA_i_7_ = NODE,8, F,-; +CIIN_0 = NODE,5, E,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 5bb44c3..73e3601 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Wed Sep 14 23:54:26 2016 +Design '68030_tk' created Thu Oct 06 21:34:55 2016 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 7fcaecf..34fce03 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,303 +1,302 @@ -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ CLK_EXP AHIGH_28_ FPU_CS AHIGH_27_ FPU_SENSE AHIGH_26_ DSACK1 AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ VPA A_DECODE_20_ VMA A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ RW A_DECODE_16_ AMIGA_ADDR_ENABLE A_DECODE_15_ AMIGA_BUS_DATA_DIR A_DECODE_14_ AMIGA_BUS_ENABLE_LOW A_DECODE_13_ AMIGA_BUS_ENABLE_HIGH A_DECODE_12_ CIIN A_DECODE_11_ A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ -#$ NODES 602 N_130_i pos_clk_un6_bgack_000_0_n N_131_i DTACK_c_i CLK_030_H_i N_56_0 RW_000_i VPA_c_i a_i_1__n N_55_0 \ -# RESET_OUT_i N_6_i AS_030_i N_47_0 FPU_SENSE_i N_26_i inst_BGACK_030_INTreg sm_amiga_i_i_7__n N_34_0 vcc_n_n \ -# a_decode_i_16__n BG_030_c_i inst_VMA_INTreg AS_030_D0_i pos_clk_un6_bg_030_i_n gnd_n_n size_dma_i_0__n pos_clk_un9_bg_030_0_n un1_amiga_bus_enable_low size_dma_i_1__n \ -# N_25_i un6_as_030 a_decode_i_18__n N_35_0 un3_size a_decode_i_19__n N_24_i un4_size ahigh_i_30__n N_36_0 \ -# un1_LDS_000_INT ahigh_i_31__n N_17_i un1_UDS_000_INT ahigh_i_28__n N_43_0 un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_29__n N_4_i un1_DS_000_ENABLE_0_sqmuxa \ -# ahigh_i_26__n N_49_0 un4_as_000 ahigh_i_27__n N_3_i un10_ciin ahigh_i_24__n N_50_0 un21_fpu_cs ahigh_i_25__n \ -# N_215_i un21_berr N_210_i N_216_i un6_ds_030 N_211_i N_301_0 cpu_est_2_ N_212_i N_243_0 \ -# cpu_est_3_ N_266_i cpu_est_0_ un6_ds_030_i N_249_i cpu_est_1_ un4_as_000_i AMIGA_BUS_DATA_DIR_c_0 inst_AS_000_INT AS_000_INT_i \ -# N_268_i inst_AMIGA_BUS_ENABLE_DMA_LOW un6_as_030_i pos_clk_ds_000_dma_4_0_n inst_AS_030_D0 AS_030_c CLK_030_c_i inst_AS_030_000_SYNC N_236_0 inst_BGACK_030_INT_D \ -# AS_000_c un1_as_000_i inst_AS_000_DMA N_297_i inst_DS_000_DMA RW_000_c N_160_i CYCLE_DMA_0_ pos_clk_un21_bgack_030_int_i_0_i_n CYCLE_DMA_1_ \ -# N_100_i SIZE_DMA_0_ UDS_000_c N_186_0 SIZE_DMA_1_ N_183_0 inst_VPA_D LDS_000_c N_182_0 CLK_000_D_1_ \ -# N_181_0 inst_DTACK_D0 size_c_0__n N_228_i inst_RESET_OUT N_176_0 CLK_000_D_0_ size_c_1__n LDS_000_c_i inst_CLK_OUT_PRE_50 \ -# UDS_000_c_i inst_CLK_OUT_PRE_25 ahigh_c_24__n N_173_i inst_CLK_OUT_PRE_D N_304_i IPL_D0_0_ ahigh_c_25__n AS_030_000_SYNC_i IPL_D0_1_ \ -# N_157_i IPL_D0_2_ ahigh_c_26__n N_110_0 CLK_000_D_2_ RW_c_i pos_clk_un6_bg_030_n ahigh_c_27__n N_106_0 inst_AMIGA_BUS_ENABLE_DMA_HIGH \ -# N_284_i inst_DSACK1_INTreg ahigh_c_28__n pos_clk_ipl_n N_334_i inst_LDS_000_INT ahigh_c_29__n inst_DS_000_ENABLE N_278_i inst_UDS_000_INT \ -# ahigh_c_30__n N_279_i SM_AMIGA_6_ SM_AMIGA_4_ ahigh_c_31__n N_332_i SM_AMIGA_1_ N_237_0 SM_AMIGA_0_ un1_SM_AMIGA_0_sqmuxa_1_0 \ -# inst_RW_000_INT N_247_i inst_RW_000_DMA N_248_i RST_DLY_0_ RST_DLY_1_ N_246_i RST_DLY_2_ inst_A0_DMA pos_clk_a0_dma_3_n \ -# un10_ciin_i inst_CLK_030_H N_241_0 SM_AMIGA_5_ un1_DS_000_ENABLE_0_sqmuxa_i SM_AMIGA_3_ N_242_0 SM_AMIGA_2_ N_48_i N_227_i \ -# N_9 N_225_i N_224_i N_15 N_223_i N_16 N_22 N_218_i CLK_OUT_PRE_25_0 pos_clk_size_dma_6_0_1__n \ -# N_217_i pos_clk_size_dma_6_0_0__n N_213_i N_319_i N_300_0 N_15_i a_decode_c_16__n N_45_0 N_16_i a_decode_c_17__n \ -# N_44_0 N_22_i a_decode_c_18__n N_38_0 pos_clk_un21_bgack_030_int_i_0_i_1_n a_decode_c_19__n pos_clk_un21_bgack_030_int_i_0_i_2_n N_238_i_1 a_decode_c_20__n N_238_i_2 \ -# N_239_i_1 a_decode_c_21__n N_239_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_22__n un10_ciin_1 un10_ciin_2 a_decode_c_23__n un10_ciin_3 un10_ciin_4 \ -# a_c_0__n un10_ciin_5 un10_ciin_6 SM_AMIGA_i_7_ a_c_1__n un10_ciin_7 pos_clk_size_dma_6_0__n un10_ciin_8 pos_clk_size_dma_6_1__n nEXP_SPACE_c \ -# un10_ciin_9 G_107 un10_ciin_10 G_108 BERR_c un10_ciin_11 G_109 N_357_1 pos_clk_un21_bgack_030_int_i_0_n BG_030_c \ -# N_357_2 N_237 N_357_3 N_241 BG_000DFFreg N_357_4 N_242 N_304_i_1 un21_fpu_cs_1 N_283 \ -# BGACK_000_c un21_berr_1_0 N_294 N_266_1 N_300 CLK_030_c N_266_2 N_67_i_1 N_106 N_67_i_2 \ -# N_314_1 N_134 CLK_OSZI_c N_314_2 N_138 N_318_1 N_156 N_318_2 N_160 CLK_OUT_INTreg \ -# N_341_1 N_167 N_341_2 N_172 N_151_i_1 N_173 FPU_SENSE_c N_143_i_1 N_181 N_141_i_1 \ -# N_182 IPL_030DFF_0_reg N_237_0_1 N_183 N_240_i_1 N_191 IPL_030DFF_1_reg N_60_i_1 N_199 N_64_i_1 \ -# N_205 IPL_030DFF_2_reg N_155_i_1 N_209 N_147_i_1 N_319 ipl_c_0__n N_145_i_1 N_213 N_139_i_1 \ -# N_216 ipl_c_1__n pos_clk_un6_bg_030_1_n N_217 N_220_1 N_218 ipl_c_2__n N_216_1 N_220 N_205_1 \ -# N_223 N_199_1 N_224 DTACK_c pos_clk_ipl_1_n N_225 uds_000_int_0_un3_n N_227 uds_000_int_0_un1_n N_228 \ -# uds_000_int_0_un0_n N_246 VPA_c as_000_int_0_un3_n N_247 as_000_int_0_un1_n N_248 as_000_int_0_un0_n N_332 RST_c \ -# dsack1_int_0_un3_n N_278 dsack1_int_0_un1_n N_279 dsack1_int_0_un0_n N_334 RW_c vma_int_0_un3_n N_284 vma_int_0_un1_n \ -# N_343 fc_c_0__n vma_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_0_x2 lds_000_int_0_un3_n un21_berr_1 fc_c_1__n lds_000_int_0_un1_n N_357 lds_000_int_0_un0_n \ -# N_266 ipl_030_0_1__un3_n N_186 AMIGA_BUS_DATA_DIR_c ipl_030_0_1__un1_n pos_clk_un21_bgack_030_int_i_0_o2_2_x2 ipl_030_0_1__un0_n N_297 ipl_030_0_0__un3_n N_236 \ -# ipl_030_0_0__un1_n pos_clk_ds_000_dma_4_n ipl_030_0_0__un0_n N_268 UDS_000_INT_i cpu_est_0_3__un3_n N_249 un1_UDS_000_INT_0 cpu_est_0_3__un1_n N_243 \ -# LDS_000_INT_i cpu_est_0_3__un0_n N_215 un1_LDS_000_INT_0 cpu_est_0_2__un3_n N_130 N_23_i cpu_est_0_2__un1_n N_131 N_37_0 \ -# cpu_est_0_2__un0_n N_3 N_21_i cpu_est_0_1__un3_n N_4 N_39_0 cpu_est_0_1__un1_n N_17 N_20_i cpu_est_0_1__un0_n \ -# N_24 N_40_0 ipl_030_0_2__un3_n N_25 N_19_i ipl_030_0_2__un1_n pos_clk_un9_bg_030_n N_41_0 ipl_030_0_2__un0_n N_6 \ -# N_14_i amiga_bus_enable_dma_low_0_un3_n pos_clk_un6_bgack_000_n N_46_0 amiga_bus_enable_dma_low_0_un1_n N_26 ipl_c_i_0__n amiga_bus_enable_dma_low_0_un0_n N_208 N_52_0 \ -# rw_000_dma_0_un3_n N_207 ipl_c_i_1__n rw_000_dma_0_un1_n N_349 N_53_0 rw_000_dma_0_un0_n N_314 ipl_c_i_2__n as_000_dma_0_un3_n \ -# N_318 N_54_0 as_000_dma_0_un1_n N_348 N_27_i as_000_dma_0_un0_n N_201 N_31_0 ds_000_dma_0_un3_n N_200 \ -# N_28_i ds_000_dma_0_un1_n N_203 N_32_0 ds_000_dma_0_un0_n N_204 N_29_i bgack_030_int_0_un3_n N_185 N_33_0 \ -# bgack_030_int_0_un1_n N_184 a_c_i_0__n bgack_030_int_0_un0_n N_180 size_c_i_1__n bg_000_0_un3_n N_179 pos_clk_un10_sm_amiga_i_n bg_000_0_un1_n \ -# N_178 N_256_0 bg_000_0_un0_n N_171 N_318_i amiga_bus_enable_dma_high_0_un3_n N_341 N_314_i amiga_bus_enable_dma_high_0_un1_n N_342 \ -# pos_clk_un9_clk_000_pe_0_n amiga_bus_enable_dma_high_0_un0_n N_169 N_219_i un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n N_154 N_220_i un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n N_165 cpu_est_2_0_1__n \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n N_162 N_221_i size_dma_0_0__un3_n N_299 N_348_i size_dma_0_0__un1_n N_153 cpu_est_2_0_2__n size_dma_0_0__un0_n \ -# N_142 N_222_i size_dma_0_1__un3_n N_298 N_196_i size_dma_0_1__un1_n N_80 N_226_i size_dma_0_1__un0_n N_232 \ -# ds_000_enable_0_un3_n N_233 N_231_i ds_000_enable_0_un1_n N_229 N_229_i ds_000_enable_0_un0_n N_231 N_302_i as_030_000_sync_0_un3_n \ -# N_226 N_233_i as_030_000_sync_0_un1_n N_221 N_232_i as_030_000_sync_0_un0_n N_222 rw_000_int_0_un3_n cpu_est_2_2__n N_80_0 \ -# rw_000_int_0_un1_n cpu_est_2_1__n N_343_i rw_000_int_0_un0_n N_219 N_214_0 a0_dma_0_un3_n pos_clk_un9_clk_000_pe_n N_166_i a0_dma_0_un1_n \ -# N_256 N_134_i a0_dma_0_un0_n N_29 N_298_i a_decode_15__n N_28 N_142_0 N_27 N_153_i \ -# a_decode_14__n N_14 N_154_0 N_19 N_156_i a_decode_13__n N_20 N_305_i N_21 N_299_i \ -# a_decode_12__n N_23 N_162_0 un1_amiga_bus_enable_low_i N_165_0 a_decode_11__n un21_fpu_cs_i N_169_i cpu_est_i_1__n VMA_INT_i \ -# a_decode_10__n rst_dly_i_2__n N_341_i rst_dly_i_1__n N_342_i a_decode_9__n cpu_est_i_0__n N_171_i cpu_est_i_2__n N_172_i \ -# a_decode_8__n sm_amiga_i_0__n N_178_0 sm_amiga_i_3__n N_179_0 a_decode_7__n sm_amiga_i_4__n N_180_0 sm_amiga_i_5__n N_184_0 \ -# a_decode_6__n rst_dly_i_0__n N_185_0 sm_amiga_i_2__n N_203_i a_decode_5__n sm_amiga_i_1__n N_204_i VPA_D_i N_205_i \ -# a_decode_4__n clk_000_d_i_1__n cpu_est_i_3__n N_200_i a_decode_3__n sm_amiga_i_6__n N_199_i clk_000_d_i_0__n N_201_i a_decode_2__n \ -# BGACK_030_INT_i AS_000_i AS_000_DMA_i N_208_i nEXP_SPACE_i N_207_i cycle_dma_i_0__n N_167_i DS_000_DMA_i N_138_i \ -# AMIGA_BUS_ENABLE_DMA_LOW_i N_349_i +#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 SIZE_0_ CLK_000 AHIGH_30_ CLK_OSZI AHIGH_29_ CLK_DIV_OUT AHIGH_28_ CLK_EXP AHIGH_27_ FPU_CS AHIGH_26_ FPU_SENSE AHIGH_25_ DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E A_DECODE_20_ VPA A_DECODE_19_ VMA A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ RW A_DECODE_15_ AMIGA_ADDR_ENABLE A_DECODE_14_ AMIGA_BUS_DATA_DIR A_DECODE_13_ AMIGA_BUS_ENABLE_LOW A_DECODE_12_ AMIGA_BUS_ENABLE_HIGH A_DECODE_11_ CIIN A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 601 nEXP_SPACE_i N_171_i CLK_030_H_i FPU_SENSE_i N_121_i AS_030_i N_255_0 AS_000_DMA_i un1_SM_AMIGA_0_sqmuxa_1_0 AS_000_i \ +# N_48_0 AS_000_INT_i N_125_i DSACK1_INT_i N_126_i inst_BGACK_030_INTreg clk_000_d_i_0__n vcc_n_n clk_000_d_i_3__n N_127_i \ +# un5_e clk_000_d_i_1__n N_128_i inst_VMA_INTreg cpu_est_i_2__n gnd_n_n cpu_est_i_3__n RW_c_i un1_amiga_bus_enable_low a_decode_i_16__n \ +# pos_clk_rw_000_int_5_0_n un7_as_030 a_decode_i_18__n N_129_i un1_UDS_000_INT a_decode_i_19__n un1_LDS_000_INT ahigh_i_30__n un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_31__n \ +# un10_ciin_i un1_DS_000_ENABLE_0_sqmuxa ahigh_i_28__n N_261_0 un10_ciin ahigh_i_29__n N_65_0 un21_fpu_cs ahigh_i_26__n N_134_i \ +# un21_berr ahigh_i_27__n N_153_i un6_ds_030 ahigh_i_24__n N_67_0 cpu_est_3_ ahigh_i_25__n un2_as_030_i cpu_est_0_ \ +# N_206_i N_263_i cpu_est_1_ N_207_i N_265_i cpu_est_2_ N_208_i AS_030_000_SYNC_i inst_AMIGA_BUS_ENABLE_DMA_LOW N_84_0 \ +# inst_AS_030_D0 clk_000_d_i_2__n inst_AS_030_000_SYNC N_81_i N_85_i inst_BGACK_030_INT_D un6_ds_030_i N_141_i inst_AS_000_DMA DS_000_DMA_i \ +# un1_DS_000_ENABLE_0_sqmuxa_i inst_DS_000_DMA N_147_i pos_clk_un21_bgack_030_int_i_0_i_n CYCLE_DMA_0_ N_145_i N_269_i CYCLE_DMA_1_ un7_as_030_i N_90_i \ +# inst_VPA_D RESET_OUT_i N_270_i CLK_000_D_2_ AS_030_c N_271_0 CLK_000_D_3_ N_96_0 inst_DTACK_D0 AS_000_c \ +# N_97_0 inst_RESET_OUT N_98_0 CLK_000_D_1_ RW_000_c N_282_i CLK_000_D_0_ N_284_i inst_CLK_OUT_PRE_50 pos_clk_un14_clk_000_ne_i_n \ +# inst_CLK_OUT_PRE_D UDS_000_c un5_e_0 IPL_D0_0_ N_285_i IPL_D0_1_ LDS_000_c N_291_i IPL_D0_2_ N_292_i \ +# CLK_000_D_4_ size_c_0__n N_192_i pos_clk_un6_bg_030_n N_17_i inst_AMIGA_BUS_ENABLE_DMA_HIGH size_c_1__n cpu_est_2_0_2__n pos_clk_ipl_n N_286_i \ +# SM_AMIGA_1_ ahigh_c_24__n N_288_i AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa cpu_est_2_0_1__n inst_UDS_000_INT ahigh_c_25__n N_289_i inst_DS_000_ENABLE N_290_i \ +# inst_LDS_000_INT ahigh_c_26__n pos_clk_un9_clk_000_pe_0_n SM_AMIGA_6_ N_280_i SM_AMIGA_4_ ahigh_c_27__n pos_clk_un10_sm_amiga_i_n SM_AMIGA_0_ a_c_i_0__n \ +# SIZE_DMA_0_ ahigh_c_28__n size_c_i_1__n SIZE_DMA_1_ N_27_i inst_RW_000_INT ahigh_c_29__n N_30_0 inst_RW_000_DMA N_26_i \ +# RST_DLY_0_ ahigh_c_30__n N_29_0 RST_DLY_1_ N_25_i RST_DLY_2_ ahigh_c_31__n N_28_0 inst_A0_DMA ipl_c_i_2__n \ +# pos_clk_un9_clk_000_pe_n N_51_0 inst_CLK_030_H ipl_c_i_1__n pos_clk_rw_000_int_5_n N_50_0 inst_DSACK1_INT ipl_c_i_0__n inst_AS_000_INT N_49_0 \ +# SM_AMIGA_5_ N_4_i SM_AMIGA_3_ N_44_0 SM_AMIGA_2_ N_14_i N_4 N_41_0 N_15_i N_40_0 \ +# N_9 N_16_i N_39_0 N_18_i N_37_0 N_14 N_21_i N_15 N_34_0 N_16 \ +# N_23_i N_18 N_32_0 N_21 LDS_000_INT_i N_23 un1_LDS_000_INT_0 N_25 UDS_000_INT_i N_26 \ +# un1_UDS_000_INT_0 N_27 N_96_0_1 N_96_0_2 N_96_0_3 pos_clk_un21_bgack_030_int_i_0_i_1_n N_84_0_1 a_decode_c_16__n N_84_0_2 N_240_0_1 \ +# a_decode_c_17__n pos_clk_un10_sm_amiga_i_1_n N_289_1 a_decode_c_18__n N_289_2 N_290_1 a_decode_c_19__n N_290_2 pos_clk_un14_clk_000_ne_1_n a_decode_c_20__n \ +# pos_clk_un14_clk_000_ne_2_n N_153_1 a_decode_c_21__n N_153_2 N_153_3 a_decode_c_22__n N_153_4 N_153_5 a_decode_c_23__n un10_ciin_1 \ +# un10_ciin_2 a_c_0__n un10_ciin_3 un10_ciin_4 a_c_1__n un10_ciin_5 un10_ciin_6 SM_AMIGA_i_7_ nEXP_SPACE_c un10_ciin_7 \ +# cpu_est_2_1__n un10_ciin_8 cpu_est_2_2__n BERR_c un10_ciin_9 G_107 un10_ciin_10 G_108 BG_030_c un10_ciin_11 \ +# G_109 N_260_i_1 pos_clk_un21_bgack_030_int_i_0_n BG_000DFFreg N_260_i_2 N_81 N_233_i_1 N_94 N_233_i_2 N_254 \ +# BGACK_000_c N_232_i_1 N_255 N_232_i_2 N_261 CLK_030_c N_247_1 N_65 N_77_1 N_67 \ +# N_83_1 N_269 N_88_1 N_108 CLK_OSZI_c N_142_i_1 N_135 N_146_i_1 N_136 N_234_i_1 \ +# N_145 CLK_OUT_INTreg pos_clk_un6_bg_030_1_n N_278 N_124_1 N_147 un21_berr_1 N_58 FPU_SENSE_c un21_fpu_cs_1 \ +# N_110 N_140_i_1 N_239 IPL_030DFF_0_reg N_154_i_1 N_90 N_152_i_1 N_265 IPL_030DFF_1_reg N_150_i_1 \ +# pos_clk_CYCLE_DMA_5_1_i_x2 N_148_i_1 pos_clk_un21_bgack_030_int_i_0_x2 IPL_030DFF_2_reg N_144_i_1 pos_clk_un19_bgack_030_int_n N_255_0_1 N_280 ipl_c_0__n N_258_i_1 \ +# N_263 N_259_i_1 N_247 ipl_c_1__n N_282_1 N_77 N_284_1 N_289 ipl_c_2__n N_288_1 \ +# N_291 un5_e_0_1 N_290 N_192_i_1 N_286 DTACK_c pos_clk_ipl_1_n N_288 bg_000_0_un3_n N_285 \ +# bg_000_0_un1_n N_17 bg_000_0_un0_n N_292 VPA_c amiga_bus_enable_dma_low_0_un3_n pos_clk_un14_clk_000_ne_n amiga_bus_enable_dma_low_0_un1_n N_282 amiga_bus_enable_dma_low_0_un0_n \ +# N_284 RST_c a0_dma_0_un3_n N_98 a0_dma_0_un1_n N_97 a0_dma_0_un0_n N_84 RW_c rw_000_dma_0_un3_n \ +# N_96 rw_000_dma_0_un1_n N_271 fc_c_0__n rw_000_dma_0_un0_n N_117 bgack_030_int_0_un3_n N_141 fc_c_1__n bgack_030_int_0_un1_n \ +# N_134 bgack_030_int_0_un0_n N_153 ds_000_dma_0_un3_n N_129 AMIGA_BUS_DATA_DIR_c ds_000_dma_0_un1_n N_127 ds_000_dma_0_un0_n N_128 \ +# size_dma_0_1__un3_n N_125 size_dma_0_1__un1_n N_126 size_dma_0_1__un0_n N_124 BG_030_c_i size_dma_0_0__un3_n N_121 pos_clk_un6_bg_030_i_n \ +# size_dma_0_0__un1_n N_171 pos_clk_un9_bg_030_0_n size_dma_0_0__un0_n N_120 N_24_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_119 N_31_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n \ +# N_118 N_22_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_116 N_33_0 cpu_est_0_1__un3_n N_114 N_20_i cpu_est_0_1__un1_n N_115 \ +# N_35_0 cpu_est_0_1__un0_n N_243 N_19_i cpu_est_0_2__un3_n N_240 N_36_0 cpu_est_0_2__un1_n N_88 N_8_i \ +# cpu_est_0_2__un0_n N_89 N_42_0 cpu_est_0_3__un3_n N_82 N_3_i cpu_est_0_3__un1_n N_83 N_45_0 cpu_est_0_3__un0_n \ +# N_78 VPA_c_i ipl_030_0_0__un3_n N_79 N_52_0 ipl_030_0_0__un1_n N_91 DTACK_c_i ipl_030_0_0__un0_n N_244 \ +# N_53_0 ipl_030_0_1__un3_n N_62 ipl_030_0_1__un1_n N_64 N_249_i ipl_030_0_1__un0_n N_59 N_248_i ipl_030_0_2__un3_n \ +# N_61 N_247_i ipl_030_0_2__un1_n N_163 ipl_030_0_2__un0_n N_245 N_77_i uds_000_int_0_un3_n N_242 N_251_i \ +# uds_000_int_0_un1_n N_246 N_76_i uds_000_int_0_un0_n N_248 amiga_bus_enable_dma_high_0_un3_n N_236 N_131_i amiga_bus_enable_dma_high_0_un1_n N_249 \ +# N_130_i amiga_bus_enable_dma_high_0_un0_n N_92 N_264_i as_000_dma_0_un3_n N_251 N_170_i as_000_dma_0_un1_n N_76 pos_clk_un6_bgack_000_0_n \ +# as_000_dma_0_un0_n N_80 pos_clk_rw_000_dma_3_0_n ds_000_enable_0_un3_n pos_clk_a0_dma_3_n N_123_i ds_000_enable_0_un1_n SIZE_DMA_3_sqmuxa N_124_i ds_000_enable_0_un0_n \ +# N_87 AMIGA_BUS_DATA_DIR_c_0 lds_000_int_0_un3_n pos_clk_size_dma_6_1__n N_122_i lds_000_int_0_un1_n pos_clk_size_dma_6_0__n pos_clk_ds_000_dma_4_0_n lds_000_int_0_un0_n N_170 \ +# N_242_i as_030_000_sync_0_un3_n N_122 N_239_i as_030_000_sync_0_un1_n N_123 N_87_i as_030_000_sync_0_un0_n N_130 N_236_0 \ +# rw_000_int_0_un3_n pos_clk_ds_000_dma_4_n N_246_i rw_000_int_0_un1_n pos_clk_rw_000_dma_3_n pos_clk_size_dma_6_0_0__n rw_000_int_0_un0_n pos_clk_un6_bgack_000_n N_245_i vma_int_0_un3_n \ +# N_131 pos_clk_size_dma_6_0_1__n vma_int_0_un1_n N_3 N_91_i vma_int_0_un0_n N_8 N_210_i a_decode_15__n N_19 \ +# pos_clk_un19_bgack_030_int_i_n N_20 N_163_0 a_decode_14__n N_22 N_59_i N_24 N_61_i a_decode_13__n pos_clk_un9_bg_030_n \ +# un1_amiga_bus_enable_low_i N_62_i a_decode_12__n un21_fpu_cs_i N_64_i BGACK_030_INT_i a_decode_11__n AMIGA_BUS_ENABLE_DMA_LOW_i N_244_i N_80_i \ +# a_decode_10__n cycle_dma_i_0__n N_78_i_0 RW_000_i N_79_i a_decode_9__n rst_dly_i_0__n rst_dly_i_1__n N_82_i a_decode_8__n \ +# rst_dly_i_2__n N_83_i LDS_000_i N_55_0 a_decode_7__n UDS_000_i N_88_i sm_amiga_i_2__n N_89_i a_decode_6__n \ +# N_58_i N_240_0 sm_amiga_i_3__n N_243_0 a_decode_5__n cpu_est_i_1__n CLK_030_c_i cpu_est_i_0__n N_254_0 a_decode_4__n \ +# sm_amiga_i_1__n N_114_i N_110_i N_115_i a_decode_3__n a_i_1__n VMA_INT_i N_116_i a_decode_2__n VPA_D_i \ +# N_117_i DTACK_D0_i AS_030_D0_i N_118_i sm_amiga_i_0__n sm_amiga_i_i_7__n N_119_i sm_amiga_i_6__n sm_amiga_i_5__n N_120_i \ +# sm_amiga_i_4__n .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ A_DECODE_17_.BLIF A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ - FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_130_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF N_131_i.BLIF DTACK_c_i.BLIF CLK_030_H_i.BLIF N_56_0.BLIF RW_000_i.BLIF \ - VPA_c_i.BLIF a_i_1__n.BLIF N_55_0.BLIF RESET_OUT_i.BLIF N_6_i.BLIF AS_030_i.BLIF N_47_0.BLIF FPU_SENSE_i.BLIF N_26_i.BLIF \ - inst_BGACK_030_INTreg.BLIF sm_amiga_i_i_7__n.BLIF N_34_0.BLIF vcc_n_n.BLIF a_decode_i_16__n.BLIF BG_030_c_i.BLIF inst_VMA_INTreg.BLIF AS_030_D0_i.BLIF pos_clk_un6_bg_030_i_n.BLIF \ - gnd_n_n.BLIF size_dma_i_0__n.BLIF pos_clk_un9_bg_030_0_n.BLIF un1_amiga_bus_enable_low.BLIF size_dma_i_1__n.BLIF N_25_i.BLIF un6_as_030.BLIF a_decode_i_18__n.BLIF N_35_0.BLIF \ - un3_size.BLIF a_decode_i_19__n.BLIF N_24_i.BLIF un4_size.BLIF ahigh_i_30__n.BLIF N_36_0.BLIF un1_LDS_000_INT.BLIF ahigh_i_31__n.BLIF N_17_i.BLIF \ - un1_UDS_000_INT.BLIF ahigh_i_28__n.BLIF N_43_0.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_29__n.BLIF N_4_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF ahigh_i_26__n.BLIF N_49_0.BLIF \ - un4_as_000.BLIF ahigh_i_27__n.BLIF N_3_i.BLIF un10_ciin.BLIF ahigh_i_24__n.BLIF N_50_0.BLIF un21_fpu_cs.BLIF ahigh_i_25__n.BLIF N_215_i.BLIF \ - un21_berr.BLIF N_210_i.BLIF N_216_i.BLIF un6_ds_030.BLIF N_211_i.BLIF N_301_0.BLIF cpu_est_2_.BLIF N_212_i.BLIF N_243_0.BLIF \ - cpu_est_3_.BLIF N_266_i.BLIF cpu_est_0_.BLIF un6_ds_030_i.BLIF N_249_i.BLIF cpu_est_1_.BLIF un4_as_000_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF inst_AS_000_INT.BLIF \ - AS_000_INT_i.BLIF N_268_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un6_as_030_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF inst_AS_030_D0.BLIF AS_030_c.BLIF CLK_030_c_i.BLIF inst_AS_030_000_SYNC.BLIF \ - N_236_0.BLIF inst_BGACK_030_INT_D.BLIF AS_000_c.BLIF un1_as_000_i.BLIF inst_AS_000_DMA.BLIF N_297_i.BLIF inst_DS_000_DMA.BLIF RW_000_c.BLIF N_160_i.BLIF \ - CYCLE_DMA_0_.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF CYCLE_DMA_1_.BLIF N_100_i.BLIF SIZE_DMA_0_.BLIF UDS_000_c.BLIF N_186_0.BLIF SIZE_DMA_1_.BLIF N_183_0.BLIF \ - inst_VPA_D.BLIF LDS_000_c.BLIF N_182_0.BLIF CLK_000_D_1_.BLIF N_181_0.BLIF inst_DTACK_D0.BLIF size_c_0__n.BLIF N_228_i.BLIF inst_RESET_OUT.BLIF \ - N_176_0.BLIF CLK_000_D_0_.BLIF size_c_1__n.BLIF LDS_000_c_i.BLIF inst_CLK_OUT_PRE_50.BLIF UDS_000_c_i.BLIF inst_CLK_OUT_PRE_25.BLIF ahigh_c_24__n.BLIF N_173_i.BLIF \ - inst_CLK_OUT_PRE_D.BLIF N_304_i.BLIF IPL_D0_0_.BLIF ahigh_c_25__n.BLIF AS_030_000_SYNC_i.BLIF IPL_D0_1_.BLIF N_157_i.BLIF IPL_D0_2_.BLIF ahigh_c_26__n.BLIF \ - N_110_0.BLIF CLK_000_D_2_.BLIF RW_c_i.BLIF pos_clk_un6_bg_030_n.BLIF ahigh_c_27__n.BLIF N_106_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_284_i.BLIF inst_DSACK1_INTreg.BLIF \ - ahigh_c_28__n.BLIF pos_clk_ipl_n.BLIF N_334_i.BLIF inst_LDS_000_INT.BLIF ahigh_c_29__n.BLIF inst_DS_000_ENABLE.BLIF N_278_i.BLIF inst_UDS_000_INT.BLIF ahigh_c_30__n.BLIF \ - N_279_i.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF ahigh_c_31__n.BLIF N_332_i.BLIF SM_AMIGA_1_.BLIF N_237_0.BLIF SM_AMIGA_0_.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF \ - inst_RW_000_INT.BLIF N_247_i.BLIF inst_RW_000_DMA.BLIF N_248_i.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_246_i.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF \ - pos_clk_a0_dma_3_n.BLIF un10_ciin_i.BLIF inst_CLK_030_H.BLIF N_241_0.BLIF SM_AMIGA_5_.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_3_.BLIF N_242_0.BLIF SM_AMIGA_2_.BLIF \ - N_48_i.BLIF N_227_i.BLIF N_9.BLIF N_225_i.BLIF N_224_i.BLIF N_15.BLIF N_223_i.BLIF N_16.BLIF N_22.BLIF \ - N_218_i.BLIF CLK_OUT_PRE_25_0.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_217_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF N_213_i.BLIF N_319_i.BLIF N_300_0.BLIF N_15_i.BLIF \ - a_decode_c_16__n.BLIF N_45_0.BLIF N_16_i.BLIF a_decode_c_17__n.BLIF N_44_0.BLIF N_22_i.BLIF a_decode_c_18__n.BLIF N_38_0.BLIF pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ - a_decode_c_19__n.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n.BLIF N_238_i_1.BLIF a_decode_c_20__n.BLIF N_238_i_2.BLIF N_239_i_1.BLIF a_decode_c_21__n.BLIF N_239_i_2.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF \ - a_decode_c_22__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF a_decode_c_23__n.BLIF un10_ciin_3.BLIF un10_ciin_4.BLIF a_c_0__n.BLIF un10_ciin_5.BLIF un10_ciin_6.BLIF \ - SM_AMIGA_i_7_.BLIF a_c_1__n.BLIF un10_ciin_7.BLIF pos_clk_size_dma_6_0__n.BLIF un10_ciin_8.BLIF pos_clk_size_dma_6_1__n.BLIF nEXP_SPACE_c.BLIF un10_ciin_9.BLIF G_107.BLIF \ - un10_ciin_10.BLIF G_108.BLIF BERR_c.BLIF un10_ciin_11.BLIF G_109.BLIF N_357_1.BLIF pos_clk_un21_bgack_030_int_i_0_n.BLIF BG_030_c.BLIF N_357_2.BLIF \ - N_237.BLIF N_357_3.BLIF N_241.BLIF BG_000DFFreg.BLIF N_357_4.BLIF N_242.BLIF N_304_i_1.BLIF un21_fpu_cs_1.BLIF N_283.BLIF \ - BGACK_000_c.BLIF un21_berr_1_0.BLIF N_294.BLIF N_266_1.BLIF N_300.BLIF CLK_030_c.BLIF N_266_2.BLIF N_67_i_1.BLIF N_106.BLIF \ - N_67_i_2.BLIF N_314_1.BLIF N_134.BLIF CLK_OSZI_c.BLIF N_314_2.BLIF N_138.BLIF N_318_1.BLIF N_156.BLIF N_318_2.BLIF \ - N_160.BLIF CLK_OUT_INTreg.BLIF N_341_1.BLIF N_167.BLIF N_341_2.BLIF N_172.BLIF N_151_i_1.BLIF N_173.BLIF FPU_SENSE_c.BLIF \ - N_143_i_1.BLIF N_181.BLIF N_141_i_1.BLIF N_182.BLIF IPL_030DFF_0_reg.BLIF N_237_0_1.BLIF N_183.BLIF N_240_i_1.BLIF N_191.BLIF \ - IPL_030DFF_1_reg.BLIF N_60_i_1.BLIF N_199.BLIF N_64_i_1.BLIF N_205.BLIF IPL_030DFF_2_reg.BLIF N_155_i_1.BLIF N_209.BLIF N_147_i_1.BLIF \ - N_319.BLIF ipl_c_0__n.BLIF N_145_i_1.BLIF N_213.BLIF N_139_i_1.BLIF N_216.BLIF ipl_c_1__n.BLIF pos_clk_un6_bg_030_1_n.BLIF N_217.BLIF \ - N_220_1.BLIF N_218.BLIF ipl_c_2__n.BLIF N_216_1.BLIF N_220.BLIF N_205_1.BLIF N_223.BLIF N_199_1.BLIF N_224.BLIF \ - DTACK_c.BLIF pos_clk_ipl_1_n.BLIF N_225.BLIF uds_000_int_0_un3_n.BLIF N_227.BLIF uds_000_int_0_un1_n.BLIF N_228.BLIF uds_000_int_0_un0_n.BLIF N_246.BLIF \ - VPA_c.BLIF as_000_int_0_un3_n.BLIF N_247.BLIF as_000_int_0_un1_n.BLIF N_248.BLIF as_000_int_0_un0_n.BLIF N_332.BLIF RST_c.BLIF dsack1_int_0_un3_n.BLIF \ - N_278.BLIF dsack1_int_0_un1_n.BLIF N_279.BLIF dsack1_int_0_un0_n.BLIF N_334.BLIF RW_c.BLIF vma_int_0_un3_n.BLIF N_284.BLIF vma_int_0_un1_n.BLIF \ - N_343.BLIF fc_c_0__n.BLIF vma_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF lds_000_int_0_un3_n.BLIF un21_berr_1.BLIF fc_c_1__n.BLIF lds_000_int_0_un1_n.BLIF N_357.BLIF \ - lds_000_int_0_un0_n.BLIF N_266.BLIF ipl_030_0_1__un3_n.BLIF N_186.BLIF AMIGA_BUS_DATA_DIR_c.BLIF ipl_030_0_1__un1_n.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.BLIF ipl_030_0_1__un0_n.BLIF N_297.BLIF \ - ipl_030_0_0__un3_n.BLIF N_236.BLIF ipl_030_0_0__un1_n.BLIF pos_clk_ds_000_dma_4_n.BLIF ipl_030_0_0__un0_n.BLIF N_268.BLIF UDS_000_INT_i.BLIF cpu_est_0_3__un3_n.BLIF N_249.BLIF \ - un1_UDS_000_INT_0.BLIF cpu_est_0_3__un1_n.BLIF N_243.BLIF LDS_000_INT_i.BLIF cpu_est_0_3__un0_n.BLIF N_215.BLIF un1_LDS_000_INT_0.BLIF cpu_est_0_2__un3_n.BLIF N_130.BLIF \ - N_23_i.BLIF cpu_est_0_2__un1_n.BLIF N_131.BLIF N_37_0.BLIF cpu_est_0_2__un0_n.BLIF N_3.BLIF N_21_i.BLIF cpu_est_0_1__un3_n.BLIF N_4.BLIF \ - N_39_0.BLIF cpu_est_0_1__un1_n.BLIF N_17.BLIF N_20_i.BLIF cpu_est_0_1__un0_n.BLIF N_24.BLIF N_40_0.BLIF ipl_030_0_2__un3_n.BLIF N_25.BLIF \ - N_19_i.BLIF ipl_030_0_2__un1_n.BLIF pos_clk_un9_bg_030_n.BLIF N_41_0.BLIF ipl_030_0_2__un0_n.BLIF N_6.BLIF N_14_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ - N_46_0.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_26.BLIF ipl_c_i_0__n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_208.BLIF N_52_0.BLIF rw_000_dma_0_un3_n.BLIF N_207.BLIF \ - ipl_c_i_1__n.BLIF rw_000_dma_0_un1_n.BLIF N_349.BLIF N_53_0.BLIF rw_000_dma_0_un0_n.BLIF N_314.BLIF ipl_c_i_2__n.BLIF as_000_dma_0_un3_n.BLIF N_318.BLIF \ - N_54_0.BLIF as_000_dma_0_un1_n.BLIF N_348.BLIF N_27_i.BLIF as_000_dma_0_un0_n.BLIF N_201.BLIF N_31_0.BLIF ds_000_dma_0_un3_n.BLIF N_200.BLIF \ - N_28_i.BLIF ds_000_dma_0_un1_n.BLIF N_203.BLIF N_32_0.BLIF ds_000_dma_0_un0_n.BLIF N_204.BLIF N_29_i.BLIF bgack_030_int_0_un3_n.BLIF N_185.BLIF \ - N_33_0.BLIF bgack_030_int_0_un1_n.BLIF N_184.BLIF a_c_i_0__n.BLIF bgack_030_int_0_un0_n.BLIF N_180.BLIF size_c_i_1__n.BLIF bg_000_0_un3_n.BLIF N_179.BLIF \ - pos_clk_un10_sm_amiga_i_n.BLIF bg_000_0_un1_n.BLIF N_178.BLIF N_256_0.BLIF bg_000_0_un0_n.BLIF N_171.BLIF N_318_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF N_341.BLIF \ - N_314_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF N_342.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_169.BLIF N_219_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n.BLIF N_154.BLIF \ - N_220_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n.BLIF N_165.BLIF cpu_est_2_0_1__n.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n.BLIF N_162.BLIF N_221_i.BLIF size_dma_0_0__un3_n.BLIF N_299.BLIF \ - N_348_i.BLIF size_dma_0_0__un1_n.BLIF N_153.BLIF cpu_est_2_0_2__n.BLIF size_dma_0_0__un0_n.BLIF N_142.BLIF N_222_i.BLIF size_dma_0_1__un3_n.BLIF N_298.BLIF \ - N_196_i.BLIF size_dma_0_1__un1_n.BLIF N_80.BLIF N_226_i.BLIF size_dma_0_1__un0_n.BLIF N_232.BLIF ds_000_enable_0_un3_n.BLIF N_233.BLIF N_231_i.BLIF \ - ds_000_enable_0_un1_n.BLIF N_229.BLIF N_229_i.BLIF ds_000_enable_0_un0_n.BLIF N_231.BLIF N_302_i.BLIF as_030_000_sync_0_un3_n.BLIF N_226.BLIF N_233_i.BLIF \ - as_030_000_sync_0_un1_n.BLIF N_221.BLIF N_232_i.BLIF as_030_000_sync_0_un0_n.BLIF N_222.BLIF rw_000_int_0_un3_n.BLIF cpu_est_2_2__n.BLIF N_80_0.BLIF rw_000_int_0_un1_n.BLIF \ - cpu_est_2_1__n.BLIF N_343_i.BLIF rw_000_int_0_un0_n.BLIF N_219.BLIF N_214_0.BLIF a0_dma_0_un3_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_166_i.BLIF a0_dma_0_un1_n.BLIF \ - N_256.BLIF N_134_i.BLIF a0_dma_0_un0_n.BLIF N_29.BLIF N_298_i.BLIF a_decode_15__n.BLIF N_28.BLIF N_142_0.BLIF N_27.BLIF \ - N_153_i.BLIF a_decode_14__n.BLIF N_14.BLIF N_154_0.BLIF N_19.BLIF N_156_i.BLIF a_decode_13__n.BLIF N_20.BLIF N_305_i.BLIF \ - N_21.BLIF N_299_i.BLIF a_decode_12__n.BLIF N_23.BLIF N_162_0.BLIF un1_amiga_bus_enable_low_i.BLIF N_165_0.BLIF a_decode_11__n.BLIF un21_fpu_cs_i.BLIF \ - N_169_i.BLIF cpu_est_i_1__n.BLIF VMA_INT_i.BLIF a_decode_10__n.BLIF rst_dly_i_2__n.BLIF N_341_i.BLIF rst_dly_i_1__n.BLIF N_342_i.BLIF a_decode_9__n.BLIF \ - cpu_est_i_0__n.BLIF N_171_i.BLIF cpu_est_i_2__n.BLIF N_172_i.BLIF a_decode_8__n.BLIF sm_amiga_i_0__n.BLIF N_178_0.BLIF sm_amiga_i_3__n.BLIF N_179_0.BLIF \ - a_decode_7__n.BLIF sm_amiga_i_4__n.BLIF N_180_0.BLIF sm_amiga_i_5__n.BLIF N_184_0.BLIF a_decode_6__n.BLIF rst_dly_i_0__n.BLIF N_185_0.BLIF sm_amiga_i_2__n.BLIF \ - N_203_i.BLIF a_decode_5__n.BLIF sm_amiga_i_1__n.BLIF N_204_i.BLIF VPA_D_i.BLIF N_205_i.BLIF a_decode_4__n.BLIF clk_000_d_i_1__n.BLIF cpu_est_i_3__n.BLIF \ - N_200_i.BLIF a_decode_3__n.BLIF sm_amiga_i_6__n.BLIF N_199_i.BLIF clk_000_d_i_0__n.BLIF N_201_i.BLIF a_decode_2__n.BLIF BGACK_030_INT_i.BLIF AS_000_i.BLIF \ - AS_000_DMA_i.BLIF N_208_i.BLIF nEXP_SPACE_i.BLIF N_207_i.BLIF cycle_dma_i_0__n.BLIF N_167_i.BLIF DS_000_DMA_i.BLIF N_138_i.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF \ - N_349_i.BLIF AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN \ - AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN \ - RW.PIN + FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF nEXP_SPACE_i.BLIF N_171_i.BLIF CLK_030_H_i.BLIF FPU_SENSE_i.BLIF N_121_i.BLIF AS_030_i.BLIF N_255_0.BLIF \ + AS_000_DMA_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF AS_000_i.BLIF N_48_0.BLIF AS_000_INT_i.BLIF N_125_i.BLIF DSACK1_INT_i.BLIF N_126_i.BLIF inst_BGACK_030_INTreg.BLIF \ + clk_000_d_i_0__n.BLIF vcc_n_n.BLIF clk_000_d_i_3__n.BLIF N_127_i.BLIF un5_e.BLIF clk_000_d_i_1__n.BLIF N_128_i.BLIF inst_VMA_INTreg.BLIF cpu_est_i_2__n.BLIF \ + gnd_n_n.BLIF cpu_est_i_3__n.BLIF RW_c_i.BLIF un1_amiga_bus_enable_low.BLIF a_decode_i_16__n.BLIF pos_clk_rw_000_int_5_0_n.BLIF un7_as_030.BLIF a_decode_i_18__n.BLIF N_129_i.BLIF \ + un1_UDS_000_INT.BLIF a_decode_i_19__n.BLIF un1_LDS_000_INT.BLIF ahigh_i_30__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_31__n.BLIF un10_ciin_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF ahigh_i_28__n.BLIF \ + N_261_0.BLIF un10_ciin.BLIF ahigh_i_29__n.BLIF N_65_0.BLIF un21_fpu_cs.BLIF ahigh_i_26__n.BLIF N_134_i.BLIF un21_berr.BLIF ahigh_i_27__n.BLIF \ + N_153_i.BLIF un6_ds_030.BLIF ahigh_i_24__n.BLIF N_67_0.BLIF cpu_est_3_.BLIF ahigh_i_25__n.BLIF un2_as_030_i.BLIF cpu_est_0_.BLIF N_206_i.BLIF \ + N_263_i.BLIF cpu_est_1_.BLIF N_207_i.BLIF N_265_i.BLIF cpu_est_2_.BLIF N_208_i.BLIF AS_030_000_SYNC_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_84_0.BLIF \ + inst_AS_030_D0.BLIF clk_000_d_i_2__n.BLIF inst_AS_030_000_SYNC.BLIF N_81_i.BLIF N_85_i.BLIF inst_BGACK_030_INT_D.BLIF un6_ds_030_i.BLIF N_141_i.BLIF inst_AS_000_DMA.BLIF \ + DS_000_DMA_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF inst_DS_000_DMA.BLIF N_147_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF CYCLE_DMA_0_.BLIF N_145_i.BLIF N_269_i.BLIF CYCLE_DMA_1_.BLIF \ + un7_as_030_i.BLIF N_90_i.BLIF inst_VPA_D.BLIF RESET_OUT_i.BLIF N_270_i.BLIF CLK_000_D_2_.BLIF AS_030_c.BLIF N_271_0.BLIF CLK_000_D_3_.BLIF \ + N_96_0.BLIF inst_DTACK_D0.BLIF AS_000_c.BLIF N_97_0.BLIF inst_RESET_OUT.BLIF N_98_0.BLIF CLK_000_D_1_.BLIF RW_000_c.BLIF N_282_i.BLIF \ + CLK_000_D_0_.BLIF N_284_i.BLIF inst_CLK_OUT_PRE_50.BLIF pos_clk_un14_clk_000_ne_i_n.BLIF inst_CLK_OUT_PRE_D.BLIF UDS_000_c.BLIF un5_e_0.BLIF IPL_D0_0_.BLIF N_285_i.BLIF \ + IPL_D0_1_.BLIF LDS_000_c.BLIF N_291_i.BLIF IPL_D0_2_.BLIF N_292_i.BLIF CLK_000_D_4_.BLIF size_c_0__n.BLIF N_192_i.BLIF pos_clk_un6_bg_030_n.BLIF \ + N_17_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF size_c_1__n.BLIF cpu_est_2_0_2__n.BLIF pos_clk_ipl_n.BLIF N_286_i.BLIF SM_AMIGA_1_.BLIF ahigh_c_24__n.BLIF N_288_i.BLIF \ + AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF cpu_est_2_0_1__n.BLIF inst_UDS_000_INT.BLIF ahigh_c_25__n.BLIF N_289_i.BLIF inst_DS_000_ENABLE.BLIF N_290_i.BLIF inst_LDS_000_INT.BLIF ahigh_c_26__n.BLIF \ + pos_clk_un9_clk_000_pe_0_n.BLIF SM_AMIGA_6_.BLIF N_280_i.BLIF SM_AMIGA_4_.BLIF ahigh_c_27__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_0_.BLIF a_c_i_0__n.BLIF SIZE_DMA_0_.BLIF \ + ahigh_c_28__n.BLIF size_c_i_1__n.BLIF SIZE_DMA_1_.BLIF N_27_i.BLIF inst_RW_000_INT.BLIF ahigh_c_29__n.BLIF N_30_0.BLIF inst_RW_000_DMA.BLIF N_26_i.BLIF \ + RST_DLY_0_.BLIF ahigh_c_30__n.BLIF N_29_0.BLIF RST_DLY_1_.BLIF N_25_i.BLIF RST_DLY_2_.BLIF ahigh_c_31__n.BLIF N_28_0.BLIF inst_A0_DMA.BLIF \ + ipl_c_i_2__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_51_0.BLIF inst_CLK_030_H.BLIF ipl_c_i_1__n.BLIF pos_clk_rw_000_int_5_n.BLIF N_50_0.BLIF inst_DSACK1_INT.BLIF ipl_c_i_0__n.BLIF \ + inst_AS_000_INT.BLIF N_49_0.BLIF SM_AMIGA_5_.BLIF N_4_i.BLIF SM_AMIGA_3_.BLIF N_44_0.BLIF SM_AMIGA_2_.BLIF N_14_i.BLIF N_4.BLIF \ + N_41_0.BLIF N_15_i.BLIF N_40_0.BLIF N_9.BLIF N_16_i.BLIF N_39_0.BLIF N_18_i.BLIF N_37_0.BLIF N_14.BLIF \ + N_21_i.BLIF N_15.BLIF N_34_0.BLIF N_16.BLIF N_23_i.BLIF N_18.BLIF N_32_0.BLIF N_21.BLIF LDS_000_INT_i.BLIF \ + N_23.BLIF un1_LDS_000_INT_0.BLIF N_25.BLIF UDS_000_INT_i.BLIF N_26.BLIF un1_UDS_000_INT_0.BLIF N_27.BLIF N_96_0_1.BLIF N_96_0_2.BLIF \ + N_96_0_3.BLIF pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF N_84_0_1.BLIF a_decode_c_16__n.BLIF N_84_0_2.BLIF N_240_0_1.BLIF a_decode_c_17__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_289_1.BLIF \ + a_decode_c_18__n.BLIF N_289_2.BLIF N_290_1.BLIF a_decode_c_19__n.BLIF N_290_2.BLIF pos_clk_un14_clk_000_ne_1_n.BLIF a_decode_c_20__n.BLIF pos_clk_un14_clk_000_ne_2_n.BLIF N_153_1.BLIF \ + a_decode_c_21__n.BLIF N_153_2.BLIF N_153_3.BLIF a_decode_c_22__n.BLIF N_153_4.BLIF N_153_5.BLIF a_decode_c_23__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF \ + a_c_0__n.BLIF un10_ciin_3.BLIF un10_ciin_4.BLIF a_c_1__n.BLIF un10_ciin_5.BLIF un10_ciin_6.BLIF SM_AMIGA_i_7_.BLIF nEXP_SPACE_c.BLIF un10_ciin_7.BLIF \ + cpu_est_2_1__n.BLIF un10_ciin_8.BLIF cpu_est_2_2__n.BLIF BERR_c.BLIF un10_ciin_9.BLIF G_107.BLIF un10_ciin_10.BLIF G_108.BLIF BG_030_c.BLIF \ + un10_ciin_11.BLIF G_109.BLIF N_260_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_n.BLIF BG_000DFFreg.BLIF N_260_i_2.BLIF N_81.BLIF N_233_i_1.BLIF N_94.BLIF \ + N_233_i_2.BLIF N_254.BLIF BGACK_000_c.BLIF N_232_i_1.BLIF N_255.BLIF N_232_i_2.BLIF N_261.BLIF CLK_030_c.BLIF N_247_1.BLIF \ + N_65.BLIF N_77_1.BLIF N_67.BLIF N_83_1.BLIF N_269.BLIF N_88_1.BLIF N_108.BLIF CLK_OSZI_c.BLIF N_142_i_1.BLIF \ + N_135.BLIF N_146_i_1.BLIF N_136.BLIF N_234_i_1.BLIF N_145.BLIF CLK_OUT_INTreg.BLIF pos_clk_un6_bg_030_1_n.BLIF N_278.BLIF N_124_1.BLIF \ + N_147.BLIF un21_berr_1.BLIF N_58.BLIF FPU_SENSE_c.BLIF un21_fpu_cs_1.BLIF N_110.BLIF N_140_i_1.BLIF N_239.BLIF IPL_030DFF_0_reg.BLIF \ + N_154_i_1.BLIF N_90.BLIF N_152_i_1.BLIF N_265.BLIF IPL_030DFF_1_reg.BLIF N_150_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_148_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_x2.BLIF \ + IPL_030DFF_2_reg.BLIF N_144_i_1.BLIF pos_clk_un19_bgack_030_int_n.BLIF N_255_0_1.BLIF N_280.BLIF ipl_c_0__n.BLIF N_258_i_1.BLIF N_263.BLIF N_259_i_1.BLIF \ + N_247.BLIF ipl_c_1__n.BLIF N_282_1.BLIF N_77.BLIF N_284_1.BLIF N_289.BLIF ipl_c_2__n.BLIF N_288_1.BLIF N_291.BLIF \ + un5_e_0_1.BLIF N_290.BLIF N_192_i_1.BLIF N_286.BLIF DTACK_c.BLIF pos_clk_ipl_1_n.BLIF N_288.BLIF bg_000_0_un3_n.BLIF N_285.BLIF \ + bg_000_0_un1_n.BLIF N_17.BLIF bg_000_0_un0_n.BLIF N_292.BLIF VPA_c.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_un14_clk_000_ne_n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_282.BLIF \ + amiga_bus_enable_dma_low_0_un0_n.BLIF N_284.BLIF RST_c.BLIF a0_dma_0_un3_n.BLIF N_98.BLIF a0_dma_0_un1_n.BLIF N_97.BLIF a0_dma_0_un0_n.BLIF N_84.BLIF \ + RW_c.BLIF rw_000_dma_0_un3_n.BLIF N_96.BLIF rw_000_dma_0_un1_n.BLIF N_271.BLIF fc_c_0__n.BLIF rw_000_dma_0_un0_n.BLIF N_117.BLIF bgack_030_int_0_un3_n.BLIF \ + N_141.BLIF fc_c_1__n.BLIF bgack_030_int_0_un1_n.BLIF N_134.BLIF bgack_030_int_0_un0_n.BLIF N_153.BLIF ds_000_dma_0_un3_n.BLIF N_129.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ + ds_000_dma_0_un1_n.BLIF N_127.BLIF ds_000_dma_0_un0_n.BLIF N_128.BLIF size_dma_0_1__un3_n.BLIF N_125.BLIF size_dma_0_1__un1_n.BLIF N_126.BLIF size_dma_0_1__un0_n.BLIF \ + N_124.BLIF BG_030_c_i.BLIF size_dma_0_0__un3_n.BLIF N_121.BLIF pos_clk_un6_bg_030_i_n.BLIF size_dma_0_0__un1_n.BLIF N_171.BLIF pos_clk_un9_bg_030_0_n.BLIF size_dma_0_0__un0_n.BLIF \ + N_120.BLIF N_24_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_119.BLIF N_31_0.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_118.BLIF N_22_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF \ + N_116.BLIF N_33_0.BLIF cpu_est_0_1__un3_n.BLIF N_114.BLIF N_20_i.BLIF cpu_est_0_1__un1_n.BLIF N_115.BLIF N_35_0.BLIF cpu_est_0_1__un0_n.BLIF \ + N_243.BLIF N_19_i.BLIF cpu_est_0_2__un3_n.BLIF N_240.BLIF N_36_0.BLIF cpu_est_0_2__un1_n.BLIF N_88.BLIF N_8_i.BLIF cpu_est_0_2__un0_n.BLIF \ + N_89.BLIF N_42_0.BLIF cpu_est_0_3__un3_n.BLIF N_82.BLIF N_3_i.BLIF cpu_est_0_3__un1_n.BLIF N_83.BLIF N_45_0.BLIF cpu_est_0_3__un0_n.BLIF \ + N_78.BLIF VPA_c_i.BLIF ipl_030_0_0__un3_n.BLIF N_79.BLIF N_52_0.BLIF ipl_030_0_0__un1_n.BLIF N_91.BLIF DTACK_c_i.BLIF ipl_030_0_0__un0_n.BLIF \ + N_244.BLIF N_53_0.BLIF ipl_030_0_1__un3_n.BLIF N_62.BLIF ipl_030_0_1__un1_n.BLIF N_64.BLIF N_249_i.BLIF ipl_030_0_1__un0_n.BLIF N_59.BLIF \ + N_248_i.BLIF ipl_030_0_2__un3_n.BLIF N_61.BLIF N_247_i.BLIF ipl_030_0_2__un1_n.BLIF N_163.BLIF ipl_030_0_2__un0_n.BLIF N_245.BLIF N_77_i.BLIF \ + uds_000_int_0_un3_n.BLIF N_242.BLIF N_251_i.BLIF uds_000_int_0_un1_n.BLIF N_246.BLIF N_76_i.BLIF uds_000_int_0_un0_n.BLIF N_248.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ + N_236.BLIF N_131_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF N_249.BLIF N_130_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_92.BLIF N_264_i.BLIF as_000_dma_0_un3_n.BLIF \ + N_251.BLIF N_170_i.BLIF as_000_dma_0_un1_n.BLIF N_76.BLIF pos_clk_un6_bgack_000_0_n.BLIF as_000_dma_0_un0_n.BLIF N_80.BLIF pos_clk_rw_000_dma_3_0_n.BLIF ds_000_enable_0_un3_n.BLIF \ + pos_clk_a0_dma_3_n.BLIF N_123_i.BLIF ds_000_enable_0_un1_n.BLIF SIZE_DMA_3_sqmuxa.BLIF N_124_i.BLIF ds_000_enable_0_un0_n.BLIF N_87.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF lds_000_int_0_un3_n.BLIF \ + pos_clk_size_dma_6_1__n.BLIF N_122_i.BLIF lds_000_int_0_un1_n.BLIF pos_clk_size_dma_6_0__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF lds_000_int_0_un0_n.BLIF N_170.BLIF N_242_i.BLIF as_030_000_sync_0_un3_n.BLIF \ + N_122.BLIF N_239_i.BLIF as_030_000_sync_0_un1_n.BLIF N_123.BLIF N_87_i.BLIF as_030_000_sync_0_un0_n.BLIF N_130.BLIF N_236_0.BLIF rw_000_int_0_un3_n.BLIF \ + pos_clk_ds_000_dma_4_n.BLIF N_246_i.BLIF rw_000_int_0_un1_n.BLIF pos_clk_rw_000_dma_3_n.BLIF pos_clk_size_dma_6_0_0__n.BLIF rw_000_int_0_un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_245_i.BLIF vma_int_0_un3_n.BLIF \ + N_131.BLIF pos_clk_size_dma_6_0_1__n.BLIF vma_int_0_un1_n.BLIF N_3.BLIF N_91_i.BLIF vma_int_0_un0_n.BLIF N_8.BLIF N_210_i.BLIF a_decode_15__n.BLIF \ + N_19.BLIF pos_clk_un19_bgack_030_int_i_n.BLIF N_20.BLIF N_163_0.BLIF a_decode_14__n.BLIF N_22.BLIF N_59_i.BLIF N_24.BLIF N_61_i.BLIF \ + a_decode_13__n.BLIF pos_clk_un9_bg_030_n.BLIF un1_amiga_bus_enable_low_i.BLIF N_62_i.BLIF a_decode_12__n.BLIF un21_fpu_cs_i.BLIF N_64_i.BLIF BGACK_030_INT_i.BLIF a_decode_11__n.BLIF \ + AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_244_i.BLIF N_80_i.BLIF a_decode_10__n.BLIF cycle_dma_i_0__n.BLIF N_78_i_0.BLIF RW_000_i.BLIF N_79_i.BLIF a_decode_9__n.BLIF \ + rst_dly_i_0__n.BLIF rst_dly_i_1__n.BLIF N_82_i.BLIF a_decode_8__n.BLIF rst_dly_i_2__n.BLIF N_83_i.BLIF LDS_000_i.BLIF N_55_0.BLIF a_decode_7__n.BLIF \ + UDS_000_i.BLIF N_88_i.BLIF sm_amiga_i_2__n.BLIF N_89_i.BLIF a_decode_6__n.BLIF N_58_i.BLIF N_240_0.BLIF sm_amiga_i_3__n.BLIF N_243_0.BLIF \ + a_decode_5__n.BLIF cpu_est_i_1__n.BLIF CLK_030_c_i.BLIF cpu_est_i_0__n.BLIF N_254_0.BLIF a_decode_4__n.BLIF sm_amiga_i_1__n.BLIF N_114_i.BLIF N_110_i.BLIF \ + N_115_i.BLIF a_decode_3__n.BLIF a_i_1__n.BLIF VMA_INT_i.BLIF N_116_i.BLIF a_decode_2__n.BLIF VPA_D_i.BLIF N_117_i.BLIF DTACK_D0_i.BLIF \ + AS_030_D0_i.BLIF N_118_i.BLIF sm_amiga_i_0__n.BLIF sm_amiga_i_i_7__n.BLIF N_119_i.BLIF sm_amiga_i_6__n.BLIF sm_amiga_i_5__n.BLIF N_120_i.BLIF sm_amiga_i_4__n.BLIF \ + AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN \ + AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ - RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ - SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ - IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ - SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C CLK_000_D_2_.D CLK_000_D_2_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ - SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D \ - RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C inst_RW_000_INT.D inst_RW_000_INT.C \ - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D \ - inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ - inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ - inst_A0_DMA.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2.X1 pos_clk_un21_bgack_030_int_i_0_o2_2_x2.X2 CLK_OUT_PRE_25_0.X1 \ - CLK_OUT_PRE_25_0.X2 G_109.X1 G_109.X2 G_108.X1 G_108.X2 G_107.X1 G_107.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_130_i pos_clk_un6_bgack_000_0_n N_131_i DTACK_c_i \ - CLK_030_H_i N_56_0 RW_000_i VPA_c_i a_i_1__n N_55_0 RESET_OUT_i N_6_i AS_030_i N_47_0 FPU_SENSE_i \ - N_26_i sm_amiga_i_i_7__n N_34_0 vcc_n_n a_decode_i_16__n BG_030_c_i AS_030_D0_i pos_clk_un6_bg_030_i_n gnd_n_n size_dma_i_0__n pos_clk_un9_bg_030_0_n \ - un1_amiga_bus_enable_low size_dma_i_1__n N_25_i un6_as_030 a_decode_i_18__n N_35_0 un3_size a_decode_i_19__n N_24_i un4_size ahigh_i_30__n \ - N_36_0 un1_LDS_000_INT ahigh_i_31__n N_17_i un1_UDS_000_INT ahigh_i_28__n N_43_0 un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_29__n N_4_i un1_DS_000_ENABLE_0_sqmuxa \ - ahigh_i_26__n N_49_0 un4_as_000 ahigh_i_27__n N_3_i un10_ciin ahigh_i_24__n N_50_0 un21_fpu_cs ahigh_i_25__n N_215_i \ - un21_berr N_210_i N_216_i un6_ds_030 N_211_i N_301_0 N_212_i N_243_0 N_266_i un6_ds_030_i N_249_i \ - un4_as_000_i AMIGA_BUS_DATA_DIR_c_0 AS_000_INT_i N_268_i un6_as_030_i pos_clk_ds_000_dma_4_0_n AS_030_c CLK_030_c_i N_236_0 AS_000_c un1_as_000_i \ - N_297_i RW_000_c N_160_i pos_clk_un21_bgack_030_int_i_0_i_n N_100_i UDS_000_c N_186_0 N_183_0 LDS_000_c N_182_0 N_181_0 \ - size_c_0__n N_228_i N_176_0 size_c_1__n LDS_000_c_i UDS_000_c_i ahigh_c_24__n N_173_i N_304_i ahigh_c_25__n AS_030_000_SYNC_i \ - N_157_i ahigh_c_26__n N_110_0 RW_c_i pos_clk_un6_bg_030_n ahigh_c_27__n N_106_0 N_284_i ahigh_c_28__n pos_clk_ipl_n N_334_i \ - ahigh_c_29__n N_278_i ahigh_c_30__n N_279_i ahigh_c_31__n N_332_i N_237_0 un1_SM_AMIGA_0_sqmuxa_1_0 N_247_i N_248_i N_246_i \ - pos_clk_a0_dma_3_n un10_ciin_i N_241_0 un1_DS_000_ENABLE_0_sqmuxa_i N_242_0 N_48_i N_227_i N_9 N_225_i N_224_i N_15 \ - N_223_i N_16 N_22 N_218_i pos_clk_size_dma_6_0_1__n N_217_i pos_clk_size_dma_6_0_0__n N_213_i N_319_i N_300_0 N_15_i \ - a_decode_c_16__n N_45_0 N_16_i a_decode_c_17__n N_44_0 N_22_i a_decode_c_18__n N_38_0 pos_clk_un21_bgack_030_int_i_0_i_1_n a_decode_c_19__n pos_clk_un21_bgack_030_int_i_0_i_2_n \ - N_238_i_1 a_decode_c_20__n N_238_i_2 N_239_i_1 a_decode_c_21__n N_239_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_22__n un10_ciin_1 un10_ciin_2 a_decode_c_23__n \ - un10_ciin_3 un10_ciin_4 a_c_0__n un10_ciin_5 un10_ciin_6 a_c_1__n un10_ciin_7 pos_clk_size_dma_6_0__n un10_ciin_8 pos_clk_size_dma_6_1__n nEXP_SPACE_c \ - un10_ciin_9 un10_ciin_10 BERR_c un10_ciin_11 N_357_1 pos_clk_un21_bgack_030_int_i_0_n BG_030_c N_357_2 N_237 N_357_3 N_241 \ - N_357_4 N_242 N_304_i_1 un21_fpu_cs_1 N_283 BGACK_000_c un21_berr_1_0 N_294 N_266_1 N_300 CLK_030_c \ - N_266_2 N_67_i_1 N_106 N_67_i_2 N_314_1 N_134 CLK_OSZI_c N_314_2 N_138 N_318_1 N_156 \ - N_318_2 N_160 N_341_1 N_167 N_341_2 N_172 N_151_i_1 N_173 FPU_SENSE_c N_143_i_1 N_181 \ - N_141_i_1 N_182 N_237_0_1 N_183 N_240_i_1 N_191 N_60_i_1 N_199 N_64_i_1 N_205 N_155_i_1 \ - N_209 N_147_i_1 N_319 ipl_c_0__n N_145_i_1 N_213 N_139_i_1 N_216 ipl_c_1__n pos_clk_un6_bg_030_1_n N_217 \ - N_220_1 N_218 ipl_c_2__n N_216_1 N_220 N_205_1 N_223 N_199_1 N_224 DTACK_c pos_clk_ipl_1_n \ - N_225 uds_000_int_0_un3_n N_227 uds_000_int_0_un1_n N_228 uds_000_int_0_un0_n N_246 VPA_c as_000_int_0_un3_n N_247 as_000_int_0_un1_n \ - N_248 as_000_int_0_un0_n N_332 RST_c dsack1_int_0_un3_n N_278 dsack1_int_0_un1_n N_279 dsack1_int_0_un0_n N_334 RW_c \ - vma_int_0_un3_n N_284 vma_int_0_un1_n N_343 fc_c_0__n vma_int_0_un0_n lds_000_int_0_un3_n un21_berr_1 fc_c_1__n lds_000_int_0_un1_n N_357 \ - lds_000_int_0_un0_n N_266 ipl_030_0_1__un3_n N_186 AMIGA_BUS_DATA_DIR_c ipl_030_0_1__un1_n ipl_030_0_1__un0_n N_297 ipl_030_0_0__un3_n N_236 ipl_030_0_0__un1_n \ - pos_clk_ds_000_dma_4_n ipl_030_0_0__un0_n N_268 UDS_000_INT_i cpu_est_0_3__un3_n N_249 un1_UDS_000_INT_0 cpu_est_0_3__un1_n N_243 LDS_000_INT_i cpu_est_0_3__un0_n \ - N_215 un1_LDS_000_INT_0 cpu_est_0_2__un3_n N_130 N_23_i cpu_est_0_2__un1_n N_131 N_37_0 cpu_est_0_2__un0_n N_3 N_21_i \ - cpu_est_0_1__un3_n N_4 N_39_0 cpu_est_0_1__un1_n N_17 N_20_i cpu_est_0_1__un0_n N_24 N_40_0 ipl_030_0_2__un3_n N_25 \ - N_19_i ipl_030_0_2__un1_n pos_clk_un9_bg_030_n N_41_0 ipl_030_0_2__un0_n N_6 N_14_i amiga_bus_enable_dma_low_0_un3_n pos_clk_un6_bgack_000_n N_46_0 amiga_bus_enable_dma_low_0_un1_n \ - N_26 ipl_c_i_0__n amiga_bus_enable_dma_low_0_un0_n N_208 N_52_0 rw_000_dma_0_un3_n N_207 ipl_c_i_1__n rw_000_dma_0_un1_n N_349 N_53_0 \ - rw_000_dma_0_un0_n N_314 ipl_c_i_2__n as_000_dma_0_un3_n N_318 N_54_0 as_000_dma_0_un1_n N_348 N_27_i as_000_dma_0_un0_n N_201 \ - N_31_0 ds_000_dma_0_un3_n N_200 N_28_i ds_000_dma_0_un1_n N_203 N_32_0 ds_000_dma_0_un0_n N_204 N_29_i bgack_030_int_0_un3_n \ - N_185 N_33_0 bgack_030_int_0_un1_n N_184 a_c_i_0__n bgack_030_int_0_un0_n N_180 size_c_i_1__n bg_000_0_un3_n N_179 pos_clk_un10_sm_amiga_i_n \ - bg_000_0_un1_n N_178 N_256_0 bg_000_0_un0_n N_171 N_318_i amiga_bus_enable_dma_high_0_un3_n N_341 N_314_i amiga_bus_enable_dma_high_0_un1_n N_342 \ - pos_clk_un9_clk_000_pe_0_n amiga_bus_enable_dma_high_0_un0_n N_169 N_219_i un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n N_154 N_220_i un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n N_165 cpu_est_2_0_1__n un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n \ - N_162 N_221_i size_dma_0_0__un3_n N_299 N_348_i size_dma_0_0__un1_n N_153 cpu_est_2_0_2__n size_dma_0_0__un0_n N_142 N_222_i \ - size_dma_0_1__un3_n N_298 N_196_i size_dma_0_1__un1_n N_80 N_226_i size_dma_0_1__un0_n N_232 ds_000_enable_0_un3_n N_233 N_231_i \ - ds_000_enable_0_un1_n N_229 N_229_i ds_000_enable_0_un0_n N_231 N_302_i as_030_000_sync_0_un3_n N_226 N_233_i as_030_000_sync_0_un1_n N_221 \ - N_232_i as_030_000_sync_0_un0_n N_222 rw_000_int_0_un3_n cpu_est_2_2__n N_80_0 rw_000_int_0_un1_n cpu_est_2_1__n N_343_i rw_000_int_0_un0_n N_219 \ - N_214_0 a0_dma_0_un3_n pos_clk_un9_clk_000_pe_n N_166_i a0_dma_0_un1_n N_256 N_134_i a0_dma_0_un0_n N_29 N_298_i a_decode_15__n \ - N_28 N_142_0 N_27 N_153_i a_decode_14__n N_14 N_154_0 N_19 N_156_i a_decode_13__n N_20 \ - N_305_i N_21 N_299_i a_decode_12__n N_23 N_162_0 un1_amiga_bus_enable_low_i N_165_0 a_decode_11__n un21_fpu_cs_i N_169_i \ - cpu_est_i_1__n VMA_INT_i a_decode_10__n rst_dly_i_2__n N_341_i rst_dly_i_1__n N_342_i a_decode_9__n cpu_est_i_0__n N_171_i cpu_est_i_2__n \ - N_172_i a_decode_8__n sm_amiga_i_0__n N_178_0 sm_amiga_i_3__n N_179_0 a_decode_7__n sm_amiga_i_4__n N_180_0 sm_amiga_i_5__n N_184_0 \ - a_decode_6__n rst_dly_i_0__n N_185_0 sm_amiga_i_2__n N_203_i a_decode_5__n sm_amiga_i_1__n N_204_i VPA_D_i N_205_i a_decode_4__n \ - clk_000_d_i_1__n cpu_est_i_3__n N_200_i a_decode_3__n sm_amiga_i_6__n N_199_i clk_000_d_i_0__n N_201_i a_decode_2__n BGACK_030_INT_i AS_000_i \ - AS_000_DMA_i N_208_i nEXP_SPACE_i N_207_i cycle_dma_i_0__n N_167_i DS_000_DMA_i N_138_i AMIGA_BUS_ENABLE_DMA_LOW_i N_349_i \ + RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ + SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ + IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ + IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ + CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ + cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ + CLK_000_D_0_.D CLK_000_D_0_.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ + inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ + inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D \ + inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ + inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C pos_clk_un21_bgack_030_int_i_0_x2.X1 pos_clk_un21_bgack_030_int_i_0_x2.X2 G_107.X1 \ + G_107.X2 G_108.X1 G_108.X2 G_109.X1 G_109.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ nEXP_SPACE_i N_171_i CLK_030_H_i FPU_SENSE_i \ + N_121_i AS_030_i N_255_0 AS_000_DMA_i un1_SM_AMIGA_0_sqmuxa_1_0 AS_000_i N_48_0 AS_000_INT_i N_125_i DSACK1_INT_i N_126_i \ + clk_000_d_i_0__n vcc_n_n clk_000_d_i_3__n N_127_i un5_e clk_000_d_i_1__n N_128_i cpu_est_i_2__n gnd_n_n cpu_est_i_3__n RW_c_i \ + un1_amiga_bus_enable_low a_decode_i_16__n pos_clk_rw_000_int_5_0_n un7_as_030 a_decode_i_18__n N_129_i un1_UDS_000_INT a_decode_i_19__n un1_LDS_000_INT ahigh_i_30__n un1_SM_AMIGA_0_sqmuxa_1 \ + ahigh_i_31__n un10_ciin_i un1_DS_000_ENABLE_0_sqmuxa ahigh_i_28__n N_261_0 un10_ciin ahigh_i_29__n N_65_0 un21_fpu_cs ahigh_i_26__n N_134_i \ + un21_berr ahigh_i_27__n N_153_i un6_ds_030 ahigh_i_24__n N_67_0 ahigh_i_25__n un2_as_030_i N_206_i N_263_i N_207_i \ + N_265_i N_208_i AS_030_000_SYNC_i N_84_0 clk_000_d_i_2__n N_81_i N_85_i un6_ds_030_i N_141_i DS_000_DMA_i un1_DS_000_ENABLE_0_sqmuxa_i \ + N_147_i pos_clk_un21_bgack_030_int_i_0_i_n N_145_i N_269_i un7_as_030_i N_90_i RESET_OUT_i N_270_i AS_030_c N_271_0 N_96_0 \ + AS_000_c N_97_0 N_98_0 RW_000_c N_282_i N_284_i pos_clk_un14_clk_000_ne_i_n UDS_000_c un5_e_0 N_285_i LDS_000_c \ + N_291_i N_292_i size_c_0__n N_192_i pos_clk_un6_bg_030_n N_17_i size_c_1__n cpu_est_2_0_2__n pos_clk_ipl_n N_286_i ahigh_c_24__n \ + N_288_i AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa cpu_est_2_0_1__n ahigh_c_25__n N_289_i N_290_i ahigh_c_26__n pos_clk_un9_clk_000_pe_0_n N_280_i ahigh_c_27__n pos_clk_un10_sm_amiga_i_n \ + a_c_i_0__n ahigh_c_28__n size_c_i_1__n N_27_i ahigh_c_29__n N_30_0 N_26_i ahigh_c_30__n N_29_0 N_25_i ahigh_c_31__n \ + N_28_0 ipl_c_i_2__n pos_clk_un9_clk_000_pe_n N_51_0 ipl_c_i_1__n pos_clk_rw_000_int_5_n N_50_0 ipl_c_i_0__n N_49_0 N_4_i N_44_0 \ + N_14_i N_4 N_41_0 N_15_i N_40_0 N_9 N_16_i N_39_0 N_18_i N_37_0 N_14 \ + N_21_i N_15 N_34_0 N_16 N_23_i N_18 N_32_0 N_21 LDS_000_INT_i N_23 un1_LDS_000_INT_0 \ + N_25 UDS_000_INT_i N_26 un1_UDS_000_INT_0 N_27 N_96_0_1 N_96_0_2 N_96_0_3 pos_clk_un21_bgack_030_int_i_0_i_1_n N_84_0_1 a_decode_c_16__n \ + N_84_0_2 N_240_0_1 a_decode_c_17__n pos_clk_un10_sm_amiga_i_1_n N_289_1 a_decode_c_18__n N_289_2 N_290_1 a_decode_c_19__n N_290_2 pos_clk_un14_clk_000_ne_1_n \ + a_decode_c_20__n pos_clk_un14_clk_000_ne_2_n N_153_1 a_decode_c_21__n N_153_2 N_153_3 a_decode_c_22__n N_153_4 N_153_5 a_decode_c_23__n un10_ciin_1 \ + un10_ciin_2 a_c_0__n un10_ciin_3 un10_ciin_4 a_c_1__n un10_ciin_5 un10_ciin_6 nEXP_SPACE_c un10_ciin_7 cpu_est_2_1__n un10_ciin_8 \ + cpu_est_2_2__n BERR_c un10_ciin_9 un10_ciin_10 BG_030_c un10_ciin_11 N_260_i_1 pos_clk_un21_bgack_030_int_i_0_n N_260_i_2 N_81 N_233_i_1 \ + N_94 N_233_i_2 N_254 BGACK_000_c N_232_i_1 N_255 N_232_i_2 N_261 CLK_030_c N_247_1 N_65 \ + N_77_1 N_67 N_83_1 N_269 N_88_1 N_108 CLK_OSZI_c N_142_i_1 N_135 N_146_i_1 N_136 \ + N_234_i_1 N_145 pos_clk_un6_bg_030_1_n N_278 N_124_1 N_147 un21_berr_1 N_58 FPU_SENSE_c un21_fpu_cs_1 N_110 \ + N_140_i_1 N_239 N_154_i_1 N_90 N_152_i_1 N_265 N_150_i_1 N_148_i_1 N_144_i_1 pos_clk_un19_bgack_030_int_n N_255_0_1 \ + N_280 ipl_c_0__n N_258_i_1 N_263 N_259_i_1 N_247 ipl_c_1__n N_282_1 N_77 N_284_1 N_289 \ + ipl_c_2__n N_288_1 N_291 un5_e_0_1 N_290 N_192_i_1 N_286 DTACK_c pos_clk_ipl_1_n N_288 bg_000_0_un3_n \ + N_285 bg_000_0_un1_n N_17 bg_000_0_un0_n N_292 VPA_c amiga_bus_enable_dma_low_0_un3_n pos_clk_un14_clk_000_ne_n amiga_bus_enable_dma_low_0_un1_n N_282 amiga_bus_enable_dma_low_0_un0_n \ + N_284 RST_c a0_dma_0_un3_n N_98 a0_dma_0_un1_n N_97 a0_dma_0_un0_n N_84 RW_c rw_000_dma_0_un3_n N_96 \ + rw_000_dma_0_un1_n N_271 fc_c_0__n rw_000_dma_0_un0_n N_117 bgack_030_int_0_un3_n N_141 fc_c_1__n bgack_030_int_0_un1_n N_134 bgack_030_int_0_un0_n \ + N_153 ds_000_dma_0_un3_n N_129 AMIGA_BUS_DATA_DIR_c ds_000_dma_0_un1_n N_127 ds_000_dma_0_un0_n N_128 size_dma_0_1__un3_n N_125 size_dma_0_1__un1_n \ + N_126 size_dma_0_1__un0_n N_124 BG_030_c_i size_dma_0_0__un3_n N_121 pos_clk_un6_bg_030_i_n size_dma_0_0__un1_n N_171 pos_clk_un9_bg_030_0_n size_dma_0_0__un0_n \ + N_120 N_24_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_119 N_31_0 un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_118 N_22_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_116 N_33_0 \ + cpu_est_0_1__un3_n N_114 N_20_i cpu_est_0_1__un1_n N_115 N_35_0 cpu_est_0_1__un0_n N_243 N_19_i cpu_est_0_2__un3_n N_240 \ + N_36_0 cpu_est_0_2__un1_n N_88 N_8_i cpu_est_0_2__un0_n N_89 N_42_0 cpu_est_0_3__un3_n N_82 N_3_i cpu_est_0_3__un1_n \ + N_83 N_45_0 cpu_est_0_3__un0_n N_78 VPA_c_i ipl_030_0_0__un3_n N_79 N_52_0 ipl_030_0_0__un1_n N_91 DTACK_c_i \ + ipl_030_0_0__un0_n N_244 N_53_0 ipl_030_0_1__un3_n N_62 ipl_030_0_1__un1_n N_64 N_249_i ipl_030_0_1__un0_n N_59 N_248_i \ + ipl_030_0_2__un3_n N_61 N_247_i ipl_030_0_2__un1_n N_163 ipl_030_0_2__un0_n N_245 N_77_i uds_000_int_0_un3_n N_242 N_251_i \ + uds_000_int_0_un1_n N_246 N_76_i uds_000_int_0_un0_n N_248 amiga_bus_enable_dma_high_0_un3_n N_236 N_131_i amiga_bus_enable_dma_high_0_un1_n N_249 N_130_i \ + amiga_bus_enable_dma_high_0_un0_n N_92 N_264_i as_000_dma_0_un3_n N_251 N_170_i as_000_dma_0_un1_n N_76 pos_clk_un6_bgack_000_0_n as_000_dma_0_un0_n N_80 \ + pos_clk_rw_000_dma_3_0_n ds_000_enable_0_un3_n pos_clk_a0_dma_3_n N_123_i ds_000_enable_0_un1_n SIZE_DMA_3_sqmuxa N_124_i ds_000_enable_0_un0_n N_87 AMIGA_BUS_DATA_DIR_c_0 lds_000_int_0_un3_n \ + pos_clk_size_dma_6_1__n N_122_i lds_000_int_0_un1_n pos_clk_size_dma_6_0__n pos_clk_ds_000_dma_4_0_n lds_000_int_0_un0_n N_170 N_242_i as_030_000_sync_0_un3_n N_122 N_239_i \ + as_030_000_sync_0_un1_n N_123 N_87_i as_030_000_sync_0_un0_n N_130 N_236_0 rw_000_int_0_un3_n pos_clk_ds_000_dma_4_n N_246_i rw_000_int_0_un1_n pos_clk_rw_000_dma_3_n \ + pos_clk_size_dma_6_0_0__n rw_000_int_0_un0_n pos_clk_un6_bgack_000_n N_245_i vma_int_0_un3_n N_131 pos_clk_size_dma_6_0_1__n vma_int_0_un1_n N_3 N_91_i vma_int_0_un0_n \ + N_8 N_210_i a_decode_15__n N_19 pos_clk_un19_bgack_030_int_i_n N_20 N_163_0 a_decode_14__n N_22 N_59_i N_24 \ + N_61_i a_decode_13__n pos_clk_un9_bg_030_n un1_amiga_bus_enable_low_i N_62_i a_decode_12__n un21_fpu_cs_i N_64_i BGACK_030_INT_i a_decode_11__n AMIGA_BUS_ENABLE_DMA_LOW_i \ + N_244_i N_80_i a_decode_10__n cycle_dma_i_0__n N_78_i_0 RW_000_i N_79_i a_decode_9__n rst_dly_i_0__n rst_dly_i_1__n N_82_i \ + a_decode_8__n rst_dly_i_2__n N_83_i LDS_000_i N_55_0 a_decode_7__n UDS_000_i N_88_i sm_amiga_i_2__n N_89_i a_decode_6__n \ + N_58_i N_240_0 sm_amiga_i_3__n N_243_0 a_decode_5__n cpu_est_i_1__n CLK_030_c_i cpu_est_i_0__n N_254_0 a_decode_4__n sm_amiga_i_1__n \ + N_114_i N_110_i N_115_i a_decode_3__n a_i_1__n VMA_INT_i N_116_i a_decode_2__n VPA_D_i N_117_i DTACK_D0_i \ + AS_030_D0_i N_118_i sm_amiga_i_0__n sm_amiga_i_i_7__n N_119_i sm_amiga_i_6__n sm_amiga_i_5__n N_120_i sm_amiga_i_4__n \ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE \ DS_030.OE DSACK1.OE RESET.OE CIIN.OE -.names un6_as_030_i.BLIF AS_030 +.names un7_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c 1 1 -.names N_283.BLIF AS_030.OE +.names N_135.BLIF AS_030.OE 1 1 -.names un4_as_000_i.BLIF AS_000 +.names N_145_i.BLIF AS_000 1 1 .names AS_000.PIN AS_000_c 1 1 -.names un1_as_000_i.BLIF AS_000.OE +.names N_136.BLIF AS_000.OE 1 1 .names inst_RW_000_INT.BLIF RW_000 1 1 .names RW_000.PIN RW_000_c 1 1 -.names un1_as_000_i.BLIF RW_000.OE +.names N_136.BLIF RW_000.OE 1 1 .names un1_UDS_000_INT.BLIF UDS_000 1 1 .names UDS_000.PIN UDS_000_c 1 1 -.names un1_as_000_i.BLIF UDS_000.OE +.names N_136.BLIF UDS_000.OE 1 1 .names un1_LDS_000_INT.BLIF LDS_000 1 1 .names LDS_000.PIN LDS_000_c 1 1 -.names un1_as_000_i.BLIF LDS_000.OE +.names N_136.BLIF LDS_000.OE 1 1 -.names un4_size.BLIF SIZE_0_ +.names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 .names SIZE_0_.PIN size_c_0__n 1 1 -.names N_48_i.BLIF SIZE_0_.OE +.names un2_as_030_i.BLIF SIZE_0_.OE 1 1 -.names un3_size.BLIF SIZE_1_ +.names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 .names SIZE_1_.PIN size_c_1__n 1 1 -.names N_48_i.BLIF SIZE_1_.OE +.names un2_as_030_i.BLIF SIZE_1_.OE 1 1 .names gnd_n_n.BLIF AHIGH_24_ 1 1 .names AHIGH_24_.PIN ahigh_c_24__n 1 1 -.names N_283.BLIF AHIGH_24_.OE +.names N_135.BLIF AHIGH_24_.OE 1 1 .names gnd_n_n.BLIF AHIGH_25_ 1 1 .names AHIGH_25_.PIN ahigh_c_25__n 1 1 -.names N_283.BLIF AHIGH_25_.OE +.names N_135.BLIF AHIGH_25_.OE 1 1 .names gnd_n_n.BLIF AHIGH_26_ 1 1 .names AHIGH_26_.PIN ahigh_c_26__n 1 1 -.names N_283.BLIF AHIGH_26_.OE +.names N_135.BLIF AHIGH_26_.OE 1 1 .names gnd_n_n.BLIF AHIGH_27_ 1 1 .names AHIGH_27_.PIN ahigh_c_27__n 1 1 -.names N_283.BLIF AHIGH_27_.OE +.names N_135.BLIF AHIGH_27_.OE 1 1 .names gnd_n_n.BLIF AHIGH_28_ 1 1 .names AHIGH_28_.PIN ahigh_c_28__n 1 1 -.names N_283.BLIF AHIGH_28_.OE +.names N_135.BLIF AHIGH_28_.OE 1 1 .names gnd_n_n.BLIF AHIGH_29_ 1 1 .names AHIGH_29_.PIN ahigh_c_29__n 1 1 -.names N_283.BLIF AHIGH_29_.OE +.names N_135.BLIF AHIGH_29_.OE 1 1 .names gnd_n_n.BLIF AHIGH_30_ 1 1 .names AHIGH_30_.PIN ahigh_c_30__n 1 1 -.names N_283.BLIF AHIGH_30_.OE +.names N_135.BLIF AHIGH_30_.OE 1 1 .names gnd_n_n.BLIF AHIGH_31_ 1 1 .names AHIGH_31_.PIN ahigh_c_31__n 1 1 -.names N_283.BLIF AHIGH_31_.OE +.names N_135.BLIF AHIGH_31_.OE 1 1 .names inst_A0_DMA.BLIF A_0_ 1 1 .names A_0_.PIN a_c_0__n 1 1 -.names N_283.BLIF A_0_.OE +.names N_135.BLIF A_0_.OE 1 1 .names gnd_n_n.BLIF BERR 1 1 @@ -309,13 +308,13 @@ 1 1 .names RW.PIN RW_c 1 1 -.names N_294.BLIF RW.OE +.names N_278.BLIF RW.OE 1 1 .names un6_ds_030_i.BLIF DS_030 1 1 -.names N_283.BLIF DS_030.OE +.names N_135.BLIF DS_030.OE 1 1 -.names inst_DSACK1_INTreg.BLIF DSACK1 +.names N_147_i.BLIF DSACK1 1 1 .names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 @@ -325,1348 +324,1344 @@ 1 1 .names un10_ciin.BLIF CIIN 1 1 -.names N_241.BLIF CIIN.OE +.names N_261.BLIF CIIN.OE 1 1 -.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_2_.D +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF pos_clk_un10_sm_amiga_i_n 11 1 -.names N_165.BLIF inst_VPA_D.BLIF N_342 -11 1 -.names N_203_i.BLIF N_204_i.BLIF N_239_i_1 -11 1 -.names inst_VPA_D.BLIF VPA_D_i +.names RST_DLY_2_.BLIF rst_dly_i_2__n 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names N_205_i.BLIF RST_c.BLIF N_239_i_2 -11 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF N_299 -11 1 -.names N_239_i_1.BLIF N_239_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_134_i.BLIF N_214_0.BLIF N_298 -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n -11 1 -.names N_179.BLIF sm_amiga_i_2__n.BLIF N_334 -11 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_242_0.BLIF N_242 -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_279 -11 1 -.names N_227.BLIF N_227_i -0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_225.BLIF N_225_i -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_305_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names N_224.BLIF N_224_i -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_156_i -11 1 -.names N_223.BLIF N_223_i -0 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_218.BLIF N_218_i -0 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_154_0 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_153_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names N_217.BLIF N_217_i -0 1 -.names N_298_i.BLIF RST_c.BLIF N_142_0 -11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_213.BLIF N_213_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_134_i -11 1 -.names N_319.BLIF N_319_i -0 1 -.names N_134.BLIF RST_c.BLIF N_166_i -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names N_300_0.BLIF N_300 -0 1 -.names N_343_i.BLIF RST_c.BLIF N_214_0 -11 1 -.names N_15.BLIF N_15_i -0 1 -.names AS_030_D0_i.BLIF N_167.BLIF N_80_0 -11 1 -.names N_45_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_232_i.BLIF N_233_i.BLIF cpu_est_0_.D -11 1 -.names N_16.BLIF N_16_i -0 1 -.names N_229_i.BLIF N_231_i.BLIF N_302_i -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C -1 1 -.names RW_c.BLIF RW_c_i -0 1 -.names N_166_i.BLIF N_226_i.BLIF SM_AMIGA_5_.D -11 1 -.names N_106_0.BLIF N_106 -0 1 -.names N_221_i.BLIF N_222_i.BLIF N_196_i -11 1 -.names N_284.BLIF N_284_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_334.BLIF N_334_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_138_i -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C -1 1 -.names N_278.BLIF N_278_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_279.BLIF N_279_i -0 1 -.names N_138_i.BLIF SM_AMIGA_6_.BLIF N_167_i -11 1 -.names N_332.BLIF N_332_i -0 1 -.names N_237_0.BLIF N_237 -0 1 -.names N_134_i.BLIF SM_AMIGA_5_.BLIF N_185_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_184_0 -11 1 -.names N_247.BLIF N_247_i -0 1 -.names N_138_i.BLIF SM_AMIGA_4_.BLIF N_180_0 -11 1 -.names N_248.BLIF N_248_i -0 1 -.names N_172_i.BLIF SM_AMIGA_3_.BLIF N_179_0 -11 1 -.names N_246.BLIF N_246_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_178_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C -1 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names N_134_i.BLIF N_171.BLIF N_172_i -11 1 -.names N_241_0.BLIF N_241 -0 1 -.names N_341_i.BLIF N_342_i.BLIF N_171_i -11 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF un1_DS_000_ENABLE_0_sqmuxa_i -0 1 -.names N_134_i.BLIF SM_AMIGA_1_.BLIF N_169_i -11 1 -.names N_236_0.BLIF N_236 -0 1 -.names BERR_c.BLIF inst_DTACK_D0.BLIF N_165_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C -1 1 -.names N_297.BLIF N_297_i -0 1 -.names N_299_i.BLIF sm_amiga_i_4__n.BLIF N_162_0 -11 1 -.names N_160_i.BLIF N_160 -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_56_0 -11 1 -.names pos_clk_un21_bgack_030_int_i_0_i_n.BLIF pos_clk_un21_bgack_030_int_i_0_n -0 1 -.names CYCLE_DMA_0_.BLIF N_138_i.BLIF N_208 -11 1 -.names N_100_i.BLIF inst_BGACK_030_INT_D.D -0 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -.names N_186_0.BLIF N_186 -0 1 -.names cycle_dma_i_0__n.BLIF N_138.BLIF N_207 -11 1 -.names N_183_0.BLIF N_183 -0 1 -.names N_138_i.BLIF SM_AMIGA_0_.BLIF N_228 -11 1 -.names N_182_0.BLIF N_182 -0 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_181_0.BLIF N_181 -0 1 -.names N_294.BLIF nEXP_SPACE_i.BLIF N_283 -11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names N_228.BLIF N_228_i -0 1 -.names N_138.BLIF SM_AMIGA_2_.BLIF N_278 +.names N_263_i.BLIF N_291.BLIF N_289_1 11 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_173_i.BLIF N_173 -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +.names N_269.BLIF rst_dly_i_2__n.BLIF N_249 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_289_2 +11 1 +.names N_236.BLIF N_239_i.BLIF N_251 +11 1 +.names N_289_1.BLIF N_289_2.BLIF N_289 +11 1 +.names N_92.BLIF rst_dly_i_1__n.BLIF N_76 +11 1 +.names N_269_i.BLIF N_280_i.BLIF N_290_1 +11 1 +.names N_236.BLIF RST_DLY_0_.BLIF N_78 11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_110_0.BLIF inst_AS_030_D0.D -0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_294 +.names N_291.BLIF VPA_D_i.BLIF N_290_2 11 1 -.names N_43_0.BLIF inst_RW_000_DMA.D -0 1 -.names AS_000_c.BLIF N_138_i.BLIF N_349 +.names N_92.BLIF rst_dly_i_0__n.BLIF N_79 11 1 -.names N_4.BLIF N_4_i +.names N_290_1.BLIF N_290_2.BLIF N_290 +11 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_82 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF pos_clk_un14_clk_000_ne_1_n +11 1 +.names a_c_1__n.BLIF a_i_1__n 0 1 -.names BGACK_000_c.BLIF N_349_i.BLIF pos_clk_un6_bgack_000_0_n +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF pos_clk_un14_clk_000_ne_2_n +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_81 11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 -.names N_49_0.BLIF inst_AS_000_DMA.D -0 1 -.names N_130.BLIF N_130_i -0 1 -.names N_3.BLIF N_3_i -0 1 -.names N_160.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_50_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_130_i.BLIF N_160.BLIF amiga_bus_enable_dma_low_0_un1_n +.names pos_clk_un14_clk_000_ne_1_n.BLIF pos_clk_un14_clk_000_ne_2_n.BLIF pos_clk_un14_clk_000_ne_n 11 1 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +.names N_110.BLIF N_110_i +0 1 +.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_153_1 +11 1 +.names N_110_i.BLIF sm_amiga_i_3__n.BLIF N_244 +11 1 +.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_153_2 +11 1 +.names N_85_i.BLIF sm_amiga_i_2__n.BLIF N_64 +11 1 +.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_153_3 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 -.names N_215.BLIF N_215_i +.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +.names N_243.BLIF sm_amiga_i_1__n.BLIF N_62 11 1 -.names N_216.BLIF N_216_i +.names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -.names N_301_0.BLIF inst_RESET_OUT.D -0 1 -.names N_160.BLIF rw_000_dma_0_un3_n -0 1 -.names N_243_0.BLIF N_243 -0 1 -.names N_243.BLIF N_160.BLIF rw_000_dma_0_un1_n -11 1 -.names N_266.BLIF N_266_i -0 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_249.BLIF N_249_i -0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_236.BLIF as_000_dma_0_un3_n -0 1 -.names N_268.BLIF N_268_i -0 1 -.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_236.BLIF as_000_dma_0_un1_n -11 1 -.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names CLK_030_c.BLIF CLK_030_c_i -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -.names N_56_0.BLIF inst_DTACK_D0.D -0 1 -.names N_237.BLIF ds_000_dma_0_un3_n -0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names pos_clk_ds_000_dma_4_n.BLIF N_237.BLIF ds_000_dma_0_un1_n -11 1 -.names N_55_0.BLIF inst_VPA_D.D -0 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names N_6.BLIF N_6_i -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names N_47_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_26.BLIF N_26_i -0 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low -11 1 -.names N_34_0.BLIF BG_000DFFreg.D -0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_25.BLIF N_25_i -0 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names N_24.BLIF N_24_i -0 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names N_17.BLIF N_17_i -0 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names N_184_0.BLIF N_184 -0 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names N_185_0.BLIF N_185 -0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names N_203.BLIF N_203_i -0 1 -.names N_26_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names N_204.BLIF N_204_i -0 1 -.names N_6_i.BLIF RST_c.BLIF N_47_0 -11 1 -.names N_205.BLIF N_205_i -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_55_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names N_200.BLIF N_200_i -0 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_131 -11 1 -.names N_199.BLIF N_199_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_332 -11 1 -.names N_201.BLIF N_201_i -0 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_268 -11 1 -.names N_208.BLIF N_208_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -.names N_207.BLIF N_207_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_249 -11 1 -.names N_167_i.BLIF N_167 -0 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names N_138_i.BLIF N_138 -0 1 -.names CLK_030_H_i.BLIF N_186.BLIF N_246 -11 1 -.names N_349.BLIF N_349_i -0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_215 -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C -1 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names N_3_i.BLIF RST_c.BLIF N_50_0 -11 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names N_4_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names N_153_i.BLIF N_153 -0 1 -.names N_17_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names N_154_0.BLIF N_154 -0 1 -.names N_24_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C -1 1 -.names N_156_i.BLIF N_156 -0 1 -.names N_25_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names N_299.BLIF N_299_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names N_162_0.BLIF N_162 -0 1 -.names N_160.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names N_165_0.BLIF N_165 -0 1 -.names N_131_i.BLIF N_160.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -.names N_169_i.BLIF N_169 -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 -1- 1 --1 1 -.names N_341.BLIF N_341_i -0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 -11 1 -.names N_342.BLIF N_342_i -0 1 -.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_186_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -.names N_171_i.BLIF N_171 -0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_100_i -11 1 -.names N_172_i.BLIF N_172 -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_160_i +.names N_269_i.BLIF cpu_est_0_.BLIF N_61 11 1 -.names N_178_0.BLIF N_178 -0 1 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -.names N_179_0.BLIF N_179 -0 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_180_0.BLIF N_180 -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_236_0 -11 1 -.names N_221.BLIF N_221_i -0 1 -.names N_268_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF pos_clk_ds_000_dma_4_0_n -11 1 -.names N_348.BLIF N_348_i -0 1 -.names N_249_i.BLIF N_266_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_243_0 -11 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -.names N_222.BLIF N_222_i -0 1 -.names N_215_i.BLIF N_216_i.BLIF N_301_0 -11 1 -.names N_226.BLIF N_226_i -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_297 -11 1 -.names N_231.BLIF N_231_i -0 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_130 -11 1 -.names N_229.BLIF N_229_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_233.BLIF N_233_i -0 1 -.names AS_030_D0_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_242_0 -11 1 -.names N_232.BLIF N_232_i -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_241_0 -11 1 -.names N_80_0.BLIF N_80 -0 1 -.names N_167.BLIF N_176_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 -11 1 -.names N_343.BLIF N_343_i -0 1 -.names N_176_0.BLIF RW_c_i.BLIF N_106_0 -11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names N_134_i.BLIF N_134 -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_110_0 -11 1 -.names N_298.BLIF N_298_i -0 1 -.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_157_i -11 1 -.names N_142_0.BLIF N_142 -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_173_i -11 1 -.names N_54_0.BLIF IPL_D0_2_.D -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names N_27.BLIF N_27_i -0 1 -.names N_228_i.BLIF SM_AMIGA_i_7_.BLIF N_176_0 -11 1 -.names N_31_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names N_157_i.BLIF N_160_i.BLIF N_181_0 -11 1 -.names N_28.BLIF N_28_i -0 1 -.names N_304_i.BLIF nEXP_SPACE_c.BLIF N_182_0 -11 1 -.names N_32_0.BLIF IPL_030DFF_1_reg.D -0 1 -.names N_157_i.BLIF N_304_i.BLIF N_183_0 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names A_DECODE_16_.BLIF a_decode_c_16__n -1 1 -.names N_29.BLIF N_29_i -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n -0 1 -.names A_DECODE_17_.BLIF a_decode_c_17__n -1 1 -.names N_33_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n -11 1 -.names A_DECODE_18_.BLIF a_decode_c_18__n -1 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n -11 1 -.names A_DECODE_19_.BLIF a_decode_c_19__n -1 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n.BLIF N_191 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names A_DECODE_20_.BLIF a_decode_c_20__n -1 1 -.names N_256_0.BLIF N_256 -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names A_DECODE_21_.BLIF a_decode_c_21__n -1 1 -.names N_318.BLIF N_318_i -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names A_DECODE_22_.BLIF a_decode_c_22__n -1 1 -.names N_314.BLIF N_314_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names A_DECODE_23_.BLIF a_decode_c_23__n -1 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n -0 1 -.names N_160_i.BLIF RST_c.BLIF N_209 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -.names N_219.BLIF N_219_i -0 1 -.names AS_030_D0_i.BLIF N_181.BLIF N_319 -11 1 -.names A_1_.BLIF a_c_1__n -1 1 -.names N_220.BLIF N_220_i -0 1 -.names AS_030_D0_i.BLIF N_357.BLIF N_213 -11 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names N_23.BLIF N_23_i -0 1 -.names BGACK_030_INT_i.BLIF N_173.BLIF N_217 -11 1 -.names N_37_0.BLIF inst_UDS_000_INT.D -0 1 -.names BGACK_030_INT_i.BLIF N_173_i.BLIF N_218 -11 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names BG_030.BLIF BG_030_c -1 1 -.names N_21.BLIF N_21_i -0 1 -.names N_182.BLIF sm_amiga_i_i_7__n.BLIF N_227 -11 1 -.names BG_000DFFreg.BLIF BG_000 -1 1 -.names N_39_0.BLIF inst_AS_000_INT.D -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names N_20.BLIF N_20_i -0 1 -.names N_183.BLIF sm_amiga_i_6__n.BLIF N_284 -11 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names N_40_0.BLIF inst_DSACK1_INTreg.D -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names N_19.BLIF N_19_i -0 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -.names N_41_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_213_i.BLIF N_319_i.BLIF N_300_0 -11 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names N_14.BLIF N_14_i -0 1 -.names N_217_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names N_46_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_218_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_48_i -11 1 -.names un21_fpu_cs_i.BLIF FPU_CS -1 1 -.names N_52_0.BLIF IPL_D0_0_.D -0 1 -.names G_109.BLIF N_212_i -0 1 -.names FPU_SENSE.BLIF FPU_SENSE_c -1 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ -1 1 -.names N_53_0.BLIF IPL_D0_1_.D -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ -1 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ -1 1 .names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names IPL_0_.BLIF ipl_c_0__n +.names N_269.BLIF cpu_est_i_0__n.BLIF N_59 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C 1 1 .names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 +.names N_240.BLIF N_269_i.BLIF N_58 +11 1 +.names inst_BGACK_030_INT_D.BLIF inst_BGACK_030_INTreg.BLIF N_96_0_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names AS_030_D0_i.BLIF sm_amiga_i_i_7__n.BLIF N_96_0_2 +11 1 +.names N_58.BLIF N_58_i +0 1 +.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0_3 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names N_96_0_3.BLIF nEXP_SPACE_c.BLIF N_96_0 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names pos_clk_un21_bgack_030_int_i_0_x2.BLIF N_264_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_1_n +11 1 +.names N_84.BLIF sm_amiga_i_i_7__n.BLIF N_116 +11 1 +.names pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF pos_clk_un19_bgack_030_int_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_n +11 1 +.names N_263_i.BLIF sm_amiga_i_1__n.BLIF N_115 +11 1 +.names CLK_000_D_4_.BLIF clk_000_d_i_3__n.BLIF N_84_0_1 +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF N_84_0_2 +11 1 +.names N_90.BLIF sm_amiga_i_0__n.BLIF N_114 +11 1 +.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0 +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names BERR_c.BLIF N_88_i.BLIF N_240_0_1 +11 1 +.names N_263_i.BLIF SM_AMIGA_4_.BLIF N_110 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names N_263_i.BLIF SM_AMIGA_2_.BLIF N_243_0 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names N_49_0.BLIF IPL_D0_0_.D +0 1 +.names N_82_i.BLIF N_83_i.BLIF N_55_0 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_59_i.BLIF N_61_i.BLIF cpu_est_0_.D +11 1 +.names N_44_0.BLIF inst_AS_000_DMA.D +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_14.BLIF N_14_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_89 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_15.BLIF N_15_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_40_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +11 1 +.names N_16.BLIF N_16_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names N_39_0.BLIF inst_RW_000_INT.D +0 1 +.names CLK_030_H_i.BLIF N_98.BLIF N_129 +11 1 +.names N_18.BLIF N_18_i +0 1 +.names N_90_i.BLIF RST_c.BLIF N_128 +11 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_147.BLIF RST_c.BLIF N_127 +11 1 +.names N_21.BLIF N_21_i +0 1 +.names N_265_i.BLIF RST_c.BLIF N_126 +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +.names N_34_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_145.BLIF RST_c.BLIF N_125 +11 1 +.names N_23.BLIF N_23_i +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_290.BLIF N_290_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_121 +11 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names N_280_i.BLIF N_280 +0 1 +.names N_271.BLIF sm_amiga_i_4__n.BLIF N_120 +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_265.BLIF sm_amiga_i_5__n.BLIF N_119 +11 1 +.names N_27.BLIF N_27_i +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +.names N_30_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_97.BLIF sm_amiga_i_6__n.BLIF N_118 +11 1 +.names N_26.BLIF N_26_i +0 1 +.names N_263_i.BLIF SM_AMIGA_0_.BLIF N_117 +11 1 +.names N_29_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_254_0 +11 1 +.names N_25.BLIF N_25_i +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +.names N_28_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_147 +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_278 +11 1 +.names N_51_0.BLIF IPL_D0_2_.D +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_145 +11 1 +.names N_50_0.BLIF IPL_D0_1_.D +0 1 +.names N_265_i.BLIF RW_c.BLIF N_141 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +.names N_97_0.BLIF N_97 +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names N_98_0.BLIF N_98 +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names N_282.BLIF N_282_i +0 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 +11 1 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +.names N_284.BLIF N_284_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF N_136 +11 1 +.names pos_clk_un14_clk_000_ne_n.BLIF pos_clk_un14_clk_000_ne_i_n +0 1 +.names N_278.BLIF nEXP_SPACE_i.BLIF N_135 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +.names un5_e_0.BLIF un5_e +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_285.BLIF N_285_i +0 1 +.names AS_030_i.BLIF N_96.BLIF N_134 +11 1 +.names N_291.BLIF N_291_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +.names N_292.BLIF N_292_i +0 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names N_17.BLIF N_17_i +0 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_2__n.BLIF N_85_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +0 1 +.names N_263_i.BLIF SM_AMIGA_6_.BLIF N_265_i +11 1 +.names N_286.BLIF N_286_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_288.BLIF N_288_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_263_i +11 1 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names N_289.BLIF N_289_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF un2_as_030_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +.names N_134.BLIF N_134_i +0 1 +.names N_134_i.BLIF N_153_i.BLIF N_67_0 +11 1 +.names N_153.BLIF N_153_i +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_65_0 +11 1 +.names N_67_0.BLIF N_67 +0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_261_0 +11 1 +.names N_263_i.BLIF N_263 +0 1 +.names N_270_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +.names N_265_i.BLIF N_265 +0 1 +.names N_127_i.BLIF N_128_i.BLIF inst_DSACK1_INT.D +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_125_i.BLIF N_126_i.BLIF inst_AS_000_INT.D +11 1 +.names N_84_0.BLIF N_84 +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names CLK_000_D_2_.BLIF clk_000_d_i_2__n +0 1 +.names N_265.BLIF N_270_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +.names N_141.BLIF N_141_i +0 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_291 +11 1 +.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_286 +11 1 +.names pos_clk_un21_bgack_030_int_i_0_i_n.BLIF pos_clk_un21_bgack_030_int_i_0_n +0 1 +.names N_280_i.BLIF cpu_est_i_2__n.BLIF N_17 +11 1 +.names N_269_i.BLIF N_269 +0 1 +.names N_280.BLIF cpu_est_2_.BLIF N_285 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names N_90_i.BLIF N_90 +0 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names N_271_0.BLIF N_271 +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_96_0.BLIF N_96 +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n +0 1 +.names N_171.BLIF N_171_i +0 1 +.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names N_121.BLIF N_121_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n +11 1 +.names N_255_0.BLIF N_255 +0 1 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_108 +1- 1 +-1 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_98_0 +11 1 +.names N_48_0.BLIF inst_AS_030_D0.D +0 1 +.names N_84_0.BLIF sm_amiga_i_i_7__n.BLIF N_97_0 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names N_125.BLIF N_125_i +0 1 +.names N_269_i.BLIF SM_AMIGA_5_.BLIF N_271_0 +11 1 +.names N_126.BLIF N_126_i +0 1 +.names N_117_i.BLIF SM_AMIGA_i_7_.BLIF N_270_i +11 1 +.names N_127.BLIF N_127_i +0 1 +.names N_85_i.BLIF SM_AMIGA_1_.BLIF N_90_i +11 1 +.names N_128.BLIF N_128_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names RW_c.BLIF RW_c_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_269_i +11 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names N_110_i.BLIF N_141_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +11 1 +.names N_129.BLIF N_129_i +0 1 .names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i +.names un10_ciin.BLIF un10_ciin_i 0 1 .names ahigh_c_29__n.BLIF ahigh_i_29__n 0 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT +.names N_261_0.BLIF N_261 0 1 .names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 -.names N_23_i.BLIF RST_c.BLIF N_37_0 -11 1 +.names N_65_0.BLIF N_65 +0 1 .names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names DTACK.BLIF DTACK_c -1 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 -11 1 +.names N_83.BLIF N_83_i +0 1 .names a_decode_c_18__n.BLIF a_decode_i_18__n 0 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 -11 1 +.names N_55_0.BLIF inst_RESET_OUT.D +0 1 .names a_decode_c_19__n.BLIF a_decode_i_19__n 0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C +.names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 -.names N_302_i.BLIF E -1 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +.names N_88.BLIF N_88_i 0 1 -.names VPA.BLIF VPA_c -1 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n +.names N_89.BLIF N_89_i 0 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names RST.BLIF RST_c -1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_23 -1- 1 --1 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n +.names N_240_0.BLIF N_240 0 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C +.names N_243_0.BLIF N_243 +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 -.names N_80.BLIF as_000_int_0_un3_n +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_280_i +11 1 +.names N_254_0.BLIF N_254 +0 1 +.names N_289_i.BLIF N_290_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names N_114.BLIF N_114_i +0 1 +.names N_286_i.BLIF N_288_i.BLIF cpu_est_2_0_1__n +11 1 +.names N_115.BLIF N_115_i +0 1 +.names N_17_i.BLIF N_285_i.BLIF cpu_est_2_0_2__n +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C +1 1 +.names N_116.BLIF N_116_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_2__n.BLIF N_292 +11 1 +.names N_117.BLIF N_117_i +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D +0 1 +.names N_118.BLIF N_118_i 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_167.BLIF N_80.BLIF as_000_int_0_un1_n -11 1 -.names G_107.BLIF N_210_i +.names N_119.BLIF N_119_i 0 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names G_108.BLIF N_211_i +.names G_107.BLIF N_206_i 0 1 -.names FC_1_.BLIF fc_c_1__n +.names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_21 +.names N_120.BLIF N_120_i +0 1 +.names G_108.BLIF N_207_i +0 1 +.names N_246.BLIF N_246_i +0 1 +.names G_109.BLIF N_208_i +0 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_245.BLIF N_245_i +0 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_91.BLIF N_91_i +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names pos_clk_un19_bgack_030_int_i_n.BLIF pos_clk_un19_bgack_030_int_n +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names N_163_0.BLIF N_163 +0 1 +.names N_25_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names N_59.BLIF N_59_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names N_61.BLIF N_61_i +0 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_62.BLIF N_62_i +0 1 +.names N_269.BLIF cpu_est_0_1__un3_n +0 1 +.names N_64.BLIF N_64_i +0 1 +.names cpu_est_1_.BLIF N_269.BLIF cpu_est_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names N_244.BLIF N_244_i +0 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_78.BLIF N_78_i_0 +0 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names N_209.BLIF size_dma_0_0__un3_n +.names N_79.BLIF N_79_i 0 1 +.names N_269.BLIF cpu_est_0_2__un3_n +0 1 +.names N_82.BLIF N_82_i +0 1 +.names cpu_est_2_.BLIF N_269.BLIF cpu_est_0_2__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names A_DECODE_16_.BLIF a_decode_c_16__n +1 1 +.names N_76.BLIF N_76_i +0 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names A_DECODE_17_.BLIF a_decode_c_17__n +1 1 +.names N_131.BLIF N_131_i +0 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names A_DECODE_18_.BLIF a_decode_c_18__n +1 1 +.names N_130.BLIF N_130_i +0 1 +.names N_269.BLIF cpu_est_0_3__un3_n +0 1 +.names A_DECODE_19_.BLIF a_decode_c_19__n +1 1 +.names N_170.BLIF N_170_i +0 1 +.names cpu_est_3_.BLIF N_269.BLIF cpu_est_0_3__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names A_DECODE_20_.BLIF a_decode_c_20__n +1 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names N_192_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names A_DECODE_21_.BLIF a_decode_c_21__n +1 1 +.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n +0 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 +.names A_DECODE_22_.BLIF a_decode_c_22__n +1 1 +.names N_123.BLIF N_123_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names A_DECODE_23_.BLIF a_decode_c_23__n +1 1 +.names N_124.BLIF N_124_i +0 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names A_1_.BLIF a_c_1__n +1 1 +.names N_122.BLIF N_122_i +0 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_25 +1- 1 +-1 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_242_i.BLIF N_242 +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_239_i.BLIF N_239 +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names N_87.BLIF N_87_i +0 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_26 +1- 1 +-1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names N_236_0.BLIF N_236 +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_19.BLIF N_19_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +1 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names N_36_0.BLIF inst_RW_000_DMA.D +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +.names N_8.BLIF N_8_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_27 +1- 1 +-1 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names N_3.BLIF N_3_i +0 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names N_45_0.BLIF inst_DS_000_DMA.D +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names N_52_0.BLIF inst_VPA_D.D +0 1 +.names N_81.BLIF N_81_i +0 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names N_94.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names N_53_0.BLIF inst_DTACK_D0.D +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_94.BLIF amiga_bus_enable_dma_high_0_un1_n +11 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names N_249.BLIF N_249_i +0 1 +.names N_81_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names N_248.BLIF N_248_i +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 +1- 1 +-1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names N_247.BLIF N_247_i +0 1 +.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 .names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 1 -.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +.names IPL_2_.BLIF ipl_c_2__n 1 1 -.names N_256.BLIF dsack1_int_0_un3_n +.names N_77.BLIF N_77_i 0 1 -.names SIZE_DMA_0_.BLIF N_209.BLIF size_dma_0_0__un1_n +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names N_169.BLIF N_256.BLIF dsack1_int_0_un1_n -11 1 -.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D -1- 1 --1 1 -.names N_191.BLIF AMIGA_BUS_ENABLE_HIGH -1 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names N_209.BLIF size_dma_0_1__un3_n +.names N_251.BLIF N_251_i 0 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +11 1 +.names DTACK.BLIF DTACK_c +1 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_23_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 .names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names un5_e.BLIF E +1 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names SIZE_DMA_1_.BLIF N_209.BLIF size_dma_0_1__un1_n +.names N_18_i.BLIF RST_c.BLIF N_37_0 11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +.names VPA.BLIF VPA_c +1 1 +.names N_24.BLIF N_24_i 0 1 -.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +.names N_16_i.BLIF RST_c.BLIF N_39_0 11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_220_1 -11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names N_220_1.BLIF cpu_est_i_3__n.BLIF N_220 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names un6_as_030.BLIF un6_as_030_i +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names N_31_0.BLIF BG_000DFFreg.D 0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names RST.BLIF RST_c +1 1 +.names N_22.BLIF N_22_i +0 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 .names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 -.names N_134_i.BLIF N_343.BLIF N_216_1 -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i +.names N_33_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_216_1.BLIF RST_c.BLIF N_216 +.names N_4_i.BLIF RST_c.BLIF N_44_0 11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +.names N_20.BLIF N_20_i 0 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 11 1 -.names N_214_0.BLIF rst_dly_i_0__n.BLIF N_205_1 -11 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names un4_as_000.BLIF un4_as_000_i +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_35_0.BLIF inst_A0_DMA.D 0 1 -.names N_205_1.BLIF rst_dly_i_1__n.BLIF N_205 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 11 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +.names FC_1_.BLIF fc_c_1__n +1 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names un6_ds_030.BLIF un6_ds_030_i +.names inst_RESET_OUT.BLIF RESET_OUT_i 0 1 .names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 -.names N_156.BLIF N_214_0.BLIF N_199_1 -11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 -1- 1 --1 1 -.names N_242.BLIF ds_000_enable_0_un3_n +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names N_199_1.BLIF rst_dly_i_2__n.BLIF N_199 +.names un7_as_030.BLIF un7_as_030_i +0 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_145.BLIF N_145_i +0 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low 11 1 +.names N_147.BLIF N_147_i +0 1 +.names N_108.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_242.BLIF ds_000_enable_0_un1_n -11 1 -.names N_212_i.BLIF N_210_i.BLIF pos_clk_ipl_1_n -11 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names pos_clk_ipl_1_n.BLIF N_207_i.BLIF pos_clk_ipl_n +11 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_129_i.BLIF RST_c.BLIF N_258_i_1 +11 1 +.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +11 1 +.names N_254.BLIF as_000_dma_0_un3_n +0 1 +.names N_258_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +11 1 +.names N_3_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_254.BLIF as_000_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_264_i.BLIF N_259_i_1 +11 1 +.names N_8_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names N_259_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D +11 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_282_1 +11 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_65.BLIF ds_000_enable_0_un3_n +0 1 +.names N_282_1.BLIF cpu_est_i_3__n.BLIF N_282 +11 1 +.names N_22_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_65.BLIF ds_000_enable_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names N_292.BLIF cpu_est_3_.BLIF N_284_1 +11 1 +.names N_24_i.BLIF RST_c.BLIF N_31_0 +11 1 .names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n 11 1 -.names pos_clk_ipl_1_n.BLIF N_211_i.BLIF pos_clk_ipl_n +.names N_284_1.BLIF cpu_est_i_1__n.BLIF N_284 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names N_247_i.BLIF N_248_i.BLIF N_240_i_1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_288_1 11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names N_300.BLIF as_030_000_sync_0_un3_n +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names N_240_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names N_288_1.BLIF cpu_est_i_3__n.BLIF N_288 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names inst_AS_030_000_SYNC.BLIF N_300.BLIF as_030_000_sync_0_un1_n +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names N_246_i.BLIF RST_c.BLIF N_60_i_1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names pos_clk_un14_clk_000_ne_i_n.BLIF N_282_i.BLIF un5_e_0_1 11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_24 1- 1 -1 1 -.names inst_AS_030_D0.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names N_60_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +.names un5_e_0_1.BLIF N_284_i.BLIF un5_e_0 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +.names N_80.BLIF N_80_i 0 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names N_285_i.BLIF N_291_i.BLIF N_192_i_1 +11 1 +.names N_94.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names N_67.BLIF as_030_000_sync_0_un3_n +0 1 +.names N_192_i_1.BLIF N_292_i.BLIF N_192_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_94.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names inst_AS_030_000_SYNC.BLIF N_67.BLIF as_030_000_sync_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_208_i.BLIF N_206_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_80_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_22 +1- 1 +-1 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C -1 1 -.names AS_000_i.BLIF N_100_i.BLIF N_64_i_1 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +.names N_114_i.BLIF N_115_i.BLIF N_140_i_1 11 1 +.names N_94.BLIF a0_dma_0_un3_n +0 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names N_64_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF CYCLE_DMA_1_.D +.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D 11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names inst_A0_DMA.BLIF N_94.BLIF a0_dma_0_un1_n 11 1 -.names N_106.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names N_227_i.BLIF N_228_i.BLIF N_155_i_1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names N_116_i.BLIF N_117_i.BLIF N_154_i_1 +11 1 +.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 -1- 1 --1 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names N_155_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +.names N_154_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_134.BLIF cpu_est_0_3__un3_n -0 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names N_138.BLIF N_225_i.BLIF N_147_i_1 +.names N_118_i.BLIF N_265.BLIF N_152_i_1 11 1 -.names cpu_est_3_.BLIF N_134.BLIF cpu_est_0_3__un1_n -11 1 -.names N_160.BLIF a0_dma_0_un3_n +.names N_94.BLIF rw_000_dma_0_un3_n 0 1 -.names N_147_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names N_196_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names inst_RW_000_DMA.BLIF N_94.BLIF rw_000_dma_0_un1_n 11 1 -.names pos_clk_a0_dma_3_n.BLIF N_160.BLIF a0_dma_0_un1_n +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 -.names N_172.BLIF N_224_i.BLIF N_145_i_1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names N_119_i.BLIF N_269.BLIF N_150_i_1 11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +.names pos_clk_rw_000_dma_3_n.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_150_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names N_145_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D -11 1 -.names N_134.BLIF cpu_est_0_2__un3_n -0 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_22 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -.names N_138.BLIF N_223_i.BLIF N_139_i_1 +.names N_120_i.BLIF N_263.BLIF N_148_i_1 11 1 -.names cpu_est_2_.BLIF N_134.BLIF cpu_est_0_2__un1_n -11 1 -.names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_22_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names N_16_i.BLIF RST_c.BLIF N_44_0 -11 1 -.names N_314_1.BLIF N_314_2.BLIF N_314 -11 1 -.names N_134.BLIF cpu_est_0_1__un3_n +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_15_i.BLIF RST_c.BLIF N_45_0 -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 -.names N_134_i.BLIF N_348.BLIF N_318_1 -11 1 -.names cpu_est_1_.BLIF N_134.BLIF cpu_est_0_1__un1_n -11 1 .names vcc_n_n 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_318_2 +.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 .names gnd_n_n -.names N_318_1.BLIF N_318_2.BLIF N_318 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names N_171_i.BLIF N_263.BLIF N_144_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 .names A_DECODE_15_.BLIF a_decode_15__n 1 1 -.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D -1 1 -.names N_154_0.BLIF N_305_i.BLIF N_341_1 -11 1 -.names N_29_i.BLIF RST_c.BLIF N_33_0 +.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 +1- 1 +-1 1 .names A_DECODE_14_.BLIF a_decode_14__n 1 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_341_2 -11 1 -.names N_28_i.BLIF RST_c.BLIF N_32_0 +.names N_121_i.BLIF RW_000_i.BLIF N_255_0_1 11 1 +.names N_255.BLIF ds_000_dma_0_un3_n +0 1 .names A_DECODE_13_.BLIF a_decode_13__n 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C -1 1 -.names N_341_1.BLIF N_341_2.BLIF N_341 +.names N_255_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_255_0 11 1 -.names N_27_i.BLIF RST_c.BLIF N_31_0 +.names pos_clk_ds_000_dma_4_n.BLIF N_255.BLIF ds_000_dma_0_un1_n 11 1 .names A_DECODE_12_.BLIF a_decode_12__n 1 1 -.names N_167.BLIF N_284_i.BLIF N_151_i_1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_88_1 11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 .names A_DECODE_11_.BLIF a_decode_11__n 1 1 -.names N_151_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 +.names N_88_1.BLIF pos_clk_un14_clk_000_ne_n.BLIF N_88 11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 .names A_DECODE_10_.BLIF a_decode_10__n 1 1 -.names N_138.BLIF N_334_i.BLIF N_143_i_1 +.names N_62_i.BLIF N_64_i.BLIF N_142_i_1 11 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_122 11 1 .names A_DECODE_9_.BLIF a_decode_9__n 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -.names N_143_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D -11 1 -.names N_14_i.BLIF RST_c.BLIF N_46_0 +.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D 11 1 +.names RW_000_c.BLIF RW_000_i +0 1 .names A_DECODE_8_.BLIF a_decode_8__n 1 1 -.names N_166_i.BLIF N_278_i.BLIF N_141_i_1 -11 1 -.names N_19_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names A_DECODE_7_.BLIF a_decode_7__n -1 1 -.names N_141_i_1.BLIF N_279_i.BLIF SM_AMIGA_1_.D -11 1 -.names N_20_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names A_DECODE_6_.BLIF a_decode_6__n -1 1 -.names N_332_i.BLIF RW_000_i.BLIF N_237_0_1 -11 1 -.names N_21_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names A_DECODE_5_.BLIF a_decode_5__n -1 1 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 -.names N_237_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_237_0 +.names N_58_i.BLIF N_244_i.BLIF N_146_i_1 11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_123 +11 1 +.names A_DECODE_7_.BLIF a_decode_7__n +1 1 +.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 +.names A_DECODE_6_.BLIF a_decode_6__n +1 1 +.names N_78_i_0.BLIF N_79_i.BLIF N_234_i_1 +11 1 +.names cycle_dma_i_0__n.BLIF N_263.BLIF N_130 +11 1 +.names A_DECODE_5_.BLIF a_decode_5__n +1 1 +.names N_234_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +11 1 +.names AS_000_c.BLIF N_263_i.BLIF N_170 +11 1 .names A_DECODE_4_.BLIF a_decode_4__n 1 1 -.names N_357_4.BLIF N_357_3.BLIF N_357 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 -.names N_154.BLIF cpu_est_i_2__n.BLIF N_222 +.names N_122_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF pos_clk_ds_000_dma_4_0_n 11 1 .names A_DECODE_3_.BLIF a_decode_3__n 1 1 -.names clk_000_d_i_1__n.BLIF AS_030_000_SYNC_i.BLIF N_304_i_1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n 11 1 -.names N_153.BLIF cpu_est_2_.BLIF N_221 +.names N_123_i.BLIF N_124_i.BLIF AMIGA_BUS_DATA_DIR_c_0 11 1 .names A_DECODE_2_.BLIF a_decode_2__n 1 1 -.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 -1 1 -.names N_304_i_1.BLIF CLK_000_D_2_.BLIF N_304_i +.names N_264_i.BLIF RW_000_c.BLIF N_124_1 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n +11 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names N_124_1.BLIF nEXP_SPACE_i.BLIF N_124 +11 1 +.names BGACK_000_c.BLIF N_170_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names N_153.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_264_i +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +11 1 +.names N_153.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 +11 1 +.names CYCLE_DMA_0_.BLIF N_263_i.BLIF N_131 +11 1 +.names N_130_i.BLIF N_131_i.BLIF N_260_i_1 +11 1 +.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un3_n 0 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_219 -11 1 -.names N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 +.names CYCLE_DMA_0_.BLIF pos_clk_un21_bgack_030_int_i_0_x2.X1 1 1 -.names un21_fpu_cs_1.BLIF N_357.BLIF un21_fpu_cs +.names N_264_i.BLIF RST_c.BLIF N_260_i_2 11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +.names SIZE_DMA_1_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un1_n 11 1 -.names N_166_i.BLIF rst_dly_i_1__n.BLIF N_204 +.names N_260_i_1.BLIF N_260_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names un21_berr_1_0.BLIF N_357.BLIF un21_berr +.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names N_142.BLIF N_156_i.BLIF N_203 -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.X1 +.names CYCLE_DMA_1_.BLIF pos_clk_un21_bgack_030_int_i_0_x2.X2 1 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_266_1 +.names N_76_i.BLIF N_77_i.BLIF N_233_i_1 11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_266_2 -11 1 -.names N_134.BLIF rst_dly_i_2__n.BLIF N_201 -11 1 -.names CYCLE_DMA_1_.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.X2 -1 1 -.names N_266_1.BLIF N_266_2.BLIF N_266 -11 1 -.names N_142.BLIF N_343.BLIF N_200 -11 1 -.names AS_000_i.BLIF N_100_i.BLIF N_67_i_1 -11 1 -.names N_207_i.BLIF N_208_i.BLIF N_67_i_2 -11 1 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1 -1 1 -.names N_67_i_1.BLIF N_67_i_2.BLIF CYCLE_DMA_0_.D -11 1 -.names N_138_i.BLIF N_305_i.BLIF N_314_1 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_25_0.X2 -1 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_314_2 -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 -.names IPL_D0_2_.BLIF G_109.X1 +.names N_251_i.BLIF RST_c.BLIF N_233_i_2 +11 1 +.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un3_n +0 1 +.names N_233_i_1.BLIF N_233_i_2.BLIF RST_DLY_1_.D +11 1 +.names SIZE_DMA_0_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un1_n +11 1 +.names IPL_D0_0_.BLIF G_107.X1 1 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +.names N_247_i.BLIF N_248_i.BLIF N_232_i_1 11 1 -.names N_166_i.BLIF rst_dly_i_0__n.BLIF N_248 +.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n 11 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 +.names N_249_i.BLIF RST_c.BLIF N_232_i_2 11 1 -.names N_142.BLIF RST_DLY_0_.BLIF N_247 -11 1 -.names ipl_c_2__n.BLIF G_109.X2 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names ipl_c_0__n.BLIF G_107.X2 1 1 -.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +.names N_232_i_1.BLIF N_232_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_138_i.BLIF N_162.BLIF un1_DS_000_ENABLE_0_sqmuxa +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_80 11 1 -.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +.names N_210_i.BLIF N_239.BLIF N_247_1 11 1 -.names N_134_i.BLIF cpu_est_0_.BLIF N_233 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 -.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +.names N_247_1.BLIF rst_dly_i_2__n.BLIF N_247 11 1 -.names N_134.BLIF cpu_est_i_0__n.BLIF N_232 +.names N_94.BLIF RST_c.BLIF SIZE_DMA_3_sqmuxa 11 1 .names IPL_D0_1_.BLIF G_108.X1 1 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +.names N_210_i.BLIF rst_dly_i_0__n.BLIF N_77_1 11 1 -.names N_178.BLIF cpu_est_2_.BLIF N_231 +.names N_210_i.BLIF N_269_i.BLIF N_87 11 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +.names N_77_1.BLIF rst_dly_i_1__n.BLIF N_77 11 1 -.names N_184.BLIF cpu_est_i_2__n.BLIF N_229 +.names N_239_i.BLIF RST_DLY_2_.BLIF N_91 11 1 .names ipl_c_1__n.BLIF G_108.X2 1 1 -.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 +.names N_91.BLIF N_269_i.BLIF N_83_1 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +.names N_269.BLIF RST_c.BLIF N_92 11 1 -.names N_167.BLIF sm_amiga_i_5__n.BLIF N_226 +.names N_83_1.BLIF RST_c.BLIF N_83 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_357_1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_94 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names IPL_D0_0_.BLIF G_107.X1 +.names N_153_1.BLIF N_153_2.BLIF N_153_4 +11 1 +.names N_91_i.BLIF RST_c.BLIF N_210_i +11 1 +.names IPL_D0_2_.BLIF G_109.X1 1 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_357_2 +.names N_153_3.BLIF fc_c_0__n.BLIF N_153_5 11 1 -.names N_185.BLIF sm_amiga_i_4__n.BLIF N_225 +.names N_245_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n 11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_357_3 +.names N_153_4.BLIF N_153_5.BLIF N_153 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names ipl_c_0__n.BLIF G_107.X2 +.names N_246_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names ipl_c_2__n.BLIF G_109.X2 1 1 -.names N_357_1.BLIF N_357_2.BLIF N_357_4 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names N_180.BLIF sm_amiga_i_3__n.BLIF N_224 +.names N_87_i.BLIF RST_c.BLIF N_236_0 11 1 -.names N_44_0.BLIF inst_RW_000_INT.D -0 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_22.BLIF N_22_i -0 1 -.names N_169.BLIF sm_amiga_i_0__n.BLIF N_223 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 1 1 -.names N_38_0.BLIF inst_A0_DMA.D +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +11 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_239_i +11 1 +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_242_i +11 1 +.names N_131.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 +1 1 +.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +11 1 +.names N_58.BLIF SM_AMIGA_3_.BLIF N_163_0 +11 1 +.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names N_221_i.BLIF N_348_i.BLIF cpu_est_2_0_2__n +.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +11 1 +.names N_163.BLIF sm_amiga_i_2__n.BLIF N_171 11 1 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 -.names AS_000_i.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.BLIF pos_clk_un21_bgack_030_int_i_0_i_1_n +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 -.names N_219_i.BLIF N_220_i.BLIF cpu_est_2_0_1__n +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 -.names BGACK_030_INT_i.BLIF N_297_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names N_314_i.BLIF N_318_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un19_bgack_030_int_i_n 11 1 -.names pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_n +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names AS_030_D0_i.BLIF N_169.BLIF N_256_0 +.names BGACK_030_INT_i.BLIF N_242_i.BLIF N_245 11 1 -.names N_199_i.BLIF N_200_i.BLIF N_238_i_1 +.names N_240_0_1.BLIF N_89_i.BLIF N_240_0 11 1 -.names N_153_i.BLIF cpu_est_i_2__n.BLIF N_348 +.names BGACK_030_INT_i.BLIF N_242.BLIF N_246 11 1 -.names N_201_i.BLIF RST_c.BLIF N_238_i_2 +.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_156_i.BLIF RST_DLY_2_.BLIF N_343 +.names N_91.BLIF N_236.BLIF N_248 11 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index d2bdb56..5422309 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,112 +1,113 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Sep 14 23:54:26 2016 +#$ DATE Thu Oct 06 21:34:55 2016 #$ MODULE bus68030 #$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ -# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \ -# SIZE_0_ CLK_OSZI AHIGH_30_ CLK_DIV_OUT AHIGH_29_ CLK_EXP AHIGH_28_ FPU_CS AHIGH_27_ \ -# FPU_SENSE AHIGH_26_ DSACK1 AHIGH_25_ DTACK AHIGH_24_ AVEC A_DECODE_22_ E A_DECODE_21_ \ -# VPA A_DECODE_20_ VMA A_DECODE_19_ RST A_DECODE_18_ RESET A_DECODE_17_ RW A_DECODE_16_ \ -# AMIGA_ADDR_ENABLE A_DECODE_15_ AMIGA_BUS_DATA_DIR A_DECODE_14_ \ -# AMIGA_BUS_ENABLE_LOW A_DECODE_13_ AMIGA_BUS_ENABLE_HIGH A_DECODE_12_ CIIN \ -# A_DECODE_11_ A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ \ -# A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ \ -# IPL_0_ FC_0_ A_1_ -#$ NODES 602 N_130_i pos_clk_un6_bgack_000_0_n N_131_i DTACK_c_i CLK_030_H_i N_56_0 \ -# RW_000_i VPA_c_i a_i_1__n N_55_0 RESET_OUT_i N_6_i AS_030_i N_47_0 FPU_SENSE_i N_26_i \ -# inst_BGACK_030_INTreg sm_amiga_i_i_7__n N_34_0 vcc_n_n a_decode_i_16__n BG_030_c_i \ -# inst_VMA_INTreg AS_030_D0_i pos_clk_un6_bg_030_i_n gnd_n_n size_dma_i_0__n \ -# pos_clk_un9_bg_030_0_n un1_amiga_bus_enable_low size_dma_i_1__n N_25_i un6_as_030 \ -# a_decode_i_18__n N_35_0 un3_size a_decode_i_19__n N_24_i un4_size ahigh_i_30__n \ -# N_36_0 un1_LDS_000_INT ahigh_i_31__n N_17_i un1_UDS_000_INT ahigh_i_28__n N_43_0 \ -# un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_29__n N_4_i un1_DS_000_ENABLE_0_sqmuxa \ -# ahigh_i_26__n N_49_0 un4_as_000 ahigh_i_27__n N_3_i un10_ciin ahigh_i_24__n N_50_0 \ -# un21_fpu_cs ahigh_i_25__n N_215_i un21_berr N_210_i N_216_i un6_ds_030 N_211_i N_301_0 \ -# cpu_est_2_ N_212_i N_243_0 cpu_est_3_ N_266_i cpu_est_0_ un6_ds_030_i N_249_i \ -# cpu_est_1_ un4_as_000_i AMIGA_BUS_DATA_DIR_c_0 inst_AS_000_INT AS_000_INT_i N_268_i \ -# inst_AMIGA_BUS_ENABLE_DMA_LOW un6_as_030_i pos_clk_ds_000_dma_4_0_n \ -# inst_AS_030_D0 AS_030_c CLK_030_c_i inst_AS_030_000_SYNC N_236_0 \ -# inst_BGACK_030_INT_D AS_000_c un1_as_000_i inst_AS_000_DMA N_297_i inst_DS_000_DMA \ -# RW_000_c N_160_i CYCLE_DMA_0_ pos_clk_un21_bgack_030_int_i_0_i_n CYCLE_DMA_1_ \ -# N_100_i SIZE_DMA_0_ UDS_000_c N_186_0 SIZE_DMA_1_ N_183_0 inst_VPA_D LDS_000_c N_182_0 \ -# CLK_000_D_1_ N_181_0 inst_DTACK_D0 size_c_0__n N_228_i inst_RESET_OUT N_176_0 \ -# CLK_000_D_0_ size_c_1__n LDS_000_c_i inst_CLK_OUT_PRE_50 UDS_000_c_i \ -# inst_CLK_OUT_PRE_25 ahigh_c_24__n N_173_i inst_CLK_OUT_PRE_D N_304_i IPL_D0_0_ \ -# ahigh_c_25__n AS_030_000_SYNC_i IPL_D0_1_ N_157_i IPL_D0_2_ ahigh_c_26__n N_110_0 \ -# CLK_000_D_2_ RW_c_i pos_clk_un6_bg_030_n ahigh_c_27__n N_106_0 \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_284_i inst_DSACK1_INTreg ahigh_c_28__n \ -# pos_clk_ipl_n N_334_i inst_LDS_000_INT ahigh_c_29__n inst_DS_000_ENABLE N_278_i \ -# inst_UDS_000_INT ahigh_c_30__n N_279_i SM_AMIGA_6_ SM_AMIGA_4_ ahigh_c_31__n N_332_i \ -# SM_AMIGA_1_ N_237_0 SM_AMIGA_0_ un1_SM_AMIGA_0_sqmuxa_1_0 inst_RW_000_INT N_247_i \ -# inst_RW_000_DMA N_248_i RST_DLY_0_ RST_DLY_1_ N_246_i RST_DLY_2_ inst_A0_DMA \ -# pos_clk_a0_dma_3_n un10_ciin_i inst_CLK_030_H N_241_0 SM_AMIGA_5_ \ -# un1_DS_000_ENABLE_0_sqmuxa_i SM_AMIGA_3_ N_242_0 SM_AMIGA_2_ N_48_i N_227_i N_9 \ -# N_225_i N_224_i N_15 N_223_i N_16 N_22 N_218_i CLK_OUT_PRE_25_0 \ -# pos_clk_size_dma_6_0_1__n N_217_i pos_clk_size_dma_6_0_0__n N_213_i N_319_i N_300_0 \ -# N_15_i a_decode_c_16__n N_45_0 N_16_i a_decode_c_17__n N_44_0 N_22_i a_decode_c_18__n \ -# N_38_0 pos_clk_un21_bgack_030_int_i_0_i_1_n a_decode_c_19__n \ -# pos_clk_un21_bgack_030_int_i_0_i_2_n N_238_i_1 a_decode_c_20__n N_238_i_2 \ -# N_239_i_1 a_decode_c_21__n N_239_i_2 pos_clk_un10_sm_amiga_i_1_n a_decode_c_22__n \ -# un10_ciin_1 un10_ciin_2 a_decode_c_23__n un10_ciin_3 un10_ciin_4 a_c_0__n \ -# un10_ciin_5 un10_ciin_6 SM_AMIGA_i_7_ a_c_1__n un10_ciin_7 pos_clk_size_dma_6_0__n \ -# un10_ciin_8 pos_clk_size_dma_6_1__n nEXP_SPACE_c un10_ciin_9 G_107 un10_ciin_10 \ -# G_108 BERR_c un10_ciin_11 G_109 N_357_1 pos_clk_un21_bgack_030_int_i_0_n BG_030_c \ -# N_357_2 N_237 N_357_3 N_241 BG_000DFFreg N_357_4 N_242 N_304_i_1 un21_fpu_cs_1 N_283 \ -# BGACK_000_c un21_berr_1_0 N_294 N_266_1 N_300 CLK_030_c N_266_2 N_67_i_1 N_106 N_67_i_2 \ -# N_314_1 N_134 CLK_OSZI_c N_314_2 N_138 N_318_1 N_156 N_318_2 N_160 CLK_OUT_INTreg \ -# N_341_1 N_167 N_341_2 N_172 N_151_i_1 N_173 FPU_SENSE_c N_143_i_1 N_181 N_141_i_1 N_182 \ -# IPL_030DFF_0_reg N_237_0_1 N_183 N_240_i_1 N_191 IPL_030DFF_1_reg N_60_i_1 N_199 \ -# N_64_i_1 N_205 IPL_030DFF_2_reg N_155_i_1 N_209 N_147_i_1 N_319 ipl_c_0__n N_145_i_1 \ -# N_213 N_139_i_1 N_216 ipl_c_1__n pos_clk_un6_bg_030_1_n N_217 N_220_1 N_218 ipl_c_2__n \ -# N_216_1 N_220 N_205_1 N_223 N_199_1 N_224 DTACK_c pos_clk_ipl_1_n N_225 \ -# uds_000_int_0_un3_n N_227 uds_000_int_0_un1_n N_228 uds_000_int_0_un0_n N_246 VPA_c \ -# as_000_int_0_un3_n N_247 as_000_int_0_un1_n N_248 as_000_int_0_un0_n N_332 RST_c \ -# dsack1_int_0_un3_n N_278 dsack1_int_0_un1_n N_279 dsack1_int_0_un0_n N_334 RW_c \ -# vma_int_0_un3_n N_284 vma_int_0_un1_n N_343 fc_c_0__n vma_int_0_un0_n \ -# pos_clk_CYCLE_DMA_5_1_i_0_x2 lds_000_int_0_un3_n un21_berr_1 fc_c_1__n \ -# lds_000_int_0_un1_n N_357 lds_000_int_0_un0_n N_266 ipl_030_0_1__un3_n N_186 \ -# AMIGA_BUS_DATA_DIR_c ipl_030_0_1__un1_n pos_clk_un21_bgack_030_int_i_0_o2_2_x2 \ -# ipl_030_0_1__un0_n N_297 ipl_030_0_0__un3_n N_236 ipl_030_0_0__un1_n \ -# pos_clk_ds_000_dma_4_n ipl_030_0_0__un0_n N_268 UDS_000_INT_i cpu_est_0_3__un3_n \ -# N_249 un1_UDS_000_INT_0 cpu_est_0_3__un1_n N_243 LDS_000_INT_i cpu_est_0_3__un0_n \ -# N_215 un1_LDS_000_INT_0 cpu_est_0_2__un3_n N_130 N_23_i cpu_est_0_2__un1_n N_131 \ -# N_37_0 cpu_est_0_2__un0_n N_3 N_21_i cpu_est_0_1__un3_n N_4 N_39_0 cpu_est_0_1__un1_n \ -# N_17 N_20_i cpu_est_0_1__un0_n N_24 N_40_0 ipl_030_0_2__un3_n N_25 N_19_i \ -# ipl_030_0_2__un1_n pos_clk_un9_bg_030_n N_41_0 ipl_030_0_2__un0_n N_6 N_14_i \ -# amiga_bus_enable_dma_low_0_un3_n pos_clk_un6_bgack_000_n N_46_0 \ -# amiga_bus_enable_dma_low_0_un1_n N_26 ipl_c_i_0__n \ -# amiga_bus_enable_dma_low_0_un0_n N_208 N_52_0 rw_000_dma_0_un3_n N_207 ipl_c_i_1__n \ -# rw_000_dma_0_un1_n N_349 N_53_0 rw_000_dma_0_un0_n N_314 ipl_c_i_2__n \ -# as_000_dma_0_un3_n N_318 N_54_0 as_000_dma_0_un1_n N_348 N_27_i as_000_dma_0_un0_n \ -# N_201 N_31_0 ds_000_dma_0_un3_n N_200 N_28_i ds_000_dma_0_un1_n N_203 N_32_0 \ -# ds_000_dma_0_un0_n N_204 N_29_i bgack_030_int_0_un3_n N_185 N_33_0 \ -# bgack_030_int_0_un1_n N_184 a_c_i_0__n bgack_030_int_0_un0_n N_180 size_c_i_1__n \ -# bg_000_0_un3_n N_179 pos_clk_un10_sm_amiga_i_n bg_000_0_un1_n N_178 N_256_0 \ -# bg_000_0_un0_n N_171 N_318_i amiga_bus_enable_dma_high_0_un3_n N_341 N_314_i \ -# amiga_bus_enable_dma_high_0_un1_n N_342 pos_clk_un9_clk_000_pe_0_n \ -# amiga_bus_enable_dma_high_0_un0_n N_169 N_219_i \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n N_154 N_220_i \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n N_165 cpu_est_2_0_1__n \ -# un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n N_162 N_221_i \ -# size_dma_0_0__un3_n N_299 N_348_i size_dma_0_0__un1_n N_153 cpu_est_2_0_2__n \ -# size_dma_0_0__un0_n N_142 N_222_i size_dma_0_1__un3_n N_298 N_196_i \ -# size_dma_0_1__un1_n N_80 N_226_i size_dma_0_1__un0_n N_232 ds_000_enable_0_un3_n \ -# N_233 N_231_i ds_000_enable_0_un1_n N_229 N_229_i ds_000_enable_0_un0_n N_231 N_302_i \ -# as_030_000_sync_0_un3_n N_226 N_233_i as_030_000_sync_0_un1_n N_221 N_232_i \ -# as_030_000_sync_0_un0_n N_222 rw_000_int_0_un3_n cpu_est_2_2__n N_80_0 \ -# rw_000_int_0_un1_n cpu_est_2_1__n N_343_i rw_000_int_0_un0_n N_219 N_214_0 \ -# a0_dma_0_un3_n pos_clk_un9_clk_000_pe_n N_166_i a0_dma_0_un1_n N_256 N_134_i \ -# a0_dma_0_un0_n N_29 N_298_i a_decode_15__n N_28 N_142_0 N_27 N_153_i a_decode_14__n \ -# N_14 N_154_0 N_19 N_156_i a_decode_13__n N_20 N_305_i N_21 N_299_i a_decode_12__n N_23 \ -# N_162_0 un1_amiga_bus_enable_low_i N_165_0 a_decode_11__n un21_fpu_cs_i N_169_i \ -# cpu_est_i_1__n VMA_INT_i a_decode_10__n rst_dly_i_2__n N_341_i rst_dly_i_1__n \ -# N_342_i a_decode_9__n cpu_est_i_0__n N_171_i cpu_est_i_2__n N_172_i a_decode_8__n \ -# sm_amiga_i_0__n N_178_0 sm_amiga_i_3__n N_179_0 a_decode_7__n sm_amiga_i_4__n \ -# N_180_0 sm_amiga_i_5__n N_184_0 a_decode_6__n rst_dly_i_0__n N_185_0 sm_amiga_i_2__n \ -# N_203_i a_decode_5__n sm_amiga_i_1__n N_204_i VPA_D_i N_205_i a_decode_4__n \ -# clk_000_d_i_1__n cpu_est_i_3__n N_200_i a_decode_3__n sm_amiga_i_6__n N_199_i \ -# clk_000_d_i_0__n N_201_i a_decode_2__n BGACK_030_INT_i AS_000_i AS_000_DMA_i N_208_i \ -# nEXP_SPACE_i N_207_i cycle_dma_i_0__n N_167_i DS_000_DMA_i N_138_i \ -# AMIGA_BUS_ENABLE_DMA_LOW_i N_349_i +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 SIZE_0_ \ +# CLK_000 AHIGH_30_ CLK_OSZI AHIGH_29_ CLK_DIV_OUT AHIGH_28_ CLK_EXP AHIGH_27_ FPU_CS \ +# AHIGH_26_ FPU_SENSE AHIGH_25_ DSACK1 AHIGH_24_ DTACK A_DECODE_22_ AVEC A_DECODE_21_ E \ +# A_DECODE_20_ VPA A_DECODE_19_ VMA A_DECODE_18_ RST A_DECODE_17_ RESET A_DECODE_16_ RW \ +# A_DECODE_15_ AMIGA_ADDR_ENABLE A_DECODE_14_ AMIGA_BUS_DATA_DIR A_DECODE_13_ \ +# AMIGA_BUS_ENABLE_LOW A_DECODE_12_ AMIGA_BUS_ENABLE_HIGH A_DECODE_11_ CIIN \ +# A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ \ +# A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 601 nEXP_SPACE_i N_171_i CLK_030_H_i FPU_SENSE_i N_121_i AS_030_i N_255_0 \ +# AS_000_DMA_i un1_SM_AMIGA_0_sqmuxa_1_0 AS_000_i N_48_0 AS_000_INT_i N_125_i \ +# DSACK1_INT_i N_126_i inst_BGACK_030_INTreg clk_000_d_i_0__n vcc_n_n \ +# clk_000_d_i_3__n N_127_i un5_e clk_000_d_i_1__n N_128_i inst_VMA_INTreg \ +# cpu_est_i_2__n gnd_n_n cpu_est_i_3__n RW_c_i un1_amiga_bus_enable_low \ +# a_decode_i_16__n pos_clk_rw_000_int_5_0_n un7_as_030 a_decode_i_18__n N_129_i \ +# un1_UDS_000_INT a_decode_i_19__n un1_LDS_000_INT ahigh_i_30__n \ +# un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_31__n un10_ciin_i un1_DS_000_ENABLE_0_sqmuxa \ +# ahigh_i_28__n N_261_0 un10_ciin ahigh_i_29__n N_65_0 un21_fpu_cs ahigh_i_26__n \ +# N_134_i un21_berr ahigh_i_27__n N_153_i un6_ds_030 ahigh_i_24__n N_67_0 cpu_est_3_ \ +# ahigh_i_25__n un2_as_030_i cpu_est_0_ N_206_i N_263_i cpu_est_1_ N_207_i N_265_i \ +# cpu_est_2_ N_208_i AS_030_000_SYNC_i inst_AMIGA_BUS_ENABLE_DMA_LOW N_84_0 \ +# inst_AS_030_D0 clk_000_d_i_2__n inst_AS_030_000_SYNC N_81_i N_85_i \ +# inst_BGACK_030_INT_D un6_ds_030_i N_141_i inst_AS_000_DMA DS_000_DMA_i \ +# un1_DS_000_ENABLE_0_sqmuxa_i inst_DS_000_DMA N_147_i \ +# pos_clk_un21_bgack_030_int_i_0_i_n CYCLE_DMA_0_ N_145_i N_269_i CYCLE_DMA_1_ \ +# un7_as_030_i N_90_i inst_VPA_D RESET_OUT_i N_270_i CLK_000_D_2_ AS_030_c N_271_0 \ +# CLK_000_D_3_ N_96_0 inst_DTACK_D0 AS_000_c N_97_0 inst_RESET_OUT N_98_0 CLK_000_D_1_ \ +# RW_000_c N_282_i CLK_000_D_0_ N_284_i inst_CLK_OUT_PRE_50 \ +# pos_clk_un14_clk_000_ne_i_n inst_CLK_OUT_PRE_D UDS_000_c un5_e_0 IPL_D0_0_ N_285_i \ +# IPL_D0_1_ LDS_000_c N_291_i IPL_D0_2_ N_292_i CLK_000_D_4_ size_c_0__n N_192_i \ +# pos_clk_un6_bg_030_n N_17_i inst_AMIGA_BUS_ENABLE_DMA_HIGH size_c_1__n \ +# cpu_est_2_0_2__n pos_clk_ipl_n N_286_i SM_AMIGA_1_ ahigh_c_24__n N_288_i \ +# AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa cpu_est_2_0_1__n inst_UDS_000_INT \ +# ahigh_c_25__n N_289_i inst_DS_000_ENABLE N_290_i inst_LDS_000_INT ahigh_c_26__n \ +# pos_clk_un9_clk_000_pe_0_n SM_AMIGA_6_ N_280_i SM_AMIGA_4_ ahigh_c_27__n \ +# pos_clk_un10_sm_amiga_i_n SM_AMIGA_0_ a_c_i_0__n SIZE_DMA_0_ ahigh_c_28__n \ +# size_c_i_1__n SIZE_DMA_1_ N_27_i inst_RW_000_INT ahigh_c_29__n N_30_0 \ +# inst_RW_000_DMA N_26_i RST_DLY_0_ ahigh_c_30__n N_29_0 RST_DLY_1_ N_25_i RST_DLY_2_ \ +# ahigh_c_31__n N_28_0 inst_A0_DMA ipl_c_i_2__n pos_clk_un9_clk_000_pe_n N_51_0 \ +# inst_CLK_030_H ipl_c_i_1__n pos_clk_rw_000_int_5_n N_50_0 inst_DSACK1_INT \ +# ipl_c_i_0__n inst_AS_000_INT N_49_0 SM_AMIGA_5_ N_4_i SM_AMIGA_3_ N_44_0 SM_AMIGA_2_ \ +# N_14_i N_4 N_41_0 N_15_i N_40_0 N_9 N_16_i N_39_0 N_18_i N_37_0 N_14 N_21_i N_15 N_34_0 N_16 \ +# N_23_i N_18 N_32_0 N_21 LDS_000_INT_i N_23 un1_LDS_000_INT_0 N_25 UDS_000_INT_i N_26 \ +# un1_UDS_000_INT_0 N_27 N_96_0_1 N_96_0_2 N_96_0_3 \ +# pos_clk_un21_bgack_030_int_i_0_i_1_n N_84_0_1 a_decode_c_16__n N_84_0_2 N_240_0_1 \ +# a_decode_c_17__n pos_clk_un10_sm_amiga_i_1_n N_289_1 a_decode_c_18__n N_289_2 \ +# N_290_1 a_decode_c_19__n N_290_2 pos_clk_un14_clk_000_ne_1_n a_decode_c_20__n \ +# pos_clk_un14_clk_000_ne_2_n N_153_1 a_decode_c_21__n N_153_2 N_153_3 \ +# a_decode_c_22__n N_153_4 N_153_5 a_decode_c_23__n un10_ciin_1 un10_ciin_2 a_c_0__n \ +# un10_ciin_3 un10_ciin_4 a_c_1__n un10_ciin_5 un10_ciin_6 SM_AMIGA_i_7_ nEXP_SPACE_c \ +# un10_ciin_7 cpu_est_2_1__n un10_ciin_8 cpu_est_2_2__n BERR_c un10_ciin_9 G_107 \ +# un10_ciin_10 G_108 BG_030_c un10_ciin_11 G_109 N_260_i_1 \ +# pos_clk_un21_bgack_030_int_i_0_n BG_000DFFreg N_260_i_2 N_81 N_233_i_1 N_94 \ +# N_233_i_2 N_254 BGACK_000_c N_232_i_1 N_255 N_232_i_2 N_261 CLK_030_c N_247_1 N_65 \ +# N_77_1 N_67 N_83_1 N_269 N_88_1 N_108 CLK_OSZI_c N_142_i_1 N_135 N_146_i_1 N_136 \ +# N_234_i_1 N_145 CLK_OUT_INTreg pos_clk_un6_bg_030_1_n N_278 N_124_1 N_147 un21_berr_1 \ +# N_58 FPU_SENSE_c un21_fpu_cs_1 N_110 N_140_i_1 N_239 IPL_030DFF_0_reg N_154_i_1 N_90 \ +# N_152_i_1 N_265 IPL_030DFF_1_reg N_150_i_1 pos_clk_CYCLE_DMA_5_1_i_x2 N_148_i_1 \ +# pos_clk_un21_bgack_030_int_i_0_x2 IPL_030DFF_2_reg N_144_i_1 \ +# pos_clk_un19_bgack_030_int_n N_255_0_1 N_280 ipl_c_0__n N_258_i_1 N_263 N_259_i_1 \ +# N_247 ipl_c_1__n N_282_1 N_77 N_284_1 N_289 ipl_c_2__n N_288_1 N_291 un5_e_0_1 N_290 \ +# N_192_i_1 N_286 DTACK_c pos_clk_ipl_1_n N_288 bg_000_0_un3_n N_285 bg_000_0_un1_n N_17 \ +# bg_000_0_un0_n N_292 VPA_c amiga_bus_enable_dma_low_0_un3_n \ +# pos_clk_un14_clk_000_ne_n amiga_bus_enable_dma_low_0_un1_n N_282 \ +# amiga_bus_enable_dma_low_0_un0_n N_284 RST_c a0_dma_0_un3_n N_98 a0_dma_0_un1_n N_97 \ +# a0_dma_0_un0_n N_84 RW_c rw_000_dma_0_un3_n N_96 rw_000_dma_0_un1_n N_271 fc_c_0__n \ +# rw_000_dma_0_un0_n N_117 bgack_030_int_0_un3_n N_141 fc_c_1__n \ +# bgack_030_int_0_un1_n N_134 bgack_030_int_0_un0_n N_153 ds_000_dma_0_un3_n N_129 \ +# AMIGA_BUS_DATA_DIR_c ds_000_dma_0_un1_n N_127 ds_000_dma_0_un0_n N_128 \ +# size_dma_0_1__un3_n N_125 size_dma_0_1__un1_n N_126 size_dma_0_1__un0_n N_124 \ +# BG_030_c_i size_dma_0_0__un3_n N_121 pos_clk_un6_bg_030_i_n size_dma_0_0__un1_n \ +# N_171 pos_clk_un9_bg_030_0_n size_dma_0_0__un0_n N_120 N_24_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_119 N_31_0 \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_118 N_22_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_116 N_33_0 cpu_est_0_1__un3_n N_114 \ +# N_20_i cpu_est_0_1__un1_n N_115 N_35_0 cpu_est_0_1__un0_n N_243 N_19_i \ +# cpu_est_0_2__un3_n N_240 N_36_0 cpu_est_0_2__un1_n N_88 N_8_i cpu_est_0_2__un0_n N_89 \ +# N_42_0 cpu_est_0_3__un3_n N_82 N_3_i cpu_est_0_3__un1_n N_83 N_45_0 \ +# cpu_est_0_3__un0_n N_78 VPA_c_i ipl_030_0_0__un3_n N_79 N_52_0 ipl_030_0_0__un1_n \ +# N_91 DTACK_c_i ipl_030_0_0__un0_n N_244 N_53_0 ipl_030_0_1__un3_n N_62 \ +# ipl_030_0_1__un1_n N_64 N_249_i ipl_030_0_1__un0_n N_59 N_248_i ipl_030_0_2__un3_n \ +# N_61 N_247_i ipl_030_0_2__un1_n N_163 ipl_030_0_2__un0_n N_245 N_77_i \ +# uds_000_int_0_un3_n N_242 N_251_i uds_000_int_0_un1_n N_246 N_76_i \ +# uds_000_int_0_un0_n N_248 amiga_bus_enable_dma_high_0_un3_n N_236 N_131_i \ +# amiga_bus_enable_dma_high_0_un1_n N_249 N_130_i amiga_bus_enable_dma_high_0_un0_n \ +# N_92 N_264_i as_000_dma_0_un3_n N_251 N_170_i as_000_dma_0_un1_n N_76 \ +# pos_clk_un6_bgack_000_0_n as_000_dma_0_un0_n N_80 pos_clk_rw_000_dma_3_0_n \ +# ds_000_enable_0_un3_n pos_clk_a0_dma_3_n N_123_i ds_000_enable_0_un1_n \ +# SIZE_DMA_3_sqmuxa N_124_i ds_000_enable_0_un0_n N_87 AMIGA_BUS_DATA_DIR_c_0 \ +# lds_000_int_0_un3_n pos_clk_size_dma_6_1__n N_122_i lds_000_int_0_un1_n \ +# pos_clk_size_dma_6_0__n pos_clk_ds_000_dma_4_0_n lds_000_int_0_un0_n N_170 N_242_i \ +# as_030_000_sync_0_un3_n N_122 N_239_i as_030_000_sync_0_un1_n N_123 N_87_i \ +# as_030_000_sync_0_un0_n N_130 N_236_0 rw_000_int_0_un3_n pos_clk_ds_000_dma_4_n \ +# N_246_i rw_000_int_0_un1_n pos_clk_rw_000_dma_3_n pos_clk_size_dma_6_0_0__n \ +# rw_000_int_0_un0_n pos_clk_un6_bgack_000_n N_245_i vma_int_0_un3_n N_131 \ +# pos_clk_size_dma_6_0_1__n vma_int_0_un1_n N_3 N_91_i vma_int_0_un0_n N_8 N_210_i \ +# a_decode_15__n N_19 pos_clk_un19_bgack_030_int_i_n N_20 N_163_0 a_decode_14__n N_22 \ +# N_59_i N_24 N_61_i a_decode_13__n pos_clk_un9_bg_030_n un1_amiga_bus_enable_low_i \ +# N_62_i a_decode_12__n un21_fpu_cs_i N_64_i BGACK_030_INT_i a_decode_11__n \ +# AMIGA_BUS_ENABLE_DMA_LOW_i N_244_i N_80_i a_decode_10__n cycle_dma_i_0__n N_78_i_0 \ +# RW_000_i N_79_i a_decode_9__n rst_dly_i_0__n rst_dly_i_1__n N_82_i a_decode_8__n \ +# rst_dly_i_2__n N_83_i LDS_000_i N_55_0 a_decode_7__n UDS_000_i N_88_i sm_amiga_i_2__n \ +# N_89_i a_decode_6__n N_58_i N_240_0 sm_amiga_i_3__n N_243_0 a_decode_5__n \ +# cpu_est_i_1__n CLK_030_c_i cpu_est_i_0__n N_254_0 a_decode_4__n sm_amiga_i_1__n \ +# N_114_i N_110_i N_115_i a_decode_3__n a_i_1__n VMA_INT_i N_116_i a_decode_2__n VPA_D_i \ +# N_117_i DTACK_D0_i AS_030_D0_i N_118_i sm_amiga_i_0__n sm_amiga_i_i_7__n N_119_i \ +# sm_amiga_i_6__n sm_amiga_i_5__n N_120_i sm_amiga_i_4__n .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -119,155 +120,157 @@ A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ -AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_130_i.BLIF \ -pos_clk_un6_bgack_000_0_n.BLIF N_131_i.BLIF DTACK_c_i.BLIF CLK_030_H_i.BLIF \ -N_56_0.BLIF RW_000_i.BLIF VPA_c_i.BLIF a_i_1__n.BLIF N_55_0.BLIF \ -RESET_OUT_i.BLIF N_6_i.BLIF AS_030_i.BLIF N_47_0.BLIF FPU_SENSE_i.BLIF \ -N_26_i.BLIF inst_BGACK_030_INTreg.BLIF sm_amiga_i_i_7__n.BLIF N_34_0.BLIF \ -vcc_n_n.BLIF a_decode_i_16__n.BLIF BG_030_c_i.BLIF inst_VMA_INTreg.BLIF \ -AS_030_D0_i.BLIF pos_clk_un6_bg_030_i_n.BLIF gnd_n_n.BLIF size_dma_i_0__n.BLIF \ -pos_clk_un9_bg_030_0_n.BLIF un1_amiga_bus_enable_low.BLIF size_dma_i_1__n.BLIF \ -N_25_i.BLIF un6_as_030.BLIF a_decode_i_18__n.BLIF N_35_0.BLIF un3_size.BLIF \ -a_decode_i_19__n.BLIF N_24_i.BLIF un4_size.BLIF ahigh_i_30__n.BLIF N_36_0.BLIF \ -un1_LDS_000_INT.BLIF ahigh_i_31__n.BLIF N_17_i.BLIF un1_UDS_000_INT.BLIF \ -ahigh_i_28__n.BLIF N_43_0.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF ahigh_i_29__n.BLIF \ -N_4_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF ahigh_i_26__n.BLIF N_49_0.BLIF \ -un4_as_000.BLIF ahigh_i_27__n.BLIF N_3_i.BLIF un10_ciin.BLIF \ -ahigh_i_24__n.BLIF N_50_0.BLIF un21_fpu_cs.BLIF ahigh_i_25__n.BLIF \ -N_215_i.BLIF un21_berr.BLIF N_210_i.BLIF N_216_i.BLIF un6_ds_030.BLIF \ -N_211_i.BLIF N_301_0.BLIF cpu_est_2_.BLIF N_212_i.BLIF N_243_0.BLIF \ -cpu_est_3_.BLIF N_266_i.BLIF cpu_est_0_.BLIF un6_ds_030_i.BLIF N_249_i.BLIF \ -cpu_est_1_.BLIF un4_as_000_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ -inst_AS_000_INT.BLIF AS_000_INT_i.BLIF N_268_i.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un6_as_030_i.BLIF \ -pos_clk_ds_000_dma_4_0_n.BLIF inst_AS_030_D0.BLIF AS_030_c.BLIF \ -CLK_030_c_i.BLIF inst_AS_030_000_SYNC.BLIF N_236_0.BLIF \ -inst_BGACK_030_INT_D.BLIF AS_000_c.BLIF un1_as_000_i.BLIF inst_AS_000_DMA.BLIF \ -N_297_i.BLIF inst_DS_000_DMA.BLIF RW_000_c.BLIF N_160_i.BLIF CYCLE_DMA_0_.BLIF \ -pos_clk_un21_bgack_030_int_i_0_i_n.BLIF CYCLE_DMA_1_.BLIF N_100_i.BLIF \ -SIZE_DMA_0_.BLIF UDS_000_c.BLIF N_186_0.BLIF SIZE_DMA_1_.BLIF N_183_0.BLIF \ -inst_VPA_D.BLIF LDS_000_c.BLIF N_182_0.BLIF CLK_000_D_1_.BLIF N_181_0.BLIF \ -inst_DTACK_D0.BLIF size_c_0__n.BLIF N_228_i.BLIF inst_RESET_OUT.BLIF \ -N_176_0.BLIF CLK_000_D_0_.BLIF size_c_1__n.BLIF LDS_000_c_i.BLIF \ -inst_CLK_OUT_PRE_50.BLIF UDS_000_c_i.BLIF inst_CLK_OUT_PRE_25.BLIF \ -ahigh_c_24__n.BLIF N_173_i.BLIF inst_CLK_OUT_PRE_D.BLIF N_304_i.BLIF \ -IPL_D0_0_.BLIF ahigh_c_25__n.BLIF AS_030_000_SYNC_i.BLIF IPL_D0_1_.BLIF \ -N_157_i.BLIF IPL_D0_2_.BLIF ahigh_c_26__n.BLIF N_110_0.BLIF CLK_000_D_2_.BLIF \ -RW_c_i.BLIF pos_clk_un6_bg_030_n.BLIF ahigh_c_27__n.BLIF N_106_0.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_284_i.BLIF inst_DSACK1_INTreg.BLIF \ -ahigh_c_28__n.BLIF pos_clk_ipl_n.BLIF N_334_i.BLIF inst_LDS_000_INT.BLIF \ -ahigh_c_29__n.BLIF inst_DS_000_ENABLE.BLIF N_278_i.BLIF inst_UDS_000_INT.BLIF \ -ahigh_c_30__n.BLIF N_279_i.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF \ -ahigh_c_31__n.BLIF N_332_i.BLIF SM_AMIGA_1_.BLIF N_237_0.BLIF SM_AMIGA_0_.BLIF \ -un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_RW_000_INT.BLIF N_247_i.BLIF \ -inst_RW_000_DMA.BLIF N_248_i.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_246_i.BLIF \ -RST_DLY_2_.BLIF inst_A0_DMA.BLIF pos_clk_a0_dma_3_n.BLIF un10_ciin_i.BLIF \ -inst_CLK_030_H.BLIF N_241_0.BLIF SM_AMIGA_5_.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_3_.BLIF N_242_0.BLIF \ -SM_AMIGA_2_.BLIF N_48_i.BLIF N_227_i.BLIF N_9.BLIF N_225_i.BLIF N_224_i.BLIF \ -N_15.BLIF N_223_i.BLIF N_16.BLIF N_22.BLIF N_218_i.BLIF CLK_OUT_PRE_25_0.BLIF \ -pos_clk_size_dma_6_0_1__n.BLIF N_217_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ -N_213_i.BLIF N_319_i.BLIF N_300_0.BLIF N_15_i.BLIF a_decode_c_16__n.BLIF \ -N_45_0.BLIF N_16_i.BLIF a_decode_c_17__n.BLIF N_44_0.BLIF N_22_i.BLIF \ -a_decode_c_18__n.BLIF N_38_0.BLIF pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ -a_decode_c_19__n.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n.BLIF N_238_i_1.BLIF \ -a_decode_c_20__n.BLIF N_238_i_2.BLIF N_239_i_1.BLIF a_decode_c_21__n.BLIF \ -N_239_i_2.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF a_decode_c_22__n.BLIF \ -un10_ciin_1.BLIF un10_ciin_2.BLIF a_decode_c_23__n.BLIF un10_ciin_3.BLIF \ -un10_ciin_4.BLIF a_c_0__n.BLIF un10_ciin_5.BLIF un10_ciin_6.BLIF \ -SM_AMIGA_i_7_.BLIF a_c_1__n.BLIF un10_ciin_7.BLIF pos_clk_size_dma_6_0__n.BLIF \ -un10_ciin_8.BLIF pos_clk_size_dma_6_1__n.BLIF nEXP_SPACE_c.BLIF \ -un10_ciin_9.BLIF G_107.BLIF un10_ciin_10.BLIF G_108.BLIF BERR_c.BLIF \ -un10_ciin_11.BLIF G_109.BLIF N_357_1.BLIF \ -pos_clk_un21_bgack_030_int_i_0_n.BLIF BG_030_c.BLIF N_357_2.BLIF N_237.BLIF \ -N_357_3.BLIF N_241.BLIF BG_000DFFreg.BLIF N_357_4.BLIF N_242.BLIF \ -N_304_i_1.BLIF un21_fpu_cs_1.BLIF N_283.BLIF BGACK_000_c.BLIF \ -un21_berr_1_0.BLIF N_294.BLIF N_266_1.BLIF N_300.BLIF CLK_030_c.BLIF \ -N_266_2.BLIF N_67_i_1.BLIF N_106.BLIF N_67_i_2.BLIF N_314_1.BLIF N_134.BLIF \ -CLK_OSZI_c.BLIF N_314_2.BLIF N_138.BLIF N_318_1.BLIF N_156.BLIF N_318_2.BLIF \ -N_160.BLIF CLK_OUT_INTreg.BLIF N_341_1.BLIF N_167.BLIF N_341_2.BLIF N_172.BLIF \ -N_151_i_1.BLIF N_173.BLIF FPU_SENSE_c.BLIF N_143_i_1.BLIF N_181.BLIF \ -N_141_i_1.BLIF N_182.BLIF IPL_030DFF_0_reg.BLIF N_237_0_1.BLIF N_183.BLIF \ -N_240_i_1.BLIF N_191.BLIF IPL_030DFF_1_reg.BLIF N_60_i_1.BLIF N_199.BLIF \ -N_64_i_1.BLIF N_205.BLIF IPL_030DFF_2_reg.BLIF N_155_i_1.BLIF N_209.BLIF \ -N_147_i_1.BLIF N_319.BLIF ipl_c_0__n.BLIF N_145_i_1.BLIF N_213.BLIF \ -N_139_i_1.BLIF N_216.BLIF ipl_c_1__n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ -N_217.BLIF N_220_1.BLIF N_218.BLIF ipl_c_2__n.BLIF N_216_1.BLIF N_220.BLIF \ -N_205_1.BLIF N_223.BLIF N_199_1.BLIF N_224.BLIF DTACK_c.BLIF \ -pos_clk_ipl_1_n.BLIF N_225.BLIF uds_000_int_0_un3_n.BLIF N_227.BLIF \ -uds_000_int_0_un1_n.BLIF N_228.BLIF uds_000_int_0_un0_n.BLIF N_246.BLIF \ -VPA_c.BLIF as_000_int_0_un3_n.BLIF N_247.BLIF as_000_int_0_un1_n.BLIF \ -N_248.BLIF as_000_int_0_un0_n.BLIF N_332.BLIF RST_c.BLIF \ -dsack1_int_0_un3_n.BLIF N_278.BLIF dsack1_int_0_un1_n.BLIF N_279.BLIF \ -dsack1_int_0_un0_n.BLIF N_334.BLIF RW_c.BLIF vma_int_0_un3_n.BLIF N_284.BLIF \ -vma_int_0_un1_n.BLIF N_343.BLIF fc_c_0__n.BLIF vma_int_0_un0_n.BLIF \ -pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF lds_000_int_0_un3_n.BLIF un21_berr_1.BLIF \ -fc_c_1__n.BLIF lds_000_int_0_un1_n.BLIF N_357.BLIF lds_000_int_0_un0_n.BLIF \ -N_266.BLIF ipl_030_0_1__un3_n.BLIF N_186.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -ipl_030_0_1__un1_n.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.BLIF \ -ipl_030_0_1__un0_n.BLIF N_297.BLIF ipl_030_0_0__un3_n.BLIF N_236.BLIF \ -ipl_030_0_0__un1_n.BLIF pos_clk_ds_000_dma_4_n.BLIF ipl_030_0_0__un0_n.BLIF \ -N_268.BLIF UDS_000_INT_i.BLIF cpu_est_0_3__un3_n.BLIF N_249.BLIF \ -un1_UDS_000_INT_0.BLIF cpu_est_0_3__un1_n.BLIF N_243.BLIF LDS_000_INT_i.BLIF \ -cpu_est_0_3__un0_n.BLIF N_215.BLIF un1_LDS_000_INT_0.BLIF \ -cpu_est_0_2__un3_n.BLIF N_130.BLIF N_23_i.BLIF cpu_est_0_2__un1_n.BLIF \ -N_131.BLIF N_37_0.BLIF cpu_est_0_2__un0_n.BLIF N_3.BLIF N_21_i.BLIF \ -cpu_est_0_1__un3_n.BLIF N_4.BLIF N_39_0.BLIF cpu_est_0_1__un1_n.BLIF N_17.BLIF \ -N_20_i.BLIF cpu_est_0_1__un0_n.BLIF N_24.BLIF N_40_0.BLIF \ -ipl_030_0_2__un3_n.BLIF N_25.BLIF N_19_i.BLIF ipl_030_0_2__un1_n.BLIF \ -pos_clk_un9_bg_030_n.BLIF N_41_0.BLIF ipl_030_0_2__un0_n.BLIF N_6.BLIF \ -N_14_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ -N_46_0.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_26.BLIF ipl_c_i_0__n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_208.BLIF N_52_0.BLIF \ -rw_000_dma_0_un3_n.BLIF N_207.BLIF ipl_c_i_1__n.BLIF rw_000_dma_0_un1_n.BLIF \ -N_349.BLIF N_53_0.BLIF rw_000_dma_0_un0_n.BLIF N_314.BLIF ipl_c_i_2__n.BLIF \ -as_000_dma_0_un3_n.BLIF N_318.BLIF N_54_0.BLIF as_000_dma_0_un1_n.BLIF \ -N_348.BLIF N_27_i.BLIF as_000_dma_0_un0_n.BLIF N_201.BLIF N_31_0.BLIF \ -ds_000_dma_0_un3_n.BLIF N_200.BLIF N_28_i.BLIF ds_000_dma_0_un1_n.BLIF \ -N_203.BLIF N_32_0.BLIF ds_000_dma_0_un0_n.BLIF N_204.BLIF N_29_i.BLIF \ -bgack_030_int_0_un3_n.BLIF N_185.BLIF N_33_0.BLIF bgack_030_int_0_un1_n.BLIF \ -N_184.BLIF a_c_i_0__n.BLIF bgack_030_int_0_un0_n.BLIF N_180.BLIF \ -size_c_i_1__n.BLIF bg_000_0_un3_n.BLIF N_179.BLIF \ -pos_clk_un10_sm_amiga_i_n.BLIF bg_000_0_un1_n.BLIF N_178.BLIF N_256_0.BLIF \ -bg_000_0_un0_n.BLIF N_171.BLIF N_318_i.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF N_341.BLIF N_314_i.BLIF \ -amiga_bus_enable_dma_high_0_un1_n.BLIF N_342.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF \ -N_169.BLIF N_219_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n.BLIF \ -N_154.BLIF N_220_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n.BLIF \ -N_165.BLIF cpu_est_2_0_1__n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n.BLIF N_162.BLIF N_221_i.BLIF \ -size_dma_0_0__un3_n.BLIF N_299.BLIF N_348_i.BLIF size_dma_0_0__un1_n.BLIF \ -N_153.BLIF cpu_est_2_0_2__n.BLIF size_dma_0_0__un0_n.BLIF N_142.BLIF \ -N_222_i.BLIF size_dma_0_1__un3_n.BLIF N_298.BLIF N_196_i.BLIF \ -size_dma_0_1__un1_n.BLIF N_80.BLIF N_226_i.BLIF size_dma_0_1__un0_n.BLIF \ -N_232.BLIF ds_000_enable_0_un3_n.BLIF N_233.BLIF N_231_i.BLIF \ -ds_000_enable_0_un1_n.BLIF N_229.BLIF N_229_i.BLIF ds_000_enable_0_un0_n.BLIF \ -N_231.BLIF N_302_i.BLIF as_030_000_sync_0_un3_n.BLIF N_226.BLIF N_233_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_221.BLIF N_232_i.BLIF \ -as_030_000_sync_0_un0_n.BLIF N_222.BLIF rw_000_int_0_un3_n.BLIF \ -cpu_est_2_2__n.BLIF N_80_0.BLIF rw_000_int_0_un1_n.BLIF cpu_est_2_1__n.BLIF \ -N_343_i.BLIF rw_000_int_0_un0_n.BLIF N_219.BLIF N_214_0.BLIF \ -a0_dma_0_un3_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_166_i.BLIF \ -a0_dma_0_un1_n.BLIF N_256.BLIF N_134_i.BLIF a0_dma_0_un0_n.BLIF N_29.BLIF \ -N_298_i.BLIF a_decode_15__n.BLIF N_28.BLIF N_142_0.BLIF N_27.BLIF N_153_i.BLIF \ -a_decode_14__n.BLIF N_14.BLIF N_154_0.BLIF N_19.BLIF N_156_i.BLIF \ -a_decode_13__n.BLIF N_20.BLIF N_305_i.BLIF N_21.BLIF N_299_i.BLIF \ -a_decode_12__n.BLIF N_23.BLIF N_162_0.BLIF un1_amiga_bus_enable_low_i.BLIF \ -N_165_0.BLIF a_decode_11__n.BLIF un21_fpu_cs_i.BLIF N_169_i.BLIF \ -cpu_est_i_1__n.BLIF VMA_INT_i.BLIF a_decode_10__n.BLIF rst_dly_i_2__n.BLIF \ -N_341_i.BLIF rst_dly_i_1__n.BLIF N_342_i.BLIF a_decode_9__n.BLIF \ -cpu_est_i_0__n.BLIF N_171_i.BLIF cpu_est_i_2__n.BLIF N_172_i.BLIF \ -a_decode_8__n.BLIF sm_amiga_i_0__n.BLIF N_178_0.BLIF sm_amiga_i_3__n.BLIF \ -N_179_0.BLIF a_decode_7__n.BLIF sm_amiga_i_4__n.BLIF N_180_0.BLIF \ -sm_amiga_i_5__n.BLIF N_184_0.BLIF a_decode_6__n.BLIF rst_dly_i_0__n.BLIF \ -N_185_0.BLIF sm_amiga_i_2__n.BLIF N_203_i.BLIF a_decode_5__n.BLIF \ -sm_amiga_i_1__n.BLIF N_204_i.BLIF VPA_D_i.BLIF N_205_i.BLIF a_decode_4__n.BLIF \ -clk_000_d_i_1__n.BLIF cpu_est_i_3__n.BLIF N_200_i.BLIF a_decode_3__n.BLIF \ -sm_amiga_i_6__n.BLIF N_199_i.BLIF clk_000_d_i_0__n.BLIF N_201_i.BLIF \ -a_decode_2__n.BLIF BGACK_030_INT_i.BLIF AS_000_i.BLIF AS_000_DMA_i.BLIF \ -N_208_i.BLIF nEXP_SPACE_i.BLIF N_207_i.BLIF cycle_dma_i_0__n.BLIF N_167_i.BLIF \ -DS_000_DMA_i.BLIF N_138_i.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_349_i.BLIF \ +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF nEXP_SPACE_i.BLIF N_171_i.BLIF \ +CLK_030_H_i.BLIF FPU_SENSE_i.BLIF N_121_i.BLIF AS_030_i.BLIF N_255_0.BLIF \ +AS_000_DMA_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF AS_000_i.BLIF N_48_0.BLIF \ +AS_000_INT_i.BLIF N_125_i.BLIF DSACK1_INT_i.BLIF N_126_i.BLIF \ +inst_BGACK_030_INTreg.BLIF clk_000_d_i_0__n.BLIF vcc_n_n.BLIF \ +clk_000_d_i_3__n.BLIF N_127_i.BLIF un5_e.BLIF clk_000_d_i_1__n.BLIF \ +N_128_i.BLIF inst_VMA_INTreg.BLIF cpu_est_i_2__n.BLIF gnd_n_n.BLIF \ +cpu_est_i_3__n.BLIF RW_c_i.BLIF un1_amiga_bus_enable_low.BLIF \ +a_decode_i_16__n.BLIF pos_clk_rw_000_int_5_0_n.BLIF un7_as_030.BLIF \ +a_decode_i_18__n.BLIF N_129_i.BLIF un1_UDS_000_INT.BLIF a_decode_i_19__n.BLIF \ +un1_LDS_000_INT.BLIF ahigh_i_30__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +ahigh_i_31__n.BLIF un10_ciin_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ +ahigh_i_28__n.BLIF N_261_0.BLIF un10_ciin.BLIF ahigh_i_29__n.BLIF N_65_0.BLIF \ +un21_fpu_cs.BLIF ahigh_i_26__n.BLIF N_134_i.BLIF un21_berr.BLIF \ +ahigh_i_27__n.BLIF N_153_i.BLIF un6_ds_030.BLIF ahigh_i_24__n.BLIF N_67_0.BLIF \ +cpu_est_3_.BLIF ahigh_i_25__n.BLIF un2_as_030_i.BLIF cpu_est_0_.BLIF \ +N_206_i.BLIF N_263_i.BLIF cpu_est_1_.BLIF N_207_i.BLIF N_265_i.BLIF \ +cpu_est_2_.BLIF N_208_i.BLIF AS_030_000_SYNC_i.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_84_0.BLIF inst_AS_030_D0.BLIF \ +clk_000_d_i_2__n.BLIF inst_AS_030_000_SYNC.BLIF N_81_i.BLIF N_85_i.BLIF \ +inst_BGACK_030_INT_D.BLIF un6_ds_030_i.BLIF N_141_i.BLIF inst_AS_000_DMA.BLIF \ +DS_000_DMA_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF inst_DS_000_DMA.BLIF \ +N_147_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF CYCLE_DMA_0_.BLIF \ +N_145_i.BLIF N_269_i.BLIF CYCLE_DMA_1_.BLIF un7_as_030_i.BLIF N_90_i.BLIF \ +inst_VPA_D.BLIF RESET_OUT_i.BLIF N_270_i.BLIF CLK_000_D_2_.BLIF AS_030_c.BLIF \ +N_271_0.BLIF CLK_000_D_3_.BLIF N_96_0.BLIF inst_DTACK_D0.BLIF AS_000_c.BLIF \ +N_97_0.BLIF inst_RESET_OUT.BLIF N_98_0.BLIF CLK_000_D_1_.BLIF RW_000_c.BLIF \ +N_282_i.BLIF CLK_000_D_0_.BLIF N_284_i.BLIF inst_CLK_OUT_PRE_50.BLIF \ +pos_clk_un14_clk_000_ne_i_n.BLIF inst_CLK_OUT_PRE_D.BLIF UDS_000_c.BLIF \ +un5_e_0.BLIF IPL_D0_0_.BLIF N_285_i.BLIF IPL_D0_1_.BLIF LDS_000_c.BLIF \ +N_291_i.BLIF IPL_D0_2_.BLIF N_292_i.BLIF CLK_000_D_4_.BLIF size_c_0__n.BLIF \ +N_192_i.BLIF pos_clk_un6_bg_030_n.BLIF N_17_i.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF size_c_1__n.BLIF cpu_est_2_0_2__n.BLIF \ +pos_clk_ipl_n.BLIF N_286_i.BLIF SM_AMIGA_1_.BLIF ahigh_c_24__n.BLIF \ +N_288_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF cpu_est_2_0_1__n.BLIF \ +inst_UDS_000_INT.BLIF ahigh_c_25__n.BLIF N_289_i.BLIF inst_DS_000_ENABLE.BLIF \ +N_290_i.BLIF inst_LDS_000_INT.BLIF ahigh_c_26__n.BLIF \ +pos_clk_un9_clk_000_pe_0_n.BLIF SM_AMIGA_6_.BLIF N_280_i.BLIF SM_AMIGA_4_.BLIF \ +ahigh_c_27__n.BLIF pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_0_.BLIF \ +a_c_i_0__n.BLIF SIZE_DMA_0_.BLIF ahigh_c_28__n.BLIF size_c_i_1__n.BLIF \ +SIZE_DMA_1_.BLIF N_27_i.BLIF inst_RW_000_INT.BLIF ahigh_c_29__n.BLIF \ +N_30_0.BLIF inst_RW_000_DMA.BLIF N_26_i.BLIF RST_DLY_0_.BLIF \ +ahigh_c_30__n.BLIF N_29_0.BLIF RST_DLY_1_.BLIF N_25_i.BLIF RST_DLY_2_.BLIF \ +ahigh_c_31__n.BLIF N_28_0.BLIF inst_A0_DMA.BLIF ipl_c_i_2__n.BLIF \ +pos_clk_un9_clk_000_pe_n.BLIF N_51_0.BLIF inst_CLK_030_H.BLIF \ +ipl_c_i_1__n.BLIF pos_clk_rw_000_int_5_n.BLIF N_50_0.BLIF inst_DSACK1_INT.BLIF \ +ipl_c_i_0__n.BLIF inst_AS_000_INT.BLIF N_49_0.BLIF SM_AMIGA_5_.BLIF N_4_i.BLIF \ +SM_AMIGA_3_.BLIF N_44_0.BLIF SM_AMIGA_2_.BLIF N_14_i.BLIF N_4.BLIF N_41_0.BLIF \ +N_15_i.BLIF N_40_0.BLIF N_9.BLIF N_16_i.BLIF N_39_0.BLIF N_18_i.BLIF \ +N_37_0.BLIF N_14.BLIF N_21_i.BLIF N_15.BLIF N_34_0.BLIF N_16.BLIF N_23_i.BLIF \ +N_18.BLIF N_32_0.BLIF N_21.BLIF LDS_000_INT_i.BLIF N_23.BLIF \ +un1_LDS_000_INT_0.BLIF N_25.BLIF UDS_000_INT_i.BLIF N_26.BLIF \ +un1_UDS_000_INT_0.BLIF N_27.BLIF N_96_0_1.BLIF N_96_0_2.BLIF N_96_0_3.BLIF \ +pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF N_84_0_1.BLIF a_decode_c_16__n.BLIF \ +N_84_0_2.BLIF N_240_0_1.BLIF a_decode_c_17__n.BLIF \ +pos_clk_un10_sm_amiga_i_1_n.BLIF N_289_1.BLIF a_decode_c_18__n.BLIF \ +N_289_2.BLIF N_290_1.BLIF a_decode_c_19__n.BLIF N_290_2.BLIF \ +pos_clk_un14_clk_000_ne_1_n.BLIF a_decode_c_20__n.BLIF \ +pos_clk_un14_clk_000_ne_2_n.BLIF N_153_1.BLIF a_decode_c_21__n.BLIF \ +N_153_2.BLIF N_153_3.BLIF a_decode_c_22__n.BLIF N_153_4.BLIF N_153_5.BLIF \ +a_decode_c_23__n.BLIF un10_ciin_1.BLIF un10_ciin_2.BLIF a_c_0__n.BLIF \ +un10_ciin_3.BLIF un10_ciin_4.BLIF a_c_1__n.BLIF un10_ciin_5.BLIF \ +un10_ciin_6.BLIF SM_AMIGA_i_7_.BLIF nEXP_SPACE_c.BLIF un10_ciin_7.BLIF \ +cpu_est_2_1__n.BLIF un10_ciin_8.BLIF cpu_est_2_2__n.BLIF BERR_c.BLIF \ +un10_ciin_9.BLIF G_107.BLIF un10_ciin_10.BLIF G_108.BLIF BG_030_c.BLIF \ +un10_ciin_11.BLIF G_109.BLIF N_260_i_1.BLIF \ +pos_clk_un21_bgack_030_int_i_0_n.BLIF BG_000DFFreg.BLIF N_260_i_2.BLIF \ +N_81.BLIF N_233_i_1.BLIF N_94.BLIF N_233_i_2.BLIF N_254.BLIF BGACK_000_c.BLIF \ +N_232_i_1.BLIF N_255.BLIF N_232_i_2.BLIF N_261.BLIF CLK_030_c.BLIF \ +N_247_1.BLIF N_65.BLIF N_77_1.BLIF N_67.BLIF N_83_1.BLIF N_269.BLIF \ +N_88_1.BLIF N_108.BLIF CLK_OSZI_c.BLIF N_142_i_1.BLIF N_135.BLIF \ +N_146_i_1.BLIF N_136.BLIF N_234_i_1.BLIF N_145.BLIF CLK_OUT_INTreg.BLIF \ +pos_clk_un6_bg_030_1_n.BLIF N_278.BLIF N_124_1.BLIF N_147.BLIF \ +un21_berr_1.BLIF N_58.BLIF FPU_SENSE_c.BLIF un21_fpu_cs_1.BLIF N_110.BLIF \ +N_140_i_1.BLIF N_239.BLIF IPL_030DFF_0_reg.BLIF N_154_i_1.BLIF N_90.BLIF \ +N_152_i_1.BLIF N_265.BLIF IPL_030DFF_1_reg.BLIF N_150_i_1.BLIF \ +pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_148_i_1.BLIF \ +pos_clk_un21_bgack_030_int_i_0_x2.BLIF IPL_030DFF_2_reg.BLIF N_144_i_1.BLIF \ +pos_clk_un19_bgack_030_int_n.BLIF N_255_0_1.BLIF N_280.BLIF ipl_c_0__n.BLIF \ +N_258_i_1.BLIF N_263.BLIF N_259_i_1.BLIF N_247.BLIF ipl_c_1__n.BLIF \ +N_282_1.BLIF N_77.BLIF N_284_1.BLIF N_289.BLIF ipl_c_2__n.BLIF N_288_1.BLIF \ +N_291.BLIF un5_e_0_1.BLIF N_290.BLIF N_192_i_1.BLIF N_286.BLIF DTACK_c.BLIF \ +pos_clk_ipl_1_n.BLIF N_288.BLIF bg_000_0_un3_n.BLIF N_285.BLIF \ +bg_000_0_un1_n.BLIF N_17.BLIF bg_000_0_un0_n.BLIF N_292.BLIF VPA_c.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_un14_clk_000_ne_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF N_282.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_284.BLIF RST_c.BLIF \ +a0_dma_0_un3_n.BLIF N_98.BLIF a0_dma_0_un1_n.BLIF N_97.BLIF \ +a0_dma_0_un0_n.BLIF N_84.BLIF RW_c.BLIF rw_000_dma_0_un3_n.BLIF N_96.BLIF \ +rw_000_dma_0_un1_n.BLIF N_271.BLIF fc_c_0__n.BLIF rw_000_dma_0_un0_n.BLIF \ +N_117.BLIF bgack_030_int_0_un3_n.BLIF N_141.BLIF fc_c_1__n.BLIF \ +bgack_030_int_0_un1_n.BLIF N_134.BLIF bgack_030_int_0_un0_n.BLIF N_153.BLIF \ +ds_000_dma_0_un3_n.BLIF N_129.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +ds_000_dma_0_un1_n.BLIF N_127.BLIF ds_000_dma_0_un0_n.BLIF N_128.BLIF \ +size_dma_0_1__un3_n.BLIF N_125.BLIF size_dma_0_1__un1_n.BLIF N_126.BLIF \ +size_dma_0_1__un0_n.BLIF N_124.BLIF BG_030_c_i.BLIF size_dma_0_0__un3_n.BLIF \ +N_121.BLIF pos_clk_un6_bg_030_i_n.BLIF size_dma_0_0__un1_n.BLIF N_171.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF size_dma_0_0__un0_n.BLIF N_120.BLIF N_24_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_119.BLIF N_31_0.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_118.BLIF N_22_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_116.BLIF N_33_0.BLIF \ +cpu_est_0_1__un3_n.BLIF N_114.BLIF N_20_i.BLIF cpu_est_0_1__un1_n.BLIF \ +N_115.BLIF N_35_0.BLIF cpu_est_0_1__un0_n.BLIF N_243.BLIF N_19_i.BLIF \ +cpu_est_0_2__un3_n.BLIF N_240.BLIF N_36_0.BLIF cpu_est_0_2__un1_n.BLIF \ +N_88.BLIF N_8_i.BLIF cpu_est_0_2__un0_n.BLIF N_89.BLIF N_42_0.BLIF \ +cpu_est_0_3__un3_n.BLIF N_82.BLIF N_3_i.BLIF cpu_est_0_3__un1_n.BLIF N_83.BLIF \ +N_45_0.BLIF cpu_est_0_3__un0_n.BLIF N_78.BLIF VPA_c_i.BLIF \ +ipl_030_0_0__un3_n.BLIF N_79.BLIF N_52_0.BLIF ipl_030_0_0__un1_n.BLIF \ +N_91.BLIF DTACK_c_i.BLIF ipl_030_0_0__un0_n.BLIF N_244.BLIF N_53_0.BLIF \ +ipl_030_0_1__un3_n.BLIF N_62.BLIF ipl_030_0_1__un1_n.BLIF N_64.BLIF \ +N_249_i.BLIF ipl_030_0_1__un0_n.BLIF N_59.BLIF N_248_i.BLIF \ +ipl_030_0_2__un3_n.BLIF N_61.BLIF N_247_i.BLIF ipl_030_0_2__un1_n.BLIF \ +N_163.BLIF ipl_030_0_2__un0_n.BLIF N_245.BLIF N_77_i.BLIF \ +uds_000_int_0_un3_n.BLIF N_242.BLIF N_251_i.BLIF uds_000_int_0_un1_n.BLIF \ +N_246.BLIF N_76_i.BLIF uds_000_int_0_un0_n.BLIF N_248.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF N_236.BLIF N_131_i.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF N_249.BLIF N_130_i.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_92.BLIF N_264_i.BLIF \ +as_000_dma_0_un3_n.BLIF N_251.BLIF N_170_i.BLIF as_000_dma_0_un1_n.BLIF \ +N_76.BLIF pos_clk_un6_bgack_000_0_n.BLIF as_000_dma_0_un0_n.BLIF N_80.BLIF \ +pos_clk_rw_000_dma_3_0_n.BLIF ds_000_enable_0_un3_n.BLIF \ +pos_clk_a0_dma_3_n.BLIF N_123_i.BLIF ds_000_enable_0_un1_n.BLIF \ +SIZE_DMA_3_sqmuxa.BLIF N_124_i.BLIF ds_000_enable_0_un0_n.BLIF N_87.BLIF \ +AMIGA_BUS_DATA_DIR_c_0.BLIF lds_000_int_0_un3_n.BLIF \ +pos_clk_size_dma_6_1__n.BLIF N_122_i.BLIF lds_000_int_0_un1_n.BLIF \ +pos_clk_size_dma_6_0__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +lds_000_int_0_un0_n.BLIF N_170.BLIF N_242_i.BLIF as_030_000_sync_0_un3_n.BLIF \ +N_122.BLIF N_239_i.BLIF as_030_000_sync_0_un1_n.BLIF N_123.BLIF N_87_i.BLIF \ +as_030_000_sync_0_un0_n.BLIF N_130.BLIF N_236_0.BLIF rw_000_int_0_un3_n.BLIF \ +pos_clk_ds_000_dma_4_n.BLIF N_246_i.BLIF rw_000_int_0_un1_n.BLIF \ +pos_clk_rw_000_dma_3_n.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ +rw_000_int_0_un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF N_245_i.BLIF \ +vma_int_0_un3_n.BLIF N_131.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +vma_int_0_un1_n.BLIF N_3.BLIF N_91_i.BLIF vma_int_0_un0_n.BLIF N_8.BLIF \ +N_210_i.BLIF a_decode_15__n.BLIF N_19.BLIF pos_clk_un19_bgack_030_int_i_n.BLIF \ +N_20.BLIF N_163_0.BLIF a_decode_14__n.BLIF N_22.BLIF N_59_i.BLIF N_24.BLIF \ +N_61_i.BLIF a_decode_13__n.BLIF pos_clk_un9_bg_030_n.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_62_i.BLIF a_decode_12__n.BLIF \ +un21_fpu_cs_i.BLIF N_64_i.BLIF BGACK_030_INT_i.BLIF a_decode_11__n.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_244_i.BLIF N_80_i.BLIF a_decode_10__n.BLIF \ +cycle_dma_i_0__n.BLIF N_78_i_0.BLIF RW_000_i.BLIF N_79_i.BLIF \ +a_decode_9__n.BLIF rst_dly_i_0__n.BLIF rst_dly_i_1__n.BLIF N_82_i.BLIF \ +a_decode_8__n.BLIF rst_dly_i_2__n.BLIF N_83_i.BLIF LDS_000_i.BLIF N_55_0.BLIF \ +a_decode_7__n.BLIF UDS_000_i.BLIF N_88_i.BLIF sm_amiga_i_2__n.BLIF N_89_i.BLIF \ +a_decode_6__n.BLIF N_58_i.BLIF N_240_0.BLIF sm_amiga_i_3__n.BLIF N_243_0.BLIF \ +a_decode_5__n.BLIF cpu_est_i_1__n.BLIF CLK_030_c_i.BLIF cpu_est_i_0__n.BLIF \ +N_254_0.BLIF a_decode_4__n.BLIF sm_amiga_i_1__n.BLIF N_114_i.BLIF N_110_i.BLIF \ +N_115_i.BLIF a_decode_3__n.BLIF a_i_1__n.BLIF VMA_INT_i.BLIF N_116_i.BLIF \ +a_decode_2__n.BLIF VPA_D_i.BLIF N_117_i.BLIF DTACK_D0_i.BLIF AS_030_D0_i.BLIF \ +N_118_i.BLIF sm_amiga_i_0__n.BLIF sm_amiga_i_i_7__n.BLIF N_119_i.BLIF \ +sm_amiga_i_6__n.BLIF sm_amiga_i_5__n.BLIF N_120_i.BLIF sm_amiga_i_4__n.BLIF \ AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ @@ -275,162 +278,163 @@ AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ -SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \ -IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ -IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D \ -SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C CLK_000_D_2_.D CLK_000_D_2_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ -cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C RST_DLY_0_.D \ -RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \ -inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ +IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ +IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ +SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ +CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ +CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D \ +SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ +cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ +RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D \ +inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ -inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 \ -UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_130_i pos_clk_un6_bgack_000_0_n N_131_i \ -DTACK_c_i CLK_030_H_i N_56_0 RW_000_i VPA_c_i a_i_1__n N_55_0 RESET_OUT_i \ -N_6_i AS_030_i N_47_0 FPU_SENSE_i N_26_i sm_amiga_i_i_7__n N_34_0 vcc_n_n \ -a_decode_i_16__n BG_030_c_i AS_030_D0_i pos_clk_un6_bg_030_i_n gnd_n_n \ -size_dma_i_0__n pos_clk_un9_bg_030_0_n un1_amiga_bus_enable_low \ -size_dma_i_1__n N_25_i un6_as_030 a_decode_i_18__n N_35_0 un3_size \ -a_decode_i_19__n N_24_i un4_size ahigh_i_30__n N_36_0 un1_LDS_000_INT \ -ahigh_i_31__n N_17_i un1_UDS_000_INT ahigh_i_28__n N_43_0 \ -un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_29__n N_4_i un1_DS_000_ENABLE_0_sqmuxa \ -ahigh_i_26__n N_49_0 un4_as_000 ahigh_i_27__n N_3_i un10_ciin ahigh_i_24__n \ -N_50_0 un21_fpu_cs ahigh_i_25__n N_215_i un21_berr N_210_i N_216_i un6_ds_030 \ -N_211_i N_301_0 N_212_i N_243_0 N_266_i un6_ds_030_i N_249_i un4_as_000_i \ -AMIGA_BUS_DATA_DIR_c_0 AS_000_INT_i N_268_i un6_as_030_i \ -pos_clk_ds_000_dma_4_0_n AS_030_c CLK_030_c_i N_236_0 AS_000_c un1_as_000_i \ -N_297_i RW_000_c N_160_i pos_clk_un21_bgack_030_int_i_0_i_n N_100_i UDS_000_c \ -N_186_0 N_183_0 LDS_000_c N_182_0 N_181_0 size_c_0__n N_228_i N_176_0 \ -size_c_1__n LDS_000_c_i UDS_000_c_i ahigh_c_24__n N_173_i N_304_i \ -ahigh_c_25__n AS_030_000_SYNC_i N_157_i ahigh_c_26__n N_110_0 RW_c_i \ -pos_clk_un6_bg_030_n ahigh_c_27__n N_106_0 N_284_i ahigh_c_28__n pos_clk_ipl_n \ -N_334_i ahigh_c_29__n N_278_i ahigh_c_30__n N_279_i ahigh_c_31__n N_332_i \ -N_237_0 un1_SM_AMIGA_0_sqmuxa_1_0 N_247_i N_248_i N_246_i pos_clk_a0_dma_3_n \ -un10_ciin_i N_241_0 un1_DS_000_ENABLE_0_sqmuxa_i N_242_0 N_48_i N_227_i N_9 \ -N_225_i N_224_i N_15 N_223_i N_16 N_22 N_218_i pos_clk_size_dma_6_0_1__n \ -N_217_i pos_clk_size_dma_6_0_0__n N_213_i N_319_i N_300_0 N_15_i \ -a_decode_c_16__n N_45_0 N_16_i a_decode_c_17__n N_44_0 N_22_i a_decode_c_18__n \ -N_38_0 pos_clk_un21_bgack_030_int_i_0_i_1_n a_decode_c_19__n \ -pos_clk_un21_bgack_030_int_i_0_i_2_n N_238_i_1 a_decode_c_20__n N_238_i_2 \ -N_239_i_1 a_decode_c_21__n N_239_i_2 pos_clk_un10_sm_amiga_i_1_n \ -a_decode_c_22__n un10_ciin_1 un10_ciin_2 a_decode_c_23__n un10_ciin_3 \ -un10_ciin_4 a_c_0__n un10_ciin_5 un10_ciin_6 a_c_1__n un10_ciin_7 \ -pos_clk_size_dma_6_0__n un10_ciin_8 pos_clk_size_dma_6_1__n nEXP_SPACE_c \ -un10_ciin_9 un10_ciin_10 BERR_c un10_ciin_11 N_357_1 \ -pos_clk_un21_bgack_030_int_i_0_n BG_030_c N_357_2 N_237 N_357_3 N_241 N_357_4 \ -N_242 N_304_i_1 un21_fpu_cs_1 N_283 BGACK_000_c un21_berr_1_0 N_294 N_266_1 \ -N_300 CLK_030_c N_266_2 N_67_i_1 N_106 N_67_i_2 N_314_1 N_134 CLK_OSZI_c \ -N_314_2 N_138 N_318_1 N_156 N_318_2 N_160 N_341_1 N_167 N_341_2 N_172 \ -N_151_i_1 N_173 FPU_SENSE_c N_143_i_1 N_181 N_141_i_1 N_182 N_237_0_1 N_183 \ -N_240_i_1 N_191 N_60_i_1 N_199 N_64_i_1 N_205 N_155_i_1 N_209 N_147_i_1 N_319 \ -ipl_c_0__n N_145_i_1 N_213 N_139_i_1 N_216 ipl_c_1__n pos_clk_un6_bg_030_1_n \ -N_217 N_220_1 N_218 ipl_c_2__n N_216_1 N_220 N_205_1 N_223 N_199_1 N_224 \ -DTACK_c pos_clk_ipl_1_n N_225 uds_000_int_0_un3_n N_227 uds_000_int_0_un1_n \ -N_228 uds_000_int_0_un0_n N_246 VPA_c as_000_int_0_un3_n N_247 \ -as_000_int_0_un1_n N_248 as_000_int_0_un0_n N_332 RST_c dsack1_int_0_un3_n \ -N_278 dsack1_int_0_un1_n N_279 dsack1_int_0_un0_n N_334 RW_c vma_int_0_un3_n \ -N_284 vma_int_0_un1_n N_343 fc_c_0__n vma_int_0_un0_n lds_000_int_0_un3_n \ -un21_berr_1 fc_c_1__n lds_000_int_0_un1_n N_357 lds_000_int_0_un0_n N_266 \ -ipl_030_0_1__un3_n N_186 AMIGA_BUS_DATA_DIR_c ipl_030_0_1__un1_n \ -ipl_030_0_1__un0_n N_297 ipl_030_0_0__un3_n N_236 ipl_030_0_0__un1_n \ -pos_clk_ds_000_dma_4_n ipl_030_0_0__un0_n N_268 UDS_000_INT_i \ -cpu_est_0_3__un3_n N_249 un1_UDS_000_INT_0 cpu_est_0_3__un1_n N_243 \ -LDS_000_INT_i cpu_est_0_3__un0_n N_215 un1_LDS_000_INT_0 cpu_est_0_2__un3_n \ -N_130 N_23_i cpu_est_0_2__un1_n N_131 N_37_0 cpu_est_0_2__un0_n N_3 N_21_i \ -cpu_est_0_1__un3_n N_4 N_39_0 cpu_est_0_1__un1_n N_17 N_20_i \ -cpu_est_0_1__un0_n N_24 N_40_0 ipl_030_0_2__un3_n N_25 N_19_i \ -ipl_030_0_2__un1_n pos_clk_un9_bg_030_n N_41_0 ipl_030_0_2__un0_n N_6 N_14_i \ -amiga_bus_enable_dma_low_0_un3_n pos_clk_un6_bgack_000_n N_46_0 \ -amiga_bus_enable_dma_low_0_un1_n N_26 ipl_c_i_0__n \ -amiga_bus_enable_dma_low_0_un0_n N_208 N_52_0 rw_000_dma_0_un3_n N_207 \ -ipl_c_i_1__n rw_000_dma_0_un1_n N_349 N_53_0 rw_000_dma_0_un0_n N_314 \ -ipl_c_i_2__n as_000_dma_0_un3_n N_318 N_54_0 as_000_dma_0_un1_n N_348 N_27_i \ -as_000_dma_0_un0_n N_201 N_31_0 ds_000_dma_0_un3_n N_200 N_28_i \ -ds_000_dma_0_un1_n N_203 N_32_0 ds_000_dma_0_un0_n N_204 N_29_i \ -bgack_030_int_0_un3_n N_185 N_33_0 bgack_030_int_0_un1_n N_184 a_c_i_0__n \ -bgack_030_int_0_un0_n N_180 size_c_i_1__n bg_000_0_un3_n N_179 \ -pos_clk_un10_sm_amiga_i_n bg_000_0_un1_n N_178 N_256_0 bg_000_0_un0_n N_171 \ -N_318_i amiga_bus_enable_dma_high_0_un3_n N_341 N_314_i \ -amiga_bus_enable_dma_high_0_un1_n N_342 pos_clk_un9_clk_000_pe_0_n \ -amiga_bus_enable_dma_high_0_un0_n N_169 N_219_i \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n N_154 N_220_i \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n N_165 cpu_est_2_0_1__n \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n N_162 N_221_i \ -size_dma_0_0__un3_n N_299 N_348_i size_dma_0_0__un1_n N_153 cpu_est_2_0_2__n \ -size_dma_0_0__un0_n N_142 N_222_i size_dma_0_1__un3_n N_298 N_196_i \ -size_dma_0_1__un1_n N_80 N_226_i size_dma_0_1__un0_n N_232 \ -ds_000_enable_0_un3_n N_233 N_231_i ds_000_enable_0_un1_n N_229 N_229_i \ -ds_000_enable_0_un0_n N_231 N_302_i as_030_000_sync_0_un3_n N_226 N_233_i \ -as_030_000_sync_0_un1_n N_221 N_232_i as_030_000_sync_0_un0_n N_222 \ -rw_000_int_0_un3_n cpu_est_2_2__n N_80_0 rw_000_int_0_un1_n cpu_est_2_1__n \ -N_343_i rw_000_int_0_un0_n N_219 N_214_0 a0_dma_0_un3_n \ -pos_clk_un9_clk_000_pe_n N_166_i a0_dma_0_un1_n N_256 N_134_i a0_dma_0_un0_n \ -N_29 N_298_i a_decode_15__n N_28 N_142_0 N_27 N_153_i a_decode_14__n N_14 \ -N_154_0 N_19 N_156_i a_decode_13__n N_20 N_305_i N_21 N_299_i a_decode_12__n \ -N_23 N_162_0 un1_amiga_bus_enable_low_i N_165_0 a_decode_11__n un21_fpu_cs_i \ -N_169_i cpu_est_i_1__n VMA_INT_i a_decode_10__n rst_dly_i_2__n N_341_i \ -rst_dly_i_1__n N_342_i a_decode_9__n cpu_est_i_0__n N_171_i cpu_est_i_2__n \ -N_172_i a_decode_8__n sm_amiga_i_0__n N_178_0 sm_amiga_i_3__n N_179_0 \ -a_decode_7__n sm_amiga_i_4__n N_180_0 sm_amiga_i_5__n N_184_0 a_decode_6__n \ -rst_dly_i_0__n N_185_0 sm_amiga_i_2__n N_203_i a_decode_5__n sm_amiga_i_1__n \ -N_204_i VPA_D_i N_205_i a_decode_4__n clk_000_d_i_1__n cpu_est_i_3__n N_200_i \ -a_decode_3__n sm_amiga_i_6__n N_199_i clk_000_d_i_0__n N_201_i a_decode_2__n \ -BGACK_030_INT_i AS_000_i AS_000_DMA_i N_208_i nEXP_SPACE_i N_207_i \ -cycle_dma_i_0__n N_167_i DS_000_DMA_i N_138_i AMIGA_BUS_ENABLE_DMA_LOW_i \ -N_349_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ -AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ -DSACK1.OE RESET.OE CIIN.OE CLK_OUT_PRE_25_0 G_107 G_108 G_109 \ -pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2 -.names N_145_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ +inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ +AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ \ +AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ nEXP_SPACE_i \ +N_171_i CLK_030_H_i FPU_SENSE_i N_121_i AS_030_i N_255_0 AS_000_DMA_i \ +un1_SM_AMIGA_0_sqmuxa_1_0 AS_000_i N_48_0 AS_000_INT_i N_125_i DSACK1_INT_i \ +N_126_i clk_000_d_i_0__n vcc_n_n clk_000_d_i_3__n N_127_i un5_e \ +clk_000_d_i_1__n N_128_i cpu_est_i_2__n gnd_n_n cpu_est_i_3__n RW_c_i \ +un1_amiga_bus_enable_low a_decode_i_16__n pos_clk_rw_000_int_5_0_n un7_as_030 \ +a_decode_i_18__n N_129_i un1_UDS_000_INT a_decode_i_19__n un1_LDS_000_INT \ +ahigh_i_30__n un1_SM_AMIGA_0_sqmuxa_1 ahigh_i_31__n un10_ciin_i \ +un1_DS_000_ENABLE_0_sqmuxa ahigh_i_28__n N_261_0 un10_ciin ahigh_i_29__n \ +N_65_0 un21_fpu_cs ahigh_i_26__n N_134_i un21_berr ahigh_i_27__n N_153_i \ +un6_ds_030 ahigh_i_24__n N_67_0 ahigh_i_25__n un2_as_030_i N_206_i N_263_i \ +N_207_i N_265_i N_208_i AS_030_000_SYNC_i N_84_0 clk_000_d_i_2__n N_81_i \ +N_85_i un6_ds_030_i N_141_i DS_000_DMA_i un1_DS_000_ENABLE_0_sqmuxa_i N_147_i \ +pos_clk_un21_bgack_030_int_i_0_i_n N_145_i N_269_i un7_as_030_i N_90_i \ +RESET_OUT_i N_270_i AS_030_c N_271_0 N_96_0 AS_000_c N_97_0 N_98_0 RW_000_c \ +N_282_i N_284_i pos_clk_un14_clk_000_ne_i_n UDS_000_c un5_e_0 N_285_i \ +LDS_000_c N_291_i N_292_i size_c_0__n N_192_i pos_clk_un6_bg_030_n N_17_i \ +size_c_1__n cpu_est_2_0_2__n pos_clk_ipl_n N_286_i ahigh_c_24__n N_288_i \ +AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa cpu_est_2_0_1__n ahigh_c_25__n N_289_i \ +N_290_i ahigh_c_26__n pos_clk_un9_clk_000_pe_0_n N_280_i ahigh_c_27__n \ +pos_clk_un10_sm_amiga_i_n a_c_i_0__n ahigh_c_28__n size_c_i_1__n N_27_i \ +ahigh_c_29__n N_30_0 N_26_i ahigh_c_30__n N_29_0 N_25_i ahigh_c_31__n N_28_0 \ +ipl_c_i_2__n pos_clk_un9_clk_000_pe_n N_51_0 ipl_c_i_1__n \ +pos_clk_rw_000_int_5_n N_50_0 ipl_c_i_0__n N_49_0 N_4_i N_44_0 N_14_i N_4 \ +N_41_0 N_15_i N_40_0 N_9 N_16_i N_39_0 N_18_i N_37_0 N_14 N_21_i N_15 N_34_0 \ +N_16 N_23_i N_18 N_32_0 N_21 LDS_000_INT_i N_23 un1_LDS_000_INT_0 N_25 \ +UDS_000_INT_i N_26 un1_UDS_000_INT_0 N_27 N_96_0_1 N_96_0_2 N_96_0_3 \ +pos_clk_un21_bgack_030_int_i_0_i_1_n N_84_0_1 a_decode_c_16__n N_84_0_2 \ +N_240_0_1 a_decode_c_17__n pos_clk_un10_sm_amiga_i_1_n N_289_1 \ +a_decode_c_18__n N_289_2 N_290_1 a_decode_c_19__n N_290_2 \ +pos_clk_un14_clk_000_ne_1_n a_decode_c_20__n pos_clk_un14_clk_000_ne_2_n \ +N_153_1 a_decode_c_21__n N_153_2 N_153_3 a_decode_c_22__n N_153_4 N_153_5 \ +a_decode_c_23__n un10_ciin_1 un10_ciin_2 a_c_0__n un10_ciin_3 un10_ciin_4 \ +a_c_1__n un10_ciin_5 un10_ciin_6 nEXP_SPACE_c un10_ciin_7 cpu_est_2_1__n \ +un10_ciin_8 cpu_est_2_2__n BERR_c un10_ciin_9 un10_ciin_10 BG_030_c \ +un10_ciin_11 N_260_i_1 pos_clk_un21_bgack_030_int_i_0_n N_260_i_2 N_81 \ +N_233_i_1 N_94 N_233_i_2 N_254 BGACK_000_c N_232_i_1 N_255 N_232_i_2 N_261 \ +CLK_030_c N_247_1 N_65 N_77_1 N_67 N_83_1 N_269 N_88_1 N_108 CLK_OSZI_c \ +N_142_i_1 N_135 N_146_i_1 N_136 N_234_i_1 N_145 pos_clk_un6_bg_030_1_n N_278 \ +N_124_1 N_147 un21_berr_1 N_58 FPU_SENSE_c un21_fpu_cs_1 N_110 N_140_i_1 N_239 \ +N_154_i_1 N_90 N_152_i_1 N_265 N_150_i_1 N_148_i_1 N_144_i_1 \ +pos_clk_un19_bgack_030_int_n N_255_0_1 N_280 ipl_c_0__n N_258_i_1 N_263 \ +N_259_i_1 N_247 ipl_c_1__n N_282_1 N_77 N_284_1 N_289 ipl_c_2__n N_288_1 N_291 \ +un5_e_0_1 N_290 N_192_i_1 N_286 DTACK_c pos_clk_ipl_1_n N_288 bg_000_0_un3_n \ +N_285 bg_000_0_un1_n N_17 bg_000_0_un0_n N_292 VPA_c \ +amiga_bus_enable_dma_low_0_un3_n pos_clk_un14_clk_000_ne_n \ +amiga_bus_enable_dma_low_0_un1_n N_282 amiga_bus_enable_dma_low_0_un0_n N_284 \ +RST_c a0_dma_0_un3_n N_98 a0_dma_0_un1_n N_97 a0_dma_0_un0_n N_84 RW_c \ +rw_000_dma_0_un3_n N_96 rw_000_dma_0_un1_n N_271 fc_c_0__n rw_000_dma_0_un0_n \ +N_117 bgack_030_int_0_un3_n N_141 fc_c_1__n bgack_030_int_0_un1_n N_134 \ +bgack_030_int_0_un0_n N_153 ds_000_dma_0_un3_n N_129 AMIGA_BUS_DATA_DIR_c \ +ds_000_dma_0_un1_n N_127 ds_000_dma_0_un0_n N_128 size_dma_0_1__un3_n N_125 \ +size_dma_0_1__un1_n N_126 size_dma_0_1__un0_n N_124 BG_030_c_i \ +size_dma_0_0__un3_n N_121 pos_clk_un6_bg_030_i_n size_dma_0_0__un1_n N_171 \ +pos_clk_un9_bg_030_0_n size_dma_0_0__un0_n N_120 N_24_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_119 N_31_0 \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_118 N_22_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_116 N_33_0 cpu_est_0_1__un3_n \ +N_114 N_20_i cpu_est_0_1__un1_n N_115 N_35_0 cpu_est_0_1__un0_n N_243 N_19_i \ +cpu_est_0_2__un3_n N_240 N_36_0 cpu_est_0_2__un1_n N_88 N_8_i \ +cpu_est_0_2__un0_n N_89 N_42_0 cpu_est_0_3__un3_n N_82 N_3_i \ +cpu_est_0_3__un1_n N_83 N_45_0 cpu_est_0_3__un0_n N_78 VPA_c_i \ +ipl_030_0_0__un3_n N_79 N_52_0 ipl_030_0_0__un1_n N_91 DTACK_c_i \ +ipl_030_0_0__un0_n N_244 N_53_0 ipl_030_0_1__un3_n N_62 ipl_030_0_1__un1_n \ +N_64 N_249_i ipl_030_0_1__un0_n N_59 N_248_i ipl_030_0_2__un3_n N_61 N_247_i \ +ipl_030_0_2__un1_n N_163 ipl_030_0_2__un0_n N_245 N_77_i uds_000_int_0_un3_n \ +N_242 N_251_i uds_000_int_0_un1_n N_246 N_76_i uds_000_int_0_un0_n N_248 \ +amiga_bus_enable_dma_high_0_un3_n N_236 N_131_i \ +amiga_bus_enable_dma_high_0_un1_n N_249 N_130_i \ +amiga_bus_enable_dma_high_0_un0_n N_92 N_264_i as_000_dma_0_un3_n N_251 \ +N_170_i as_000_dma_0_un1_n N_76 pos_clk_un6_bgack_000_0_n as_000_dma_0_un0_n \ +N_80 pos_clk_rw_000_dma_3_0_n ds_000_enable_0_un3_n pos_clk_a0_dma_3_n N_123_i \ +ds_000_enable_0_un1_n SIZE_DMA_3_sqmuxa N_124_i ds_000_enable_0_un0_n N_87 \ +AMIGA_BUS_DATA_DIR_c_0 lds_000_int_0_un3_n pos_clk_size_dma_6_1__n N_122_i \ +lds_000_int_0_un1_n pos_clk_size_dma_6_0__n pos_clk_ds_000_dma_4_0_n \ +lds_000_int_0_un0_n N_170 N_242_i as_030_000_sync_0_un3_n N_122 N_239_i \ +as_030_000_sync_0_un1_n N_123 N_87_i as_030_000_sync_0_un0_n N_130 N_236_0 \ +rw_000_int_0_un3_n pos_clk_ds_000_dma_4_n N_246_i rw_000_int_0_un1_n \ +pos_clk_rw_000_dma_3_n pos_clk_size_dma_6_0_0__n rw_000_int_0_un0_n \ +pos_clk_un6_bgack_000_n N_245_i vma_int_0_un3_n N_131 \ +pos_clk_size_dma_6_0_1__n vma_int_0_un1_n N_3 N_91_i vma_int_0_un0_n N_8 \ +N_210_i a_decode_15__n N_19 pos_clk_un19_bgack_030_int_i_n N_20 N_163_0 \ +a_decode_14__n N_22 N_59_i N_24 N_61_i a_decode_13__n pos_clk_un9_bg_030_n \ +un1_amiga_bus_enable_low_i N_62_i a_decode_12__n un21_fpu_cs_i N_64_i \ +BGACK_030_INT_i a_decode_11__n AMIGA_BUS_ENABLE_DMA_LOW_i N_244_i N_80_i \ +a_decode_10__n cycle_dma_i_0__n N_78_i_0 RW_000_i N_79_i a_decode_9__n \ +rst_dly_i_0__n rst_dly_i_1__n N_82_i a_decode_8__n rst_dly_i_2__n N_83_i \ +LDS_000_i N_55_0 a_decode_7__n UDS_000_i N_88_i sm_amiga_i_2__n N_89_i \ +a_decode_6__n N_58_i N_240_0 sm_amiga_i_3__n N_243_0 a_decode_5__n \ +cpu_est_i_1__n CLK_030_c_i cpu_est_i_0__n N_254_0 a_decode_4__n \ +sm_amiga_i_1__n N_114_i N_110_i N_115_i a_decode_3__n a_i_1__n VMA_INT_i \ +N_116_i a_decode_2__n VPA_D_i N_117_i DTACK_D0_i AS_030_D0_i N_118_i \ +sm_amiga_i_0__n sm_amiga_i_i_7__n N_119_i sm_amiga_i_6__n sm_amiga_i_5__n \ +N_120_i sm_amiga_i_4__n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE \ +SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE \ +AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE \ +DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_107 G_108 G_109 \ +pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_un21_bgack_030_int_i_0_x2 +.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names N_143_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +.names N_150_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 -.names N_141_i_1.BLIF N_279_i.BLIF SM_AMIGA_1_.D +.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 -.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D 11 1 -.names N_31_0.BLIF IPL_030DFF_0_reg.D +.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +11 1 +.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +11 1 +.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +11 1 +.names N_28_0.BLIF IPL_030DFF_0_reg.D 0 1 -.names N_32_0.BLIF IPL_030DFF_1_reg.D +.names N_29_0.BLIF IPL_030DFF_1_reg.D 0 1 -.names N_33_0.BLIF IPL_030DFF_2_reg.D +.names N_30_0.BLIF IPL_030DFF_2_reg.D 0 1 -.names N_52_0.BLIF IPL_D0_0_.D +.names N_49_0.BLIF IPL_D0_0_.D 0 1 -.names N_53_0.BLIF IPL_D0_1_.D +.names N_50_0.BLIF IPL_D0_1_.D 0 1 -.names N_54_0.BLIF IPL_D0_2_.D +.names N_51_0.BLIF IPL_D0_2_.D 0 1 -.names N_155_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +.names N_154_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_151_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +.names N_260_i_1.BLIF N_260_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_166_i.BLIF N_226_i.BLIF SM_AMIGA_5_.D -11 1 -.names N_147_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_67_i_1.BLIF N_67_i_2.BLIF CYCLE_DMA_0_.D -11 1 -.names N_64_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF CYCLE_DMA_1_.D +.names N_259_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -438,7 +442,7 @@ pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 -.names N_232_i.BLIF N_233_i.BLIF cpu_est_0_.D +.names N_59_i.BLIF N_61_i.BLIF cpu_est_0_.D 11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 @@ -449,352 +453,406 @@ pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_un21_bgack_030_int_i_0_o2_2_x2 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D 1- 1 -1 1 -.names N_240_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names N_234_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_239_i_1.BLIF N_239_i_2.BLIF RST_DLY_1_.D +.names N_233_i_1.BLIF N_233_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_2_.D +.names N_232_i_1.BLIF N_232_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_44_0.BLIF inst_RW_000_INT.D -0 1 -.names N_45_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_46_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_47_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names N_49_0.BLIF inst_AS_000_DMA.D -0 1 -.names N_50_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_110_0.BLIF inst_AS_030_D0.D -0 1 -.names N_55_0.BLIF inst_VPA_D.D -0 1 -.names N_56_0.BLIF inst_DTACK_D0.D -0 1 -.names N_60_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +.names N_127_i.BLIF N_128_i.BLIF inst_DSACK1_INT.D 11 1 -.names N_301_0.BLIF inst_RESET_OUT.D +.names N_125_i.BLIF N_126_i.BLIF inst_AS_000_INT.D +11 1 +.names N_48_0.BLIF inst_AS_030_D0.D +0 1 +.names N_52_0.BLIF inst_VPA_D.D +0 1 +.names N_53_0.BLIF inst_DTACK_D0.D +0 1 +.names N_258_i_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D +11 1 +.names N_55_0.BLIF inst_RESET_OUT.D 0 1 .names N_9.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names N_34_0.BLIF BG_000DFFreg.D +.names N_31_0.BLIF BG_000DFFreg.D 0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +.names N_33_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_37_0.BLIF inst_UDS_000_INT.D +.names N_34_0.BLIF inst_UDS_000_INT.D 0 1 -.names N_38_0.BLIF inst_A0_DMA.D +.names N_35_0.BLIF inst_A0_DMA.D 0 1 -.names N_39_0.BLIF inst_AS_000_INT.D +.names N_36_0.BLIF inst_RW_000_DMA.D 0 1 -.names N_40_0.BLIF inst_DSACK1_INTreg.D +.names N_37_0.BLIF inst_VMA_INTreg.D 0 1 -.names N_41_0.BLIF inst_VMA_INTreg.D +.names N_39_0.BLIF inst_RW_000_INT.D 0 1 -.names N_43_0.BLIF inst_RW_000_DMA.D +.names N_40_0.BLIF inst_AS_030_000_SYNC.D 0 1 -.names N_100_i.BLIF inst_BGACK_030_INT_D.D +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_44_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_45_0.BLIF inst_DS_000_DMA.D +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_130.BLIF N_130_i +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names BGACK_000_c.BLIF N_349_i.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names N_131.BLIF N_131_i -0 1 -.names DTACK_c.BLIF DTACK_c_i +.names N_171.BLIF N_171_i 0 1 .names inst_CLK_030_H.BLIF CLK_030_H_i 0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_56_0 -11 1 -.names RW_000_c.BLIF RW_000_i +.names FPU_SENSE_c.BLIF FPU_SENSE_i 0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_55_0 -11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_6.BLIF N_6_i +.names N_121.BLIF N_121_i 0 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names N_6_i.BLIF RST_c.BLIF N_47_0 +.names N_255_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_255_0 11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i +.names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names N_26.BLIF N_26_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_26_i.BLIF RST_c.BLIF N_34_0 +.names N_265.BLIF N_270_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 11 1 -.names vcc_n_n - 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n +.names AS_000_c.BLIF AS_000_i 0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names gnd_n_n -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ -un1_amiga_bus_enable_low -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_25.BLIF N_25_i -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_25_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_24.BLIF N_24_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names N_24_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names N_17.BLIF N_17_i -0 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT -0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_17_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names N_4.BLIF N_4_i -0 1 -.names N_138_i.BLIF N_162.BLIF un1_DS_000_ENABLE_0_sqmuxa -11 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_4_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names N_3.BLIF N_3_i -0 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_3_i.BLIF RST_c.BLIF N_50_0 -11 1 -.names un21_fpu_cs_1.BLIF N_357.BLIF un21_fpu_cs -11 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_215.BLIF N_215_i -0 1 -.names un21_berr_1_0.BLIF N_357.BLIF un21_berr -11 1 -.names G_107.BLIF N_210_i -0 1 -.names N_216.BLIF N_216_i -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names G_108.BLIF N_211_i -0 1 -.names N_215_i.BLIF N_216_i.BLIF N_301_0 -11 1 -.names G_109.BLIF N_212_i -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_243_0 -11 1 -.names N_266.BLIF N_266_i -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_249.BLIF N_249_i -0 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names N_249_i.BLIF N_266_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +.names AS_030_i.BLIF RST_c.BLIF N_48_0 11 1 .names inst_AS_000_INT.BLIF AS_000_INT_i 0 1 -.names N_268.BLIF N_268_i +.names N_125.BLIF N_125_i 0 1 -.names un6_as_030.BLIF un6_as_030_i +.names inst_DSACK1_INT.BLIF DSACK1_INT_i 0 1 -.names N_268_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF \ -pos_clk_ds_000_dma_4_0_n -11 1 -.names CLK_030_c.BLIF CLK_030_c_i +.names N_126.BLIF N_126_i 0 1 -.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_236_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names N_297.BLIF N_297_i +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n 0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_160_i -11 1 -.names pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ -pos_clk_un21_bgack_030_int_i_0_i_2_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_n -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_100_i -11 1 -.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_186_0 -11 1 -.names N_157_i.BLIF N_304_i.BLIF N_183_0 -11 1 -.names N_304_i.BLIF nEXP_SPACE_c.BLIF N_182_0 -11 1 -.names N_157_i.BLIF N_160_i.BLIF N_181_0 -11 1 -.names N_228.BLIF N_228_i +.names vcc_n_n + 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n 0 1 -.names N_228_i.BLIF SM_AMIGA_i_7_.BLIF N_176_0 -11 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names N_127.BLIF N_127_i 0 1 -.names UDS_000_c.BLIF UDS_000_c_i +.names un5_e_0.BLIF un5_e 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_173_i -11 1 -.names N_304_i_1.BLIF CLK_000_D_2_.BLIF N_304_i -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names N_128.BLIF N_128_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names gnd_n_n +.names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 -.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_157_i -11 1 -.names AS_030_i.BLIF RST_c.BLIF N_110_0 -11 1 .names RW_c.BLIF RW_c_i 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low 11 1 -.names N_176_0.BLIF RW_c_i.BLIF N_106_0 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_270_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n 11 1 -.names N_284.BLIF N_284_i -0 1 -.names pos_clk_ipl_1_n.BLIF N_211_i.BLIF pos_clk_ipl_n +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 11 1 -.names N_334.BLIF N_334_i +.names a_decode_c_18__n.BLIF a_decode_i_18__n 0 1 -.names N_278.BLIF N_278_i +.names N_129.BLIF N_129_i 0 1 -.names N_279.BLIF N_279_i +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names N_332.BLIF N_332_i +.names a_decode_c_19__n.BLIF a_decode_i_19__n 0 1 -.names N_237_0_1.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_237_0 -11 1 -.names N_167.BLIF N_176_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 -11 1 -.names N_247.BLIF N_247_i +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names N_248.BLIF N_248_i +.names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 -.names N_246.BLIF N_246_i +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 .names un10_ciin.BLIF un10_ciin_i 0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_241_0 -11 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 -.names AS_030_D0_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_242_0 -11 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_48_i -11 1 -.names N_227.BLIF N_227_i +.names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_261_0 +11 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF N_65_0 +11 1 +.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_134.BLIF N_134_i +0 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names N_153.BLIF N_153_i +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_134_i.BLIF N_153_i.BLIF N_67_0 +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF un2_as_030_i +11 1 +.names G_107.BLIF N_206_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_263_i +11 1 +.names G_108.BLIF N_207_i +0 1 +.names N_263_i.BLIF SM_AMIGA_6_.BLIF N_265_i +11 1 +.names G_109.BLIF N_208_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0 +11 1 +.names CLK_000_D_2_.BLIF clk_000_d_i_2__n +0 1 +.names N_81.BLIF N_81_i +0 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_2__n.BLIF N_85_i +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_141.BLIF N_141_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_110_i.BLIF N_141_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +11 1 +.names N_147.BLIF N_147_i +0 1 +.names pos_clk_un21_bgack_030_int_i_0_i_1_n.BLIF \ +pos_clk_un19_bgack_030_int_n.BLIF pos_clk_un21_bgack_030_int_i_0_i_n +11 1 +.names N_145.BLIF N_145_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_269_i +11 1 +.names un7_as_030.BLIF un7_as_030_i +0 1 +.names N_85_i.BLIF SM_AMIGA_1_.BLIF N_90_i +11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names N_117_i.BLIF SM_AMIGA_i_7_.BLIF N_270_i +11 1 +.names N_269_i.BLIF SM_AMIGA_5_.BLIF N_271_0 +11 1 +.names N_96_0_3.BLIF nEXP_SPACE_c.BLIF N_96_0 +11 1 +.names N_84_0.BLIF sm_amiga_i_i_7__n.BLIF N_97_0 +11 1 +.names AS_000_DMA_i.BLIF CLK_030_c_i.BLIF N_98_0 +11 1 +.names N_282.BLIF N_282_i +0 1 +.names N_284.BLIF N_284_i +0 1 +.names pos_clk_un14_clk_000_ne_n.BLIF pos_clk_un14_clk_000_ne_i_n +0 1 +.names un5_e_0_1.BLIF N_284_i.BLIF un5_e_0 +11 1 +.names N_285.BLIF N_285_i +0 1 +.names N_291.BLIF N_291_i +0 1 +.names N_292.BLIF N_292_i +0 1 +.names N_192_i_1.BLIF N_292_i.BLIF N_192_i +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names N_17.BLIF N_17_i +0 1 +.names N_17_i.BLIF N_285_i.BLIF cpu_est_2_0_2__n +11 1 +.names pos_clk_ipl_1_n.BLIF N_207_i.BLIF pos_clk_ipl_n +11 1 +.names N_286.BLIF N_286_i +0 1 +.names N_288.BLIF N_288_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +11 1 +.names N_286_i.BLIF N_288_i.BLIF cpu_est_2_0_1__n +11 1 +.names N_289.BLIF N_289_i +0 1 +.names N_290.BLIF N_290_i +0 1 +.names N_289_i.BLIF N_290_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_280_i +11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_27.BLIF N_27_i +0 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_26.BLIF N_26_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names N_25.BLIF N_25_i +0 1 +.names N_25_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_4_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names N_14.BLIF N_14_i +0 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_15.BLIF N_15_i +0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_9 1- 1 -1 1 -.names N_225.BLIF N_225_i +.names N_16.BLIF N_16_i 0 1 -.names N_224.BLIF N_224_i +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names N_18.BLIF N_18_i +0 1 +.names N_18_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names N_21.BLIF N_21_i 0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_223.BLIF N_223_i -0 1 +.names N_21_i.BLIF RST_c.BLIF N_34_0 +11 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_16 1- 1 -1 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_22 +.names N_23.BLIF N_23_i +0 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names N_218.BLIF N_218_i -0 1 -.names N_218_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names N_23_i.BLIF RST_c.BLIF N_32_0 11 1 -.names N_217.BLIF N_217_i +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names N_217_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_23 +1- 1 +-1 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names N_213.BLIF N_213_i +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_25 +1- 1 +-1 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names N_319.BLIF N_319_i -0 1 -.names N_213_i.BLIF N_319_i.BLIF N_300_0 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_26 +1- 1 +-1 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names N_15.BLIF N_15_i -0 1 -.names N_15_i.BLIF RST_c.BLIF N_45_0 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_27 +1- 1 +-1 1 +.names inst_BGACK_030_INT_D.BLIF inst_BGACK_030_INTreg.BLIF N_96_0_1 11 1 -.names N_16.BLIF N_16_i -0 1 -.names N_16_i.BLIF RST_c.BLIF N_44_0 +.names AS_030_D0_i.BLIF sm_amiga_i_i_7__n.BLIF N_96_0_2 11 1 -.names N_22.BLIF N_22_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_38_0 +.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0_3 11 1 -.names AS_000_i.BLIF pos_clk_un21_bgack_030_int_i_0_o2_2_x2.BLIF \ +.names pos_clk_un21_bgack_030_int_i_0_x2.BLIF N_264_i.BLIF \ pos_clk_un21_bgack_030_int_i_0_i_1_n 11 1 -.names BGACK_030_INT_i.BLIF N_297_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_2_n +.names CLK_000_D_4_.BLIF clk_000_d_i_3__n.BLIF N_84_0_1 11 1 -.names N_199_i.BLIF N_200_i.BLIF N_238_i_1 +.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF N_84_0_2 11 1 -.names N_201_i.BLIF RST_c.BLIF N_238_i_2 +.names BERR_c.BLIF N_88_i.BLIF N_240_0_1 11 1 -.names N_203_i.BLIF N_204_i.BLIF N_239_i_1 +.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_205_i.BLIF RST_c.BLIF N_239_i_2 +.names N_263_i.BLIF N_291.BLIF N_289_1 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_289_2 +11 1 +.names N_269_i.BLIF N_280_i.BLIF N_290_1 +11 1 +.names N_291.BLIF VPA_D_i.BLIF N_290_2 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF pos_clk_un14_clk_000_ne_1_n +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF pos_clk_un14_clk_000_ne_2_n +11 1 +.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_153_1 +11 1 +.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_153_2 +11 1 +.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_153_3 +11 1 +.names N_153_1.BLIF N_153_2.BLIF N_153_4 +11 1 +.names N_153_3.BLIF fc_c_0__n.BLIF N_153_5 11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 @@ -810,11 +868,11 @@ pos_clk_un21_bgack_030_int_i_0_i_1_n 11 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 @@ -822,697 +880,641 @@ pos_clk_un21_bgack_030_int_i_0_i_1_n 11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_357_1 +.names N_130_i.BLIF N_131_i.BLIF N_260_i_1 11 1 .names pos_clk_un21_bgack_030_int_i_0_i_n.BLIF \ pos_clk_un21_bgack_030_int_i_0_n 0 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_357_2 +.names N_264_i.BLIF RST_c.BLIF N_260_i_2 11 1 -.names N_237_0.BLIF N_237 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_81 +11 1 +.names N_76_i.BLIF N_77_i.BLIF N_233_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_94 +11 1 +.names N_251_i.BLIF RST_c.BLIF N_233_i_2 +11 1 +.names N_254_0.BLIF N_254 0 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_357_3 +.names N_247_i.BLIF N_248_i.BLIF N_232_i_1 11 1 -.names N_241_0.BLIF N_241 +.names N_255_0.BLIF N_255 0 1 -.names N_357_1.BLIF N_357_2.BLIF N_357_4 +.names N_249_i.BLIF RST_c.BLIF N_232_i_2 11 1 -.names N_242_0.BLIF N_242 +.names N_261_0.BLIF N_261 0 1 -.names clk_000_d_i_1__n.BLIF AS_030_000_SYNC_i.BLIF N_304_i_1 +.names N_210_i.BLIF N_239.BLIF N_247_1 11 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 -11 1 -.names N_294.BLIF nEXP_SPACE_i.BLIF N_283 -11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 -11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_294 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_266_1 -11 1 -.names N_300_0.BLIF N_300 +.names N_65_0.BLIF N_65 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_266_2 +.names N_210_i.BLIF rst_dly_i_0__n.BLIF N_77_1 11 1 -.names AS_000_i.BLIF N_100_i.BLIF N_67_i_1 -11 1 -.names N_106_0.BLIF N_106 +.names N_67_0.BLIF N_67 0 1 -.names N_207_i.BLIF N_208_i.BLIF N_67_i_2 +.names N_91.BLIF N_269_i.BLIF N_83_1 11 1 -.names N_138_i.BLIF N_305_i.BLIF N_314_1 -11 1 -.names N_134_i.BLIF N_134 +.names N_269_i.BLIF N_269 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_314_2 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_88_1 11 1 -.names N_138_i.BLIF N_138 -0 1 -.names N_134_i.BLIF N_348.BLIF N_318_1 -11 1 -.names N_156_i.BLIF N_156 -0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_318_2 -11 1 -.names N_160_i.BLIF N_160 -0 1 -.names N_154_0.BLIF N_305_i.BLIF N_341_1 -11 1 -.names N_167_i.BLIF N_167 -0 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_341_2 -11 1 -.names N_172_i.BLIF N_172 -0 1 -.names N_167.BLIF N_284_i.BLIF N_151_i_1 -11 1 -.names N_173_i.BLIF N_173 -0 1 -.names N_138.BLIF N_334_i.BLIF N_143_i_1 -11 1 -.names N_181_0.BLIF N_181 -0 1 -.names N_166_i.BLIF N_278_i.BLIF N_141_i_1 -11 1 -.names N_182_0.BLIF N_182 -0 1 -.names N_332_i.BLIF RW_000_i.BLIF N_237_0_1 -11 1 -.names N_183_0.BLIF N_183 -0 1 -.names N_247_i.BLIF N_248_i.BLIF N_240_i_1 -11 1 -.names un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n.BLIF N_191 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_108 1- 1 -1 1 -.names N_246_i.BLIF RST_c.BLIF N_60_i_1 +.names N_62_i.BLIF N_64_i.BLIF N_142_i_1 11 1 -.names N_199_1.BLIF rst_dly_i_2__n.BLIF N_199 +.names N_278.BLIF nEXP_SPACE_i.BLIF N_135 11 1 -.names AS_000_i.BLIF N_100_i.BLIF N_64_i_1 +.names N_58_i.BLIF N_244_i.BLIF N_146_i_1 11 1 -.names N_205_1.BLIF rst_dly_i_1__n.BLIF N_205 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF N_136 11 1 -.names N_227_i.BLIF N_228_i.BLIF N_155_i_1 +.names N_78_i_0.BLIF N_79_i.BLIF N_234_i_1 11 1 -.names N_160_i.BLIF RST_c.BLIF N_209 -11 1 -.names N_138.BLIF N_225_i.BLIF N_147_i_1 -11 1 -.names AS_030_D0_i.BLIF N_181.BLIF N_319 -11 1 -.names N_172.BLIF N_224_i.BLIF N_145_i_1 -11 1 -.names AS_030_D0_i.BLIF N_357.BLIF N_213 -11 1 -.names N_138.BLIF N_223_i.BLIF N_139_i_1 -11 1 -.names N_216_1.BLIF RST_c.BLIF N_216 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_145 11 1 .names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 -.names BGACK_030_INT_i.BLIF N_173.BLIF N_217 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_278 11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_220_1 +.names N_264_i.BLIF RW_000_c.BLIF N_124_1 11 1 -.names BGACK_030_INT_i.BLIF N_173_i.BLIF N_218 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_147 11 1 -.names N_134_i.BLIF N_343.BLIF N_216_1 +.names N_153.BLIF BGACK_000_c.BLIF un21_berr_1 11 1 -.names N_220_1.BLIF cpu_est_i_3__n.BLIF N_220 +.names N_240.BLIF N_269_i.BLIF N_58 11 1 -.names N_214_0.BLIF rst_dly_i_0__n.BLIF N_205_1 +.names N_153.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 11 1 -.names N_169.BLIF sm_amiga_i_0__n.BLIF N_223 +.names N_263_i.BLIF SM_AMIGA_4_.BLIF N_110 11 1 -.names N_156.BLIF N_214_0.BLIF N_199_1 +.names N_114_i.BLIF N_115_i.BLIF N_140_i_1 11 1 -.names N_180.BLIF sm_amiga_i_3__n.BLIF N_224 -11 1 -.names N_212_i.BLIF N_210_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_185.BLIF sm_amiga_i_4__n.BLIF N_225 -11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +.names N_239_i.BLIF N_239 0 1 -.names N_182.BLIF sm_amiga_i_i_7__n.BLIF N_227 +.names N_116_i.BLIF N_117_i.BLIF N_154_i_1 11 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names N_138_i.BLIF SM_AMIGA_0_.BLIF N_228 -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CLK_030_H_i.BLIF N_186.BLIF N_246 -11 1 -.names N_80.BLIF as_000_int_0_un3_n +.names N_90_i.BLIF N_90 0 1 -.names N_142.BLIF RST_DLY_0_.BLIF N_247 +.names N_118_i.BLIF N_265.BLIF N_152_i_1 11 1 -.names N_167.BLIF N_80.BLIF as_000_int_0_un1_n -11 1 -.names N_166_i.BLIF rst_dly_i_0__n.BLIF N_248 -11 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_332 -11 1 -.names N_256.BLIF dsack1_int_0_un3_n +.names N_265_i.BLIF N_265 0 1 -.names N_138.BLIF SM_AMIGA_2_.BLIF N_278 +.names N_119_i.BLIF N_269.BLIF N_150_i_1 11 1 -.names N_169.BLIF N_256.BLIF dsack1_int_0_un1_n +.names N_120_i.BLIF N_263.BLIF N_148_i_1 11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_279 +.names N_171_i.BLIF N_263.BLIF N_144_i_1 11 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names N_179.BLIF sm_amiga_i_2__n.BLIF N_334 -11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +.names pos_clk_un19_bgack_030_int_i_n.BLIF pos_clk_un19_bgack_030_int_n 0 1 -.names N_183.BLIF sm_amiga_i_6__n.BLIF N_284 +.names N_121_i.BLIF RW_000_i.BLIF N_255_0_1 11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names N_156_i.BLIF RST_DLY_2_.BLIF N_343 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +.names N_280_i.BLIF N_280 0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_129_i.BLIF RST_c.BLIF N_258_i_1 11 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names N_357_4.BLIF N_357_3.BLIF N_357 -11 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names N_266_1.BLIF N_266_2.BLIF N_266 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names N_263_i.BLIF N_263 0 1 -.names N_186_0.BLIF N_186 -0 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_264_i.BLIF N_259_i_1 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_247_1.BLIF rst_dly_i_2__n.BLIF N_247 11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_297 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_282_1 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names N_236_0.BLIF N_236 -0 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +.names N_77_1.BLIF rst_dly_i_1__n.BLIF N_77 11 1 -.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n -0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names N_292.BLIF cpu_est_3_.BLIF N_284_1 11 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_268 +.names N_289_1.BLIF N_289_2.BLIF N_289 11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names N_134.BLIF cpu_est_0_3__un3_n -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_249 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_288_1 11 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_291 11 1 -.names cpu_est_3_.BLIF N_134.BLIF cpu_est_0_3__un1_n +.names pos_clk_un14_clk_000_ne_i_n.BLIF N_282_i.BLIF un5_e_0_1 11 1 -.names N_243_0.BLIF N_243 -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_196_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names N_290_1.BLIF N_290_2.BLIF N_290 11 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_215 +.names N_285_i.BLIF N_291_i.BLIF N_192_i_1 11 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_286 11 1 -.names N_134.BLIF cpu_est_0_2__un3_n -0 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_130 +.names N_208_i.BLIF N_206_i.BLIF pos_clk_ipl_1_n 11 1 -.names N_23.BLIF N_23_i -0 1 -.names cpu_est_2_.BLIF N_134.BLIF cpu_est_0_2__un1_n +.names N_288_1.BLIF cpu_est_i_3__n.BLIF N_288 11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_131 -11 1 -.names N_23_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_21.BLIF N_21_i -0 1 -.names N_134.BLIF cpu_est_0_1__un3_n -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_21_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names cpu_est_1_.BLIF N_134.BLIF cpu_est_0_1__un1_n -11 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names N_20.BLIF N_20_i -0 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 -1- 1 --1 1 -.names N_20_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 -1- 1 --1 1 -.names N_19.BLIF N_19_i -0 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names N_19_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_14.BLIF N_14_i -0 1 -.names N_160.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names N_14_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_130_i.BLIF N_160.BLIF amiga_bus_enable_dma_low_0_un1_n -11 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names CYCLE_DMA_0_.BLIF N_138_i.BLIF N_208 -11 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 -11 1 -.names N_160.BLIF rw_000_dma_0_un3_n -0 1 -.names cycle_dma_i_0__n.BLIF N_138.BLIF N_207 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names N_243.BLIF N_160.BLIF rw_000_dma_0_un1_n -11 1 -.names AS_000_c.BLIF N_138_i.BLIF N_349 -11 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_314_1.BLIF N_314_2.BLIF N_314 -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names N_236.BLIF as_000_dma_0_un3_n -0 1 -.names N_318_1.BLIF N_318_2.BLIF N_318 -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 -11 1 -.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_236.BLIF as_000_dma_0_un1_n -11 1 -.names N_153_i.BLIF cpu_est_i_2__n.BLIF N_348 -11 1 -.names N_27.BLIF N_27_i -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names N_134.BLIF rst_dly_i_2__n.BLIF N_201 -11 1 -.names N_27_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names N_237.BLIF ds_000_dma_0_un3_n -0 1 -.names N_142.BLIF N_343.BLIF N_200 -11 1 -.names N_28.BLIF N_28_i -0 1 -.names pos_clk_ds_000_dma_4_n.BLIF N_237.BLIF ds_000_dma_0_un1_n -11 1 -.names N_142.BLIF N_156_i.BLIF N_203 -11 1 -.names N_28_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names N_166_i.BLIF rst_dly_i_1__n.BLIF N_204 -11 1 -.names N_29.BLIF N_29_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_185_0.BLIF N_185 -0 1 -.names N_29_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names N_184_0.BLIF N_184 -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names N_180_0.BLIF N_180 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 .names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names N_179_0.BLIF N_179 -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n +.names N_280.BLIF cpu_est_2_.BLIF N_285 11 1 .names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names N_178_0.BLIF N_178 -0 1 -.names AS_030_D0_i.BLIF N_169.BLIF N_256_0 +.names N_280_i.BLIF cpu_est_i_2__n.BLIF N_17 11 1 .names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names N_171_i.BLIF N_171 -0 1 -.names N_318.BLIF N_318_i -0 1 -.names N_160.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names N_341_1.BLIF N_341_2.BLIF N_341 +.names cpu_est_0_.BLIF cpu_est_i_2__n.BLIF N_292 11 1 -.names N_314.BLIF N_314_i +.names N_94.BLIF amiga_bus_enable_dma_low_0_un3_n 0 1 -.names N_131_i.BLIF N_160.BLIF amiga_bus_enable_dma_high_0_un1_n +.names pos_clk_un14_clk_000_ne_1_n.BLIF pos_clk_un14_clk_000_ne_2_n.BLIF \ +pos_clk_un14_clk_000_ne_n 11 1 -.names N_165.BLIF inst_VPA_D.BLIF N_342 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_94.BLIF \ +amiga_bus_enable_dma_low_0_un1_n 11 1 -.names N_314_i.BLIF N_318_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names N_282_1.BLIF cpu_est_i_3__n.BLIF N_282 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +.names N_80_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n 11 1 -.names N_169_i.BLIF N_169 -0 1 -.names N_219.BLIF N_219_i -0 1 -.names inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n -0 1 -.names N_154_0.BLIF N_154 -0 1 -.names N_220.BLIF N_220_i -0 1 -.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un1_n +.names N_284_1.BLIF cpu_est_i_1__n.BLIF N_284 11 1 -.names N_165_0.BLIF N_165 +.names N_94.BLIF a0_dma_0_un3_n 0 1 -.names N_219_i.BLIF N_220_i.BLIF cpu_est_2_0_1__n +.names N_98_0.BLIF N_98 +0 1 +.names inst_A0_DMA.BLIF N_94.BLIF a0_dma_0_un1_n 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_i_m2_0__un0_n +.names N_97_0.BLIF N_97 +0 1 +.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names N_162_0.BLIF N_162 +.names N_84_0.BLIF N_84 0 1 -.names N_221.BLIF N_221_i +.names N_94.BLIF rw_000_dma_0_un3_n 0 1 -.names N_209.BLIF size_dma_0_0__un3_n +.names N_96_0.BLIF N_96 0 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF N_299 +.names inst_RW_000_DMA.BLIF N_94.BLIF rw_000_dma_0_un1_n 11 1 -.names N_348.BLIF N_348_i +.names N_271_0.BLIF N_271 0 1 -.names SIZE_DMA_0_.BLIF N_209.BLIF size_dma_0_0__un1_n +.names pos_clk_rw_000_dma_3_n.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n 11 1 -.names N_153_i.BLIF N_153 +.names N_263_i.BLIF SM_AMIGA_0_.BLIF N_117 +11 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_221_i.BLIF N_348_i.BLIF cpu_est_2_0_2__n +.names N_265_i.BLIF RW_c.BLIF N_141 +11 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names AS_030_i.BLIF N_96.BLIF N_134 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names N_153_4.BLIF N_153_5.BLIF N_153 +11 1 +.names N_255.BLIF ds_000_dma_0_un3_n +0 1 +.names CLK_030_H_i.BLIF N_98.BLIF N_129 +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_255.BLIF ds_000_dma_0_un1_n +11 1 +.names N_147.BLIF RST_c.BLIF N_127 +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names N_90_i.BLIF RST_c.BLIF N_128 +11 1 +.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un3_n +0 1 +.names N_145.BLIF RST_c.BLIF N_125 +11 1 +.names SIZE_DMA_1_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un1_n +11 1 +.names N_265_i.BLIF RST_c.BLIF N_126 +11 1 +.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ +size_dma_0_1__un0_n +11 1 +.names N_124_1.BLIF nEXP_SPACE_i.BLIF N_124 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un3_n +0 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_121 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names SIZE_DMA_0_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un1_n +11 1 +.names N_163.BLIF sm_amiga_i_2__n.BLIF N_171 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 .names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \ size_dma_0_0__un0_n 11 1 -.names N_142_0.BLIF N_142 +.names N_271.BLIF sm_amiga_i_4__n.BLIF N_120 +11 1 +.names N_24.BLIF N_24_i 0 1 -.names N_222.BLIF N_222_i +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names N_209.BLIF size_dma_0_1__un3_n +.names N_265.BLIF sm_amiga_i_5__n.BLIF N_119 +11 1 +.names N_24_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names N_97.BLIF sm_amiga_i_6__n.BLIF N_118 +11 1 +.names N_22.BLIF N_22_i 0 1 -.names N_134_i.BLIF N_214_0.BLIF N_298 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n 11 1 -.names N_221_i.BLIF N_222_i.BLIF N_196_i +.names N_84.BLIF sm_amiga_i_i_7__n.BLIF N_116 11 1 -.names SIZE_DMA_1_.BLIF N_209.BLIF size_dma_0_1__un1_n +.names N_22_i.BLIF RST_c.BLIF N_33_0 11 1 -.names N_80_0.BLIF N_80 +.names N_269.BLIF cpu_est_0_1__un3_n 0 1 -.names N_226.BLIF N_226_i +.names N_90.BLIF sm_amiga_i_0__n.BLIF N_114 +11 1 +.names N_20.BLIF N_20_i 0 1 -.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ -size_dma_0_1__un0_n +.names cpu_est_1_.BLIF N_269.BLIF cpu_est_0_1__un1_n 11 1 -.names N_134.BLIF cpu_est_i_0__n.BLIF N_232 +.names N_263_i.BLIF sm_amiga_i_1__n.BLIF N_115 11 1 -.names N_242.BLIF ds_000_enable_0_un3_n +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_243_0.BLIF N_243 0 1 -.names N_134_i.BLIF cpu_est_0_.BLIF N_233 -11 1 -.names N_231.BLIF N_231_i +.names N_19.BLIF N_19_i 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_242.BLIF ds_000_enable_0_un1_n +.names N_269.BLIF cpu_est_0_2__un3_n +0 1 +.names N_240_0.BLIF N_240 +0 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 11 1 -.names N_184.BLIF cpu_est_i_2__n.BLIF N_229 +.names cpu_est_2_.BLIF N_269.BLIF cpu_est_0_2__un1_n 11 1 -.names N_229.BLIF N_229_i +.names N_88_1.BLIF pos_clk_un14_clk_000_ne_n.BLIF N_88 +11 1 +.names N_8.BLIF N_8_i +0 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_89 +11 1 +.names N_8_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names N_269.BLIF cpu_est_0_3__un3_n +0 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_82 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names cpu_est_3_.BLIF N_269.BLIF cpu_est_0_3__un1_n +11 1 +.names N_83_1.BLIF RST_c.BLIF N_83 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names N_192_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_236.BLIF RST_DLY_0_.BLIF N_78 +11 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_92.BLIF rst_dly_i_0__n.BLIF N_79 +11 1 +.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names N_239_i.BLIF RST_DLY_2_.BLIF N_91 +11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_110_i.BLIF sm_amiga_i_3__n.BLIF N_244 +11 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_53_0 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_243.BLIF sm_amiga_i_1__n.BLIF N_62 +11 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_85_i.BLIF sm_amiga_i_2__n.BLIF N_64 +11 1 +.names N_249.BLIF N_249_i +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_269.BLIF cpu_est_i_0__n.BLIF N_59 +11 1 +.names N_248.BLIF N_248_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names N_269_i.BLIF cpu_est_0_.BLIF N_61 +11 1 +.names N_247.BLIF N_247_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names N_163_0.BLIF N_163 +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names BGACK_030_INT_i.BLIF N_242_i.BLIF N_245 +11 1 +.names N_77.BLIF N_77_i +0 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +0 1 +.names N_242_i.BLIF N_242 +0 1 +.names N_251.BLIF N_251_i +0 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names BGACK_030_INT_i.BLIF N_242.BLIF N_246 +11 1 +.names N_76.BLIF N_76_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_91.BLIF N_236.BLIF N_248 +11 1 +.names N_94.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names N_236_0.BLIF N_236 +0 1 +.names N_131.BLIF N_131_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_94.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names N_269.BLIF rst_dly_i_2__n.BLIF N_249 +11 1 +.names N_130.BLIF N_130_i +0 1 +.names N_81_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n +11 1 +.names N_269.BLIF RST_c.BLIF N_92 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_264_i +11 1 +.names N_254.BLIF as_000_dma_0_un3_n +0 1 +.names N_236.BLIF N_239_i.BLIF N_251 +11 1 +.names N_170.BLIF N_170_i +0 1 +.names pos_clk_un21_bgack_030_int_i_0_n.BLIF N_254.BLIF as_000_dma_0_un1_n +11 1 +.names N_92.BLIF rst_dly_i_1__n.BLIF N_76 +11 1 +.names BGACK_000_c.BLIF N_170_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_80 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n +11 1 +.names N_65.BLIF ds_000_enable_0_un3_n +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names N_123.BLIF N_123_i +0 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_65.BLIF ds_000_enable_0_un1_n +11 1 +.names N_94.BLIF RST_c.BLIF SIZE_DMA_3_sqmuxa +11 1 +.names N_124.BLIF N_124_i 0 1 .names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ ds_000_enable_0_un0_n 11 1 -.names N_178.BLIF cpu_est_2_.BLIF N_231 +.names N_210_i.BLIF N_269_i.BLIF N_87 11 1 -.names N_229_i.BLIF N_231_i.BLIF N_302_i +.names N_123_i.BLIF N_124_i.BLIF AMIGA_BUS_DATA_DIR_c_0 11 1 -.names N_300.BLIF as_030_000_sync_0_un3_n +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names N_167.BLIF sm_amiga_i_5__n.BLIF N_226 -11 1 -.names N_233.BLIF N_233_i +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n 0 1 -.names inst_AS_030_000_SYNC.BLIF N_300.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_153.BLIF cpu_est_2_.BLIF N_221 -11 1 -.names N_232.BLIF N_232_i +.names N_122.BLIF N_122_i 0 1 -.names inst_AS_030_D0.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names N_154.BLIF cpu_est_i_2__n.BLIF N_222 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names N_122_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names AS_000_c.BLIF N_263_i.BLIF N_170 +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_242_i +11 1 +.names N_67.BLIF as_030_000_sync_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_122 +11 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_239_i +11 1 +.names inst_AS_030_000_SYNC.BLIF N_67.BLIF as_030_000_sync_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_123 +11 1 +.names N_87.BLIF N_87_i +0 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names cycle_dma_i_0__n.BLIF N_263.BLIF N_130 +11 1 +.names N_87_i.BLIF RST_c.BLIF N_236_0 11 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n 0 1 -.names AS_030_D0_i.BLIF N_167.BLIF N_80_0 +.names N_246.BLIF N_246_i +0 1 +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +rw_000_int_0_un1_n 11 1 -.names N_106.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n +0 1 +.names N_246_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names N_343.BLIF N_343_i -0 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_219 -11 1 -.names N_343_i.BLIF RST_c.BLIF N_214_0 -11 1 -.names N_160.BLIF a0_dma_0_un3_n +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +.names N_245.BLIF N_245_i 0 1 -.names N_134.BLIF RST_c.BLIF N_166_i -11 1 -.names pos_clk_a0_dma_3_n.BLIF N_160.BLIF a0_dma_0_un1_n -11 1 -.names N_256_0.BLIF N_256 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_134_i +.names CYCLE_DMA_0_.BLIF N_263_i.BLIF N_131 11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +.names N_245_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_298.BLIF N_298_i +.names N_91.BLIF N_91_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 -1- 1 --1 1 -.names N_298_i.BLIF RST_c.BLIF N_142_0 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_8 1- 1 -1 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_153_i +.names N_91_i.BLIF RST_c.BLIF N_210_i 11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_154_0 +.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un19_bgack_030_int_i_n 11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_19 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 1- 1 -1 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_156_i +.names N_58.BLIF SM_AMIGA_3_.BLIF N_163_0 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_20 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_22 1- 1 -1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_305_i -11 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_299.BLIF N_299_i +.names N_59.BLIF N_59_i 0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_23 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_24 1- 1 -1 1 -.names N_299_i.BLIF sm_amiga_i_4__n.BLIF N_162_0 -11 1 +.names N_61.BLIF N_61_i +0 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names BERR_c.BLIF inst_DTACK_D0.BLIF N_165_0 -11 1 +.names N_62.BLIF N_62_i +0 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names N_134_i.BLIF SM_AMIGA_1_.BLIF N_169_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_341.BLIF N_341_i -0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names N_342.BLIF N_342_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_341_i.BLIF N_342_i.BLIF N_171_i -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_134_i.BLIF N_171.BLIF N_172_i -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_178_0 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_172_i.BLIF SM_AMIGA_3_.BLIF N_179_0 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names N_138_i.BLIF SM_AMIGA_4_.BLIF N_180_0 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_184_0 -11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_134_i.BLIF SM_AMIGA_5_.BLIF N_185_0 -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_203.BLIF N_203_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_204.BLIF N_204_i -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_205.BLIF N_205_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_200.BLIF N_200_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_199.BLIF N_199_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_201.BLIF N_201_i +.names N_64.BLIF N_64_i 0 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names AS_000_c.BLIF AS_000_i +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i 0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i +.names N_244.BLIF N_244_i 0 1 -.names N_208.BLIF N_208_i -0 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_207.BLIF N_207_i +.names N_80.BLIF N_80_i 0 1 .names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 -.names N_138_i.BLIF SM_AMIGA_6_.BLIF N_167_i -11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names N_78.BLIF N_78_i_0 0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_138_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +.names RW_000_c.BLIF RW_000_i 0 1 -.names N_349.BLIF N_349_i +.names N_79.BLIF N_79_i +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names N_82.BLIF N_82_i +0 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_83.BLIF N_83_i +0 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names N_82_i.BLIF N_83_i.BLIF N_55_0 +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_88.BLIF N_88_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_89.BLIF N_89_i +0 1 +.names N_58.BLIF N_58_i +0 1 +.names N_240_0_1.BLIF N_89_i.BLIF N_240_0 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names N_263_i.BLIF SM_AMIGA_2_.BLIF N_243_0 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names CLK_030_c_i.BLIF pos_clk_un21_bgack_030_int_i_0_i_n.BLIF N_254_0 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_114.BLIF N_114_i +0 1 +.names N_110.BLIF N_110_i +0 1 +.names N_115.BLIF N_115_i +0 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_116.BLIF N_116_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_117.BLIF N_117_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_118.BLIF N_118_i +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_119.BLIF N_119_i +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_120.BLIF N_120_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 @@ -1535,13 +1537,13 @@ as_030_000_sync_0_un0_n .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names inst_DSACK1_INTreg.BLIF DSACK1 +.names N_147_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_302_i.BLIF E +.names un5_e.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1559,7 +1561,7 @@ as_030_000_sync_0_un0_n .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_191.BLIF AMIGA_BUS_ENABLE_HIGH +.names N_108.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 .names un10_ciin.BLIF CIIN @@ -1571,6 +1573,15 @@ as_030_000_sync_0_un0_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 0 0 @@ -1604,13 +1615,10 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C 1 1 0 0 .names CLK_000_D_1_.BLIF CLK_000_D_2_.D @@ -1619,6 +1627,18 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF CLK_000_D_2_.C 1 1 0 0 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +0 0 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -1658,28 +1678,10 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 0 0 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_AS_030_D0.C @@ -1700,12 +1702,6 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C -1 1 -0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -1721,46 +1717,58 @@ as_030_000_sync_0_un0_n .names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -0 0 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names un3_size.BLIF SIZE_1_ +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 0 0 .names gnd_n_n.BLIF AHIGH_31_ 1 1 0 0 -.names un6_as_030_i.BLIF AS_030 +.names un7_as_030_i.BLIF AS_030 1 1 0 0 -.names un4_as_000_i.BLIF AS_000 +.names N_145_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1778,7 +1786,7 @@ as_030_000_sync_0_un0_n .names inst_RW_000_DMA.BLIF RW 1 1 0 0 -.names un4_size.BLIF SIZE_0_ +.names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 .names gnd_n_n.BLIF AHIGH_30_ @@ -1970,61 +1978,61 @@ as_030_000_sync_0_un0_n .names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 -.names N_283.BLIF AS_030.OE +.names N_135.BLIF AS_030.OE 1 1 0 0 -.names un1_as_000_i.BLIF AS_000.OE +.names N_136.BLIF AS_000.OE 1 1 0 0 -.names un1_as_000_i.BLIF RW_000.OE +.names N_136.BLIF RW_000.OE 1 1 0 0 -.names un1_as_000_i.BLIF UDS_000.OE +.names N_136.BLIF UDS_000.OE 1 1 0 0 -.names un1_as_000_i.BLIF LDS_000.OE +.names N_136.BLIF LDS_000.OE 1 1 0 0 -.names N_48_i.BLIF SIZE_0_.OE +.names un2_as_030_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_48_i.BLIF SIZE_1_.OE +.names un2_as_030_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_24_.OE +.names N_135.BLIF AHIGH_24_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_25_.OE +.names N_135.BLIF AHIGH_25_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_26_.OE +.names N_135.BLIF AHIGH_26_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_27_.OE +.names N_135.BLIF AHIGH_27_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_28_.OE +.names N_135.BLIF AHIGH_28_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_29_.OE +.names N_135.BLIF AHIGH_29_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_30_.OE +.names N_135.BLIF AHIGH_30_.OE 1 1 0 0 -.names N_283.BLIF AHIGH_31_.OE +.names N_135.BLIF AHIGH_31_.OE 1 1 0 0 -.names N_283.BLIF A_0_.OE +.names N_135.BLIF A_0_.OE 1 1 0 0 .names un21_berr.BLIF BERR.OE 1 1 0 0 -.names N_294.BLIF RW.OE +.names N_278.BLIF RW.OE 1 1 0 0 -.names N_283.BLIF DS_030.OE +.names N_135.BLIF DS_030.OE 1 1 0 0 .names nEXP_SPACE_c.BLIF DSACK1.OE @@ -2033,14 +2041,9 @@ as_030_000_sync_0_un0_n .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_241.BLIF CIIN.OE +.names N_261.BLIF CIIN.OE 1 1 0 0 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0 -01 1 -10 1 -11 0 -00 0 .names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_107 01 1 10 1 @@ -2056,13 +2059,12 @@ as_030_000_sync_0_un0_n 10 1 11 0 00 0 -.names CYCLE_DMA_1_.BLIF N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2 +.names CYCLE_DMA_1_.BLIF N_131.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un21_bgack_030_int_i_0_o2_2_x2 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un21_bgack_030_int_i_0_x2 01 1 10 1 11 0 diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd deleted file mode 100644 index 0563cbc..0000000 --- a/Logic/BUS68030.cmd +++ /dev/null @@ -1,8 +0,0 @@ -STYFILENAME: 68030_tk.sty -PROJECT: BUS68030 -WORKING_PATH: "c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic" -MODULE: BUS68030 -VHDL_FILE_LIST: 68030-68000-bus.vhd -OUTPUT_FILE_NAME: BUS68030 -SUFFIX_NAME: edi -PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 6b7c176..9be7bc7 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 9 14 23 54 22) + (timeStamp 2016 10 6 21 34 50) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -140,6 +140,12 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -162,14 +168,14 @@ ) (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_D_2 "CLK_000_D[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_D_3 "CLK_000_D[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_4 "CLK_000_D[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -194,19 +200,9 @@ ) (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -220,8 +216,6 @@ ) (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_OUT_PRE_25 (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) @@ -232,21 +226,29 @@ ) (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) @@ -323,529 +325,531 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_0_a3 "pos_clk.un6_bg_030_0_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_110 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_1 "pos_clk.CYCLE_DMA_5_1_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i "pos_clk.CYCLE_DMA_5_1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_2_0_0_a3_0_1_1 "cpu_est_2_0_0_a3_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_2_0_0_a3_0_1 "cpu_est_2_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_1_3 "cpu_est_2_i_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_3 "cpu_est_2_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_110_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_110 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_1 "pos_clk.CYCLE_DMA_5_1_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_0 "pos_clk.CYCLE_DMA_5_1_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_0 "SM_AMIGA_srsts_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_0 "SM_AMIGA_srsts_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_0_a3_1 "pos_clk.un6_bg_030_0_a2_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a3 "pos_clk.un9_clk_000_pe_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0_1 "pos_clk.un9_clk_000_pe_0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0_2 "pos_clk.un9_clk_000_pe_0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0 "pos_clk.un9_clk_000_pe_0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_6 "SM_AMIGA_srsts_i_0_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_6 "SM_AMIGA_srsts_i_0_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_2 "SM_AMIGA_srsts_i_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_2 "SM_AMIGA_srsts_i_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_1 "SM_AMIGA_srsts_i_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1 "SM_AMIGA_srsts_i_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_1_0 "SM_AMIGA_nss_i_i_0_0_o2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_0 "SM_AMIGA_nss_i_i_0_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_1 "pos_clk.CYCLE_DMA_5_0_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_2 "pos_clk.CYCLE_DMA_5_0_i_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0 "pos_clk.CYCLE_DMA_5_0_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_1 "pos_clk.un9_clk_000_pe_0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_2 "pos_clk.un9_clk_000_pe_0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_2_o3_1 "pos_clk.un21_bgack_030_int_i_0_o2_2_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_2_o3_2 "pos_clk.un21_bgack_030_int_i_0_o2_2_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_2_o3 "pos_clk.un21_bgack_030_int_i_0_o2_2_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_0 "SM_AMIGA_srsts_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_1_0 "SM_AMIGA_nss_i_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0 "SM_AMIGA_nss_i_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_6 "SM_AMIGA_srsts_i_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_6 "SM_AMIGA_srsts_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_5 "SM_AMIGA_srsts_i_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_5 "SM_AMIGA_srsts_i_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_4 "SM_AMIGA_srsts_i_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_4 "SM_AMIGA_srsts_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_2 "SM_AMIGA_srsts_i_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_2 "SM_AMIGA_srsts_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_a2_0_1_3 "SM_AMIGA_srsts_i_o3_i_a2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_a2_0_3 "SM_AMIGA_srsts_i_o3_i_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_3 "SM_AMIGA_srsts_i_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_3 "SM_AMIGA_srsts_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a2_1 "pos_clk.un6_bg_030_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a2 "pos_clk.un6_bg_030_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_2 "pos_clk.CYCLE_DMA_5_0_i_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_a2_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2_0_4 "pos_clk.un34_as_030_d0_i_a2_0_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2_0_5 "pos_clk.un34_as_030_d0_i_a2_0_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2_0 "pos_clk.un34_as_030_d0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_o2_3 "SM_AMIGA_srsts_i_o3_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_218_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_217_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_319_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i_i "pos_clk.un35_as_030_d0_0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_1 "pos_clk.un9_clk_000_pe_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_2 "pos_clk.un9_clk_000_pe_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3 "pos_clk.un9_clk_000_pe_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_0_1 "pos_clk.un9_clk_000_pe_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_0_2 "pos_clk.un9_clk_000_pe_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_0 "pos_clk.un9_clk_000_pe_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_ne_0_a2_0_a3_1 "pos_clk.un14_clk_000_ne_0_a2_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_ne_0_a2_0_a3_2 "pos_clk.un14_clk_000_ne_0_a2_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_ne_0_a2_0_a3 "pos_clk.un14_clk_000_ne_0_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2_0_1 "pos_clk.un34_as_030_d0_i_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2_0_2 "pos_clk.un34_as_030_d0_i_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2_0_3 "pos_clk.un34_as_030_d0_i_a2_0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_o2_1 "pos_clk.un34_as_030_d0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_o2_2 "pos_clk.un34_as_030_d0_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_o2_3 "pos_clk.un34_as_030_d0_i_o2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_o2 "pos_clk.un34_as_030_d0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_1 "pos_clk.un21_bgack_030_int_i_0_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o2 "pos_clk.un21_bgack_030_int_i_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o2_1_0 "SM_AMIGA_nss_i_i_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o2_2_0 "SM_AMIGA_nss_i_i_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o2_0 "SM_AMIGA_nss_i_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_o2_1_3 "SM_AMIGA_srsts_i_o3_i_o2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_14_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_i_a2_i_i "pos_clk.RW_000_INT_5_i_a2_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_290_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_i "pos_clk.un9_clk_000_pe_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_o2_i_3 "cpu_est_2_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_i_6 "SM_AMIGA_srsts_i_0_o2_0_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_284_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_334_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_278_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_279_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_247_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_248_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_246_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un13_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_297_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_2_o3_i "pos_clk.un21_bgack_030_int_i_0_o2_2_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_o3_i "pos_clk.CYCLE_DMA_5_0_i_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_6 "SM_AMIGA_srsts_i_0_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i_o2_i "pos_clk.un35_as_030_d0_0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_ne_i "pos_clk.un14_clk_000_ne_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_285_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_291_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_292_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_i_2 "cpu_est_2_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_286_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_288_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_i_1 "cpu_est_2_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_289_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_i "pos_clk.un34_as_030_d0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_PE_0_o3_i_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_6 "SM_AMIGA_srsts_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_o2_i_0 "SM_AMIGA_nss_i_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_2 "CLK_000_D_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_i "pos_clk.un21_bgack_030_int_i_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_156_i_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_4 "SM_AMIGA_srsts_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_o2_i "pos_clk.un34_as_030_d0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_171_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0_i "pos_clk.RW_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_o2_i_3 "SM_AMIGA_srsts_i_o3_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_1 "SM_AMIGA_srsts_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_246_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_245_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un19_bgack_030_int_i_0 "pos_clk.un19_bgack_030_int_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_2 "SM_AMIGA_srsts_i_o3_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_59_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_61_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_62_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_64_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_244_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_78_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_79_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_82_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_76_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_i "pos_clk.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_DMA_3_0_i "pos_clk.RW_000_DMA_3_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_i "pos_clk.DS_000_DMA_4_f0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_87_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_216_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_266_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_249_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_268_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_0_0_i "pos_clk.DS_000_DMA_4_f0_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_6_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_249_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_248_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_247_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_77_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_251_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_0_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_203_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_204_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_205_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_200_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_199_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_201_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_207_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_a2_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_258_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_349_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_i "pos_clk.un6_bgack_000_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_o2_i_3 "cpu_est_2_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_299_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_2_i_3 "SM_AMIGA_srsts_i_0_0_o2_2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_341_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_342_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_1_i_3 "SM_AMIGA_srsts_i_0_0_o2_1_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_0_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_2 "SM_AMIGA_srsts_i_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_348_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_229_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_233_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_232_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_343_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_0_o3_i_a2_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_298_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_28_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_29_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_318_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_314_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_i "pos_clk.un9_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_14_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_UDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_a3_3 "cpu_est_2_i_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a3_2 "cpu_est_2_0_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a3_1 "cpu_est_2_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_109 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_108 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_107 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0_a3_0_0 "cpu_est_0_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0_a3_0 "cpu_est_0_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_5 "SM_AMIGA_srsts_i_0_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_4 "SM_AMIGA_srsts_i_0_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_3 "SM_AMIGA_srsts_i_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_0 "SM_AMIGA_srsts_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0 "pos_clk.un9_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_117_1_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_2 "SM_AMIGA_srsts_i_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_1 "SM_AMIGA_srsts_i_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_o2 "pos_clk.un9_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_o2_3 "cpu_est_2_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_0_o3_i_a2_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLYlde_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_117_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0_0 "cpu_est_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_0_3 "cpu_est_2_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_258_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_a2_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_x2 "pos_clk.CYCLE_DMA_5_1_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_2 "SM_AMIGA_srsts_i_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_1_3 "SM_AMIGA_srsts_i_0_0_o2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_o2_0 "SM_AMIGA_srsts_i_0_o2_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_2_3 "SM_AMIGA_srsts_i_0_0_o2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_102 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_a3 "pos_clk.CYCLE_DMA_5_0_i_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0_0 "SM_AMIGA_nss_i_i_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un3_as_030_i_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_1 "SM_AMIGA_srsts_i_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_220 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_as_030_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_rw_i_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_0_0_a3 "pos_clk.DS_000_DMA_4_f0_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_221 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance un21_berr_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_o3 "pos_clk.CYCLE_DMA_5_0_i_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_2_x2 "pos_clk.un21_bgack_030_int_i_0_o2_2_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_0_0 "pos_clk.DS_000_DMA_4_f0_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un21_bgack_030_int_i_0_o2_2_a2 "pos_clk.un21_bgack_030_int_i_0_o2_2_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_i_a2_i "pos_clk.RW_000_INT_5_i_a2_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i_o2_0 "pos_clk.un35_as_030_d0_0_i_o2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i_o2 "pos_clk.un35_as_030_d0_0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_6 "SM_AMIGA_srsts_i_0_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_222 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i_a3 "pos_clk.un35_as_030_d0_0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i_a3_0 "pos_clk.un35_as_030_d0_0_i_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_0 "pos_clk.SIZE_DMA_6_0_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_1 "pos_clk.SIZE_DMA_6_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0 "SM_AMIGA_nss_i_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_6 "SM_AMIGA_srsts_i_0_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_A0_DMA_3_0_a2_0_a3 "pos_clk.A0_DMA_3_0_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un35_as_030_d0_0_i "pos_clk.un35_as_030_d0_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_0 "pos_clk.SIZE_DMA_6_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_1 "pos_clk.SIZE_DMA_6_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_212_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_229 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_230 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_227 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_228 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_225 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_80_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_a2 "pos_clk.DS_000_DMA_4_f0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance I_226 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_223 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_224 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_210_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_211_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_a2 "pos_clk.CYCLE_DMA_5_0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_a2 "pos_clk.un6_bgack_000_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0 "pos_clk.DS_000_DMA_4_f0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_DMA_3_0 "pos_clk.RW_000_DMA_3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_o2 "pos_clk.CYCLE_DMA_5_1_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_102 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance un6_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_117_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a2 "pos_clk.un5_bgack_030_int_d_i_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_117_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_2 "SM_AMIGA_srsts_i_o3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a4_2 "SM_AMIGA_srsts_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_227 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_228 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un19_bgack_030_int "pos_clk.un19_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_110_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_3 "SM_AMIGA_srsts_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_1 "SM_AMIGA_srsts_i_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_1 "SM_AMIGA_srsts_i_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_a2_0_0 "cpu_est_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_0_a2_0 "cpu_est_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_a2_3 "SM_AMIGA_srsts_i_o3_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_58_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_0 "SM_AMIGA_nss_i_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_0 "SM_AMIGA_srsts_i_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_0_sqmuxa_0_o3_i_o2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_1 "SM_AMIGA_srsts_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_0 "cpu_est_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_a2_1_3 "SM_AMIGA_srsts_i_o3_i_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_4 "SM_AMIGA_srsts_i_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_5 "SM_AMIGA_srsts_i_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_6 "SM_AMIGA_srsts_i_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a2_0_0 "SM_AMIGA_nss_i_i_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DSACK1_INT_1_i_a2 "pos_clk.DSACK1_INT_1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_rw_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_as_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AS_000_INT_1_i_a2 "pos_clk.AS_000_INT_1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_231 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un7_as_030_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_000_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_as_030_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_230 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i_a2 "pos_clk.un34_as_030_d0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0_i_o2_1 "SM_AMIGA_srsts_i_o3_0_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_6 "SM_AMIGA_srsts_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_PE_0_o3_i_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un21_bgack_030_int_i_0_x2 "pos_clk.un21_bgack_030_int_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance un2_as_030_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d0_i "pos_clk.un34_as_030_d0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_a2_3 "cpu_est_2_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_1 "cpu_est_2_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_2 "cpu_est_2_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_a3_3 "cpu_est_2_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_6 "SM_AMIGA_srsts_i_0_o2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_4 "SM_AMIGA_srsts_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0 "SM_AMIGA_srsts_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_156_i_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_235 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_236 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_233 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_234 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_107 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_108 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_109 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_o2_3 "cpu_est_2_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_1 "cpu_est_2_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_2 "cpu_est_2_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_a2_0_3 "cpu_est_2_i_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_207_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_239 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_240 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_237 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_238 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_81_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_UDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un7_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un6_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -854,28 +858,29 @@ (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__r)) - (portRef I0 (instanceRef un1_as_000_0)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_o2)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) + (portRef I0 (instanceRef un1_as_000_i_a2)) + (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2_1)) (portRef I0 (instanceRef BGACK_030)) )) (net VCC (joined (portRef I0 (instanceRef AVEC)) )) + (net un5_e (joined + (portRef O (instanceRef un5_e_0_i)) + (portRef I0 (instanceRef E)) + )) (net VMA_INT (joined (portRef Q (instanceRef VMA_INT)) (portRef I0 (instanceRef VMA_INT_0_n)) @@ -899,117 +904,100 @@ (portRef O (instanceRef un1_amiga_bus_enable_low)) (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) )) - (net un6_as_030 (joined - (portRef O (instanceRef un6_as_030_0_a2_0_a3)) - (portRef I0 (instanceRef un6_as_030_i)) - )) - (net un3_size (joined - (portRef O (instanceRef un3_size)) - (portRef I0 (instanceRef SIZE_1)) - )) - (net un4_size (joined - (portRef O (instanceRef un4_size)) - (portRef I0 (instanceRef SIZE_0)) - )) - (net un1_LDS_000_INT (joined - (portRef O (instanceRef un1_LDS_000_INT_i)) - (portRef I0 (instanceRef LDS_000)) + (net un7_as_030 (joined + (portRef O (instanceRef un7_as_030_0_a2)) + (portRef I0 (instanceRef un7_as_030_i)) )) (net un1_UDS_000_INT (joined (portRef O (instanceRef un1_UDS_000_INT_i)) (portRef I0 (instanceRef UDS_000)) )) + (net un1_LDS_000_INT (joined + (portRef O (instanceRef un1_LDS_000_INT_i)) + (portRef I0 (instanceRef LDS_000)) + )) (net un1_SM_AMIGA_0_sqmuxa_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_i)) (portRef I1 (instanceRef RW_000_INT_0_m)) (portRef I0 (instanceRef RW_000_INT_0_r)) )) (net un1_DS_000_ENABLE_0_sqmuxa (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_a3)) + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_i)) (portRef I0 (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_i)) - )) - (net un4_as_000 (joined - (portRef O (instanceRef un4_as_000)) - (portRef I0 (instanceRef un4_as_000_i)) )) (net un10_ciin (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3)) + (portRef O (instanceRef un10_ciin_0_a2)) (portRef I0 (instanceRef un10_ciin_i)) (portRef I0 (instanceRef CIIN)) )) (net un21_fpu_cs (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3)) + (portRef O (instanceRef un21_fpu_cs_0_a2)) (portRef I0 (instanceRef un21_fpu_cs_i)) )) (net un21_berr (joined - (portRef O (instanceRef un21_berr_0_a2_0_a3)) + (portRef O (instanceRef un21_berr_0_a2)) (portRef OE (instanceRef BERR)) )) (net un6_ds_030 (joined (portRef O (instanceRef un6_ds_030)) (portRef I0 (instanceRef un6_ds_030_i)) )) - (net (rename cpu_est_2 "cpu_est[2]") (joined - (portRef Q (instanceRef cpu_est_2)) - (portRef I1 (instanceRef un5_e_0_i_a3_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_2)) - (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) - )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef un5_e_0_i_o2_0)) - (portRef I0 (instanceRef cpu_est_2_i_0_0_o2_3)) - (portRef I0 (instanceRef cpu_est_i_3)) (portRef I0 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_i_3)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3_1)) + (portRef I1 (instanceRef un5_e_0_a3_0_1)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2)) - (portRef I1 (instanceRef cpu_est_0_0_0_a3_0_0)) + (portRef I0 (instanceRef cpu_est_2_i_0_a2_0_3)) + (portRef I0 (instanceRef cpu_est_2_i_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_0_0_a2_0_0)) (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1_1)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef un5_e_0_i_o2)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_1)) (portRef I0 (instanceRef cpu_est_0_1__m)) + (portRef I1 (instanceRef cpu_est_2_i_0_o2_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_1)) (portRef I0 (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef un5_e_0_a3_1)) )) - (net AS_000_INT (joined - (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef AS_000_INT_0_n)) + (net (rename cpu_est_2 "cpu_est[2]") (joined + (portRef Q (instanceRef cpu_est_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef cpu_est_2_i_0_a3_3)) + (portRef I1 (instanceRef un5_e_0_a3_1)) )) (net AMIGA_BUS_ENABLE_DMA_LOW (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) (portRef I0 (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3_1)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_1)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_o2)) + (portRef I1 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_1)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_a3)) (portRef I0 (instanceRef AS_000_DMA_0_n)) (portRef I0 (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) @@ -1018,64 +1006,58 @@ )) (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_x2)) - (portRef I0 (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_x2)) (portRef I0 (instanceRef G_102)) + (portRef I0 (instanceRef CYCLE_DMA_i_0)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_x2)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) - )) - (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined - (portRef Q (instanceRef SIZE_DMA_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_i_0)) - (portRef I0 (instanceRef un4_size)) - )) - (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined - (portRef Q (instanceRef SIZE_DMA_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_i_1)) - (portRef I0 (instanceRef un3_size)) + (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_x2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_i_a2_1_3)) )) - (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined - (portRef Q (instanceRef CLK_000_D_1)) - (portRef I0 (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2)) - (portRef I0 (instanceRef CLK_000_D_i_1)) - (portRef D (instanceRef CLK_000_D_2)) + (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined + (portRef Q (instanceRef CLK_000_D_2)) + (portRef I0 (instanceRef CLK_000_D_i_2)) + (portRef D (instanceRef CLK_000_D_3)) + )) + (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined + (portRef Q (instanceRef CLK_000_D_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_1)) + (portRef I0 (instanceRef CLK_000_D_i_3)) + (portRef D (instanceRef CLK_000_D_4)) )) (net DTACK_D0 (joined (portRef Q (instanceRef DTACK_D0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2_3)) + (portRef I0 (instanceRef DTACK_D0_i)) )) (net RESET_OUT (joined (portRef Q (instanceRef RESET_OUT)) - (portRef I1 (instanceRef un1_as_000_0)) (portRef I0 (instanceRef RESET_OUT_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_i_a3)) - (portRef I1 (instanceRef un1_rw_i_a2_0_a2)) + (portRef I1 (instanceRef un1_as_000_i_a2)) + (portRef I1 (instanceRef un1_rw_i_a2)) + (portRef I0 (instanceRef RESET_OUT_2_0_a2)) + )) + (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined + (portRef Q (instanceRef CLK_000_D_1)) + (portRef I0 (instanceRef N_156_i_0_o2_i_o2)) + (portRef I0 (instanceRef CLK_000_D_i_1)) + (portRef D (instanceRef CLK_000_D_2)) )) (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined (portRef Q (instanceRef CLK_000_D_0)) - (portRef I0 (instanceRef N_258_i_0_o2)) + (portRef I0 (instanceRef CLK_000_PE_0_o3_i_o2_i_o2)) (portRef I0 (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2)) (portRef D (instanceRef CLK_000_D_1)) )) (net CLK_OUT_PRE_50 (joined (portRef Q (instanceRef CLK_OUT_PRE_50)) (portRef I0 (instanceRef CLK_OUT_PRE_50_i)) - (portRef I1 (instanceRef CLK_OUT_PRE_25_0)) - )) - (net CLK_OUT_PRE_25 (joined - (portRef Q (instanceRef CLK_OUT_PRE_25)) - (portRef I0 (instanceRef CLK_OUT_PRE_25_0)) (portRef D (instanceRef CLK_OUT_PRE_D)) )) (net CLK_OUT_PRE_D (joined @@ -1094,74 +1076,82 @@ (portRef Q (instanceRef IPL_D0_2)) (portRef I0 (instanceRef G_109)) )) - (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined - (portRef Q (instanceRef CLK_000_D_2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) + (net (rename CLK_000_D_4 "CLK_000_D[4]") (joined + (portRef Q (instanceRef CLK_000_D_4)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0)) )) (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a2)) (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) )) (net AMIGA_BUS_ENABLE_DMA_HIGH (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__n)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - )) - (net DSACK1_INT (joined - (portRef Q (instanceRef DSACK1_INT)) - (portRef I0 (instanceRef DSACK1_INT_0_n)) - (portRef I0 (instanceRef DSACK1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) )) (net (rename pos_clk_ipl "pos_clk.ipl") (joined (portRef O (instanceRef G_110)) (portRef I1 (instanceRef IPL_030_0_2__m)) (portRef I0 (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__r)) (portRef I1 (instanceRef IPL_030_0_1__m)) (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) )) - (net LDS_000_INT (joined - (portRef Q (instanceRef LDS_000_INT)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) - (portRef I0 (instanceRef LDS_000_INT_i)) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) )) - (net DS_000_ENABLE (joined - (portRef Q (instanceRef DS_000_ENABLE)) - (portRef I0 (instanceRef DS_000_ENABLE_0_n)) - (portRef I0 (instanceRef un1_UDS_000_INT)) - (portRef I0 (instanceRef un1_LDS_000_INT)) + (net AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) (portRef I0 (instanceRef UDS_000_INT_0_n)) (portRef I0 (instanceRef UDS_000_INT_i)) )) + (net DS_000_ENABLE (joined + (portRef Q (instanceRef DS_000_ENABLE)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) + (portRef I0 (instanceRef un1_LDS_000_INT)) + (portRef I0 (instanceRef un1_UDS_000_INT)) + )) + (net LDS_000_INT (joined + (portRef Q (instanceRef LDS_000_INT)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + (portRef I0 (instanceRef LDS_000_INT_i)) + )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_a2_0_o2_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_a2)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) (portRef I0 (instanceRef SM_AMIGA_i_4)) - )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_i_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3_i_o2_i_a2)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) )) + (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined + (portRef Q (instanceRef SIZE_DMA_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_0)) + )) + (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined + (portRef Q (instanceRef SIZE_DMA_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_1)) + )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) (portRef I0 (instanceRef RW_000_INT_0_n)) @@ -1169,59 +1159,76 @@ )) (net RW_000_DMA (joined (portRef Q (instanceRef RW_000_DMA)) - (portRef I0 (instanceRef RW_000_DMA_0_n)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) (portRef I0 (instanceRef RW)) )) (net (rename RST_DLY_0 "RST_DLY[0]") (joined (portRef Q (instanceRef RST_DLY_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_a2)) + (portRef I0 (instanceRef RST_DLY_e2_i_o2_0)) (portRef I0 (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a3)) )) (net (rename RST_DLY_1 "RST_DLY[1]") (joined (portRef Q (instanceRef RST_DLY_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_o2_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_o2_0)) (portRef I0 (instanceRef RST_DLY_i_1)) )) (net (rename RST_DLY_2 "RST_DLY[2]") (joined (portRef Q (instanceRef RST_DLY_2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1_a2)) (portRef I0 (instanceRef RST_DLY_i_2)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_0_a2)) )) (net A0_DMA (joined (portRef Q (instanceRef A0_DMA)) - (portRef I0 (instanceRef A0_DMA_0_n)) + (portRef I0 (instanceRef A0_DMA_0_m)) (portRef I0 (instanceRef A_0)) )) - (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined - (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3)) - (portRef I0 (instanceRef A0_DMA_0_m)) + (net (rename pos_clk_un9_clk_000_pe "pos_clk.un9_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) (portRef I0 (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_a3)) + )) + (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + )) + (net DSACK1_INT (joined + (portRef Q (instanceRef DSACK1_INT)) + (portRef I0 (instanceRef DSACK1_INT_i)) + )) + (net AS_000_INT (joined + (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef AS_000_INT_i)) )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_5)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) (portRef I0 (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) (portRef I0 (instanceRef SM_AMIGA_i_2)) )) - (net N_7 (joined + (net N_4 (joined + (portRef O (instanceRef AS_000_DMA_0_p)) + (portRef I0 (instanceRef N_4_i)) + )) + (net N_6 (joined (portRef O (instanceRef SIZE_DMA_0_0__p)) (portRef D (instanceRef SIZE_DMA_0)) )) - (net N_8 (joined + (net N_7 (joined (portRef O (instanceRef SIZE_DMA_0_1__p)) (portRef D (instanceRef SIZE_DMA_1)) )) @@ -1241,6 +1248,10 @@ (portRef O (instanceRef cpu_est_0_3__p)) (portRef D (instanceRef cpu_est_3)) )) + (net N_14 (joined + (portRef O (instanceRef LDS_000_INT_0_p)) + (portRef I0 (instanceRef N_14_i)) + )) (net N_15 (joined (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef I0 (instanceRef N_15_i)) @@ -1249,159 +1260,214 @@ (portRef O (instanceRef RW_000_INT_0_p)) (portRef I0 (instanceRef N_16_i)) )) - (net N_22 (joined - (portRef O (instanceRef A0_DMA_0_p)) - (portRef I0 (instanceRef N_22_i)) + (net N_18 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef I0 (instanceRef N_18_i)) )) - (net N_30 (joined - (portRef O (instanceRef CLK_OUT_PRE_25_0)) - (portRef D (instanceRef CLK_OUT_PRE_25)) + (net N_21 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef I0 (instanceRef N_21_i)) )) - (net N_31 (joined + (net N_23 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (portRef I0 (instanceRef N_23_i)) + )) + (net N_25 (joined + (portRef O (instanceRef IPL_030_0_0__p)) + (portRef I0 (instanceRef N_25_i)) + )) + (net N_26 (joined + (portRef O (instanceRef IPL_030_0_1__p)) + (portRef I0 (instanceRef N_26_i)) + )) + (net N_27 (joined + (portRef O (instanceRef IPL_030_0_2__p)) + (portRef I0 (instanceRef N_27_i)) + )) + (net N_28 (joined (portRef O (instanceRef IPL_030_1_i_0)) (portRef D (instanceRef IPL_030DFF_0)) )) - (net N_32 (joined + (net N_29 (joined (portRef O (instanceRef IPL_030_1_i_1)) (portRef D (instanceRef IPL_030DFF_1)) )) - (net N_33 (joined + (net N_30 (joined (portRef O (instanceRef IPL_030_1_i_2)) (portRef D (instanceRef IPL_030DFF_2)) )) - (net N_34 (joined + (net N_31 (joined (portRef O (instanceRef BG_000_1_i)) (portRef D (instanceRef BG_000DFF)) )) - (net N_35 (joined + (net N_32 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) )) - (net N_36 (joined + (net N_33 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) )) - (net N_37 (joined + (net N_34 (joined (portRef O (instanceRef UDS_000_INT_1_i)) (portRef D (instanceRef UDS_000_INT)) )) - (net N_38 (joined + (net N_35 (joined (portRef O (instanceRef A0_DMA_1_i)) (portRef D (instanceRef A0_DMA)) )) - (net N_39 (joined - (portRef O (instanceRef AS_000_INT_1_i)) - (portRef D (instanceRef AS_000_INT)) + (net N_36 (joined + (portRef O (instanceRef RW_000_DMA_1_i)) + (portRef D (instanceRef RW_000_DMA)) )) - (net N_40 (joined - (portRef O (instanceRef DSACK1_INT_1_i)) - (portRef D (instanceRef DSACK1_INT)) - )) - (net N_41 (joined + (net N_37 (joined (portRef O (instanceRef VMA_INT_1_i)) (portRef D (instanceRef VMA_INT)) )) - (net N_43 (joined - (portRef O (instanceRef RW_000_DMA_2_i)) - (portRef D (instanceRef RW_000_DMA)) - )) - (net N_44 (joined + (net N_39 (joined (portRef O (instanceRef RW_000_INT_1_i)) (portRef D (instanceRef RW_000_INT)) )) - (net N_45 (joined + (net N_40 (joined (portRef O (instanceRef AS_030_000_SYNC_1_i)) (portRef D (instanceRef AS_030_000_SYNC)) )) - (net N_46 (joined + (net N_41 (joined (portRef O (instanceRef LDS_000_INT_1_i)) (portRef D (instanceRef LDS_000_INT)) )) - (net N_47 (joined + (net N_42 (joined (portRef O (instanceRef BGACK_030_INT_1_i)) (portRef D (instanceRef BGACK_030_INT)) )) - (net N_49 (joined + (net N_44 (joined (portRef O (instanceRef AS_000_DMA_1_i)) (portRef D (instanceRef AS_000_DMA)) )) - (net N_50 (joined + (net N_45 (joined (portRef O (instanceRef DS_000_DMA_1_i)) (portRef D (instanceRef DS_000_DMA)) )) - (net N_52 (joined + (net N_48 (joined + (portRef O (instanceRef AS_030_D0_0_0_i)) + (portRef D (instanceRef AS_030_D0)) + )) + (net N_49 (joined (portRef O (instanceRef IPL_D0_0_i_0)) (portRef D (instanceRef IPL_D0_0)) )) - (net N_53 (joined + (net N_50 (joined (portRef O (instanceRef IPL_D0_0_i_1)) (portRef D (instanceRef IPL_D0_1)) )) - (net N_54 (joined + (net N_51 (joined (portRef O (instanceRef IPL_D0_0_i_2)) (portRef D (instanceRef IPL_D0_2)) )) - (net N_55 (joined + (net N_52 (joined (portRef O (instanceRef VPA_D_0_i)) (portRef D (instanceRef VPA_D)) )) - (net N_56 (joined + (net N_53 (joined (portRef O (instanceRef DTACK_D0_0_i)) (portRef D (instanceRef DTACK_D0)) )) - (net N_59 (joined + (net N_55 (joined + (portRef O (instanceRef RESET_OUT_2_0_i)) + (portRef D (instanceRef RESET_OUT)) + )) + (net N_56 (joined (portRef O (instanceRef DS_000_ENABLE_1)) (portRef D (instanceRef DS_000_ENABLE)) )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef Q (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o3)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o2)) (portRef I0 (instanceRef SM_AMIGA_i_i_7)) )) - (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__n)) + (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__n)) )) - (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__n)) + (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) )) - (net N_210 (joined + (net N_206 (joined (portRef O (instanceRef G_107)) - (portRef I0 (instanceRef N_210_i)) + (portRef I0 (instanceRef N_206_i)) )) - (net N_211 (joined + (net N_207 (joined (portRef O (instanceRef G_108)) - (portRef I0 (instanceRef N_211_i)) + (portRef I0 (instanceRef N_207_i)) )) - (net N_212 (joined + (net N_208 (joined (portRef O (instanceRef G_109)) - (portRef I0 (instanceRef N_212_i)) + (portRef I0 (instanceRef N_208_i)) )) (net (rename pos_clk_un21_bgack_030_int_i_0 "pos_clk.un21_bgack_030_int_i_0") (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3_i)) + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_i)) (portRef I0 (instanceRef AS_000_DMA_0_m)) )) - (net N_237 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0_i)) + (net N_81 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I0 (instanceRef N_81_i)) + )) + (net N_94 (joined + (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a2)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + )) + (net N_254 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_i)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) + )) + (net N_255 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_i)) (portRef I1 (instanceRef DS_000_DMA_0_m)) (portRef I0 (instanceRef DS_000_DMA_0_r)) )) - (net N_241 (joined - (portRef O (instanceRef un13_ciin_i_0_0_i)) + (net N_261 (joined + (portRef O (instanceRef un13_ciin_i_0_i)) (portRef OE (instanceRef CIIN)) )) - (net N_242 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + (net N_65 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_i)) (portRef I1 (instanceRef DS_000_ENABLE_0_m)) (portRef I0 (instanceRef DS_000_ENABLE_0_r)) )) - (net N_100 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3_i)) - (portRef D (instanceRef BGACK_030_INT_D)) + (net N_67 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) - (net N_283 (joined - (portRef O (instanceRef un3_as_030_i_a2_0_a3)) + (net N_269 (joined + (portRef O (instanceRef N_156_i_0_o2_i_o2_i)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I0 (instanceRef cpu_est_0_0_a2_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_a2_1)) + (portRef I0 (instanceRef RST_DLY_e2_i_a2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_5)) + )) + (net N_108 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) + )) + (net N_135 (joined + (portRef O (instanceRef un4_as_030_i_a2)) (portRef OE (instanceRef AHIGH_24)) (portRef OE (instanceRef AHIGH_25)) (portRef OE (instanceRef AHIGH_26)) @@ -1414,491 +1480,414 @@ (portRef OE (instanceRef A_0)) (portRef OE (instanceRef DS_030)) )) - (net N_294 (joined - (portRef O (instanceRef un1_rw_i_a2_0_a2)) - (portRef I0 (instanceRef un3_as_030_i_a2_0_a3)) - (portRef OE (instanceRef RW)) + (net N_136 (joined + (portRef O (instanceRef un1_as_000_i_a2)) + (portRef OE (instanceRef AS_000)) + (portRef OE (instanceRef LDS_000)) + (portRef OE (instanceRef RW_000)) + (portRef OE (instanceRef UDS_000)) )) - (net N_300 (joined - (portRef O (instanceRef pos_clk_un35_as_030_d0_0_i_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) - )) - (net N_301 (joined - (portRef O (instanceRef RESET_OUT_2_i_i_i)) - (portRef D (instanceRef RESET_OUT)) - )) - (net N_106 (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_i_a2_i_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - )) - (net N_110 (joined - (portRef O (instanceRef AS_030_D0_0_i_a2_i_i)) - (portRef D (instanceRef AS_030_D0)) - )) - (net N_134 (joined - (portRef O (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2_i)) - (portRef I0 (instanceRef RST_DLYlde_i_a2_i)) - (portRef I0 (instanceRef cpu_est_0_0_0_a3_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - )) - (net N_138 (joined - (portRef O (instanceRef N_258_i_0_o2_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_1)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - )) - (net N_156 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_0_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1_0)) - )) - (net N_160 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_o2_i)) - (portRef I1 (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - )) - (net N_167 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_a2_0_o2_i_o2_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_5)) - (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) - )) - (net N_172 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - )) - (net N_173 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) - )) - (net N_181 (joined - (portRef O (instanceRef pos_clk_un35_as_030_d0_0_i_o2_i)) - (portRef I1 (instanceRef pos_clk_un35_as_030_d0_0_i_a3)) - )) - (net N_182 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0)) - )) - (net N_183 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_6)) - )) - (net N_191 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__p)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) - )) - (net N_199 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3)) - (portRef I0 (instanceRef N_199_i)) - )) - (net N_205 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3_1)) - (portRef I0 (instanceRef N_205_i)) - )) - (net N_209 (joined - (portRef O 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(instanceRef SM_AMIGA_srsts_i_a4_2)) + )) + (net N_245 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef N_245_i)) + )) + (net N_242 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + )) + (net N_246 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (portRef I0 (instanceRef N_246_i)) + )) + (net N_248 (joined + (portRef O (instanceRef RST_DLY_e2_i_a2_0)) + (portRef I0 (instanceRef N_248_i)) + )) + (net N_236 (joined + (portRef O (instanceRef RST_DLY_e2_i_o2_i)) + (portRef I0 (instanceRef RST_DLY_e0_i_a2)) + (portRef I0 (instanceRef RST_DLY_e1_i_a2)) + (portRef I1 (instanceRef RST_DLY_e2_i_a2_0)) + )) + (net N_249 (joined + (portRef O (instanceRef RST_DLY_e2_i_a2_1)) + (portRef I0 (instanceRef N_249_i)) + )) + (net N_92 (joined + (portRef O (instanceRef RST_DLY_e2_i_a2_4)) + (portRef I0 (instanceRef RST_DLY_e0_i_a2_0)) + (portRef I0 (instanceRef RST_DLY_e1_i_a2_0)) + )) + (net N_251 (joined + (portRef O (instanceRef RST_DLY_e1_i_a2)) + (portRef I0 (instanceRef N_251_i)) + )) + (net N_76 (joined + (portRef O (instanceRef RST_DLY_e1_i_a2_0)) + (portRef I0 (instanceRef N_76_i)) + )) + (net N_80 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I0 (instanceRef N_80_i)) + )) + (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined + (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I0 (instanceRef A0_DMA_0_n)) + )) + (net SIZE_DMA_3_sqmuxa (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_0_a2)) + (portRef I1 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__r)) + )) + (net N_87 (joined + (portRef O (instanceRef RST_DLY_e2_i_a2_3)) + (portRef I0 (instanceRef N_87_i)) + )) + (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__n)) + )) + (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__n)) + )) + (net N_170 (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_a2)) + (portRef I0 (instanceRef N_170_i)) + )) + (net N_122 (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I0 (instanceRef N_122_i)) + )) + (net N_123 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2)) + (portRef I0 (instanceRef N_123_i)) )) (net N_130 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3)) + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) (portRef I0 (instanceRef N_130_i)) )) + (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) + )) + (net (rename pos_clk_RW_000_DMA_3 "pos_clk.RW_000_DMA_3") (joined + (portRef O (instanceRef pos_clk_RW_000_DMA_3_0_i)) + (portRef I0 (instanceRef RW_000_DMA_0_n)) + )) + (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) (net N_131 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3)) + (portRef O (instanceRef G_102)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) (portRef I0 (instanceRef N_131_i)) )) (net N_3 (joined (portRef O (instanceRef DS_000_DMA_0_p)) (portRef I0 (instanceRef N_3_i)) )) - (net N_4 (joined - (portRef O (instanceRef AS_000_DMA_0_p)) - (portRef I0 (instanceRef N_4_i)) + (net N_8 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef I0 (instanceRef N_8_i)) )) - (net N_17 (joined + (net N_19 (joined (portRef O (instanceRef RW_000_DMA_0_p)) - (portRef I0 (instanceRef N_17_i)) + (portRef I0 (instanceRef N_19_i)) + )) + (net N_20 (joined + (portRef O (instanceRef A0_DMA_0_p)) + (portRef I0 (instanceRef N_20_i)) + )) + (net N_22 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef I0 (instanceRef N_22_i)) )) (net N_24 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef O (instanceRef BG_000_0_p)) (portRef I0 (instanceRef N_24_i)) )) - (net N_25 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - (portRef I0 (instanceRef N_25_i)) - )) (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined (portRef O (instanceRef pos_clk_un9_bg_030_i)) (portRef I1 (instanceRef BG_000_0_m)) (portRef I0 (instanceRef BG_000_0_r)) )) - (net N_6 (joined - (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef I0 (instanceRef N_6_i)) - )) - (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) - )) - (net N_26 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef I0 (instanceRef N_26_i)) - )) - (net N_208 (joined - (portRef O (instanceRef G_102)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) - (portRef I0 (instanceRef N_208_i)) - )) - (net N_207 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) - (portRef I0 (instanceRef N_207_i)) - )) - (net N_349 (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_a2)) - (portRef I0 (instanceRef N_349_i)) - )) - (net N_314 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) - (portRef I0 (instanceRef N_314_i)) - )) - (net N_318 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) - (portRef I0 (instanceRef N_318_i)) - )) - (net N_348 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I0 (instanceRef N_348_i)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) - )) - (net N_201 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_1)) - (portRef I0 (instanceRef N_201_i)) - )) - (net N_200 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_0)) - (portRef I0 (instanceRef N_200_i)) - )) - (net N_203 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3)) - (portRef I0 (instanceRef N_203_i)) - )) - (net N_204 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3_0)) - (portRef I0 (instanceRef N_204_i)) - )) - (net N_185 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_4)) - )) - (net N_184 (joined - (portRef O (instanceRef un5_e_0_i_o2_0_i)) - (portRef I0 (instanceRef un5_e_0_i_a3)) - )) - (net N_180 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3)) - )) - (net N_179 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_2)) - )) - (net N_178 (joined - (portRef O (instanceRef un5_e_0_i_o2_i)) - (portRef I0 (instanceRef un5_e_0_i_a3_0)) - )) - (net N_171 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - )) - (net N_341 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - (portRef I0 (instanceRef N_341_i)) - )) - (net N_342 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) - (portRef I0 (instanceRef N_342_i)) - )) - (net N_169 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_o2_i_0)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0)) - (portRef I0 (instanceRef DSACK1_INT_0_m)) - )) - (net N_154 (joined - (portRef O (instanceRef cpu_est_2_i_0_0_o2_i_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_0_a3_3)) - )) - (net N_165 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) - )) - (net N_162 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_o2_i)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_a3)) - )) - (net N_299 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_a2)) - (portRef I0 (instanceRef N_299_i)) - )) - (net N_153 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_2)) - )) - (net N_142 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_i)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a3)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_0)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a3)) - )) - (net N_298 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2)) - (portRef I0 (instanceRef N_298_i)) - )) - (net N_80 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_0_i)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) - )) - (net N_232 (joined - (portRef O (instanceRef cpu_est_0_0_0_a3_0)) - (portRef I0 (instanceRef N_232_i)) - )) - (net N_233 (joined - (portRef O (instanceRef cpu_est_0_0_0_a3_0_0)) - (portRef I0 (instanceRef N_233_i)) - )) - (net N_229 (joined - (portRef O (instanceRef un5_e_0_i_a3)) - (portRef I0 (instanceRef N_229_i)) - )) - (net N_231 (joined - (portRef O (instanceRef un5_e_0_i_a3_0)) - (portRef I0 (instanceRef N_231_i)) - )) - (net N_226 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_5)) - (portRef I0 (instanceRef N_226_i)) - )) - (net N_221 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a3_2)) - (portRef I0 (instanceRef N_221_i)) - )) - (net N_222 (joined - (portRef O (instanceRef cpu_est_2_i_0_0_a3_3)) - (portRef I0 (instanceRef N_222_i)) - )) - (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) - )) - (net N_219 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a3_1)) - (portRef I0 (instanceRef N_219_i)) - )) - (net (rename pos_clk_un9_clk_000_pe "pos_clk.un9_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) - )) - (net N_256 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) - (portRef I1 (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_r)) - )) - (net N_29 (joined - (portRef O (instanceRef IPL_030_0_2__p)) - (portRef I0 (instanceRef N_29_i)) - )) - (net N_28 (joined - (portRef O (instanceRef IPL_030_0_1__p)) - (portRef I0 (instanceRef N_28_i)) - )) - (net N_27 (joined - (portRef O (instanceRef IPL_030_0_0__p)) - (portRef I0 (instanceRef N_27_i)) - )) - (net N_14 (joined - (portRef O (instanceRef LDS_000_INT_0_p)) - (portRef I0 (instanceRef N_14_i)) - )) - (net N_19 (joined - (portRef O (instanceRef VMA_INT_0_p)) - (portRef I0 (instanceRef N_19_i)) - )) - (net N_20 (joined - (portRef O (instanceRef DSACK1_INT_0_p)) - (portRef I0 (instanceRef N_20_i)) - )) - (net N_21 (joined - (portRef O (instanceRef AS_000_INT_0_p)) - (portRef I0 (instanceRef N_21_i)) - )) - (net N_23 (joined - (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef I0 (instanceRef N_23_i)) - )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) @@ -1907,279 +1896,308 @@ (portRef O (instanceRef un21_fpu_cs_i)) (portRef I0 (instanceRef FPU_CS)) )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef un5_e_0_i_o2_0)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1_1)) - )) - (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined - (portRef O (instanceRef RST_DLY_i_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3)) - )) - (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined - (portRef O (instanceRef RST_DLY_i_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_2_i_0_0_o2_3)) - (portRef I1 (instanceRef cpu_est_0_0_0_a3_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I1 (instanceRef un5_e_0_i_a3)) - (portRef I1 (instanceRef cpu_est_2_i_0_0_a3_3)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_o2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_4)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_5)) - )) - (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined - (portRef O (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a3_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1_1)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_2)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) - )) - (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined - (portRef O (instanceRef CLK_000_D_i_1)) - (portRef I1 (instanceRef N_258_i_0_o2)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef un5_e_0_i_o2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_6)) - )) - (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined - (portRef O (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef CLK_000_NE_0_o3_i_a2_0_o2_i_o2)) - )) (net BGACK_030_INT_i (joined (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef un1_as_030_i_a2_i)) - (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_0)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3)) + (portRef I0 (instanceRef un2_as_030_0)) + (portRef I0 (instanceRef un1_rw_i_a2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) + (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_0)) (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I0 (instanceRef un1_rw_i_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3_2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_220)) - (portRef I0 (instanceRef un6_ds_030)) - (portRef I1 (instanceRef un6_as_030_0_a2_0_a3)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) - )) - (net AS_000_DMA_i (joined - (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef CLK_030_H_2_i_0_o2)) - (portRef I0 (instanceRef un6_as_030_0_a2_0_a3)) - )) - (net nEXP_SPACE_i (joined - (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef un1_as_030_i_a2_i)) - (portRef I0 (instanceRef un13_ciin_i_0_0)) - (portRef I1 (instanceRef un3_as_030_i_a2_0_a3)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2)) - )) - (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined - (portRef O (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) - )) - (net DS_000_DMA_i (joined - (portRef O (instanceRef DS_000_DMA_i)) - (portRef I1 (instanceRef un6_ds_030)) )) (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) (portRef I0 (instanceRef un1_amiga_bus_enable_low)) )) - (net N_130_i (joined - (portRef O (instanceRef N_130_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (net N_80_i (joined + (portRef O (instanceRef N_80_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) - (net N_131_i (joined - (portRef O (instanceRef N_131_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - )) - (net CLK_030_H_i (joined - (portRef O (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef CLK_030_H_2_i_0_a3)) + (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined + (portRef O (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) )) (net RW_000_i (joined - (portRef O (instanceRef I_221)) - (portRef I1 (instanceRef un14_amiga_bus_data_dir_i_0_0)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_a3)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + (portRef O (instanceRef I_226)) + (portRef I1 (instanceRef pos_clk_RW_000_DMA_3_0)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + )) + (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined + (portRef O (instanceRef RST_DLY_i_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_a2_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_a2_1_1)) + )) + (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined + (portRef O (instanceRef RST_DLY_i_1)) + (portRef I1 (instanceRef RST_DLY_e1_i_a2_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_a2_1)) + )) + (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined + (portRef O (instanceRef RST_DLY_i_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_a2_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_a2)) + )) + (net LDS_000_i (joined + (portRef O (instanceRef I_227)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + )) + (net UDS_000_i (joined + (portRef O (instanceRef I_228)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_2)) + )) + (net N_58_i (joined + (portRef O (instanceRef N_58_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_3)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_3)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1_1)) + (portRef I1 (instanceRef un5_e_0_a3_0)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_1)) + (portRef I1 (instanceRef cpu_est_0_0_a2_0)) + (portRef I1 (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + )) + (net N_110_i (joined + (portRef O (instanceRef N_110_i)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_3)) )) (net (rename A_i_1 "A_i[1]") (joined (portRef O (instanceRef A_i_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) )) - (net RESET_OUT_i (joined - (portRef O (instanceRef RESET_OUT_i)) - (portRef OE (instanceRef RESET)) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_a2_0_1_3)) )) - (net AS_030_i (joined - (portRef O (instanceRef I_222)) - (portRef I1 (instanceRef un4_as_000)) - (portRef I0 (instanceRef AS_030_D0_0_i_a2_i)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a3_1)) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_i_a2_0_1_3)) )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a3_1)) - )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0)) - (portRef I0 (instanceRef pos_clk_un35_as_030_d0_0_i_o2_0)) - )) - (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined - (portRef O (instanceRef A_DECODE_i_16)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2_2)) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_a2_1_3)) )) (net AS_030_D0_i (joined (portRef O (instanceRef AS_030_D0_i)) - (portRef I0 (instanceRef pos_clk_un35_as_030_d0_0_i_a3_0)) - (portRef I0 (instanceRef pos_clk_un35_as_030_d0_0_i_a3)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_5)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_2)) + (portRef I1 (instanceRef un10_ciin_0_a2_5)) )) - (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined - (portRef O (instanceRef SIZE_DMA_i_0)) - (portRef I1 (instanceRef un3_size)) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) )) - (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined - (portRef O (instanceRef SIZE_DMA_i_1)) - (portRef I1 (instanceRef un4_size)) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2_2)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_5)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_4)) + )) + (net nEXP_SPACE_i (joined + (portRef O (instanceRef nEXP_SPACE_i)) + (portRef I0 (instanceRef un13_ciin_i_0)) + (portRef I1 (instanceRef un2_as_030_0)) + (portRef I1 (instanceRef un4_as_030_i_a2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2_0)) + )) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_a2)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_230)) + (portRef I0 (instanceRef AS_030_D0_0_0)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2)) + (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2)) + (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_1)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef un7_as_030_0_a2)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_231)) + (portRef I0 (instanceRef un6_ds_030)) + (portRef I1 (instanceRef un7_as_030_0_a2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) + )) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2)) + )) + (net DSACK1_INT_i (joined + (portRef O (instanceRef DSACK1_INT_i)) + (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2)) + )) + (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined + (portRef O (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef N_156_i_0_o2_i_o2)) + )) + (net (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (joined + (portRef O (instanceRef CLK_000_D_i_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0)) + )) + (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined + (portRef O (instanceRef CLK_000_D_i_1)) + (portRef I1 (instanceRef CLK_000_PE_0_o3_i_o2_i_o2)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef cpu_est_2_i_0_a2_0_3)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_2)) + (portRef I0 (instanceRef cpu_est_2_i_0_a2_3)) + (portRef I1 (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3_2)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef cpu_est_2_i_0_a2_3)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1)) + (portRef I1 (instanceRef un5_e_0_a3)) + )) + (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined + (portRef O (instanceRef A_DECODE_i_16)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_2)) )) (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined (portRef O (instanceRef A_DECODE_i_18)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2_3)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_2)) )) (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined (portRef O (instanceRef A_DECODE_i_19)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2_3)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_3)) )) (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined - (portRef O (instanceRef I_223)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_4)) + (portRef O (instanceRef I_233)) + (portRef I0 (instanceRef un10_ciin_0_a2_4)) )) (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined - (portRef O (instanceRef I_224)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_4)) + (portRef O (instanceRef I_234)) + (portRef I1 (instanceRef un10_ciin_0_a2_4)) )) (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined - (portRef O (instanceRef I_225)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_3)) + (portRef O (instanceRef I_235)) + (portRef I0 (instanceRef un10_ciin_0_a2_3)) )) (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined - (portRef O (instanceRef I_226)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_3)) + (portRef O (instanceRef I_236)) + (portRef I1 (instanceRef un10_ciin_0_a2_3)) )) (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined - (portRef O (instanceRef I_227)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_2)) + (portRef O (instanceRef I_237)) + (portRef I0 (instanceRef un10_ciin_0_a2_2)) )) (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined - (portRef O (instanceRef I_228)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_2)) + (portRef O (instanceRef I_238)) + (portRef I1 (instanceRef un10_ciin_0_a2_2)) )) (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined - (portRef O (instanceRef I_229)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_1)) + (portRef O (instanceRef I_239)) + (portRef I0 (instanceRef un10_ciin_0_a2_1)) )) (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined - (portRef O (instanceRef I_230)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_1)) + (portRef O (instanceRef I_240)) + (portRef I1 (instanceRef un10_ciin_0_a2_1)) )) - (net N_210_i (joined - (portRef O (instanceRef N_210_i)) + (net N_206_i (joined + (portRef O (instanceRef N_206_i)) (portRef I1 (instanceRef G_110_1)) )) - (net N_211_i (joined - (portRef O (instanceRef N_211_i)) + (net N_207_i (joined + (portRef O (instanceRef N_207_i)) (portRef I1 (instanceRef G_110)) )) - (net N_212_i (joined - (portRef O (instanceRef N_212_i)) + (net N_208_i (joined + (portRef O (instanceRef N_208_i)) (portRef I0 (instanceRef G_110_1)) )) (net CLK_OUT_PRE_50_i (joined (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) + (net AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i)) + (portRef D (instanceRef BGACK_030_INT_D)) + )) + (net N_81_i (joined + (portRef O (instanceRef N_81_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + )) (net un6_ds_030_i (joined (portRef O (instanceRef un6_ds_030_i)) (portRef I0 (instanceRef DS_030)) )) - (net un4_as_000_i (joined - (portRef O (instanceRef un4_as_000_i)) + (net DS_000_DMA_i (joined + (portRef O (instanceRef DS_000_DMA_i)) + (portRef I1 (instanceRef un6_ds_030)) + )) + (net N_147_i (joined + (portRef O (instanceRef N_147_i)) + (portRef I0 (instanceRef DSACK1)) + )) + (net N_145_i (joined + (portRef O (instanceRef N_145_i)) (portRef I0 (instanceRef AS_000)) )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef un4_as_000)) - )) - (net un6_as_030_i (joined - (portRef O (instanceRef un6_as_030_i)) + (net un7_as_030_i (joined + (portRef O (instanceRef un7_as_030_i)) (portRef I0 (instanceRef AS_030)) )) + (net RESET_OUT_i (joined + (portRef O (instanceRef RESET_OUT_i)) + (portRef OE (instanceRef RESET)) + )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef I_222)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef I_230)) )) (net AS_030 (joined (portRef AS_030) @@ -2187,8 +2205,8 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) - (portRef I0 (instanceRef I_220)) + (portRef I0 (instanceRef I_231)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_a2)) )) (net AS_000 (joined (portRef AS_000) @@ -2196,8 +2214,8 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_221)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2)) + (portRef I0 (instanceRef I_226)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2_0_1)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -2209,9 +2227,9 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_a2)) - (portRef I0 (instanceRef UDS_000_c_i)) + (portRef I1 (instanceRef pos_clk_un19_bgack_030_int)) + (portRef I0 (instanceRef I_228)) + (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2)) )) (net UDS_000 (joined (portRef IO (instanceRef UDS_000)) @@ -2219,8 +2237,8 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_a2)) - (portRef I0 (instanceRef LDS_000_c_i)) + (portRef I0 (instanceRef pos_clk_un19_bgack_030_int)) + (portRef I0 (instanceRef I_227)) )) (net LDS_000 (joined (portRef IO (instanceRef LDS_000)) @@ -2228,7 +2246,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I0 (instanceRef pos_clk_un10_sm_amiga_1)) + (portRef I1 (instanceRef pos_clk_un10_sm_amiga)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef IO (instanceRef SIZE_0)) @@ -2244,7 +2262,7 @@ )) (net (rename AHIGH_c_24 "AHIGH_c[24]") (joined (portRef O (instanceRef AHIGH_24)) - (portRef I0 (instanceRef I_229)) + (portRef I0 (instanceRef I_239)) )) (net (rename AHIGH_24 "AHIGH[24]") (joined (portRef IO (instanceRef AHIGH_24)) @@ -2252,7 +2270,7 @@ )) (net (rename AHIGH_c_25 "AHIGH_c[25]") (joined (portRef O (instanceRef AHIGH_25)) - (portRef I0 (instanceRef I_230)) + (portRef I0 (instanceRef I_240)) )) (net (rename AHIGH_25 "AHIGH[25]") (joined (portRef IO (instanceRef AHIGH_25)) @@ -2260,7 +2278,7 @@ )) (net (rename AHIGH_c_26 "AHIGH_c[26]") (joined (portRef O (instanceRef AHIGH_26)) - (portRef I0 (instanceRef I_227)) + (portRef I0 (instanceRef I_237)) )) (net (rename AHIGH_26 "AHIGH[26]") (joined (portRef IO (instanceRef AHIGH_26)) @@ -2268,7 +2286,7 @@ )) (net (rename AHIGH_c_27 "AHIGH_c[27]") (joined (portRef O (instanceRef AHIGH_27)) - (portRef I0 (instanceRef I_228)) + (portRef I0 (instanceRef I_238)) )) (net (rename AHIGH_27 "AHIGH[27]") (joined (portRef IO (instanceRef AHIGH_27)) @@ -2276,7 +2294,7 @@ )) (net (rename AHIGH_c_28 "AHIGH_c[28]") (joined (portRef O (instanceRef AHIGH_28)) - (portRef I0 (instanceRef I_225)) + (portRef I0 (instanceRef I_235)) )) (net (rename AHIGH_28 "AHIGH[28]") (joined (portRef IO (instanceRef AHIGH_28)) @@ -2284,7 +2302,7 @@ )) (net (rename AHIGH_c_29 "AHIGH_c[29]") (joined (portRef O (instanceRef AHIGH_29)) - (portRef I0 (instanceRef I_226)) + (portRef I0 (instanceRef I_236)) )) (net (rename AHIGH_29 "AHIGH[29]") (joined (portRef IO (instanceRef AHIGH_29)) @@ -2292,7 +2310,7 @@ )) (net (rename AHIGH_c_30 "AHIGH_c[30]") (joined (portRef O (instanceRef AHIGH_30)) - (portRef I0 (instanceRef I_223)) + (portRef I0 (instanceRef I_233)) )) (net (rename AHIGH_30 "AHIGH[30]") (joined (portRef IO (instanceRef AHIGH_30)) @@ -2300,7 +2318,7 @@ )) (net (rename AHIGH_c_31 "AHIGH_c[31]") (joined (portRef O (instanceRef AHIGH_31)) - (portRef I0 (instanceRef I_224)) + (portRef I0 (instanceRef I_234)) )) (net (rename AHIGH_31 "AHIGH[31]") (joined (portRef (member ahigh 0)) @@ -2414,7 +2432,7 @@ )) (net (rename A_DECODE_c_17 "A_DECODE_c[17]") (joined (portRef O (instanceRef A_DECODE_17)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_1)) )) (net (rename A_DECODE_17 "A_DECODE[17]") (joined (portRef (member a_decode 6)) @@ -2438,7 +2456,7 @@ )) (net (rename A_DECODE_c_20 "A_DECODE_c[20]") (joined (portRef O (instanceRef A_DECODE_20)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_6)) + (portRef I0 (instanceRef un10_ciin_0_a2_6)) )) (net (rename A_DECODE_20 "A_DECODE[20]") (joined (portRef (member a_decode 3)) @@ -2446,7 +2464,7 @@ )) (net (rename A_DECODE_c_21 "A_DECODE_c[21]") (joined (portRef O (instanceRef A_DECODE_21)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_6)) + (portRef I1 (instanceRef un10_ciin_0_a2_6)) )) (net (rename A_DECODE_21 "A_DECODE[21]") (joined (portRef (member a_decode 2)) @@ -2454,7 +2472,7 @@ )) (net (rename A_DECODE_c_22 "A_DECODE_c[22]") (joined (portRef O (instanceRef A_DECODE_22)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_11)) + (portRef I1 (instanceRef un10_ciin_0_a2_11)) )) (net (rename A_DECODE_22 "A_DECODE[22]") (joined (portRef (member a_decode 1)) @@ -2462,7 +2480,7 @@ )) (net (rename A_DECODE_c_23 "A_DECODE_c[23]") (joined (portRef O (instanceRef A_DECODE_23)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_5)) + (portRef I0 (instanceRef un10_ciin_0_a2_5)) )) (net (rename A_DECODE_23 "A_DECODE[23]") (joined (portRef (member a_decode 0)) @@ -2480,7 +2498,7 @@ (net (rename A_c_1 "A_c[1]") (joined (portRef O (instanceRef A_1)) (portRef I0 (instanceRef A_i_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) )) (net (rename A_1 "A[1]") (joined (portRef (member a 0)) @@ -2488,10 +2506,10 @@ )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) - (portRef I1 (instanceRef pos_clk_un35_as_030_d0_0_i_o2_0)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3_1)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_2_0)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_1)) (portRef OE (instanceRef DSACK1)) )) (net nEXP_SPACE (joined @@ -2500,7 +2518,7 @@ )) (net BERR_c (joined (portRef O (instanceRef BERR)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_o2_1_3)) )) (net BERR (joined (portRef BERR) @@ -2530,9 +2548,10 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I1 (instanceRef un21_berr_0_a2_1)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -2540,7 +2559,7 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0_a3)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) (portRef I0 (instanceRef CLK_030_c_i)) )) (net CLK_030 (joined @@ -2570,9 +2589,10 @@ (portRef CLK (instanceRef CLK_000_D_0)) (portRef CLK (instanceRef CLK_000_D_1)) (portRef CLK (instanceRef CLK_000_D_2)) + (portRef CLK (instanceRef CLK_000_D_3)) + (portRef CLK (instanceRef CLK_000_D_4)) (portRef CLK (instanceRef CLK_030_H)) (portRef CLK (instanceRef CLK_OUT_INT)) - (portRef CLK (instanceRef CLK_OUT_PRE_25)) (portRef CLK (instanceRef CLK_OUT_PRE_50)) (portRef CLK (instanceRef CLK_OUT_PRE_D)) (portRef CLK (instanceRef CYCLE_DMA_0)) @@ -2636,7 +2656,7 @@ (net FPU_SENSE_c (joined (portRef O (instanceRef FPU_SENSE)) (portRef I0 (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a3_1_0)) + (portRef I1 (instanceRef un21_berr_0_a2)) )) (net FPU_SENSE (joined (portRef FPU_SENSE) @@ -2671,8 +2691,8 @@ )) (net (rename IPL_c_0 "IPL_c[0]") (joined (portRef O (instanceRef IPL_0)) - (portRef I1 (instanceRef G_107)) (portRef I0 (instanceRef IPL_030_0_0__m)) + (portRef I1 (instanceRef G_107)) (portRef I0 (instanceRef IPL_c_i_0)) )) (net (rename IPL_0 "IPL[0]") (joined @@ -2681,8 +2701,8 @@ )) (net (rename IPL_c_1 "IPL_c[1]") (joined (portRef O (instanceRef IPL_1)) - (portRef I1 (instanceRef G_108)) (portRef I0 (instanceRef IPL_030_0_1__m)) + (portRef I1 (instanceRef G_108)) (portRef I0 (instanceRef IPL_c_i_1)) )) (net (rename IPL_1 "IPL[1]") (joined @@ -2733,50 +2753,56 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) + (portRef I1 (instanceRef IPL_D0_0_1)) + (portRef I1 (instanceRef IPL_D0_0_0)) + (portRef I1 (instanceRef AS_000_DMA_1)) + (portRef I1 (instanceRef LDS_000_INT_1)) (portRef I1 (instanceRef AS_030_000_SYNC_1)) (portRef I1 (instanceRef RW_000_INT_1)) - (portRef I1 (instanceRef A0_DMA_1)) - (portRef I1 (instanceRef DS_000_ENABLE_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3)) - (portRef I1 (instanceRef AS_030_D0_0_i_a2_i)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_o3)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I1 (instanceRef RW_000_DMA_2)) - (portRef I1 (instanceRef AS_000_DMA_1)) - (portRef I1 (instanceRef DS_000_DMA_1)) - (portRef I1 (instanceRef RESET_OUT_2_i_i_a3)) - (portRef I0 (instanceRef VPA_D_0)) - (portRef I1 (instanceRef BGACK_030_INT_1)) - (portRef I1 (instanceRef BG_000_1)) - (portRef I1 (instanceRef DTACK_D0_0)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_1)) - (portRef I1 (instanceRef RST_DLYlde_i_a2_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_o2)) - (portRef I1 (instanceRef AS_000_INT_1)) - (portRef I1 (instanceRef DSACK1_INT_1)) (portRef I1 (instanceRef VMA_INT_1)) - (portRef I1 (instanceRef LDS_000_INT_1)) - (portRef I1 (instanceRef IPL_D0_0_0)) - (portRef I1 (instanceRef IPL_D0_0_1)) - (portRef I1 (instanceRef IPL_D0_0_2)) - (portRef I1 (instanceRef IPL_030_1_0)) - (portRef I1 (instanceRef IPL_030_1_1)) - (portRef I1 (instanceRef IPL_030_1_2)) (portRef I1 (instanceRef UDS_000_INT_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - (portRef I1 (instanceRef CLK_030_H_2_i_0_1)) - (portRef I1 (instanceRef RST_DLY_e0_i_0)) - (portRef I1 (instanceRef RESET_OUT_2_i_i_a3_0)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef IPL_030_1_2)) + (portRef I1 (instanceRef IPL_030_1_1)) + (portRef I1 (instanceRef IPL_030_1_0)) + (portRef I1 (instanceRef IPL_D0_0_2)) + (portRef I1 (instanceRef AS_030_D0_0_0)) + (portRef I1 (instanceRef AS_000_INT_0_i_a2)) + (portRef I1 (instanceRef AS_000_INT_0_i_a2_0)) + (portRef I1 (instanceRef DSACK1_INT_0_i_a2)) + (portRef I1 (instanceRef DSACK1_INT_0_i_a2_0)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) + (portRef I1 (instanceRef RESET_OUT_2_0_a2)) + (portRef I1 (instanceRef RST_DLY_e2_i_o2)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_a2_4)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_0_a2)) + (portRef I1 (instanceRef BG_000_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I1 (instanceRef A0_DMA_1)) + (portRef I1 (instanceRef RW_000_DMA_1)) + (portRef I1 (instanceRef BGACK_030_INT_1)) + (portRef I1 (instanceRef DS_000_DMA_1)) + (portRef I0 (instanceRef VPA_D_0)) + (portRef I1 (instanceRef DTACK_D0_0)) + (portRef I1 (instanceRef RESET_OUT_2_0_a2_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_2)) + (portRef I1 (instanceRef RST_DLY_e1_i_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + (portRef I1 (instanceRef RST_DLY_e0_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_1)) )) (net RST (joined (portRef RST) @@ -2788,7 +2814,7 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_a2)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_a2)) (portRef I0 (instanceRef RW_c_i)) )) (net RW (joined @@ -2797,7 +2823,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2_1)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_5)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -2805,7 +2831,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_3)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -2816,7 +2842,7 @@ (portRef AMIGA_ADDR_ENABLE) )) (net AMIGA_BUS_DATA_DIR_c (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) (net AMIGA_BUS_DATA_DIR (joined @@ -2835,420 +2861,6 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net UDS_000_INT_i (joined - (portRef O (instanceRef UDS_000_INT_i)) - (portRef I1 (instanceRef un1_UDS_000_INT)) - )) - (net un1_UDS_000_INT_0 (joined - (portRef O (instanceRef un1_UDS_000_INT)) - (portRef I0 (instanceRef un1_UDS_000_INT_i)) - )) - (net LDS_000_INT_i (joined - (portRef O (instanceRef LDS_000_INT_i)) - (portRef I1 (instanceRef un1_LDS_000_INT)) - )) - (net un1_LDS_000_INT_0 (joined - (portRef O (instanceRef un1_LDS_000_INT)) - (portRef I0 (instanceRef un1_LDS_000_INT_i)) - )) - (net N_23_i (joined - (portRef O (instanceRef N_23_i)) - (portRef I0 (instanceRef UDS_000_INT_1)) - )) - (net N_37_0 (joined - (portRef O (instanceRef UDS_000_INT_1)) - (portRef I0 (instanceRef UDS_000_INT_1_i)) - )) - (net N_21_i (joined - (portRef O (instanceRef N_21_i)) - (portRef I0 (instanceRef AS_000_INT_1)) - )) - (net N_39_0 (joined - (portRef O (instanceRef AS_000_INT_1)) - (portRef I0 (instanceRef AS_000_INT_1_i)) - )) - (net N_20_i (joined - (portRef O (instanceRef N_20_i)) - (portRef I0 (instanceRef DSACK1_INT_1)) - )) - (net N_40_0 (joined - (portRef O (instanceRef DSACK1_INT_1)) - (portRef I0 (instanceRef DSACK1_INT_1_i)) - )) - (net N_19_i (joined - (portRef O (instanceRef N_19_i)) - (portRef I0 (instanceRef VMA_INT_1)) - )) - (net N_41_0 (joined - (portRef O (instanceRef VMA_INT_1)) - (portRef I0 (instanceRef VMA_INT_1_i)) - )) - (net N_14_i (joined - (portRef O (instanceRef N_14_i)) - (portRef I0 (instanceRef LDS_000_INT_1)) - )) - (net N_46_0 (joined - (portRef O (instanceRef LDS_000_INT_1)) - (portRef I0 (instanceRef LDS_000_INT_1_i)) - )) - (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined - (portRef O (instanceRef IPL_c_i_0)) - (portRef I0 (instanceRef IPL_D0_0_0)) - )) - (net N_52_0 (joined - (portRef O (instanceRef IPL_D0_0_0)) - (portRef I0 (instanceRef IPL_D0_0_i_0)) - )) - (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined - (portRef O (instanceRef IPL_c_i_1)) - (portRef I0 (instanceRef IPL_D0_0_1)) - )) - (net N_53_0 (joined - (portRef O (instanceRef IPL_D0_0_1)) - (portRef I0 (instanceRef IPL_D0_0_i_1)) - )) - (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined - (portRef O (instanceRef IPL_c_i_2)) - (portRef I0 (instanceRef IPL_D0_0_2)) - )) - (net N_54_0 (joined - (portRef O (instanceRef IPL_D0_0_2)) - (portRef I0 (instanceRef IPL_D0_0_i_2)) - )) - (net N_27_i (joined - (portRef O (instanceRef N_27_i)) - (portRef I0 (instanceRef IPL_030_1_0)) - )) - (net N_31_0 (joined - (portRef O (instanceRef IPL_030_1_0)) - (portRef I0 (instanceRef IPL_030_1_i_0)) - )) - (net N_28_i (joined - (portRef O (instanceRef N_28_i)) - (portRef I0 (instanceRef IPL_030_1_1)) - )) - (net N_32_0 (joined - (portRef O (instanceRef IPL_030_1_1)) - (portRef I0 (instanceRef IPL_030_1_i_1)) - )) - (net N_29_i (joined - (portRef O (instanceRef N_29_i)) - (portRef I0 (instanceRef IPL_030_1_2)) - )) - (net N_33_0 (joined - (portRef O (instanceRef IPL_030_1_2)) - (portRef I0 (instanceRef IPL_030_1_i_2)) - )) - (net (rename A_c_i_0 "A_c_i[0]") (joined - (portRef O (instanceRef A_c_i_0)) - (portRef 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(portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) - )) - (net N_182_0 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) - )) - (net N_181_0 (joined - (portRef O (instanceRef pos_clk_un35_as_030_d0_0_i_o2)) - (portRef I0 (instanceRef pos_clk_un35_as_030_d0_0_i_o2_i)) - )) - (net N_228_i (joined - (portRef O (instanceRef N_228_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) - )) - (net N_176_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o3)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_i_a2_i)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - )) - (net LDS_000_c_i (joined - (portRef O (instanceRef LDS_000_c_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) - )) - (net UDS_000_c_i (joined - (portRef O (instanceRef UDS_000_c_i)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) - )) - (net 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(joined + (portRef O (instanceRef N_170_i)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0)) + )) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_i)) + )) + (net (rename pos_clk_RW_000_DMA_3_0 "pos_clk.RW_000_DMA_3_0") (joined + (portRef O (instanceRef pos_clk_RW_000_DMA_3_0)) + (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_0_i)) + )) + (net N_123_i (joined + (portRef O (instanceRef N_123_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0)) + )) + (net N_124_i (joined + (portRef O (instanceRef N_124_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_i)) + )) + (net N_122_i (joined + (portRef O (instanceRef N_122_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + )) + (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + )) + (net N_242_i (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) + )) + (net N_239_i (joined + (portRef O (instanceRef RST_DLY_e2_i_o2_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_a2)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_0_a2)) + (portRef I0 (instanceRef RST_DLY_e2_i_o2_0_i)) + )) + (net N_87_i (joined + (portRef O (instanceRef N_87_i)) + (portRef I0 (instanceRef RST_DLY_e2_i_o2)) + )) + (net N_236_0 (joined + (portRef O (instanceRef RST_DLY_e2_i_o2)) + (portRef I0 (instanceRef RST_DLY_e2_i_o2_i)) )) (net N_246_i (joined (portRef O (instanceRef N_246_i)) - (portRef I0 (instanceRef CLK_030_H_2_i_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) )) - (net N_60_i (joined - (portRef O (instanceRef CLK_030_H_2_i_0)) - (portRef D (instanceRef CLK_030_H)) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + )) + (net N_245_i (joined + (portRef O (instanceRef N_245_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + )) + (net N_91_i (joined + (portRef O (instanceRef N_91_i)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_117_0)) + )) + (net N_210_i (joined + (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_117_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_a2_3)) + (portRef I0 (instanceRef RST_DLY_e1_i_a2_1_1)) + (portRef I0 (instanceRef RST_DLY_e2_i_a2_1_0)) + )) + (net (rename pos_clk_un19_bgack_030_int_i "pos_clk.un19_bgack_030_int_i") (joined + (portRef O (instanceRef pos_clk_un19_bgack_030_int)) + (portRef I0 (instanceRef pos_clk_un19_bgack_030_int_i_0)) + )) + (net N_163_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_2)) + )) + (net N_59_i (joined + (portRef O (instanceRef N_59_i)) + (portRef I0 (instanceRef cpu_est_0_0_0)) + )) + (net N_61_i (joined + (portRef O (instanceRef N_61_i)) + (portRef I1 (instanceRef cpu_est_0_0_0)) + )) + (net N_226_i (joined + (portRef O (instanceRef cpu_est_0_0_0)) + (portRef D (instanceRef cpu_est_0)) + )) + (net N_62_i (joined + (portRef O (instanceRef N_62_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) )) (net N_64_i (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) + (portRef O (instanceRef N_64_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + )) + (net N_142_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_244_i (joined + (portRef O (instanceRef N_244_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_3)) + )) + (net N_146_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_3)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net N_78_i_0 (joined + (portRef O (instanceRef N_78_i)) + (portRef I0 (instanceRef RST_DLY_e0_i_1)) + )) + (net N_79_i (joined + (portRef O (instanceRef N_79_i)) + (portRef I1 (instanceRef RST_DLY_e0_i_1)) + )) + (net N_234_i (joined + (portRef O (instanceRef RST_DLY_e0_i)) + (portRef D (instanceRef RST_DLY_0)) + )) + (net N_82_i (joined + (portRef O (instanceRef N_82_i)) + (portRef I0 (instanceRef RESET_OUT_2_0)) + )) + (net N_83_i (joined + (portRef O (instanceRef N_83_i)) + (portRef I1 (instanceRef RESET_OUT_2_0)) + )) + (net N_55_0 (joined + (portRef O (instanceRef RESET_OUT_2_0)) + (portRef I0 (instanceRef RESET_OUT_2_0_i)) + )) + (net N_88_i (joined + (portRef O (instanceRef N_88_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_i_o2_1_3)) + )) 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(portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_116_i (joined + (portRef O (instanceRef N_116_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + )) + (net N_117_i (joined + (portRef O (instanceRef N_117_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + )) + (net N_154_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0)) + (portRef D (instanceRef SM_AMIGA_i_7)) + )) + (net N_118_i (joined + (portRef O (instanceRef N_118_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_6)) + )) + (net N_152_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_6)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net N_119_i (joined + (portRef O (instanceRef N_119_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_5)) + )) + (net N_150_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_5)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_120_i (joined + (portRef O (instanceRef N_120_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_4)) + )) + (net N_148_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_4)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net N_171_i (joined + (portRef O (instanceRef N_171_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_2)) + )) + (net N_144_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_2)) + (portRef D (instanceRef SM_AMIGA_2)) + )) + (net N_121_i (joined + (portRef O (instanceRef N_121_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + )) + (net N_255_0 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + )) + (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_i)) + )) + (net N_48_0 (joined + (portRef O (instanceRef AS_030_D0_0_0)) + (portRef I0 (instanceRef AS_030_D0_0_0_i)) + )) + (net N_125_i (joined + (portRef O (instanceRef N_125_i)) + (portRef I0 (instanceRef AS_000_INT_0_i)) + )) + (net N_126_i (joined + (portRef O (instanceRef N_126_i)) + (portRef I1 (instanceRef AS_000_INT_0_i)) + )) + (net N_256_i (joined + (portRef O (instanceRef AS_000_INT_0_i)) + (portRef D (instanceRef AS_000_INT)) + )) + (net N_127_i (joined + (portRef O (instanceRef N_127_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i)) + )) + (net N_128_i (joined + (portRef O (instanceRef N_128_i)) + (portRef I1 (instanceRef DSACK1_INT_0_i)) + )) + (net N_257_i (joined + (portRef O (instanceRef DSACK1_INT_0_i)) + (portRef D (instanceRef DSACK1_INT)) + )) + (net RW_c_i (joined + (portRef O (instanceRef RW_c_i)) + (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0)) + )) + (net (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_i)) + )) + (net N_129_i (joined + (portRef O (instanceRef N_129_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_1)) + )) + (net N_258_i (joined + (portRef O (instanceRef CLK_030_H_2_i)) + (portRef D (instanceRef CLK_030_H)) + )) + (net N_259_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) (portRef D (instanceRef CYCLE_DMA_1)) )) (net un10_ciin_i (joined (portRef O (instanceRef un10_ciin_i)) - (portRef I1 (instanceRef un13_ciin_i_0_0)) + (portRef I1 (instanceRef un13_ciin_i_0)) )) - (net N_241_0 (joined - (portRef O (instanceRef un13_ciin_i_0_0)) - (portRef I0 (instanceRef un13_ciin_i_0_0_i)) + (net N_261_0 (joined + (portRef O (instanceRef un13_ciin_i_0)) + (portRef I0 (instanceRef un13_ciin_i_0_i)) )) - (net un1_DS_000_ENABLE_0_sqmuxa_i (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_i)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (net N_65_0 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_i)) )) - (net N_242_0 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + (net N_134_i (joined + (portRef O (instanceRef N_134_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i)) )) - (net N_48_i (joined - (portRef O (instanceRef un1_as_030_i_a2_i)) + (net N_153_i (joined + (portRef O (instanceRef N_153_i)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i)) + )) + (net N_67_0 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_i)) + )) + (net un2_as_030_i (joined + (portRef O (instanceRef un2_as_030_0)) (portRef OE (instanceRef SIZE_0)) (portRef OE (instanceRef SIZE_1)) )) - (net N_227_i (joined - (portRef O (instanceRef N_227_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + (net N_263_i (joined + (portRef O (instanceRef CLK_000_PE_0_o3_i_o2_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) + (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3_i_o2_i_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_0)) + (portRef I1 (instanceRef G_102)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_a2)) + (portRef I0 (instanceRef CLK_000_PE_0_o3_i_o2_i_o2_i)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) )) - (net N_155_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - (portRef D (instanceRef SM_AMIGA_i_7)) + (net N_265_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_a2)) + (portRef I0 (instanceRef AS_000_INT_0_i_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) )) - (net N_225_i (joined - (portRef O (instanceRef N_225_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_2_0)) )) - (net N_147_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef D (instanceRef SM_AMIGA_4)) + (net N_84_0 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_i_0)) )) - (net N_224_i (joined - (portRef O (instanceRef N_224_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + (net (rename CLK_000_D_i_2 "CLK_000_D_i[2]") (joined + (portRef O (instanceRef CLK_000_D_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_1)) )) - (net N_145_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_3)) - (portRef D (instanceRef SM_AMIGA_3)) + (net N_85_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_i_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_1)) )) - (net N_223_i (joined - (portRef O (instanceRef N_223_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (net N_141_i (joined + (portRef O (instanceRef N_141_i)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2)) )) - (net N_139_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_0)) - (portRef D (instanceRef SM_AMIGA_0)) + (net un1_DS_000_ENABLE_0_sqmuxa_i (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o2_i)) )) - (net N_218_i (joined - (portRef O (instanceRef N_218_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + (net (rename pos_clk_un21_bgack_030_int_i_0_i "pos_clk.un21_bgack_030_int_i_0_i") (joined + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o2)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_i)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i)) + (portRef I1 (instanceRef CLK_030_H_2_i)) )) - (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + (net N_269_i (joined + (portRef O (instanceRef N_156_i_0_o2_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_i_a2_3)) + (portRef I0 (instanceRef cpu_est_0_0_a2_0_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_a2_3)) + (portRef I0 (instanceRef N_156_i_0_o2_i_o2_i)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) + (portRef I1 (instanceRef RESET_OUT_2_0_a2_0_1)) )) - (net N_217_i (joined - (portRef O (instanceRef N_217_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + (net N_90_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0)) + (portRef I0 (instanceRef DSACK1_INT_0_i_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) )) - (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) + (net N_270_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o2)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0)) )) - (net N_213_i (joined - (portRef O (instanceRef N_213_i)) - (portRef I0 (instanceRef pos_clk_un35_as_030_d0_0_i)) + (net N_271_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_4)) )) - (net N_319_i (joined - (portRef O (instanceRef N_319_i)) - (portRef I1 (instanceRef pos_clk_un35_as_030_d0_0_i)) + (net N_96_0 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_i)) )) - (net N_300_0 (joined - (portRef O (instanceRef pos_clk_un35_as_030_d0_0_i)) - (portRef I0 (instanceRef pos_clk_un35_as_030_d0_0_i_i)) + (net N_97_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_6)) + )) + (net N_98_0 (joined + (portRef O (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2_i)) + )) + (net N_282_i (joined + (portRef O (instanceRef N_282_i)) + (portRef I1 (instanceRef un5_e_0_1)) + )) + (net N_284_i (joined + (portRef O (instanceRef N_284_i)) + (portRef I1 (instanceRef un5_e_0)) + )) + (net (rename pos_clk_un14_clk_000_ne_i "pos_clk.un14_clk_000_ne_i") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_ne_i)) + (portRef I0 (instanceRef un5_e_0_1)) + )) + (net un5_e_0 (joined + (portRef O (instanceRef un5_e_0)) + (portRef I0 (instanceRef un5_e_0_i)) + )) + (net N_285_i (joined + (portRef O (instanceRef N_285_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_2)) + (portRef I0 (instanceRef cpu_est_2_i_0_1_3)) + )) + (net N_291_i (joined + (portRef O (instanceRef N_291_i)) + (portRef I1 (instanceRef cpu_est_2_i_0_1_3)) + )) + (net N_292_i (joined + (portRef O (instanceRef N_292_i)) + (portRef I1 (instanceRef cpu_est_2_i_0_3)) + )) + (net N_192_i (joined + (portRef O (instanceRef cpu_est_2_i_0_3)) + (portRef I0 (instanceRef cpu_est_0_3__n)) + )) + (net N_17_i (joined + (portRef O (instanceRef N_17_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_2)) + )) + (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_i_2)) + )) + (net N_286_i (joined + (portRef O (instanceRef N_286_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_1)) + )) + (net N_288_i (joined + (portRef O (instanceRef N_288_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_1)) + )) + (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_i_1)) + )) + (net N_289_i (joined + (portRef O (instanceRef N_289_i)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0)) + )) + (net N_290_i (joined + (portRef O (instanceRef N_290_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0)) + )) + (net (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_i)) + )) + (net N_280_i (joined + (portRef O (instanceRef cpu_est_2_i_0_o2_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_2)) + (portRef I0 (instanceRef cpu_est_2_i_0_o2_i_3)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) + )) + (net (rename pos_clk_un10_sm_amiga_i "pos_clk.un10_sm_amiga_i") (joined + (portRef O (instanceRef pos_clk_un10_sm_amiga)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) + )) + (net (rename A_c_i_0 "A_c_i[0]") (joined + (portRef O (instanceRef A_c_i_0)) + (portRef I1 (instanceRef pos_clk_un10_sm_amiga_1)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I0 (instanceRef pos_clk_un10_sm_amiga_1)) + )) + (net N_27_i (joined + (portRef O (instanceRef N_27_i)) + (portRef I0 (instanceRef IPL_030_1_2)) + )) + (net N_30_0 (joined + (portRef O (instanceRef IPL_030_1_2)) + (portRef I0 (instanceRef IPL_030_1_i_2)) + )) + (net N_26_i (joined + (portRef O (instanceRef N_26_i)) + (portRef I0 (instanceRef IPL_030_1_1)) + )) + (net N_29_0 (joined + (portRef O (instanceRef IPL_030_1_1)) + (portRef I0 (instanceRef IPL_030_1_i_1)) + )) + (net N_25_i (joined + (portRef O (instanceRef N_25_i)) + (portRef I0 (instanceRef IPL_030_1_0)) + )) + (net N_28_0 (joined + (portRef O (instanceRef IPL_030_1_0)) + (portRef I0 (instanceRef IPL_030_1_i_0)) + )) + (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined + (portRef O (instanceRef IPL_c_i_2)) + (portRef I0 (instanceRef IPL_D0_0_2)) + )) + (net N_51_0 (joined + (portRef O (instanceRef IPL_D0_0_2)) + (portRef I0 (instanceRef IPL_D0_0_i_2)) + )) + (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined + (portRef O (instanceRef IPL_c_i_1)) + (portRef I0 (instanceRef IPL_D0_0_1)) + )) + (net N_50_0 (joined + (portRef O (instanceRef IPL_D0_0_1)) + (portRef I0 (instanceRef IPL_D0_0_i_1)) + )) + (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined + (portRef O (instanceRef IPL_c_i_0)) + (portRef I0 (instanceRef IPL_D0_0_0)) + )) + (net N_49_0 (joined + (portRef O (instanceRef IPL_D0_0_0)) + (portRef I0 (instanceRef IPL_D0_0_i_0)) + )) + (net N_4_i (joined + (portRef O (instanceRef N_4_i)) + (portRef I0 (instanceRef AS_000_DMA_1)) + )) + (net N_44_0 (joined + (portRef O (instanceRef AS_000_DMA_1)) + (portRef I0 (instanceRef AS_000_DMA_1_i)) + )) + (net N_14_i (joined + (portRef O (instanceRef N_14_i)) + (portRef I0 (instanceRef LDS_000_INT_1)) + )) + (net N_41_0 (joined + (portRef O (instanceRef LDS_000_INT_1)) + (portRef I0 (instanceRef LDS_000_INT_1_i)) )) (net N_15_i (joined (portRef O (instanceRef N_15_i)) (portRef I0 (instanceRef AS_030_000_SYNC_1)) )) - (net N_45_0 (joined + (net N_40_0 (joined (portRef O (instanceRef AS_030_000_SYNC_1)) (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) )) @@ -3599,418 +3548,298 @@ (portRef O (instanceRef N_16_i)) (portRef I0 (instanceRef RW_000_INT_1)) )) - (net N_44_0 (joined + (net N_39_0 (joined (portRef O (instanceRef RW_000_INT_1)) (portRef I0 (instanceRef RW_000_INT_1_i)) )) - (net N_22_i (joined - (portRef O (instanceRef N_22_i)) - (portRef I0 (instanceRef A0_DMA_1)) + (net N_18_i (joined + (portRef O (instanceRef N_18_i)) + (portRef I0 (instanceRef VMA_INT_1)) )) - (net N_38_0 (joined - (portRef O (instanceRef A0_DMA_1)) - (portRef I0 (instanceRef A0_DMA_1_i)) + (net N_37_0 (joined + (portRef O (instanceRef VMA_INT_1)) + (portRef I0 (instanceRef VMA_INT_1_i)) + )) + (net N_21_i (joined + (portRef O (instanceRef N_21_i)) + (portRef I0 (instanceRef UDS_000_INT_1)) + )) + (net N_34_0 (joined + (portRef O (instanceRef UDS_000_INT_1)) + (portRef I0 (instanceRef UDS_000_INT_1_i)) + )) + (net N_23_i (joined + (portRef O (instanceRef N_23_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + )) + (net N_32_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) + )) + (net LDS_000_INT_i (joined + (portRef O (instanceRef LDS_000_INT_i)) + (portRef I1 (instanceRef un1_LDS_000_INT)) + )) + (net un1_LDS_000_INT_0 (joined + (portRef O (instanceRef un1_LDS_000_INT)) + (portRef I0 (instanceRef un1_LDS_000_INT_i)) + )) + (net UDS_000_INT_i (joined + (portRef O (instanceRef UDS_000_INT_i)) + (portRef I1 (instanceRef un1_UDS_000_INT)) + )) + (net un1_UDS_000_INT_0 (joined + (portRef O (instanceRef un1_UDS_000_INT)) + (portRef I0 (instanceRef un1_UDS_000_INT_i)) + )) + (net N_96_0_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_3)) + )) + (net N_96_0_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2_3)) + )) + (net N_96_0_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_3)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2)) )) (net (rename pos_clk_un21_bgack_030_int_i_0_i_1 "pos_clk.un21_bgack_030_int_i_0_i_1") (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3_1)) - (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3)) + (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2)) )) - (net (rename pos_clk_un21_bgack_030_int_i_0_i_2 "pos_clk.un21_bgack_030_int_i_0_i_2") (joined - (portRef O (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3_2)) - (portRef I1 (instanceRef pos_clk_un21_bgack_030_int_i_0_o2_2_o3)) + (net N_84_0_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) )) - (net N_238_i_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e2_i_0)) + (net N_84_0_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) )) - (net N_238_i_2 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0)) - )) - (net N_239_i_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0)) - )) - (net N_239_i_2 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e1_i_0)) + (net N_240_0_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_o2_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_o2_3)) )) (net (rename pos_clk_un10_sm_amiga_i_1 "pos_clk.un10_sm_amiga_i_1") (joined (portRef O (instanceRef pos_clk_un10_sm_amiga_1)) (portRef I0 (instanceRef pos_clk_un10_sm_amiga)) )) + (net N_289_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3)) + )) + (net N_289_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3)) + )) + (net N_290_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) + )) + (net N_290_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) + )) + (net (rename pos_clk_un14_clk_000_ne_1 "pos_clk.un14_clk_000_ne_1") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3)) + )) + (net (rename pos_clk_un14_clk_000_ne_2 "pos_clk.un14_clk_000_ne_2") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un14_clk_000_ne_0_a2_0_a3)) + )) + (net N_153_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_4)) + )) + (net N_153_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_4)) + )) + (net N_153_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_3)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_5)) + )) + (net N_153_4 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_4)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0)) + )) + (net N_153_5 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_5)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0)) + )) (net un10_ciin_1 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_1)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_7)) + (portRef O (instanceRef un10_ciin_0_a2_1)) + (portRef I0 (instanceRef un10_ciin_0_a2_7)) )) (net un10_ciin_2 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_2)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_7)) + (portRef O (instanceRef un10_ciin_0_a2_2)) + (portRef I1 (instanceRef un10_ciin_0_a2_7)) )) (net un10_ciin_3 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_3)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_8)) + (portRef O (instanceRef un10_ciin_0_a2_3)) + (portRef I0 (instanceRef un10_ciin_0_a2_8)) )) (net un10_ciin_4 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_4)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_8)) + (portRef O (instanceRef un10_ciin_0_a2_4)) + (portRef I1 (instanceRef un10_ciin_0_a2_8)) )) (net un10_ciin_5 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_5)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_9)) + (portRef O (instanceRef un10_ciin_0_a2_5)) + (portRef I0 (instanceRef un10_ciin_0_a2_9)) )) (net un10_ciin_6 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_6)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_9)) + (portRef O (instanceRef un10_ciin_0_a2_6)) + (portRef I1 (instanceRef un10_ciin_0_a2_9)) )) (net un10_ciin_7 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_7)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_10)) + (portRef O (instanceRef un10_ciin_0_a2_7)) + (portRef I0 (instanceRef un10_ciin_0_a2_10)) )) (net un10_ciin_8 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_8)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3_10)) + (portRef O (instanceRef un10_ciin_0_a2_8)) + (portRef I1 (instanceRef un10_ciin_0_a2_10)) )) (net un10_ciin_9 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_9)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3_11)) + (portRef O (instanceRef un10_ciin_0_a2_9)) + (portRef I0 (instanceRef un10_ciin_0_a2_11)) )) (net un10_ciin_10 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_10)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a3)) + (portRef O (instanceRef un10_ciin_0_a2_10)) + (portRef I0 (instanceRef un10_ciin_0_a2)) )) (net un10_ciin_11 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a3_11)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a3)) + (portRef O (instanceRef un10_ciin_0_a2_11)) + (portRef I1 (instanceRef un10_ciin_0_a2)) )) - (net N_357_1 (joined - (portRef O (instanceRef un21_berr_0_a2_0_a2_1)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2_4)) + (net N_260_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) )) - (net N_357_2 (joined - (portRef O (instanceRef un21_berr_0_a2_0_a2_2)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2_4)) + (net N_260_i_2 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) )) - (net N_357_3 (joined - (portRef O (instanceRef un21_berr_0_a2_0_a2_3)) - (portRef I1 (instanceRef un21_berr_0_a2_0_a2)) + (net N_233_i_1 (joined + (portRef O (instanceRef RST_DLY_e1_i_1)) + (portRef I0 (instanceRef RST_DLY_e1_i)) )) - (net N_357_4 (joined - (portRef O (instanceRef un21_berr_0_a2_0_a2_4)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a2)) + (net N_233_i_2 (joined + (portRef O (instanceRef RST_DLY_e1_i_2)) + (portRef I1 (instanceRef RST_DLY_e1_i)) )) - (net N_304_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) + (net N_232_i_1 (joined + (portRef O (instanceRef RST_DLY_e2_i_1)) + (portRef I0 (instanceRef RST_DLY_e2_i)) )) - (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3)) + (net N_232_i_2 (joined + (portRef O (instanceRef RST_DLY_e2_i_2)) + (portRef I1 (instanceRef RST_DLY_e2_i)) )) - (net un21_berr_1_0 (joined - (portRef O (instanceRef un21_berr_0_a2_0_a3_1_0)) - (portRef I0 (instanceRef un21_berr_0_a2_0_a3)) + (net N_247_1 (joined + (portRef O (instanceRef RST_DLY_e2_i_a2_1_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_a2)) )) - (net N_266_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0)) + (net N_77_1 (joined + (portRef O (instanceRef RST_DLY_e1_i_a2_1_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_a2_1)) )) - (net N_266_2 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0)) + (net N_83_1 (joined + (portRef O (instanceRef RESET_OUT_2_0_a2_0_1)) + (portRef I0 (instanceRef RESET_OUT_2_0_a2_0)) )) - (net N_67_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + (net N_88_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_a2_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_a2_0_3)) )) - (net N_67_i_2 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + (net N_142_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) )) - (net N_314_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) + (net N_146_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_3)) )) - (net N_314_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) - )) - (net N_318_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) - )) - (net N_318_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) - )) - (net N_341_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - )) - (net N_341_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - )) - (net N_151_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_6)) - )) - (net N_143_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2)) - )) - (net N_141_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1)) - )) - (net N_237_0_1 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0)) - )) - (net N_240_i_1 (joined - (portRef O (instanceRef RST_DLY_e0_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e0_i_0)) - )) - (net N_60_i_1 (joined - (portRef O (instanceRef CLK_030_H_2_i_0_1)) - (portRef I0 (instanceRef CLK_030_H_2_i_0)) - )) - (net N_64_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) - )) - (net N_155_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - )) - (net N_147_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4)) - )) - (net N_145_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - )) - (net N_139_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_0)) + (net N_234_i_1 (joined + (portRef O (instanceRef RST_DLY_e0_i_1)) + (portRef I0 (instanceRef RST_DLY_e0_i)) )) (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2)) )) - (net N_220_1 (joined + (net N_124_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a2_0)) + )) + (net un21_berr_1 (joined + (portRef O (instanceRef un21_berr_0_a2_1)) + (portRef I0 (instanceRef un21_berr_0_a2)) + )) + (net un21_fpu_cs_1 (joined + (portRef O (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2)) + )) + (net N_140_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0)) + )) + (net N_154_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0)) + )) + (net N_152_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_6)) + )) + (net N_150_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_5)) + )) + (net N_148_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_4)) + )) + (net N_144_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_2)) + )) + (net N_255_0_1 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i)) + )) + (net N_258_i_1 (joined + (portRef O (instanceRef CLK_030_H_2_i_1)) + (portRef I0 (instanceRef CLK_030_H_2_i)) + )) + (net N_259_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + )) + (net N_282_1 (joined + (portRef O (instanceRef un5_e_0_a3_1)) + (portRef I0 (instanceRef un5_e_0_a3)) + )) + (net N_284_1 (joined + (portRef O (instanceRef un5_e_0_a3_0_1)) + (portRef I0 (instanceRef un5_e_0_a3_0)) + )) + (net N_288_1 (joined (portRef O (instanceRef cpu_est_2_0_0_a3_0_1_1)) (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1)) )) - (net N_216_1 (joined - (portRef O (instanceRef RESET_OUT_2_i_i_a3_0_1)) - (portRef I0 (instanceRef RESET_OUT_2_i_i_a3_0)) + (net un5_e_0_1 (joined + (portRef O (instanceRef un5_e_0_1)) + (portRef I0 (instanceRef un5_e_0)) )) - (net N_205_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3_1_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_1)) - )) - (net N_199_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_1_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3)) + (net N_192_i_1 (joined + (portRef O (instanceRef cpu_est_2_i_0_1_3)) + (portRef I0 (instanceRef cpu_est_2_i_0_3)) )) (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined (portRef O (instanceRef G_110_1)) (portRef I0 (instanceRef G_110)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) - )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) - )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) - )) - (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined - (portRef O (instanceRef DSACK1_INT_0_r)) - (portRef I1 (instanceRef DSACK1_INT_0_n)) - )) - (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined - (portRef O (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_p)) - )) - (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined - (portRef O (instanceRef DSACK1_INT_0_n)) - (portRef I1 (instanceRef DSACK1_INT_0_p)) - )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) - )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) - )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) - )) - (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined - (portRef O (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_3__n)) - )) - (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined - (portRef O (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined - (portRef O (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) - )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) - )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) - )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - )) - (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined - (portRef O (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_n)) - )) - (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined - (portRef O (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_p)) - )) - (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined - (portRef O (instanceRef RW_000_DMA_0_n)) - (portRef I1 (instanceRef RW_000_DMA_0_p)) - )) - (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined - (portRef O (instanceRef AS_000_DMA_0_r)) - (portRef I1 (instanceRef AS_000_DMA_0_n)) - )) - (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined - (portRef O (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_p)) - )) - (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined - (portRef O (instanceRef AS_000_DMA_0_n)) - (portRef I1 (instanceRef AS_000_DMA_0_p)) - )) - (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined - (portRef O (instanceRef DS_000_DMA_0_r)) - (portRef I1 (instanceRef DS_000_DMA_0_n)) - )) - (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined - (portRef O (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_p)) - )) - (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined - (portRef O (instanceRef DS_000_DMA_0_n)) - (portRef I1 (instanceRef DS_000_DMA_0_p)) - )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) - )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) - )) (net (rename BG_000_0_un3 "BG_000_0.un3") (joined (portRef O (instanceRef BG_000_0_r)) (portRef I1 (instanceRef BG_000_0_n)) @@ -4023,41 +3852,65 @@ (portRef O (instanceRef BG_000_0_n)) (portRef I1 (instanceRef BG_000_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.un3") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__r)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__n)) + (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined + (portRef O (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_n)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.un1") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__p)) + (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined + (portRef O (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_p)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0_.un0") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__n)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_i_m2_0__p)) + (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined + (portRef O (instanceRef A0_DMA_0_n)) + (portRef I1 (instanceRef A0_DMA_0_p)) )) - (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_0__r)) - (portRef I1 (instanceRef SIZE_DMA_0_0__n)) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) )) - (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_0_0__p)) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) )) - (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_0__n)) - (portRef I1 (instanceRef SIZE_DMA_0_0__p)) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) + )) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) + )) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) + )) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) )) (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined (portRef O (instanceRef SIZE_DMA_0_1__r)) @@ -4071,6 +3924,138 @@ (portRef O (instanceRef SIZE_DMA_0_1__n)) (portRef I1 (instanceRef SIZE_DMA_0_1__p)) )) + (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_0__n)) + )) + (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__p)) + )) + (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_0__n)) + (portRef I1 (instanceRef SIZE_DMA_0_0__p)) + )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un3") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) + )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un1") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) + )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un0") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) + )) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) + )) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined + (portRef O (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) + )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) + )) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) + )) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) + )) (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined (portRef O (instanceRef DS_000_ENABLE_0_r)) (portRef I1 (instanceRef DS_000_ENABLE_0_n)) @@ -4083,6 +4068,18 @@ (portRef O (instanceRef DS_000_ENABLE_0_n)) (portRef I1 (instanceRef DS_000_ENABLE_0_p)) )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined (portRef O (instanceRef AS_030_000_SYNC_0_r)) (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) @@ -4107,17 +4104,17 @@ (portRef O (instanceRef RW_000_INT_0_n)) (portRef I1 (instanceRef RW_000_INT_0_p)) )) - (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined - (portRef O (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef A0_DMA_0_n)) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) )) - (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined - (portRef O (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_p)) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) )) - (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined - (portRef O (instanceRef A0_DMA_0_n)) - (portRef I1 (instanceRef A0_DMA_0_p)) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) )) ) (property orig_inst_of (string "BUS68030")) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 49666ab..4aa1db1 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj -#-- Written on Wed Sep 14 23:54:13 2016 +#-- Written on Thu Oct 06 21:34:26 2016 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index e76f9b9..d7b4466 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -201,8 +201,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#jRU6 -.;N3PR#_$MD HMC8sHR("{(UwUc-dUnw.(-ccwnA-g(gw-.7q666jq }(A"N; +RNP3M#$_lMkOsEN#(R(c +j;N3PR#_$MD HMC8sHRq"{Un4 n-6Uww7d-Ac6c7-UUB.-ABUABdc A}cq"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -353,35 +353,33 @@ F@:@(64U:::6UcQ:BQBhRQ;Qh RNH3Ds0_HFsolMNCBR"Q"Qh;L oR4qr9N; LLR3HF0bsH08s;R4 -RoMk_M4NolHNk_L#M_CNCLD_IDF;M -NRN3#PMC_CV0_D#No46R.no; -MMRkn#_N_jjd;M -NRN3#PMC_CV0_D#No46R.no; -MMRkdH_#x -C;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_Mc#CHx;M +RoMk_M6CN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRMN4_lNHo_#Lk_NCML_DCD;FI +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR(kM__N#j;dj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kM_1z7_jjj_aQh;M NRN3#PMC_CV0_D#No46R.no; MMRk47_p1j_jjh_QaN; M#R3N_PCM_C0VoDN#.4R6 -n;okMRMz4_7j1_jQj_h -a;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_M41qv_vqQt_#j_JGlkN;_4 +n;okMRM14_vv_qQ_tqjJ_#lNkG_ +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMk_M47j1_j j_hpqA __j#kJlG +N;N3MR#CNP_0MC_NVDoR#4.;6n +RoMkjM4_HOHMN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRM_.4V_bkO +#;N3MR#CNP_0MC_NVDoR#4.;6n +RoMk4M._sLCsN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRM8n_#d_jjN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_ +c;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_n RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4kM__71j_jj Ahqpj __l#Jk;GN -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRckM__N#j;jj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4kMjH_OH -M;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk4M._kVb_;O# -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.kM4C_Ls -s;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_Mn8j#_d -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_( -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRUh_;M +oR(h_;M NRN3#PMC_CV0_D#No46R.no; M_RhgN; M#R3N_PCM_C0VoDN#.4R6 @@ -391,11 +389,27 @@ oR4h_.N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;4d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_6N; +oR4h_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4n +n;ohMR_;46 RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_.N; +oR4h_nN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;4U +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_4N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.d +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_6N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.n +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_(N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.U +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_gN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;dj RNM3P#NCC_M0D_VN4o#Rn.6;M @@ -413,39 +427,39 @@ n;ohMR_;dn RNM3P#NCC_M0D_VN4o#Rn.6;M oRdh_(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;dU +n;ohMR_;dg RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_gN; +oRch_jN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cj +n;ohMR_;c4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_4N; +oRch_.N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cd +n;ohMR_;cc RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_cN; +oRch_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;c6 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_nN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;c( +n;ohMR_;cU RNM3P#NCC_M0D_VN4o#Rn.6;M oRch_gN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;6j RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_.N; +oR6h_4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;6d +n;ohMR_;6. RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_cN; +oR6h_dN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;66 RNM3P#NCC_M0D_VN4o#Rn.6;M oR6h_nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;6g +n;ohMR_;nU +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRnh_gN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;(j RNM3P#NCC_M0D_VN4o#Rn.6;M oR(h_4N; M#R3N_PCM_C0VoDN#.4R6 @@ -457,107 +471,27 @@ n;ohMR_;(c RNM3P#NCC_M0D_VN4o#Rn.6;M oR(h_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(n -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_(N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(U -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_4 -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_.4N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_..4;M +n;ohMR_n.j;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;d( +M_Rh.;j( RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_c -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_..N; +oR.h_j +U;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh6_.cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_d.U;M +n;ohMR_6.6;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;gc +M_Rh.;n4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_j -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_d4N; +oR.h_n +g;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh(_.UN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_gd4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rhd;d. +n;oAMRtj_jj3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_d -c;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_ddN; +oR_Atj_jjjM3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_(d6;M -NRN3#PMC_CV0_D#No46R.no; -M7Rz1j_jjh_Qa3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR1z7_jjj_aQh_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMz_71j_jjQ_hajM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1j_jjh_Qa3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1j_jjh_Qa3_jk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRq71B_i4Q_hajM3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;o7MR1iqB4h_Qa3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRq71B_i4Q_hajM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oeMRvQq_hja_3dkM;M -NRN3#PMC_CV0_D#No46R.no; -MvReqh_Qa3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqev_aQh_kj3M -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMp_71j_jjQ_hajM3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;opMR7j1_jQj_hja_34kM;M -NRN3#PMC_CV0_D#No46R.no; -M7Rp1j_jjh_Qa3_jk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_4j__M3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__34_k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_4j__M3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3j_k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_jj__M3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3j_k;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_dj__M3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3d_k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_dj__M3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3._k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_.j__M3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3._k;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_4j__M3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__34_k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_4j__M3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3._k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_.j__M3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3._k;Mj +n;oAMRtj_jj3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oRQqvtAq_z 1_hpqA v_7qm_pW3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M @@ -565,47 +499,35 @@ oRQqvtAq_z 1_hpqA v_7qm_pW3_jk;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M oRQqvtAq_z 1_hpqA v_7qm_pW3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_)Wj_jj7_vqjM3kdN; +oR_qj7_vqjM3kdN; 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diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 322d342..7dd4de7 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Wed Sep 14 23:54:20 2016 +#Thu Oct 06 21:34:49 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -25,9 +25,10 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register DS_030_D0_3 @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register nEXP_SPACE_D0_3 @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning register BGACK_030_INT_PRE_2 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_2 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":126:36:126:38|Pruning register CLK_OUT_PRE_25_3 @W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":154:2:154:3|Pruning register CLK_030_D0_2 -@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 3 of CLK_000_D_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... @N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:38:131:40|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: @@ -46,7 +47,7 @@ State machine has 8 reachable states with original encodings of: At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Sep 14 23:54:21 2016 +# Thu Oct 06 21:34:49 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -56,7 +57,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Sep 14 23:54:22 2016 +# Thu Oct 06 21:34:50 2016 ###########################################################] Map & Optimize Report @@ -80,15 +81,15 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 54 uses +DFF 55 uses BI_DIR 18 uses BUFTH 4 uses IBUF 38 uses OBUF 15 uses -AND2 269 uses -INV 239 uses -OR2 25 uses -XOR2 6 uses +AND2 272 uses +INV 237 uses +OR2 23 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -98,6 +99,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Sep 14 23:54:22 2016 +# Thu Oct 06 21:34:50 2016 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 44e539ae5951ec87cffaa66d6de4e1ee4d7080a3..7ec3484afe21bea5cf7bfb19a3d04435b9d2f013 100644 GIT binary patch delta 12211 zcmV;kFHF$ZWS?SxABzY80000001JFlON-ku5WeSE3<-f2l3+XDJbY>!a#(0LWwYCp zAjq;350ND!jY(bd<2!PsjAp*4Je^LV^^UZn->0rlXEb^=8BO3xlfgi6^GKvE zI14Xz2M69xR*&8`$kq{&FBr0O zZSV0?6TI8KhjhEm=W!INTpRi@gGZ|tEQ$ewJJU^i4boOXHJ>3kg_0dZY}k~uriW5P7nly2Ln-GgX_bZ>QauQg_DvY%m9rH_tpM%}@=rk= zU)#XeE?(<@Xy_OCA9eU>3^-==QEmoav)iguk#GjiL&e>BEW05M3(#M7<2R2Lv110- zSR!|@h%Yvp9KOCh9-fZH_&$&2-{<7o`@HE4Venx*n(SVmi}Ah?0z>gbn3|fd1?J6HGPL_WN&c4v!^|(m$B+ar*JY8mQTs!9C7(NKmNczE0+2BPA zQA=M%!?jdb94Mb3GLt;r89c?a2dVzmYj$5%a!BL zuHD1fpEjs}-M@B?FLXF1{DS^s|M?4~Qn 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zF~g8Qs=X`5{E>er(19@%eEDOtopH?K<8+r}zg&Qai|^I9Ts&@wmwEA9p8u97-*WNo zM_%|gdBo|M(tkOiG0cn=#XU{u_x@+c^&}s1W~?jX`V5!8UwO=M@7b_TTO1|E+(o>M&Snd(z|nq#YRfRHXhJLr}TceBW&xrGgqW8 zwc00Z5LAEIuc*5hzE_ZyD)V{dx-k;fwp(KtGmqu^_WGIp`6I~YTlHM4iKb-pAZB8G z1Ls3Yhmm=(LazESD9M`1*%u#5c89TVRmU_B^5;>@d=WX8fp-41r1^vEzPd+QaLD(Y z!|%8GBGue#Wl_|5S6r+WB~Of!J2q~>|Nb8U0RI*L;&M>n0ssI2|NjF3Dn)p(m#qK* DMZu{q diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index 7a1f330..acb1ab4 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -18,9 +18,9 @@ 1 0 - C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk-50Mhz-New.jed - 08/30/16 22:39:22 - 0xE8C5 + C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed + 09/14/16 23:54:30 + 0xD04F Erase,Program,Verify