From 7b64ad431c5f4ddd992ef65e05d3e742aa997690 Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Fri, 19 Aug 2016 00:42:01 +0200 Subject: [PATCH] Horray! No Sync of Pos and Neg edges needed anymore! --- Logic/68030-68000-bus.vhd | 42 +- Logic/68030_TK.tcl | 1671 +++++ Logic/68030_tk.bl2 | 3123 ++++----- Logic/68030_tk.bl3 | 1140 ++-- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 612 +- Logic/68030_tk.fti | 316 +- Logic/68030_tk.grp | 43 +- Logic/68030_tk.ipr | 2 +- Logic/68030_tk.jed | 1299 ++-- Logic/68030_tk.lco | 166 +- Logic/68030_tk.nrp | 24 + Logic/68030_tk.out | 1208 +++- Logic/68030_tk.plc | 186 +- Logic/68030_tk.prd | 1428 ++-- Logic/68030_tk.rpt | 1445 ++-- Logic/68030_tk.tal | 65 +- Logic/68030_tk.tt2 | 1170 ++-- Logic/68030_tk.tt3 | 1170 ++-- Logic/68030_tk.tt4 | 570 +- Logic/68030_tk.tte | 570 +- Logic/68030_tk.vcl | 122 +- Logic/68030_tk.vco | 166 +- Logic/68030_tk.vho | 3983 +++++++++++ Logic/68030_tk.xrf | 2 +- Logic/BUS68030.bl0 | 3186 +++++---- Logic/BUS68030.bl1 | 3123 ++++----- Logic/BUS68030.edi | 5186 +++++++-------- Logic/BUS68030.fse | 20 +- Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 5873 ++++++++--------- Logic/BUS68030.srr | 42 +- Logic/BUS68030.srs | Bin 13588 -> 13350 bytes Logic/automake.err | 1 - Logic/bus68030.exf | 1002 ++- Logic/bus68030.srf | 42 +- Logic/dm/BUS68030_comp.xdm | 2 +- Logic/run_options.txt | 2 +- Logic/synlog/BUS68030_multi_srs_gen.srr | 2 +- Logic/synlog/bus68030_fpga_mapper.srr | 14 +- .../synlog/report/BUS68030_compiler_notes.txt | 8 +- .../report/BUS68030_compiler_runstatus.xml | 2 +- .../report/BUS68030_compiler_warnings.txt | 14 +- .../report/BUS68030_fpga_mapper_runstatus.xml | 2 +- Logic/syntmp/BUS68030_srr.htm | 60 +- Logic/syntmp/BUS68030_toc.htm | 2 +- Logic/syntmp/run_option.xml | 2 +- Logic/syntmp/statusReport.html | 6 +- Logic/synwork/BUS68030_comp.fdep | 2 +- Logic/synwork/BUS68030_comp.fdeporig | 2 +- Logic/synwork/BUS68030_comp.srs | Bin 13047 -> 12878 bytes Logic/synwork/BUS68030_comp.tlg | 22 +- Logic/synwork/BUS68030_mult.srs | Bin 13588 -> 13350 bytes Logic/synwork/BUS68030_mult_srs/skeleton.srs | Bin 1222 -> 1222 bytes Logic/synwork/BUS68030_s.srs | Bin 13047 -> 12878 bytes 55 files changed, 22061 insertions(+), 17083 deletions(-) create mode 100644 Logic/68030_tk.nrp create mode 100644 Logic/68030_tk.vho diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index acc9e3b..e6dc186 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -61,10 +61,8 @@ end BUS68030; architecture Behavioral of BUS68030 is --- values are determined empiracally for 7.09 MHz Clock with a base clock of 100Mhz -constant PE_CLK : integer := 10; -constant NE_CLK : integer := 12; -constant DS_SAMPLE : integer := 12; +-- values are determined empirically +constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ @@ -132,25 +130,17 @@ signal CLK_OUT_INT: STD_LOGIC := '1'; signal CLK_OUT_EXP_INT: STD_LOGIC := '1'; signal CLK_030_H: STD_LOGIC := '1'; signal CLK_000_D: STD_LOGIC_VECTOR ( DS_SAMPLE downto 0 ); -signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( PE_CLK downto 0 ); -signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( NE_CLK downto 0 ); signal CLK_000_PE: STD_LOGIC := '0'; signal CLK_000_NE: STD_LOGIC := '0'; -signal CLK_000_NE_D0: STD_LOGIC := '0'; signal DTACK_D0: STD_LOGIC := '1'; signal RESET_OUT: STD_LOGIC := '0'; signal CLK_030_D0: STD_LOGIC := '0'; ---signal NO_RESET: STD_LOGIC := '0'; signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000"; ---signal RST_DLY_AMIGA: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000"; ---signal RESET_OUT_AMIGA: STD_LOGIC := '0'; begin - CLK_000_PE <= CLK_000_P_SYNC(PE_CLK); - CLK_000_NE <= CLK_000_N_SYNC(NE_CLK); - --CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1); - --CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2); + CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1); + CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1); --pos edge clock process @@ -180,17 +170,9 @@ begin CLK_000_D(0) <= CLK_000; CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0); - --shift registers for edge detection - CLK_000_P_SYNC( PE_CLK downto 1 ) <= CLK_000_P_SYNC( (PE_CLK-1) downto 0 ); - CLK_000_P_SYNC(0) <= CLK_000_D(0) AND NOT CLK_000_D(1); - CLK_000_N_SYNC( NE_CLK downto 1 ) <= CLK_000_N_SYNC( (NE_CLK-1) downto 0 ); - CLK_000_N_SYNC(0) <= NOT CLK_000_D(0) AND CLK_000_D(1); - - CLK_000_NE_D0 <= CLK_000_NE; - -- e-clock is changed on the FALLING edge! - if(CLK_000_NE_D0 = '1' ) then + if(CLK_000_NE = '1' ) then case (cpu_est) is when E1 => cpu_est <= E2 ; when E2 => cpu_est <= E3 ; @@ -363,13 +345,13 @@ begin when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe if(CLK_000_PE='1')then --go to s2 SM_AMIGA <= AS_SET_P; --as for amiga set! + RW_000_INT <= RW; + AS_000_INT <= '0'; + if (RW='1' ) then --read: set udl/lds + DS_000_ENABLE <= '1'; + end if; end if; when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here - RW_000_INT <= RW; - AS_000_INT <= '0'; - if (RW='1' ) then --read: set udl/lds - DS_000_ENABLE <= '1'; - end if; if(CLK_000_NE='1')then --go to s3 SM_AMIGA<=AS_SET_N; end if; @@ -382,7 +364,7 @@ begin end if; when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA DS_000_ENABLE <= '1'; - if( CLK_000_NE_D0='1' and --falling edge + if( CLK_000_NE='1' and --falling edge ((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle (VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle )then --go to s5 @@ -496,7 +478,7 @@ begin -- bus drivers AMIGA_ADDR_ENABLE <= '0'; - AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE + AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and AS_030_000_SYNC='0' else --not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE '1'; AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index cec1bdd..3cf99e5 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -369264,3 +369264,1674 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 08/19/16 00:20:27 ########### + +########## Tcl recorder starts at 08/19/16 00:22:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:22:47 ########### + + +########## Tcl recorder starts at 08/19/16 00:22:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:22:47 ########### + + +########## Tcl recorder starts at 08/19/16 00:24:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:24:31 ########### + + +########## Tcl recorder starts at 08/19/16 00:24:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:24:31 ########### + + +########## Tcl recorder starts at 08/19/16 00:25:25 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:25:25 ########### + + +########## Tcl recorder starts at 08/19/16 00:25:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:25:25 ########### + + +########## Tcl recorder starts at 08/19/16 00:26:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:26:30 ########### + + +########## Tcl recorder starts at 08/19/16 00:26:30 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:26:30 ########### + + +########## Tcl recorder starts at 08/19/16 00:29:25 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:29:25 ########### + + +########## Tcl recorder starts at 08/19/16 00:29:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:29:25 ########### + + +########## Tcl recorder starts at 08/19/16 00:32:29 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:32:29 ########### + + +########## Tcl recorder starts at 08/19/16 00:32:30 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:32:30 ########### + + +########## Tcl recorder starts at 08/19/16 00:35:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:35:17 ########### + + +########## Tcl recorder starts at 08/19/16 00:35:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:35:17 ########### + + +########## Tcl recorder starts at 08/19/16 00:38:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:38:08 ########### + + +########## Tcl recorder starts at 08/19/16 00:38:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:38:09 ########### + + +########## Tcl recorder starts at 08/19/16 00:39:20 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:39:20 ########### + + +########## Tcl recorder starts at 08/19/16 00:39:21 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:39:21 ########### + + +########## Tcl recorder starts at 08/19/16 00:39:48 ########## + +# Commands to make the Process: +# Report File +if [catch {open 68030_tk.rss w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rss: $rspFile" +} else { + puts $rspFile "-i \"68030_tk.tte\" -lib \"$install_dir/ispcpld/dat/mach4a\" -strategy top -sdfmdl \"$install_dir/ispcpld/dat/sdf.mdl\" -simmdl \"$install_dir/ispcpld/dat/sim.mdl\" -pla \"68030_tk.tte\" -lci \"68030_tk.lct\" -prj \"68030_tk\" -dir \"$proj_dir\" -err automake.err -log \"68030_tk.nrp\" -exf \"BUS68030.exf\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/sdf\" \"@68030_tk.rss\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rss + +########## Tcl recorder end at 08/19/16 00:39:48 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 362f1eb..528a282 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,128 +1,121 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE 68030_tk -#$ PINS 75 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \ -# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ \ -# A_DECODE_13_ IPL_030_2_ A_DECODE_12_ A_DECODE_11_ IPL_2_ A_DECODE_10_ A_DECODE_9_ \ -# FC_1_ A_DECODE_8_ AS_030 A_DECODE_7_ AS_000 A_DECODE_6_ RW_000 A_DECODE_5_ DS_030 \ -# A_DECODE_4_ UDS_000 A_DECODE_3_ LDS_000 A_DECODE_2_ nEXP_SPACE A_0_ BERR IPL_030_1_ \ -# BG_030 IPL_030_0_ BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 \ -# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW \ -# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ -# CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ -#$ NODES 694 N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n \ -# N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 pos_clk_un10_sm_amiga_i_n \ -# cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i \ -# sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 \ -# cpu_est_2_0_2__n vma_int_0_un3_n inst_BGACK_030_INTreg N_223 N_315_i \ -# vma_int_0_un1_n vcc_n_n N_343 N_291_0 vma_int_0_un0_n inst_VMA_INTreg N_192 \ -# AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n \ -# un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n \ -# un1_amiga_bus_enable_low N_315 N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 \ -# cpu_est_2_2__n N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ -# sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ -# un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ -# rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ -# N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ -# un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ -# cpu_est_2_ pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n cpu_est_3_ \ -# un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n cpu_est_0_ un21_fpu_cs_i \ -# N_226_i ds_000_enable_0_un1_n cpu_est_1_ N_275_i ds_000_enable_0_un0_n \ -# inst_AS_000_INT clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n \ -# inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ -# inst_AS_030_D0 rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n inst_AS_030_000_SYNC \ -# BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n inst_BGACK_030_INT_D \ -# cpu_est_i_2__n N_217_i un1_amiga_bus_enable_dma_high_0_m2_0__un1_n \ -# inst_AS_000_DMA nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n \ -# inst_DS_000_DMA rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n \ -# CYCLE_DMA_0_ cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n CYCLE_DMA_1_ \ -# cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n SIZE_DMA_0_ VPA_D_i N_195_0 \ -# amiga_bus_enable_dma_high_0_un3_n SIZE_DMA_1_ sm_amiga_i_3__n N_190_0 \ -# amiga_bus_enable_dma_high_0_un1_n inst_VPA_D sm_amiga_i_0__n N_157_i \ -# amiga_bus_enable_dma_high_0_un0_n inst_UDS_000_INT cpu_est_i_3__n N_154_i \ -# size_dma_0_0__un3_n inst_LDS_000_INT sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n \ -# inst_CLK_OUT_PRE_D RESET_OUT_i N_141_0 size_dma_0_0__un0_n CLK_000_D_10_ \ -# BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n CLK_000_D_11_ sm_amiga_i_2__n \ -# N_216_i size_dma_0_1__un1_n inst_DTACK_D0 sm_amiga_i_4__n N_337_i \ -# size_dma_0_1__un0_n inst_RESET_OUT clk_000_p_sync_i_10__n ds_000_dma_0_un3_n \ -# inst_CLK_OUT_PRE_50 sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n CLK_000_D_1_ \ -# sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n CLK_000_D_0_ clk_000_d_i_11__n \ -# un1_as_000_i as_000_dma_0_un3_n CLK_000_P_SYNC_10_ sm_amiga_i_6__n N_284_i \ -# as_000_dma_0_un1_n SM_AMIGA_5_ RW_i N_285_i as_000_dma_0_un0_n IPL_D0_0_ \ -# DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n IPL_D0_1_ LDS_000_INT_i N_280_i \ -# rw_000_dma_0_un1_n IPL_D0_2_ UDS_000_INT_i N_277_i rw_000_dma_0_un0_n CLK_000_D_2_ \ -# AS_030_i N_257_0 a0_dma_0_un3_n CLK_000_D_3_ AS_000_INT_i N_235_i a0_dma_0_un1_n \ -# CLK_000_D_4_ a_decode_i_19__n N_236_i a0_dma_0_un0_n CLK_000_D_5_ a_decode_i_18__n \ -# cpu_est_2_0_1__n a_decode_15__n CLK_000_D_6_ a_decode_i_16__n N_231_i CLK_000_D_7_ \ -# AS_000_i N_230_i a_decode_14__n CLK_000_D_8_ FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ -# CLK_000_D_9_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_000_D_12_ \ -# CLK_030_i N_37_0 pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n SM_AMIGA_0_ \ -# clk_000_d_i_10__n N_334_i inst_DSACK1_INTreg RW_000_i N_335_i a_decode_11__n \ -# a_i_1__n N_194_0 CLK_030_H_i N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i \ -# un1_SM_AMIGA_5_i CLK_000_N_SYNC_0_ clk_000_d_i_0__n N_346_i a_decode_9__n \ -# SM_AMIGA_4_ clk_000_d_i_1__n N_163_i inst_DS_000_ENABLE AS_030_D0_i N_345_i \ -# a_decode_8__n CLK_000_N_SYNC_12_ size_dma_i_0__n N_344_i RST_DLY_0_ size_dma_i_1__n \ -# N_153_0 a_decode_7__n RST_DLY_1_ ahigh_i_30__n pos_clk_un3_as_030_d0_i_n RST_DLY_2_ \ -# ahigh_i_31__n N_293_0 a_decode_6__n CLK_000_P_SYNC_0_ ahigh_i_28__n N_233_i \ -# CLK_000_P_SYNC_1_ ahigh_i_29__n N_232_i a_decode_5__n CLK_000_P_SYNC_2_ \ -# ahigh_i_26__n N_290_0 CLK_000_P_SYNC_3_ ahigh_i_27__n VPA_c_i a_decode_4__n \ -# CLK_000_P_SYNC_4_ ahigh_i_24__n N_54_0 CLK_000_P_SYNC_5_ ahigh_i_25__n N_5_i \ -# a_decode_3__n CLK_000_P_SYNC_6_ N_212_i N_47_0 CLK_000_P_SYNC_7_ N_213_i N_7_i \ -# a_decode_2__n CLK_000_P_SYNC_8_ N_214_i N_46_0 CLK_000_P_SYNC_9_ N_18_i \ -# CLK_000_N_SYNC_1_ N_41_0 CLK_000_N_SYNC_2_ N_321_i N_10_i CLK_000_N_SYNC_3_ N_322_i \ -# N_43_0 CLK_000_N_SYNC_4_ un6_ds_030_i DTACK_c_i CLK_000_N_SYNC_5_ DS_000_DMA_i \ -# N_55_0 CLK_000_N_SYNC_6_ un4_as_000_i pos_clk_un6_bgack_000_0_n CLK_000_N_SYNC_7_ \ -# un6_as_030_i N_137_i CLK_000_N_SYNC_8_ un4_lds_000_i N_184_0 CLK_000_N_SYNC_9_ \ -# un4_uds_000_i N_349_i CLK_000_N_SYNC_10_ AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i \ -# CLK_000_N_SYNC_11_ AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i \ -# inst_RW_000_INT AS_000_c N_324_i inst_RW_000_DMA inst_CLK_000_NE_D0 RW_000_c N_199_0 \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_197_0 inst_A0_DMA N_196_0 pos_clk_a0_dma_3_n \ -# UDS_000_c LDS_000_c_i SM_AMIGA_6_ UDS_000_c_i inst_CLK_030_H LDS_000_c N_181_i \ -# SM_AMIGA_1_ N_347_i SM_AMIGA_3_ size_c_0__n N_348_i SM_AMIGA_2_ N_178_i \ -# pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 pos_clk_un5_bgack_030_int_d_i_n \ -# N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n \ -# N_148_0 N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ -# ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i N_120_0 \ -# ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n \ -# N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i \ -# N_298_0 N_295_0 N_294_0 N_319_i un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i \ -# SM_AMIGA_i_7_ N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n \ -# G_134 N_3_i G_135 N_49_0 G_136 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i \ -# N_292 N_40_0 N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i \ -# N_298 N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ -# N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 \ -# a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n N_144_i_2 N_144_i_3 \ -# N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 a_c_0__n N_176_i_1 N_207 \ -# N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 \ -# nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 \ -# N_228 BG_030_c un10_ciin_6 N_236 un10_ciin_7 N_277 BG_000DFFreg un10_ciin_8 N_281 \ -# un10_ciin_9 N_282 un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 \ -# CLK_030_c N_347_2 N_319 pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ -# pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ -# un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 CLK_OUT_INTreg N_366_3 N_328 N_366_4 \ -# N_329 un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ -# IPL_030DFF_0_reg N_142_i_2 N_336 N_339_1 N_338 IPL_030DFF_1_reg N_280_1 N_339 N_280_2 \ -# N_341 IPL_030DFF_2_reg N_231_1 N_344 N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 \ -# pos_clk_un23_bgack_030_int_i_0_x2 ipl_c_1__n N_230_3 cpu_est_0_0_x2_0_x2_0_ \ -# N_226_1 pos_clk_CYCLE_DMA_5_0_i_x2 ipl_c_2__n N_226_2 pos_clk_CYCLE_DMA_5_1_i_x2 \ -# N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 N_132_i_1 N_366 N_120_0_1 \ -# N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 N_187 N_140_i_1 N_137 RST_c \ -# N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n N_10 RW_c \ -# N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 \ -# DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n \ -# AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 N_18 N_215_1 DS_000_ENABLE_1_sqmuxa \ -# pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i bg_000_0_un1_n N_233 \ -# pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 pos_clk_un9_bg_030_0_n \ -# uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n N_191 N_33_0 \ -# uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ -# lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n \ -# N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 dsack1_int_0_un0_n \ -# pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 \ -# ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n N_284 N_52_0 \ -# ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 \ -# ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n \ -# N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 cpu_est_0_3__un3_n N_280 N_29_i \ -# cpu_est_0_3__un1_n +#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \ +# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \ +# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \ +# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \ +# A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE \ +# A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ \ +# AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ \ +# A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 662 N_28 N_246_i bgack_030_int_0_un1_n N_17 sm_amiga_nss_i_0_0__n \ +# bgack_030_int_0_un0_n N_19 dsack1_int_0_un3_n N_23 N_220_i dsack1_int_0_un1_n N_24 \ +# N_219_i dsack1_int_0_un0_n N_25 N_218_i cpu_est_0_3__un3_n \ +# un1_amiga_bus_enable_low_i cpu_est_0_3__un1_n un21_fpu_cs_i N_224_i \ +# cpu_est_0_3__un0_n inst_BGACK_030_INTreg BGACK_030_INT_i N_222_i \ +# cpu_est_0_2__un3_n vcc_n_n AMIGA_BUS_ENABLE_DMA_LOW_i N_223_i cpu_est_0_2__un1_n \ +# inst_VMA_INTreg UDS_000_INT_i N_322_i cpu_est_0_2__un0_n gnd_n_n LDS_000_INT_i \ +# N_312_i cpu_est_0_1__un3_n un1_amiga_bus_enable_low N_131_i N_139_0 \ +# cpu_est_0_1__un1_n un6_as_030 N_132_i N_108_i cpu_est_0_1__un0_n un3_size RW_000_i \ +# N_258_i vma_int_0_un3_n un4_size a_i_1__n N_257_i vma_int_0_un1_n un4_uds_000 \ +# clk_000_d_i_11__n vma_int_0_un0_n un4_lds_000 sm_amiga_i_6__n N_245_i \ +# ipl_030_0_0__un3_n un4_as_000 clk_000_d_i_1__n nEXP_SPACE_c_i ipl_030_0_0__un1_n \ +# un10_ciin AS_030_000_SYNC_i un1_as_030_i ipl_030_0_0__un0_n un21_fpu_cs \ +# sm_amiga_i_0__n pos_clk_un3_as_030_d0_0_n ds_000_dma_0_un3_n un22_berr \ +# sm_amiga_i_3__n N_107_0 ds_000_dma_0_un1_n un6_ds_030 sm_amiga_i_i_7__n N_115_i \ +# ds_000_dma_0_un0_n cpu_est_3_ sm_amiga_i_5__n N_63_0 as_000_dma_0_un3_n cpu_est_0_ \ +# rst_dly_i_0__n N_278_0 as_000_dma_0_un1_n cpu_est_1_ rst_dly_i_1__n N_279_0 \ +# as_000_dma_0_un0_n cpu_est_2_ N_364_i_0 N_260_i a_decode_15__n inst_AS_000_INT \ +# cpu_est_i_0__n N_67_0 inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n \ +# pos_clk_rw_000_int_5_0_n a_decode_14__n inst_AS_030_D0 AS_030_i \ +# un1_SM_AMIGA_0_sqmuxa_1_0 inst_AS_030_000_SYNC FPU_SENSE_i un10_ciin_i \ +# a_decode_13__n inst_BGACK_030_INT_D N_157_i N_313_0 inst_AS_000_DMA \ +# a_decode_i_16__n N_4_i a_decode_12__n inst_DS_000_DMA a_decode_i_18__n N_48_0 \ +# CYCLE_DMA_0_ a_decode_i_19__n N_5_i a_decode_11__n CYCLE_DMA_1_ N_113_i N_47_0 \ +# SIZE_DMA_0_ N_114_i N_7_i a_decode_10__n SIZE_DMA_1_ AS_000_INT_i N_46_0 inst_VPA_D \ +# size_dma_i_1__n N_18_i a_decode_9__n inst_UDS_000_INT size_dma_i_0__n N_41_0 \ +# inst_LDS_000_INT RESET_OUT_i N_22_i a_decode_8__n inst_CLK_OUT_PRE_D cpu_est_i_1__n \ +# N_37_0 CLK_000_D_1_ cpu_est_i_2__n N_26_i a_decode_7__n CLK_000_D_10_ VPA_D_i N_33_0 \ +# CLK_000_D_11_ DTACK_D0_i BG_030_c_i a_decode_6__n inst_DTACK_D0 cpu_est_i_3__n \ +# pos_clk_un6_bg_030_i_n inst_RESET_OUT CLK_030_i pos_clk_un9_bg_030_0_n \ +# a_decode_5__n CLK_000_D_0_ clk_000_d_i_0__n N_10_i inst_CLK_OUT_PRE_50 \ +# clk_000_d_i_10__n N_43_0 a_decode_4__n IPL_D0_0_ AS_000_DMA_i VPA_c_i IPL_D0_1_ \ +# AS_000_i N_54_0 a_decode_3__n IPL_D0_2_ CLK_030_H_i un3_as_030_i CLK_000_D_2_ \ +# cycle_dma_i_0__n N_370_i a_decode_2__n CLK_000_D_3_ AS_030_D0_i \ +# pos_clk_un6_bgack_000_0_n CLK_000_D_4_ ahigh_i_30__n N_283_i CLK_000_D_5_ \ +# ahigh_i_31__n pos_clk_size_dma_6_0_0__n CLK_000_D_6_ ahigh_i_28__n N_345_i \ +# CLK_000_D_7_ ahigh_i_29__n pos_clk_size_dma_6_0_1__n CLK_000_D_8_ ahigh_i_26__n \ +# UDS_000_c_i CLK_000_D_9_ ahigh_i_27__n LDS_000_c_i CLK_000_D_12_ ahigh_i_24__n \ +# N_171_i pos_clk_un6_bg_030_n ahigh_i_25__n N_21_i inst_AMIGA_BUS_ENABLE_DMA_HIGH \ +# N_241_i N_38_0 inst_DSACK1_INTreg N_242_i DTACK_c_i pos_clk_ipl_n N_243_i N_55_0 \ +# inst_DS_000_ENABLE N_249_i SM_AMIGA_6_ un6_ds_030_i N_248_i SM_AMIGA_0_ DS_000_DMA_i \ +# pos_clk_un9_clk_000_pe_0_n SM_AMIGA_4_ un4_as_000_i N_250_i inst_RW_000_INT \ +# un6_as_030_i N_251_i inst_RW_000_DMA un4_lds_000_i cpu_est_2_0_1__n RST_DLY_0_ \ +# un4_uds_000_i N_253_i RST_DLY_1_ AS_030_c N_369_i RST_DLY_2_ cpu_est_2_0_2__n \ +# inst_A0_DMA AS_000_c N_254_i inst_CLK_030_H N_316_i SM_AMIGA_1_ RW_000_c N_256_i \ +# SM_AMIGA_5_ N_255_i SM_AMIGA_3_ N_317_i SM_AMIGA_2_ UDS_000_c N_267_i \ +# pos_clk_ds_000_dma_4_n N_266_i N_3 LDS_000_c N_57_0 N_8 N_151_0 size_c_0__n N_321_i \ +# N_158_i size_c_1__n VMA_INT_i N_361_i ahigh_c_24__n N_362_i N_27 N_169_i ahigh_c_25__n \ +# N_186_0 N_195_0 ahigh_c_26__n N_196_0 ahigh_c_27__n N_263_i N_262_i ahigh_c_28__n \ +# N_323_0 N_101_i ahigh_c_29__n N_366_i N_182_i ahigh_c_30__n \ +# pos_clk_un23_bgack_030_int_i_0_0_n N_310_i ahigh_c_31__n N_359_i N_144_0 \ +# CLK_OUT_PRE_D_i N_142_0 N_311_i N_319_i N_93_i N_272_0 N_290_i N_273_0 N_346_i \ +# pos_clk_ds_000_dma_4_0_n N_268_i N_269_i SM_AMIGA_i_7_ sm_amiga_nss_0_3__n N_341_i \ +# N_238_i N_239_i sm_amiga_nss_0_2__n N_263 N_235_i G_116 N_236_i G_117 \ +# sm_amiga_nss_0_4__n G_118 N_234_i pos_clk_un23_bgack_030_int_i_0_n \ +# sm_amiga_nss_0_5__n N_272 N_231_i N_273 N_232_i sm_amiga_nss_0_6__n N_313 N_230_i \ +# a_decode_c_16__n sm_amiga_nss_0_7__n N_226_i N_108 a_decode_c_17__n N_331_i N_319 \ +# N_142 a_decode_c_18__n un1_as_000_i N_144 N_27_i N_322 a_decode_c_19__n N_30_0 N_169 \ +# ipl_c_i_0__n N_195 a_decode_c_20__n N_51_0 N_323 N_3_i N_209 a_decode_c_21__n N_49_0 \ +# N_218 N_8_i N_224 a_decode_c_22__n N_45_0 N_226 sm_amiga_nss_i_0_1_0__n N_331 \ +# a_decode_c_23__n sm_amiga_nss_i_0_2_0__n N_229 sm_amiga_nss_i_0_3_0__n N_230 \ +# a_c_0__n sm_amiga_nss_i_0_4_0__n N_231 sm_amiga_nss_i_0_5_0__n N_232 a_c_1__n \ +# pos_clk_un10_sm_amiga_i_1_n N_233 un10_ciin_1 N_234 nEXP_SPACE_c un10_ciin_2 N_235 \ +# un10_ciin_3 N_236 BERR_c un10_ciin_4 N_238 un10_ciin_5 N_239 BG_030_c un10_ciin_6 N_240 \ +# un10_ciin_7 N_251 BG_000DFFreg un10_ciin_8 N_262 un10_ciin_9 N_341 un10_ciin_10 N_268 \ +# BGACK_000_c un10_ciin_11 N_269 pos_clk_un23_bgack_030_int_i_0_0_1_n N_282 CLK_030_c \ +# pos_clk_un23_bgack_030_int_i_0_0_2_n N_346 N_60_i_1 N_290 N_60_i_2 N_310 N_248_1 \ +# N_311 CLK_OSZI_c N_248_2 N_355 N_249_1 N_356 N_249_2 N_359 CLK_OUT_INTreg N_361_1 N_360 \ +# N_361_2 N_365 N_157_1 N_366 FPU_SENSE_c N_157_2 \ +# pos_clk_un23_bgack_030_int_i_0_o2_2_x2 N_157_3 pos_clk_CYCLE_DMA_5_1_i_0_x2 \ +# IPL_030DFF_0_reg N_157_4 N_248 N_260_1 N_249 IPL_030DFF_1_reg N_260_2 N_369 \ +# un21_fpu_cs_1 N_196 IPL_030DFF_2_reg un22_berr_1_0 N_186 N_275_i_1 N_361 ipl_c_0__n \ +# N_275_i_2 N_362 N_274_i_1 N_151 ipl_c_1__n N_274_i_2 N_321 N_115_1 N_266 ipl_c_2__n \ +# N_115_2 N_267 N_332_1 N_255 N_246_1 N_256 DTACK_c N_246_2 N_253 N_246_3 N_254 N_246_4 \ +# cpu_est_2_2__n N_332_4_1 cpu_est_2_1__n VPA_c N_332_4_2 N_250 N_273_0_1 \ +# pos_clk_un9_clk_000_pe_n N_276_i_1 N_364 RST_c N_277_i_1 N_21 N_314_i_1 N_171 N_356_1 \ +# pos_clk_size_dma_6_1__n RW_c N_282_1 N_345 N_251_1 pos_clk_size_dma_6_0__n fc_c_0__n \ +# pos_clk_un6_bg_030_1_n N_283 N_240_1 pos_clk_un6_bgack_000_n fc_c_1__n N_238_1 N_370 \ +# N_233_1 N_259 N_231_1 N_10 AMIGA_BUS_DATA_DIR_c N_224_1 pos_clk_un9_bg_030_n N_218_1 \ +# N_4 pos_clk_ipl_1_n N_114 rw_000_dma_0_un3_n N_278 rw_000_dma_0_un1_n N_5 N_25_i \ +# rw_000_dma_0_un0_n N_113 N_34_0 lds_000_int_0_un3_n N_279 N_24_i lds_000_int_0_un1_n \ +# N_6 N_35_0 lds_000_int_0_un0_n N_115 N_23_i ipl_030_0_1__un3_n N_63 N_36_0 \ +# ipl_030_0_1__un1_n N_7 N_19_i ipl_030_0_1__un0_n pos_clk_un3_as_030_d0_n N_40_0 \ +# amiga_bus_enable_dma_high_0_un3_n N_67 N_17_i amiga_bus_enable_dma_high_0_un1_n \ +# N_18 N_42_0 amiga_bus_enable_dma_high_0_un0_n pos_clk_rw_000_int_5_n ipl_c_i_1__n \ +# amiga_bus_enable_dma_low_0_un3_n un1_SM_AMIGA_0_sqmuxa_1 N_52_0 \ +# amiga_bus_enable_dma_low_0_un1_n N_22 ipl_c_i_2__n \ +# amiga_bus_enable_dma_low_0_un0_n pos_clk_a0_dma_3_n N_53_0 uds_000_int_0_un3_n \ +# N_363 N_28_i uds_000_int_0_un1_n N_26 N_31_0 uds_000_int_0_un0_n N_157 N_29_i \ +# ipl_030_0_2__un3_n N_260 N_32_0 ipl_030_0_2__un1_n un22_berr_1 a_c_i_0__n \ +# ipl_030_0_2__un0_n N_219 size_c_i_1__n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_139 pos_clk_un10_sm_amiga_i_n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_220 N_332_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_222 N_240_i as_000_int_0_un3_n N_223 \ +# N_315_0 as_000_int_0_un1_n N_368 N_281_0 as_000_int_0_un0_n N_257 N_270_i \ +# ds_000_enable_0_un3_n N_258 N_282_i ds_000_enable_0_un1_n N_312 \ +# AMIGA_BUS_DATA_DIR_c_0 ds_000_enable_0_un0_n N_143 RW_c_i as_030_000_sync_0_un3_n \ +# N_332 N_140_0 as_030_000_sync_0_un1_n N_332_4 N_353_i as_030_000_sync_0_un0_n N_246 \ +# N_143_0 rw_000_int_0_un3_n N_180 sm_amiga_i_1__n rw_000_int_0_un1_n N_320 N_320_i \ +# rw_000_int_0_un0_n N_244 N_357_i a0_dma_0_un3_n N_334 N_356_i a0_dma_0_un1_n N_335 \ +# N_156_0 a0_dma_0_un0_n N_159 sm_amiga_i_4__n bg_000_0_un3_n N_156 N_159_i \ +# bg_000_0_un1_n N_357 sm_amiga_i_2__n bg_000_0_un0_n N_353 N_180_i \ +# size_dma_0_1__un3_n N_140 N_334_i size_dma_0_1__un1_n N_270 N_335_i \ +# size_dma_0_1__un0_n N_281 N_244_i size_dma_0_0__un3_n N_131 N_233_i \ +# size_dma_0_0__un1_n N_132 N_355_i size_dma_0_0__un0_n N_29 N_229_i \ +# bgack_030_int_0_un3_n .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -135,186 +128,175 @@ A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ -AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_166.BLIF N_32_0.BLIF \ -cpu_est_0_3__un0_n.BLIF N_141.BLIF a_c_i_0__n.BLIF cpu_est_0_2__un3_n.BLIF \ -N_226.BLIF size_c_i_1__n.BLIF cpu_est_0_2__un1_n.BLIF N_357.BLIF \ -pos_clk_un10_sm_amiga_i_n.BLIF cpu_est_0_2__un0_n.BLIF N_219.BLIF N_258_0.BLIF \ -sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_217.BLIF N_357_i.BLIF \ -sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_221.BLIF N_254_i.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_220.BLIF cpu_est_2_0_2__n.BLIF \ -vma_int_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF N_223.BLIF N_315_i.BLIF \ -vma_int_0_un1_n.BLIF vcc_n_n.BLIF N_343.BLIF N_291_0.BLIF vma_int_0_un0_n.BLIF \ -inst_VMA_INTreg.BLIF N_192.BLIF AS_030_000_SYNC_i.BLIF cpu_est_0_1__un3_n.BLIF \ -gnd_n_n.BLIF N_164.BLIF N_146_0.BLIF cpu_est_0_1__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_0__n.BLIF N_291.BLIF N_149_i.BLIF \ -cpu_est_0_1__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_315.BLIF N_164_i.BLIF \ -sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF un6_as_030.BLIF cpu_est_2_2__n.BLIF \ -N_166_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF un3_size.BLIF N_254.BLIF \ -N_172_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF un4_size.BLIF N_258.BLIF \ -N_176_i.BLIF rw_000_int_0_un3_n.BLIF un4_uds_000.BLIF N_29.BLIF N_186_0.BLIF \ -rw_000_int_0_un1_n.BLIF un4_lds_000.BLIF N_28.BLIF N_192_0.BLIF \ -rw_000_int_0_un0_n.BLIF un4_as_000.BLIF N_27.BLIF N_228_i.BLIF \ -bgack_030_int_0_un3_n.BLIF un10_ciin.BLIF N_4.BLIF N_227_i.BLIF \ -bgack_030_int_0_un1_n.BLIF un21_fpu_cs.BLIF N_17.BLIF N_343_i.BLIF \ -bgack_030_int_0_un0_n.BLIF un22_berr.BLIF N_21.BLIF as_000_int_0_un3_n.BLIF \ -un6_ds_030.BLIF N_26.BLIF N_223_i.BLIF as_000_int_0_un1_n.BLIF cpu_est_2_.BLIF \ -pos_clk_un9_bg_030_n.BLIF N_225_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_3_.BLIF \ -un1_amiga_bus_enable_low_i.BLIF N_224_i.BLIF ds_000_enable_0_un3_n.BLIF \ -cpu_est_0_.BLIF un21_fpu_cs_i.BLIF N_226_i.BLIF ds_000_enable_0_un1_n.BLIF \ -cpu_est_1_.BLIF N_275_i.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_000_INT.BLIF \ -clk_000_n_sync_i_12__n.BLIF N_220_i.BLIF as_030_000_sync_0_un3_n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF N_221_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF inst_AS_030_D0.BLIF rst_dly_i_1__n.BLIF \ -N_222_i.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ -BERR_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ -inst_BGACK_030_INT_D.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_AS_000_DMA.BLIF \ -nEXP_SPACE_i.BLIF N_215_i.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF inst_DS_000_DMA.BLIF \ -rst_dly_i_0__n.BLIF N_219_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ -CYCLE_DMA_0_.BLIF cpu_est_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ -CYCLE_DMA_1_.BLIF cpu_est_i_0__n.BLIF N_200_i.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF SIZE_DMA_0_.BLIF VPA_D_i.BLIF \ -N_195_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SIZE_DMA_1_.BLIF \ -sm_amiga_i_3__n.BLIF N_190_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ -inst_VPA_D.BLIF sm_amiga_i_0__n.BLIF N_157_i.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF inst_UDS_000_INT.BLIF \ -cpu_est_i_3__n.BLIF N_154_i.BLIF size_dma_0_0__un3_n.BLIF \ -inst_LDS_000_INT.BLIF sm_amiga_i_1__n.BLIF N_340_i.BLIF \ -size_dma_0_0__un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF RESET_OUT_i.BLIF N_141_0.BLIF \ -size_dma_0_0__un0_n.BLIF CLK_000_D_10_.BLIF BGACK_030_INT_i.BLIF \ -un3_as_030_i.BLIF size_dma_0_1__un3_n.BLIF CLK_000_D_11_.BLIF \ -sm_amiga_i_2__n.BLIF N_216_i.BLIF size_dma_0_1__un1_n.BLIF inst_DTACK_D0.BLIF \ -sm_amiga_i_4__n.BLIF N_337_i.BLIF size_dma_0_1__un0_n.BLIF inst_RESET_OUT.BLIF \ -clk_000_p_sync_i_10__n.BLIF ds_000_dma_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF \ -sm_amiga_i_5__n.BLIF un10_ciin_i.BLIF ds_000_dma_0_un1_n.BLIF \ -CLK_000_D_1_.BLIF sm_amiga_i_i_7__n.BLIF N_296_0.BLIF ds_000_dma_0_un0_n.BLIF \ -CLK_000_D_0_.BLIF clk_000_d_i_11__n.BLIF un1_as_000_i.BLIF \ -as_000_dma_0_un3_n.BLIF CLK_000_P_SYNC_10_.BLIF sm_amiga_i_6__n.BLIF \ -N_284_i.BLIF as_000_dma_0_un1_n.BLIF SM_AMIGA_5_.BLIF RW_i.BLIF N_285_i.BLIF \ -as_000_dma_0_un0_n.BLIF IPL_D0_0_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF \ -N_292_0.BLIF rw_000_dma_0_un3_n.BLIF IPL_D0_1_.BLIF LDS_000_INT_i.BLIF \ -N_280_i.BLIF rw_000_dma_0_un1_n.BLIF IPL_D0_2_.BLIF UDS_000_INT_i.BLIF \ -N_277_i.BLIF rw_000_dma_0_un0_n.BLIF CLK_000_D_2_.BLIF AS_030_i.BLIF \ -N_257_0.BLIF a0_dma_0_un3_n.BLIF CLK_000_D_3_.BLIF AS_000_INT_i.BLIF \ -N_235_i.BLIF a0_dma_0_un1_n.BLIF CLK_000_D_4_.BLIF a_decode_i_19__n.BLIF \ -N_236_i.BLIF a0_dma_0_un0_n.BLIF CLK_000_D_5_.BLIF a_decode_i_18__n.BLIF \ -cpu_est_2_0_1__n.BLIF a_decode_15__n.BLIF CLK_000_D_6_.BLIF \ -a_decode_i_16__n.BLIF N_231_i.BLIF CLK_000_D_7_.BLIF AS_000_i.BLIF \ -N_230_i.BLIF a_decode_14__n.BLIF CLK_000_D_8_.BLIF FPU_SENSE_i.BLIF \ -pos_clk_un4_clk_000_pe_0_n.BLIF CLK_000_D_9_.BLIF \ -AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_22_i.BLIF a_decode_13__n.BLIF \ -CLK_000_D_12_.BLIF CLK_030_i.BLIF N_37_0.BLIF pos_clk_un6_bg_030_n.BLIF \ -DTACK_D0_i.BLIF a_decode_12__n.BLIF SM_AMIGA_0_.BLIF clk_000_d_i_10__n.BLIF \ -N_334_i.BLIF inst_DSACK1_INTreg.BLIF RW_000_i.BLIF N_335_i.BLIF \ -a_decode_11__n.BLIF a_i_1__n.BLIF N_194_0.BLIF CLK_030_H_i.BLIF N_191_0.BLIF \ -a_decode_10__n.BLIF pos_clk_ipl_n.BLIF AS_000_DMA_i.BLIF un1_SM_AMIGA_5_i.BLIF \ -CLK_000_N_SYNC_0_.BLIF clk_000_d_i_0__n.BLIF N_346_i.BLIF a_decode_9__n.BLIF \ -SM_AMIGA_4_.BLIF clk_000_d_i_1__n.BLIF N_163_i.BLIF inst_DS_000_ENABLE.BLIF \ -AS_030_D0_i.BLIF N_345_i.BLIF a_decode_8__n.BLIF CLK_000_N_SYNC_12_.BLIF \ -size_dma_i_0__n.BLIF N_344_i.BLIF RST_DLY_0_.BLIF size_dma_i_1__n.BLIF \ -N_153_0.BLIF a_decode_7__n.BLIF RST_DLY_1_.BLIF ahigh_i_30__n.BLIF \ -pos_clk_un3_as_030_d0_i_n.BLIF RST_DLY_2_.BLIF ahigh_i_31__n.BLIF N_293_0.BLIF \ -a_decode_6__n.BLIF CLK_000_P_SYNC_0_.BLIF ahigh_i_28__n.BLIF N_233_i.BLIF \ -CLK_000_P_SYNC_1_.BLIF ahigh_i_29__n.BLIF N_232_i.BLIF a_decode_5__n.BLIF \ -CLK_000_P_SYNC_2_.BLIF ahigh_i_26__n.BLIF N_290_0.BLIF CLK_000_P_SYNC_3_.BLIF \ -ahigh_i_27__n.BLIF VPA_c_i.BLIF a_decode_4__n.BLIF CLK_000_P_SYNC_4_.BLIF \ -ahigh_i_24__n.BLIF N_54_0.BLIF CLK_000_P_SYNC_5_.BLIF ahigh_i_25__n.BLIF \ -N_5_i.BLIF a_decode_3__n.BLIF CLK_000_P_SYNC_6_.BLIF N_212_i.BLIF N_47_0.BLIF \ -CLK_000_P_SYNC_7_.BLIF N_213_i.BLIF N_7_i.BLIF a_decode_2__n.BLIF \ -CLK_000_P_SYNC_8_.BLIF N_214_i.BLIF N_46_0.BLIF CLK_000_P_SYNC_9_.BLIF \ -N_18_i.BLIF CLK_000_N_SYNC_1_.BLIF N_41_0.BLIF CLK_000_N_SYNC_2_.BLIF \ -N_321_i.BLIF N_10_i.BLIF CLK_000_N_SYNC_3_.BLIF N_322_i.BLIF N_43_0.BLIF \ -CLK_000_N_SYNC_4_.BLIF un6_ds_030_i.BLIF DTACK_c_i.BLIF CLK_000_N_SYNC_5_.BLIF \ -DS_000_DMA_i.BLIF N_55_0.BLIF CLK_000_N_SYNC_6_.BLIF un4_as_000_i.BLIF \ -pos_clk_un6_bgack_000_0_n.BLIF CLK_000_N_SYNC_7_.BLIF un6_as_030_i.BLIF \ -N_137_i.BLIF CLK_000_N_SYNC_8_.BLIF un4_lds_000_i.BLIF N_184_0.BLIF \ -CLK_000_N_SYNC_9_.BLIF un4_uds_000_i.BLIF N_349_i.BLIF CLK_000_N_SYNC_10_.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_185_i.BLIF CLK_000_N_SYNC_11_.BLIF \ -AS_030_c.BLIF N_187_0.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_203_i.BLIF \ -inst_RW_000_INT.BLIF AS_000_c.BLIF N_324_i.BLIF inst_RW_000_DMA.BLIF \ -inst_CLK_000_NE_D0.BLIF RW_000_c.BLIF N_199_0.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_197_0.BLIF inst_A0_DMA.BLIF N_196_0.BLIF \ -pos_clk_a0_dma_3_n.BLIF UDS_000_c.BLIF LDS_000_c_i.BLIF SM_AMIGA_6_.BLIF \ -UDS_000_c_i.BLIF inst_CLK_030_H.BLIF LDS_000_c.BLIF N_181_i.BLIF \ -SM_AMIGA_1_.BLIF N_347_i.BLIF SM_AMIGA_3_.BLIF size_c_0__n.BLIF N_348_i.BLIF \ -SM_AMIGA_2_.BLIF N_178_i.BLIF pos_clk_ds_000_dma_4_n.BLIF size_c_1__n.BLIF \ -VMA_INT_i.BLIF N_3.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_8.BLIF \ -ahigh_c_24__n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ -CLK_OUT_PRE_D_i.BLIF ahigh_c_25__n.BLIF N_148_0.BLIF N_341_i.BLIF \ -ahigh_c_26__n.BLIF N_338_i.BLIF N_339_i.BLIF N_19.BLIF ahigh_c_27__n.BLIF \ -N_20.BLIF N_336_i.BLIF N_24.BLIF ahigh_c_28__n.BLIF N_122_0.BLIF N_25.BLIF \ -N_211_i.BLIF ahigh_c_29__n.BLIF N_332_i.BLIF ahigh_c_30__n.BLIF N_331_i.BLIF \ -N_120_0.BLIF ahigh_c_31__n.BLIF N_330_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ -N_329_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_328_i.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF N_325_i.BLIF N_327_i.BLIF \ -AMIGA_BUS_DATA_DIR_c_0.BLIF N_320_i.BLIF N_298_0.BLIF N_295_0.BLIF \ -N_294_0.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ -N_206_i.BLIF N_283_i.BLIF SM_AMIGA_i_7_.BLIF N_122.BLIF N_281_i.BLIF \ -pos_clk_size_dma_6_0__n.BLIF N_282_i.BLIF pos_clk_size_dma_6_1__n.BLIF \ -G_134.BLIF N_3_i.BLIF G_135.BLIF N_49_0.BLIF G_136.BLIF N_8_i.BLIF N_45_0.BLIF \ -pos_clk_un23_bgack_030_int_i_1_n.BLIF N_19_i.BLIF N_292.BLIF N_40_0.BLIF \ -N_294.BLIF a_decode_c_16__n.BLIF N_20_i.BLIF N_295.BLIF N_39_0.BLIF N_296.BLIF \ -a_decode_c_17__n.BLIF N_24_i.BLIF N_298.BLIF N_35_0.BLIF N_120.BLIF \ -a_decode_c_18__n.BLIF N_25_i.BLIF N_148.BLIF N_34_0.BLIF N_149.BLIF \ -a_decode_c_19__n.BLIF N_194_0_1.BLIF N_157.BLIF N_237_i_1.BLIF N_172.BLIF \ -a_decode_c_20__n.BLIF N_237_i_2.BLIF N_176.BLIF N_238_i_1.BLIF N_178.BLIF \ -a_decode_c_21__n.BLIF N_238_i_2.BLIF N_181.BLIF N_144_i_1.BLIF N_184.BLIF \ -a_decode_c_22__n.BLIF N_144_i_2.BLIF N_144_i_3.BLIF N_196.BLIF \ -a_decode_c_23__n.BLIF N_136_i_1.BLIF N_197.BLIF N_136_i_2.BLIF N_206.BLIF \ -a_c_0__n.BLIF N_176_i_1.BLIF N_207.BLIF N_146_0_1.BLIF N_211.BLIF \ -a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_215.BLIF un10_ciin_1.BLIF \ -N_222.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_224.BLIF un10_ciin_3.BLIF \ -N_225.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_227.BLIF un10_ciin_5.BLIF N_228.BLIF \ -BG_030_c.BLIF un10_ciin_6.BLIF N_236.BLIF un10_ciin_7.BLIF N_277.BLIF \ -BG_000DFFreg.BLIF un10_ciin_8.BLIF N_281.BLIF un10_ciin_9.BLIF N_282.BLIF \ -un10_ciin_10.BLIF N_283.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_285.BLIF \ -N_347_1.BLIF N_318.BLIF CLK_030_c.BLIF N_347_2.BLIF N_319.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF N_320.BLIF CLK_000_c.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF N_321.BLIF un21_fpu_cs_1.BLIF \ -N_322.BLIF CLK_OSZI_c.BLIF un22_berr_1_0.BLIF N_323.BLIF N_366_1.BLIF \ -N_325.BLIF N_366_2.BLIF N_327.BLIF CLK_OUT_INTreg.BLIF N_366_3.BLIF N_328.BLIF \ -N_366_4.BLIF N_329.BLIF un1_SM_AMIGA_5_i_1.BLIF N_330.BLIF FPU_SENSE_c.BLIF \ -un1_SM_AMIGA_5_i_2.BLIF N_331.BLIF N_142_i_1.BLIF N_332.BLIF \ -IPL_030DFF_0_reg.BLIF N_142_i_2.BLIF N_336.BLIF N_339_1.BLIF N_338.BLIF \ -IPL_030DFF_1_reg.BLIF N_280_1.BLIF N_339.BLIF N_280_2.BLIF N_341.BLIF \ -IPL_030DFF_2_reg.BLIF N_231_1.BLIF N_344.BLIF N_231_2.BLIF N_347.BLIF \ -ipl_c_0__n.BLIF N_230_1.BLIF N_348.BLIF N_230_2.BLIF \ -pos_clk_un23_bgack_030_int_i_0_x2.BLIF ipl_c_1__n.BLIF N_230_3.BLIF \ -cpu_est_0_0_x2_0_x2_0_.BLIF N_226_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ -ipl_c_2__n.BLIF N_226_2.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_226_3.BLIF \ -N_199.BLIF N_239_i_1.BLIF N_324.BLIF DTACK_c.BLIF N_122_0_1.BLIF \ -un22_berr_1.BLIF N_132_i_1.BLIF N_366.BLIF N_120_0_1.BLIF N_335.BLIF \ -N_106_i_1.BLIF N_208.BLIF VPA_c.BLIF N_103_i_1.BLIF N_203.BLIF N_92_i_1.BLIF \ -N_187.BLIF N_140_i_1.BLIF N_137.BLIF RST_c.BLIF N_138_i_1.BLIF N_349.BLIF \ -N_344_1.BLIF pos_clk_un6_bgack_000_n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ -N_10.BLIF RW_c.BLIF N_327_1.BLIF N_5.BLIF N_319_1.BLIF N_293.BLIF \ -fc_c_0__n.BLIF N_285_1.BLIF N_6.BLIF N_277_1.BLIF un1_SM_AMIGA_5.BLIF \ -fc_c_1__n.BLIF N_236_1.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_228_1.BLIF \ -N_7.BLIF N_225_1.BLIF pos_clk_un3_as_030_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -N_224_1.BLIF N_290.BLIF N_222_1.BLIF N_18.BLIF N_215_1.BLIF \ -DS_000_ENABLE_1_sqmuxa.BLIF pos_clk_ipl_1_n.BLIF N_232.BLIF \ -bg_000_0_un3_n.BLIF N_194.BLIF BG_030_c_i.BLIF bg_000_0_un1_n.BLIF N_233.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF bg_000_0_un0_n.BLIF N_275.BLIF \ -pos_clk_un9_bg_030_0_n.BLIF uds_000_int_0_un3_n.BLIF N_153.BLIF N_26_i.BLIF \ -uds_000_int_0_un1_n.BLIF N_191.BLIF N_33_0.BLIF uds_000_int_0_un0_n.BLIF \ -N_334.BLIF N_21_i.BLIF lds_000_int_0_un3_n.BLIF N_146.BLIF N_38_0.BLIF \ -lds_000_int_0_un1_n.BLIF N_345.BLIF N_17_i.BLIF lds_000_int_0_un0_n.BLIF \ -N_346.BLIF N_42_0.BLIF dsack1_int_0_un3_n.BLIF N_163.BLIF N_4_i.BLIF \ -dsack1_int_0_un1_n.BLIF N_22.BLIF N_48_0.BLIF dsack1_int_0_un0_n.BLIF \ -pos_clk_un4_clk_000_pe_n.BLIF ipl_c_i_0__n.BLIF ipl_030_0_2__un3_n.BLIF \ -cpu_est_2_1__n.BLIF N_51_0.BLIF ipl_030_0_2__un1_n.BLIF N_235.BLIF \ -ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_284.BLIF N_52_0.BLIF \ -ipl_030_0_1__un3_n.BLIF N_190.BLIF ipl_c_i_2__n.BLIF ipl_030_0_1__un1_n.BLIF \ -N_337.BLIF N_53_0.BLIF ipl_030_0_1__un0_n.BLIF N_195.BLIF N_27_i.BLIF \ -ipl_030_0_0__un3_n.BLIF N_340.BLIF N_30_0.BLIF ipl_030_0_0__un1_n.BLIF \ -N_231.BLIF N_28_i.BLIF ipl_030_0_0__un0_n.BLIF N_230.BLIF N_31_0.BLIF \ -cpu_est_0_3__un3_n.BLIF N_280.BLIF N_29_i.BLIF cpu_est_0_3__un1_n.BLIF \ -AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ -AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ -AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ -BERR.PIN.BLIF RW.PIN.BLIF +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_28.BLIF N_246_i.BLIF \ +bgack_030_int_0_un1_n.BLIF N_17.BLIF sm_amiga_nss_i_0_0__n.BLIF \ +bgack_030_int_0_un0_n.BLIF N_19.BLIF dsack1_int_0_un3_n.BLIF N_23.BLIF \ +N_220_i.BLIF dsack1_int_0_un1_n.BLIF N_24.BLIF N_219_i.BLIF \ +dsack1_int_0_un0_n.BLIF N_25.BLIF N_218_i.BLIF cpu_est_0_3__un3_n.BLIF \ +un1_amiga_bus_enable_low_i.BLIF cpu_est_0_3__un1_n.BLIF un21_fpu_cs_i.BLIF \ +N_224_i.BLIF cpu_est_0_3__un0_n.BLIF inst_BGACK_030_INTreg.BLIF \ +BGACK_030_INT_i.BLIF N_222_i.BLIF cpu_est_0_2__un3_n.BLIF vcc_n_n.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_223_i.BLIF cpu_est_0_2__un1_n.BLIF \ +inst_VMA_INTreg.BLIF UDS_000_INT_i.BLIF N_322_i.BLIF cpu_est_0_2__un0_n.BLIF \ +gnd_n_n.BLIF LDS_000_INT_i.BLIF N_312_i.BLIF cpu_est_0_1__un3_n.BLIF \ +un1_amiga_bus_enable_low.BLIF N_131_i.BLIF N_139_0.BLIF \ +cpu_est_0_1__un1_n.BLIF un6_as_030.BLIF N_132_i.BLIF N_108_i.BLIF \ +cpu_est_0_1__un0_n.BLIF un3_size.BLIF RW_000_i.BLIF N_258_i.BLIF \ +vma_int_0_un3_n.BLIF un4_size.BLIF a_i_1__n.BLIF N_257_i.BLIF \ +vma_int_0_un1_n.BLIF un4_uds_000.BLIF clk_000_d_i_11__n.BLIF \ +vma_int_0_un0_n.BLIF un4_lds_000.BLIF sm_amiga_i_6__n.BLIF N_245_i.BLIF \ +ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF clk_000_d_i_1__n.BLIF \ +nEXP_SPACE_c_i.BLIF ipl_030_0_0__un1_n.BLIF un10_ciin.BLIF \ +AS_030_000_SYNC_i.BLIF un1_as_030_i.BLIF ipl_030_0_0__un0_n.BLIF \ +un21_fpu_cs.BLIF sm_amiga_i_0__n.BLIF pos_clk_un3_as_030_d0_0_n.BLIF \ +ds_000_dma_0_un3_n.BLIF un22_berr.BLIF sm_amiga_i_3__n.BLIF N_107_0.BLIF \ +ds_000_dma_0_un1_n.BLIF un6_ds_030.BLIF sm_amiga_i_i_7__n.BLIF N_115_i.BLIF \ +ds_000_dma_0_un0_n.BLIF cpu_est_3_.BLIF sm_amiga_i_5__n.BLIF N_63_0.BLIF \ +as_000_dma_0_un3_n.BLIF cpu_est_0_.BLIF rst_dly_i_0__n.BLIF N_278_0.BLIF \ +as_000_dma_0_un1_n.BLIF cpu_est_1_.BLIF rst_dly_i_1__n.BLIF N_279_0.BLIF \ +as_000_dma_0_un0_n.BLIF cpu_est_2_.BLIF N_364_i_0.BLIF N_260_i.BLIF \ +a_decode_15__n.BLIF inst_AS_000_INT.BLIF cpu_est_i_0__n.BLIF N_67_0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF \ +pos_clk_rw_000_int_5_0_n.BLIF a_decode_14__n.BLIF inst_AS_030_D0.BLIF \ +AS_030_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_AS_030_000_SYNC.BLIF \ +FPU_SENSE_i.BLIF un10_ciin_i.BLIF a_decode_13__n.BLIF \ +inst_BGACK_030_INT_D.BLIF N_157_i.BLIF N_313_0.BLIF inst_AS_000_DMA.BLIF \ +a_decode_i_16__n.BLIF N_4_i.BLIF a_decode_12__n.BLIF inst_DS_000_DMA.BLIF \ +a_decode_i_18__n.BLIF N_48_0.BLIF CYCLE_DMA_0_.BLIF a_decode_i_19__n.BLIF \ +N_5_i.BLIF a_decode_11__n.BLIF CYCLE_DMA_1_.BLIF N_113_i.BLIF N_47_0.BLIF \ +SIZE_DMA_0_.BLIF N_114_i.BLIF N_7_i.BLIF a_decode_10__n.BLIF SIZE_DMA_1_.BLIF \ +AS_000_INT_i.BLIF N_46_0.BLIF inst_VPA_D.BLIF size_dma_i_1__n.BLIF N_18_i.BLIF \ +a_decode_9__n.BLIF inst_UDS_000_INT.BLIF size_dma_i_0__n.BLIF N_41_0.BLIF \ +inst_LDS_000_INT.BLIF RESET_OUT_i.BLIF N_22_i.BLIF a_decode_8__n.BLIF \ +inst_CLK_OUT_PRE_D.BLIF cpu_est_i_1__n.BLIF N_37_0.BLIF CLK_000_D_1_.BLIF \ +cpu_est_i_2__n.BLIF N_26_i.BLIF a_decode_7__n.BLIF CLK_000_D_10_.BLIF \ +VPA_D_i.BLIF N_33_0.BLIF CLK_000_D_11_.BLIF DTACK_D0_i.BLIF BG_030_c_i.BLIF \ +a_decode_6__n.BLIF inst_DTACK_D0.BLIF cpu_est_i_3__n.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF inst_RESET_OUT.BLIF CLK_030_i.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF a_decode_5__n.BLIF CLK_000_D_0_.BLIF \ +clk_000_d_i_0__n.BLIF N_10_i.BLIF inst_CLK_OUT_PRE_50.BLIF \ +clk_000_d_i_10__n.BLIF N_43_0.BLIF a_decode_4__n.BLIF IPL_D0_0_.BLIF \ +AS_000_DMA_i.BLIF VPA_c_i.BLIF IPL_D0_1_.BLIF AS_000_i.BLIF N_54_0.BLIF \ +a_decode_3__n.BLIF IPL_D0_2_.BLIF CLK_030_H_i.BLIF un3_as_030_i.BLIF \ +CLK_000_D_2_.BLIF cycle_dma_i_0__n.BLIF N_370_i.BLIF a_decode_2__n.BLIF \ +CLK_000_D_3_.BLIF AS_030_D0_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ +CLK_000_D_4_.BLIF ahigh_i_30__n.BLIF N_283_i.BLIF CLK_000_D_5_.BLIF \ +ahigh_i_31__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF CLK_000_D_6_.BLIF \ +ahigh_i_28__n.BLIF N_345_i.BLIF CLK_000_D_7_.BLIF ahigh_i_29__n.BLIF \ +pos_clk_size_dma_6_0_1__n.BLIF CLK_000_D_8_.BLIF ahigh_i_26__n.BLIF \ +UDS_000_c_i.BLIF CLK_000_D_9_.BLIF ahigh_i_27__n.BLIF LDS_000_c_i.BLIF \ +CLK_000_D_12_.BLIF ahigh_i_24__n.BLIF N_171_i.BLIF pos_clk_un6_bg_030_n.BLIF \ +ahigh_i_25__n.BLIF N_21_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +N_241_i.BLIF N_38_0.BLIF inst_DSACK1_INTreg.BLIF N_242_i.BLIF DTACK_c_i.BLIF \ +pos_clk_ipl_n.BLIF N_243_i.BLIF N_55_0.BLIF inst_DS_000_ENABLE.BLIF \ +N_249_i.BLIF SM_AMIGA_6_.BLIF un6_ds_030_i.BLIF N_248_i.BLIF SM_AMIGA_0_.BLIF \ +DS_000_DMA_i.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF SM_AMIGA_4_.BLIF \ +un4_as_000_i.BLIF N_250_i.BLIF inst_RW_000_INT.BLIF un6_as_030_i.BLIF \ +N_251_i.BLIF inst_RW_000_DMA.BLIF un4_lds_000_i.BLIF cpu_est_2_0_1__n.BLIF \ +RST_DLY_0_.BLIF un4_uds_000_i.BLIF N_253_i.BLIF RST_DLY_1_.BLIF AS_030_c.BLIF \ +N_369_i.BLIF RST_DLY_2_.BLIF cpu_est_2_0_2__n.BLIF inst_A0_DMA.BLIF \ +AS_000_c.BLIF N_254_i.BLIF inst_CLK_030_H.BLIF N_316_i.BLIF SM_AMIGA_1_.BLIF \ +RW_000_c.BLIF N_256_i.BLIF SM_AMIGA_5_.BLIF N_255_i.BLIF SM_AMIGA_3_.BLIF \ +N_317_i.BLIF SM_AMIGA_2_.BLIF UDS_000_c.BLIF N_267_i.BLIF \ +pos_clk_ds_000_dma_4_n.BLIF N_266_i.BLIF N_3.BLIF LDS_000_c.BLIF N_57_0.BLIF \ +N_8.BLIF N_151_0.BLIF size_c_0__n.BLIF N_321_i.BLIF N_158_i.BLIF \ +size_c_1__n.BLIF VMA_INT_i.BLIF N_361_i.BLIF ahigh_c_24__n.BLIF N_362_i.BLIF \ +N_27.BLIF N_169_i.BLIF ahigh_c_25__n.BLIF N_186_0.BLIF N_195_0.BLIF \ +ahigh_c_26__n.BLIF N_196_0.BLIF ahigh_c_27__n.BLIF N_263_i.BLIF N_262_i.BLIF \ +ahigh_c_28__n.BLIF N_323_0.BLIF N_101_i.BLIF ahigh_c_29__n.BLIF N_366_i.BLIF \ +N_182_i.BLIF ahigh_c_30__n.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF \ +N_310_i.BLIF ahigh_c_31__n.BLIF N_359_i.BLIF N_144_0.BLIF CLK_OUT_PRE_D_i.BLIF \ +N_142_0.BLIF N_311_i.BLIF N_319_i.BLIF N_93_i.BLIF N_272_0.BLIF N_290_i.BLIF \ +N_273_0.BLIF N_346_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_268_i.BLIF \ +N_269_i.BLIF SM_AMIGA_i_7_.BLIF sm_amiga_nss_0_3__n.BLIF N_341_i.BLIF \ +N_238_i.BLIF N_239_i.BLIF sm_amiga_nss_0_2__n.BLIF N_263.BLIF N_235_i.BLIF \ +G_116.BLIF N_236_i.BLIF G_117.BLIF sm_amiga_nss_0_4__n.BLIF G_118.BLIF \ +N_234_i.BLIF pos_clk_un23_bgack_030_int_i_0_n.BLIF sm_amiga_nss_0_5__n.BLIF \ +N_272.BLIF N_231_i.BLIF N_273.BLIF N_232_i.BLIF sm_amiga_nss_0_6__n.BLIF \ +N_313.BLIF N_230_i.BLIF a_decode_c_16__n.BLIF sm_amiga_nss_0_7__n.BLIF \ +N_226_i.BLIF N_108.BLIF a_decode_c_17__n.BLIF N_331_i.BLIF N_319.BLIF \ +N_142.BLIF a_decode_c_18__n.BLIF un1_as_000_i.BLIF N_144.BLIF N_27_i.BLIF \ +N_322.BLIF a_decode_c_19__n.BLIF N_30_0.BLIF N_169.BLIF ipl_c_i_0__n.BLIF \ +N_195.BLIF a_decode_c_20__n.BLIF N_51_0.BLIF N_323.BLIF N_3_i.BLIF N_209.BLIF \ +a_decode_c_21__n.BLIF N_49_0.BLIF N_218.BLIF N_8_i.BLIF N_224.BLIF \ +a_decode_c_22__n.BLIF N_45_0.BLIF N_226.BLIF sm_amiga_nss_i_0_1_0__n.BLIF \ +N_331.BLIF a_decode_c_23__n.BLIF sm_amiga_nss_i_0_2_0__n.BLIF N_229.BLIF \ +sm_amiga_nss_i_0_3_0__n.BLIF N_230.BLIF a_c_0__n.BLIF \ +sm_amiga_nss_i_0_4_0__n.BLIF N_231.BLIF sm_amiga_nss_i_0_5_0__n.BLIF \ +N_232.BLIF a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_233.BLIF \ +un10_ciin_1.BLIF N_234.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_235.BLIF \ +un10_ciin_3.BLIF N_236.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_238.BLIF \ +un10_ciin_5.BLIF N_239.BLIF BG_030_c.BLIF un10_ciin_6.BLIF N_240.BLIF \ +un10_ciin_7.BLIF N_251.BLIF BG_000DFFreg.BLIF un10_ciin_8.BLIF N_262.BLIF \ +un10_ciin_9.BLIF N_341.BLIF un10_ciin_10.BLIF N_268.BLIF BGACK_000_c.BLIF \ +un10_ciin_11.BLIF N_269.BLIF pos_clk_un23_bgack_030_int_i_0_0_1_n.BLIF \ +N_282.BLIF CLK_030_c.BLIF pos_clk_un23_bgack_030_int_i_0_0_2_n.BLIF N_346.BLIF \ +N_60_i_1.BLIF N_290.BLIF N_60_i_2.BLIF N_310.BLIF N_248_1.BLIF N_311.BLIF \ +CLK_OSZI_c.BLIF N_248_2.BLIF N_355.BLIF N_249_1.BLIF N_356.BLIF N_249_2.BLIF \ +N_359.BLIF CLK_OUT_INTreg.BLIF N_361_1.BLIF N_360.BLIF N_361_2.BLIF N_365.BLIF \ +N_157_1.BLIF N_366.BLIF FPU_SENSE_c.BLIF N_157_2.BLIF \ +pos_clk_un23_bgack_030_int_i_0_o2_2_x2.BLIF N_157_3.BLIF \ +pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF IPL_030DFF_0_reg.BLIF N_157_4.BLIF \ +N_248.BLIF N_260_1.BLIF N_249.BLIF IPL_030DFF_1_reg.BLIF N_260_2.BLIF \ +N_369.BLIF un21_fpu_cs_1.BLIF N_196.BLIF IPL_030DFF_2_reg.BLIF \ +un22_berr_1_0.BLIF N_186.BLIF N_275_i_1.BLIF N_361.BLIF ipl_c_0__n.BLIF \ +N_275_i_2.BLIF N_362.BLIF N_274_i_1.BLIF N_151.BLIF ipl_c_1__n.BLIF \ +N_274_i_2.BLIF N_321.BLIF N_115_1.BLIF N_266.BLIF ipl_c_2__n.BLIF N_115_2.BLIF \ +N_267.BLIF N_332_1.BLIF N_255.BLIF N_246_1.BLIF N_256.BLIF DTACK_c.BLIF \ +N_246_2.BLIF N_253.BLIF N_246_3.BLIF N_254.BLIF N_246_4.BLIF \ +cpu_est_2_2__n.BLIF N_332_4_1.BLIF cpu_est_2_1__n.BLIF VPA_c.BLIF \ +N_332_4_2.BLIF N_250.BLIF N_273_0_1.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ +N_276_i_1.BLIF N_364.BLIF RST_c.BLIF N_277_i_1.BLIF N_21.BLIF N_314_i_1.BLIF \ +N_171.BLIF N_356_1.BLIF pos_clk_size_dma_6_1__n.BLIF RW_c.BLIF N_282_1.BLIF \ +N_345.BLIF N_251_1.BLIF pos_clk_size_dma_6_0__n.BLIF fc_c_0__n.BLIF \ +pos_clk_un6_bg_030_1_n.BLIF N_283.BLIF N_240_1.BLIF \ +pos_clk_un6_bgack_000_n.BLIF fc_c_1__n.BLIF N_238_1.BLIF N_370.BLIF \ +N_233_1.BLIF N_259.BLIF N_231_1.BLIF N_10.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +N_224_1.BLIF pos_clk_un9_bg_030_n.BLIF N_218_1.BLIF N_4.BLIF \ +pos_clk_ipl_1_n.BLIF N_114.BLIF rw_000_dma_0_un3_n.BLIF N_278.BLIF \ +rw_000_dma_0_un1_n.BLIF N_5.BLIF N_25_i.BLIF rw_000_dma_0_un0_n.BLIF \ +N_113.BLIF N_34_0.BLIF lds_000_int_0_un3_n.BLIF N_279.BLIF N_24_i.BLIF \ +lds_000_int_0_un1_n.BLIF N_6.BLIF N_35_0.BLIF lds_000_int_0_un0_n.BLIF \ +N_115.BLIF N_23_i.BLIF ipl_030_0_1__un3_n.BLIF N_63.BLIF N_36_0.BLIF \ +ipl_030_0_1__un1_n.BLIF N_7.BLIF N_19_i.BLIF ipl_030_0_1__un0_n.BLIF \ +pos_clk_un3_as_030_d0_n.BLIF N_40_0.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF N_67.BLIF N_17_i.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF N_18.BLIF N_42_0.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF pos_clk_rw_000_int_5_n.BLIF \ +ipl_c_i_1__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1.BLIF N_52_0.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ +N_22.BLIF ipl_c_i_2__n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF \ +pos_clk_a0_dma_3_n.BLIF N_53_0.BLIF uds_000_int_0_un3_n.BLIF N_363.BLIF \ +N_28_i.BLIF uds_000_int_0_un1_n.BLIF N_26.BLIF N_31_0.BLIF \ +uds_000_int_0_un0_n.BLIF N_157.BLIF N_29_i.BLIF ipl_030_0_2__un3_n.BLIF \ +N_260.BLIF N_32_0.BLIF ipl_030_0_2__un1_n.BLIF un22_berr_1.BLIF \ +a_c_i_0__n.BLIF ipl_030_0_2__un0_n.BLIF N_219.BLIF size_c_i_1__n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_139.BLIF \ +pos_clk_un10_sm_amiga_i_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_220.BLIF N_332_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_222.BLIF N_240_i.BLIF \ +as_000_int_0_un3_n.BLIF N_223.BLIF N_315_0.BLIF as_000_int_0_un1_n.BLIF \ +N_368.BLIF N_281_0.BLIF as_000_int_0_un0_n.BLIF N_257.BLIF N_270_i.BLIF \ +ds_000_enable_0_un3_n.BLIF N_258.BLIF N_282_i.BLIF ds_000_enable_0_un1_n.BLIF \ +N_312.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF ds_000_enable_0_un0_n.BLIF N_143.BLIF \ +RW_c_i.BLIF as_030_000_sync_0_un3_n.BLIF N_332.BLIF N_140_0.BLIF \ +as_030_000_sync_0_un1_n.BLIF N_332_4.BLIF N_353_i.BLIF \ +as_030_000_sync_0_un0_n.BLIF N_246.BLIF N_143_0.BLIF rw_000_int_0_un3_n.BLIF \ +N_180.BLIF sm_amiga_i_1__n.BLIF rw_000_int_0_un1_n.BLIF N_320.BLIF \ +N_320_i.BLIF rw_000_int_0_un0_n.BLIF N_244.BLIF N_357_i.BLIF \ +a0_dma_0_un3_n.BLIF N_334.BLIF N_356_i.BLIF a0_dma_0_un1_n.BLIF N_335.BLIF \ +N_156_0.BLIF a0_dma_0_un0_n.BLIF N_159.BLIF sm_amiga_i_4__n.BLIF \ +bg_000_0_un3_n.BLIF N_156.BLIF N_159_i.BLIF bg_000_0_un1_n.BLIF N_357.BLIF \ +sm_amiga_i_2__n.BLIF bg_000_0_un0_n.BLIF N_353.BLIF N_180_i.BLIF \ +size_dma_0_1__un3_n.BLIF N_140.BLIF N_334_i.BLIF size_dma_0_1__un1_n.BLIF \ +N_270.BLIF N_335_i.BLIF size_dma_0_1__un0_n.BLIF N_281.BLIF N_244_i.BLIF \ +size_dma_0_0__un3_n.BLIF N_131.BLIF N_233_i.BLIF size_dma_0_0__un1_n.BLIF \ +N_132.BLIF N_355_i.BLIF size_dma_0_0__un0_n.BLIF N_29.BLIF N_229_i.BLIF \ +bgack_030_int_0_un3_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ +AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ +A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ @@ -324,171 +306,150 @@ SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \ -CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \ -CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ -CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \ -CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ -CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ -SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ -CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ -CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ -CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ -CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \ -CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \ -CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ -CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ -CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \ -CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ -CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \ -CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ +IPL_D0_2_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \ CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ -CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ -CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ -RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ -inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D \ +CLK_000_D_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C \ +SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D \ +cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \ +RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ +CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ +CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C RST_DLY_0_.D RST_DLY_0_.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ -inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 \ -BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ \ -AHIGH_24_ A_0_ N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n \ -cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 \ -pos_clk_un10_sm_amiga_i_n cpu_est_0_2__un0_n N_219 N_258_0 \ -sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n \ -N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 cpu_est_2_0_2__n \ -vma_int_0_un3_n N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 N_291_0 \ -vma_int_0_un0_n N_192 AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 \ -N_146_0 cpu_est_0_1__un1_n un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i \ -cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 N_164_i \ -sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n N_166_i \ -sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ -sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ -un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ -rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ -N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ -un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ -pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n un1_amiga_bus_enable_low_i \ -N_224_i ds_000_enable_0_un3_n un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n \ -N_275_i ds_000_enable_0_un0_n clk_000_n_sync_i_12__n N_220_i \ -as_030_000_sync_0_un3_n rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ -rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n BERR_i \ -un1_amiga_bus_enable_dma_high_0_m2_0__un3_n cpu_est_i_2__n N_217_i \ -un1_amiga_bus_enable_dma_high_0_m2_0__un1_n nEXP_SPACE_i N_215_i \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n rst_dly_i_0__n N_219_i \ -amiga_bus_enable_dma_low_0_un3_n cpu_est_i_1__n \ -amiga_bus_enable_dma_low_0_un1_n cpu_est_i_0__n N_200_i \ -amiga_bus_enable_dma_low_0_un0_n VPA_D_i N_195_0 \ -amiga_bus_enable_dma_high_0_un3_n sm_amiga_i_3__n N_190_0 \ -amiga_bus_enable_dma_high_0_un1_n sm_amiga_i_0__n N_157_i \ -amiga_bus_enable_dma_high_0_un0_n cpu_est_i_3__n N_154_i size_dma_0_0__un3_n \ -sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n RESET_OUT_i N_141_0 \ -size_dma_0_0__un0_n BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n \ -sm_amiga_i_2__n N_216_i size_dma_0_1__un1_n sm_amiga_i_4__n N_337_i \ -size_dma_0_1__un0_n clk_000_p_sync_i_10__n ds_000_dma_0_un3_n sm_amiga_i_5__n \ -un10_ciin_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n \ -clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n sm_amiga_i_6__n N_284_i \ -as_000_dma_0_un1_n RW_i N_285_i as_000_dma_0_un0_n DS_000_ENABLE_1_sqmuxa_i \ -N_292_0 rw_000_dma_0_un3_n LDS_000_INT_i N_280_i rw_000_dma_0_un1_n \ -UDS_000_INT_i N_277_i rw_000_dma_0_un0_n AS_030_i N_257_0 a0_dma_0_un3_n \ -AS_000_INT_i N_235_i a0_dma_0_un1_n a_decode_i_19__n N_236_i a0_dma_0_un0_n \ -a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n a_decode_i_16__n N_231_i \ -AS_000_i N_230_i a_decode_14__n FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ -AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_030_i N_37_0 \ -pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n clk_000_d_i_10__n N_334_i \ -RW_000_i N_335_i a_decode_11__n a_i_1__n N_194_0 CLK_030_H_i N_191_0 \ -a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i clk_000_d_i_0__n \ -N_346_i a_decode_9__n clk_000_d_i_1__n N_163_i AS_030_D0_i N_345_i \ -a_decode_8__n size_dma_i_0__n N_344_i size_dma_i_1__n N_153_0 a_decode_7__n \ -ahigh_i_30__n pos_clk_un3_as_030_d0_i_n ahigh_i_31__n N_293_0 a_decode_6__n \ -ahigh_i_28__n N_233_i ahigh_i_29__n N_232_i a_decode_5__n ahigh_i_26__n \ -N_290_0 ahigh_i_27__n VPA_c_i a_decode_4__n ahigh_i_24__n N_54_0 ahigh_i_25__n \ -N_5_i a_decode_3__n N_212_i N_47_0 N_213_i N_7_i a_decode_2__n N_214_i N_46_0 \ -N_18_i N_41_0 N_321_i N_10_i N_322_i N_43_0 un6_ds_030_i DTACK_c_i \ -DS_000_DMA_i N_55_0 un4_as_000_i pos_clk_un6_bgack_000_0_n un6_as_030_i \ -N_137_i un4_lds_000_i N_184_0 un4_uds_000_i N_349_i AMIGA_BUS_ENABLE_DMA_LOW_i \ -N_185_i AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i AS_000_c \ -N_324_i RW_000_c N_199_0 N_197_0 N_196_0 pos_clk_a0_dma_3_n UDS_000_c \ -LDS_000_c_i UDS_000_c_i LDS_000_c N_181_i N_347_i size_c_0__n N_348_i N_178_i \ -pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 \ -pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n \ -pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 \ -N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ -ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i \ -N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i \ -pos_clk_size_dma_6_0_1__n N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i \ -AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i \ -un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i N_122 N_281_i \ -pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n N_3_i N_49_0 N_8_i \ -N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i N_292 N_40_0 N_294 \ -a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 \ -N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ -N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 \ -N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n \ -N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 \ -a_c_0__n N_176_i_1 N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n \ -N_215 un10_ciin_1 N_222 nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 \ -BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 BG_030_c un10_ciin_6 N_236 \ -un10_ciin_7 N_277 un10_ciin_8 N_281 un10_ciin_9 N_282 un10_ciin_10 N_283 \ -BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 CLK_030_c N_347_2 N_319 \ -pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ -pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ -un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 N_366_3 N_328 N_366_4 N_329 \ -un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ -N_142_i_2 N_336 N_339_1 N_338 N_280_1 N_339 N_280_2 N_341 N_231_1 N_344 \ -N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 ipl_c_1__n N_230_3 N_226_1 \ -ipl_c_2__n N_226_2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 \ -N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 \ -N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n \ -pos_clk_un6_bg_030_1_n N_10 RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 \ -N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 \ -N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 \ -N_18 N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 \ -BG_030_c_i bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 \ -pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n \ -N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ -lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 \ -dsack1_int_0_un3_n N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 \ -dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n \ -cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n \ -N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 \ -N_53_0 ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 \ -ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 \ -cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n AS_030.OE AS_000.OE \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ +RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_28 N_246_i bgack_030_int_0_un1_n N_17 \ +sm_amiga_nss_i_0_0__n bgack_030_int_0_un0_n N_19 dsack1_int_0_un3_n N_23 \ +N_220_i dsack1_int_0_un1_n N_24 N_219_i dsack1_int_0_un0_n N_25 N_218_i \ +cpu_est_0_3__un3_n un1_amiga_bus_enable_low_i cpu_est_0_3__un1_n un21_fpu_cs_i \ +N_224_i cpu_est_0_3__un0_n BGACK_030_INT_i N_222_i cpu_est_0_2__un3_n vcc_n_n \ +AMIGA_BUS_ENABLE_DMA_LOW_i N_223_i cpu_est_0_2__un1_n UDS_000_INT_i N_322_i \ +cpu_est_0_2__un0_n gnd_n_n LDS_000_INT_i N_312_i cpu_est_0_1__un3_n \ +un1_amiga_bus_enable_low N_131_i N_139_0 cpu_est_0_1__un1_n un6_as_030 N_132_i \ +N_108_i cpu_est_0_1__un0_n un3_size RW_000_i N_258_i vma_int_0_un3_n un4_size \ +a_i_1__n N_257_i vma_int_0_un1_n un4_uds_000 clk_000_d_i_11__n vma_int_0_un0_n \ +un4_lds_000 sm_amiga_i_6__n N_245_i ipl_030_0_0__un3_n un4_as_000 \ +clk_000_d_i_1__n nEXP_SPACE_c_i ipl_030_0_0__un1_n un10_ciin AS_030_000_SYNC_i \ +un1_as_030_i ipl_030_0_0__un0_n un21_fpu_cs sm_amiga_i_0__n \ +pos_clk_un3_as_030_d0_0_n ds_000_dma_0_un3_n un22_berr sm_amiga_i_3__n N_107_0 \ +ds_000_dma_0_un1_n un6_ds_030 sm_amiga_i_i_7__n N_115_i ds_000_dma_0_un0_n \ +sm_amiga_i_5__n N_63_0 as_000_dma_0_un3_n rst_dly_i_0__n N_278_0 \ +as_000_dma_0_un1_n rst_dly_i_1__n N_279_0 as_000_dma_0_un0_n N_364_i_0 N_260_i \ +a_decode_15__n cpu_est_i_0__n N_67_0 rst_dly_i_2__n pos_clk_rw_000_int_5_0_n \ +a_decode_14__n AS_030_i un1_SM_AMIGA_0_sqmuxa_1_0 FPU_SENSE_i un10_ciin_i \ +a_decode_13__n N_157_i N_313_0 a_decode_i_16__n N_4_i a_decode_12__n \ +a_decode_i_18__n N_48_0 a_decode_i_19__n N_5_i a_decode_11__n N_113_i N_47_0 \ +N_114_i N_7_i a_decode_10__n AS_000_INT_i N_46_0 size_dma_i_1__n N_18_i \ +a_decode_9__n size_dma_i_0__n N_41_0 RESET_OUT_i N_22_i a_decode_8__n \ +cpu_est_i_1__n N_37_0 cpu_est_i_2__n N_26_i a_decode_7__n VPA_D_i N_33_0 \ +DTACK_D0_i BG_030_c_i a_decode_6__n cpu_est_i_3__n pos_clk_un6_bg_030_i_n \ +CLK_030_i pos_clk_un9_bg_030_0_n a_decode_5__n clk_000_d_i_0__n N_10_i \ +clk_000_d_i_10__n N_43_0 a_decode_4__n AS_000_DMA_i VPA_c_i AS_000_i N_54_0 \ +a_decode_3__n CLK_030_H_i un3_as_030_i cycle_dma_i_0__n N_370_i a_decode_2__n \ +AS_030_D0_i pos_clk_un6_bgack_000_0_n ahigh_i_30__n N_283_i ahigh_i_31__n \ +pos_clk_size_dma_6_0_0__n ahigh_i_28__n N_345_i ahigh_i_29__n \ +pos_clk_size_dma_6_0_1__n ahigh_i_26__n UDS_000_c_i ahigh_i_27__n LDS_000_c_i \ +ahigh_i_24__n N_171_i pos_clk_un6_bg_030_n ahigh_i_25__n N_21_i N_241_i N_38_0 \ +N_242_i DTACK_c_i pos_clk_ipl_n N_243_i N_55_0 N_249_i un6_ds_030_i N_248_i \ +DS_000_DMA_i pos_clk_un9_clk_000_pe_0_n un4_as_000_i N_250_i un6_as_030_i \ +N_251_i un4_lds_000_i cpu_est_2_0_1__n un4_uds_000_i N_253_i AS_030_c N_369_i \ +cpu_est_2_0_2__n AS_000_c N_254_i N_316_i RW_000_c N_256_i N_255_i N_317_i \ +UDS_000_c N_267_i pos_clk_ds_000_dma_4_n N_266_i N_3 LDS_000_c N_57_0 N_8 \ +N_151_0 size_c_0__n N_321_i N_158_i size_c_1__n VMA_INT_i N_361_i \ +ahigh_c_24__n N_362_i N_27 N_169_i ahigh_c_25__n N_186_0 N_195_0 ahigh_c_26__n \ +N_196_0 ahigh_c_27__n N_263_i N_262_i ahigh_c_28__n N_323_0 N_101_i \ +ahigh_c_29__n N_366_i N_182_i ahigh_c_30__n pos_clk_un23_bgack_030_int_i_0_0_n \ +N_310_i ahigh_c_31__n N_359_i N_144_0 CLK_OUT_PRE_D_i N_142_0 N_311_i N_319_i \ +N_93_i N_272_0 N_290_i N_273_0 N_346_i pos_clk_ds_000_dma_4_0_n N_268_i \ +N_269_i sm_amiga_nss_0_3__n N_341_i N_238_i N_239_i sm_amiga_nss_0_2__n N_263 \ +N_235_i N_236_i sm_amiga_nss_0_4__n N_234_i pos_clk_un23_bgack_030_int_i_0_n \ +sm_amiga_nss_0_5__n N_272 N_231_i N_273 N_232_i sm_amiga_nss_0_6__n N_313 \ +N_230_i a_decode_c_16__n sm_amiga_nss_0_7__n N_226_i N_108 a_decode_c_17__n \ +N_331_i N_319 N_142 a_decode_c_18__n un1_as_000_i N_144 N_27_i N_322 \ +a_decode_c_19__n N_30_0 N_169 ipl_c_i_0__n N_195 a_decode_c_20__n N_51_0 N_323 \ +N_3_i N_209 a_decode_c_21__n N_49_0 N_218 N_8_i N_224 a_decode_c_22__n N_45_0 \ +N_226 sm_amiga_nss_i_0_1_0__n N_331 a_decode_c_23__n sm_amiga_nss_i_0_2_0__n \ +N_229 sm_amiga_nss_i_0_3_0__n N_230 a_c_0__n sm_amiga_nss_i_0_4_0__n N_231 \ +sm_amiga_nss_i_0_5_0__n N_232 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_233 \ +un10_ciin_1 N_234 nEXP_SPACE_c un10_ciin_2 N_235 un10_ciin_3 N_236 BERR_c \ +un10_ciin_4 N_238 un10_ciin_5 N_239 BG_030_c un10_ciin_6 N_240 un10_ciin_7 \ +N_251 un10_ciin_8 N_262 un10_ciin_9 N_341 un10_ciin_10 N_268 BGACK_000_c \ +un10_ciin_11 N_269 pos_clk_un23_bgack_030_int_i_0_0_1_n N_282 CLK_030_c \ +pos_clk_un23_bgack_030_int_i_0_0_2_n N_346 N_60_i_1 N_290 N_60_i_2 N_310 \ +N_248_1 N_311 CLK_OSZI_c N_248_2 N_355 N_249_1 N_356 N_249_2 N_359 N_361_1 \ +N_360 N_361_2 N_365 N_157_1 N_366 FPU_SENSE_c N_157_2 N_157_3 N_157_4 N_248 \ +N_260_1 N_249 N_260_2 N_369 un21_fpu_cs_1 N_196 un22_berr_1_0 N_186 N_275_i_1 \ +N_361 ipl_c_0__n N_275_i_2 N_362 N_274_i_1 N_151 ipl_c_1__n N_274_i_2 N_321 \ +N_115_1 N_266 ipl_c_2__n N_115_2 N_267 N_332_1 N_255 N_246_1 N_256 DTACK_c \ +N_246_2 N_253 N_246_3 N_254 N_246_4 cpu_est_2_2__n N_332_4_1 cpu_est_2_1__n \ +VPA_c N_332_4_2 N_250 N_273_0_1 pos_clk_un9_clk_000_pe_n N_276_i_1 N_364 RST_c \ +N_277_i_1 N_21 N_314_i_1 N_171 N_356_1 pos_clk_size_dma_6_1__n RW_c N_282_1 \ +N_345 N_251_1 pos_clk_size_dma_6_0__n fc_c_0__n pos_clk_un6_bg_030_1_n N_283 \ +N_240_1 pos_clk_un6_bgack_000_n fc_c_1__n N_238_1 N_370 N_233_1 N_259 N_231_1 \ +N_10 AMIGA_BUS_DATA_DIR_c N_224_1 pos_clk_un9_bg_030_n N_218_1 N_4 \ +pos_clk_ipl_1_n N_114 rw_000_dma_0_un3_n N_278 rw_000_dma_0_un1_n N_5 N_25_i \ +rw_000_dma_0_un0_n N_113 N_34_0 lds_000_int_0_un3_n N_279 N_24_i \ +lds_000_int_0_un1_n N_6 N_35_0 lds_000_int_0_un0_n N_115 N_23_i \ +ipl_030_0_1__un3_n N_63 N_36_0 ipl_030_0_1__un1_n N_7 N_19_i \ +ipl_030_0_1__un0_n pos_clk_un3_as_030_d0_n N_40_0 \ +amiga_bus_enable_dma_high_0_un3_n N_67 N_17_i \ +amiga_bus_enable_dma_high_0_un1_n N_18 N_42_0 \ +amiga_bus_enable_dma_high_0_un0_n pos_clk_rw_000_int_5_n ipl_c_i_1__n \ +amiga_bus_enable_dma_low_0_un3_n un1_SM_AMIGA_0_sqmuxa_1 N_52_0 \ +amiga_bus_enable_dma_low_0_un1_n N_22 ipl_c_i_2__n \ +amiga_bus_enable_dma_low_0_un0_n pos_clk_a0_dma_3_n N_53_0 uds_000_int_0_un3_n \ +N_363 N_28_i uds_000_int_0_un1_n N_26 N_31_0 uds_000_int_0_un0_n N_157 N_29_i \ +ipl_030_0_2__un3_n N_260 N_32_0 ipl_030_0_2__un1_n un22_berr_1 a_c_i_0__n \ +ipl_030_0_2__un0_n N_219 size_c_i_1__n \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_139 pos_clk_un10_sm_amiga_i_n \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_220 N_332_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_222 N_240_i as_000_int_0_un3_n \ +N_223 N_315_0 as_000_int_0_un1_n N_368 N_281_0 as_000_int_0_un0_n N_257 \ +N_270_i ds_000_enable_0_un3_n N_258 N_282_i ds_000_enable_0_un1_n N_312 \ +AMIGA_BUS_DATA_DIR_c_0 ds_000_enable_0_un0_n N_143 RW_c_i \ +as_030_000_sync_0_un3_n N_332 N_140_0 as_030_000_sync_0_un1_n N_332_4 N_353_i \ +as_030_000_sync_0_un0_n N_246 N_143_0 rw_000_int_0_un3_n N_180 sm_amiga_i_1__n \ +rw_000_int_0_un1_n N_320 N_320_i rw_000_int_0_un0_n N_244 N_357_i \ +a0_dma_0_un3_n N_334 N_356_i a0_dma_0_un1_n N_335 N_156_0 a0_dma_0_un0_n N_159 \ +sm_amiga_i_4__n bg_000_0_un3_n N_156 N_159_i bg_000_0_un1_n N_357 \ +sm_amiga_i_2__n bg_000_0_un0_n N_353 N_180_i size_dma_0_1__un3_n N_140 N_334_i \ +size_dma_0_1__un1_n N_270 N_335_i size_dma_0_1__un0_n N_281 N_244_i \ +size_dma_0_0__un3_n N_131 N_233_i size_dma_0_0__un1_n N_132 N_355_i \ +size_dma_0_0__un0_n N_29 N_229_i bgack_030_int_0_un3_n AS_030.OE AS_000.OE \ RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ -AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 \ -G_135 G_136 pos_clk_un23_bgack_030_int_i_0_x2 cpu_est_0_0_x2_0_x2_0_ \ -pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 -.names N_144_i_3.BLIF N_226_i.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_142_i_1.BLIF N_142_i_2.BLIF SM_AMIGA_6_.D -11 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 -.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_136_i_1.BLIF N_136_i_2.BLIF SM_AMIGA_3_.D -11 1 -.names N_257_0.BLIF SM_AMIGA_2_.D +AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_116 \ +G_117 G_118 pos_clk_un23_bgack_030_int_i_0_o2_2_x2 \ +pos_clk_CYCLE_DMA_5_1_i_0_x2 +.names sm_amiga_nss_i_0_0__n.BLIF SM_AMIGA_i_7_.D +0 1 +.names N_315_0.BLIF SM_AMIGA_6_.D +0 1 +.names sm_amiga_nss_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names sm_amiga_nss_0_3__n.BLIF SM_AMIGA_4_.D +0 1 +.names sm_amiga_nss_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names sm_amiga_nss_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names sm_amiga_nss_0_6__n.BLIF SM_AMIGA_1_.D +0 1 +.names sm_amiga_nss_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names N_132_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names N_185_i.BLIF N_324_i.BLIF SM_AMIGA_0_.D -11 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 @@ -507,9 +468,9 @@ pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_53_0.BLIF IPL_D0_2_.D 0 1 -.names N_92_i_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF CYCLE_DMA_0_.D +.names N_60_i_1.BLIF N_60_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_103_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D +.names N_277_i_1.BLIF N_101_i.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -517,39 +478,17 @@ pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 +.names N_257_i.BLIF N_258_i.BLIF cpu_est_0_.D +11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF CLK_000_N_SYNC_0_.D +.names N_275_i_1.BLIF N_275_i_2.BLIF RST_DLY_1_.D 11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D +.names N_274_i_1.BLIF N_274_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_239_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names N_314_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_237_i_1.BLIF N_237_i_2.BLIF RST_DLY_2_.D -11 1 -.names N_106_i_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF inst_CLK_030_H.D -11 1 -.names N_337_i.BLIF RST_c.BLIF inst_RESET_OUT.D -11 1 -.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_38_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_39_0.BLIF inst_A0_DMA.D -0 1 -.names N_40_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_41_0.BLIF inst_RW_000_INT.D -0 1 -.names N_42_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_43_0.BLIF inst_BGACK_030_INTreg.D -0 1 .names N_45_0.BLIF inst_AS_000_DMA.D 0 1 .names N_46_0.BLIF inst_AS_030_000_SYNC.D @@ -560,1187 +499,1185 @@ pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_49_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_323.BLIF inst_AS_030_D0.D +.names N_107_0.BLIF inst_AS_030_D0.D 0 1 .names N_54_0.BLIF inst_VPA_D.D 0 1 .names N_55_0.BLIF inst_DTACK_D0.D 0 1 +.names N_276_i_1.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_57_0.BLIF inst_RESET_OUT.D +0 1 +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 .names N_33_0.BLIF BG_000DFFreg.D 0 1 .names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 .names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_186_0.BLIF inst_BGACK_030_INT_D.D +.names N_36_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_37_0.BLIF inst_A0_DMA.D +0 1 +.names N_38_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_40_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_43_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_101_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_166_i.BLIF N_166 -0 1 -.names N_29_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_141_0.BLIF N_141 -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names N_226_3.BLIF sm_amiga_i_3__n.BLIF N_226 -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n -11 1 -.names N_164_i.BLIF cpu_est_i_2__n.BLIF N_357 -11 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_2__n.BLIF N_219 -11 1 -.names N_275_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_258_0 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names N_141.BLIF N_166_i.BLIF N_217 -11 1 -.names N_357.BLIF N_357_i -0 1 -.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_1__n.BLIF N_221 -11 1 -.names N_254.BLIF N_254_i -0 1 -.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_149_i.BLIF N_340.BLIF N_220 -11 1 -.names N_254_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n -11 1 -.names pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_192.BLIF N_343.BLIF N_223 -11 1 -.names N_315.BLIF N_315_i -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names vcc_n_n - 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_343 -11 1 -.names N_157.BLIF N_315_i.BLIF N_291_0 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names N_192_0.BLIF N_192 -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n -0 1 -.names gnd_n_n -.names N_164_i.BLIF N_164 -0 1 -.names N_146_0_1.BLIF nEXP_SPACE_c.BLIF N_146_0 -11 1 -.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n -11 1 -.names un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ -un1_amiga_bus_enable_dma_high_0__n -0 1 -.names N_291_0.BLIF N_291 -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_149_i -11 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ -un1_amiga_bus_enable_low -11 1 -.names N_164_i.BLIF cpu_est_2_.BLIF N_315 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_164_i -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n -0 1 -.names N_149_i.BLIF RST_DLY_2_.BLIF N_166_i -11 1 -.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names N_164.BLIF cpu_est_2_.BLIF N_254 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_172_i -11 1 -.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF \ -sm_amiga_srsts_i_0_0_m2_5__un0_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names N_258_0.BLIF N_258 -0 1 -.names N_176_i_1.BLIF sm_amiga_i_2__n.BLIF N_176_i -11 1 -.names N_122.BLIF rw_000_int_0_un3_n -0 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 -1- 1 --1 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_186_0 -11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_122.BLIF rw_000_int_0_un1_n -11 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 -11 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 1- 1 -1 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_192_0 -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 -1- 1 --1 1 -.names N_228.BLIF N_228_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_227.BLIF N_227_i +.names N_246.BLIF N_246_i 0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_343.BLIF N_343_i -0 1 +.names sm_amiga_nss_i_0_4_0__n.BLIF sm_amiga_nss_i_0_5_0__n.BLIF \ +sm_amiga_nss_i_0_0__n +11 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names un22_berr_1_0.BLIF N_366.BLIF un22_berr -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_293.BLIF as_000_int_0_un3_n -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names N_223.BLIF N_223_i -0 1 -.names sm_amiga_i_5__n.BLIF N_293.BLIF as_000_int_0_un1_n -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names N_225.BLIF N_225_i -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names N_224.BLIF N_224_i -0 1 -.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n -0 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names N_226.BLIF N_226_i -0 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ -ds_000_enable_0_un1_n -11 1 -.names N_275.BLIF N_275_i -0 1 -.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names CLK_000_N_SYNC_12_.BLIF clk_000_n_sync_i_12__n -0 1 -.names N_220.BLIF N_220_i -0 1 -.names N_290.BLIF as_030_000_sync_0_un3_n -0 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_221.BLIF N_221_i -0 1 -.names inst_AS_030_000_SYNC.BLIF N_290.BLIF as_030_000_sync_0_un1_n -11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names N_222.BLIF N_222_i -0 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names BERR_c.BLIF BERR_i -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_217.BLIF N_217_i -0 1 -.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un1_n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_215.BLIF N_215_i -0 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n -11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_219.BLIF N_219_i -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_322_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_low_0_un1_n -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_200_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names CLK_000_N_SYNC_12_.BLIF N_166_i.BLIF N_195_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_1_.BLIF N_190_0 -11 1 -.names N_321_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_high_0_un1_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_154_i.BLIF cpu_est_i_0__n.BLIF N_157_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_154_i -11 1 -.names N_294.BLIF size_dma_0_0__un3_n -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_340.BLIF N_340_i -0 1 -.names pos_clk_size_dma_6_0__n.BLIF N_294.BLIF size_dma_0_0__un1_n -11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_340_i.BLIF RST_c.BLIF N_141_0 -11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_200_i.BLIF inst_RESET_OUT.BLIF un3_as_030_i -11 1 -.names N_294.BLIF size_dma_0_1__un3_n -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_166.BLIF RST_c.BLIF N_216_i -11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_294.BLIF size_dma_0_1__un1_n -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names N_337.BLIF N_337_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names CLK_000_P_SYNC_10_.BLIF clk_000_p_sync_i_10__n -0 1 -.names N_120.BLIF ds_000_dma_0_un3_n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names pos_clk_ds_000_dma_4_n.BLIF N_120.BLIF ds_000_dma_0_un1_n -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_296_0 -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names CLK_000_D_11_.BLIF clk_000_d_i_11__n -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names N_298.BLIF as_000_dma_0_un3_n -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_284.BLIF N_284_i -0 1 -.names pos_clk_un23_bgack_030_int_i_1_n.BLIF N_298.BLIF as_000_dma_0_un1_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names N_285.BLIF N_285_i -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i -0 1 -.names N_284_i.BLIF N_285_i.BLIF N_292_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_280.BLIF N_280_i -0 1 -.names N_295.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n -11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names N_277.BLIF N_277_i -0 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_277_i.BLIF N_280_i.BLIF N_257_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n -0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_235.BLIF N_235_i -0 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -a0_dma_0_un1_n -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_236.BLIF N_236_i -0 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_235_i.BLIF N_236_i.BLIF cpu_est_2_0_1__n -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names N_231.BLIF N_231_i -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names N_230.BLIF N_230_i -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names N_230_i.BLIF N_231_i.BLIF pos_clk_un4_clk_000_pe_0_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names N_22.BLIF N_22_i -0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CLK_000_D_10_.BLIF clk_000_d_i_10__n -0 1 -.names N_334.BLIF N_334_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_335.BLIF N_335_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names N_194_0_1.BLIF nEXP_SPACE_c.BLIF N_194_0 -11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_5_.BLIF N_191_0 -11 1 -.names pos_clk_ipl_1_n.BLIF N_213_i.BLIF pos_clk_ipl_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_346.BLIF N_346_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names sm_amiga_i_6__n.BLIF SM_AMIGA_i_7_.BLIF N_163_i -11 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_345.BLIF N_345_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names N_344.BLIF N_344_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_344_i.BLIF N_345_i.BLIF N_153_0 -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n -11 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_293_0 -11 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_233.BLIF N_233_i -0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names N_232.BLIF N_232_i -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_232_i.BLIF N_233_i.BLIF N_290_0 -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_54_0 -11 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_5.BLIF N_5_i -0 1 -.names G_134.BLIF N_212_i -0 1 -.names N_5_i.BLIF RST_c.BLIF N_47_0 -11 1 -.names G_135.BLIF N_213_i -0 1 -.names N_7.BLIF N_7_i -0 1 -.names G_136.BLIF N_214_i -0 1 -.names N_7_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_18.BLIF N_18_i -0 1 -.names N_18_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names N_321.BLIF N_321_i -0 1 -.names N_10.BLIF N_10_i -0 1 -.names N_322.BLIF N_322_i -0 1 -.names N_10_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 -11 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names BGACK_000_c.BLIF N_203.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names un6_as_030.BLIF un6_as_030_i -0 1 -.names BERR_c.BLIF clk_000_p_sync_i_10__n.BLIF N_137_i -11 1 -.names un4_lds_000.BLIF un4_lds_000_i -0 1 -.names N_137.BLIF sm_amiga_i_3__n.BLIF N_184_0 -11 1 -.names un4_uds_000.BLIF un4_uds_000_i -0 1 -.names N_349.BLIF N_349_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_349_i.BLIF RST_c.BLIF N_185_i -11 1 -.names N_137_i.BLIF SM_AMIGA_4_.BLIF N_187_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names AS_000_c.BLIF CLK_000_P_SYNC_10_.BLIF N_203_i -11 1 -.names N_324.BLIF N_324_i -0 1 -.names CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF N_199_0 -11 1 -.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_197_0 -11 1 -.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF N_196_0 -11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_181_i -11 1 -.names N_347.BLIF N_347_i -0 1 -.names N_348.BLIF N_348_i -0 1 -.names N_347_i.BLIF N_348_i.BLIF N_178_i -11 1 -.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -pos_clk_un5_bgack_030_int_d_i_n -11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n -11 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_148_0 -11 1 -.names N_341.BLIF N_341_i -0 1 -.names N_338.BLIF N_338_i -0 1 -.names N_339.BLIF N_339_i -0 1 .names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +.names N_278.BLIF dsack1_int_0_un3_n +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_23 1- 1 -1 1 -.names N_336.BLIF N_336_i +.names N_220.BLIF N_220_i 0 1 +.names N_114_i.BLIF N_278.BLIF dsack1_int_0_un1_n +11 1 .names amiga_bus_enable_dma_low_0_un1_n.BLIF \ amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 1- 1 -1 1 -.names N_122_0_1.BLIF SM_AMIGA_i_7_.BLIF N_122_0 +.names N_219.BLIF N_219_i +0 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 .names amiga_bus_enable_dma_high_0_un1_n.BLIF \ amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 1- 1 -1 1 -.names N_211.BLIF N_211_i +.names N_218.BLIF N_218_i 0 1 -.names N_332.BLIF N_332_i +.names N_108.BLIF cpu_est_0_3__un3_n 0 1 -.names N_331.BLIF N_331_i +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names N_120_0_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_120_0 +.names cpu_est_3_.BLIF N_108.BLIF cpu_est_0_3__un1_n 11 1 -.names N_330.BLIF N_330_i +.names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names N_330_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ -pos_clk_ds_000_dma_4_0_n -11 1 -.names N_329.BLIF N_329_i +.names N_224.BLIF N_224_i 0 1 -.names N_329_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names N_316_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names N_328.BLIF N_328_i +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names N_328_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_325.BLIF N_325_i +.names N_222.BLIF N_222_i 0 1 -.names N_327.BLIF N_327_i +.names N_108.BLIF cpu_est_0_2__un3_n 0 1 -.names N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_320.BLIF N_320_i +.names vcc_n_n + 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i 0 1 -.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_298_0 -11 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_295_0 -11 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_294_0 -11 1 -.names N_319.BLIF N_319_i +.names N_223.BLIF N_223_i 0 1 -.names N_207.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n +.names cpu_est_2_.BLIF N_108.BLIF cpu_est_0_2__un1_n 11 1 -.names N_206.BLIF N_206_i +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_322_i +11 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names gnd_n_n +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_312.BLIF N_312_i +0 1 +.names N_108.BLIF cpu_est_0_1__un3_n +0 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low +11 1 +.names N_131.BLIF N_131_i +0 1 +.names N_312_i.BLIF RST_c.BLIF N_139_0 +11 1 +.names cpu_est_1_.BLIF N_108.BLIF cpu_est_0_1__un1_n +11 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names N_132.BLIF N_132_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_108_i +11 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_258.BLIF N_258_i +0 1 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names N_257.BLIF N_257_i +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 +11 1 +.names CLK_000_D_11_.BLIF clk_000_d_i_11__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_364_i_0.BLIF RST_c.BLIF N_245_i +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_c_i.BLIF un1_as_030_i +11 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_0_n +11 1 +.names N_273.BLIF ds_000_dma_0_un3_n +0 1 +.names un22_berr_1_0.BLIF N_157.BLIF un22_berr +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_107_0 +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_273.BLIF ds_000_dma_0_un1_n +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_115.BLIF N_115_i +0 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_115_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_63_0 +11 1 +.names N_272.BLIF as_000_dma_0_un3_n +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names N_114_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_278_0 +11 1 +.names pos_clk_un23_bgack_030_int_i_0_n.BLIF N_272.BLIF as_000_dma_0_un1_n +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names N_113_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_279_0 +11 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names N_364.BLIF N_364_i_0 +0 1 +.names N_260.BLIF N_260_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names N_260_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_67_0 +11 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_182_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_113_i.BLIF N_182_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names N_157.BLIF N_157_i +0 1 +.names nEXP_SPACE_c_i.BLIF un10_ciin_i.BLIF N_313_0 +11 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_4.BLIF N_4_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_4_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_5.BLIF N_5_i +0 1 +.names N_113.BLIF N_113_i +0 1 +.names N_5_i.BLIF RST_c.BLIF N_47_0 +11 1 +.names N_114.BLIF N_114_i +0 1 +.names N_7.BLIF N_7_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_7_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names N_18.BLIF N_18_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names N_18_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names N_22.BLIF N_22_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_22_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_26.BLIF N_26_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_10.BLIF N_10_i +0 1 +.names CLK_000_D_10_.BLIF clk_000_d_i_10__n +0 1 +.names N_10_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_54_0 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names inst_RESET_OUT.BLIF un1_as_030_i.BLIF un3_as_030_i +11 1 +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names N_370.BLIF N_370_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names BGACK_000_c.BLIF N_370_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 .names N_283.BLIF N_283_i 0 1 -.names N_122_0.BLIF N_122 +.names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names N_281.BLIF N_281_i +.names N_283_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +.names N_345.BLIF N_345_i 0 1 -.names N_282.BLIF N_282_i +.names ahigh_c_29__n.BLIF ahigh_i_29__n 0 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names N_345_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_171_i +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_21.BLIF N_21_i +0 1 +.names G_116.BLIF N_241_i +0 1 +.names N_21_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names G_117.BLIF N_242_i +0 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names pos_clk_ipl_1_n.BLIF N_242_i.BLIF pos_clk_ipl_n +11 1 +.names G_118.BLIF N_243_i +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +11 1 +.names N_249.BLIF N_249_i +0 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_248.BLIF N_248_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_248_i.BLIF N_249_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names N_250.BLIF N_250_i +0 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names N_251.BLIF N_251_i +0 1 +.names un4_lds_000.BLIF un4_lds_000_i +0 1 +.names N_250_i.BLIF N_251_i.BLIF cpu_est_2_0_1__n +11 1 +.names un4_uds_000.BLIF un4_uds_000_i +0 1 +.names N_253.BLIF N_253_i +0 1 +.names N_369.BLIF N_369_i +0 1 +.names N_253_i.BLIF N_369_i.BLIF cpu_est_2_0_2__n +11 1 +.names N_254.BLIF N_254_i +0 1 +.names N_253_i.BLIF N_254_i.BLIF N_316_i +11 1 +.names N_256.BLIF N_256_i +0 1 +.names N_255.BLIF N_255_i +0 1 +.names N_255_i.BLIF N_256_i.BLIF N_317_i +11 1 +.names N_267.BLIF N_267_i +0 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names N_266.BLIF N_266_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names N_266_i.BLIF N_267_i.BLIF N_57_0 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_151_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_321_i +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_2__n.BLIF N_158_i +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_361.BLIF N_361_i +0 1 +.names N_362.BLIF N_362_i +0 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 +1- 1 +-1 1 +.names N_361_i.BLIF N_362_i.BLIF N_169_i +11 1 +.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_186_0 +11 1 +.names N_108_i.BLIF N_169.BLIF N_195_0 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_196_0 +11 1 +.names N_263.BLIF N_263_i +0 1 +.names N_262.BLIF N_262_i +0 1 +.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_323_0 +11 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_101_i +11 1 +.names N_366.BLIF N_366_i +0 1 +.names N_366_i.BLIF SM_AMIGA_i_7_.BLIF N_182_i +11 1 +.names pos_clk_un23_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un23_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_0_0_n +11 1 +.names N_310.BLIF N_310_i +0 1 +.names N_359.BLIF N_359_i +0 1 +.names N_310_i.BLIF N_359_i.BLIF N_144_0 +11 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_142_0 +11 1 +.names N_311.BLIF N_311_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_319_i +11 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_93_i +11 1 +.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_272_0 +11 1 +.names N_290.BLIF N_290_i +0 1 +.names N_273_0_1.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_273_0 +11 1 +.names N_346.BLIF N_346_i +0 1 +.names N_346_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names N_268.BLIF N_268_i +0 1 +.names N_269.BLIF N_269_i +0 1 +.names N_268_i.BLIF N_269_i.BLIF sm_amiga_nss_0_3__n +11 1 +.names N_341.BLIF N_341_i +0 1 +.names N_238.BLIF N_238_i +0 1 +.names N_239.BLIF N_239_i +0 1 +.names N_238_i.BLIF N_239_i.BLIF sm_amiga_nss_0_2__n +11 1 +.names CYCLE_DMA_0_.BLIF N_319_i.BLIF N_263 +11 1 +.names N_235.BLIF N_235_i +0 1 +.names N_236.BLIF N_236_i +0 1 +.names N_235_i.BLIF N_236_i.BLIF sm_amiga_nss_0_4__n +11 1 +.names N_234.BLIF N_234_i +0 1 +.names pos_clk_un23_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_un23_bgack_030_int_i_0_n +0 1 +.names N_233_i.BLIF N_234_i.BLIF sm_amiga_nss_0_5__n +11 1 +.names N_272_0.BLIF N_272 +0 1 +.names N_231.BLIF N_231_i +0 1 +.names N_273_0.BLIF N_273 +0 1 +.names N_232.BLIF N_232_i +0 1 +.names N_231_i.BLIF N_232_i.BLIF sm_amiga_nss_0_6__n +11 1 +.names N_313_0.BLIF N_313 +0 1 +.names N_230.BLIF N_230_i +0 1 +.names N_229_i.BLIF N_230_i.BLIF sm_amiga_nss_0_7__n +11 1 +.names N_226.BLIF N_226_i +0 1 +.names N_108_i.BLIF N_108 +0 1 +.names N_331.BLIF N_331_i +0 1 +.names N_319_i.BLIF N_319 +0 1 +.names N_142_0.BLIF N_142 +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +11 1 +.names N_144_0.BLIF N_144 +0 1 +.names N_27.BLIF N_27_i +0 1 +.names N_322_i.BLIF N_322 +0 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_169_i.BLIF N_169 +0 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names N_195_0.BLIF N_195 +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names N_323_0.BLIF N_323 0 1 .names N_3.BLIF N_3_i 0 1 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_209 +1- 1 +-1 1 .names N_3_i.BLIF RST_c.BLIF N_49_0 11 1 +.names N_218_1.BLIF rst_dly_i_2__n.BLIF N_218 +11 1 .names N_8.BLIF N_8_i 0 1 +.names N_224_1.BLIF rst_dly_i_1__n.BLIF N_224 +11 1 .names N_8_i.BLIF RST_c.BLIF N_45_0 11 1 -.names pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ -pos_clk_un23_bgack_030_int_i_1_n -0 1 -.names N_19.BLIF N_19_i -0 1 -.names N_292_0.BLIF N_292 -0 1 -.names N_19_i.BLIF RST_c.BLIF N_40_0 +.names N_139.BLIF RST_DLY_0_.BLIF N_226 11 1 -.names N_294_0.BLIF N_294 -0 1 -.names N_20.BLIF N_20_i -0 1 -.names N_295_0.BLIF N_295 -0 1 -.names N_20_i.BLIF RST_c.BLIF N_39_0 +.names N_334_i.BLIF N_335_i.BLIF sm_amiga_nss_i_0_1_0__n 11 1 -.names N_296_0.BLIF N_296 -0 1 -.names N_24.BLIF N_24_i -0 1 -.names N_298_0.BLIF N_298 -0 1 -.names N_24_i.BLIF RST_c.BLIF N_35_0 +.names N_368.BLIF rst_dly_i_0__n.BLIF N_331 11 1 -.names N_120_0.BLIF N_120 -0 1 -.names N_25.BLIF N_25_i -0 1 -.names N_148_0.BLIF N_148 -0 1 -.names N_25_i.BLIF RST_c.BLIF N_34_0 +.names N_233_i.BLIF N_244_i.BLIF sm_amiga_nss_i_0_2_0__n 11 1 -.names N_149_i.BLIF N_149 -0 1 -.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_194_0_1 +.names N_365.BLIF SM_AMIGA_0_.BLIF N_229 11 1 -.names N_157_i.BLIF N_157 -0 1 -.names N_215_i.BLIF N_217_i.BLIF N_237_i_1 +.names N_246_i.BLIF N_229_i.BLIF sm_amiga_nss_i_0_3_0__n 11 1 -.names N_172_i.BLIF N_172 -0 1 -.names N_219_i.BLIF RST_c.BLIF N_237_i_2 +.names N_360.BLIF SM_AMIGA_1_.BLIF N_230 11 1 -.names N_176_i.BLIF N_176 -0 1 -.names N_220_i.BLIF RST_c.BLIF N_238_i_1 +.names sm_amiga_nss_i_0_1_0__n.BLIF sm_amiga_nss_i_0_2_0__n.BLIF \ +sm_amiga_nss_i_0_4_0__n 11 1 -.names N_178_i.BLIF N_178 -0 1 -.names N_221_i.BLIF N_222_i.BLIF N_238_i_2 +.names N_231_1.BLIF SM_AMIGA_1_.BLIF N_231 11 1 -.names N_181_i.BLIF N_181 -0 1 -.names N_185_i.BLIF N_223_i.BLIF N_144_i_1 +.names sm_amiga_nss_i_0_3_0__n.BLIF N_355_i.BLIF sm_amiga_nss_i_0_5_0__n 11 1 -.names N_184_0.BLIF N_184 -0 1 -.names N_224_i.BLIF N_225_i.BLIF N_144_i_2 +.names N_359.BLIF SM_AMIGA_2_.BLIF N_232 11 1 -.names N_144_i_1.BLIF N_144_i_2.BLIF N_144_i_3 -11 1 -.names N_196_0.BLIF N_196 -0 1 -.names N_227_i.BLIF N_228_i.BLIF N_136_i_1 -11 1 -.names N_197_0.BLIF N_197 -0 1 -.names N_343_i.BLIF RST_c.BLIF N_136_i_2 -11 1 -.names sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF \ -sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF N_206 -1- 1 --1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_176_i_1 -11 1 -.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_207 -1- 1 --1 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_0_.BLIF N_146_0_1 -11 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_211 -1- 1 --1 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_215_1.BLIF rst_dly_i_2__n.BLIF N_215 +.names N_233_1.BLIF SM_AMIGA_3_.BLIF N_233 11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names N_222_1.BLIF rst_dly_i_1__n.BLIF N_222 +.names N_365.BLIF SM_AMIGA_2_.BLIF N_234 11 1 .names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names N_224_1.BLIF clk_000_p_sync_i_10__n.BLIF N_224 +.names N_195.BLIF N_355.BLIF N_235 11 1 .names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names N_225_1.BLIF clk_000_n_sync_i_12__n.BLIF N_225 +.names N_359.BLIF SM_AMIGA_4_.BLIF N_236 11 1 .names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 -.names N_196.BLIF sm_amiga_i_3__n.BLIF N_227 +.names N_238_1.BLIF SM_AMIGA_5_.BLIF N_238 11 1 .names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names N_228_1.BLIF sm_amiga_i_4__n.BLIF N_228 +.names N_359.BLIF SM_AMIGA_6_.BLIF N_239 11 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names N_236_1.BLIF cpu_est_i_3__n.BLIF N_236 +.names N_240_1.BLIF SM_AMIGA_i_7_.BLIF N_240 11 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names N_277_1.BLIF SM_AMIGA_2_.BLIF N_277 +.names N_251_1.BLIF cpu_est_i_3__n.BLIF N_251 11 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names N_187.BLIF sm_amiga_i_5__n.BLIF N_281 +.names cycle_dma_i_0__n.BLIF N_319.BLIF N_262 11 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 -.names clk_000_n_sync_i_12__n.BLIF sm_amiga_i_4__n.BLIF N_282 +.names CLK_030_H_i.BLIF N_323.BLIF N_341 11 1 .names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 -.names N_191.BLIF sm_amiga_i_6__n.BLIF N_283 +.names N_365.BLIF SM_AMIGA_4_.BLIF N_268 11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names N_285_1.BLIF cpu_est_i_3__n.BLIF N_285 +.names N_360.BLIF SM_AMIGA_5_.BLIF N_269 11 1 -.names N_157_i.BLIF VMA_INT_i.BLIF N_347_1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_1_n 11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_318 +.names N_282_1.BLIF un1_as_030_i.BLIF N_282 11 1 -.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_347_2 +.names pos_clk_un23_bgack_030_int_i_0_o2_2_x2.BLIF N_311_i.BLIF \ +pos_clk_un23_bgack_030_int_i_0_0_2_n 11 1 -.names N_319_1.BLIF SM_AMIGA_0_.BLIF N_319 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_346 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_1_n +.names AS_000_i.BLIF N_101_i.BLIF N_60_i_1 11 1 -.names CLK_030_H_i.BLIF N_197.BLIF N_320 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_290 11 1 -.names pos_clk_un23_bgack_030_int_i_0_x2.BLIF N_341_i.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_2_n +.names N_262_i.BLIF N_263_i.BLIF N_60_i_2 11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_321 +.names BERR_c.BLIF RST_c.BLIF N_310 11 1 -.names FPU_SENSE_i.BLIF N_366.BLIF un21_fpu_cs_1 +.names N_158_i.BLIF N_319_i.BLIF N_248_1 11 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_322 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_311 11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_248_2 +11 1 +.names N_310.BLIF SM_AMIGA_3_.BLIF N_355 +11 1 +.names N_108_i.BLIF N_369.BLIF N_249_1 +11 1 +.names N_356_1.BLIF clk_000_d_i_10__n.BLIF N_356 +11 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_249_2 +11 1 +.names N_319_i.BLIF RST_c.BLIF N_359 +11 1 +.names N_151_0.BLIF N_158_i.BLIF N_361_1 +11 1 +.names N_108_i.BLIF RST_c.BLIF N_360 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_361_2 +11 1 +.names N_310.BLIF N_319.BLIF N_365 +11 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_157_1 +11 1 +.names N_319_i.BLIF SM_AMIGA_0_.BLIF N_366 +11 1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_157_2 +11 1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_157_3 +11 1 +.names N_157_1.BLIF N_157_2.BLIF N_157_4 +11 1 +.names N_248_1.BLIF N_248_2.BLIF N_248 +11 1 +.names N_157_i.BLIF N_363.BLIF N_260_1 +11 1 +.names N_249_1.BLIF N_249_2.BLIF N_249 +11 1 +.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_260_2 +11 1 +.names N_321_i.BLIF cpu_est_i_2__n.BLIF N_369 +11 1 +.names FPU_SENSE_i.BLIF N_157.BLIF un21_fpu_cs_1 +11 1 +.names N_196_0.BLIF N_196 +0 1 .names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_323 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_366_1 -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_325 -11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_366_2 -11 1 -.names N_327_1.BLIF RW_000_c.BLIF N_327 -11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_366_3 -11 1 -.names BGACK_030_INT_i.BLIF N_181.BLIF N_328 -11 1 -.names N_366_1.BLIF N_366_2.BLIF N_366_4 -11 1 -.names BGACK_030_INT_i.BLIF N_181_i.BLIF N_329 -11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_163_i.BLIF un1_SM_AMIGA_5_i_1 -11 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 -11 1 -.names N_346_i.BLIF sm_amiga_i_0__n.BLIF un1_SM_AMIGA_5_i_2 -11 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 -11 1 -.names N_163.BLIF N_334_i.BLIF N_142_i_1 -11 1 -.names N_190.BLIF sm_amiga_i_2__n.BLIF N_332 -11 1 -.names N_335_i.BLIF RST_c.BLIF N_142_i_2 -11 1 -.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF N_336 -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_0__n.BLIF N_339_1 -11 1 -.names N_141.BLIF RST_DLY_0_.BLIF N_338 -11 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_280_1 -11 1 -.names N_339_1.BLIF RST_c.BLIF N_339 -11 1 -.names RST_c.BLIF SM_AMIGA_3_.BLIF N_280_2 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_341 -11 1 -.names CLK_000_N_SYNC_12_.BLIF N_357.BLIF N_231_1 -11 1 -.names N_344_1.BLIF clk_000_d_i_10__n.BLIF N_344 -11 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_231_2 -11 1 -.names N_347_1.BLIF N_347_2.BLIF N_347 -11 1 -.names CLK_000_P_SYNC_10_.BLIF cpu_est_i_0__n.BLIF N_230_1 -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_230_2 -11 1 -.names N_230_1.BLIF N_230_2.BLIF N_230_3 -11 1 -.names N_146.BLIF N_172_i.BLIF N_226_1 -11 1 -.names N_176_i.BLIF sm_amiga_i_0__n.BLIF N_226_2 -11 1 -.names N_226_1.BLIF N_226_2.BLIF N_226_3 -11 1 -.names N_199_0.BLIF N_199 +.names N_186_0.BLIF N_186 0 1 -.names N_338_i.BLIF N_339_i.BLIF N_239_i_1 +.names N_222_i.BLIF N_223_i.BLIF N_275_i_1 11 1 -.names N_199.BLIF sm_amiga_i_0__n.BLIF N_324 +.names N_361_1.BLIF N_361_2.BLIF N_361 11 1 -.names N_336_i.BLIF sm_amiga_i_5__n.BLIF N_122_0_1 +.names N_224_i.BLIF RST_c.BLIF N_275_i_2 11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_362 11 1 -.names N_211_i.BLIF N_332_i.BLIF N_132_i_1 +.names N_218_i.BLIF N_219_i.BLIF N_274_i_1 11 1 -.names N_366_4.BLIF N_366_3.BLIF N_366 -11 1 -.names N_331_i.BLIF RW_000_i.BLIF N_120_0_1 -11 1 -.names N_137.BLIF SM_AMIGA_i_7_.BLIF N_335 -11 1 -.names N_320_i.BLIF RST_c.BLIF N_106_i_1 -11 1 -.names CLK_000_P_SYNC_10_.BLIF CYCLE_DMA_0_.BLIF N_208 -11 1 -.names AS_000_i.BLIF N_186_0.BLIF N_103_i_1 -11 1 -.names N_203_i.BLIF N_203 +.names N_151_0.BLIF N_151 0 1 -.names AS_000_i.BLIF N_186_0.BLIF N_92_i_1 +.names N_220_i.BLIF RST_c.BLIF N_274_i_2 11 1 -.names N_187_0.BLIF N_187 +.names N_321_i.BLIF N_321 0 1 -.names N_206_i.BLIF N_283_i.BLIF N_140_i_1 +.names N_143.BLIF sm_amiga_i_0__n.BLIF N_115_1 11 1 -.names N_137_i.BLIF N_137 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_266 +11 1 +.names sm_amiga_i_5__n.BLIF SM_AMIGA_i_7_.BLIF N_115_2 +11 1 +.names N_360.BLIF N_364.BLIF N_267 +11 1 +.names CLK_000_D_2_.BLIF N_332_4.BLIF N_332_1 +11 1 +.names N_186.BLIF cpu_est_2_.BLIF N_255 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_246_1 +11 1 +.names N_151.BLIF cpu_est_i_2__n.BLIF N_256 +11 1 +.names CLK_000_D_2_.BLIF N_180_i.BLIF N_246_2 +11 1 +.names N_321.BLIF cpu_est_2_.BLIF N_253 +11 1 +.names N_320_i.BLIF N_332_4.BLIF N_246_3 +11 1 +.names N_196.BLIF cpu_est_i_2__n.BLIF N_254 +11 1 +.names N_246_1.BLIF N_246_2.BLIF N_246_4 +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names N_281_i.BLIF N_282_i.BLIF N_138_i_1 +.names AS_030_000_SYNC_i.BLIF clk_000_d_i_1__n.BLIF N_332_4_1 11 1 -.names N_137.BLIF SM_AMIGA_0_.BLIF N_349 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names RST_c.BLIF nEXP_SPACE_c.BLIF N_332_4_2 11 1 -.names N_148.BLIF CLK_000_D_11_.BLIF N_344_1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_250 +11 1 +.names N_290_i.BLIF RW_000_i.BLIF N_273_0_1 +11 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names N_341_i.BLIF RST_c.BLIF N_276_i_1 +11 1 +.names N_322_i.BLIF RST_DLY_2_.BLIF N_364 +11 1 +.names pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF AS_000_i.BLIF N_277_i_1 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names N_226_i.BLIF N_331_i.BLIF N_314_i_1 +11 1 +.names N_171_i.BLIF N_171 +0 1 +.names N_142.BLIF CLK_000_D_11_.BLIF N_356_1 +11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names AS_000_i.BLIF RW_000_c.BLIF N_282_1 +11 1 +.names BGACK_030_INT_i.BLIF N_171_i.BLIF N_345 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_251_1 +11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names BGACK_030_INT_i.BLIF N_171.BLIF N_283 +11 1 +.names N_365.BLIF SM_AMIGA_6_.BLIF N_240_1 11 1 .names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +.names N_108.BLIF N_310.BLIF N_238_1 +11 1 +.names AS_000_c.BLIF N_319_i.BLIF N_370 +11 1 +.names N_169.BLIF N_360.BLIF N_233_1 +11 1 +.names N_363.BLIF RST_c.BLIF N_259 +11 1 +.names N_108.BLIF N_310.BLIF N_231_1 11 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 1- 1 -1 1 -.names AS_000_i.BLIF N_200_i.BLIF N_327_1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names N_245_i.BLIF rst_dly_i_0__n.BLIF N_224_1 +11 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 +.names N_245_i.BLIF N_322.BLIF N_218_1 +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_243_i.BLIF N_241_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_156.BLIF SM_AMIGA_1_.BLIF N_114 +11 1 +.names N_363.BLIF rw_000_dma_0_un3_n +0 1 +.names N_278_0.BLIF N_278 +0 1 +.names inst_RW_000_DMA.BLIF N_363.BLIF rw_000_dma_0_un1_n 11 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 1- 1 -1 1 -.names inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF N_319_1 -11 1 -.names N_293_0.BLIF N_293 +.names N_25.BLIF N_25_i 0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_285_1 +.names N_281.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_319_i.BLIF SM_AMIGA_6_.BLIF N_113 +11 1 +.names N_25_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +0 1 +.names N_279_0.BLIF N_279 +0 1 +.names N_24.BLIF N_24_i +0 1 +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_184.BLIF RST_c.BLIF N_277_1 +.names N_24_i.BLIF RST_c.BLIF N_35_0 11 1 -.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names N_115_1.BLIF N_115_2.BLIF N_115 +11 1 +.names N_23.BLIF N_23_i 0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_236_1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_63_0.BLIF N_63 +0 1 +.names N_23_i.BLIF RST_c.BLIF N_36_0 11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \ -DS_000_ENABLE_1_sqmuxa_1 -11 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_228_1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n 11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 1- 1 -1 1 -.names N_172.BLIF BERR_i.BLIF N_225_1 +.names N_19.BLIF N_19_i +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +.names pos_clk_un3_as_030_d0_0_n.BLIF pos_clk_un3_as_030_d0_n 0 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_176.BLIF BERR_i.BLIF N_224_1 +.names N_19_i.BLIF RST_c.BLIF N_40_0 11 1 -.names N_290_0.BLIF N_290 +.names N_363.BLIF amiga_bus_enable_dma_high_0_un3_n 0 1 -.names N_216_i.BLIF rst_dly_i_0__n.BLIF N_222_1 +.names N_67_0.BLIF N_67 +0 1 +.names N_17.BLIF N_17_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_363.BLIF \ +amiga_bus_enable_dma_high_0_un1_n 11 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names N_149.BLIF N_216_i.BLIF N_215_1 -11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names N_214_i.BLIF N_212_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_194.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_232 -11 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names N_194_0.BLIF N_194 -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names N_366.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_233 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names N_153.BLIF SM_AMIGA_1_.BLIF N_275 -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 -.names N_153_0.BLIF N_153 -0 1 -.names N_26.BLIF N_26_i -0 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names N_191_0.BLIF N_191 -0 1 -.names N_26_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_146.BLIF sm_amiga_i_6__n.BLIF N_334 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n -0 1 -.names N_146_0.BLIF N_146 -0 1 -.names N_21_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_345 -11 1 -.names N_17.BLIF N_17_i -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names clk_000_p_sync_i_10__n.BLIF SM_AMIGA_4_.BLIF N_346 -11 1 .names N_17_i.BLIF RST_c.BLIF N_42_0 11 1 -.names N_258.BLIF dsack1_int_0_un3_n -0 1 -.names N_163_i.BLIF N_163 -0 1 -.names N_4.BLIF N_4_i -0 1 -.names N_275_i.BLIF N_258.BLIF dsack1_int_0_un1_n +.names N_132_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n 11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names N_4_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names pos_clk_un4_clk_000_pe_0_n.BLIF pos_clk_un4_clk_000_pe_n +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n 0 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_235 -11 1 .names ipl_c_1__n.BLIF ipl_c_i_1__n 0 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_154_i.BLIF cpu_est_i_1__n.BLIF N_284 -11 1 +.names N_363.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 .names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names N_190_0.BLIF N_190 -0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_363.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_22 +1- 1 +-1 1 .names ipl_c_2__n.BLIF ipl_c_i_2__n 0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names N_131_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n 11 1 -.names N_195.BLIF RESET_OUT_i.BLIF N_337 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 .names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_195_0.BLIF N_195 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names N_27.BLIF N_27_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names CLK_000_N_SYNC_12_.BLIF N_166.BLIF N_340 -11 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names N_231_1.BLIF N_231_2.BLIF N_231 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_363 11 1 .names N_28.BLIF N_28_i 0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_230_3.BLIF cpu_est_i_3__n.BLIF N_230 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 +1- 1 +-1 1 .names N_28_i.BLIF RST_c.BLIF N_31_0 11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names N_280_1.BLIF N_280_2.BLIF N_280 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_157_4.BLIF N_157_3.BLIF N_157 11 1 .names N_29.BLIF N_29_i 0 1 -.names N_291.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names N_260_1.BLIF N_260_2.BLIF N_260 11 1 -.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_134 +.names N_29_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_139.BLIF N_364.BLIF N_219 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n +0 1 +.names N_139_0.BLIF N_139 +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names N_108.BLIF rst_dly_i_2__n.BLIF N_220 +11 1 +.names N_332.BLIF N_332_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n +11 1 +.names N_139.BLIF N_322_i.BLIF N_222 +11 1 +.names N_240.BLIF N_240_i +0 1 +.names N_279.BLIF as_000_int_0_un3_n +0 1 +.names N_368.BLIF rst_dly_i_1__n.BLIF N_223 +11 1 +.names N_240_i.BLIF N_332_i.BLIF N_315_0 +11 1 +.names N_113_i.BLIF N_279.BLIF as_000_int_0_un1_n +11 1 +.names N_108.BLIF RST_c.BLIF N_368 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_281_0 +11 1 +.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names N_108.BLIF cpu_est_i_0__n.BLIF N_257 +11 1 +.names N_270.BLIF N_270_i +0 1 +.names N_63.BLIF ds_000_enable_0_un3_n +0 1 +.names N_108_i.BLIF cpu_est_0_.BLIF N_258 +11 1 +.names N_282.BLIF N_282_i +0 1 +.names N_115.BLIF N_63.BLIF ds_000_enable_0_un1_n +11 1 +.names N_108_i.BLIF N_364_i_0.BLIF N_312 +11 1 +.names N_270_i.BLIF N_282_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n +11 1 +.names N_143_0.BLIF N_143 +0 1 +.names RW_c.BLIF RW_c_i +0 1 +.names N_67.BLIF as_030_000_sync_0_un3_n +0 1 +.names N_332_1.BLIF sm_amiga_i_i_7__n.BLIF N_332 +11 1 +.names RW_c_i.BLIF SM_AMIGA_6_.BLIF N_140_0 +11 1 +.names pos_clk_un3_as_030_d0_n.BLIF N_67.BLIF as_030_000_sync_0_un1_n +11 1 +.names N_332_4_1.BLIF N_332_4_2.BLIF N_332_4 +11 1 +.names N_353.BLIF N_353_i +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names N_246_4.BLIF N_246_3.BLIF N_246 +11 1 +.names N_159.BLIF N_353_i.BLIF N_143_0 +11 1 +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +0 1 +.names N_180_i.BLIF N_180 +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +rw_000_int_0_un1_n +11 1 +.names N_320_i.BLIF N_320 +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_320_i +11 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names N_320.BLIF N_360.BLIF N_244 +11 1 +.names N_357.BLIF N_357_i +0 1 +.names N_363.BLIF a0_dma_0_un3_n +0 1 +.names N_144.BLIF N_180.BLIF N_334 +11 1 +.names N_356.BLIF N_356_i +0 1 +.names inst_A0_DMA.BLIF N_363.BLIF a0_dma_0_un1_n +11 1 +.names N_310.BLIF N_320.BLIF N_335 +11 1 +.names N_356_i.BLIF N_357_i.BLIF N_156_0 +11 1 +.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names N_159_i.BLIF N_159 +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names N_156_0.BLIF N_156 +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_159_i +11 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_357 +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_140.BLIF N_319_i.BLIF N_353 +11 1 +.names N_159_i.BLIF sm_amiga_i_2__n.BLIF N_180_i +11 1 +.names N_259.BLIF size_dma_0_1__un3_n +0 1 +.names N_140_0.BLIF N_140 +0 1 +.names N_334.BLIF N_334_i +0 1 +.names SIZE_DMA_1_.BLIF N_259.BLIF size_dma_0_1__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_270 +11 1 +.names N_335.BLIF N_335_i +0 1 +.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ +size_dma_0_1__un0_n +11 1 +.names N_281_0.BLIF N_281 +0 1 +.names N_244.BLIF N_244_i +0 1 +.names N_259.BLIF size_dma_0_0__un3_n +0 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_131 +11 1 +.names N_233.BLIF N_233_i +0 1 +.names SIZE_DMA_0_.BLIF N_259.BLIF size_dma_0_0__un1_n +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_132 +11 1 +.names N_355.BLIF N_355_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \ +size_dma_0_0__un0_n +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +1- 1 +-1 1 +.names N_229.BLIF N_229_i +0 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_116 01 1 10 1 11 0 00 0 -.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_135 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_117 01 1 10 1 11 0 00 0 -.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_136 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_118 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_x2 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +pos_clk_un23_bgack_030_int_i_0_o2_2_x2 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_ -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_0_.BLIF CLK_000_P_SYNC_10_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_1_.BLIF N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +.names CYCLE_DMA_1_.BLIF N_263.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2 01 1 10 1 11 0 @@ -1772,7 +1709,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_292.BLIF E +.names N_317_i.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1790,7 +1727,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names un1_amiga_bus_enable_dma_high_0__n.BLIF AMIGA_BUS_ENABLE_HIGH +.names N_209.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 .names un10_ciin.BLIF CIIN @@ -1850,192 +1787,6 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C -1 1 -0 0 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C -1 1 -0 0 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C -1 1 -0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 -0 0 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C -1 1 -0 0 -.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_12_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -0 0 -.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 -0 0 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 -0 0 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 -0 0 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C -1 1 -0 0 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C -1 1 -0 0 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C -1 1 -0 0 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C -1 1 -0 0 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C -1 1 -0 0 -.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_10_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C -1 1 -0 0 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C -1 1 -0 0 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C -1 1 -0 0 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C -1 1 -0 0 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C -1 1 -0 0 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C -1 1 -0 0 -.names CLK_000_c.BLIF CLK_000_D_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -0 0 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -0 0 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -0 0 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_3_.C -1 1 -0 0 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_4_.C -1 1 -0 0 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_5_.C -1 1 -0 0 .names CLK_000_D_5_.BLIF CLK_000_D_6_.D 1 1 0 0 @@ -2078,16 +1829,22 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF CLK_000_D_12_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 -.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_1_.C @@ -2096,34 +1853,43 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +0 0 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_AS_000_DMA.C @@ -2150,6 +1916,15 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF inst_DTACK_D0.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -2159,10 +1934,25 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 0 0 -.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C @@ -2369,9 +2159,6 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_030.BLIF CLK_030_c 1 1 0 0 -.names CLK_000.BLIF CLK_000_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -2420,10 +2207,10 @@ DS_000_ENABLE_1_sqmuxa_1 .names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 -.names N_200_i.BLIF SIZE_0_.OE +.names un1_as_030_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_200_i.BLIF SIZE_1_.OE +.names un1_as_030_i.BLIF SIZE_1_.OE 1 1 0 0 .names un3_as_030_i.BLIF AHIGH_24_.OE @@ -2456,7 +2243,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names un22_berr.BLIF BERR.OE 1 1 0 0 -.names N_318.BLIF RW.OE +.names N_93_i.BLIF RW.OE 1 1 0 0 .names un3_as_030_i.BLIF DS_030.OE @@ -2468,7 +2255,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_296.BLIF CIIN.OE +.names N_313.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 520efcc..5987a90 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,64 +1,49 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE 68030_tk -#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \ -# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_030_2_ IPL_2_ FC_1_ AS_030 \ -# AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE A_0_ BERR IPL_030_1_ BG_030 IPL_030_0_ \ -# BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE \ -# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ \ -# AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ -#$ NODES 89 N_226 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ \ -# cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \ +#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \ +# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \ +# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \ +# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \ +# RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 63 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_3_ cpu_est_0_ cpu_est_1_ \ +# cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \ # inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \ # CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \ -# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 \ -# inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ \ -# SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ \ -# CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ \ -# SM_AMIGA_0_ inst_DSACK1_INTreg CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE \ -# CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \ -# CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \ -# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \ -# CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ \ -# CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ \ -# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ \ -# inst_RW_000_INT inst_RW_000_DMA inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH \ -# inst_A0_DMA SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ \ -# SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg \ -# IPL_030DFF_2_reg +# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ \ +# inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ \ +# IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ \ +# CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg inst_DS_000_ENABLE SM_AMIGA_6_ \ +# SM_AMIGA_0_ SM_AMIGA_4_ inst_RW_000_INT inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ \ +# RST_DLY_2_ inst_A0_DMA inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ \ +# SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \ +# IPL_030DFF_1_reg IPL_030DFF_2_reg .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ -A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF N_226.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \ +A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_AS_000_INT.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \ SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ -inst_CLK_OUT_PRE_D.BLIF CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF \ -inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \ -IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF CLK_000_D_2_.BLIF \ -CLK_000_D_3_.BLIF CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF CLK_000_D_6_.BLIF \ -CLK_000_D_7_.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF CLK_000_D_12_.BLIF \ -SM_AMIGA_0_.BLIF inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_0_.BLIF \ -SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF CLK_000_N_SYNC_12_.BLIF \ -RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF CLK_000_P_SYNC_0_.BLIF \ -CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \ -CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \ -CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.BLIF \ -CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \ -CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF \ -CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \ -CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.BLIF inst_RW_000_INT.BLIF \ -inst_RW_000_DMA.BLIF inst_CLK_000_NE_D0.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF \ -inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ -SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \ +inst_CLK_OUT_PRE_D.BLIF CLK_000_D_1_.BLIF CLK_000_D_10_.BLIF \ +CLK_000_D_11_.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF \ +inst_CLK_OUT_PRE_50.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \ +CLK_000_D_2_.BLIF CLK_000_D_3_.BLIF CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF \ +CLK_000_D_6_.BLIF CLK_000_D_7_.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF \ +CLK_000_D_12_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF \ +inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \ +inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \ +BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \ IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ @@ -66,186 +51,149 @@ AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ -SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ -IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ -IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ -CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \ -CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \ -CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ -CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \ -CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ -CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ -SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ -CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ -CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ -CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ -CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \ -CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \ -CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ -CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ -CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \ -CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ -CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \ -CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ -CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \ -CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ -CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ -CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ -RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \ -inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \ -inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ +SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ +IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ +IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \ +IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_6_.D CLK_000_D_6_.C \ +CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D \ +CLK_000_D_9_.C CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C \ +CLK_000_D_12_.D CLK_000_D_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ +cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_1_.C RST_DLY_2_.D \ +RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ +CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ +CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C RST_DLY_0_.D RST_DLY_0_.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \ +inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.D \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D \ inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ \ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \ -N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ -AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ -DSACK1.OE RESET.OE CIIN.OE inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 \ -SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 -.names RST.BLIF N_226.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF \ -inst_DTACK_D0.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_0_.BLIF \ -SM_AMIGA_4_.BLIF CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ -BERR.PIN.BLIF SM_AMIGA_i_7_.D -10001000--000-100-0- 1 -10001000---00110--0- 1 -10001000-100--1-0--- 1 -10001000-1-0-11----- 1 -10-----10-000-100-0- 1 -10-----10--00110--0- 1 -10--------000--0000- 1 -10-----10100--1-0--- 1 -10---------001-0-00- 1 -10-----101-0-11----- 1 -10-------100----00-- 1 -10-------1-0-1---0-- 1 -10-------0---------1 1 -10---------0-------1 1 --------11--------1-0 0 ----------1-1-------- 0 -------10---------1-0 0 ------1-0---------1-0 0 -----0--0---------1-0 0 ----1---0---------1-0 0 ---1----0---------1-0 0 --------------0--1--0 0 -----------1--0-----0 0 ----------0--------10 0 ----------0-----1---0 0 ----------0--1------0 0 ---------------0--1-0 0 --1------------------ 0 -0------------------- 0 ------------1-------0 0 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF \ -CLK_000_P_SYNC_10_.BLIF CLK_000_N_SYNC_0_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D -110-1-0- 1 --1-0-1-1 1 --1---10- 1 ----1--1- 0 -----00-- 0 ---1--0-- 0 -0----0-- 0 ------01- 0 --0------ 0 -------10 0 -.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \ -CLK_000_N_SYNC_12_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D -110-1- 1 -1-10-1 1 +AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE \ +AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \ +AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE \ +CIIN.OE cpu_est_2_.D.X1 cpu_est_2_.D.X2 RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 \ +inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 \ +SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF CLK_000_D_2_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_6_.D +1100-1-0- 1 +-1--0-111 1 +-1-1--111 1 +---01--1- 0 +------01- 0 +-----0-0- 0 +---1---0- 0 +--1----0- 0 +0------0- 0 +-0------- 0 +-------10 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D +1011-- 1 1-1-11 1 ----10- 0 --00--- 0 ---0-0- 0 ---1--0 0 -0----- 0 -.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF \ -CLK_000_N_SYNC_12_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D -10-1-1 1 -1-1-1- 1 -1-11-- 1 +10--11 1 ---00- 0 +--0-0- 0 +-1--0- 0 -10--- 0 ---00-- 0 +---0-0 0 0----- 0 --0--0 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ -CLK_000_P_SYNC_10_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF \ -SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_2_.D -1001000--11-- 1 -1-----10-11-- 1 -1-------0--11 1 -1---------11- 1 -------11---0- 0 ---------1-0-- 0 +-1---0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_5_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D +110-1- 1 +1-01-1 1 +11-1-1 1 +---00- 0 +--10-- 0 +-0-0-- 0 +-01--- 0 +----00 0 +0----- 0 +--1--0 0 +-0---0 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ +inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_2_.D +10100001-01-- 1 +1-----11001-- 1 +1--------0-11 1 +1------1---11 1 +------1-1--0- 0 -----10----0- 0 ----1-0----0- 0 ----0--0----0- 0 ---1---0----0- 0 +---1--0----0- 0 +--0---0----0- 0 -1----0----0- 0 ----------0-0- 0 +------1-1---0 0 +-------0-1--- 0 +-----10-----0 0 +----1-0-----0 0 +---1--0-----0 0 +--0---0-----0 0 +-1----0-----0 0 ----------00- 0 -0------------ 0 +---------1-0- 0 +-------0---0- 0 ----------0-0 0 -.names RST.BLIF CLK_000_P_SYNC_10_.BLIF CLK_000_N_SYNC_12_.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D -11-01- 1 -1-01-1 1 -1--111 1 ---1-0- 0 --0-0-- 0 +0------------ 0 +---------1--0 0 +-------0----0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D +101-1- 1 +1-11-1 1 +10-1-1 1 ---00- 0 ----1-0 0 -0----- 0 -.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF \ -CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D -1-011- 1 -101--1 1 --11--- 0 ---0-0- 0 --00-- 0 ---1--0 0 +-1-0-- 0 +-10--- 0 +----00 0 0----- 0 -.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \ -cpu_est_2_.D -0111 1 -1-0- 1 -10-- 1 -1--0 1 -1111 0 -0-0- 0 -00-- 0 -0--0 0 -.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -inst_CLK_000_NE_D0.BLIF cpu_est_3_.D -1-111 1 -010-- 1 --1--0 1 ---101 0 -00--- 0 -1-0-1 0 -0-1-1 0 --0--0 0 +--0--0 0 +-1---0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D +110-1- 1 +1-01-1 1 +11-1-1 1 +---00- 0 +--10-- 0 +-0-0-- 0 +-01--- 0 +----00 0 +0----- 0 +--1--0 0 +-0---0 0 +.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D +-11110 1 +10-0-- 1 +1---0- 1 +1----1 1 +0--0-- 0 +-10-10 0 +-1-010 0 +-0-110 0 +0---0- 0 +0----1 0 .names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D 0-01100- 1 @@ -327,26 +275,30 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D 1- 1 -0 1 01 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \ -CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D -10100 1 -10010 1 ---00- 0 ---11- 0 --1--- 0 -0---- 0 -----1 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D -101010 1 -10-100 1 -1001-0 1 ---111- 0 ----00- 0 ---00-- 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D +100010 1 +101-00 1 +1011-0 1 +--101- 0 +--0-0- 0 +--01-- 0 -1---- 0 0----- 0 -----1 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D +1010010 1 +10-1-00 1 +10-11-0 1 +1001--0 1 +--1101- 0 +---0-0- 0 +---01-- 0 +--00--- 0 +-1----- 0 +0------ 0 +------1 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D -111-- 1 @@ -365,150 +317,44 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D 11-0-- 0 110--- 0 10---1 0 -.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \ -cpu_est_1_.D -0101 1 --01- 1 ---10 1 -1-0- 0 --111 0 --00- 0 ---00 0 -.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D -10 1 -0- 0 --1 0 -.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D -01 1 -1- 0 --0 0 -.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ -RST_DLY_2_.BLIF RST_DLY_0_.D -1-111 1 -110-- 1 -101-- 1 --110- 0 --00-- 0 --11-0 0 -0---- 0 -.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ -RST_DLY_2_.BLIF RST_DLY_1_.D -1--11 1 -1110- 1 -1-01- 1 -10-1- 1 +.names cpu_est_0_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_0_.D +010 1 +10- 1 +1-1 1 +110 0 +00- 0 +0-1 0 +.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF cpu_est_1_.D +01010 1 +-01-- 1 +--10- 1 +--1-1 1 +1-0-- 0 -1110 0 --00- 0 --0-0- 0 -0---- 0 -.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ -RST_DLY_2_.BLIF RST_DLY_2_.D -1111- 1 -1---1 1 -0---- 0 ----00 0 ---0-0 0 --0--0 0 -.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D -1-1111 1 -11---- 1 --0--0- 0 --0-0-- 0 --00--- 0 +-00-- 0 +--0-1 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D +11011- 1 +1----1 1 0----- 0 +----00 0 +---0-0 0 +--1--0 0 -0---0 0 -.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \ -SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D -1--000-01-- 1 -1-100--01-- 1 -10----1--1- 1 -1---00-01-1 1 -1-1-0--01-1 1 ---0--1---0- 0 ---0--10---- 0 --10--1----- 0 ----1-----00 0 ----1--0---0 0 --1-1------0 0 ---------00- 0 --------1-0- 0 -----1----0- 0 -------0-0-- 0 --1------0-- 0 -------01--- 0 --1-----1--- 0 -----1-0---- 0 --1--1------ 0 -0---------- 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_P_SYNC_10_.BLIF \ -CLK_000_N_SYNC_12_.BLIF inst_VMA_INTreg.D ---0000-1- 1 --1----1-- 1 --1---0--- 1 --1--0---- 1 --1------0 1 -0-------- 1 --1-1----- 1 --11------ 1 -1-00110-1 0 -10-----0- 0 -10-1----- 0 -101------ 0 -10---1--- 0 -10--1---- 0 -.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ -inst_UDS_000_INT.D --10- 1 -0--- 1 ---11 1 -100- 0 -1-10 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D --111- 1 -0---- 1 --0--1 1 -11-0- 0 -110-- 0 -10--0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1-1- 1 --10-- 1 -0---- 1 --0--1 1 -1110- 0 -10--0 0 -.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_0_.BLIF \ -inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D ---0-1-- 1 --101--- 1 ---0--0- 1 -0------ 1 ---1---1 1 -1-0001- 0 -100-01- 0 -1-1---0 0 -.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D ---1100 1 --10--- 1 -0----- 1 -100--- 0 -1-1-1- 0 -1-10-- 0 -1-1--1 0 -.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \ -CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D -1-1-- 1 -1--11 1 --0--- 1 --100- 0 --10-0 0 -01--- 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D +1--111 1 +1100-- 1 +1-11-- 1 +10-1-- 1 +-1010- 0 +-101-0 0 +--10-- 0 +-0-0-- 0 +0----- 0 .names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ LDS_000.PIN.BLIF inst_AS_000_DMA.D @@ -546,14 +392,20 @@ SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D -111----10-101 0 011-----10-101 0 --1------00--1 0 -.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF SM_AMIGA_5_.BLIF \ -BERR.PIN.BLIF inst_AS_000_INT.D --1-0- 1 ---10- 1 -0---- 1 ----00 1 -100-1 0 -1--1- 0 +.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF inst_AS_000_INT.D +-1---0- 1 +-1--0-- 1 +-1-1--- 1 +--1--0- 1 +--1-0-- 1 +--11--- 1 +0------ 1 +-----00 1 +----0-0 1 +---1--0 1 +1--011- 0 +100---1 0 .names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \ CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF CLK_000_D_12_.BLIF \ inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D @@ -561,8 +413,8 @@ inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D -----001-- 1 ----11-1-- 1 1-10-1---- 1 -1--0-1---0 1 -------10- 1 +1--0-1---0 1 --1--00--- 1 --1-11---- 1 -----00--0 1 @@ -615,13 +467,56 @@ inst_DS_000_DMA.D 1- 1 -0 1 01 0 +.names RST.BLIF CLK_000_D_1_.BLIF inst_RESET_OUT.BLIF CLK_000_D_0_.BLIF \ +RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D +11-0111 1 +1-1---- 1 +0------ 0 +--0--0- 0 +--0-0-- 0 +--01--- 0 +-00---- 0 +--0---0 0 +.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ +inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF \ +inst_DS_000_ENABLE.D +1-01-00-01-- 1 +1-01--0-01-1 1 +1----00001-- 1 +10--1-----1- 1 +---0---1--0- 0 +--1----1--0- 0 +---00--1---- 0 +--1-0--1---- 0 +-1-0---1---- 0 +-11----1---- 0 +---0-1----0- 0 +--1--1----0- 0 +---001------ 0 +--1-01------ 0 +-1-0-1------ 0 +-11--1------ 0 +---------00- 0 +--------1-0- 0 +------1---0- 0 +----0----0-- 0 +-1-------0-- 0 +----0---1--- 0 +-1------1--- 0 +----0-1----- 0 +-1----1----- 0 +-----1----00 0 +----01-----0 0 +-1---1-----0 0 +0----------- 0 .names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D +--0--- 1 +-1---- 1 ----01 1 ---0-1 1 0----1 1 ---0--- 1 --1---- 1 10111- 0 -01--0 0 .names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ @@ -641,6 +536,80 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0---- 1 1-101 0 110-- 0 +.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ +inst_UDS_000_INT.D +-10- 1 +0--- 1 +--11 1 +100- 0 +1-10 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +-111- 1 +0---- 1 +-0--1 1 +11-0- 0 +110-- 0 +10--0 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF inst_VMA_INTreg.D +--0000-01 1 +-1----1-- 1 +-1------1 1 +-1-----0- 1 +-1---1--- 1 +-1--0---- 1 +-1-0----- 1 +-11------ 1 +0-------- 1 +1-0110010 0 +10---1--- 0 +101------ 0 +10-----1- 0 +10--1---- 0 +10-1----- 0 +10------0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1-1- 1 +-10-- 1 +0---- 1 +-0--1 1 +1110- 0 +10--0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \ +inst_RW_000_INT.D +---0-1-- 1 +-01-1--- 1 +-011---1 1 +--0--1-- 1 +-1---1-- 1 +------0- 1 +0------- 1 +10110-10 0 +1--0001- 0 +1-0--01- 0 +11---01- 0 +.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D +--1100 1 +-10--- 1 +0----- 1 +100--- 0 +1-1-1- 0 +1-10-- 0 +1-1--1 0 +.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D +1--011 1 +1-1--- 1 +-0---- 1 +-10-0- 0 +-101-- 0 +01---- 0 +-10--0 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -648,20 +617,6 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.D .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 1 0 -.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF SM_AMIGA_5_.BLIF \ -SM_AMIGA_0_.BLIF CLK_000_N_SYNC_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_226 ---00000000 1 --100-00000 1 -0-00-00000 1 -10--1----- 0 ---------1- 0 --------1-- 0 -------1--- 0 ------1---- 0 ----1------ 0 ---1------- 0 ----------1 0 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -699,11 +654,11 @@ AS_030.PIN.BLIF FPU_CS 0 0 .names AVEC 1 -.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_1_.BLIF E -010 1 -101 1 --00 0 -0-1 0 +.names cpu_est_3_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF E +100 1 +011 1 +0-0 0 +-01 0 11- 0 .names inst_VMA_INTreg.BLIF VMA 1 1 @@ -725,14 +680,12 @@ AMIGA_BUS_ENABLE_LOW 1- 1 -1 1 00 0 -.names CLK_000.BLIF inst_BGACK_030_INTreg.BLIF SM_AMIGA_0_.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH -111-- 1 --0-1- 1 --1--0 1 --0-0- 0 --10-1 0 -01--1 0 +.names inst_BGACK_030_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_HIGH +11- 1 +0-1 1 +10- 0 +0-0 0 .names A_DECODE_23_.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ @@ -805,194 +758,6 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C -1 1 -0 0 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C -1 1 -0 0 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C -1 1 -0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C -1 1 -0 0 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C -1 1 -0 0 -.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_12_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CYCLE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CYCLE_DMA_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SIZE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SIZE_DMA_1_.C -1 1 -0 0 -.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_.D -10 1 -01 1 -00 0 -11 0 -.names CLK_OSZI.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C -1 1 -0 0 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C -1 1 -0 0 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C -1 1 -0 0 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C -1 1 -0 0 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C -1 1 -0 0 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C -1 1 -0 0 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C -1 1 -0 0 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C -1 1 -0 0 -.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_10_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C -1 1 -0 0 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C -1 1 -0 0 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C -1 1 -0 0 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C -1 1 -0 0 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C -1 1 -0 0 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C -1 1 -0 0 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_0_.C -1 1 -0 0 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_1_.C -1 1 -0 0 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_2_.C -1 1 -0 0 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_3_.C -1 1 -0 0 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_4_.C -1 1 -0 0 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_5_.C -1 1 -0 0 .names CLK_000_D_5_.BLIF CLK_000_D_6_.D 1 1 0 0 @@ -1035,16 +800,22 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_D_12_.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C +.names CLK_OSZI.BLIF CYCLE_DMA_0_.C 1 1 0 0 -.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +.names CLK_OSZI.BLIF CYCLE_DMA_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C +.names CLK_OSZI.BLIF SIZE_DMA_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF RST_DLY_0_.C +.names CLK_OSZI.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_1_.C 1 1 0 0 .names CLK_OSZI.BLIF RST_DLY_1_.C @@ -1053,34 +824,43 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF RST_DLY_2_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_CLK_030_H.C +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 -.names CLK_OSZI.BLIF inst_RESET_OUT.C +.names CLK_OSZI.BLIF CLK_000_D_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D 1 1 0 0 -.names CLK_OSZI.BLIF inst_VMA_INTreg.C +.names CLK_OSZI.BLIF CLK_000_D_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_UDS_000_INT.C +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D 1 1 0 0 -.names CLK_OSZI.BLIF inst_A0_DMA.C +.names CLK_OSZI.BLIF CLK_000_D_2_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_RW_000_DMA.C +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D 1 1 0 0 -.names CLK_OSZI.BLIF inst_RW_000_INT.C +.names CLK_OSZI.BLIF CLK_000_D_3_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_LDS_000_INT.C +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D 1 1 0 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +.names CLK_OSZI.BLIF CLK_000_D_4_.C +1 1 +0 0 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_5_.C +1 1 +0 0 +.names CLK_OSZI.BLIF RST_DLY_0_.C 1 1 0 0 .names CLK_OSZI.BLIF inst_AS_000_DMA.C @@ -1107,6 +887,15 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_DTACK_D0.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RESET_OUT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 .names CLK_OSZI.BLIF BG_000DFFreg.C 1 1 0 0 @@ -1116,10 +905,25 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 0 0 -.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D +.names CLK_OSZI.BLIF inst_UDS_000_INT.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C +.names CLK_OSZI.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C @@ -1322,6 +1126,32 @@ AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE -00----------- 0 00------------ 0 -0-----------1 0 +.names cpu_est_2_.BLIF cpu_est_2_.D.X1 +1 1 +0 0 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF cpu_est_2_.D.X2 +11-10 1 +0---- 0 +-0--- 0 +---0- 0 +----1 0 +.names RST_DLY_1_.BLIF RST_DLY_1_.D.X1 +1 1 +0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_1_.D.X2 +11010- 1 +0---1- 1 +-10110 1 +10---- 0 +1-1--- 0 +1--0-- 0 +0---0- 0 +-0--0- 0 +--1-0- 0 +---00- 0 +1---11 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1 10 1 0- 0 @@ -1345,27 +1175,81 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2 0--010-00- 0 0--001-0-0 0 0--010-0-0 0 -.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1 +.names RST.BLIF SM_AMIGA_3_.BLIF BERR.PIN.BLIF SM_AMIGA_3_.D.X1 +111 1 +0-- 0 +-0- 0 +--0 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ +inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_3_.D.X2 +1------0-110- 1 +1------0-11-0 1 +10100001-0-11 1 +1-----1100-11 1 +0------------ 0 +-------1-1--- 0 +-------0-0--- 0 +-------0--0-- 0 +-------1---0- 0 +-------1----0 0 +-1----01----- 0 +--0---01----- 0 +---1--01----- 0 +----1-01----- 0 +-----101----- 0 +------111---- 0 +-------0---11 0 +.names RST.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X1 11 1 0- 0 -0 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ -CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_NE_D0.BLIF \ -SM_AMIGA_3_.BLIF BERR.PIN.BLIF SM_AMIGA_3_.D.X2 -1-------11-0- 1 -1----------10 1 -1001000--011- 1 -1-----10-011- 1 -0------------ 0 ---------0--0- 0 ----------0-0- 0 ----------1-11 0 -----------011 0 --1----0----11 0 ---1---0----11 0 ----0--0----11 0 -----1-0----11 0 ------10----11 0 -------11---11 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_VMA_INTreg.BLIF cpu_est_3_.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_VPA_D.BLIF CLK_000_D_1_.BLIF inst_DTACK_D0.BLIF CLK_000_D_0_.BLIF \ +CLK_000_D_2_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_1_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_i_7_.D.X2 +11-----0-0--100000000 1 +-1-------0-1-------10 1 +-1-------0-1---1----0 1 +-1-------0-1-1------0 1 +-1-------1-0----1---0 1 +-1-------1-0-----1--0 1 +-101000-01-0------1-0 1 +-1------1100------1-0 1 +01-----------00000001 1 +-1-----1-----00000001 1 +-1-------1---00000001 1 +-1----------000000001 1 +-1-------0-1-01000001 1 +-0------------------- 0 +-------------1------1 0 +---------------1----1 0 +----------------1---1 0 +-----------------1--1 0 +------------------1-1 0 +-------------------11 0 +---------0-0-1------- 0 +---------0-0---1----- 0 +---------0-0-------1- 0 +---------1----1-----1 0 +-----------0--1-----1 0 +---------1-1--------0 0 +---------0---0-01--0- 0 +---------0---0-0-1-0- 0 +---------0---0-0--10- 0 +---------1------000-0 0 +1------0-0--1-0-----1 0 +--1-----01------00--0 0 +---0----01------00--0 0 +----1---01------00--0 0 +-----1--01------00--0 0 +------1-01------00--0 0 +--------111-----00--0 0 +0--------0---0-0---00 0 +-------1-0---0-0---00 0 +---------0--00-0---00 0 +---------0---010---00 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index f4156fc..0261573 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Fri Aug 19 00:20:41 2016 +// Design '68030_tk' created Fri Aug 19 00:39:35 2016 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 221b8d3..2cbeac8 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Fri Aug 19 00:20:41 2016 +Design bus68030 created Fri Aug 19 00:39:35 2016 P-Terms Fan-in Fan-out Type Name (attributes) @@ -23,19 +23,6 @@ Design bus68030 created Fri Aug 19 00:20:41 2016 1 2 1 Pin LDS_000.OE 0 0 1 Pin BERR 1 9 1 Pin BERR.OE - 1 1 1 Pin CLK_DIV_OUT.D - 1 1 1 Pin CLK_DIV_OUT.C - 1 9 1 Pin FPU_CS- - 1 0 1 Pin AVEC - 2 3 1 Pin E - 0 0 1 Pin RESET - 1 1 1 Pin RESET.OE - 0 0 1 Pin AMIGA_ADDR_ENABLE - 2 4 1 Pin AMIGA_BUS_DATA_DIR - 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- - 3 5 1 Pin AMIGA_BUS_ENABLE_HIGH - 1 13 1 Pin CIIN - 1 1 1 Pin CIIN.OE 1 2 1 Pin SIZE_0_ 1 2 1 Pin SIZE_0_.OE 0 0 1 Pin AHIGH_30_ @@ -48,25 +35,31 @@ Design bus68030 created Fri Aug 19 00:20:41 2016 1 3 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ 1 3 1 Pin AHIGH_26_.OE + 1 1 1 Pin CLK_DIV_OUT.D + 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_25_ 1 3 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 3 1 Pin AHIGH_24_.OE + 1 9 1 Pin FPU_CS- + 1 0 1 Pin AVEC + 2 3 1 Pin E + 0 0 1 Pin RESET + 1 1 1 Pin RESET.OE + 0 0 1 Pin AMIGA_ADDR_ENABLE + 2 4 1 Pin AMIGA_BUS_DATA_DIR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- + 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE - 3 7 1 Pin RW_000.D- + 4 8 1 Pin RW_000.D- 1 1 1 Pin RW_000.C - 1 3 1 Pin A_0_.OE - 3 5 1 Pin A_0_.D - 1 1 1 Pin A_0_.C - 10 8 1 Pin IPL_030_1_.D- - 1 1 1 Pin IPL_030_1_.C - 10 8 1 Pin IPL_030_0_.D- - 1 1 1 Pin IPL_030_0_.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C - 3 5 1 Pin BGACK_030.D + 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C @@ -78,16 +71,23 @@ Design bus68030 created Fri Aug 19 00:20:41 2016 1 2 1 Pin RW.OE 2 5 1 Pin RW.D- 1 1 1 Pin RW.C - 3 10 1 Node N_226 - 4 4 1 Node cpu_est_2_.D - 1 1 1 Node cpu_est_2_.C - 3 5 1 Node cpu_est_3_.D + 1 3 1 Pin A_0_.OE + 3 5 1 Pin A_0_.D + 1 1 1 Pin A_0_.C + 10 8 1 Pin IPL_030_1_.D- + 1 1 1 Pin IPL_030_1_.C + 10 8 1 Pin IPL_030_0_.D- + 1 1 1 Pin IPL_030_0_.C + 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C - 2 2 1 Node cpu_est_0_.D + 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C - 3 4 1 Node cpu_est_1_.D + 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 2 5 1 Node inst_AS_000_INT.D- + 1 4 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 + 1 1 1 Node cpu_est_2_.C + 2 7 1 Node inst_AS_000_INT.D- 1 1 1 Node inst_AS_000_INT.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C @@ -101,9 +101,9 @@ Design bus68030 created Fri Aug 19 00:20:41 2016 1 1 1 Node inst_AS_000_DMA.C 9 12 1 Node inst_DS_000_DMA.D 1 1 1 Node inst_DS_000_DMA.C - 2 5 1 Node CYCLE_DMA_0_.D + 3 6 1 Node CYCLE_DMA_0_.D 1 1 1 Node CYCLE_DMA_0_.C - 3 6 1 Node CYCLE_DMA_1_.D + 4 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C 3 6 1 Node SIZE_DMA_0_.D- 1 1 1 Node SIZE_DMA_0_.C @@ -117,24 +117,20 @@ Design bus68030 created Fri Aug 19 00:20:41 2016 1 1 1 Node inst_LDS_000_INT.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 1 1 Node CLK_000_D_1_.D + 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_10_.D 1 1 1 Node CLK_000_D_10_.C 1 1 1 Node CLK_000_D_11_.D 1 1 1 Node CLK_000_D_11_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C - 2 6 1 Node inst_RESET_OUT.D + 2 7 1 Node inst_RESET_OUT.D 1 1 1 Node inst_RESET_OUT.C - 1 1 1 Node inst_CLK_OUT_PRE_50.D - 1 1 1 Node inst_CLK_OUT_PRE_50.C - 1 1 1 Node CLK_000_D_1_.D - 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C - 1 1 1 Node CLK_000_P_SYNC_10_.D - 1 1 1 Node CLK_000_P_SYNC_10_.C - 3 6 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C + 1 1 1 Node inst_CLK_OUT_PRE_50.D + 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 2 1 Node IPL_D0_0_.D- 1 1 1 Node IPL_D0_0_.C 1 2 1 Node IPL_D0_1_.D- @@ -159,85 +155,42 @@ Design bus68030 created Fri Aug 19 00:20:41 2016 1 1 1 Node CLK_000_D_9_.C 1 1 1 Node CLK_000_D_12_.D 1 1 1 Node CLK_000_D_12_.C - 2 6 1 Node SM_AMIGA_0_.D - 1 1 1 Node SM_AMIGA_0_.C - 1 2 1 Node CLK_000_N_SYNC_0_.D - 1 1 1 Node CLK_000_N_SYNC_0_.C - 3 6 1 Node SM_AMIGA_4_.D - 1 1 1 Node SM_AMIGA_4_.C - 5 11 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C - 1 1 1 Node CLK_000_N_SYNC_12_.D - 1 1 1 Node CLK_000_N_SYNC_12_.C - 3 5 1 Node RST_DLY_0_.D - 1 1 1 Node RST_DLY_0_.C - 4 5 1 Node RST_DLY_1_.D - 1 1 1 Node RST_DLY_1_.C - 2 5 1 Node RST_DLY_2_.D - 1 1 1 Node RST_DLY_2_.C - 1 2 1 Node CLK_000_P_SYNC_0_.D - 1 1 1 Node CLK_000_P_SYNC_0_.C - 1 1 1 Node CLK_000_P_SYNC_1_.D - 1 1 1 Node CLK_000_P_SYNC_1_.C - 1 1 1 Node CLK_000_P_SYNC_2_.D - 1 1 1 Node CLK_000_P_SYNC_2_.C - 1 1 1 Node CLK_000_P_SYNC_3_.D - 1 1 1 Node CLK_000_P_SYNC_3_.C - 1 1 1 Node CLK_000_P_SYNC_4_.D - 1 1 1 Node CLK_000_P_SYNC_4_.C - 1 1 1 Node CLK_000_P_SYNC_5_.D - 1 1 1 Node CLK_000_P_SYNC_5_.C - 1 1 1 Node CLK_000_P_SYNC_6_.D - 1 1 1 Node CLK_000_P_SYNC_6_.C - 1 1 1 Node CLK_000_P_SYNC_7_.D - 1 1 1 Node CLK_000_P_SYNC_7_.C - 1 1 1 Node CLK_000_P_SYNC_8_.D - 1 1 1 Node CLK_000_P_SYNC_8_.C - 1 1 1 Node CLK_000_P_SYNC_9_.D - 1 1 1 Node CLK_000_P_SYNC_9_.C - 1 1 1 Node CLK_000_N_SYNC_1_.D - 1 1 1 Node CLK_000_N_SYNC_1_.C - 1 1 1 Node CLK_000_N_SYNC_2_.D - 1 1 1 Node CLK_000_N_SYNC_2_.C - 1 1 1 Node CLK_000_N_SYNC_3_.D - 1 1 1 Node CLK_000_N_SYNC_3_.C - 1 1 1 Node CLK_000_N_SYNC_4_.D - 1 1 1 Node CLK_000_N_SYNC_4_.C - 1 1 1 Node CLK_000_N_SYNC_5_.D - 1 1 1 Node CLK_000_N_SYNC_5_.C - 1 1 1 Node CLK_000_N_SYNC_6_.D - 1 1 1 Node CLK_000_N_SYNC_6_.C - 1 1 1 Node CLK_000_N_SYNC_7_.D - 1 1 1 Node CLK_000_N_SYNC_7_.C - 1 1 1 Node CLK_000_N_SYNC_8_.D - 1 1 1 Node CLK_000_N_SYNC_8_.C - 1 1 1 Node CLK_000_N_SYNC_9_.D - 1 1 1 Node CLK_000_N_SYNC_9_.C - 1 1 1 Node CLK_000_N_SYNC_10_.D - 1 1 1 Node CLK_000_N_SYNC_10_.C - 1 1 1 Node CLK_000_N_SYNC_11_.D - 1 1 1 Node CLK_000_N_SYNC_11_.C - 1 1 1 Node inst_CLK_000_NE_D0.D - 1 1 1 Node inst_CLK_000_NE_D0.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 3 8 1 Node SM_AMIGA_6_.D + 4 12 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C + 3 6 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 3 6 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C + 4 6 1 Node RST_DLY_0_.D + 1 1 1 Node RST_DLY_0_.C + 2 6 1 NodeX1 RST_DLY_1_.D.X1 + 1 2 1 NodeX2 RST_DLY_1_.D.X2 + 1 1 1 Node RST_DLY_1_.C + 2 6 1 Node RST_DLY_2_.D + 1 1 1 Node RST_DLY_2_.C 8 10 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C 3 6 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C - 5 13 1 Node SM_AMIGA_3_.T + 3 6 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C + 4 13 1 NodeX1 SM_AMIGA_3_.D.X1 + 1 3 1 NodeX2 SM_AMIGA_3_.D.X2 1 1 1 Node SM_AMIGA_3_.C 4 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C - 14 20 1 Node SM_AMIGA_i_7_.D + 13 21 1 NodeX1 SM_AMIGA_i_7_.D.X1 + 1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 351 P-Term Total: 351 + 301 P-Term Total: 301 Total Pins: 61 - Total Nodes: 79 + Total Nodes: 53 Average P-Term/Output: 2 @@ -275,36 +228,6 @@ BERR = (0); BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_DIV_OUT.C = (CLK_OSZI); - -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); - -AVEC = (1); - -E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q); - -RESET = (0); - -RESET.OE = (!inst_RESET_OUT.Q); - -AMIGA_ADDR_ENABLE = (0); - -AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN - # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); - -!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); - -AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q - # BGACK_030.Q & !SM_AMIGA_i_7_.Q - # CLK_000 & BGACK_030.Q & SM_AMIGA_0_.Q); - -CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); - -CIIN.OE = (CIIN_0); - SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); @@ -329,6 +252,10 @@ AHIGH_26_ = (0); AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_DIV_OUT.C = (CLK_OSZI); + AHIGH_25_ = (0); AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -337,6 +264,31 @@ AHIGH_24_ = (0); AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); + +AVEC = (1); + +E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q); + +RESET = (0); + +RESET.OE = (!inst_RESET_OUT.Q); + +AMIGA_ADDR_ENABLE = (0); + +AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN + # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); + +!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); + +AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & inst_AS_030_000_SYNC.Q + # !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); + +CIIN.OE = (CIIN_0); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -352,12 +304,50 @@ IPL_030_2_.C = (CLK_OSZI); RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); -!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN - # RST & !CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); +!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); RW_000.C = (CLK_OSZI); +!BG_000.D = (!BG_030 & RST & !BG_000.Q + # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); + +BG_000.C = (CLK_OSZI); + +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN); + +BGACK_030.C = (CLK_OSZI); + +CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_EXP.C = (CLK_OSZI); + +DSACK1.OE = (nEXP_SPACE); + +!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q + # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN + # !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q + # RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q); + +DSACK1.C = (CLK_OSZI); + +VMA.T = (!RST & !VMA.Q + # !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q + # RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +VMA.C = (CLK_OSZI); + +RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); + +!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); + +RW.C = (CLK_OSZI); + A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); A_0_.D = (!RST @@ -392,72 +382,33 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -!BG_000.D = (!BG_030 & RST & !BG_000.Q - # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); - -BG_000.C = (CLK_OSZI); - -BGACK_030.D = (!RST - # BGACK_000 & BGACK_030.Q - # BGACK_000 & CLK_000_P_SYNC_10_.Q & AS_000.PIN); - -BGACK_030.C = (CLK_OSZI); - -CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_EXP.C = (CLK_OSZI); - -DSACK1.OE = (nEXP_SPACE); - -!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q - # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN - # !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q - # RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q); - -DSACK1.C = (CLK_OSZI); - -VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_P_SYNC_10_.Q - # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_N_SYNC_12_.Q); - -VMA.C = (CLK_OSZI); - -RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); - -!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); - -RW.C = (CLK_OSZI); - -N_226 = (!nEXP_SPACE & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # inst_AS_030_000_SYNC.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !CLK_000_N_SYNC_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); - -cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q - # cpu_est_2_.Q & !cpu_est_1_.Q - # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q - # !cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); - -cpu_est_2_.C = (CLK_OSZI); - -cpu_est_3_.D = (cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q - # cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); +cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q + # cpu_est_3_.Q & CLK_000_D_0_.Q + # cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q + # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_3_.C = (CLK_OSZI); -cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q - # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); +cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q + # cpu_est_0_.Q & CLK_000_D_0_.Q + # !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q - # cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q - # !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); + # cpu_est_1_.Q & !CLK_000_D_1_.Q + # cpu_est_1_.Q & CLK_000_D_0_.Q + # !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_1_.C = (CLK_OSZI); -!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q +cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN); inst_AS_000_INT.C = (CLK_OSZI); @@ -507,14 +458,16 @@ inst_DS_000_DMA.D = (!RST inst_DS_000_DMA.C = (CLK_OSZI); -CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN); +CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CLK_000_D_1_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_D_0_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN); CYCLE_DMA_0_.C = (CLK_OSZI); CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN); + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & CLK_000_D_1_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_D_0_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN); CYCLE_DMA_1_.C = (CLK_OSZI); @@ -549,6 +502,10 @@ inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); +CLK_000_D_1_.D = (CLK_000_D_0_.Q); + +CLK_000_D_1_.C = (CLK_OSZI); + CLK_000_D_10_.D = (CLK_000_D_9_.Q); CLK_000_D_10_.C = (CLK_OSZI); @@ -562,31 +519,17 @@ CLK_000_D_11_.C = (CLK_OSZI); inst_DTACK_D0.C = (CLK_OSZI); inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q - # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); inst_RESET_OUT.C = (CLK_OSZI); -inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); - -inst_CLK_OUT_PRE_50.C = (CLK_OSZI); - -CLK_000_D_1_.D = (CLK_000_D_0_.Q); - -CLK_000_D_1_.C = (CLK_OSZI); - CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); -CLK_000_P_SYNC_10_.D = (CLK_000_P_SYNC_9_.Q); +inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); -CLK_000_P_SYNC_10_.C = (CLK_OSZI); - -SM_AMIGA_5_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_6_.Q - # RST & SM_AMIGA_5_.Q & !CLK_000_N_SYNC_12_.Q & BERR.PIN - # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); - -SM_AMIGA_5_.C = (CLK_OSZI); +inst_CLK_OUT_PRE_50.C = (CLK_OSZI); !IPL_D0_0_.D = (RST & !IPL_0_); @@ -636,150 +579,55 @@ CLK_000_D_12_.D = (CLK_000_D_11_.Q); CLK_000_D_12_.C = (CLK_OSZI); -SM_AMIGA_0_.D = (RST & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_0_.Q & BERR.PIN); - -SM_AMIGA_0_.C = (CLK_OSZI); - -CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -CLK_000_N_SYNC_0_.C = (CLK_OSZI); - -SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q - # RST & SM_AMIGA_5_.Q & CLK_000_N_SYNC_12_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & BERR.PIN); - -SM_AMIGA_4_.C = (CLK_OSZI); - -inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN - # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q - # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN - # RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN); - -inst_DS_000_ENABLE.C = (CLK_OSZI); - -CLK_000_N_SYNC_12_.D = (CLK_000_N_SYNC_11_.Q); - -CLK_000_N_SYNC_12_.C = (CLK_OSZI); - -RST_DLY_0_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q - # RST & CLK_000_N_SYNC_12_.Q & !RST_DLY_0_.Q - # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); - -RST_DLY_0_.C = (CLK_OSZI); - -RST_DLY_1_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_1_.Q - # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q - # RST & RST_DLY_1_.Q & RST_DLY_2_.Q - # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q); - -RST_DLY_1_.C = (CLK_OSZI); - -RST_DLY_2_.D = (RST & RST_DLY_2_.Q - # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); - -RST_DLY_2_.C = (CLK_OSZI); - -CLK_000_P_SYNC_0_.D = (!CLK_000_D_1_.Q & CLK_000_D_0_.Q); - -CLK_000_P_SYNC_0_.C = (CLK_OSZI); - -CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); - -CLK_000_P_SYNC_1_.C = (CLK_OSZI); - -CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); - -CLK_000_P_SYNC_2_.C = (CLK_OSZI); - -CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); - -CLK_000_P_SYNC_3_.C = (CLK_OSZI); - -CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); - -CLK_000_P_SYNC_4_.C = (CLK_OSZI); - -CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); - -CLK_000_P_SYNC_5_.C = (CLK_OSZI); - -CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); - -CLK_000_P_SYNC_6_.C = (CLK_OSZI); - -CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); - -CLK_000_P_SYNC_7_.C = (CLK_OSZI); - -CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); - -CLK_000_P_SYNC_8_.C = (CLK_OSZI); - -CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); - -CLK_000_P_SYNC_9_.C = (CLK_OSZI); - -CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); - -CLK_000_N_SYNC_1_.C = (CLK_OSZI); - -CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); - -CLK_000_N_SYNC_2_.C = (CLK_OSZI); - -CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); - -CLK_000_N_SYNC_3_.C = (CLK_OSZI); - -CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); - -CLK_000_N_SYNC_4_.C = (CLK_OSZI); - -CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); - -CLK_000_N_SYNC_5_.C = (CLK_OSZI); - -CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); - -CLK_000_N_SYNC_6_.C = (CLK_OSZI); - -CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); - -CLK_000_N_SYNC_7_.C = (CLK_OSZI); - -CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); - -CLK_000_N_SYNC_8_.C = (CLK_OSZI); - -CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); - -CLK_000_N_SYNC_9_.C = (CLK_OSZI); - -CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); - -CLK_000_N_SYNC_10_.C = (CLK_OSZI); - -CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); - -CLK_000_N_SYNC_11_.C = (CLK_OSZI); - -inst_CLK_000_NE_D0.D = (CLK_000_N_SYNC_12_.Q); - -inst_CLK_000_NE_D0.C = (CLK_OSZI); - !inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); -SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_6_.Q & BERR.PIN - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_N_SYNC_0_.Q & !SM_AMIGA_i_7_.Q); +inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN + # RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); +SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q + # RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN); + +SM_AMIGA_0_.C = (CLK_OSZI); + +SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q + # RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q & BERR.PIN); + +SM_AMIGA_4_.C = (CLK_OSZI); + +RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q + # RST & CLK_000_D_0_.Q & RST_DLY_0_.Q + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q + # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); + +RST_DLY_0_.C = (CLK_OSZI); + +RST_DLY_1_.D.X1 = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_2_.Q); + +RST_DLY_1_.D.X2 = (RST & RST_DLY_1_.Q); + +RST_DLY_1_.C = (CLK_OSZI); + +RST_DLY_2_.D = (RST & RST_DLY_2_.Q + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); + +RST_DLY_2_.C = (CLK_OSZI); + inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN @@ -791,41 +639,49 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); -SM_AMIGA_1_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q & BERR.PIN - # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN); +SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN + # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN); SM_AMIGA_1_.C = (CLK_OSZI); -SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q - # SM_AMIGA_3_.Q & !BERR.PIN - # RST & CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q - # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); +SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q + # RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q & BERR.PIN + # RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q & BERR.PIN); + +SM_AMIGA_5_.C = (CLK_OSZI); + +SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN + # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN); + +SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN); SM_AMIGA_3_.C = (CLK_OSZI); -SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_2_.Q & BERR.PIN - # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q - # RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); +SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_i_7_.D = (RST & !N_226 & !CLK_000_P_SYNC_10_.Q & BERR.PIN - # RST & !N_226 & !SM_AMIGA_0_.Q & BERR.PIN - # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_3_.Q - # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q - # RST & !N_226 & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q - # RST & !N_226 & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); +SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !BERR.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !BERR.PIN + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q & !BERR.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN + # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN); + +SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN); SM_AMIGA_i_7_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index b7a3320..24156ef 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -6,7 +6,7 @@ DATA LOCATION AHIGH_24_:C_8_19 // IO DATA LOCATION AHIGH_25_:C_12_18 // IO DATA LOCATION AHIGH_26_:C_5_17 // IO -DATA LOCATION AHIGH_27_:C_4_16 // IO +DATA LOCATION AHIGH_27_:C_9_16 // IO DATA LOCATION AHIGH_28_:C_0_15 // IO DATA LOCATION AHIGH_29_:B_13_6 // IO DATA LOCATION AHIGH_30_:B_0_5 // IO @@ -30,128 +30,102 @@ DATA LOCATION A_DECODE_22_:H_*_84 // INP DATA LOCATION A_DECODE_23_:H_*_85 // INP DATA LOCATION BERR:E_0_41 // IO DATA LOCATION BGACK_000:D_*_28 // INP -DATA LOCATION BGACK_030:H_6_83 // IO {RN_BGACK_030} +DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CIIN_0:E_10 // NOD DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_D_0_:G_13 // NOD -DATA LOCATION CLK_000_D_10_:G_15 // NOD -DATA LOCATION CLK_000_D_11_:H_10 // NOD -DATA LOCATION CLK_000_D_12_:H_2 // NOD -DATA LOCATION CLK_000_D_1_:C_6 // NOD -DATA LOCATION CLK_000_D_2_:G_11 // NOD -DATA LOCATION CLK_000_D_3_:G_7 // NOD +DATA LOCATION CLK_000_D_0_:C_13 // NOD +DATA LOCATION CLK_000_D_10_:C_14 // NOD +DATA LOCATION CLK_000_D_11_:H_0 // NOD +DATA LOCATION CLK_000_D_12_:G_14 // NOD +DATA LOCATION CLK_000_D_1_:H_3 // NOD +DATA LOCATION CLK_000_D_2_:E_2 // NOD +DATA LOCATION CLK_000_D_3_:E_9 // NOD DATA LOCATION CLK_000_D_4_:C_11 // NOD -DATA LOCATION CLK_000_D_5_:E_13 // NOD -DATA LOCATION CLK_000_D_6_:B_11 // NOD -DATA LOCATION CLK_000_D_7_:G_3 // NOD -DATA LOCATION CLK_000_D_8_:B_7 // NOD -DATA LOCATION CLK_000_D_9_:D_11 // NOD -DATA LOCATION CLK_000_N_SYNC_0_:D_2 // NOD -DATA LOCATION CLK_000_N_SYNC_10_:C_14 // NOD -DATA LOCATION CLK_000_N_SYNC_11_:C_10 // NOD -DATA LOCATION CLK_000_N_SYNC_12_:D_13 // NOD -DATA LOCATION CLK_000_N_SYNC_1_:E_9 // NOD -DATA LOCATION CLK_000_N_SYNC_2_:A_3 // NOD -DATA LOCATION CLK_000_N_SYNC_3_:F_7 // NOD -DATA LOCATION CLK_000_N_SYNC_4_:A_14 // NOD -DATA LOCATION CLK_000_N_SYNC_5_:A_6 // NOD -DATA LOCATION CLK_000_N_SYNC_6_:B_3 // NOD -DATA LOCATION CLK_000_N_SYNC_7_:G_6 // NOD -DATA LOCATION CLK_000_N_SYNC_8_:B_14 // NOD -DATA LOCATION CLK_000_N_SYNC_9_:F_3 // NOD -DATA LOCATION CLK_000_P_SYNC_0_:D_7 // NOD -DATA LOCATION CLK_000_P_SYNC_10_:A_8 // NOD -DATA LOCATION CLK_000_P_SYNC_1_:A_15 // NOD -DATA LOCATION CLK_000_P_SYNC_2_:F_11 // NOD -DATA LOCATION CLK_000_P_SYNC_3_:C_7 // NOD -DATA LOCATION CLK_000_P_SYNC_4_:A_11 // NOD -DATA LOCATION CLK_000_P_SYNC_5_:G_14 // NOD -DATA LOCATION CLK_000_P_SYNC_6_:G_10 // NOD -DATA LOCATION CLK_000_P_SYNC_7_:D_3 // NOD -DATA LOCATION CLK_000_P_SYNC_8_:A_7 // NOD -DATA LOCATION CLK_000_P_SYNC_9_:C_3 // NOD +DATA LOCATION CLK_000_D_5_:E_5 // NOD +DATA LOCATION CLK_000_D_6_:D_14 // NOD +DATA LOCATION CLK_000_D_7_:A_14 // NOD +DATA LOCATION CLK_000_D_8_:G_3 // NOD +DATA LOCATION CLK_000_D_9_:A_10 // NOD DATA LOCATION CLK_030:*_*_64 // INP DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CYCLE_DMA_0_:A_10 // NOD -DATA LOCATION CYCLE_DMA_1_:A_2 // NOD +DATA LOCATION CYCLE_DMA_0_:A_13 // NOD +DATA LOCATION CYCLE_DMA_1_:A_9 // NOD DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1} DATA LOCATION DS_030:A_0_98 // OUT DATA LOCATION DTACK:D_*_30 // INP DATA LOCATION E:G_4_66 // OUT DATA LOCATION FC_0_:F_*_57 // INP DATA LOCATION FC_1_:F_*_58 // INP -DATA LOCATION FPU_CS:H_4_78 // OUT +DATA LOCATION FPU_CS:H_5_78 // OUT DATA LOCATION FPU_SENSE:A_*_91 // INP -DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_} +DATA LOCATION IPL_030_0_:B_5_8 // IO {RN_IPL_030_0_} DATA LOCATION IPL_030_1_:B_9_7 // IO {RN_IPL_030_1_} DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:D_15 // NOD -DATA LOCATION IPL_D0_1_:F_15 // NOD -DATA LOCATION IPL_D0_2_:B_15 // NOD +DATA LOCATION IPL_D0_0_:B_3 // NOD +DATA LOCATION IPL_D0_1_:B_14 // NOD +DATA LOCATION IPL_D0_2_:A_3 // NOD DATA LOCATION LDS_000:D_12_31 // IO -DATA LOCATION N_226:F_14 // NOD -DATA LOCATION RESET:B_5_3 // OUT +DATA LOCATION RESET:B_2_3 // OUT DATA LOCATION RN_A_0_:G_8 // NOD {A_0_} -DATA LOCATION RN_BGACK_030:H_6 // NOD {BGACK_030} +DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1} -DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} +DATA LOCATION RN_IPL_030_0_:B_5 // NOD {IPL_030_0_} DATA LOCATION RN_IPL_030_1_:B_9 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} DATA LOCATION RN_RW:G_0 // NOD {RW} -DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} +DATA LOCATION RN_RW_000:H_1 // NOD {RW_000} DATA LOCATION RN_VMA:D_0 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RST_DLY_0_:D_10 // NOD -DATA LOCATION RST_DLY_1_:D_6 // NOD -DATA LOCATION RST_DLY_2_:D_14 // NOD +DATA LOCATION RST_DLY_0_:F_0 // NOD +DATA LOCATION RST_DLY_1_:F_13 // NOD +DATA LOCATION RST_DLY_2_:F_9 // NOD DATA LOCATION RW:G_0_71 // IO {RN_RW} -DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} +DATA LOCATION RW_000:H_1_80 // IO {RN_RW_000} DATA LOCATION SIZE_0_:G_12_70 // IO DATA LOCATION SIZE_1_:H_12_79 // IO -DATA LOCATION SIZE_DMA_0_:G_9 // NOD -DATA LOCATION SIZE_DMA_1_:G_5 // NOD -DATA LOCATION SM_AMIGA_0_:F_5 // NOD -DATA LOCATION SM_AMIGA_1_:F_13 // NOD +DATA LOCATION SIZE_DMA_0_:G_2 // NOD +DATA LOCATION SIZE_DMA_1_:G_9 // NOD +DATA LOCATION SM_AMIGA_0_:G_5 // NOD +DATA LOCATION SM_AMIGA_1_:F_1 // NOD DATA LOCATION SM_AMIGA_2_:F_6 // NOD -DATA LOCATION SM_AMIGA_3_:F_2 // NOD -DATA LOCATION SM_AMIGA_4_:F_10 // NOD -DATA LOCATION SM_AMIGA_5_:F_8 // NOD -DATA LOCATION SM_AMIGA_6_:C_9 // NOD -DATA LOCATION SM_AMIGA_i_7_:F_0 // NOD +DATA LOCATION SM_AMIGA_3_:F_10 // NOD +DATA LOCATION SM_AMIGA_4_:B_10 // NOD +DATA LOCATION SM_AMIGA_5_:F_5 // NOD +DATA LOCATION SM_AMIGA_6_:C_2 // NOD +DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:B_2 // NOD -DATA LOCATION cpu_est_1_:F_12 // NOD -DATA LOCATION cpu_est_2_:F_4 // NOD -DATA LOCATION cpu_est_3_:F_1 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_2 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_10 // NOD +DATA LOCATION cpu_est_0_:D_2 // NOD +DATA LOCATION cpu_est_1_:F_8 // NOD +DATA LOCATION cpu_est_2_:D_13 // NOD +DATA LOCATION cpu_est_3_:D_9 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_6 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_10 // NOD DATA LOCATION inst_AS_000_DMA:A_12 // NOD -DATA LOCATION inst_AS_000_INT:G_2 // NOD -DATA LOCATION inst_AS_030_000_SYNC:C_13 // NOD -DATA LOCATION inst_AS_030_D0:H_1 // NOD +DATA LOCATION inst_AS_000_INT:C_15 // NOD +DATA LOCATION inst_AS_030_000_SYNC:C_6 // NOD +DATA LOCATION inst_AS_030_D0:A_6 // NOD DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD -DATA LOCATION inst_CLK_000_NE_D0:E_5 // NOD -DATA LOCATION inst_CLK_030_H:A_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:E_2 // NOD +DATA LOCATION inst_CLK_030_H:A_5 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:E_6 // NOD DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD -DATA LOCATION inst_DS_000_DMA:A_9 // NOD -DATA LOCATION inst_DS_000_ENABLE:F_9 // NOD -DATA LOCATION inst_DTACK_D0:C_15 // NOD -DATA LOCATION inst_LDS_000_INT:A_1 // NOD -DATA LOCATION inst_RESET_OUT:D_9 // NOD -DATA LOCATION inst_UDS_000_INT:B_6 // NOD -DATA LOCATION inst_VPA_D:A_5 // NOD +DATA LOCATION inst_DS_000_DMA:A_1 // NOD +DATA LOCATION inst_DS_000_ENABLE:B_6 // NOD +DATA LOCATION inst_DTACK_D0:G_7 // NOD +DATA LOCATION inst_LDS_000_INT:D_6 // NOD +DATA LOCATION inst_RESET_OUT:A_8 // NOD +DATA LOCATION inst_UDS_000_INT:D_10 // NOD +DATA LOCATION inst_VPA_D:F_2 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AHIGH_24_:BI DATA IO_DIR AHIGH_25_:BI @@ -215,26 +189,12 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL A_DECODE_22_:1 -DATA SLEW A_DECODE_22_:1 -DATA PW_LEVEL A_DECODE_21_:1 -DATA SLEW A_DECODE_21_:1 DATA PW_LEVEL SIZE_1_:1 DATA SLEW SIZE_1_:1 -DATA PW_LEVEL A_DECODE_20_:1 -DATA SLEW A_DECODE_20_:1 -DATA PW_LEVEL A_DECODE_19_:1 -DATA SLEW A_DECODE_19_:1 DATA PW_LEVEL AHIGH_31_:1 DATA SLEW AHIGH_31_:1 -DATA PW_LEVEL A_DECODE_18_:1 -DATA SLEW A_DECODE_18_:1 -DATA PW_LEVEL A_DECODE_17_:1 -DATA SLEW A_DECODE_17_:1 DATA PW_LEVEL A_DECODE_23_:1 DATA SLEW A_DECODE_23_:1 -DATA PW_LEVEL A_DECODE_16_:1 -DATA SLEW A_DECODE_16_:1 DATA PW_LEVEL IPL_2_:1 DATA SLEW IPL_2_:1 DATA PW_LEVEL FC_1_:1 @@ -254,32 +214,54 @@ DATA PW_LEVEL BERR:1 DATA SLEW BERR:1 DATA PW_LEVEL BG_030:1 DATA SLEW BG_030:1 -DATA PW_LEVEL IPL_1_:1 -DATA SLEW IPL_1_:1 -DATA PW_LEVEL IPL_0_:1 -DATA SLEW IPL_0_:1 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:1 +DATA PW_LEVEL AHIGH_30_:1 +DATA SLEW AHIGH_30_:1 DATA PW_LEVEL BGACK_000:1 DATA SLEW BGACK_000:1 -DATA PW_LEVEL FC_0_:1 -DATA SLEW FC_0_:1 +DATA PW_LEVEL AHIGH_29_:1 +DATA SLEW AHIGH_29_:1 DATA SLEW CLK_030:1 -DATA PW_LEVEL A_1_:1 -DATA SLEW A_1_:1 +DATA PW_LEVEL AHIGH_28_:1 +DATA SLEW AHIGH_28_:1 DATA SLEW CLK_000:1 +DATA PW_LEVEL AHIGH_27_:1 +DATA SLEW AHIGH_27_:1 DATA SLEW CLK_OSZI:1 +DATA PW_LEVEL AHIGH_26_:1 +DATA SLEW AHIGH_26_:1 DATA PW_LEVEL CLK_DIV_OUT:1 DATA SLEW CLK_DIV_OUT:0 +DATA PW_LEVEL AHIGH_25_:1 +DATA SLEW AHIGH_25_:1 +DATA PW_LEVEL AHIGH_24_:1 +DATA SLEW AHIGH_24_:1 DATA PW_LEVEL FPU_CS:1 DATA SLEW FPU_CS:0 +DATA PW_LEVEL A_DECODE_22_:1 +DATA SLEW A_DECODE_22_:1 DATA PW_LEVEL FPU_SENSE:1 DATA SLEW FPU_SENSE:1 +DATA PW_LEVEL A_DECODE_21_:1 +DATA SLEW A_DECODE_21_:1 +DATA PW_LEVEL A_DECODE_20_:1 +DATA SLEW A_DECODE_20_:1 DATA PW_LEVEL DTACK:1 DATA SLEW DTACK:1 +DATA PW_LEVEL A_DECODE_19_:1 +DATA SLEW A_DECODE_19_:1 DATA PW_LEVEL AVEC:1 DATA SLEW AVEC:1 +DATA PW_LEVEL A_DECODE_18_:1 +DATA SLEW A_DECODE_18_:1 DATA PW_LEVEL E:1 DATA SLEW E:1 +DATA PW_LEVEL A_DECODE_17_:1 +DATA SLEW A_DECODE_17_:1 DATA SLEW VPA:1 +DATA PW_LEVEL A_DECODE_16_:1 +DATA SLEW A_DECODE_16_:1 DATA SLEW RST:1 DATA PW_LEVEL RESET:1 DATA SLEW RESET:1 @@ -293,32 +275,18 @@ DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 DATA PW_LEVEL CIIN:1 DATA SLEW CIIN:1 -DATA PW_LEVEL SIZE_0_:1 -DATA SLEW SIZE_0_:1 -DATA PW_LEVEL AHIGH_30_:1 -DATA SLEW AHIGH_30_:1 -DATA PW_LEVEL AHIGH_29_:1 -DATA SLEW AHIGH_29_:1 -DATA PW_LEVEL AHIGH_28_:1 -DATA SLEW AHIGH_28_:1 -DATA PW_LEVEL AHIGH_27_:1 -DATA SLEW AHIGH_27_:1 -DATA PW_LEVEL AHIGH_26_:1 -DATA SLEW AHIGH_26_:1 -DATA PW_LEVEL AHIGH_25_:1 -DATA SLEW AHIGH_25_:1 -DATA PW_LEVEL AHIGH_24_:1 -DATA SLEW AHIGH_24_:1 +DATA PW_LEVEL IPL_1_:1 +DATA SLEW IPL_1_:1 +DATA PW_LEVEL IPL_0_:1 +DATA SLEW IPL_0_:1 +DATA PW_LEVEL FC_0_:1 +DATA SLEW FC_0_:1 +DATA PW_LEVEL A_1_:1 +DATA SLEW A_1_:1 DATA PW_LEVEL IPL_030_2_:1 DATA SLEW IPL_030_2_:1 DATA PW_LEVEL RW_000:1 DATA SLEW RW_000:1 -DATA PW_LEVEL A_0_:1 -DATA SLEW A_0_:1 -DATA PW_LEVEL IPL_030_1_:1 -DATA SLEW IPL_030_1_:1 -DATA PW_LEVEL IPL_030_0_:1 -DATA SLEW IPL_030_0_:1 DATA PW_LEVEL BG_000:1 DATA SLEW BG_000:1 DATA PW_LEVEL BGACK_030:1 @@ -331,16 +299,20 @@ DATA PW_LEVEL VMA:1 DATA SLEW VMA:1 DATA PW_LEVEL RW:1 DATA SLEW RW:1 -DATA PW_LEVEL N_226:1 -DATA SLEW N_226:1 -DATA PW_LEVEL cpu_est_2_:1 -DATA SLEW cpu_est_2_:1 +DATA PW_LEVEL A_0_:1 +DATA SLEW A_0_:1 +DATA PW_LEVEL IPL_030_1_:1 +DATA SLEW IPL_030_1_:1 +DATA PW_LEVEL IPL_030_0_:1 +DATA SLEW IPL_030_0_:1 DATA PW_LEVEL cpu_est_3_:1 DATA SLEW cpu_est_3_:1 DATA PW_LEVEL cpu_est_0_:1 DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:1 DATA SLEW cpu_est_1_:1 +DATA PW_LEVEL cpu_est_2_:1 +DATA SLEW cpu_est_2_:1 DATA PW_LEVEL inst_AS_000_INT:1 DATA SLEW inst_AS_000_INT:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1 @@ -371,6 +343,8 @@ DATA PW_LEVEL inst_LDS_000_INT:1 DATA SLEW inst_LDS_000_INT:1 DATA PW_LEVEL inst_CLK_OUT_PRE_D:1 DATA SLEW inst_CLK_OUT_PRE_D:1 +DATA PW_LEVEL CLK_000_D_1_:1 +DATA SLEW CLK_000_D_1_:1 DATA PW_LEVEL CLK_000_D_10_:1 DATA SLEW CLK_000_D_10_:1 DATA PW_LEVEL CLK_000_D_11_:1 @@ -379,16 +353,10 @@ DATA PW_LEVEL inst_DTACK_D0:1 DATA SLEW inst_DTACK_D0:1 DATA PW_LEVEL inst_RESET_OUT:1 DATA SLEW inst_RESET_OUT:1 -DATA PW_LEVEL inst_CLK_OUT_PRE_50:1 -DATA SLEW inst_CLK_OUT_PRE_50:1 -DATA PW_LEVEL CLK_000_D_1_:1 -DATA SLEW CLK_000_D_1_:1 DATA PW_LEVEL CLK_000_D_0_:1 DATA SLEW CLK_000_D_0_:1 -DATA PW_LEVEL CLK_000_P_SYNC_10_:1 -DATA SLEW CLK_000_P_SYNC_10_:1 -DATA PW_LEVEL SM_AMIGA_5_:1 -DATA SLEW SM_AMIGA_5_:1 +DATA PW_LEVEL inst_CLK_OUT_PRE_50:1 +DATA SLEW inst_CLK_OUT_PRE_50:1 DATA PW_LEVEL IPL_D0_0_:1 DATA SLEW IPL_D0_0_:1 DATA PW_LEVEL IPL_D0_1_:1 @@ -413,74 +381,28 @@ DATA PW_LEVEL CLK_000_D_9_:1 DATA SLEW CLK_000_D_9_:1 DATA PW_LEVEL CLK_000_D_12_:1 DATA SLEW CLK_000_D_12_:1 -DATA PW_LEVEL SM_AMIGA_0_:1 -DATA SLEW SM_AMIGA_0_:1 -DATA PW_LEVEL CLK_000_N_SYNC_0_:1 -DATA SLEW CLK_000_N_SYNC_0_:1 -DATA PW_LEVEL SM_AMIGA_4_:1 -DATA SLEW SM_AMIGA_4_:1 +DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 +DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 DATA PW_LEVEL inst_DS_000_ENABLE:1 DATA SLEW inst_DS_000_ENABLE:1 -DATA PW_LEVEL CLK_000_N_SYNC_12_:1 -DATA SLEW CLK_000_N_SYNC_12_:1 +DATA PW_LEVEL SM_AMIGA_6_:1 +DATA SLEW SM_AMIGA_6_:1 +DATA PW_LEVEL SM_AMIGA_0_:1 +DATA SLEW SM_AMIGA_0_:1 +DATA PW_LEVEL SM_AMIGA_4_:1 +DATA SLEW SM_AMIGA_4_:1 DATA PW_LEVEL RST_DLY_0_:1 DATA SLEW RST_DLY_0_:1 DATA PW_LEVEL RST_DLY_1_:1 DATA SLEW RST_DLY_1_:1 DATA PW_LEVEL RST_DLY_2_:1 DATA SLEW RST_DLY_2_:1 -DATA PW_LEVEL CLK_000_P_SYNC_0_:1 -DATA SLEW CLK_000_P_SYNC_0_:1 -DATA PW_LEVEL CLK_000_P_SYNC_1_:1 -DATA SLEW CLK_000_P_SYNC_1_:1 -DATA PW_LEVEL CLK_000_P_SYNC_2_:1 -DATA SLEW CLK_000_P_SYNC_2_:1 -DATA PW_LEVEL CLK_000_P_SYNC_3_:1 -DATA SLEW CLK_000_P_SYNC_3_:1 -DATA PW_LEVEL CLK_000_P_SYNC_4_:1 -DATA SLEW CLK_000_P_SYNC_4_:1 -DATA PW_LEVEL CLK_000_P_SYNC_5_:1 -DATA SLEW CLK_000_P_SYNC_5_:1 -DATA PW_LEVEL CLK_000_P_SYNC_6_:1 -DATA SLEW CLK_000_P_SYNC_6_:1 -DATA PW_LEVEL CLK_000_P_SYNC_7_:1 -DATA SLEW CLK_000_P_SYNC_7_:1 -DATA PW_LEVEL CLK_000_P_SYNC_8_:1 -DATA SLEW CLK_000_P_SYNC_8_:1 -DATA PW_LEVEL CLK_000_P_SYNC_9_:1 -DATA SLEW CLK_000_P_SYNC_9_:1 -DATA PW_LEVEL CLK_000_N_SYNC_1_:1 -DATA SLEW CLK_000_N_SYNC_1_:1 -DATA PW_LEVEL CLK_000_N_SYNC_2_:1 -DATA SLEW CLK_000_N_SYNC_2_:1 -DATA PW_LEVEL CLK_000_N_SYNC_3_:1 -DATA SLEW CLK_000_N_SYNC_3_:1 -DATA PW_LEVEL CLK_000_N_SYNC_4_:1 -DATA SLEW CLK_000_N_SYNC_4_:1 -DATA PW_LEVEL CLK_000_N_SYNC_5_:1 -DATA SLEW CLK_000_N_SYNC_5_:1 -DATA PW_LEVEL CLK_000_N_SYNC_6_:1 -DATA SLEW CLK_000_N_SYNC_6_:1 -DATA PW_LEVEL CLK_000_N_SYNC_7_:1 -DATA SLEW CLK_000_N_SYNC_7_:1 -DATA PW_LEVEL CLK_000_N_SYNC_8_:1 -DATA SLEW CLK_000_N_SYNC_8_:1 -DATA PW_LEVEL CLK_000_N_SYNC_9_:1 -DATA SLEW CLK_000_N_SYNC_9_:1 -DATA PW_LEVEL CLK_000_N_SYNC_10_:1 -DATA SLEW CLK_000_N_SYNC_10_:1 -DATA PW_LEVEL CLK_000_N_SYNC_11_:1 -DATA SLEW CLK_000_N_SYNC_11_:1 -DATA PW_LEVEL inst_CLK_000_NE_D0:1 -DATA SLEW inst_CLK_000_NE_D0:1 -DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 -DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 -DATA PW_LEVEL SM_AMIGA_6_:1 -DATA SLEW SM_AMIGA_6_:1 DATA PW_LEVEL inst_CLK_030_H:1 DATA SLEW inst_CLK_030_H:1 DATA PW_LEVEL SM_AMIGA_1_:1 DATA SLEW SM_AMIGA_1_:1 +DATA PW_LEVEL SM_AMIGA_5_:1 +DATA SLEW SM_AMIGA_5_:1 DATA PW_LEVEL SM_AMIGA_3_:1 DATA SLEW SM_AMIGA_3_:1 DATA PW_LEVEL SM_AMIGA_2_:1 @@ -491,12 +413,12 @@ DATA PW_LEVEL CIIN_0:1 DATA SLEW CIIN_0:1 DATA PW_LEVEL RN_IPL_030_2_:1 DATA PW_LEVEL RN_RW_000:1 -DATA PW_LEVEL RN_A_0_:1 -DATA PW_LEVEL RN_IPL_030_1_:1 -DATA PW_LEVEL RN_IPL_030_0_:1 DATA PW_LEVEL RN_BG_000:1 DATA PW_LEVEL RN_BGACK_030:1 DATA PW_LEVEL RN_DSACK1:1 DATA PW_LEVEL RN_VMA:1 DATA PW_LEVEL RN_RW:1 +DATA PW_LEVEL RN_A_0_:1 +DATA PW_LEVEL RN_IPL_030_1_:1 +DATA PW_LEVEL RN_IPL_030_0_:1 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 6161d0d..59a789d 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,30 +1,23 @@ -GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT - CYCLE_DMA_1_ CYCLE_DMA_0_ inst_VPA_D CLK_000_P_SYNC_10_ CLK_000_P_SYNC_1_ - CLK_000_P_SYNC_4_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_4_ - CLK_000_N_SYNC_5_ DS_030 AVEC +GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_RESET_OUT + CYCLE_DMA_1_ CYCLE_DMA_0_ inst_AS_030_D0 IPL_D0_2_ CLK_000_D_7_ CLK_000_D_9_ + DS_030 AVEC GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_UDS_000_INT - cpu_est_0_ IPL_D0_2_ CLK_000_D_6_ CLK_000_D_8_ CLK_000_N_SYNC_6_ - CLK_000_N_SYNC_8_ AHIGH_31_ AHIGH_30_ AHIGH_29_ RESET -GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AMIGA_BUS_ENABLE_DMA_HIGH - inst_DTACK_D0 CLK_000_D_4_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_10_ - CLK_000_N_SYNC_11_ CLK_000_D_1_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ + RN_IPL_030_2_ CLK_EXP inst_DS_000_ENABLE SM_AMIGA_4_ IPL_D0_0_ IPL_D0_1_ + AHIGH_31_ AHIGH_30_ AHIGH_29_ RESET +GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AS_000_INT CLK_000_D_10_ + CLK_000_D_0_ CLK_000_D_4_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW -GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_RESET_OUT RST_DLY_0_ - RST_DLY_1_ RST_DLY_2_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_0_ IPL_D0_0_ - CLK_000_D_9_ CLK_000_N_SYNC_12_ CLK_000_P_SYNC_7_ AMIGA_BUS_ENABLE_HIGH - LDS_000 UDS_000 AMIGA_ADDR_ENABLE -GROUP MACH_SEG_E CLK_000_D_5_ inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 CLK_000_N_SYNC_1_ - inst_CLK_000_NE_D0 CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 -GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE - SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ cpu_est_2_ - cpu_est_1_ IPL_D0_1_ CLK_000_P_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_9_ - N_226 +GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_LDS_000_INT cpu_est_3_ + cpu_est_2_ inst_UDS_000_INT cpu_est_0_ CLK_000_D_6_ LDS_000 UDS_000 + AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE +GROUP MACH_SEG_E CLK_000_D_5_ inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 CLK_000_D_3_ + CLK_000_D_2_ CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 +GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ RST_DLY_0_ RST_DLY_1_ + RST_DLY_2_ SM_AMIGA_1_ SM_AMIGA_5_ cpu_est_1_ inst_VPA_D GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_ - inst_AS_000_INT CLK_000_D_10_ CLK_000_D_3_ CLK_000_D_7_ CLK_000_P_SYNC_5_ - CLK_000_P_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_D_0_ CLK_000_D_2_ SIZE_0_ - E + SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_DTACK_D0 CLK_000_D_8_ CLK_000_D_12_ SIZE_0_ E GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 - inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_D_11_ CLK_000_D_12_ FPU_CS - AS_030 SIZE_1_ \ No newline at end of file + inst_BGACK_030_INT_D CLK_000_D_11_ CLK_000_D_1_ FPU_CS AS_030 SIZE_1_ + \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 35e5b62..97b6f35 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -15:;107B74eO \ No newline at end of file +56;:107Kjg9j \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index a3cc5af..644f175 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Fri Aug 19 00:20:46 2016 +DATE: Fri Aug 19 00:39:40 2016 ABEL mach447a * @@ -31,194 +31,185 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS A_DECODE_22_:84 A_DECODE_21_:94 SIZE_1_:79 A_DECODE_20_:93* -NOTE PINS A_DECODE_19_:97 AHIGH_31_:4 A_DECODE_18_:95 A_DECODE_17_:59* -NOTE PINS A_DECODE_23_:85 A_DECODE_16_:96 IPL_2_:68 FC_1_:58* -NOTE PINS AS_030:82 AS_000:42 DS_030:98 UDS_000:32 LDS_000:31* -NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 IPL_1_:56 IPL_0_:67* -NOTE PINS BGACK_000:28 FC_0_:57 CLK_030:64 A_1_:60 CLK_000:11* -NOTE PINS CLK_OSZI:61 CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91* -NOTE PINS DTACK:30 AVEC:92 E:66 VPA:36 RST:86 RESET:3 AMIGA_ADDR_ENABLE:33* -NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* -NOTE PINS CIIN:47 SIZE_0_:70 AHIGH_30_:5 AHIGH_29_:6 AHIGH_28_:15* -NOTE PINS AHIGH_27_:16 AHIGH_26_:17 AHIGH_25_:18 AHIGH_24_:19* -NOTE PINS IPL_030_2_:9 RW_000:80 A_0_:69 IPL_030_1_:7 IPL_030_0_:8* -NOTE PINS BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81 VMA:35* -NOTE PINS RW:71 * +NOTE PINS SIZE_1_:79 AHIGH_31_:4 A_DECODE_23_:85 IPL_2_:68* +NOTE PINS FC_1_:58 AS_030:82 AS_000:42 DS_030:98 UDS_000:32* +NOTE PINS LDS_000:31 nEXP_SPACE:14 BERR:41 BG_030:21 SIZE_0_:70* +NOTE PINS AHIGH_30_:5 BGACK_000:28 AHIGH_29_:6 CLK_030:64* +NOTE PINS AHIGH_28_:15 CLK_000:11 AHIGH_27_:16 CLK_OSZI:61* +NOTE PINS AHIGH_26_:17 CLK_DIV_OUT:65 AHIGH_25_:18 AHIGH_24_:19* +NOTE PINS FPU_CS:78 A_DECODE_22_:84 FPU_SENSE:91 A_DECODE_21_:94* +NOTE PINS A_DECODE_20_:93 DTACK:30 A_DECODE_19_:97 AVEC:92* +NOTE PINS A_DECODE_18_:95 E:66 A_DECODE_17_:59 VPA:36 A_DECODE_16_:96* +NOTE PINS RST:86 RESET:3 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 IPL_1_:56 IPL_0_:67 FC_0_:57 A_1_:60 IPL_030_2_:9* +NOTE PINS RW_000:80 BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81* +NOTE PINS VMA:35 RW:71 A_0_:69 IPL_030_1_:7 IPL_030_0_:8* NOTE Table of node names and numbers* NOTE NODES RN_SIZE_1_:287 RN_AHIGH_31_:143 RN_AS_030:281 * NOTE NODES RN_AS_000:203 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * NOTE NODES RN_SIZE_0_:263 RN_AHIGH_30_:125 RN_AHIGH_29_:145 * -NOTE NODES RN_AHIGH_28_:149 RN_AHIGH_27_:155 RN_AHIGH_26_:157 * +NOTE NODES RN_AHIGH_28_:149 RN_AHIGH_27_:163 RN_AHIGH_26_:157 * NOTE NODES RN_AHIGH_25_:167 RN_AHIGH_24_:161 RN_IPL_030_2_:131 * -NOTE NODES RN_RW_000:269 RN_A_0_:257 RN_IPL_030_1_:139 RN_IPL_030_0_:137 * -NOTE NODES RN_BG_000:175 RN_BGACK_030:278 RN_DSACK1:283 * -NOTE NODES RN_VMA:173 RN_RW:245 N_226:242 cpu_est_2_:227 * -NOTE NODES cpu_est_3_:223 cpu_est_0_:128 cpu_est_1_:239 * -NOTE NODES inst_AS_000_INT:248 inst_AMIGA_BUS_ENABLE_DMA_LOW:140 * -NOTE NODES inst_AS_030_D0:271 inst_AS_030_000_SYNC:169 inst_BGACK_030_INT_D:289 * -NOTE NODES inst_AS_000_DMA:119 inst_DS_000_DMA:115 CYCLE_DMA_0_:116 * -NOTE NODES CYCLE_DMA_1_:104 SIZE_DMA_0_:259 SIZE_DMA_1_:253 * -NOTE NODES inst_VPA_D:109 inst_UDS_000_INT:134 inst_LDS_000_INT:103 * -NOTE NODES inst_CLK_OUT_PRE_D:209 CLK_000_D_10_:268 CLK_000_D_11_:284 * -NOTE NODES inst_DTACK_D0:172 inst_RESET_OUT:187 inst_CLK_OUT_PRE_50:200 * -NOTE NODES CLK_000_D_1_:158 CLK_000_D_0_:265 CLK_000_P_SYNC_10_:113 * -NOTE NODES SM_AMIGA_5_:233 IPL_D0_0_:196 IPL_D0_1_:244 IPL_D0_2_:148 * -NOTE NODES CLK_000_D_2_:262 CLK_000_D_3_:256 CLK_000_D_4_:166 * -NOTE NODES CLK_000_D_5_:217 CLK_000_D_6_:142 CLK_000_D_7_:250 * -NOTE NODES CLK_000_D_8_:136 CLK_000_D_9_:190 CLK_000_D_12_:272 * -NOTE NODES SM_AMIGA_0_:229 CLK_000_N_SYNC_0_:176 SM_AMIGA_4_:236 * -NOTE NODES inst_DS_000_ENABLE:235 CLK_000_N_SYNC_12_:193 * -NOTE NODES RST_DLY_0_:188 RST_DLY_1_:182 RST_DLY_2_:194 * -NOTE NODES CLK_000_P_SYNC_0_:184 CLK_000_P_SYNC_1_:124 CLK_000_P_SYNC_2_:238 * -NOTE NODES CLK_000_P_SYNC_3_:160 CLK_000_P_SYNC_4_:118 CLK_000_P_SYNC_5_:266 * -NOTE NODES CLK_000_P_SYNC_6_:260 CLK_000_P_SYNC_7_:178 CLK_000_P_SYNC_8_:112 * -NOTE NODES CLK_000_P_SYNC_9_:154 CLK_000_N_SYNC_1_:211 CLK_000_N_SYNC_2_:106 * -NOTE NODES CLK_000_N_SYNC_3_:232 CLK_000_N_SYNC_4_:122 CLK_000_N_SYNC_5_:110 * -NOTE NODES CLK_000_N_SYNC_6_:130 CLK_000_N_SYNC_7_:254 CLK_000_N_SYNC_8_:146 * -NOTE NODES CLK_000_N_SYNC_9_:226 CLK_000_N_SYNC_10_:170 * -NOTE NODES CLK_000_N_SYNC_11_:164 inst_CLK_000_NE_D0:205 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:152 SM_AMIGA_6_:163 * -NOTE NODES inst_CLK_030_H:121 SM_AMIGA_1_:241 SM_AMIGA_3_:224 * -NOTE NODES SM_AMIGA_2_:230 SM_AMIGA_i_7_:221 CIIN_0:212 * +NOTE NODES RN_RW_000:271 RN_BG_000:175 RN_BGACK_030:275 * +NOTE NODES RN_DSACK1:283 RN_VMA:173 RN_RW:245 RN_A_0_:257 * +NOTE NODES RN_IPL_030_1_:139 RN_IPL_030_0_:133 cpu_est_3_:187 * +NOTE NODES cpu_est_0_:176 cpu_est_1_:233 cpu_est_2_:193 * +NOTE NODES inst_AS_000_INT:172 inst_AMIGA_BUS_ENABLE_DMA_LOW:260 * +NOTE NODES inst_AS_030_D0:110 inst_AS_030_000_SYNC:158 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:119 inst_DS_000_DMA:103 CYCLE_DMA_0_:121 * +NOTE NODES CYCLE_DMA_1_:115 SIZE_DMA_0_:248 SIZE_DMA_1_:259 * +NOTE NODES inst_VPA_D:224 inst_UDS_000_INT:188 inst_LDS_000_INT:182 * +NOTE NODES inst_CLK_OUT_PRE_D:209 CLK_000_D_1_:274 CLK_000_D_10_:170 * +NOTE NODES CLK_000_D_11_:269 inst_DTACK_D0:256 inst_RESET_OUT:113 * +NOTE NODES CLK_000_D_0_:169 inst_CLK_OUT_PRE_50:206 IPL_D0_0_:130 * +NOTE NODES IPL_D0_1_:146 IPL_D0_2_:106 CLK_000_D_2_:200 * +NOTE NODES CLK_000_D_3_:211 CLK_000_D_4_:166 CLK_000_D_5_:205 * +NOTE NODES CLK_000_D_6_:194 CLK_000_D_7_:122 CLK_000_D_8_:250 * +NOTE NODES CLK_000_D_9_:116 CLK_000_D_12_:266 inst_AMIGA_BUS_ENABLE_DMA_HIGH:254 * +NOTE NODES inst_DS_000_ENABLE:134 SM_AMIGA_6_:152 SM_AMIGA_0_:253 * +NOTE NODES SM_AMIGA_4_:140 RST_DLY_0_:221 RST_DLY_1_:241 * +NOTE NODES RST_DLY_2_:235 inst_CLK_030_H:109 SM_AMIGA_1_:223 * +NOTE NODES SM_AMIGA_5_:229 SM_AMIGA_3_:236 SM_AMIGA_2_:230 * +NOTE NODES SM_AMIGA_i_7_:227 CIIN_0:212 * NOTE BLOCK 0 * L000000 - 111111111011111111111111111111111111111111111111111111111111111111 - 111111111101111111111111111111111110111111111101111111111111111111 - 101111111111011111111111111111111011111111111111111111111111111111 - 111111111111111111111111011111111111111111111111111111111111111111 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111101011111111110111111110111111111111111 - 111110111111110111111111110111111111010111111111111111011011111111 - 111111111111111101011111111111111111111111111111111111111111101111 - 111111111111111111110111111111111111111111010111101110111111111111* + 111111111011101111111101111111111111111111111111111111111111111111 + 111011111101111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111011111111111111111111 + 111111111111111111111111111111111111111111111111101111111111111111 + 111111111111111111111111111111111101111111111111111111111111111011 + 111111111111111111111111111111011111111111111111110111111111111111 + 111101011111111111111111111111111111111111101111111111011111111111 + 111111111111111101111011111111111111011010111111111111111111111111 + 101111111111111111011111111111111011111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111111111111111111111111111111111111011111111111110111111111111* +L000660 111111111111111111101111111111111011111111111111111111111111111111* L000726 000000000000000000000000000000000000000000000000000000000000000000* L000792 000000000000000000000000000000000000000000000000000000000000000000* L000858 000000000000000000000000000000000000000000000000000000000000000000* L000924 000000000000000000000000000000000000000000000000000000000000000000* -L000990 111111111111111111111111111111111111111111111111101111111111111111* -L001056 111111111111111111111111111111111111111111011110111111111111111111* -L001122 101111111111111111111111111111111101111110111101111111111111111111* -L001188 000000000000000000000000000000000000000000000000000000000000000000* -L001254 000000000000000000000000000000000000000000000000000000000000000000* +L000990 101111111111111111111111111111111111111111111111111111111111111111* +L001056 111111111111111111111111111111111111111101111111111111111111111111* +L001122 111101111111111111111111111111111111111111111111110111111111111111* +L001188 111110111111111111111111111111111111111111111111111011111111111111* +L001254 111111111111111111111111111111110111111111111111111111111111111111* L001320 111111111111111111111111111111111111111111111111111111111111111111* -L001386 111111111111111111111111111110111111111111110111011110111111101111* -L001452 111111111111111111111111111101111111011111111011011110111111101111* -L001518 111111111111111111111111111111111111101111110111011110111111101111* -L001584 000000000000000000000000000000000000000000000000000000000000000000* +L001386 111111111111111101111111111111111111111111111111111111011111111111* +L001452 111111111011111111011111111111111111111111101111111111111111111111* +L001518 111111110111111111111111111111011111011111101111111111111111111111* +L001584 111111111111111111011111111111111111101111101111111111111111111111* L001650 000000000000000000000000000000000000000000000000000000000000000000* -L001716 111101111111111111111111111111111111111111111111111111111111111111* -L001782 000000000000000000000000000000000000000000000000000000000000000000* -L001848 000000000000000000000000000000000000000000000000000000000000000000* -L001914 000000000000000000000000000000000000000000000000000000000000000000* -L001980 000000000000000000000000000000000000000000000000000000000000000000* +L001716 011111111111111111111111111111111111111111111011111111111111111111* +L001782 111111111111111111111111111111111111111111111111111111111111111111* +L001848 111111111111111111111111111111111111111111111111111111111111111111* +L001914 111111111111111111111111111111111111111111111111111111111111111111* +L001980 111111111111111111111111111111111111111111111111111111111111111111* L002046 000000000000000000000000000000000000000000000000000000000000000000* L002112 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111111111111111111111111111111111111111111111111111111111111111111* +L002442 011101111011111110111111111111101011111110111111111011111111111111* +L002508 011110111011111110111111111111101011111110111111110111111111111111* +L002574 011101111111111110111111111111111011011110111111111011111111111111* +L002640 011110111111111110111111111111111011011110111111110111111111111111* +L002706 011101111011111111111111111111101011111110111111111011101111111111* L002772 000000000000000000000000000000000000000000000000000000000000000000* -L002838 111111011111111111111111111111111111111111111111111111111111111111* -L002904 000000000000000000000000000000000000000000000000000000000000000000* -L002970 000000000000000000000000000000000000000000000000000000000000000000* -L003036 000000000000000000000000000000000000000000000000000000000000000000* +L002838 011111111111111111111111111111111111111011111111111111111111111111* +L002904 011110111011111111111111111111101011111110111111110111101111111111* +L002970 011101111111111111111111111111111011011110111111111011101111111111* +L003036 011110111111111111111111111111111011011110111111110111101111111111* L003102 000000000000000000000000000000000000000000000000000000000000000000* -L003168 111111111111111111011111111111111111111111111111111111111111111111* -L003234 000000000000000000000000000000000000000000000000000000000000000000* -L003300 000000000000000000000000000000000000000000000000000000000000000000* -L003366 000000000000000000000000000000000000000000000000000000000000000000* -L003432 000000000000000000000000000000000000000000000000000000000000000000* +L003168 111111111111111111111111111111111111111111111111111111111111111111* +L003234 111111111111111111111111111111111111111111111111111111111111111111* +L003300 111111111111111111111111111111111111111111111111111111111111111111* +L003366 111111111111111111111111111111111111111111111111111111111111111111* +L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111111111111111111111111011111111111111111111111111111111111111111* -L003630 000000000000000000000000000000000000000000000000000000000000000000* +L003564 011111011111111111111111111111111111111111111111111111111111111111* +L003630 010111111111011111110110111111111111111111111111111111111111110111* L003696 000000000000000000000000000000000000000000000000000000000000000000* L003762 000000000000000000000000000000000000000000000000000000000000000000* L003828 000000000000000000000000000000000000000000000000000000000000000000* -L003894 111111111111111111111111111111111111111111111111101111111111111111* -L003960 111111111111111111111111111111111111111111111111111111111111011111* -L004026 111111111111111111111111111101111111111111110111111111111111111111* -L004092 111111111111111111111111111110111111111111111011111111111111111111* -L004158 111111111111111111111111111111111111111111111111111101111111111111* +L003894 011101111111111111111111111111111011111110111111111011111111111111* +L003960 011101111111111111110111111111111011111110111111111111111111111111* +L004026 011110111111111111111001111111111011111110111111110111111111111111* +L004092 011101111111111111111110111111111011111110111111111111111111111111* +L004158 000000000000000000000000000000000000000000000000000000000000000000* L004224 000000000000000000000000000000000000000000000000000000000000000000* -L004290 111111111111111111111111111110111111011111111111011110111111101111* -L004356 111111111111111111111111111101111111101111111111011110111111101111* -L004422 000000000000000000000000000000000000000000000000000000000000000000* -L004488 000000000000000000000000000000000000000000000000000000000000000000* -L004554 000000000000000000000000000000000000000000000000000000000000000000* -L004620 111111111111011111111111111111111111111111111111111111111111111111* -L004686 111111111111111101111111111111111111111111111111111111011111111111* -L004752 111111111011111111111111111111111111110111111111111111111011111111* -L004818 111111110111111111111111111111011111111111111111110111111011111111* -L004884 111111111111111111111111111111111111110111111111111011111011111111* +L004290 111111111111111111111111111111111111111111111111011111111111111111* +L004356 111111111111111111111111111111111111111111111111111111111111111111* +L004422 111111111111111111111111111111111111111111111111111111111111111111* +L004488 111111111111111111111111111111111111111111111111111111111111111111* +L004554 111111111111111111111111111111111111111111111111111111111111111111* +L004620 111111111111111111111111111111111111111111111111111111111111111111* +L004686 111111111111111111111111111111111111111111111111111111111111111111* +L004752 111111111111111111111111111111111111111111111111111111111111111111* +L004818 111111111111111111111111111111111111111111111111111111111111111111* +L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111111111111111111111111111111111111111111111101111111111111111* -L005082 111111111111111111111111111111111111111111111111111111111111011111* +L005016 101111111111111111111111111111111111111111111111111111111111111111* +L005082 111111111111111111111111111111111111111101111111111111111111111111* L005148 111111111011111111111111111111011111111111111111111111111111111111* -L005214 111111111111111111111111111101111111111111110111111111111111111111* -L005280 111111111111111111111111111110111111111111111011111111111111111111* -L005346 111111111111111111111111111111111111111111111111111101111111111111* -L005412 111111111111111101111111111111111111111111111111111111011111111111* -L005478 000000000000000000000000000000000000000000000000000000000000000000* +L005214 111101111111111111111111111111111111111111111111110111111111111111* +L005280 111110111111111111111111111111111111111111111111111011111111111111* +L005346 011111111111111111110111111111111011111110111111110111111111111111* +L005412 011111111111111111111001111111111011111110111111111011111111111111* +L005478 011111111111111111111110111111111011111110111111110111111111111111* L005544 000000000000000000000000000000000000000000000000000000000000000000* L005610 000000000000000000000000000000000000000000000000000000000000000000* L005676 - 111111111110110111111111111111111111111111111111111111111111101111* -L005742 111111111111111111111111111111110111111111111111111111111111111111* -L005808 111111111011111110111111111110101111111111110111011110111111101111* -L005874 111111111011111110111111111101101111111111111011011110111111101111* -L005940 111111111111111110111111111110111111111111110111010110111111101111* -L006006 111111111111111110111111111101111111111111111011010110111111101111* -L006072 111111111111111111111111110111111111111111111111111111111111111111* -L006138 111111111011111111111111111110101111111111110111011110101111101111* -L006204 111111111011111111111111111101101111111111111011011110101111101111* -L006270 111111111111111111111111111110111111111111110111010110101111101111* -L006336 111111111111111111111111111101111111111111111011010110101111101111* + 111111011110111111111111111111111111111110111111111111111111111111* +L005742 111111111111111111111111111111111101111111111111111111111111111111* +L005808 111111111111111111111111111111110111111111111111111111111111111111* +L005874 111111111111111101111111111111111111111111111111111111011111111111* +L005940 000000000000000000000000000000000000000000000000000000000000000000* +L006006 000000000000000000000000000000000000000000000000000000000000000000* +L006072 111111111111111111111111111111111111111111111111111111111111111111* +L006138 111111111111111111111111111111111111111111111111111111111111111111* +L006204 111111111111111111111111111111111111111111111111111111111111111111* +L006270 111111111111111111111111111111111111111111111111111111111111111111* +L006336 111111111111111111111111111111111111111111111111111111111111111111* L006402 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* L006538 01100011111000* -L006552 10100110010011* -L006566 10100110010101* -L006580 00100110011111* -L006594 00101111111000* -L006608 01100110010010* -L006622 00100110010000* -L006636 00100110010011* -L006650 00100110010000* -L006664 10100110010010* -L006678 10100110010000* -L006692 00000110010011* -L006706 10100110010001* -L006720 10110110010011* -L006734 00110110010100* -L006748 00000110011110* +L006552 10100110011011* +L006566 11110011110101* +L006580 01110110011111* +L006594 00000011111000* +L006608 10100110010011* +L006622 01110110010001* +L006636 11101011110011* +L006650 10100110010000* +L006664 10100110010011* +L006678 00010110010001* +L006692 11100011110011* +L006706 10100110010000* +L006720 10100110010010* +L006734 00000110010101* +L006748 11101011111111* NOTE BLOCK 1 * L006762 - 111111111111111101111111111111111111111011111111111111111111111111 - 111111011111011111111111011111011111111111111111111111111111111111 - 111111111010111111111101111111111101101111111111111111111111111011 - 101111111111111111110111111111111111111111111111101111011111111111 - 111101111111111111111111111111111111111111111110111111111111111111 - 111111111111111011111111111011111111111111111111111111111111111111 - 111111111111111111111111111111111011111111110111110111111111111111 - 111111111111111111111111111110111111111111111111111111111111101111 - 111111111111111111111111111111111111111111101111111111111111111111* + 111111111111111111111101111111111111111101111111111111111111111111 + 111111111101011110111111011111111111111111111111111111111111111111 + 111101101011111111101111111111111111111111111111111111110111111111 + 111111111111111111111111110110111011111111111011111111011111111101 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111011111011111111111111111111111101111 + 101111111111111111111011111111111111111111111111110111111111111111 + 111011111111111111111111111111111111111111101111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* L007422 000000000000000000000000000000000000000000000000000000000000000000* @@ -226,219 +217,219 @@ L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* L007686 000000000000000000000000000000000000000000000000000000000000000000* -L007752 111111111111111111111111111111110111111111111111111111111111111111* +L007752 111111111111111111111111111111111111111111111111111111111111011111* L007818 000000000000000000000000000000000000000000000000000000000000000000* L007884 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101110111011111110111111111111111111110111011111111111111111110111* -L008676 011101111011111110111111111111111111111011011111111111111111111011* -L008742 101110111011111110111111111111111111111011011111111111111111111011* +L008478 111111111111111111111111111111111011111111011111111111111111111111* +L008544 000000000000000000000000000000000000000000000000000000000000000000* +L008610 000000000000000000000000000000000000000000000000000000000000000000* +L008676 000000000000000000000000000000000000000000000000000000000000000000* +L008742 000000000000000000000000000000000000000000000000000000000000000000* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111111111011111111111111111111111111111111011111111111101111111111* -L008940 101101111111111111111111111111111111111111011111111111101111111111* -L009006 011110111111111111111111111111111111111111011111111111101111111111* -L009072 111111111111111111111111111111111111110111011111111111101111111011* -L009138 111111111111111111111111111111111111111011011111111111101111110111* -L009204 000000000000000000000000000000000000000000000000000000000000000000* -L009270 111111111111111110111111111111111111111111011111111111101111111111* -L009336 000000000000000000000000000000000000000000000000000000000000000000* -L009402 000000000000000000000000000000000000000000000000000000000000000000* -L009468 000000000000000000000000000000000000000000000000000000000000000000* +L008874 111111011011111111111111110111110111111101011111111011111111111111* +L008940 111111011011111111111111111011111011111101011111111011111111111111* +L009006 111111101011111111111111110111110111111110011111111011111111111111* +L009072 111111101011111111111111111011111011111110011111111011111111111111* +L009138 111111111011111111111111111111111111111111011111111111101111111111* +L009204 111111111111111111111111110111111011111111011111111111101111111111* +L009270 111111111111111111111111111011110111111111011111111111101111111111* +L009336 111111101111111111111111111111111111111101011111111111101111111111* +L009402 111111011111111111111111111111111111111110011111111111101111111111* +L009468 111111111111111111111111111111111111111111011111111011101111111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111101111111111111110111111111111111111011111111111111111111111* -L009666 111111011111111111111111111111111111101111011111111111111111111111* -L009732 000000000000000000000000000000000000000000000000000000000000000000* -L009798 000000000000000000000000000000000000000000000000000000000000000000* -L009864 000000000000000000000000000000000000000000000000000000000000000000* -L009930 111111111111111111111111111111111111111111111111011111111111111111* -L009996 000000000000000000000000000000000000000000000000000000000000000000* -L010062 000000000000000000000000000000000000000000000000000000000000000000* -L010128 000000000000000000000000000000000000000000000000000000000000000000* -L010194 000000000000000000000000000000000000000000000000000000000000000000* +L009600 111111011011111111111111111011111011111101011111111011111111111111* +L009666 111111101011111111111111111011111011111110011111111011111111111111* +L009732 111111100111111111111111111011111011111110011111110111111111111111* +L009798 111111010111111111111111111011111011111101011111110111111111111111* +L009864 111111111111111111111111111111111011111111011111111111111011111111* +L009930 111111111111111111111111111011111111111111011111111111111011111111* +L009996 111111101111111111111111111111111111111101011111111111111011111111* +L010062 111111011111111111111111111111111111111110011111111111111011111111* +L010128 111111111011111111111111111111111111111111011111110111111011111111* +L010194 111111110111111111111111111111111111111111011111111011111011111111* L010260 - 111111111111111111111111111111101111111111111111110111111111101111* -L010326 101110111011111110111111111111111111110111011111111111111111110111* -L010392 101110111011111110111111111111111111111011011111111111111111111011* -L010458 101110110111111101111111111111111111111011011111111111111111111011* -L010524 101110110111111101111111111111111111110111011111111111111111110111* -L010590 101111111111111111111111111111111110111111011111111111111111111111* -L010656 111110111111111111111111111111111110111111011111111111111111111111* -L010722 111111111111111111111111111111111110110111011111111111111111111011* -L010788 111111111111111111111111111111111110111011011111111111111111110111* -L010854 111111111011111101111111111111111110111111011111111111111111111111* -L010920 111111110111111110111111111111111110111111011111111111111111111111* + 101111111110111111111111111111111111011111111111111111111111111111* +L010326 111111111111111111101001111101111111111111011011111111111111111110* +L010392 111111111111111111101111101101111111111111011011111111111111111110* +L010458 110101111111111111111111111111101111111111011111111111111111111111* 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111111111111101111111111111111111111111111011111111111111111111011* -L011382 101101111111101111111111111111111111111111011111111111111111111111* -L011448 011110111111101111111111111111111111111111011111111111111111111111* -L011514 111111111111101111111111111111111111111011011111111111111111111111* -L011580 111111111011101101111111111111111111111111011111111111111111111111* -L011646 111111110111101110111111111111111111111111011111111111111111111111* + 101111111110111111111111111111111111011111111111111111111111111111* +L011052 111111111111101111111111110111111011111111011111111111111111111111* +L011118 111111111111101111111111111011110111111111011111111111111111111111* +L011184 111111111111101111111111111111111111111110011111111111111111111111* +L011250 111111111011101111111111111111111111111111011111110111111111111111* +L011316 111111110111101111111111111111111111111111011111111011111111111111* +L011382 111111111111111111111111111111111111111111111111111111111111111111* +L011448 111111111111111111111111111111111111111111111111111111111111111111* +L011514 111111111111111111111111111111111111111111111111111111111111111111* +L011580 111111111111111111111111111111111111111111111111111111111111111111* +L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 - 111111111111111111111111111111101111111111111111110111111111101111* + 101111111110111111111111111111111111011111111111111111111111111111* L011778 000000000000000000000000000000000000000000000000000000000000000000* -L011844 111111111111111111111111111111111111111111011101111111111111101111* -L011910 111111111111110111111111101111111111111111011111111111111111011111* -L011976 000000000000000000000000000000000000000000000000000000000000000000* +L011844 111111111111111111010110111111111111111111011111111111111111111111* +L011910 110111111111111111110111011111111111111111011111111111111111111111* +L011976 110111111111111111111110011111111111111111011111111111111111111111* L012042 000000000000000000000000000000000000000000000000000000000000000000* L012108 000000000000000000000000000000000000000000000000000000000000000000* -L012174 111111111111111111111111110111111111111111111111111111111111111111* -L012240 000000000000000000000000000000000000000000000000000000000000000000* -L012306 000000000000000000000000000000000000000000000000000000000000000000* -L012372 000000000000000000000000000000000000000000000000000000000000000000* +L012174 111111111111111111111111111111111111111111111111111111111111111111* +L012240 111111111111111111111111111111111111111111111111111111111111111111* +L012306 111111111111111111111111111111111111111111111111111111111111111111* +L012372 111111111111111111111111111111111111111111111111111111111111111111* L012438 - 111111111111111111111111111111111111111111111111111011111111111111* -L012504 111111111101111111111111111111111111111111111111111111111111111111* -L012570 000000000000000000000000000000000000000000000000000000000000000000* -L012636 000000000000000000000000000000000000000000000000000000000000000000* -L012702 000000000000000000000000000000000000000000000000000000000000000000* -L012768 000000000000000000000000000000000000000000000000000000000000000000* -L012834 111111111011111111111111111111111111111111011111111111111111111111* -L012900 000000000000000000000000000000000000000000000000000000000000000000* -L012966 000000000000000000000000000000000000000000000000000000000000000000* -L013032 000000000000000000000000000000000000000000000000000000000000000000* -L013098 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111101111111111111111111111111111* +L012504 111111101111111111111111111111111111111111011111111111111111111111* +L012570 111111111111111111111111111111111111111111111111111111111111111111* +L012636 111111111111111111111111111111111111111111111111111111111111111111* +L012702 111111111111111111111111111111111111111111111111111111111111111111* +L012768 111111111111111111111111111111111111111111111111111111111111111111* +L012834 111111111111111111111111111111111111111111111111111111111111111111* +L012900 111111111111111111111111111111111111111111111111111111111111111111* +L012966 111111111111111111111111111111111111111111111111111111111111111111* +L013032 111111111111111111111111111111111111111111111111111111111111111111* +L013098 111111111111111111111111111111111111111111111111111111111111111111* L013164 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L013296 0010* L013300 00100011111000* L013314 00100110011111* -L013328 10100110010101* -L013342 00010110011111* -L013356 11100110010010* -L013370 00110011111110* -L013384 11100110011100* -L013398 00100110011111* -L013412 11100110011011* -L013426 11110110010011* -L013440 11110110010110* -L013454 10000110010011* +L013328 00100011110101* +L013342 01100110011111* +L013356 11100110011000* +L013370 11110110011111* +L013384 10110110011101* +L013398 11000011111111* +L013412 11001111111010* +L013426 11100110010010* +L013440 10110110010110* +L013454 11100011110011* L013468 00001011110001* L013482 00001111110011* -L013496 00100110011110* -L013510 01100110011110* +L013496 01010110010010* +L013510 11100011111111* NOTE BLOCK 2 * L013524 - 111111111111111111111111111111111111111111111111111011111111010111 - 111101111111111111111111110111011111111110111111111111111111111111 - 111111111111101111111111111111111111111111111111111110111111111111 - 111111111111111110111111101111111110111111110111111111111111111111 - 111111101110111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111011111111111111011111111111 - 111111110111110111011101111111111111011111111111111111110111111111 - 111111111111111111111111111111111111111111101111111111111111111111 - 101011111111111111111011111111110111111111111111111111111111111111* + 111111111111111111111111111101110111111111111111111111111111011111 + 111111111101111111111111111111111111111111111011111111111111111111 + 111111111111101111011111111111111111111111111111111111111111111111 + 111011111111111111111111111011111111111111111111111111111110111101 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111001111111011111111111111111111111111111111111111111 + 111110110111111111111101111111011111011111111111111111111111111111 + 111111111111111111111011111111111111111110111111111111111111111111 + 101111101111111111111111111111111110111111111111111111111111111111* L014118 - 111111111111110111111111111111101111111111101111111111111111111111* + 111111111110111111111111111111111111011110111111111111111111111111* L014184 000000000000000000000000000000000000000000000000000000000000000000* L014250 000000000000000000000000000000000000000000000000000000000000000000* L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 111110111111111111111111111111111111111111101111111111111111111111* +L014514 111111111111111111111111111111111111111110111011111111111111111111* L014580 000000000000000000000000000000000000000000000000000000000000000000* L014646 000000000000000000000000000000000000000000000000000000000000000000* L014712 000000000000000000000000000000000000000000000000000000000000000000* L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 - 111111111111110111111111111111101111111111101111111111111111111111* -L014910 011111101111111111111111111111111111111111101111111111111111111111* -L014976 011111111111111111111111111111111111110111011011111111111111111111* -L015042 000000000000000000000000000000000000000000000000000000000000000000* + 111111111110111111111111111111111111011110111111111111111111111111* +L014910 011111011101111111101011111111111111111111111111111111111110111111* +L014976 011111111111111111110111111111111101111111111111111111111101111101* +L015042 011111111111111111111111111111111101111111111111111111111101101101* L015108 000000000000000000000000000000000000000000000000000000000000000000* L015174 000000000000000000000000000000000000000000000000000000000000000000* -L015240 111111111111111111111111111111111111111111111111111111110111111111* -L015306 000000000000000000000000000000000000000000000000000000000000000000* -L015372 000000000000000000000000000000000000000000000000000000000000000000* -L015438 000000000000000000000000000000000000000000000000000000000000000000* -L015504 000000000000000000000000000000000000000000000000000000000000000000* +L015240 111111111111111111111111111111111111111111111111111111111111111111* +L015306 111111111111111111111111111111111111111111111111111111111111111111* +L015372 111111111111111111111111111111111111111111111111111111111111111111* +L015438 111111111111111111111111111111111111111111111111111111111111111111* +L015504 111111111111111111111111111111111111111111111111111111111111111111* L015570 - 111111111111110111111111111111101111111111101111111111111111111111* -L015636 000000000000000000000000000000000000000000000000000000000000000000* -L015702 000000000000000000000000000000000000000000000000000000000000000000* -L015768 000000000000000000000000000000000000000000000000000000000000000000* -L015834 000000000000000000000000000000000000000000000000000000000000000000* -L015900 000000000000000000000000000000000000000000000000000000000000000000* + 111111111110111111111111111111111111011110111111111111111111111111* +L015636 111111111111111111111111111111111111111111111111111111111111111111* +L015702 111111111111111111111111111111111111111111111111111111111111111111* +L015768 111111111111111111111111111111111111111111111111111111111111111111* +L015834 111111111111111111111111111111111111111111111111111111111111111111* +L015900 111111111111111111111111111111111111111111111111111111111111111111* L015966 000000000000000000000000000000000000000000000000000000000000000000* -L016032 000000000000000000000000000000000000000000000000000000000000000000* -L016098 000000000000000000000000000000000000000000000000000000000000000000* -L016164 000000000000000000000000000000000000000000000000000000000000000000* -L016230 000000000000000000000000000000000000000000000000000000000000000000* +L016032 111111111111111111111111111111111111111111111111111111111111111111* +L016098 111111111111111111111111111111111111111111111111111111111111111111* +L016164 111111111111111111111111111111111111111111111111111111111111111111* +L016230 111111111111111111111111111111111111111111111111111111111111111111* L016296 - 111111111111110111111111111111101111111111101111111111111111111111* -L016362 111111111111111111111111111111111111111111111111110111111111111111* -L016428 000000000000000000000000000000000000000000000000000000000000000000* -L016494 000000000000000000000000000000000000000000000000000000000000000000* -L016560 000000000000000000000000000000000000000000000000000000000000000000* -L016626 000000000000000000000000000000000000000000000000000000000000000000* -L016692 111111111111111111111111111111111111111101111111111111111111111111* -L016758 000000000000000000000000000000000000000000000000000000000000000000* -L016824 000000000000000000000000000000000000000000000000000000000000000000* -L016890 000000000000000000000000000000000000000000000000000000000000000000* -L016956 000000000000000000000000000000000000000000000000000000000000000000* + 111111111110111111111111111111111111011110111111111111111111111111* +L016362 011111111111111111101111111111101101111111111111111111111111111111* +L016428 011011111101110111111111111111101101111101111111111111111110111111* +L016494 011111111101110111111111011111101101111101111111111111111110111111* +L016560 011111110101110111111111111111101101111101111111111111111110111111* +L016626 011111111101110111111111111011101101111101111111111111111110111111* +L016692 111111111111111111111111111111111111111111111111111111111111111111* +L016758 111111111111111111111111111111111111111111111111111111111111111111* +L016824 111111111111111111111111111111111111111111111111111111111111111111* +L016890 111111111111111111111111111111111111111111111111111111111111111111* +L016956 111111111111111111111111111111111111111111111111111111111111111111* L017022 - 111111111111110111111111111111101111111111101111111111111111111111* + 111111111110111111111111111111111111011110111111111111111111111111* L017088 000000000000000000000000000000000000000000000000000000000000000000* -L017154 000000000000000000000000000000000000000000000000000000000000000000* -L017220 000000000000000000000000000000000000000000000000000000000000000000* +L017154 011111111101110111111101111111101101111101111111111111111110111111* +L017220 011111111101100111111111111111101101111101111111111111111110111111* L017286 000000000000000000000000000000000000000000000000000000000000000000* L017352 000000000000000000000000000000000000000000000000000000000000000000* -L017418 011111111110111111111111111111010111111111111111111111111111101111* -L017484 011111111110111111111111110111111111111111111111111111111111111111* -L017550 010111111111111111111111110111111111101111111111111111111111111111* -L017616 000000000000000000000000000000000000000000000000000000000000000000* -L017682 000000000000000000000000000000000000000000000000000000000000000000* +L017418 000000000000000000000000000000000000000000000000000000000000000000* +L017484 111111111111111111111111111111111111111111111111111111111111111111* +L017550 111111111111111111111111111111111111111111111111111111111111111111* +L017616 111111111111111111111111111111111111111111111111111111111111111111* +L017682 111111111111111111111111111111111111111111111111111111111111111111* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 111111111111111111111111111111111111111111111111111111111111110111* -L017880 000000000000000000000000000000000000000000000000000000000000000000* -L017946 000000000000000000000000000000000000000000000000000000000000000000* -L018012 000000000000000000000000000000000000000000000000000000000000000000* -L018078 000000000000000000000000000000000000000000000000000000000000000000* -L018144 111111111111111111111111111111111111111111111111111101111111111111* -L018210 000000000000000000000000000000000000000000000000000000000000000000* -L018276 000000000000000000000000000000000000000000000000000000000000000000* -L018342 000000000000000000000000000000000000000000000000000000000000000000* -L018408 000000000000000000000000000000000000000000000000000000000000000000* +L017814 111111111111111111111111111111111111111111111111111111111111111111* +L017880 111111111111111111111111111111111111111111111111111111111111111111* +L017946 111111111111111111111111111111111111111111111111111111111111111111* +L018012 111111111111111111111111111111111111111111111111111111111111111111* +L018078 111111111111111111111111111111111111111111111111111111111111111111* +L018144 111101111111111111111111111111111111111111111111111111111111111111* +L018210 111111111111111111111111111111111111111111111111111111111111111111* +L018276 111111111111111111111111111111111111111111111111111111111111111111* +L018342 111111111111111111111111111111111111111111111111111111111111111111* +L018408 111111111111111111111111111111111111111111111111111111111111111111* L018474 000000000000000000000000000000000000000000000000000000000000000000* L018540 000000000000000000000000000000000000000000000000000000000000000000* -L018606 000000000000000000000000000000000000000000000000000000000000000000* -L018672 000000000000000000000000000000000000000000000000000000000000000000* -L018738 000000000000000000000000000000000000000000000000000000000000000000* -L018804 000000000000000000000000000000000000000000000000000000000000000000* -L018870 010111111111111111111011111111111111111111111111111111111111101111* -L018936 010111111110111111111011101111011111110111011111111111111111111111* -L019002 010111111110111111111011111111011111110111011111111111011111111111* -L019068 010111110110111111111011111111011111110111011111111111111111111111* -L019134 010111111110111110111011111111011111110111011111111111111111111111* +L018606 111111111111111111111111111111111111111111111111111111111111111111* +L018672 111111111111111111111111111111111111111111111111111111111111111111* +L018738 111111111111111111111111111111111111111111111111111111111111111111* +L018804 111111111111111111111111111111111111111111111111111111111111111111* +L018870 111111111111111111111111111101111111111111111111111111111111111111* +L018936 000000000000000000000000000000000000000000000000000000000000000000* +L019002 000000000000000000000000000000000000000000000000000000000000000000* +L019068 000000000000000000000000000000000000000000000000000000000000000000* +L019134 000000000000000000000000000000000000000000000000000000000000000000* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 111111111111111111111111111111111101111111111111111111111111111111* -L019332 010111111110111111111001111111011111110111011111111111111111111111* -L019398 010111111110101111111011111111011111110111011111111111111111111111* +L019266 111111111111111101111111111111111111111111111111111111111111111111* +L019332 000000000000000000000000000000000000000000000000000000000000000000* +L019398 000000000000000000000000000000000000000000000000000000000000000000* L019464 000000000000000000000000000000000000000000000000000000000000000000* L019530 000000000000000000000000000000000000000000000000000000000000000000* -L019596 011111111111111111101111111111111111111111111111111111111111111111* -L019662 000000000000000000000000000000000000000000000000000000000000000000* +L019596 011111111111111111111011111111111111111111111111111111111111011101* +L019662 011111111111111111111111111111101001111111111111111111111111111111* L019728 000000000000000000000000000000000000000000000000000000000000000000* L019794 000000000000000000000000000000000000000000000000000000000000000000* L019860 000000000000000000000000000000000000000000000000000000000000000000* @@ -448,173 +439,173 @@ L019926 L020058 0010* L020062 00100011110000* L020076 01101111110011* -L020090 11100110010100* -L020104 00100110010010* -L020118 00100011111000* -L020132 00101111110011* -L020146 00100110010111* -L020160 00100110010011* -L020174 00100011110000* -L020188 10100110010011* -L020202 00100110011110* -L020216 00100110011110* -L020230 00101011111000* -L020244 11100110011011* -L020258 00110110010001* -L020272 01100110011111* +L020090 10100110011110* +L020104 11011111110010* +L020118 11111011111000* +L020132 00110011110011* +L020146 11100110010110* +L020160 11100011110010* +L020174 00001111110001* +L020188 00000011110011* +L020202 11101011111110* +L020216 00110110011111* +L020230 00001111111001* +L020244 00100110010011* +L020258 00100110010000* +L020272 11100110011111* NOTE BLOCK 3 * L020286 - 111111011111111111111111111111111111111111111101111011111111111011 - 111011111111111101111111111111111111111111011111111111111011111111 - 111111111111111111111101111111111111011111111111111111101111111101 - 111111111111111111110111111110111011111111110111111111111111111111 - 111111111110111111111111111111101111111111111111011111111111111111 - 111111111111111111111111111111111111111101111111111111111101111111 - 111111111111111111111111011111111111111111111111111111111111011111 - 111101110111111011111111111111111111111111111111111111111111111111 - 101111111111111111011111111111111101111011111111111101111111111111* + 111111111111111111111111111111111111111111111111111111111111011111 + 111111110101111111111111111111111110111111111111111111111111111111 + 101111111111111111011101111111111111111111111110111111111111111110 + 111111111111111111111111111111111111111111110111111111111011111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111101111111101111111111111111111111111111011111111111111111111111 + 111111111111110111111111111111011111011111111111111111111111111111 + 111111111111111111111011111110110111111110111111111111111111111111 + 110111011111111111111111111111111111111111111111101111011111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 101111111111111111111111111111111111111111111111111110111111111111* -L021012 111111111111111111111011111110101111111111111111111110111111011011* -L021078 011110111111111111110111111110101111111111111111111101111101110111* +L020946 111011111111111111111111111111111111111111111111101111111111111111* +L021012 111011101111111011111011111111111111111111101111111111111111011110* +L021078 110111011111111011110111111111111111111111101111011111111011101101* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 011111111111111111111111111111111111110111011110110111111111111111* -L021342 011111111111111111111111111111111110111111111110111111111111111111* +L021276 111111111001111111111111111111011111111111111111011111111111011111* +L021342 111111111011111111111111111111111111111111111111011111101111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111111111111111111111111111111111011111111111111011111111111111* -L021738 000000000000000000000000000000000000000000000000000000000000000000* -L021804 000000000000000000000000000000000000000000000000000000000000000000* +L021672 111111011111111111111011111111111111111111111111111111111111111111* +L021738 111111011111111111111111111111111111111111111111111111111111011111* +L021804 111111101111111111110111111111111111111111111111111111111111101111* L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* -L022002 111111111111111111111111111111111111111111111111111111110111111111* -L022068 000000000000000000000000000000000000000000000000000000000000000000* -L022134 000000000000000000000000000000000000000000000000000000000000000000* -L022200 000000000000000000000000000000000000000000000000000000000000000000* -L022266 000000000000000000000000000000000000000000000000000000000000000000* +L022002 111111111111111111111111111111111111111111111111111111111111111111* +L022068 111111111111111111111111111111111111111111111111111111111111111111* +L022134 111111111111111111111111111111111111111111111111111111111111111111* +L022200 111111111111111111111111111111111111111111111111111111111111111111* +L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 111111011111110111111111111111111111111111111111111111011111111111* -L022464 111111111111111011111111111111111111111111110111111111111111111111* -L022530 111111111110110111111111111111111111111111111111111111111111111111* +L022398 111111111111111111011111111111111111111101111111111111111111111111* +L022464 111111111111111111111111111111111111111110111101111111111111111111* +L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* L022728 000000000000000000000000000000000000000000000000000000000000000000* -L022794 000000000000000000000000000000000000000000000000000000000000000000* -L022860 000000000000000000000000000000000000000000000000000000000000000000* -L022926 000000000000000000000000000000000000000000000000000000000000000000* -L022992 000000000000000000000000000000000000000000000000000000000000000000* +L022794 111111111111111111111111111111111111111111111111111111111111111111* +L022860 111111111111111111111111111111111111111111111111111111111111111111* +L022926 111111111111111111111111111111111111111111111111111111111111111111* +L022992 111111111111111111111111111111111111111111111111111111111111111111* L023058 - 111111111111110111111111011111111111111111111111111111111111111111* -L023124 011111110111111111111111111111111111111111111111111111111110111111* -L023190 011111110111111111111111111111111111111110111111111111111111111111* -L023256 011111111011111111111111111111111111111101111111111111111101111111* -L023322 011111110111111111111111111111111111111111111111011111111111111111* + 111111111111111111111111111111111111011101111111111111111111111111* +L023124 111111111111111111111111111111111111111111111111101111111111111111* +L023190 111111111111111111111111111111110111111111111011111111111111111111* +L023256 101111111111101111111111111111111101111111110111111111111111111111* +L023322 000000000000000000000000000000000000000000000000000000000000000000* L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 111111111111111111111111111111111111101111111111110111111111111111* -L023520 000000000000000000000000000000000000000000000000000000000000000000* -L023586 000000000000000000000000000000000000000000000000000000000000000000* -L023652 000000000000000000000000000000000000000000000000000000000000000000* -L023718 000000000000000000000000000000000000000000000000000000000000000000* +L023454 111111111111111111111111111111111111111111111111111111111111111111* +L023520 111111111111111111111111111111111111111111111111111111111111111111* +L023586 111111111111111111111111111111111111111111111111111111111111111111* +L023652 111111111111111111111111111111111111111111111111111111111111111111* +L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 111111111111110111111111011111111111111111111111111111111111111111* -L023850 110111111111111111111110111111111111111111111111111111111111111111* -L023916 000000000000000000000000000000000000000000000000000000000000000000* -L023982 000000000000000000000000000000000000000000000000000000000000000000* -L024048 000000000000000000000000000000000000000000000000000000000000000000* -L024114 000000000000000000000000000000000000000000000000000000000000000000* -L024180 011111111111111111111111011111111111111111111111111111111111111111* -L024246 011111110111111111111111111111111111111101111111011111111101111111* -L024312 000000000000000000000000000000000000000000000000000000000000000000* -L024378 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111011101111111111111111111111111* +L023850 111110111111111111111101111111111111111111111111111111111111111111* +L023916 111111111111111111111111111111111111111111111111111111111111111111* +L023982 111111111111111111111111111111111111111111111111111111111111111111* +L024048 111111111111111111111111111111111111111111111111111111111111111111* +L024114 111111111111111111111111111111111111111111111111111111111111111111* +L024180 111111101111110111111111111111111111111111101111111111111111111111* +L024246 111111111111110111111011111111111111111111111111111111111111111111* +L024312 111111111111110111111111111111111111111111111111111111111111011111* +L024378 111111011111111111110111111111111111111111011111111111111111101101* L024444 000000000000000000000000000000000000000000000000000000000000000000* L024510 000000000000000000000000000000000000000000000000000000000000000000* -L024576 011111111111111111111111111111111111111101111111111111111110111111* -L024642 011111111111111111111111111111111111111110111111111111111101111111* -L024708 011111110111111111111111111111111111111101111111011111111111111111* +L024576 111110111111111111111111111111111111111111111011011111111111111111* +L024642 101111111111111111111111111111111111111111110111011111111111111111* +L024708 000000000000000000000000000000000000000000000000000000000000000000* L024774 000000000000000000000000000000000000000000000000000000000000000000* L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 111111111111111111111111111111111111111111111111111111111111111101* -L024972 000000000000000000000000000000000000000000000000000000000000000000* -L025038 000000000000000000000000000000000000000000000000000000000000000000* -L025104 000000000000000000000000000000000000000000000000000000000000000000* -L025170 000000000000000000000000000000000000000000000000000000000000000000* +L024906 111111111111111111111111111111111111111111111111111111111111111111* +L024972 111111111111111111111111111111111111111111111111111111111111111111* +L025038 111111111111111111111111111111111111111111111111111111111111111111* +L025104 111111111111111111111111111111111111111111111111111111111111111111* +L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 110111111111111111101111111111111111111111111111111111111111111111* -L025368 000000000000000000000000000000000000000000000000000000000000000000* -L025434 000000000000000000000000000000000000000000000000000000000000000000* -L025500 000000000000000000000000000000000000000000000000000000000000000000* -L025566 000000000000000000000000000000000000000000000000000000000000000000* -L025632 111111111111111101111111111111111111111111111111111111111111111111* -L025698 000000000000000000000000000000000000000000000000000000000000000000* +L025302 111111111111111111111101111111111011111111111111111111111111111111* +L025368 111111111111111111111111111111111111111111111111111111111111111111* +L025434 111111111111111111111111111111111111111111111111111111111111111111* +L025500 111111111111111111111111111111111111111111111111111111111111111111* +L025566 111111111111111111111111111111111111111111111111111111111111111111* +L025632 111111111111111111111111111111111111111111011111111111111111111111* +L025698 111111011111111111110111111111111111111111111111111111111111101101* L025764 000000000000000000000000000000000000000000000000000000000000000000* L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 011111110111111111111111111111111111111101111111111111111101111111* -L026094 011111111111111111111111111111111111111111111111011111111111111111* -L026160 000000000000000000000000000000000000000000000000000000000000000000* -L026226 000000000000000000000000000000000000000000000000000000000000000000* -L026292 000000000000000000000000000000000000000000000000000000000000000000* -L026358 011111111111111111111111111111111011111111111111111111111111111111* -L026424 000000000000000000000000000000000000000000000000000000000000000000* -L026490 000000000000000000000000000000000000000000000000000000000000000000* -L026556 000000000000000000000000000000000000000000000000000000000000000000* -L026622 000000000000000000000000000000000000000000000000000000000000000000* +L026028 111111111111111111111111111101111111111111111111111111111111111111* +L026094 111111111111111111111111111111111111111111111111111111111111111111* +L026160 111111111111111111111111111111111111111111111111111111111111111111* +L026226 111111111111111111111111111111111111111111111111111111111111111111* +L026292 111111111111111111111111111111111111111111111111111111111111111111* +L026358 111111111111111111111111111111111111111111111111111111111111111111* +L026424 111111111111111111111111111111111111111111111111111111111111111111* +L026490 111111111111111111111111111111111111111111111111111111111111111111* +L026556 111111111111111111111111111111111111111111111111111111111111111111* +L026622 111111111111111111111111111111111111111111111111111111111111111111* L026688 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L026820 0010* L026824 10100111010000* L026838 11100110011110* -L026852 00100110010100* -L026866 00100110011111* -L026880 10101011111001* -L026894 00100011111111* +L026852 10100110010100* +L026866 11100011111111* +L026880 10101111111001* +L026894 00001011111111* L026908 10100110010100* -L026922 00100110010010* -L026936 01101011110011* -L026950 10100110010011* -L026964 10100110010000* -L026978 00100110010011* -L026992 01101111111011* -L027006 00100110011111* -L027020 10100110010000* -L027034 01100110010010* +L026922 11101011110011* +L026936 01110011110010* +L026950 10100110010010* +L026964 11100110010001* +L026978 11101011110011* +L026992 01111111111010* +L027006 00100110011110* +L027020 00010110010001* +L027034 11100011110011* NOTE BLOCK 4 * L027048 - 111111111111111111111111111111111111111111111111111111111111111111 - 011111111111111111111111111111011111111111111111110111110111111111 - 111111110101111111111111111111111111111111110111101111111111111111 - 111011111111111111011101111011111111111111111110111111111111111111 - 111111111111111111111111111101111111111111111111111111111111111111 - 111111111111011111111111101111111111111111111111111111111101111101 - 111111111111110111111111111111111101111111101111111101111111111111 - 111111011111111111111111111111111111111011111111111111111111100111 - 111110111111111101111011111111110111101110111111111111101111111111* + 111111111111111111111111111111110111111111111111111111111111111111 + 111111111111111111111111111111111111110111011111110111111101111111 + 111111111111101111111111110101111111111111110111111111111111111111 + 111011011111111110111111111111111111111111111111111101111111111111 + 111111111111110111111111111111111111111111111111111111111111111111 + 111111111111111111111111011111111111111111111111101111111111111101 + 101111111111111111111101111111011111111111111111111111111011010111 + 111111111101111111101011111111111101111111111110111111111111111111 + 111110110111111111111111111111111111101110111111111111101111111111* L027642 - 110111111111101101111111110111111110111011111111011110111111111101* + 110111110111011101101110101111111111111111111111111111111111111001* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 111110111111111111111111111111101111111111011111111111111111101111* -L028104 111111111111111111111111111111111111111111101111111111111111011111* +L028038 111110111111111111111111111111111111111111101110111111110111111111* +L028104 111111111111111111111111111111111111111111111101111111111011111111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 111111111111110111111111111111111111111111111111111111111111011111* -L028434 111111111111111111111111111111111111111111111111111111101111111111* + 111111111111111111111111111111111111111111111101111111111111011111* +L028434 111111111111111111110111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* L028632 111111111111111111111111111111111111111111111111111111111111111111* @@ -626,7 +617,7 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111111111111111111111111111111111111011111110111111111111111111* +L029160 111111111111111111101111111111111011111111111111111111111111111111* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* @@ -638,7 +629,7 @@ L029688 111111111111111111111111111111111111111111111111111111111111111111* L029754 111111111111111111111111111111111111111111111111111111111111111111* L029820 000000000000000000000000000000000000000000000000000000000000000000* -L029886 111111111111111111111111111111111111111111111111111111111111111111* +L029886 101111111111111111111111111111111111111111111111111111111111111111* L029952 111111111111111111111111111111111111111111111111111111111111111111* L030018 111111111111111111111111111111111111111111111111111111111111111111* L030084 111111111111111111111111111111111111111111111111111111111111111111* @@ -650,20 +641,20 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 111111111111111111111111111111111111111111111111111111011111111111* +L030612 011111111111111111111111111111111111111111111111111111111111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111111111111111111111111111111110111111111111111111111111111111111* +L030942 111111111111111111111111111111111111111111111111111111011111111111* L031008 111111111111111111111111111111111111111111111111111111111111111111* L031074 111111111111111111111111111111111111111111111111111111111111111111* L031140 111111111111111111111111111111111111111111111111111111111111111111* L031206 111111111111111111111111111111111111111111111111111111111111111111* L031272 000000000000000000000000000000000000000000000000000000000000000000* -L031338 111111011010111111101010111110111111011101111011111011111011110111* -L031404 111111111111111111111111111111011111111111111111111111111111111111* +L031338 111111101101111011111111111010101101011001111011111010111111111111* +L031404 111111111111111111111111111111111111111111011111111111111111111111* L031470 000000000000000000000000000000000000000000000000000000000000000000* L031536 000000000000000000000000000000000000000000000000000000000000000000* L031602 000000000000000000000000000000000000000000000000000000000000000000* @@ -673,13 +664,13 @@ L031800 111111111111111111111111111111111111111111111111111111111111111111* L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 - 111111111111111111111111011111111111111111111111111111111111111111* -L032064 111111011010111111101010111110111111011101111011111011111011110111* + 111111111111111111111111111111111111111111111111011111111111111111* +L032064 111111101101111011111111111010101101011001111011111010111111111111* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* L032328 111111111111111111111111111111111111111111111111111111111111111111* -L032394 011111111111111111111111111111111111111111111111111111111111111111* +L032394 111111111111111111111111111111111111111111111111111111111111111111* L032460 111111111111111111111111111111111111111111111111111111111111111111* L032526 111111111111111111111111111111111111111111111111111111111111111111* L032592 111111111111111111111111111111111111111111111111111111111111111111* @@ -706,250 +697,250 @@ L033614 00010110010100* L033628 11101111110010* L033642 01111011111000* L033656 00000110011111* -L033670 11011011110000* -L033684 11110011111110* +L033670 00010110010000* +L033684 11101111111110* L033698 00110110010001* L033712 00000110011111* -L033726 10101111110000* -L033740 11100011111110* -L033754 00111011110001* -L033768 00000110011111* -L033782 11010111111100* -L033796 11111111111111* +L033726 10101011110000* +L033740 11101111111110* +L033754 00110011110000* +L033768 11001011111111* +L033782 11110111111100* +L033796 11111111111110* NOTE BLOCK 5 * L033810 - 011111111111101111111111111111111110111101110111101111111111111111 - 111111111111111110111111111111011111111011111101111111111111111110 - 111110111111111111111110111111111111111111111111111111101111111011 - 111111111111111111101011111111111111011111111111111111111111111111 - 111111111110111111111111110111111111111111111111111111111111101111 - 111111111111111111111111111111111111111111111111111111111101111111 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111110111111111111111111110111110111111111 - 111011111111111111111111101111110111111111101111111101111111111111* + 111111111111101111111101111111111111111111111111111111111111111111 + 111110111101111111111111011111111111101111111111111111111111111111 + 111011111111111110111111111110111111111110111111111111011111111111 + 111111111111111111101111111111111111111111111011111111111111111101 + 111111111111111111111111111111111111111111111111111011111111101111 + 111111111111111111111111111111111111111111011111111111111111111111 + 111111111111110111111111111111111111111111111111111111111111111111 + 111111111111111111111011111111111111111111111111111111111111111111 + 101111011111111111111111110111101110111111111111111101111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111011111111111111011111101111110101111011111101110101001011111* -L034536 111111011111111111111111111101111111111111011011101111100101111111* -L034602 111110011111101111111011111101111110101111011111101110101011011111* -L034668 111110011111101111111111111101111111111111011011101111100111111111* -L034734 111111011111111111101111111111111111111111011111101111101101111111* -L034800 111110011111101111101111111111111111111111011111101111101111111111* -L034866 111111111111111111111010111101111110101011011110101110101001011111* -L034932 111111111111111111111110111101111111111011011010101111100101111111* -L034998 111110111111101111111010111101111110101011011110101110101011011111* -L035064 111110111111101111111110111101111111111011011010101111100111111111* +L034470 011111111111111111111011111111111111111111111111110111111111111111* +L034536 011111111111111111111101111111111111111111111111110111111111111111* +L034602 011111111111111111110110111111111111111111111111111011111111111111* +L034668 011111111111011111111111111111111111011111111111110111111111111111* +L034734 000000000000000000000000000000000000000000000000000000000000000000* +L034800 010111111111111111111001111111111111111111111111111111111111111111* +L034866 011111111111111111111011111111111101111111111111111111111111011111* +L034932 011111111111111111111101111111111101111111111111111111111111011111* +L034998 000000000000000000000000000000000000000000000000000000000000000000* +L035064 000000000000000000000000000000000000000000000000000000000000000000* L035130 000000000000000000000000000000000000000000000000000000000000000000* -L035196 111111111111111111101110111111111111111011011110101111101101111111* -L035262 111110111111101111101110111111111111111011011110101111101111111111* -L035328 110111101111111111111111111111111111111111011111101111111111111111* -L035394 110111111111111111111111111111111111111111011111101111101111111111* -L035460 000000000000000000000000000000000000000000000000000000000000000000* -L035526 111111111111111111111111111111111111111101111111111111111111111111* -L035592 111111111111111111111011111111111111101111111111111111111111011111* -L035658 111111111111111111110111111101111101011111111111111111111111111111* -L035724 111111111111111111111111111110111111111111111111111111111111011111* -L035790 000000000000000000000000000000000000000000000000000000000000000000* +L035196 011111111111111111111111111011111111111111111111111111111111111111* +L035262 111111111111111111111111111111111111111111111111111111111111111111* +L035328 111111111111111111111111111111111111111111111111111111111111111111* +L035394 111111111111111111111111111111111111111111111111111111111111111111* +L035460 111111111111111111111111111111111111111111111111111111111111111111* +L035526 011111111111111111111001011111111110111111111111111111111111111111* +L035592 011010111111111111111001101110111101111111110111111111111111101110* +L035658 011010111110111111111111101110111101111111111011111111111111101110* +L035724 011010111111111111111111101110111101111111111011111111011111101110* +L035790 011010111111111111110111101110111101111111111011111111111111101110* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 111111111111111111011111111111111111111111101111111111111111111111* -L035988 111111111111111111011011111101111110101011111111111110111011011111* -L036054 111111111111111111011111111101111111111011111011111111110111111111* -L036120 111111011111111111101111111111111111110111011111111111111111111111* -L036186 111011111111111111011111111111111111111111111111111111111111111111* -L036252 111111111111111111110111111111111111101111111111111111111111111111* -L036318 111111111111111111110111111111111110111111111111111111111111111111* -L036384 111111111111111111111011111101111101011111111111111111111111111111* -L036450 111111111111111111110111111110111111111111111111111111111111111111* +L035922 011111111111111111111111111111111101111111111111111111111111111111* +L035988 011010111111111111111111101110101101111111111011111111111111101110* +L036054 011111111111111111111001111111111110111111111111111111111111111101* +L036120 011111111111111111110110111111111110111111111111111111111111011111* +L036186 011111111111111111110110111101111110111111111111111111111111111111* +L036252 011101101111110111100110111111111110111110101111111110111111111111* +L036318 011101111111111110010110111111111110111111111111111111111111111111* +L036384 010111111111111111111001111111111110111111111111111111111111111111* +L036450 011010111101111111111011101110011110111111111011111111101111101110* L036516 000000000000000000000000000000000000000000000000000000000000000000* L036582 000000000000000000000000000000000000000000000000000000000000000000* -L036648 111111111111111111011011111101111110101111011111111110111011011111* -L036714 111111111111111111011111111101111111111111011011111111110111111111* -L036780 111111111111111111011101111111111111111111011111111111111111111111* -L036846 110111101111111111111101111111111111111111011111111111111111111111* +L036648 011101101111110111100110111111111111111110101111111110111111111111* +L036714 011101111111111110010110111111111111111111111111111111111111111111* +L036780 010111111111111111110111111111111101111111111111111111111111111111* +L036846 010111111111111111111110111111111101111111111111111111111111111111* L036912 000000000000000000000000000000000000000000000000000000000000000000* -L036978 111111111111111111111111111111111111111111111111110111111111111111* -L037044 111111111111011111111111111111111111111111011111111111101101111111* -L037110 110111101111111111111111111111111111111111011111111111011111111111* +L036978 011111111111111111111001111111111111111111111111111111111111111101* +L037044 011111111111111111111011111101111101111111111111111111111111111111* +L037110 011111111111111111111101111101111101111111111111111111111111111111* L037176 000000000000000000000000000000000000000000000000000000000000000000* L037242 000000000000000000000000000000000000000000000000000000000000000000* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 111110011111111111111111111111111111111111011101111111111111111111* -L037440 110101111111111111111111111111111111111111011111111111111110111111* -L037506 110101111111111111111111111111111111111111011101111111111111111111* -L037572 000000000000000000000000000000000000000000000000000000000000000000* +L037374 111111101111111111111111111111111111111101111111111111111111111111* +L037440 111111111111111111111011111111111111111101111111111111111111111111* +L037506 111111111111111111111101111111111111111101111111111111111111111111* +L037572 111111011111111011110110111111111111111110111111111111111111111111* L037638 000000000000000000000000000000000000000000000000000000000000000000* -L037704 111110011101111111111111111111111111111111011110111111101111111111* -L037770 111110111101111111111111111111111111111011011110111111101111111111* -L037836 110111111111111111111111101111111111111111011111111111111111111101* -L037902 111111011101111101111111111111111111111111011110111111101111111111* -L037968 111111111101111101111111111111111111111011011110111111101111111111* +L037704 011111111111011111110110111111111111111111111111110111111111111111* +L037770 011111111111111111111111111111111111011111111111111111111111111111* +L037836 000000000000000000000000000000000000000000000000000000000000000000* +L037902 000000000000000000000000000000000000000000000000000000000000000000* +L037968 000000000000000000000000000000000000000000000000000000000000000000* L038034 000000000000000000000000000000000000000000000000000000000000000000* -L038100 111101111111111111111111111111111111110111011111111111111111111111* -L038166 111101111111111111111111111111111111111111011111111111111101111111* -L038232 110111101111111111111111111111111111110111011111111111111111111111* -L038298 000000000000000000000000000000000000000000000000000000000000000000* -L038364 000000000000000000000000000000000000000000000000000000000000000000* -L038430 111111111111111111111111110111111111111111111111111111111111111111* -L038496 000000000000000000000000000000000000000000000000000000000000000000* -L038562 000000000000000000000000000000000000000000000000000000000000000000* -L038628 000000000000000000000000000000000000000000000000000000000000000000* -L038694 000000000000000000000000000000000000000000000000000000000000000000* +L038100 011101111111111111111111111111111101111111111111111111111111111111* +L038166 011110111111111111111001011111111111111111111111111111111111111111* +L038232 011101101111110111100110111111111101111110101111111110111111111111* +L038298 011101111111111110010110111111111101111111111111111111111111111111* +L038364 011111111111111111111001011111111110111111111111111111111111111111* +L038430 111111111111111111111111111111111111111111111111111111111111111111* +L038496 111111111111111111111111111111111111111111111111111111111111111111* +L038562 111111111111111111111111111111111111111111111111111111111111111111* +L038628 111111111111111111111111111111111111111111111111111111111111111111* +L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 111111111111111111111111111111111101101111111111111111111111111111* -L038892 111111111111111111111111111101111110011111111111111111111111101111* -L038958 111111111111111111111111111110111101111111111111111111111111111111* -L039024 000000000000000000000000000000000000000000000000000000000000000000* -L039090 000000000000000000000000000000000000000000000000000000000000000000* -L039156 111111011111101111111101111111111111111111011111111111111111111111* -L039222 110111111111011111111111111111111111111111011111111111111110111111* -L039288 110111111111011111111101111111111111111111011111111111111111111111* +L038826 111111111111111111111111111111111111111111111111111111111111111111* +L038892 111111111111111111111111111111111111111111111111111111111111111111* +L038958 111111111111111111111111111111111111111111111111111111111111111111* +L039024 111111111111111111111111111111111111111111111111111111111111111111* +L039090 111111111111111111111111111111111111111111111111111111111111111111* +L039156 011111111111011111111111111111111111111111111111111111111111111111* +L039222 011111111111111111110110111111111111101111111111110111111111111111* +L039288 011111111111101111110110111111111111111111111111110111111111111111* L039354 000000000000000000000000000000000000000000000000000000000000000000* L039420 000000000000000000000000000000000000000000000000000000000000000000* L039486 000000000000000000000000000000000000000000000000000000000000000000* -L039552 111110111111101111101110111111101111111011111110111111101111111111* -L039618 011110111111101111101110111111111111111011111110111111101111111111* -L039684 111110111111101111101110111111111011111011111110111111101111111111* -L039750 000000000000000000000000000000000000000000000000000000000000000000* -L039816 000000000000000000000000000000000000000000000000000000000000000000* -L039882 111111111111111111111111111111111111111111011111111111111111111011* -L039948 000000000000000000000000000000000000000000000000000000000000000000* -L040014 000000000000000000000000000000000000000000000000000000000000000000* -L040080 000000000000000000000000000000000000000000000000000000000000000000* -L040146 000000000000000000000000000000000000000000000000000000000000000000* +L039552 111111111111111111111111111111111111111111111111111111111111111111* +L039618 111111111111111111111111111111111111111111111111111111111111111111* +L039684 111111111111111111111111111111111111111111111111111111111111111111* +L039750 111111111111111111111111111111111111111111111111111111111111111111* +L039816 111111111111111111111111111111111111111111111111111111111111111111* +L039882 111111111111111111111111111111111111111111111111111111111111111111* +L039948 111111111111111111111111111111111111111111111111111111111111111111* +L040014 111111111111111111111111111111111111111111111111111111111111111111* +L040080 111111111111111111111111111111111111111111111111111111111111111111* +L040146 111111111111111111111111111111111111111111111111111111111111111111* L040212 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* L040348 10100110011110* -L040362 10110110010010* -L040376 10000111011110* -L040390 00000110010011* -L040404 10000110011111* +L040362 10100110010010* +L040376 01010110011110* +L040390 11010011110011* +L040404 00100110011111* L040418 10110110010011* L040432 10100110011110* -L040446 00000110010010* -L040460 10100110011110* +L040446 11001111110011* +L040460 10100110011111* L040474 10100110010011* -L040488 10100110011111* -L040502 00100110011111* -L040516 10100110011110* -L040530 10100110011110* -L040544 10101111111110* -L040558 01100110011111* +L040488 00100110011110* +L040502 11011011111110* +L040516 11111111111110* +L040530 00100110011111* +L040544 11000011111110* +L040558 11111011111110* NOTE BLOCK 6 * L040572 - 111111111111111111111110111101111110111111111111111111111111111111 - 111111111111110111101111111111011111111111111111111111101111111111 - 111110111111111111111111111111111111011111111111111111111011111111 - 111111111001111111111111111111111111111111111011111111111110111111 - 101111111111111111111011111111111111111111111111111111111111111111 - 111111011111111111111111110111111111111011111111111111111111111111 - 111111111111101110111111111111111111111111111111010111111111111111 - 111111111111111111111111111111111111111101111111111111111111101111 - 111011111111111111111111101111111111111111101111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111011111 + 111111111111111111111111101111011111111111111011111111111111111111 + 111110111110111111111111111011111111111111111111111111111111111111 + 111111111011111111111111111111111111111111111111111111111111111110 + 111111101111111111111011111111111110111101111111111111111111111111 + 111111111111111011111111111111111111111111011111111111111111111111 + 111111111111101111011111111111111011011111111111110111011111111111 + 101111111111111101111110111111111111111111111111111111111111111111 + 111011111111111111111111111111111111111111111110101111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 101111111111111111111111111111111111110111011111111111111111011111* -L041298 111111111111101111111111111111111111111111011111111111111111101111* +L041232 011111111111110111111111111111111110111111111111011111111111111111* +L041298 101111111111101111111111111111111111111111111111011111111111111111* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111111111111111101111111111111111111111111111111111111111111111111* +L041562 111111111111111111111111111111110111111111111111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111101111111111111111111111111111111111111011111111111111111111111* -L042024 110111111011111111111111101111111111111111011111111111111111111111* -L042090 000000000000000000000000000000000000000000000000000000000000000000* +L041958 011111111111111011111111111111111111111111111111011111111111111111* +L042024 011111111011111111111111111111111111111111111111011111111111111111* +L042090 101111111111111110111111111111111111111111111111011111101111111111* L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* -L042288 111111111111110111111111111111111111111111111111111111111111111111* +L042288 111111111111111111111111111111111111111101111111111111111111111111* L042354 000000000000000000000000000000000000000000000000000000000000000000* L042420 000000000000000000000000000000000000000000000000000000000000000000* L042486 000000000000000000000000000000000000000000000000000000000000000000* L042552 000000000000000000000000000000000000000000000000000000000000000000* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111111111111111111011111111111101111111111111111111111101111111* -L042750 111111111111111111110111111111111110111111111111111111111110111111* +L042684 111101111111111111111111111111111111111111011111111011111111111111* +L042750 111110111111111111111111111111111111111111101111110111111111111111* L042816 000000000000000000000000000000000000000000000000000000000000000000* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111111111111111111111111111111111111111111101111111111111111111111* -L043080 111111111111111111111111111111111111110111110111111111111111011111* -L043146 111111111111111111111111111111111111111110111111101111111111101111* +L043014 111111111111111111110101111111111111111111111111011111111111101111* +L043080 110111111111111111111101111111111111111111111111011111111111111101* +L043146 110111111111111111111111111111111111111111111111011111111111101101* L043212 000000000000000000000000000000000000000000000000000000000000000000* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 111111111101111111111111111111111111111111111111111111111111111111* -L043476 000000000000000000000000000000000000000000000000000000000000000000* +L043410 101111101111111111111111111111111111111111111111011111111111111111* +L043476 011111111110110111111111111111111111111111111111011111111111111111* L043542 000000000000000000000000000000000000000000000000000000000000000000* L043608 000000000000000000000000000000000000000000000000000000000000000000* L043674 000000000000000000000000000000000000000000000000000000000000000000* -L043740 111111111111111111011111111111111111111111111111111111111111111111* +L043740 111111111111111111101111111111111111111111111111011111111111111111* L043806 000000000000000000000000000000000000000000000000000000000000000000* L043872 000000000000000000000000000000000000000000000000000000000000000000* L043938 000000000000000000000000000000000000000000000000000000000000000000* L044004 000000000000000000000000000000000000000000000000000000000000000000* L044070 - 111111111111111111111111111111101111111111111111110111111111101111* -L044136 111111111111111111111111111111111111111111101111111111111111111111* -L044202 111111111111111111111111111111111111110111111111111111110111011111* -L044268 111111111111111111111111111111111111111101111111111111111111101111* + 101111111111111111111111111111101111011111111111111111111111111111* +L044136 111111111111111111111111111111111111111111111111101111111111111111* +L044202 011111111111110111111111110111111111111111111111111111111111111111* +L044268 101111111111111101111111111111111111111111111111111111111111111111* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 111111111111111111111111111111111111111011011111111111111111011111* -L044532 111111111111111111111111111111111111111111011111111111101111011111* -L044598 111111111111111111111111111111111111111110011111101111111111101111* +L044466 111111111111111111111111111111111111111111111111101111111111111111* +L044532 011111111111110111111111011111111111111111111111111111111111111111* +L044598 101111111111111110111111111111111111111111111111111111101111111111* L044664 000000000000000000000000000000000000000000000000000000000000000000* L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 - 111111111111111111111111111111101111111111111111111111111111101111* -L044862 111111111111111111111101111111111111111111111111111111111111111111* -L044928 000000000000000000000000000000000000000000000000000000000000000000* + 101111111111111111111111111111101111111111111111111111111111111111* +L044862 101111011111111111111111111111111111111111111111011111111111111111* +L044928 011111111111110111111111111111111111111111111011011111111111111111* L044994 000000000000000000000000000000000000000000000000000000000000000000* L045060 000000000000000000000000000000000000000000000000000000000000000000* L045126 000000000000000000000000000000000000000000000000000000000000000000* -L045192 111111111111111111111111111111111111011111111111111111111111111111* -L045258 000000000000000000000000000000000000000000000000000000000000000000* -L045324 000000000000000000000000000000000000000000000000000000000000000000* -L045390 000000000000000000000000000000000000000000000000000000000000000000* -L045456 000000000000000000000000000000000000000000000000000000000000000000* +L045192 111111111111111111111111111111111111111111111111111111111111111111* +L045258 111111111111111111111111111111111111111111111111111111111111111111* +L045324 111111111111111111111111111111111111111111111111111111111111111111* +L045390 111111111111111111111111111111111111111111111111111111111111111111* +L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 - 111111111111111111111111111111111111111111111111110111111111101111* -L045588 111111111111111111111111111111111111111111111011111111011111111111* -L045654 000000000000000000000000000000000000000000000000000000000000000000* -L045720 000000000000000000000000000000000000000000000000000000000000000000* -L045786 000000000000000000000000000000000000000000000000000000000000000000* -L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 111111111111111111111111111101111111111111111111111111111111111111* -L045984 000000000000000000000000000000000000000000000000000000000000000000* -L046050 000000000000000000000000000000000000000000000000000000000000000000* -L046116 000000000000000000000000000000000000000000000000000000000000000000* -L046182 000000000000000000000000000000000000000000000000000000000000000000* + 101111111111111111111111111111111111011111111111111111111111111111* +L045588 111111110111111111111111101111111111111111111111111111111111111111* +L045654 111111111111111111111111111111111111111111111111111111111111111111* +L045720 111111111111111111111111111111111111111111111111111111111111111111* +L045786 111111111111111111111111111111111111111111111111111111111111111111* +L045852 111111111111111111111111111111111111111111111111111111111111111111* +L045918 111111111111111111111111111111111111111111111111111111111111111111* +L045984 111111111111111111111111111111111111111111111111111111111111111111* +L046050 111111111111111111111111111111111111111111111111111111111111111111* +L046116 111111111111111111111111111111111111111111111111111111111111111111* +L046182 111111111111111111111111111111111111111111111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111111111110111111111111111111111111111111111111111* -L046380 000000000000000000000000000000000000000000000000000000000000000000* -L046446 000000000000000000000000000000000000000000000000000000000000000000* -L046512 000000000000000000000000000000000000000000000000000000000000000000* -L046578 000000000000000000000000000000000000000000000000000000000000000000* -L046644 111111011111111111111111111111111111111111111111111111111111111111* -L046710 000000000000000000000000000000000000000000000000000000000000000000* -L046776 000000000000000000000000000000000000000000000000000000000000000000* -L046842 000000000000000000000000000000000000000000000000000000000000000000* -L046908 000000000000000000000000000000000000000000000000000000000000000000* +L046314 111111111111111111111111111111111111111111111101111111111111111111* +L046380 111111111111111111111111111111111111111111111111111111111111111111* +L046446 111111111111111111111111111111111111111111111111111111111111111111* +L046512 111111111111111111111111111111111111111111111111111111111111111111* +L046578 111111111111111111111111111111111111111111111111111111111111111111* +L046644 111111111111111111111111111111111111111111111111111111111111111111* +L046710 111111111111111111111111111111111111111111111111111111111111111111* +L046776 111111111111111111111111111111111111111111111111111111111111111111* +L046842 111111111111111111111111111111111111111111111111111111111111111111* +L046908 111111111111111111111111111111111111111111111111111111111111111111* L046974 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* @@ -960,90 +951,90 @@ L047138 11100110010100* L047152 00100110011111* L047166 10101011111001* L047180 10100110010011* -L047194 00100110010000* -L047208 00100110010010* +L047194 11100110010000* +L047208 01100110010010* L047222 10100110010001* -L047236 11100110010011* -L047250 00100110010100* -L047264 00100110010010* -L047278 00100011110010* -L047292 00100110010011* -L047306 00100110010001* -L047320 00100110011111* +L047236 10100110010011* +L047250 11100110010100* +L047264 11100011110010* +L047278 00111011110010* +L047292 11001111110011* +L047306 00110110010001* +L047320 11000011111111* NOTE BLOCK 7 * L047334 - 111111111111111111111111111111101111111111111111111111111011101111 - 111111111101111111111011111111111111111111111111111011111111111111 - 111111111111101111111111111110111111111110111111111111111111111111 - 111111111111111111111111101011111111111111111011111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111011 - 111111111111111111111111111111111111101111111111011111011111111101 - 111111011111110111111110111111111001111111111111111101111111111111 - 111111111111111111101111111111111111111111101111111111111111111111 - 101010111011111101111111111111111111111011111110111111111111111111* + 011111111111110111111111111111111111111111111111111110111011111111 + 111111111111111111111011111111011111111111111111111011111111111111 + 111111111111111111111111111111111111111111111111101111111111111111 + 111101101111111111111111101010111111111111111111111111111111111011 + 111111111111111111111111111111111111111111111111111111111111101111 + 111111110111111111011111111111111111111111111111111111011111111111 + 111111111110011110111111111111111101011111110111111111111111111111 + 111111111111111111111110111111111111111110111111111111111111111110 + 111011111111111111111111111111111011111011101110111111111101111111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 011111101111111111111111111111111111111110111110111111111111110111* -L048060 011111111111111111111111111110111111111110111110111111111111110111* -L048126 011111111111111111111111111111111111111101111111111011111111111111* +L047994 111111111111110111111111111111111111111111111111111111111111111111* +L048060 000000000000000000000000000000000000000000000000000000000000000000* +L048126 000000000000000000000000000000000000000000000000000000000000000000* L048192 000000000000000000000000000000000000000000000000000000000000000000* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 011111111111111111101111111111111111111111111111111111111111111111* -L048390 000000000000000000000000000000000000000000000000000000000000000000* -L048456 000000000000000000000000000000000000000000000000000000000000000000* -L048522 000000000000000000000000000000000000000000000000000000000000000000* +L048324 111111111111111111111101111101111111111011011111111111111111111111* +L048390 101111111111111111111111111101111111111011011111111111111111111111* +L048456 111110101111111111111111111101111111111011011111111111111111111111* +L048522 011101101111111111111110111101111111111111011111111011111111111111* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111111111111111111011111111111111111111111111111* +L048720 111111111111111111111111111111111111111111111111111111111111111111* L048786 111111111111111111111111111111111111111111111111111111111111111111* L048852 111111111111111111111111111111111111111111111111111111111111111111* L048918 111111111111111111111111111111111111111111111111111111111111111111* L048984 111111111111111111111111111111111111111111111111111111111111111111* -L049050 111111111111111111111111111111111111111111111111111111111111111111* +L049050 011111111111111111111111111111111111111111111111111111111111111111* L049116 111111111111111111111111111111111111111111111111111111111111111111* L049182 111111111111111111111111111111111111111111111111111111111111111111* L049248 111111111111111111111111111111111111111111111111111111111111111111* L049314 111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111111111011110101111010111111110111111111111111110101111111101* -L049512 111111111111111111111111111111111111111111111111111111111111111111* -L049578 111111111111111111111111111111111111111111111111111111111111111111* -L049644 111111111111111111111111111111111111111111111111111111111111111111* -L049710 111111111111111111111111111111111111111111111111111111111111111111* -L049776 111111111111111111111111111111111111111111111111111111111111111111* +L049446 111111111111111111111111111111111111111111101111111111111111111111* +L049512 111111110111111111111111111111111111111101111111111111111111111111* +L049578 011111110111111111111110111111110111111111111111111111111111111111* +L049644 000000000000000000000000000000000000000000000000000000000000000000* +L049710 000000000000000000000000000000000000000000000000000000000000000000* +L049776 111111110111101111111111010111111110111111111111011111101110111110* L049842 111111111111111111111111111111111111111111111111111111111111111111* L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 - 111111111110110111111111111111111111111111101111111111111111111111* -L050172 101111111111111111111111111111111111111111111111111111111111111111* -L050238 111111111111111111111111111111111111111111011111111111111111111101* -L050304 111101011111111111111111111111111111111111111111111111111111111101* -L050370 000000000000000000000000000000000000000000000000000000000000000000* -L050436 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111101111011110111111111111111111111111* +L050172 111111111111111111111111111111111111111111111111111111111111111111* +L050238 111111111111111111111111111111111111111111111111111111111111111111* +L050304 111111111111111111111111111111111111111111111111111111111111111111* +L050370 111111111111111111111111111111111111111111111111111111111111111111* +L050436 111111111111111111111111111111111111111111111111111111111111111111* L050502 111111111111111111111111111111111111111111111111111111111111111111* L050568 111111111111111111111111111111111111111111111111111111111111111111* L050634 111111111111111111111111111111111111111111111111111111111111111111* L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 - 111111111101111111111111111111111111111111111111111111111111111111* -L050898 111110111111111111111111111111111111111111111111101111111111111111* + 111111111111111111111111111111011111111111111111111111111111111111* +L050898 111111111111111111101111111111111011111111111111111111111111111111* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 011111111111111111111111111111011111011111111111111111111011101111* -L051294 011111111111111111111111111111010111011111111111111111111111101111* -L051360 011111110111111111111111111111011111101111111111111111111111111111* -L051426 010111111111111111111110111111111111111011111111111111111111111111* +L051228 111111111111111011111111111111111111111111011101111111111011011111* +L051294 111111111111111001111111111111111111111111011101111111111111011111* +L051360 111111111111111111111111111111111111111111011110111101111111011111* +L051426 110111111110111111111111111111111111111111011011111111111111111111* L051492 000000000000000000000000000000000000000000000000000000000000000000* L051558 - 111111111111110111111111111111111111111111011111111111111111111111* -L051624 111111111111111111111111111111111111111111111111111111111111011111* + 111111111111111111111111111111111111011101111111111111111111111111* +L051624 111111111111111111111111111111111111111111111111111111111111111111* L051690 111111111111111111111111111111111111111111111111111111111111111111* L051756 111111111111111111111111111111111111111111111111111111111111111111* L051822 111111111111111111111111111111111111111111111111111111111111111111* @@ -1054,13 +1045,13 @@ L052086 111111111111111111111111111111111111111111111111111111111111111111* L052152 111111111111111111111111111111111111111111111111111111111111111111* L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 - 111111111110111111111111111111111111111111101111111111111111111111* -L052350 111111111111111111111011111111111111111111110111111111111111111111* + 111111111111111111111111111111101111111110111111111111111111111111* +L052350 111111111111111111110111111111111111111111111111111111111111111011* L052416 111111111111111111111111111111111111111111111111111111111111111111* L052482 111111111111111111111111111111111111111111111111111111111111111111* L052548 111111111111111111111111111111111111111111111111111111111111111111* L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 011111111111111111111111111111111111111111101111111111111111111111* +L052680 111111111111111111111111111111111111111110011111111111111111111111* L052746 111111111111111111111111111111111111111111111111111111111111111111* L052812 111111111111111111111111111111111111111111111111111111111111111111* L052878 111111111111111111111111111111111111111111111111111111111111111111* @@ -1081,22 +1072,22 @@ L053736 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L053868 0010* -L053872 11100110011000* -L053886 01100110010010* -L053900 00010110010000* -L053914 11100011110011* -L053928 01111111110101* -L053942 11001011111111* -L053956 10100110010100* -L053970 11001011110011* -L053984 01110011111000* -L053998 11100110011110* -L054012 00010110010111* -L054026 11101011110011* -L054040 00111111110000* +L053872 00100110010000* +L053886 11100110010010* +L053900 11101111110000* +L053914 00110110010011* +L053928 10100110010000* +L053942 01010011111110* +L053956 11011111110100* +L053970 11111011110011* +L053984 01110011111001* +L053998 11100110011111* +L054012 11011011111110* +L054026 11111111110011* +L054040 00110011110000* L054054 01000110010010* -L054068 11010011110111* -L054082 11111011111111* +L054068 11011011111111* +L054082 11111111111111* E1 1 01111100 @@ -1116,6 +1107,6 @@ E1 10000010 1 * -CB4EF* +C4245* U00000000000000000000000000000000* -5630 +C4D1 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 10aa91b..f8c2440 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -17,7 +17,7 @@ Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; DATE = 8/19/16; -TIME = 00:20:46; +TIME = 00:39:40; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,16 +76,9 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -A_DECODE_22_ = pin,84,-,H,-; -A_DECODE_21_ = pin,94,-,A,-; SIZE_1_ = pin,79,-,H,-; -A_DECODE_20_ = pin,93,-,A,-; -A_DECODE_19_ = pin,97,-,A,-; AHIGH_31_ = pin,4,-,B,-; -A_DECODE_18_ = pin,95,-,A,-; -A_DECODE_17_ = pin,59,-,F,-; A_DECODE_23_ = pin,85,-,H,-; -A_DECODE_16_ = pin,96,-,A,-; IPL_2_ = pin,68,-,G,-; FC_1_ = pin,58,-,F,-; AS_030 = pin,82,-,H,-; @@ -96,21 +89,32 @@ LDS_000 = pin,31,-,D,-; nEXP_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; -IPL_1_ = pin,56,-,F,-; -IPL_0_ = pin,67,-,G,-; +SIZE_0_ = pin,70,-,G,-; +AHIGH_30_ = pin,5,-,B,-; BGACK_000 = pin,28,-,D,-; -FC_0_ = pin,57,-,F,-; +AHIGH_29_ = pin,6,-,B,-; CLK_030 = pin,64,-,-,-; -A_1_ = pin,60,-,F,-; +AHIGH_28_ = pin,15,-,C,-; CLK_000 = pin,11,-,-,-; +AHIGH_27_ = pin,16,-,C,-; CLK_OSZI = pin,61,-,-,-; +AHIGH_26_ = pin,17,-,C,-; CLK_DIV_OUT = pin,65,-,G,-; +AHIGH_25_ = pin,18,-,C,-; +AHIGH_24_ = pin,19,-,C,-; FPU_CS = pin,78,-,H,-; +A_DECODE_22_ = pin,84,-,H,-; FPU_SENSE = pin,91,-,A,-; +A_DECODE_21_ = pin,94,-,A,-; +A_DECODE_20_ = pin,93,-,A,-; DTACK = pin,30,-,D,-; +A_DECODE_19_ = pin,97,-,A,-; AVEC = pin,92,-,A,-; +A_DECODE_18_ = pin,95,-,A,-; E = pin,66,-,G,-; +A_DECODE_17_ = pin,59,-,F,-; VPA = pin,36,-,-,-; +A_DECODE_16_ = pin,96,-,A,-; RST = pin,86,-,-,-; RESET = pin,3,-,B,-; AMIGA_ADDR_ENABLE = pin,33,-,D,-; @@ -118,103 +122,73 @@ AMIGA_BUS_DATA_DIR = pin,48,-,E,-; AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; CIIN = pin,47,-,E,-; -SIZE_0_ = pin,70,-,G,-; -AHIGH_30_ = pin,5,-,B,-; -AHIGH_29_ = pin,6,-,B,-; -AHIGH_28_ = pin,15,-,C,-; -AHIGH_27_ = pin,16,-,C,-; -AHIGH_26_ = pin,17,-,C,-; -AHIGH_25_ = pin,18,-,C,-; -AHIGH_24_ = pin,19,-,C,-; +IPL_1_ = pin,56,-,F,-; +IPL_0_ = pin,67,-,G,-; +FC_0_ = pin,57,-,F,-; +A_1_ = pin,60,-,F,-; IPL_030_2_ = pin,9,-,B,-; RW_000 = pin,80,-,H,-; -A_0_ = pin,69,-,G,-; -IPL_030_1_ = pin,7,-,B,-; -IPL_030_0_ = pin,8,-,B,-; BG_000 = pin,29,-,D,-; BGACK_030 = pin,83,-,H,-; CLK_EXP = pin,10,-,B,-; DSACK1 = pin,81,-,H,-; VMA = pin,35,-,D,-; RW = pin,71,-,G,-; -N_226 = node,-,-,F,14; -cpu_est_2_ = node,-,-,F,4; -cpu_est_3_ = node,-,-,F,1; -cpu_est_0_ = node,-,-,B,2; -cpu_est_1_ = node,-,-,F,12; -inst_AS_000_INT = node,-,-,G,2; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,10; -inst_AS_030_D0 = node,-,-,H,1; -inst_AS_030_000_SYNC = node,-,-,C,13; +A_0_ = pin,69,-,G,-; +IPL_030_1_ = pin,7,-,B,-; +IPL_030_0_ = pin,8,-,B,-; +cpu_est_3_ = node,-,-,D,9; +cpu_est_0_ = node,-,-,D,2; +cpu_est_1_ = node,-,-,F,8; +cpu_est_2_ = node,-,-,D,13; +inst_AS_000_INT = node,-,-,C,15; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,10; +inst_AS_030_D0 = node,-,-,A,6; +inst_AS_030_000_SYNC = node,-,-,C,6; inst_BGACK_030_INT_D = node,-,-,H,13; inst_AS_000_DMA = node,-,-,A,12; -inst_DS_000_DMA = node,-,-,A,9; -CYCLE_DMA_0_ = node,-,-,A,10; -CYCLE_DMA_1_ = node,-,-,A,2; -SIZE_DMA_0_ = node,-,-,G,9; -SIZE_DMA_1_ = node,-,-,G,5; -inst_VPA_D = node,-,-,A,5; -inst_UDS_000_INT = node,-,-,B,6; -inst_LDS_000_INT = node,-,-,A,1; +inst_DS_000_DMA = node,-,-,A,1; +CYCLE_DMA_0_ = node,-,-,A,13; +CYCLE_DMA_1_ = node,-,-,A,9; +SIZE_DMA_0_ = node,-,-,G,2; +SIZE_DMA_1_ = node,-,-,G,9; +inst_VPA_D = node,-,-,F,2; +inst_UDS_000_INT = node,-,-,D,10; +inst_LDS_000_INT = node,-,-,D,6; inst_CLK_OUT_PRE_D = node,-,-,E,8; -CLK_000_D_10_ = node,-,-,G,15; -CLK_000_D_11_ = node,-,-,H,10; -inst_DTACK_D0 = node,-,-,C,15; -inst_RESET_OUT = node,-,-,D,9; -inst_CLK_OUT_PRE_50 = node,-,-,E,2; -CLK_000_D_1_ = node,-,-,C,6; -CLK_000_D_0_ = node,-,-,G,13; -CLK_000_P_SYNC_10_ = node,-,-,A,8; -SM_AMIGA_5_ = node,-,-,F,8; -IPL_D0_0_ = node,-,-,D,15; -IPL_D0_1_ = node,-,-,F,15; -IPL_D0_2_ = node,-,-,B,15; -CLK_000_D_2_ = node,-,-,G,11; -CLK_000_D_3_ = node,-,-,G,7; +CLK_000_D_1_ = node,-,-,H,3; +CLK_000_D_10_ = node,-,-,C,14; +CLK_000_D_11_ = node,-,-,H,0; +inst_DTACK_D0 = node,-,-,G,7; +inst_RESET_OUT = node,-,-,A,8; +CLK_000_D_0_ = node,-,-,C,13; +inst_CLK_OUT_PRE_50 = node,-,-,E,6; +IPL_D0_0_ = node,-,-,B,3; +IPL_D0_1_ = node,-,-,B,14; +IPL_D0_2_ = node,-,-,A,3; +CLK_000_D_2_ = node,-,-,E,2; +CLK_000_D_3_ = node,-,-,E,9; CLK_000_D_4_ = node,-,-,C,11; -CLK_000_D_5_ = node,-,-,E,13; -CLK_000_D_6_ = node,-,-,B,11; -CLK_000_D_7_ = node,-,-,G,3; -CLK_000_D_8_ = node,-,-,B,7; -CLK_000_D_9_ = node,-,-,D,11; -CLK_000_D_12_ = node,-,-,H,2; -SM_AMIGA_0_ = node,-,-,F,5; -CLK_000_N_SYNC_0_ = node,-,-,D,2; -SM_AMIGA_4_ = node,-,-,F,10; -inst_DS_000_ENABLE = node,-,-,F,9; -CLK_000_N_SYNC_12_ = node,-,-,D,13; -RST_DLY_0_ = node,-,-,D,10; -RST_DLY_1_ = node,-,-,D,6; -RST_DLY_2_ = node,-,-,D,14; -CLK_000_P_SYNC_0_ = node,-,-,D,7; -CLK_000_P_SYNC_1_ = node,-,-,A,15; -CLK_000_P_SYNC_2_ = node,-,-,F,11; -CLK_000_P_SYNC_3_ = node,-,-,C,7; -CLK_000_P_SYNC_4_ = node,-,-,A,11; -CLK_000_P_SYNC_5_ = node,-,-,G,14; -CLK_000_P_SYNC_6_ = node,-,-,G,10; -CLK_000_P_SYNC_7_ = node,-,-,D,3; -CLK_000_P_SYNC_8_ = node,-,-,A,7; -CLK_000_P_SYNC_9_ = node,-,-,C,3; -CLK_000_N_SYNC_1_ = node,-,-,E,9; -CLK_000_N_SYNC_2_ = node,-,-,A,3; -CLK_000_N_SYNC_3_ = node,-,-,F,7; -CLK_000_N_SYNC_4_ = node,-,-,A,14; -CLK_000_N_SYNC_5_ = node,-,-,A,6; -CLK_000_N_SYNC_6_ = node,-,-,B,3; -CLK_000_N_SYNC_7_ = node,-,-,G,6; -CLK_000_N_SYNC_8_ = node,-,-,B,14; -CLK_000_N_SYNC_9_ = node,-,-,F,3; -CLK_000_N_SYNC_10_ = node,-,-,C,14; -CLK_000_N_SYNC_11_ = node,-,-,C,10; -inst_CLK_000_NE_D0 = node,-,-,E,5; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,2; -SM_AMIGA_6_ = node,-,-,C,9; -inst_CLK_030_H = node,-,-,A,13; -SM_AMIGA_1_ = node,-,-,F,13; -SM_AMIGA_3_ = node,-,-,F,2; +CLK_000_D_5_ = node,-,-,E,5; +CLK_000_D_6_ = node,-,-,D,14; +CLK_000_D_7_ = node,-,-,A,14; +CLK_000_D_8_ = node,-,-,G,3; +CLK_000_D_9_ = node,-,-,A,10; +CLK_000_D_12_ = node,-,-,G,14; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,6; +inst_DS_000_ENABLE = node,-,-,B,6; +SM_AMIGA_6_ = node,-,-,C,2; +SM_AMIGA_0_ = node,-,-,G,5; +SM_AMIGA_4_ = node,-,-,B,10; +RST_DLY_0_ = node,-,-,F,0; +RST_DLY_1_ = node,-,-,F,13; +RST_DLY_2_ = node,-,-,F,9; +inst_CLK_030_H = node,-,-,A,5; +SM_AMIGA_1_ = node,-,-,F,1; +SM_AMIGA_5_ = node,-,-,F,5; +SM_AMIGA_3_ = node,-,-,F,10; SM_AMIGA_2_ = node,-,-,F,6; -SM_AMIGA_i_7_ = node,-,-,F,0; +SM_AMIGA_i_7_ = node,-,-,F,4; CIIN_0 = node,-,-,E,10; [GROUP ASSIGNMENTS] diff --git a/Logic/68030_tk.nrp b/Logic/68030_tk.nrp new file mode 100644 index 0000000..32e4e0f --- /dev/null +++ b/Logic/68030_tk.nrp @@ -0,0 +1,24 @@ +ispLEVER Classic 2.0.00.17.20.15 SDFGEN +Copyright(C),1992-2015, Lattice Semiconductor Corporation. All Rights Reserved. +Output Files: + Netlist File: 68030_tk.vho + Delay File: 68030_tk.sdf + +Parsing E:/ispLEVER_Classic2_0/ispcpld/dat/sdf.mdl +Input file: c:/users/matze/documents/github/68030tk/logic\68030_tk.tte +Reading library information ... +Mapping to combinational gates +Mapping to netlist view. +Note 18862: NODE name cpu_est_2_bus.D.X1 being renamed to GATE_cpu_est_2_bus_D_X1. +Note 18862: NODE name RST_DLY_1_bus.D.X1 being renamed to GATE_RST_DLY_1_bus_D_X1. +Note 18862: NODE name RST_DLY_1_bus.D.X2 being renamed to GATE_RST_DLY_1_bus_D_X2. +Note 18862: NODE name SM_AMIGA_3_bus.D.X1 being renamed to GATE_SM_AMIGA_3_bus_D_X1. +Note 18862: NODE name SM_AMIGA_3_bus.D.X2 being renamed to GATE_SM_AMIGA_3_bus_D_X2. +Note 18862: NODE name SM_AMIGA_i_7_bus.D.X1 being renamed to GATE_SM_AMIGA_i_7_bus_D_X1. +Note 18862: NODE name SM_AMIGA_i_7_bus.D.X2 being renamed to GATE_SM_AMIGA_i_7_bus_D_X2. +Note 18862: NODE name CIIN_0 being renamed to GATE_CIIN_OE. +Utilization Estimate + Combinational Macros: 520 + Flip-Flop and Latch Macros: 64 + I/O Pads: 61 +Elapsed time: 2 seconds diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 6905586..d2e2791 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -12827,4 +12827,1210 @@ 67 IPL_2_ 1 -1 -1 1 1 67 -1 35 VPA 1 -1 -1 1 0 35 -1 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 \ No newline at end of file + 20 BG_030 1 -1 -1 1 3 20 -1 +137 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 360 7 3 2 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21 + 70 RW 5 368 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 361 6 1 2 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 359 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 363 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21 + 80 DSACK1 5 366 7 0 80 -1 4 0 21 + 82 BGACK_030 5 365 7 0 82 -1 3 0 21 + 34 VMA 5 367 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 364 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 365 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21 + 357 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 14 0 21 + 320 CLK_000_P_SYNC_10_ 3 -1 6 4 2 3 5 7 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 296 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 321 SM_AMIGA_5_ 3 -1 5 3 0 5 7 -1 -1 2 1 21 + 297 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 2 0 21 + 325 CLK_000_D_2_ 3 -1 5 3 1 3 5 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 0 3 1 3 5 -1 -1 1 0 21 + 313 CLK_000_D_1_ 3 -1 3 3 1 3 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 0 1 6 -1 -1 1 0 21 + 304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 367 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 352 SM_AMIGA_6_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 350 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 349 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 3 1 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 354 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 1 21 + 351 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 348 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 347 inst_CLK_000_NE_D0 3 -1 1 2 5 6 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 359 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 353 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 355 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 356 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 293 N_224_i 3 -1 5 1 5 -1 -1 4 0 21 + 361 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 360 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 3 0 21 + 368 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 358 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 2 0 21 + 346 CLK_000_P_SYNC_9_ 3 -1 4 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_3_ 3 -1 0 1 3 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_2_ 3 -1 6 1 0 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_0_ 3 -1 3 1 0 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 6 1 2 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 6 1 0 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 6 1 6 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 2 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +136 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 359 7 3 2 4 6 79 -1 3 0 21 + 81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21 + 40 BERR 5 -1 4 3 0 5 7 40 -1 1 0 21 + 70 RW 5 364 6 2 5 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 365 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 358 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 367 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 366 1 0 6 -1 10 0 21 + 80 DSACK1 5 362 7 0 80 -1 4 0 21 + 82 BGACK_030 5 361 7 0 82 -1 3 0 21 + 34 VMA 5 363 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 360 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 361 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 299 inst_AS_030_D0 3 -1 0 5 0 3 4 5 7 -1 -1 1 0 21 + 356 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 15 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 3 4 2 3 5 7 -1 -1 1 0 21 + 317 CLK_000_D_0_ 3 -1 0 4 0 3 4 5 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 324 CLK_000_D_2_ 3 -1 3 3 0 3 5 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 4 3 0 3 5 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 353 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 4 0 21 + 320 SM_AMIGA_5_ 3 -1 5 2 5 7 -1 -1 4 0 21 + 363 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 351 SM_AMIGA_6_ 3 -1 5 2 1 5 -1 -1 2 0 21 + 347 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 346 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 367 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 366 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 358 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 354 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 9 0 21 + 352 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 365 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 359 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 355 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 0 21 + 349 RST_DLY_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 348 RST_DLY_0_ 3 -1 0 1 0 -1 -1 3 1 21 + 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 3 0 21 + 364 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 357 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 350 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 334 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 2 0 21 + 345 CLK_000_P_SYNC_9_ 3 -1 4 1 3 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_4_ 3 -1 1 1 2 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 6 1 1 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 3 1 6 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 6 1 3 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 4 1 0 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 1 1 4 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 6 1 6 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 7 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 1 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 7 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +135 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 359 7 3 2 4 6 79 -1 3 0 21 + 70 RW 5 364 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 365 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 358 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 357 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 366 1 0 6 -1 10 0 21 + 80 DSACK1 5 362 7 0 80 -1 4 0 21 + 82 BGACK_030 5 361 7 0 82 -1 3 0 21 + 34 VMA 5 363 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 360 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 361 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 299 inst_AS_030_D0 3 -1 7 6 0 2 3 4 5 7 -1 -1 1 0 21 + 355 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 15 0 21 + 324 CLK_000_D_2_ 3 -1 5 4 0 3 5 6 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 3 4 2 3 5 7 -1 -1 1 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 5 0 21 + 320 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 4 0 21 + 333 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 293 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 2 1 21 + 317 CLK_000_D_0_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 6 3 3 5 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 352 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 4 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 363 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 350 SM_AMIGA_6_ 3 -1 5 2 1 5 -1 -1 2 0 21 + 346 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 308 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 366 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 358 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 357 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 353 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 9 0 21 + 351 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 365 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 359 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 354 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 0 21 + 348 RST_DLY_1_ 3 -1 6 1 6 -1 -1 3 0 21 + 347 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 1 21 + 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 3 0 21 + 364 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 356 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 349 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 334 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 304 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 345 CLK_000_P_SYNC_9_ 3 -1 4 1 3 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_8_ 3 -1 2 1 4 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 347 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 352 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 353 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21 + 344 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 13 1 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 5 0 21 + 319 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 4 0 21 + 332 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 2 1 21 + 323 CLK_000_D_2_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 0 1 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21 + 333 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 341 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 4 0 21 + 339 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 314 CLK_000_D_11_ 3 -1 7 2 0 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 340 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 + 305 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 1 21 + 334 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 331 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21 + 330 CLK_000_D_9_ 3 -1 4 1 3 -1 -1 1 0 21 + 329 CLK_000_D_8_ 3 -1 0 1 4 -1 -1 1 0 21 + 328 CLK_000_D_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 327 CLK_000_D_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 326 CLK_000_D_5_ 3 -1 1 1 4 -1 -1 1 0 21 + 325 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 324 CLK_000_D_3_ 3 -1 6 1 6 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 3 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 347 7 3 1 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 4 6 7 81 -1 1 0 21 + 70 RW 5 352 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 + 68 A_0_ 5 353 6 1 2 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 6 6 0 2 3 4 5 7 -1 -1 1 0 21 + 322 CLK_000_D_2_ 3 -1 4 5 0 2 3 5 6 -1 -1 1 0 21 + 344 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 13 1 21 + 333 SM_AMIGA_6_ 3 -1 0 4 0 2 5 7 -1 -1 4 0 21 + 331 SM_AMIGA_0_ 3 -1 5 4 2 3 5 7 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 341 SM_AMIGA_5_ 3 -1 0 3 0 2 5 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 2 1 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 300 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 340 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 4 0 21 + 332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 4 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 334 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 314 CLK_000_D_11_ 3 -1 7 2 3 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 339 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 + 305 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 1 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 330 CLK_000_D_12_ 3 -1 3 1 7 -1 -1 1 0 21 + 329 CLK_000_D_9_ 3 -1 4 1 3 -1 -1 1 0 21 + 328 CLK_000_D_8_ 3 -1 5 1 4 -1 -1 1 0 21 + 327 CLK_000_D_7_ 3 -1 3 1 5 -1 -1 1 0 21 + 326 CLK_000_D_6_ 3 -1 0 1 3 -1 -1 1 0 21 + 325 CLK_000_D_5_ 3 -1 3 1 0 -1 -1 1 0 21 + 324 CLK_000_D_4_ 3 -1 0 1 3 -1 -1 1 0 21 + 323 CLK_000_D_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 319 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 3 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 63 CLK_030 1 -1 -1 2 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 347 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 352 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 353 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 4 1 2 3 5 -1 -1 7 0 21 + 333 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 4 0 21 + 344 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21 + 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 5 0 21 + 340 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 2 1 21 + 322 CLK_000_D_2_ 3 -1 7 3 2 3 5 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 341 SM_AMIGA_5_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 4 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 313 CLK_000_D_10_ 3 -1 2 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 1 2 1 6 -1 -1 1 0 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 339 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 337 RST_DLY_1_ 3 -1 3 1 3 -1 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 1 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 330 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 329 CLK_000_D_9_ 3 -1 6 1 2 -1 -1 1 0 21 + 328 CLK_000_D_8_ 3 -1 4 1 6 -1 -1 1 0 21 + 327 CLK_000_D_7_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_D_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 325 CLK_000_D_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 324 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 323 CLK_000_D_3_ 3 -1 2 1 6 -1 -1 1 0 21 + 321 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 320 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 319 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 1 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 347 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 352 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 353 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21 + 300 inst_AS_030_000_SYNC 3 -1 1 4 1 2 3 5 -1 -1 7 0 21 + 333 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 4 0 21 + 344 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21 + 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 5 0 21 + 340 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 2 1 21 + 322 CLK_000_D_2_ 3 -1 7 3 2 3 5 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 0 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 341 SM_AMIGA_5_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 4 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 313 CLK_000_D_10_ 3 -1 2 2 1 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 1 2 1 6 -1 -1 1 0 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 339 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 337 RST_DLY_1_ 3 -1 3 1 3 -1 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 1 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 330 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 329 CLK_000_D_9_ 3 -1 6 1 2 -1 -1 1 0 21 + 328 CLK_000_D_8_ 3 -1 4 1 6 -1 -1 1 0 21 + 327 CLK_000_D_7_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_D_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 325 CLK_000_D_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 324 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 323 CLK_000_D_3_ 3 -1 2 1 6 -1 -1 1 0 21 + 321 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 320 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 319 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 1 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 347 7 3 0 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 352 6 2 1 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 353 6 1 3 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 333 SM_AMIGA_6_ 3 -1 2 5 1 2 3 5 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 0 5 1 2 3 4 7 -1 -1 1 0 21 + 334 SM_AMIGA_0_ 3 -1 6 4 1 5 6 7 -1 -1 3 0 21 + 344 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 340 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 322 CLK_000_D_2_ 3 -1 4 3 2 4 5 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 336 RST_DLY_0_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 332 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 341 SM_AMIGA_5_ 3 -1 5 2 1 5 -1 -1 3 0 21 + 335 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 + 338 RST_DLY_2_ 3 -1 5 2 0 5 -1 -1 2 0 21 + 337 RST_DLY_1_ 3 -1 5 2 0 5 -1 -1 2 1 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 314 CLK_000_D_11_ 3 -1 7 2 6 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 339 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 330 CLK_000_D_12_ 3 -1 6 1 7 -1 -1 1 0 21 + 329 CLK_000_D_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 328 CLK_000_D_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 327 CLK_000_D_7_ 3 -1 0 1 6 -1 -1 1 0 21 + 326 CLK_000_D_6_ 3 -1 3 1 0 -1 -1 1 0 21 + 325 CLK_000_D_5_ 3 -1 4 1 3 -1 -1 1 0 21 + 324 CLK_000_D_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 323 CLK_000_D_3_ 3 -1 4 1 2 -1 -1 1 0 21 + 321 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 319 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 2 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 347 7 3 0 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 0 4 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 352 6 2 1 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 353 6 1 3 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 333 SM_AMIGA_6_ 3 -1 2 5 1 2 3 5 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 0 5 1 2 3 4 7 -1 -1 1 0 21 + 334 SM_AMIGA_0_ 3 -1 6 4 1 5 6 7 -1 -1 3 0 21 + 344 SM_AMIGA_i_7_ 3 -1 5 3 1 2 7 -1 -1 13 1 21 + 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 340 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 322 CLK_000_D_2_ 3 -1 4 3 2 4 5 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 + 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 336 RST_DLY_0_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 332 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 341 SM_AMIGA_5_ 3 -1 5 2 1 5 -1 -1 3 0 21 + 335 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 307 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 + 338 RST_DLY_2_ 3 -1 5 2 0 5 -1 -1 2 0 21 + 337 RST_DLY_1_ 3 -1 5 2 0 5 -1 -1 2 1 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 314 CLK_000_D_11_ 3 -1 7 2 6 7 -1 -1 1 0 21 + 308 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 301 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 339 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 342 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 1 21 + 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 310 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 + 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 330 CLK_000_D_12_ 3 -1 6 1 7 -1 -1 1 0 21 + 329 CLK_000_D_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 328 CLK_000_D_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 327 CLK_000_D_7_ 3 -1 0 1 6 -1 -1 1 0 21 + 326 CLK_000_D_6_ 3 -1 3 1 0 -1 -1 1 0 21 + 325 CLK_000_D_5_ 3 -1 4 1 3 -1 -1 1 0 21 + 324 CLK_000_D_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 323 CLK_000_D_3_ 3 -1 4 1 2 -1 -1 1 0 21 + 321 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 319 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 2 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 0cb8fab..60c3f25 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,19 +8,12 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Fri Aug 19 00:20:46 2016 +; DATE Fri Aug 19 00:39:40 2016 -Pin 84 A_DECODE_22_ -Pin 94 A_DECODE_21_ Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 -Pin 93 A_DECODE_20_ -Pin 97 A_DECODE_19_ Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 -Pin 95 A_DECODE_18_ -Pin 59 A_DECODE_17_ Pin 85 A_DECODE_23_ -Pin 96 A_DECODE_16_ Pin 68 IPL_2_ Pin 58 FC_1_ Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 @@ -31,47 +24,54 @@ Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 Pin 14 nEXP_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 Pin 21 BG_030 -Pin 56 IPL_1_ -Pin 67 IPL_0_ +Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 +Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 Pin 28 BGACK_000 -Pin 57 FC_0_ +Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 145 Pin 64 CLK_030 -Pin 60 A_1_ +Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 Pin 11 CLK_000 +Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 163 Pin 61 CLK_OSZI +Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 157 Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247 -Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 275 +Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 +Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 277 +Pin 84 A_DECODE_22_ Pin 91 FPU_SENSE +Pin 94 A_DECODE_21_ +Pin 93 A_DECODE_20_ Pin 30 DTACK +Pin 97 A_DECODE_19_ Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 95 A_DECODE_18_ Pin 66 E Comb ; S6=1 S9=1 Pair 251 +Pin 59 A_DECODE_17_ Pin 36 VPA +Pin 96 A_DECODE_16_ Pin 86 RST -Pin 3 RESET Comb ; S6=1 S9=1 Pair 133 +Pin 3 RESET Comb ; S6=1 S9=1 Pair 128 Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151 Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179 Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 -Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 -Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 -Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 145 -Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 -Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 155 -Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 157 -Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 -Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 +Pin 56 IPL_1_ +Pin 67 IPL_0_ +Pin 57 FC_0_ +Pin 60 A_1_ Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 -Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 -Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 -Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 +Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 271 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 -Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 278 +Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127 Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283 Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 +Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133 Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1 Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1 Node 281 RN_AS_030 Comb ; S6=1 S9=1 @@ -83,98 +83,72 @@ Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1 Node 145 RN_AHIGH_29_ Comb ; S6=1 S9=1 Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1 -Node 155 RN_AHIGH_27_ Comb ; S6=1 S9=1 +Node 163 RN_AHIGH_27_ Comb ; S6=1 S9=1 Node 157 RN_AHIGH_26_ Comb ; S6=1 S9=1 Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1 Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 -Node 269 RN_RW_000 Reg ; S6=1 S9=1 -Node 257 RN_A_0_ Reg ; S6=1 S9=1 -Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 271 RN_RW_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 -Node 278 RN_BGACK_030 Reg ; S6=1 S9=1 +Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 Node 283 RN_DSACK1 Reg ; S6=1 S9=1 Node 173 RN_VMA Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 -Node 242 N_226 Comb ; S6=1 S9=1 -Node 227 cpu_est_2_ Reg ; S6=1 S9=1 -Node 223 cpu_est_3_ Reg ; S6=1 S9=1 -Node 128 cpu_est_0_ Reg ; S6=1 S9=1 -Node 239 cpu_est_1_ Reg ; S6=1 S9=1 -Node 248 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 140 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 -Node 271 inst_AS_030_D0 Reg ; S6=1 S9=1 -Node 169 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 257 RN_A_0_ Reg ; S6=1 S9=1 +Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 187 cpu_est_3_ Reg ; S6=1 S9=1 +Node 176 cpu_est_0_ Reg ; S6=1 S9=1 +Node 233 cpu_est_1_ Reg ; S6=1 S9=1 +Node 193 cpu_est_2_ Reg ; S6=1 S9=1 +Node 172 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 260 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 110 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 158 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 Node 119 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 115 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 116 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 104 CYCLE_DMA_1_ Reg ; S6=1 S9=1 -Node 259 SIZE_DMA_0_ Reg ; S6=1 S9=1 -Node 253 SIZE_DMA_1_ Reg ; S6=1 S9=1 -Node 109 inst_VPA_D Reg ; S6=1 S9=1 -Node 134 inst_UDS_000_INT Reg ; S6=1 S9=1 -Node 103 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 103 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 121 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 115 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1 +Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1 +Node 224 inst_VPA_D Reg ; S6=1 S9=1 +Node 188 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 182 inst_LDS_000_INT Reg ; S6=1 S9=1 Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 268 CLK_000_D_10_ Reg ; S6=1 S9=1 -Node 284 CLK_000_D_11_ Reg ; S6=1 S9=1 -Node 172 inst_DTACK_D0 Reg ; S6=1 S9=1 -Node 187 inst_RESET_OUT Reg ; S6=1 S9=1 -Node 200 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 158 CLK_000_D_1_ Reg ; S6=1 S9=1 -Node 265 CLK_000_D_0_ Reg ; S6=1 S9=1 -Node 113 CLK_000_P_SYNC_10_ Reg ; S6=1 S9=1 -Node 233 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 196 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 244 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 148 IPL_D0_2_ Reg ; S6=1 S9=1 -Node 262 CLK_000_D_2_ Reg ; S6=1 S9=1 -Node 256 CLK_000_D_3_ Reg ; S6=1 S9=1 +Node 274 CLK_000_D_1_ Reg ; S6=1 S9=1 +Node 170 CLK_000_D_10_ Reg ; S6=1 S9=1 +Node 269 CLK_000_D_11_ Reg ; S6=1 S9=1 +Node 256 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 113 inst_RESET_OUT Reg ; S6=1 S9=1 +Node 169 CLK_000_D_0_ Reg ; S6=1 S9=1 +Node 206 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 130 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 146 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 106 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 200 CLK_000_D_2_ Reg ; S6=1 S9=1 +Node 211 CLK_000_D_3_ Reg ; S6=1 S9=1 Node 166 CLK_000_D_4_ Reg ; S6=1 S9=1 -Node 217 CLK_000_D_5_ Reg ; S6=1 S9=1 -Node 142 CLK_000_D_6_ Reg ; S6=1 S9=1 -Node 250 CLK_000_D_7_ Reg ; S6=1 S9=1 -Node 136 CLK_000_D_8_ Reg ; S6=1 S9=1 -Node 190 CLK_000_D_9_ Reg ; S6=1 S9=1 -Node 272 CLK_000_D_12_ Reg ; S6=1 S9=1 -Node 229 SM_AMIGA_0_ Reg ; S6=1 S9=1 -Node 176 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 -Node 236 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 235 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 193 CLK_000_N_SYNC_12_ Reg ; S6=1 S9=1 -Node 188 RST_DLY_0_ Reg ; S6=1 S9=1 -Node 182 RST_DLY_1_ Reg ; S6=1 S9=1 -Node 194 RST_DLY_2_ Reg ; S6=1 S9=1 -Node 184 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 -Node 124 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 -Node 238 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 -Node 160 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 -Node 118 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 -Node 266 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 -Node 260 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 -Node 178 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 -Node 112 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 -Node 154 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 -Node 211 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 -Node 106 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 -Node 232 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 -Node 122 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 -Node 110 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 -Node 130 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 -Node 254 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 -Node 146 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 -Node 226 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 -Node 170 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1 -Node 164 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1 -Node 205 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 -Node 152 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 163 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 121 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 241 SM_AMIGA_1_ Reg ; S6=1 S9=1 -Node 224 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 205 CLK_000_D_5_ Reg ; S6=1 S9=1 +Node 194 CLK_000_D_6_ Reg ; S6=1 S9=1 +Node 122 CLK_000_D_7_ Reg ; S6=1 S9=1 +Node 250 CLK_000_D_8_ Reg ; S6=1 S9=1 +Node 116 CLK_000_D_9_ Reg ; S6=1 S9=1 +Node 266 CLK_000_D_12_ Reg ; S6=1 S9=1 +Node 254 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 134 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 152 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 253 SM_AMIGA_0_ Reg ; S6=1 S9=1 +Node 140 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 221 RST_DLY_0_ Reg ; S6=1 S9=1 +Node 241 RST_DLY_1_ Reg ; S6=1 S9=1 +Node 235 RST_DLY_2_ Reg ; S6=1 S9=1 +Node 109 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 223 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 229 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 236 SM_AMIGA_3_ Reg ; S6=1 S9=1 Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 221 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 Node 212 CIIN_0 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 14669db..64dbd6c 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Fri Aug 19 00:20:46 2016 -End : Fri Aug 19 00:20:46 2016 $$$ Elapsed time: 00:00:00 +Start: Fri Aug 19 00:39:39 2016 +End : Fri Aug 19 00:39:40 2016 $$$ Elapsed time: 00:00:01 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 28 => 84% - 1 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 26 => 78% - 2 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 28 => 84% - 3 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 31 => 93% + 0 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 23 => 69% + 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 25 => 75% + 2 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 24 => 72% + 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 25 => 75% 4 | 16 | 10 | 10 => 100% | 8 | 4 => 50% | 33 | 33 => 100% - 5 | 16 | 16 | 16 => 100% | 8 | 5 => 62% | 33 | 31 => 93% - 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 28 => 84% - 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 32 => 96% + 5 | 16 | 10 | 10 => 100% | 8 | 5 => 62% | 33 | 25 => 75% + 6 | 16 | 13 | 13 => 100% | 8 | 7 => 87% | 33 | 27 => 81% + 7 | 16 | 9 | 9 => 100% | 8 | 8 => 100% | 33 | 33 => 100% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 29.63 => 89% + | Avg number of array inputs in used blocks : 26.88 => 81% * Input/Clock Signal count: 24 -> placed: 24 = 100% @@ -41,13 +41,13 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 8 => 100% - Macrocells : 128 116 => 90% - PT Clusters : 128 56 => 43% - - Single PT Clusters : 128 70 => 54% + Macrocells : 128 90 => 70% + PT Clusters : 128 53 => 41% + - Single PT Clusters : 128 46 => 35% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 1335] Route [ 1] +* Attempts: Place [ 4804] Route [ 1] =========================================================================== Signal Fanout Table =========================================================================== @@ -70,11 +70,11 @@ ___|__|__|____|____________________________________________________________ 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 13| 4| IO| 42|=> 0...|4..7| AS_000 - 14| 7| IO| 82|=> ....|4..7| AS_030 + 14| 7| IO| 82|=> 0...|4..7| AS_030 15| 0|OUT| 92|=> ....|....| AVEC - 16| 6| IO| 69|=> 01..|....| A_0_ + 16| 6| IO| 69|=> ...3|....| A_0_ |=> Paired w/: RN_A_0_ - 17| 5|INP| 60|=> .12.|....| A_1_ + 17| 5|INP| 60|=> ....|..6.| A_1_ 18| 0|INP| 96|=> ..2.|4..7| A_DECODE_16_ 19| 5|INP| 59|=> ..2.|4..7| A_DECODE_17_ 20| 0|INP| 95|=> ..2.|4..7| A_DECODE_18_ @@ -83,7 +83,7 @@ ___|__|__|____|____________________________________________________________ 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ - 26| 4| IO| 41|=> ..2.|.567| BERR + 26| 4| IO| 41|=> .12.|.567| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 @@ -92,141 +92,115 @@ ___|__|__|____|____________________________________________________________ 30| 2|INP| 21|=> ...3|....| BG_030 31| 4|OUT| 47|=> ....|....| CIIN 32| 4|NOD| . |=> ....|4...| CIIN_0 - 33| +|INP| 11|=> ...3|..6.| CLK_000 - 34| 6|NOD| . |=> ..23|....| CLK_000_D_0_ - 35| 6|NOD| . |=> ....|...7| CLK_000_D_10_ - 36| 7|NOD| . |=> ....|...7| CLK_000_D_11_ - 37| 7|NOD| . |=> ....|...7| CLK_000_D_12_ - 38| 2|NOD| . |=> ...3|..6.| CLK_000_D_1_ - 39| 6|NOD| . |=> ....|..6.| CLK_000_D_2_ - 40| 6|NOD| . |=> ..2.|....| CLK_000_D_3_ + 33| +|INP| 11|=> ..2.|....| CLK_000 + 34| 2|NOD| . |=> 0123|.567| CLK_000_D_0_ + 35| 2|NOD| . |=> ....|...7| CLK_000_D_10_ + 36| 7|NOD| . |=> ....|..67| CLK_000_D_11_ + 37| 6|NOD| . |=> ....|...7| CLK_000_D_12_ + 38| 7|NOD| . |=> 0123|4567| CLK_000_D_1_ + 39| 4|NOD| . |=> ..2.|45..| CLK_000_D_2_ + 40| 4|NOD| . |=> ..2.|....| CLK_000_D_3_ 41| 2|NOD| . |=> ....|4...| CLK_000_D_4_ - 42| 4|NOD| . |=> .1..|....| CLK_000_D_5_ - 43| 1|NOD| . |=> ....|..6.| CLK_000_D_6_ - 44| 6|NOD| . |=> .1..|....| CLK_000_D_7_ - 45| 1|NOD| . |=> ...3|....| CLK_000_D_8_ - 46| 3|NOD| . |=> ....|..6.| CLK_000_D_9_ - 47| 3|NOD| . |=> ..2.|45..| CLK_000_N_SYNC_0_ - 48| 2|NOD| . |=> ..2.|....| CLK_000_N_SYNC_10_ - 49| 2|NOD| . |=> ...3|....| CLK_000_N_SYNC_11_ - 50| 3|NOD| . |=> ...3|45..| CLK_000_N_SYNC_12_ - 51| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_1_ - 52| 0|NOD| . |=> ....|.5..| CLK_000_N_SYNC_2_ - 53| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_3_ - 54| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_4_ - 55| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_5_ - 56| 1|NOD| . |=> ....|..6.| CLK_000_N_SYNC_6_ - 57| 6|NOD| . |=> .1..|....| CLK_000_N_SYNC_7_ - 58| 1|NOD| . |=> ....|.5..| CLK_000_N_SYNC_8_ - 59| 5|NOD| . |=> ..2.|....| CLK_000_N_SYNC_9_ - 60| 3|NOD| . |=> 0...|....| CLK_000_P_SYNC_0_ - 61| 0|NOD| . |=> 0.23|.5.7| CLK_000_P_SYNC_10_ - 62| 0|NOD| . |=> ....|.5..| CLK_000_P_SYNC_1_ - 63| 5|NOD| . |=> ..2.|....| CLK_000_P_SYNC_2_ - 64| 2|NOD| . |=> 0...|....| CLK_000_P_SYNC_3_ - 65| 0|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_ - 66| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_5_ - 67| 6|NOD| . |=> ...3|....| CLK_000_P_SYNC_6_ - 68| 3|NOD| . |=> 0...|....| CLK_000_P_SYNC_7_ - 69| 0|NOD| . |=> ..2.|....| CLK_000_P_SYNC_8_ - 70| 2|NOD| . |=> 0...|....| CLK_000_P_SYNC_9_ - 71| +|INP| 64|=> 0...|...7| CLK_030 - 72| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 73| 1|OUT| 10|=> ....|....| CLK_EXP - 74| +|Cin| 61|=> ....|....| CLK_OSZI - 75| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ - 76| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ - 77| 7| IO| 81|=> ....|....| DSACK1 + 42| 4|NOD| . |=> ...3|....| CLK_000_D_5_ + 43| 3|NOD| . |=> 0...|....| CLK_000_D_6_ + 44| 0|NOD| . |=> ....|..6.| CLK_000_D_7_ + 45| 6|NOD| . |=> 0...|....| CLK_000_D_8_ + 46| 0|NOD| . |=> ..2.|....| CLK_000_D_9_ + 47| +|INP| 64|=> 0...|...7| CLK_030 + 48| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 49| 1|OUT| 10|=> ....|....| CLK_EXP + 50| +|Cin| 61|=> ....|....| CLK_OSZI + 51| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ + 52| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ + 53| 7| IO| 81|=> ....|....| DSACK1 |=> Paired w/: RN_DSACK1 - 78| 0|OUT| 98|=> ....|....| DS_030 - 79| 3|INP| 30|=> ..2.|....| DTACK - 80| 6|OUT| 66|=> ....|....| E - 81| 5|INP| 57|=> ..2.|4..7| FC_0_ - 82| 5|INP| 58|=> ..2.|4..7| FC_1_ - 83| 7|OUT| 78|=> ....|....| FPU_CS - 84| 0|INP| 91|=> ....|4..7| FPU_SENSE - 85| 1| IO| 8|=> ....|....| IPL_030_0_ + 54| 0|OUT| 98|=> ....|....| DS_030 + 55| 3|INP| 30|=> ....|..6.| DTACK + 56| 6|OUT| 66|=> ....|....| E + 57| 5|INP| 57|=> ..2.|4..7| FC_0_ + 58| 5|INP| 58|=> ..2.|4..7| FC_1_ + 59| 7|OUT| 78|=> ....|....| FPU_CS + 60| 0|INP| 91|=> ....|4..7| FPU_SENSE + 61| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 86| 1| IO| 7|=> ....|....| IPL_030_1_ + 62| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 87| 1| IO| 9|=> ....|....| IPL_030_2_ + 63| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 88| 6|INP| 67|=> .1.3|....| IPL_0_ - 89| 5|INP| 56|=> .1..|.5..| IPL_1_ - 90| 6|INP| 68|=> .1..|....| IPL_2_ - 91| 3|NOD| . |=> .1..|....| IPL_D0_0_ - 92| 5|NOD| . |=> .1..|....| IPL_D0_1_ - 93| 1|NOD| . |=> .1..|....| IPL_D0_2_ - 94| 3| IO| 31|=> 0...|..6.| LDS_000 - 95| 5|NOD| . |=> ....|.5..| N_226 - 96| 1|OUT| 3|=> ....|....| RESET - 97| 6|NOD| . |=> ....|..6.| RN_A_0_ + 64| 6|INP| 67|=> .1..|....| IPL_0_ + 65| 5|INP| 56|=> .1..|....| IPL_1_ + 66| 6|INP| 68|=> 01..|....| IPL_2_ + 67| 1|NOD| . |=> .1..|....| IPL_D0_0_ + 68| 1|NOD| . |=> .1..|....| IPL_D0_1_ + 69| 0|NOD| . |=> .1..|....| IPL_D0_2_ + 70| 3| IO| 31|=> 0...|..6.| LDS_000 + 71| 1|OUT| 3|=> ....|....| RESET + 72| 6|NOD| . |=> ....|..6.| RN_A_0_ |=> Paired w/: A_0_ - 98| 7|NOD| . |=> 0123|4.67| RN_BGACK_030 + 73| 7|NOD| . |=> 0123|4.67| RN_BGACK_030 |=> Paired w/: BGACK_030 - 99| 3|NOD| . |=> ...3|....| RN_BG_000 + 74| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 100| 7|NOD| . |=> ....|...7| RN_DSACK1 + 75| 7|NOD| . |=> ....|...7| RN_DSACK1 |=> Paired w/: DSACK1 - 101| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 76| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 102| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 77| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 103| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 78| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 104| 6|NOD| . |=> ....|..6.| RN_RW + 79| 6|NOD| . |=> ....|..6.| RN_RW |=> Paired w/: RW - 105| 7|NOD| . |=> ....|...7| RN_RW_000 + 80| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 106| 3|NOD| . |=> ...3|.5..| RN_VMA + 81| 3|NOD| . |=> ...3|.5..| RN_VMA |=> Paired w/: VMA - 107| +|INP| 86|=> 0123|.567| RST - 108| 3|NOD| . |=> ...3|....| RST_DLY_0_ - 109| 3|NOD| . |=> ...3|....| RST_DLY_1_ - 110| 3|NOD| . |=> ...3|....| RST_DLY_2_ - 111| 6| IO| 71|=> ....|.5.7| RW + 82| +|INP| 86|=> 0123|.567| RST + 83| 5|NOD| . |=> 0...|.5..| RST_DLY_0_ + 84| 5|NOD| . |=> 0...|.5..| RST_DLY_1_ + 85| 5|NOD| . |=> 0...|.5..| RST_DLY_2_ + 86| 6| IO| 71|=> .1..|...7| RW |=> Paired w/: RN_RW - 112| 7| IO| 80|=> 0...|4.6.| RW_000 + 87| 7| IO| 80|=> 0...|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 113| 6| IO| 70|=> 0...|....| SIZE_0_ - 114| 7| IO| 79|=> 0...|....| SIZE_1_ - 115| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ - 116| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ - 117| 5|NOD| . |=> ...3|.5.7| SM_AMIGA_0_ - 118| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ - 119| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ - 120| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ - 121| 5|NOD| . |=> ....|.5..| SM_AMIGA_4_ - 122| 5|NOD| . |=> ....|.567| SM_AMIGA_5_ - 123| 2|NOD| . |=> 012.|.5..| SM_AMIGA_6_ - 124| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_ - 125| 3| IO| 32|=> 0...|..6.| UDS_000 - 126| 3| IO| 35|=> ....|....| VMA + 88| 6| IO| 70|=> ...3|....| SIZE_0_ + 89| 7| IO| 79|=> ...3|....| SIZE_1_ + 90| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ + 91| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ + 92| 6|NOD| . |=> .1..|.567| SM_AMIGA_0_ + 93| 5|NOD| . |=> ....|.567| SM_AMIGA_1_ + 94| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ + 95| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ + 96| 1|NOD| . |=> .1..|.5..| SM_AMIGA_4_ + 97| 5|NOD| . |=> .1..|.5..| SM_AMIGA_5_ + 98| 2|NOD| . |=> .123|.5.7| SM_AMIGA_6_ + 99| 5|NOD| . |=> .12.|...7| SM_AMIGA_i_7_ + 100| 3| IO| 32|=> 0...|..6.| UDS_000 + 101| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 127| +|INP| 36|=> 0...|....| VPA - 128| 1|NOD| . |=> .1.3|.5..| cpu_est_0_ - 129| 5|NOD| . |=> ...3|.56.| cpu_est_1_ - 130| 5|NOD| . |=> ...3|.56.| cpu_est_2_ - 131| 5|NOD| . |=> ...3|.56.| cpu_est_3_ - 132| 2|NOD| . |=> ..23|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 133| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW - 134| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA - 135| 6|NOD| . |=> ....|4.6.| inst_AS_000_INT - 136| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC - 137| 7|NOD| . |=> ..23|4567| inst_AS_030_D0 - 138| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D - 139| 4|NOD| . |=> .1..|.5..| inst_CLK_000_NE_D0 - 140| 0|NOD| . |=> 0...|....| inst_CLK_030_H - 141| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 - 142| 4|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE_D - 143| 0|NOD| . |=> 0...|....| inst_DS_000_DMA - 144| 5|NOD| . |=> ...3|.5..| inst_DS_000_ENABLE - 145| 2|NOD| . |=> ....|.5..| inst_DTACK_D0 - 146| 0|NOD| . |=> 0..3|....| inst_LDS_000_INT - 147| 3|NOD| . |=> 0123|4.67| inst_RESET_OUT - 148| 1|NOD| . |=> .1.3|....| inst_UDS_000_INT - 149| 0|NOD| . |=> ...3|.5..| inst_VPA_D - 150| +|INP| 14|=> 0123|4567| nEXP_SPACE + 102| +|INP| 36|=> ....|.5..| VPA + 103| 3|NOD| . |=> ...3|.5..| cpu_est_0_ + 104| 5|NOD| . |=> ...3|.56.| cpu_est_1_ + 105| 3|NOD| . |=> ...3|.56.| cpu_est_2_ + 106| 3|NOD| . |=> ...3|.56.| cpu_est_3_ + 107| 6|NOD| . |=> ...3|..6.| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 108| 6|NOD| . |=> ..2.|..6.| inst_AMIGA_BUS_ENABLE_DMA_LOW + 109| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA + 110| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT + 111| 2|NOD| . |=> ..23|.5..| inst_AS_030_000_SYNC + 112| 0|NOD| . |=> .123|4..7| inst_AS_030_D0 + 113| 7|NOD| . |=> ..2.|..6.| inst_BGACK_030_INT_D + 114| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 115| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 + 116| 4|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE_D + 117| 0|NOD| . |=> 0...|....| inst_DS_000_DMA + 118| 1|NOD| . |=> .1.3|....| inst_DS_000_ENABLE + 119| 6|NOD| . |=> ....|.5..| inst_DTACK_D0 + 120| 3|NOD| . |=> ...3|....| inst_LDS_000_INT + 121| 0|NOD| . |=> 0123|4.67| inst_RESET_OUT + 122| 3|NOD| . |=> ...3|....| inst_UDS_000_INT + 123| 5|NOD| . |=> ...3|.5..| inst_VPA_D + 124| +|INP| 14|=> 0123|4567| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -347,21 +321,21 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 1]| 1 XOR free - 2| CYCLE_DMA_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free - 3|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 1|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 1]| 1 XOR to [ 1] as logic PT + 2| | ? | | S | | 4 to [ 1]| 1 XOR free + 3| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig - 7|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig - 8|CLK_000_P_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| CYCLE_DMA_0_|NOD| | S | 2 | 4 to [10]| 1 XOR free -11|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [11] for 1 PT sig + 5|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6|inst_AS_030_D0|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8|inst_RESET_OUT|NOD| | S | 2 | 4 to [ 8]| 1 XOR free + 9| CYCLE_DMA_1_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free +10| CLK_000_D_9_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free 12|inst_AS_000_DMA|NOD| | S | 7 | 4 to [12]| 1 XOR to [12] as logic PT -13|inst_CLK_030_H|NOD| | S | 8 | 4 to [12]| 1 XOR free -14|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig -15|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 to [13]| 1 XOR to [15] for 1 PT sig +13| CYCLE_DMA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free +14| CLK_000_D_7_|NOD| | S | 1 | 4 to [12]| 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Maximum PT Capacity @@ -374,21 +348,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DS_030|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 1|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) - 2| CYCLE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 17] logic PT(s) - 5| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) - 6|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) - 7|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 8|CLK_000_P_SYNC_10_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 9|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 13] logic PT(s) -10| CYCLE_DMA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) -11|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) -12|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 10] logic PT(s) -13|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 8] logic PT(s) -14|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) -15|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 1|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 18] logic PT(s) + 2| | ? | | S | |=> can support up to [ 9] logic PT(s) + 3| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 5|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 18] logic PT(s) + 6|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 9| CYCLE_DMA_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) +10| CLK_000_D_9_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 14] logic PT(s) +13| CYCLE_DMA_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +14| CLK_000_D_7_|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Node-Pin Assignments @@ -399,21 +373,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1|inst_LDS_000_INT|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2| CYCLE_DMA_1_|NOD| | => | 6 7 0 1 | 97 98 91 92 - 3|CLK_000_N_SYNC_2_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1|inst_DS_000_DMA|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2| | | | => | 6 7 0 1 | 97 98 91 92 + 3| IPL_D0_2_|NOD| | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5| inst_VPA_D|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6|CLK_000_N_SYNC_5_|NOD| | => | 0 1 2 3 | 91 92 93 94 - 7|CLK_000_P_SYNC_8_|NOD| | => | 0 1 2 3 | 91 92 93 94 - 8|CLK_000_P_SYNC_10_|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 92 93 94 95 -10| CYCLE_DMA_0_|NOD| | => | 2 3 4 5 | 93 94 95 96 -11|CLK_000_P_SYNC_4_|NOD| | => | 2 3 4 5 | 93 94 95 96 + 5|inst_CLK_030_H|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6|inst_AS_030_D0|NOD| | => | 0 1 2 3 | 91 92 93 94 + 7| | | | => | 0 1 2 3 | 91 92 93 94 + 8|inst_RESET_OUT|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9| CYCLE_DMA_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 +10| CLK_000_D_9_|NOD| | => | 2 3 4 5 | 93 94 95 96 +11| | | | => | 2 3 4 5 | 93 94 95 96 12|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 94 95 96 97 -13|inst_CLK_030_H|NOD| | => | 3 4 5 6 | 94 95 96 97 -14|CLK_000_N_SYNC_4_|NOD| | => | 4 5 6 7 | 95 96 97 98 -15|CLK_000_P_SYNC_1_|NOD| | => | 4 5 6 7 | 95 96 97 98 +13| CYCLE_DMA_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 +14| CLK_000_D_7_|NOD| | => | 4 5 6 7 | 95 96 97 98 +15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > IO-to-Node Pin Mapping @@ -463,42 +437,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] - [MCell 1 |103|NOD inst_LDS_000_INT| |*] + [MCell 1 |103|NOD inst_DS_000_DMA| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD CYCLE_DMA_1_| |*] - [MCell 3 |106|NOD CLK_000_N_SYNC_2_| |*] + [MCell 2 |104| -| | ] + [MCell 3 |106|NOD IPL_D0_2_| |*] 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD inst_VPA_D| |*] + [MCell 5 |109|NOD inst_CLK_030_H| |*] 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD CLK_000_N_SYNC_5_| |*] - [MCell 7 |112|NOD CLK_000_P_SYNC_8_| |*] + [MCell 6 |110|NOD inst_AS_030_D0| |*] + [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113|NOD CLK_000_P_SYNC_10_| |*] - [MCell 9 |115|NOD inst_DS_000_DMA| |*] + [MCell 8 |113|NOD inst_RESET_OUT| |*] + [MCell 9 |115|NOD CYCLE_DMA_1_| |*] 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116|NOD CYCLE_DMA_0_| |*] - [MCell 11 |118|NOD CLK_000_P_SYNC_4_| |*] + [MCell 10 |116|NOD CLK_000_D_9_| |*] + [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] [MCell 12 |119|NOD inst_AS_000_DMA| |*] - [MCell 13 |121|NOD inst_CLK_030_H| |*] + [MCell 13 |121|NOD CYCLE_DMA_0_| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] - [MCell 14 |122|NOD CLK_000_N_SYNC_4_| |*] - [MCell 15 |124|NOD CLK_000_P_SYNC_1_| |*] + [MCell 14 |122|NOD CLK_000_D_7_| |*] + [MCell 15 |124| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Logic Array Fan-in @@ -506,38 +480,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A_0_ -Mux01| ... | ... -Mux02| Mcel 4 9 ( 211)| CLK_000_N_SYNC_1_ -Mux03| Mcel 0 14 ( 122)| CLK_000_N_SYNC_4_ +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 5 9 ( 235)| RST_DLY_2_ +Mux02| Mcel 0 9 ( 115)| CYCLE_DMA_1_ +Mux03| Mcel 0 8 ( 113)| inst_RESET_OUT Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| Mcel 2 7 ( 160)| CLK_000_P_SYNC_3_ -Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT +Mux06| Mcel 5 13 ( 241)| RST_DLY_1_ +Mux07| ... | ... Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 3 3 ( 178)| CLK_000_P_SYNC_7_ -Mux10| Input Pin ( 36)| VPA -Mux11| ... | ... -Mux12| Mcel 2 3 ( 154)| CLK_000_P_SYNC_9_ -Mux13| Mcel 3 7 ( 184)| CLK_000_P_SYNC_0_ -Mux14| Mcel 0 10 ( 116)| CYCLE_DMA_0_ +Mux09| Mcel 0 1 ( 103)| inst_DS_000_DMA +Mux10| Mcel 7 3 ( 274)| CLK_000_D_1_ +Mux11| Mcel 2 13 ( 169)| CLK_000_D_0_ +Mux12| ... | ... +Mux13| ... | ... +Mux14| ... | ... Mux15| Mcel 0 12 ( 119)| inst_AS_000_DMA -Mux16| Mcel 5 7 ( 232)| CLK_000_N_SYNC_3_ -Mux17| IOPin 6 5 ( 70)| SIZE_0_ -Mux18| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ -Mux19| Mcel 0 9 ( 115)| inst_DS_000_DMA -Mux20| IOPin 7 6 ( 79)| SIZE_1_ -Mux21| Mcel 0 1 ( 103)| inst_LDS_000_INT -Mux22| Mcel 0 2 ( 104)| CYCLE_DMA_1_ -Mux23| Mcel 2 9 ( 163)| SM_AMIGA_6_ -Mux24| Input Pin ( 86)| RST -Mux25| Mcel 0 13 ( 121)| inst_CLK_030_H -Mux26| IOPin 4 1 ( 42)| AS_000 +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| Mcel 3 14 ( 194)| CLK_000_D_6_ +Mux18| Mcel 0 5 ( 109)| inst_CLK_030_H +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| IOPin 7 5 ( 80)| RW_000 +Mux22| IOPin 6 3 ( 68)| IPL_2_ +Mux23| ... | ... +Mux24| Mcel 6 3 ( 250)| CLK_000_D_8_ +Mux25| Mcel 0 13 ( 121)| CYCLE_DMA_0_ +Mux26| ... | ... Mux27| IOPin 3 4 ( 31)| LDS_000 -Mux28| IOPin 7 5 ( 80)| RW_000 +Mux28| ... | ... Mux29| ... | ... -Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 -Mux31| ... | ... +Mux30| ... | ... +Mux31| Mcel 5 0 ( 221)| RST_DLY_0_ Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -552,20 +526,20 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_30_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| cpu_est_0_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free - 3|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig + 2| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5| RESET|OUT| | S | 1 | 4 to [ 4]| 1 XOR to [ 5] for 1 PT sig - 6|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free - 7| CLK_000_D_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig - 8| IPL_030_0_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| IPL_030_1_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT -10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -11| CLK_000_D_6_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [ 9] as logic PT + 5| IPL_030_0_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 6|inst_DS_000_ENABLE|NOD| | S | 4 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 7| | ? | | S | | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 8| | ? | | S | | 4 to [ 6]| 1 XOR free + 9| IPL_030_1_| IO| | S |10 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +11| | ? | | S | | 4 free | 1 XOR free 12| AHIGH_31_| IO| | S | 1 | 4 to [10]| 1 XOR to [12] for 1 PT sig -13| AHIGH_29_| IO| | S | 1 | 4 to [11]| 1 XOR to [13] for 1 PT sig -14|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13| AHIGH_29_| IO| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Maximum PT Capacity @@ -577,22 +551,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 2| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) - 3|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 13] logic PT(s) - 5| RESET|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 6|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) - 7| CLK_000_D_8_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 14] logic PT(s) - 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 10] logic PT(s) -10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) -11| CLK_000_D_6_|NOD| | S | 1 |=> can support up to [ 4] logic PT(s) -12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) -13| AHIGH_29_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) -14|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) -15| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) + 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 17] logic PT(s) + 2| RESET|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 3| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 14] logic PT(s) + 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 10] logic PT(s) + 6|inst_DS_000_ENABLE|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 7| | ? | | S | |=> [ 0] PT capacity + 8| | ? | | S | |=> can support up to [ 1] logic PT(s) + 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 15] logic PT(s) +10| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13| AHIGH_29_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +14| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments @@ -604,20 +578,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_30_| IO| | => |( 5) 6 7 0 |( 5) 4 3 10 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) - 2| cpu_est_0_|NOD| | => | 6 7 0 1 | 4 3 10 9 - 3|CLK_000_N_SYNC_6_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 2| RESET|OUT| | => | 6 ( 7) 0 1 | 4 ( 3) 10 9 + 3| IPL_D0_0_|NOD| | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5| RESET|OUT| | => |( 7) 0 1 2 |( 3) 10 9 8 - 6|inst_UDS_000_INT|NOD| | => | 0 1 2 3 | 10 9 8 7 - 7| CLK_000_D_8_|NOD| | => | 0 1 2 3 | 10 9 8 7 - 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 + 5| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) + 6|inst_DS_000_ENABLE|NOD| | => | 0 1 2 3 | 10 9 8 7 + 7| | | | => | 0 1 2 3 | 10 9 8 7 + 8| | | | => | 1 2 3 4 | 9 8 7 6 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 -10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 2 3 4 5 | 8 7 6 5 -11| CLK_000_D_6_|NOD| | => | 2 3 4 5 | 8 7 6 5 +10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 8 7 6 5 +11| | | | => | 2 3 4 5 | 8 7 6 5 12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) 13| AHIGH_29_| IO| | => | 3 ( 4) 5 6 | 7 ( 6) 5 4 -14|CLK_000_N_SYNC_8_|NOD| | => | 4 5 6 7 | 6 5 4 3 -15| IPL_D0_2_|NOD| | => | 4 5 6 7 | 6 5 4 3 +14| IPL_D0_1_|NOD| | => | 4 5 6 7 | 6 5 4 3 +15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO-to-Node Pin Mapping @@ -630,12 +604,12 @@ _|_________________|__|_____|____________________|________________________ _|_________________|__|___|_____|___________________________________________ 0| CLK_EXP|OUT|*| 10| => | 0 ( 1) 2 3 4 5 6 7 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 - 2| IPL_030_0_| IO|*| 8| => | 4 5 6 7 ( 8) 9 10 11 + 2| IPL_030_0_| IO|*| 8| => | 4 ( 5) 6 7 8 9 10 11 3| IPL_030_1_| IO|*| 7| => | 6 7 8 ( 9) 10 11 12 13 4| AHIGH_29_| IO|*| 6| => | 8 9 10 11 12 (13) 14 15 5| AHIGH_30_| IO|*| 5| => | 10 11 12 13 14 15 ( 0) 1 6| AHIGH_31_| IO|*| 4| => | (12) 13 14 15 0 1 2 3 - 7| RESET|OUT|*| 3| => | 14 15 0 1 2 3 4 ( 5) + 7| RESET|OUT|*| 3| => | 14 15 0 1 ( 2) 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table @@ -674,28 +648,28 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD cpu_est_0_| |*] - [MCell 3 |130|NOD CLK_000_N_SYNC_6_| |*] + [MCell 2 |128|OUT RESET| | ] + [MCell 3 |130|NOD IPL_D0_0_| |*] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|OUT RESET| | ] + [MCell 5 |133|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD inst_UDS_000_INT| |*] - [MCell 7 |136|NOD CLK_000_D_8_| |*] + [MCell 6 |134|NOD inst_DS_000_ENABLE| |*] + [MCell 7 |136| -| | ] 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] [RegIn 4 |138| -| | ] - [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] + [MCell 8 |137| -| | ] [MCell 9 |139|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] 5 [IOpin 5 | 5| IO AHIGH_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] - [MCell 11 |142|NOD CLK_000_D_6_| |*] + [MCell 10 |140|NOD SM_AMIGA_4_| |*] + [MCell 11 |142| -| | ] 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] [RegIn 6 |144| -| | ] @@ -704,8 +678,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD CLK_000_N_SYNC_8_| |*] - [MCell 15 |148|NOD IPL_D0_2_| |*] + [MCell 14 |146|NOD IPL_D0_1_| |*] + [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Logic Array Fan-in @@ -713,39 +687,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| ... | ... -Mux02| Mcel 3 15 ( 196)| IPL_D0_0_ -Mux03| Mcel 2 9 ( 163)| SM_AMIGA_6_ +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 1 6 ( 134)| inst_DS_000_ENABLE +Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| Mcel 6 6 ( 254)| CLK_000_N_SYNC_7_ +Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ -Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux08| Mcel 1 15 ( 148)| IPL_D0_2_ -Mux09| ... | ... -Mux10| Mcel 1 2 ( 128)| cpu_est_0_ -Mux11| Mcel 1 6 ( 134)| inst_UDS_000_INT -Mux12| Mcel 1 10 ( 140)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux13| Mcel 4 13 ( 217)| CLK_000_D_5_ -Mux14| Mcel 4 5 ( 205)| inst_CLK_000_NE_D0 -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D -Mux17| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux18| IOPin 6 4 ( 69)| A_0_ -Mux19| Mcel 5 15 ( 244)| IPL_D0_1_ -Mux20| ... | ... +Mux07| ... | ... +Mux08| IOPin 6 6 ( 71)| RW +Mux09| Mcel 5 5 ( 229)| SM_AMIGA_5_ +Mux10| Mcel 7 3 ( 274)| CLK_000_D_1_ +Mux11| Mcel 2 13 ( 169)| CLK_000_D_0_ +Mux12| Mcel 1 10 ( 140)| SM_AMIGA_4_ +Mux13| Mcel 1 3 ( 130)| IPL_D0_0_ +Mux14| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux15| Mcel 0 6 ( 110)| inst_AS_030_D0 +Mux16| IOPin 6 2 ( 67)| IPL_0_ +Mux17| ... | ... +Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux19| ... | ... +Mux20| Mcel 1 14 ( 146)| IPL_D0_1_ Mux21| Input Pin ( 86)| RST -Mux22| Mcel 0 6 ( 110)| CLK_000_N_SYNC_5_ -Mux23| IOPin 5 0 ( 60)| A_1_ -Mux24| Mcel 6 3 ( 250)| CLK_000_D_7_ -Mux25| Mcel 3 9 ( 187)| inst_RESET_OUT +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_0_ +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 0 3 ( 106)| IPL_D0_2_ Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| ... | ... +Mux28| Mcel 1 5 ( 133)| RN_IPL_030_0_ Mux29| ... | ... -Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 -Mux31| IOPin 5 4 ( 56)| IPL_1_ -Mux32| ... | ... +Mux30| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux31| ... | ... +Mux32| Mcel 2 2 ( 152)| SM_AMIGA_6_ --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Macrocell (MCell) Cluster Assignments @@ -759,20 +733,20 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 2]| 1 XOR free - 3|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 2| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| | ? | | S | | 4 free | 1 XOR free 5| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig - 7|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig - 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig + 6|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 6]| 1 XOR to [ 6] as logic PT + 7| | ? | | S | | 4 free | 1 XOR free + 8| AHIGH_24_| IO| | S | 1 | 4 to [ 6]| 1 XOR to [ 8] for 1 PT sig + 9| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free 11| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig 12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [13]| 1 XOR to [13] as logic PT -14|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig -15| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| CLK_000_D_10_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15|inst_AS_000_INT|NOD| | S | 2 | 4 to [15]| 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Maximum PT Capacity @@ -785,21 +759,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 17] logic PT(s) - 3|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 4| AHIGH_27_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) - 5| AHIGH_26_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) - 6| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) - 7|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) - 9| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 17] logic PT(s) -10|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -11| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) -13|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 17] logic PT(s) -14|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -15| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| | ? | | S | |=> can support up to [ 14] logic PT(s) + 5| AHIGH_26_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 6|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| AHIGH_27_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +10| | ? | | S | |=> can support up to [ 17] logic PT(s) +11| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) +13| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +14| CLK_000_D_10_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +15|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -811,20 +785,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 6 7 0 1 | 21 22 15 16 - 3|CLK_000_P_SYNC_9_|NOD| | => | 6 7 0 1 | 21 22 15 16 - 4| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 + 2| SM_AMIGA_6_|NOD| | => | 6 7 0 1 | 21 22 15 16 + 3| | | | => | 6 7 0 1 | 21 22 15 16 + 4| | | | => | 7 0 1 2 | 22 15 16 17 5| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) - 6| CLK_000_D_1_|NOD| | => | 0 1 2 3 | 15 16 17 18 - 7|CLK_000_P_SYNC_3_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 6|inst_AS_030_000_SYNC|NOD| | => | 0 1 2 3 | 15 16 17 18 + 7| | | | => | 0 1 2 3 | 15 16 17 18 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) - 9| SM_AMIGA_6_|NOD| | => | 1 2 3 4 | 16 17 18 19 -10|CLK_000_N_SYNC_11_|NOD| | => | 2 3 4 5 | 17 18 19 20 + 9| AHIGH_27_| IO| | => |( 1) 2 3 4 |( 16) 17 18 19 +10| | | | => | 2 3 4 5 | 17 18 19 20 11| CLK_000_D_4_|NOD| | => | 2 3 4 5 | 17 18 19 20 12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 -13|inst_AS_030_000_SYNC|NOD| | => | 3 4 5 6 | 18 19 20 21 -14|CLK_000_N_SYNC_10_|NOD| | => | 4 5 6 7 | 19 20 21 22 -15| inst_DTACK_D0|NOD| | => | 4 5 6 7 | 19 20 21 22 +13| CLK_000_D_0_|NOD| | => | 3 4 5 6 | 18 19 20 21 +14| CLK_000_D_10_|NOD| | => | 4 5 6 7 | 19 20 21 22 +15|inst_AS_000_INT|NOD| | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > IO-to-Node Pin Mapping @@ -836,7 +810,7 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| AHIGH_28_| IO|*| 15| => | ( 0) 1 2 3 4 5 6 7 - 1| AHIGH_27_| IO|*| 16| => | 2 3 ( 4) 5 6 7 8 9 + 1| AHIGH_27_| IO|*| 16| => | 2 3 4 5 6 7 8 ( 9) 2| AHIGH_26_| IO|*| 17| => | 4 ( 5) 6 7 8 9 10 11 3| AHIGH_25_| IO|*| 18| => | 6 7 8 9 10 11 (12) 13 4| AHIGH_24_| IO|*| 19| => | ( 8) 9 10 11 12 13 14 15 @@ -878,38 +852,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] - [MCell 3 |154|NOD CLK_000_P_SYNC_9_| |*] + [MCell 2 |152|NOD SM_AMIGA_6_| |*] + [MCell 3 |154| -| | ] 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] [RegIn 2 |156| -| | ] - [MCell 4 |155| IO AHIGH_27_| | ] + [MCell 4 |155| -| | ] [MCell 5 |157| IO AHIGH_26_| | ] 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158|NOD CLK_000_D_1_| |*] - [MCell 7 |160|NOD CLK_000_P_SYNC_3_| |*] + [MCell 6 |158|NOD inst_AS_030_000_SYNC| |*] + [MCell 7 |160| -| | ] 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] [MCell 8 |161| IO AHIGH_24_| | ] - [MCell 9 |163|NOD SM_AMIGA_6_| |*] + [MCell 9 |163| IO AHIGH_27_| | ] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164|NOD CLK_000_N_SYNC_11_| |*] + [MCell 10 |164| -| | ] [MCell 11 |166|NOD CLK_000_D_4_| |*] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] [MCell 12 |167| IO AHIGH_25_| | ] - [MCell 13 |169|NOD inst_AS_030_000_SYNC| |*] + [MCell 13 |169|NOD CLK_000_D_0_| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] - [MCell 14 |170|NOD CLK_000_N_SYNC_10_| |*] - [MCell 15 |172|NOD inst_DTACK_D0| |*] + [MCell 14 |170|NOD CLK_000_D_10_| |*] + [MCell 15 |172|NOD inst_AS_000_INT| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Logic Array Fan-in @@ -918,38 +892,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 1 10 ( 140)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux03| IOPin 5 0 ( 60)| A_1_ +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 4 9 ( 211)| CLK_000_D_3_ +Mux03| Mcel 4 2 ( 200)| CLK_000_D_2_ Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ +Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT -Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux08| Mcel 0 10 ( 116)| CLK_000_D_9_ +Mux09| Mcel 2 6 ( 158)| inst_AS_030_000_SYNC +Mux10| Mcel 7 3 ( 274)| CLK_000_D_1_ Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux12| IOPin 5 2 ( 58)| FC_1_ -Mux13| Mcel 2 9 ( 163)| SM_AMIGA_6_ -Mux14| ... | ... -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 2 ( 176)| CLK_000_N_SYNC_0_ -Mux17| Mcel 5 3 ( 226)| CLK_000_N_SYNC_9_ -Mux18| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ -Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux20| Mcel 5 11 ( 238)| CLK_000_P_SYNC_2_ -Mux21| Mcel 7 6 ( 278)| RN_BGACK_030 -Mux22| Mcel 2 2 ( 152)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux14| Input Pin ( 11)| CLK_000 +Mux15| Mcel 0 6 ( 110)| inst_AS_030_D0 +Mux16| Mcel 2 15 ( 172)| inst_AS_000_INT +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| ... | ... +Mux22| Mcel 6 10 ( 260)| inst_AMIGA_BUS_ENABLE_DMA_LOW Mux23| ... | ... Mux24| ... | ... -Mux25| Mcel 6 13 ( 265)| CLK_000_D_0_ -Mux26| Mcel 6 7 ( 256)| CLK_000_D_3_ -Mux27| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux28| Mcel 0 7 ( 112)| CLK_000_P_SYNC_8_ -Mux29| ... | ... -Mux30| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC -Mux31| Mcel 2 14 ( 170)| CLK_000_N_SYNC_10_ -Mux32| ... | ... +Mux25| ... | ... +Mux26| ... | ... +Mux27| ... | ... +Mux28| ... | ... +Mux29| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux30| Mcel 2 13 ( 169)| CLK_000_D_0_ +Mux31| ... | ... +Mux32| Mcel 2 2 ( 152)| SM_AMIGA_6_ --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Macrocell (MCell) Cluster Assignments @@ -963,20 +937,20 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 3 | 4 to [ 4]| 1 XOR free + 2| cpu_est_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| RST_DLY_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free - 7|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 6|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 6]| 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_RESET_OUT|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10| RST_DLY_0_|NOD| | S | 3 | 4 to [10]| 1 XOR free -11| CLK_000_D_9_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig + 9| cpu_est_3_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free +10|inst_UDS_000_INT|NOD| | S | 2 | 4 to [10]| 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|CLK_000_N_SYNC_12_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| RST_DLY_2_|NOD| | S | 2 | 4 to [14]| 1 XOR free -15| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [13]| 1 XOR to [13] +14| CLK_000_D_6_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Maximum PT Capacity @@ -988,22 +962,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| VMA| IO| | S | 3 |=> can support up to [ 9] logic PT(s) - 1| BG_000| IO| | S | 2 |=> can support up to [ 13] logic PT(s) - 2|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 3|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 3 |=> can support up to [ 13] logic PT(s) - 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 6| RST_DLY_1_|NOD| | S | 4 |=> can support up to [ 17] logic PT(s) - 7|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 8| UDS_000| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 9|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) -10| RST_DLY_0_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) -11| CLK_000_D_9_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -12| LDS_000| IO| | S | 1 |=> can support up to [ 13] logic PT(s) -13|CLK_000_N_SYNC_12_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -14| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) -15| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) + 1| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 2| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 6|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 10] logic PT(s) + 9| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) +10|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 17] logic PT(s) +14| CLK_000_D_6_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -1015,20 +989,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2|CLK_000_N_SYNC_0_|NOD| | => | 6 7 0 1 | 29 28 35 34 - 3|CLK_000_P_SYNC_7_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2| cpu_est_0_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6| RST_DLY_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 - 7|CLK_000_P_SYNC_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6|inst_LDS_000_INT|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7| | | | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 - 9|inst_RESET_OUT|NOD| | => | 1 2 3 4 | 34 33 32 31 -10| RST_DLY_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 -11| CLK_000_D_9_|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9| cpu_est_3_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10|inst_UDS_000_INT|NOD| | => | 2 3 4 5 | 33 32 31 30 +11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13|CLK_000_N_SYNC_12_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| RST_DLY_2_|NOD| | => | 4 5 6 7 | 31 30 29 28 -15| IPL_D0_0_|NOD| | => | 4 5 6 7 | 31 30 29 28 +13| cpu_est_2_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| CLK_000_D_6_|NOD| | => | 4 5 6 7 | 31 30 29 28 +15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > IO-to-Node Pin Mapping @@ -1084,8 +1058,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD CLK_000_N_SYNC_0_| |*] - [MCell 3 |178|NOD CLK_000_P_SYNC_7_| |*] + [MCell 2 |176|NOD cpu_est_0_| |*] + [MCell 3 |178| -| | ] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] [RegIn 2 |180| -| | ] @@ -1094,28 +1068,28 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD RST_DLY_1_| |*] - [MCell 7 |184|NOD CLK_000_P_SYNC_0_| |*] + [MCell 6 |182|NOD inst_LDS_000_INT| |*] + [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] - [MCell 9 |187|NOD inst_RESET_OUT| |*] + [MCell 9 |187|NOD cpu_est_3_| |*] 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD RST_DLY_0_| |*] - [MCell 11 |190|NOD CLK_000_D_9_| |*] + [MCell 10 |188|NOD inst_UDS_000_INT| |*] + [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD CLK_000_N_SYNC_12_| |*] + [MCell 13 |193|NOD cpu_est_2_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD RST_DLY_2_| |*] - [MCell 15 |196|NOD IPL_D0_0_| |*] + [MCell 14 |194|NOD CLK_000_D_6_| |*] + [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Logic Array Fan-in @@ -1123,39 +1097,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 5 9 ( 235)| inst_DS_000_ENABLE -Mux02| Mcel 0 5 ( 109)| inst_VPA_D -Mux03| Input Pin ( 11)| CLK_000 -Mux04| Mcel 3 6 ( 182)| RST_DLY_1_ -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux06| ... | ... -Mux07| Mcel 7 6 ( 278)| RN_BGACK_030 -Mux08| Mcel 2 10 ( 164)| CLK_000_N_SYNC_11_ -Mux09| Mcel 0 1 ( 103)| inst_LDS_000_INT -Mux10| Mcel 1 2 ( 128)| cpu_est_0_ -Mux11| Mcel 1 6 ( 134)| inst_UDS_000_INT -Mux12| Mcel 3 9 ( 187)| inst_RESET_OUT +Mux00| IOPin 6 4 ( 69)| A_0_ +Mux01| Mcel 3 0 ( 173)| RN_VMA +Mux02| Mcel 3 10 ( 188)| inst_UDS_000_INT +Mux03| Mcel 3 2 ( 176)| cpu_est_0_ +Mux04| IOPin 2 6 ( 21)| BG_030 +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 7 6 ( 79)| SIZE_1_ +Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux08| ... | ... +Mux09| Mcel 2 6 ( 158)| inst_AS_030_000_SYNC +Mux10| Mcel 7 3 ( 274)| CLK_000_D_1_ +Mux11| Mcel 1 6 ( 134)| inst_DS_000_ENABLE +Mux12| ... | ... Mux13| ... | ... -Mux14| Mcel 5 4 ( 227)| cpu_est_2_ -Mux15| Mcel 5 1 ( 223)| cpu_est_3_ -Mux16| IOPin 6 2 ( 67)| IPL_0_ -Mux17| Mcel 3 1 ( 175)| RN_BG_000 -Mux18| Mcel 2 6 ( 158)| CLK_000_D_1_ -Mux19| Mcel 7 1 ( 271)| inst_AS_030_D0 -Mux20| Mcel 3 10 ( 188)| RST_DLY_0_ -Mux21| Input Pin ( 14)| nEXP_SPACE -Mux22| Mcel 2 2 ( 152)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux23| IOPin 2 6 ( 21)| BG_030 -Mux24| Mcel 3 14 ( 194)| RST_DLY_2_ -Mux25| Mcel 6 13 ( 265)| CLK_000_D_0_ -Mux26| Mcel 3 0 ( 173)| RN_VMA -Mux27| Mcel 5 5 ( 229)| SM_AMIGA_0_ -Mux28| Mcel 6 10 ( 260)| CLK_000_P_SYNC_6_ -Mux29| Mcel 3 13 ( 193)| CLK_000_N_SYNC_12_ -Mux30| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ -Mux31| Mcel 5 12 ( 239)| cpu_est_1_ -Mux32| Mcel 1 7 ( 136)| CLK_000_D_8_ +Mux14| Mcel 4 5 ( 205)| CLK_000_D_5_ +Mux15| Mcel 0 6 ( 110)| inst_AS_030_D0 +Mux16| Mcel 3 6 ( 182)| inst_LDS_000_INT +Mux17| IOPin 6 5 ( 70)| SIZE_0_ +Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Mcel 3 13 ( 193)| cpu_est_2_ +Mux22| Mcel 2 2 ( 152)| SM_AMIGA_6_ +Mux23| Mcel 6 6 ( 254)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux24| Input Pin ( 86)| RST +Mux25| ... | ... +Mux26| ... | ... +Mux27| Mcel 3 1 ( 175)| RN_BG_000 +Mux28| Mcel 5 2 ( 224)| inst_VPA_D +Mux29| ... | ... +Mux30| Mcel 2 13 ( 169)| CLK_000_D_0_ +Mux31| ... | ... +Mux32| Mcel 5 8 ( 233)| cpu_est_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1169,18 +1143,18 @@ Mux32| Mcel 1 7 ( 136)| CLK_000_D_8_ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| BERR| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 1]| 1 XOR free - 2|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| | ? | | S | | 4 free | 1 XOR free + 5| CLK_000_D_5_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 9| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| CIIN_0|NOD| | S | 2 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| CLK_000_D_5_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1196,19 +1170,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 18] logic PT(s) - 2|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 17] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) - 5|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 18] logic PT(s) + 5| CLK_000_D_5_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 6|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 17] logic PT(s) 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 9|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 9| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 10| CIIN_0|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) -11| | ? | | S | |=> can support up to [ 13] logic PT(s) -12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) -13| CLK_000_D_5_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1221,18 +1195,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| BERR| IO| | => | 5 6 7 ( 0)| 46 47 48 ( 41) 1|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 - 2|inst_CLK_OUT_PRE_50|NOD| | => | 6 7 0 1 | 47 48 41 42 + 2| CLK_000_D_2_|NOD| | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5|inst_CLK_000_NE_D0|NOD| | => | 7 0 1 2 | 48 41 42 43 - 6| | | | => | 0 1 2 3 | 41 42 43 44 + 5| CLK_000_D_5_|NOD| | => | 7 0 1 2 | 48 41 42 43 + 6|inst_CLK_OUT_PRE_50|NOD| | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 8|inst_CLK_OUT_PRE_D|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9|CLK_000_N_SYNC_1_|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9| CLK_000_D_3_|NOD| | => | 1 2 3 4 | 42 43 44 45 10| CIIN_0|NOD| | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) -13| CLK_000_D_5_|NOD| | => | 3 4 5 6 | 44 45 46 47 +13| | | | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 --------------------------------------------------------------------------- @@ -1288,23 +1262,23 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 42| IO AS_000|*|*] [RegIn 1 |201| -| | ] - [MCell 2 |200|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 2 |200|NOD CLK_000_D_2_| |*] [MCell 3 |202| -| | ] 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD inst_CLK_000_NE_D0| |*] + [MCell 5 |205|NOD CLK_000_D_5_| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] - [MCell 6 |206| -| | ] + [MCell 6 |206|NOD inst_CLK_OUT_PRE_50| |*] [MCell 7 |208| -| | ] 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] [MCell 8 |209|NOD inst_CLK_OUT_PRE_D| |*] - [MCell 9 |211|NOD CLK_000_N_SYNC_1_| |*] + [MCell 9 |211|NOD CLK_000_D_3_| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1314,7 +1288,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] [MCell 12 |215|OUT CIIN| | ] - [MCell 13 |217|NOD CLK_000_D_5_| |*] + [MCell 13 |217| -| | ] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] [RegIn 7 |219| -| | ] @@ -1327,38 +1301,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 2 11 ( 166)| CLK_000_D_4_ +Mux00| Mcel 4 6 ( 206)| inst_CLK_OUT_PRE_50 Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| IOPin 4 1 ( 42)| AS_000 -Mux03| IOPin 0 2 ( 93)| A_DECODE_20_ -Mux04| IOPin 1 4 ( 6)| AHIGH_29_ -Mux05| IOPin 2 4 ( 19)| AHIGH_24_ -Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT -Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| IOPin 2 2 ( 17)| AHIGH_26_ -Mux10| Mcel 7 1 ( 271)| inst_AS_030_D0 -Mux11| IOPin 2 1 ( 16)| AHIGH_27_ -Mux12| Mcel 4 10 ( 212)| CIIN_0 -Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| IOPin 2 0 ( 15)| AHIGH_28_ -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 2 ( 176)| CLK_000_N_SYNC_0_ -Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux03| IOPin 2 1 ( 16)| AHIGH_27_ +Mux04| IOPin 0 0 ( 91)| FPU_SENSE +Mux05| IOPin 0 3 ( 94)| A_DECODE_21_ +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| IOPin 2 0 ( 15)| AHIGH_28_ +Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 7 3 ( 274)| CLK_000_D_1_ +Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux13| IOPin 1 4 ( 6)| AHIGH_29_ +Mux14| IOPin 2 4 ( 19)| AHIGH_24_ +Mux15| Mcel 0 6 ( 110)| inst_AS_030_D0 +Mux16| Mcel 2 15 ( 172)| inst_AS_000_INT +Mux17| IOPin 0 2 ( 93)| A_DECODE_20_ Mux18| IOPin 7 0 ( 85)| A_DECODE_23_ -Mux19| IOPin 7 3 ( 82)| AS_030 +Mux19| IOPin 1 5 ( 5)| AHIGH_30_ Mux20| IOPin 7 1 ( 84)| A_DECODE_22_ -Mux21| IOPin 7 5 ( 80)| RW_000 +Mux21| Input Pin ( 14)| nEXP_SPACE Mux22| IOPin 2 3 ( 18)| AHIGH_25_ -Mux23| Mcel 6 2 ( 248)| inst_AS_000_INT -Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Mcel 4 10 ( 212)| CIIN_0 Mux25| IOPin 1 6 ( 4)| AHIGH_31_ -Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux27| Mcel 4 2 ( 200)| inst_CLK_OUT_PRE_50 -Mux28| IOPin 1 5 ( 5)| AHIGH_30_ -Mux29| Mcel 3 13 ( 193)| CLK_000_N_SYNC_12_ -Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 -Mux31| IOPin 0 3 ( 94)| A_DECODE_21_ +Mux26| IOPin 2 2 ( 17)| AHIGH_26_ +Mux27| Mcel 4 2 ( 200)| CLK_000_D_2_ +Mux28| IOPin 7 5 ( 80)| RW_000 +Mux29| Mcel 2 11 ( 166)| CLK_000_D_4_ +Mux30| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux31| IOPin 0 4 ( 95)| A_DECODE_18_ Mux32| IOPin 3 7 ( 28)| BGACK_000 --------------------------------------------------------------------------- =========================================================================== @@ -1371,22 +1345,22 @@ Mux32| IOPin 3 7 ( 28)| BGACK_000 | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| SM_AMIGA_i_7_|NOD| | S |14 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| cpu_est_3_|NOD| | S | 3 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 2| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 0]| 1 XOR free - 3|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 to [ 1]| 1 XOR to [ 3] for 1 PT sig - 4| cpu_est_2_|NOD| | S | 4 | 4 to [ 2]| 1 XOR to [ 2] as logic PT - 5| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 4]| 1 XOR free + 0| RST_DLY_0_|NOD| | S | 4 | 4 to [ 0]| 1 XOR free + 1| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 to [ 4]| 1 XOR free + 4| SM_AMIGA_i_7_|NOD| | S |13 :+: 1| 4 to [ 4]| 1 XOR to [ 4] + 5| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 4]| 1 XOR to [ 4] as logic PT 6| SM_AMIGA_2_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free - 7|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 7] for 1 PT sig - 8| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free - 9|inst_DS_000_ENABLE|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| SM_AMIGA_4_|NOD| | S | 3 | 4 to [10]| 1 XOR free -11|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig -12| cpu_est_1_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13| SM_AMIGA_1_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| N_226|NOD| | S | 3 | 4 to [14]| 1 XOR free -15| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig + 7| | ? | | S | | 4 to [ 5]| 1 XOR free + 8| cpu_est_1_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free + 9| RST_DLY_2_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10| SM_AMIGA_3_|NOD| | S | 4 :+: 1| 4 to [10]| 1 XOR to [10] +11| | ? | | S | | 4 free | 1 XOR free +12| | ? | | S | | 4 free | 1 XOR free +13| RST_DLY_1_|NOD| | S | 2 :+: 1| 4 to [13]| 1 XOR to [13] +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Maximum PT Capacity @@ -1398,22 +1372,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_i_7_|NOD| | S |14 |=> can support up to [ 15] logic PT(s) - 1| cpu_est_3_|NOD| | S | 3 |=> can support up to [ 4] logic PT(s) - 2| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) - 3|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 4| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 5| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) + 0| RST_DLY_0_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) + 1| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 2| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| SM_AMIGA_i_7_|NOD| | S |13 :+: 1|=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) 6| SM_AMIGA_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 7|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 8| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 9|inst_DS_000_ENABLE|NOD| | S | 5 |=> can support up to [ 9] logic PT(s) -10| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) -11|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -12| cpu_est_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) -13| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) -14| N_226|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) -15| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 7| | ? | | S | |=> can support up to [ 1] logic PT(s) + 8| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 9| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) +10| SM_AMIGA_3_|NOD| | S | 4 :+: 1|=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| | ? | | S | |=> can support up to [ 15] logic PT(s) +13| RST_DLY_1_|NOD| | S | 2 :+: 1|=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Node-Pin Assignments @@ -1423,22 +1397,22 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| SM_AMIGA_i_7_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1| cpu_est_3_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 2| SM_AMIGA_3_|NOD| | => | 6 7 0 1 | 54 53 60 59 - 3|CLK_000_N_SYNC_9_|NOD| | => | 6 7 0 1 | 54 53 60 59 - 4| cpu_est_2_|NOD| | => | 7 0 1 2 | 53 60 59 58 - 5| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 0| RST_DLY_0_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| SM_AMIGA_1_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2| inst_VPA_D|NOD| | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4| SM_AMIGA_i_7_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5| SM_AMIGA_5_|NOD| | => | 7 0 1 2 | 53 60 59 58 6| SM_AMIGA_2_|NOD| | => | 0 1 2 3 | 60 59 58 57 - 7|CLK_000_N_SYNC_3_|NOD| | => | 0 1 2 3 | 60 59 58 57 - 8| SM_AMIGA_5_|NOD| | => | 1 2 3 4 | 59 58 57 56 - 9|inst_DS_000_ENABLE|NOD| | => | 1 2 3 4 | 59 58 57 56 -10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 58 57 56 55 -11|CLK_000_P_SYNC_2_|NOD| | => | 2 3 4 5 | 58 57 56 55 -12| cpu_est_1_|NOD| | => | 3 4 5 6 | 57 56 55 54 -13| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 57 56 55 54 -14| N_226|NOD| | => | 4 5 6 7 | 56 55 54 53 -15| IPL_D0_1_|NOD| | => | 4 5 6 7 | 56 55 54 53 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| cpu_est_1_|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9| RST_DLY_2_|NOD| | => | 1 2 3 4 | 59 58 57 56 +10| SM_AMIGA_3_|NOD| | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| | | | => | 3 4 5 6 | 57 56 55 54 +13| RST_DLY_1_|NOD| | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping @@ -1487,43 +1461,43 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD SM_AMIGA_i_7_| |*] - [MCell 1 |223|NOD cpu_est_3_| |*] + [MCell 0 |221|NOD RST_DLY_0_| |*] + [MCell 1 |223|NOD SM_AMIGA_1_| |*] 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] [RegIn 1 |225| -| | ] - [MCell 2 |224|NOD SM_AMIGA_3_| |*] - [MCell 3 |226|NOD CLK_000_N_SYNC_9_| |*] + [MCell 2 |224|NOD inst_VPA_D| |*] + [MCell 3 |226| -| | ] 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD cpu_est_2_| |*] - [MCell 5 |229|NOD SM_AMIGA_0_| |*] + [MCell 4 |227|NOD SM_AMIGA_i_7_| |*] + [MCell 5 |229|NOD SM_AMIGA_5_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] [MCell 6 |230|NOD SM_AMIGA_2_| |*] - [MCell 7 |232|NOD CLK_000_N_SYNC_3_| |*] + [MCell 7 |232| -| | ] 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233|NOD SM_AMIGA_5_| |*] - [MCell 9 |235|NOD inst_DS_000_ENABLE| |*] + [MCell 8 |233|NOD cpu_est_1_| |*] + [MCell 9 |235|NOD RST_DLY_2_| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] - [MCell 10 |236|NOD SM_AMIGA_4_| |*] - [MCell 11 |238|NOD CLK_000_P_SYNC_2_| |*] + [MCell 10 |236|NOD SM_AMIGA_3_| |*] + [MCell 11 |238| -| | ] 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD cpu_est_1_| |*] - [MCell 13 |241|NOD SM_AMIGA_1_| |*] + [MCell 12 |239| -| | ] + [MCell 13 |241|NOD RST_DLY_1_| |*] 7 [IOpin 7 | 53| -| | ] [RegIn 7 |243| -| | ] - [MCell 14 |242|NOD N_226| |*] - [MCell 15 |244|NOD IPL_D0_1_| |*] + [MCell 14 |242| -| | ] + [MCell 15 |244| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Logic Array Fan-in @@ -1531,39 +1505,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC -Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_5_ -Mux03| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 5 6 ( 230)| SM_AMIGA_2_ +Mux02| Mcel 5 10 ( 236)| SM_AMIGA_3_ +Mux03| Mcel 3 2 ( 176)| cpu_est_0_ Mux04| ... | ... -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux06| Mcel 5 13 ( 241)| SM_AMIGA_1_ -Mux07| ... | ... -Mux08| IOPin 6 6 ( 71)| RW -Mux09| Mcel 5 2 ( 224)| SM_AMIGA_3_ -Mux10| Mcel 5 4 ( 227)| cpu_est_2_ -Mux11| Mcel 5 6 ( 230)| SM_AMIGA_2_ -Mux12| Mcel 7 1 ( 271)| inst_AS_030_D0 -Mux13| Mcel 0 15 ( 124)| CLK_000_P_SYNC_1_ -Mux14| Mcel 4 5 ( 205)| inst_CLK_000_NE_D0 -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 2 ( 176)| CLK_000_N_SYNC_0_ -Mux17| Mcel 5 12 ( 239)| cpu_est_1_ -Mux18| Mcel 1 2 ( 128)| cpu_est_0_ -Mux19| Mcel 5 10 ( 236)| SM_AMIGA_4_ -Mux20| Mcel 1 14 ( 146)| CLK_000_N_SYNC_8_ -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 2 15 ( 172)| inst_DTACK_D0 -Mux23| Mcel 2 9 ( 163)| SM_AMIGA_6_ -Mux24| Mcel 5 14 ( 242)| N_226 -Mux25| Mcel 0 3 ( 106)| CLK_000_N_SYNC_2_ +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| Mcel 5 13 ( 241)| RST_DLY_1_ +Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux08| Mcel 6 7 ( 256)| inst_DTACK_D0 +Mux09| Mcel 5 2 ( 224)| inst_VPA_D +Mux10| Mcel 7 3 ( 274)| CLK_000_D_1_ +Mux11| Mcel 2 13 ( 169)| CLK_000_D_0_ +Mux12| Mcel 1 10 ( 140)| SM_AMIGA_4_ +Mux13| Input Pin ( 36)| VPA +Mux14| Mcel 5 5 ( 229)| SM_AMIGA_5_ +Mux15| Mcel 4 2 ( 200)| CLK_000_D_2_ +Mux16| ... | ... +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 5 9 ( 235)| RST_DLY_2_ +Mux19| ... | ... +Mux20| Mcel 5 8 ( 233)| cpu_est_1_ +Mux21| Mcel 3 13 ( 193)| cpu_est_2_ +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_0_ +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| RST_DLY_0_ Mux26| Mcel 3 0 ( 173)| RN_VMA -Mux27| Mcel 5 5 ( 229)| SM_AMIGA_0_ -Mux28| Mcel 0 5 ( 109)| inst_VPA_D -Mux29| Mcel 3 13 ( 193)| CLK_000_N_SYNC_12_ -Mux30| Mcel 5 1 ( 223)| cpu_est_3_ -Mux31| IOPin 5 4 ( 56)| IPL_1_ -Mux32| Mcel 5 9 ( 235)| inst_DS_000_ENABLE +Mux27| Mcel 2 6 ( 158)| inst_AS_030_000_SYNC +Mux28| ... | ... +Mux29| ... | ... +Mux30| Mcel 5 1 ( 223)| SM_AMIGA_1_ +Mux31| ... | ... +Mux32| Mcel 2 2 ( 152)| SM_AMIGA_6_ --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments @@ -1577,20 +1551,20 @@ Mux32| Mcel 5 9 ( 235)| inst_DS_000_ENABLE _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free - 3| CLK_000_D_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 2| SIZE_DMA_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3| CLK_000_D_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free - 5| SIZE_DMA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig - 7| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 5| SM_AMIGA_0_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 7| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig 8| A_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| SIZE_DMA_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig + 9| SIZE_DMA_1_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [10]| 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15| CLK_000_D_10_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13| | ? | | S | | 4 free | 1 XOR free +14| CLK_000_D_12_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Maximum PT Capacity @@ -1604,20 +1578,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| RW| IO| | S | 2 |=> can support up to [ 9] logic PT(s) 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 2|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) - 3| CLK_000_D_7_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| E|OUT| | S | 2 |=> can support up to [ 13] logic PT(s) - 5| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) - 6|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 7| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 8| A_0_| IO| | S | 3 |=> can support up to [ 13] logic PT(s) - 9| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) -10|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -11| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) -12| SIZE_0_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) -13| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) -14|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -15| CLK_000_D_10_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 2| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 3| CLK_000_D_8_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| E|OUT| | S | 2 |=> can support up to [ 9] logic PT(s) + 5| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 6|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 7| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 8| A_0_| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 9| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| SIZE_0_| IO| | S | 1 |=> can support up to [ 19] logic PT(s) +13| | ? | | S | |=> can support up to [ 18] logic PT(s) +14| CLK_000_D_12_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1629,20 +1603,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 2|inst_AS_000_INT|NOD| | => | 6 7 0 1 | 71 72 65 66 - 3| CLK_000_D_7_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 2| SIZE_DMA_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3| CLK_000_D_8_|NOD| | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5| SIZE_DMA_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6|CLK_000_N_SYNC_7_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 7| CLK_000_D_3_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 5| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 0 1 2 3 | 65 66 67 68 + 7| inst_DTACK_D0|NOD| | => | 0 1 2 3 | 65 66 67 68 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9| SIZE_DMA_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10|CLK_000_P_SYNC_6_|NOD| | => | 2 3 4 5 | 67 68 69 70 -11| CLK_000_D_2_|NOD| | => | 2 3 4 5 | 67 68 69 70 + 9| SIZE_DMA_1_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 2 3 4 5 | 67 68 69 70 +11| | | | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13| CLK_000_D_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 -14|CLK_000_P_SYNC_5_|NOD| | => | 4 5 6 7 | 69 70 71 72 -15| CLK_000_D_10_|NOD| | => | 4 5 6 7 | 69 70 71 72 +13| | | | => | 3 4 5 6 | 68 69 70 71 +14| CLK_000_D_12_|NOD| | => | 4 5 6 7 | 69 70 71 72 +15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO-to-Node Pin Mapping @@ -1698,38 +1672,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 66|OUT E|*| ] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD inst_AS_000_INT| |*] - [MCell 3 |250|NOD CLK_000_D_7_| |*] + [MCell 2 |248|NOD SIZE_DMA_0_| |*] + [MCell 3 |250|NOD CLK_000_D_8_| |*] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|OUT E| | ] - [MCell 5 |253|NOD SIZE_DMA_1_| |*] + [MCell 5 |253|NOD SM_AMIGA_0_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD CLK_000_N_SYNC_7_| |*] - [MCell 7 |256|NOD CLK_000_D_3_| |*] + [MCell 6 |254|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 7 |256|NOD inst_DTACK_D0| |*] 4 [IOpin 4 | 69| IO A_0_|*|*] paired w/[ RN_A_0_] [RegIn 4 |258| -| | ] [MCell 8 |257|NOD RN_A_0_| |*] paired w/[ A_0_] - [MCell 9 |259|NOD SIZE_DMA_0_| |*] + [MCell 9 |259|NOD SIZE_DMA_1_| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD CLK_000_P_SYNC_6_| |*] - [MCell 11 |262|NOD CLK_000_D_2_| |*] + [MCell 10 |260|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 11 |262| -| | ] 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] [RegIn 6 |264| -| | ] [MCell 12 |263| IO SIZE_0_| | ] - [MCell 13 |265|NOD CLK_000_D_0_| |*] + [MCell 13 |265| -| | ] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD CLK_000_P_SYNC_5_| |*] - [MCell 15 |268|NOD CLK_000_D_10_| |*] + [MCell 14 |266|NOD CLK_000_D_12_| |*] + [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Logic Array Fan-in @@ -1737,39 +1711,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 6 0 ( 245)| RN_RW +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_5_ -Mux03| Mcel 3 11 ( 190)| CLK_000_D_9_ -Mux04| Mcel 6 2 ( 248)| inst_AS_000_INT -Mux05| Mcel 1 3 ( 130)| CLK_000_N_SYNC_6_ +Mux02| Mcel 5 8 ( 233)| cpu_est_1_ +Mux03| IOPin 5 0 ( 60)| A_1_ +Mux04| Mcel 6 2 ( 248)| SIZE_DMA_0_ +Mux05| Mcel 6 6 ( 254)| inst_AMIGA_BUS_ENABLE_DMA_HIGH Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 1 11 ( 142)| CLK_000_D_6_ -Mux08| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D -Mux09| Mcel 6 11 ( 262)| CLK_000_D_2_ -Mux10| Mcel 5 1 ( 223)| cpu_est_3_ -Mux11| Mcel 6 14 ( 266)| CLK_000_P_SYNC_5_ -Mux12| Mcel 7 1 ( 271)| inst_AS_030_D0 -Mux13| Mcel 0 11 ( 118)| CLK_000_P_SYNC_4_ -Mux14| Input Pin ( 11)| CLK_000 +Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| IOPin 3 5 ( 30)| DTACK +Mux10| Mcel 5 1 ( 223)| SM_AMIGA_1_ +Mux11| Mcel 7 3 ( 274)| CLK_000_D_1_ +Mux12| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux13| Mcel 6 8 ( 257)| RN_A_0_ +Mux14| ... | ... Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| ... | ... -Mux17| Mcel 5 12 ( 239)| cpu_est_1_ -Mux18| Mcel 2 6 ( 158)| CLK_000_D_1_ -Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux20| IOPin 3 3 ( 32)| UDS_000 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| SIZE_DMA_1_ -Mux23| ... | ... -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 3 9 ( 187)| inst_RESET_OUT +Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux17| Mcel 6 0 ( 245)| RN_RW +Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux19| ... | ... +Mux20| Mcel 0 14 ( 122)| CLK_000_D_7_ +Mux21| Mcel 3 13 ( 193)| cpu_est_2_ +Mux22| Mcel 6 10 ( 260)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux23| Mcel 7 0 ( 269)| CLK_000_D_11_ +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 3 9 ( 187)| cpu_est_3_ Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| SIZE_DMA_0_ -Mux28| Mcel 6 8 ( 257)| RN_A_0_ -Mux29| Mcel 5 4 ( 227)| cpu_est_2_ -Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| ... | ... +Mux29| ... | ... +Mux30| Mcel 2 13 ( 169)| CLK_000_D_0_ Mux31| ... | ... -Mux32| ... | ... +Mux32| Mcel 6 5 ( 253)| SM_AMIGA_0_ --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1781,17 +1755,17 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| RW_000| IO| | S | 3 | 4 to [ 0]| 1 XOR free - 1|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| CLK_000_D_12_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3| | ? | | S | | 4 free | 1 XOR free - 4| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| | ? | | S | | 4 free | 1 XOR free - 6| BGACK_030| IO| | S | 3 | 4 to [ 6]| 1 XOR free + 0| CLK_000_D_11_|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| RW_000| IO| | S | 4 | 4 to [ 1]| 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free + 5| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| DSACK1| IO| | S | 4 | 4 to [ 9]| 1 XOR free -10| CLK_000_D_11_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_1_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig @@ -1808,18 +1782,18 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW_000| IO| | S | 3 |=> can support up to [ 13] logic PT(s) - 1|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| CLK_000_D_12_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) - 3| | ? | | S | |=> can support up to [ 18] logic PT(s) - 4| FPU_CS|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) - 5| | ? | | S | |=> can support up to [ 14] logic PT(s) - 6| BGACK_030| IO| | S | 3 |=> can support up to [ 19] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| AS_030| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 9| DSACK1| IO| | S | 4 |=> can support up to [ 18] logic PT(s) -10| CLK_000_D_11_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 17] logic PT(s) + 0| CLK_000_D_11_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 1| RW_000| IO| | S | 4 |=> can support up to [ 18] logic PT(s) + 2| | ? | | S | |=> can support up to [ 9] logic PT(s) + 3| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) + 5| FPU_CS|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 14] logic PT(s) + 8| AS_030| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| DSACK1| IO| | S | 4 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) 12| SIZE_1_| IO| | S | 1 |=> can support up to [ 19] logic PT(s) 13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) @@ -1833,17 +1807,17 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 7] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 - 1|inst_AS_030_D0|NOD| | => | 5 6 7 0 | 80 79 78 85 - 2| CLK_000_D_12_|NOD| | => | 6 7 0 1 | 79 78 85 84 - 3| | | | => | 6 7 0 1 | 79 78 85 84 - 4| FPU_CS|OUT| | => |( 7) 0 1 2 |( 78) 85 84 83 - 5| | | | => | 7 0 1 2 | 78 85 84 83 - 6| BGACK_030| IO| | => | 0 1 ( 2) 3 | 85 84 ( 83) 82 + 0| CLK_000_D_11_|NOD| | => | 5 6 7 0 | 80 79 78 85 + 1| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 + 2| | | | => | 6 7 0 1 | 79 78 85 84 + 3| CLK_000_D_1_|NOD| | => | 6 7 0 1 | 79 78 85 84 + 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) + 5| FPU_CS|OUT| | => |( 7) 0 1 2 |( 78) 85 84 83 + 6| | | | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 9| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) -10| CLK_000_D_11_|NOD| | => | 2 3 4 5 | 83 82 81 80 +10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) 13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 82 81 80 79 @@ -1861,12 +1835,12 @@ _|_________________|__|_____|____________________|________________________ _|_________________|__|___|_____|___________________________________________ 0| A_DECODE_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 1| A_DECODE_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 - 2| BGACK_030| IO|*| 83| => | 4 5 ( 6) 7 8 9 10 11 + 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 4| DSACK1| IO|*| 81| => | 8 ( 9) 10 11 12 13 14 15 - 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 + 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 0 ( 1) 6| SIZE_1_| IO|*| 79| => | (12) 13 14 15 0 1 2 3 - 7| FPU_CS|OUT|*| 78| => | 14 15 0 1 2 3 ( 4) 5 + 7| FPU_CS|OUT|*| 78| => | 14 15 0 1 2 3 4 ( 5) --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table @@ -1900,22 +1874,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 85|INP A_DECODE_23_|*|*] [RegIn 0 |270| -| | ] - [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] - [MCell 1 |271|NOD inst_AS_030_D0| |*] + [MCell 0 |269|NOD CLK_000_D_11_| |*] + [MCell 1 |271|NOD RN_RW_000| |*] paired w/[ RW_000] 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD CLK_000_D_12_| |*] - [MCell 3 |274| -| | ] + [MCell 2 |272| -| | ] + [MCell 3 |274|NOD CLK_000_D_1_| |*] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] - [MCell 4 |275|OUT FPU_CS| | ] - [MCell 5 |277| -| | ] + [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] + [MCell 5 |277|OUT FPU_CS| | ] 3 [IOpin 3 | 82| IO AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] + [MCell 6 |278| -| | ] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK1|*| ] paired w/[ RN_DSACK1] @@ -1925,7 +1899,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] [RegIn 5 |285| -| | ] - [MCell 10 |284|NOD CLK_000_D_11_| |*] + [MCell 10 |284| -| | ] [MCell 11 |286| -| | ] 6 [IOpin 6 | 79| IO SIZE_1_|*|*] @@ -1944,37 +1918,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| Mcel 2 13 ( 169)| CLK_000_D_0_ Mux01| IOPin 4 0 ( 41)| BERR -Mux02| IOPin 4 1 ( 42)| AS_000 -Mux03| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ -Mux04| Mcel 7 2 ( 272)| CLK_000_D_12_ -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT -Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 9 ( 259)| SIZE_DMA_0_ -Mux11| Mcel 7 9 ( 283)| RN_DSACK1 +Mux02| Mcel 2 2 ( 152)| SM_AMIGA_6_ +Mux03| Mcel 6 5 ( 253)| SM_AMIGA_0_ +Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux05| Mcel 7 9 ( 283)| RN_DSACK1 +Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux07| Mcel 2 14 ( 170)| CLK_000_D_10_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux09| Mcel 0 12 ( 119)| inst_AS_000_DMA +Mux10| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux11| Mcel 7 3 ( 274)| CLK_000_D_1_ Mux12| IOPin 5 2 ( 58)| FC_1_ Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| Mcel 5 5 ( 229)| SM_AMIGA_0_ -Mux15| Mcel 5 13 ( 241)| SM_AMIGA_1_ -Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux14| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| IOPin 4 1 ( 42)| AS_000 Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux18| Mcel 7 10 ( 284)| CLK_000_D_11_ -Mux19| Mcel 7 1 ( 271)| inst_AS_030_D0 -Mux20| Mcel 5 8 ( 233)| SM_AMIGA_5_ -Mux21| Mcel 7 6 ( 278)| RN_BGACK_030 -Mux22| Mcel 6 5 ( 253)| SIZE_DMA_1_ -Mux23| Mcel 7 0 ( 269)| RN_RW_000 -Mux24| Mcel 0 12 ( 119)| inst_AS_000_DMA +Mux18| Mcel 0 8 ( 113)| inst_RESET_OUT +Mux19| Mcel 7 1 ( 271)| RN_RW_000 +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 0 6 ( 110)| inst_AS_030_D0 +Mux23| Mcel 7 0 ( 269)| CLK_000_D_11_ +Mux24| IOPin 5 3 ( 57)| FC_0_ Mux25| IOPin 6 6 ( 71)| RW -Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux26| Mcel 6 14 ( 266)| CLK_000_D_12_ Mux27| IOPin 0 6 ( 97)| A_DECODE_19_ Mux28| Input Pin ( 64)| CLK_030 -Mux29| ... | ... -Mux30| Mcel 6 15 ( 268)| CLK_000_D_10_ -Mux31| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux32| IOPin 3 7 ( 28)| BGACK_000 +Mux29| IOPin 0 0 ( 91)| FPU_SENSE +Mux30| Mcel 5 1 ( 223)| SM_AMIGA_1_ +Mux31| Mcel 6 2 ( 248)| SIZE_DMA_0_ +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 1234f24..6c0a21e 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Fri Aug 19 00:20:46 2016 +Project Fitted on : Fri Aug 19 00:39:40 2016 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 24 Total Output Pins : 19 Total Bidir I/O Pins : 18 - Total Flip-Flops : 89 - Total Product Terms : 251 + Total Flip-Flops : 64 + Total Product Terms : 222 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 55 9 --> 85% -Logic Macrocells 128 116 12 --> 90% +Logic Macrocells 128 91 37 --> 71% Input Registers 64 0 64 --> 0% - Unusable Macrocells .. 0 .. + Unusable Macrocells .. 1 .. -CSM Outputs/Total Block Inputs 264 237 27 --> 89% -Logical Product Terms 640 251 389 --> 39% -Product Term Clusters 128 54 74 --> 42% +CSM Outputs/Total Block Inputs 264 215 49 --> 81% +Logical Product Terms 640 226 414 --> 35% +Product Term Clusters 128 53 75 --> 41%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 28 8 0 16 0 0 42 7 Lo -Block B 26 8 0 16 0 0 46 5 Lo -Block C 28 7 0 16 0 0 25 12 Lo -Block D 31 8 0 16 0 0 28 9 Lo +Block A 23 8 0 12 0 4 39 7 Lo +Block B 25 8 0 12 1 3 44 8 Lo +Block C 24 7 0 12 0 4 21 12 Lo +Block D 25 8 0 12 0 4 25 8 Lo Block E 33 4 0 10 0 6 12 14 Lo -Block F 31 5 0 16 0 0 56 2 Lo -Block G 28 7 0 16 0 0 25 10 Lo -Block H 32 8 0 10 0 6 17 13 Lo +Block F 25 5 0 10 0 6 43 5 Lo +Block G 27 7 0 13 0 3 25 8 Lo +Block H 33 8 0 9 0 7 17 13 Lo --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O -BC----- Low Slow A_1_ + 60 F . I/O ------G- Low Slow A_1_ 96 A . I/O --C-E--H Low Slow A_DECODE_16_ 59 F . I/O --C-E--H Low Slow A_DECODE_17_ 95 A . I/O --C-E--H Low Slow A_DECODE_18_ @@ -298,16 +298,16 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 85 H . I/O ----E--- Low Slow A_DECODE_23_ 28 D . I/O ----E--H Low Slow BGACK_000 21 C . I/O ---D---- Low Slow BG_030 - 30 D . I/O --C----- Low Slow DTACK + 30 D . I/O ------G- Low Slow DTACK 57 F . I/O --C-E--H Low Slow FC_0_ 58 F . I/O --C-E--H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O -B-D---- Low Slow IPL_0_ - 56 F . I/O -B---F-- Low Slow IPL_1_ - 68 G . I/O -B------ Low Slow IPL_2_ - 11 . . Ck/I ---D--G- - Slow CLK_000 + 67 G . I/O -B------ Low Slow IPL_0_ + 56 F . I/O -B------ Low Slow IPL_1_ + 68 G . I/O AB------ Low Slow IPL_2_ + 11 . . Ck/I --C----- - Slow CLK_000 14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE - 36 . . Ded A------- - Slow VPA + 36 . . Ded -----F-- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI 64 . . Ck/I A------H - Slow CLK_030 86 . . Ded ABCD-FGH - Slow RST @@ -328,7 +328,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 33 D 1 COM -------- Low Fast AMIGA_ADDR_ENABLE 48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR - 34 D 3 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH + 34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH 20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Low Slow AVEC 83 H 3 DFF * * -------- Low Slow BGACK_030 @@ -369,14 +369,14 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 5 B 1 COM ----E--- Low Slow AHIGH_30_ 4 B 1 COM ----E--- Low Slow AHIGH_31_ 42 E 1 COM A---E--H Low Slow AS_000 - 82 H 1 COM ----E--H Low Slow AS_030 - 69 G 3 DFF * * AB------ Low Slow A_0_ - 41 E 1 COM --C--FGH Low Slow BERR + 82 H 1 COM A---E--H Low Slow AS_030 + 69 G 3 DFF * * ---D---- Low Slow A_0_ + 41 E 1 COM -BC--FGH Low Slow BERR 31 D 1 COM A-----G- Low Slow LDS_000 - 71 G 2 DFF * * -----F-H Low Slow RW - 80 H 3 DFF * * A---E-G- Low Slow RW_000 - 70 G 1 COM A------- Low Slow SIZE_0_ - 79 H 1 COM A------- Low Slow SIZE_1_ + 71 G 2 DFF * * -B-----H Low Slow RW + 80 H 4 DFF * * A---E-G- Low Slow RW_000 + 70 G 1 COM ---D---- Low Slow SIZE_0_ + 79 H 1 COM ---D---- Low Slow SIZE_1_ 32 D 1 COM A-----G- Low Slow UDS_000 ---------------------------------------------------------------------- @@ -394,94 +394,68 @@ Buried_Signal_List #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- E10 E 2 COM ----E--- Low Slow CIIN_0 - G13 G 1 DFF * * --CD---- Low Slow CLK_000_D_0_ - G15 G 1 DFF * * -------H Low Slow CLK_000_D_10_ - H10 H 1 DFF * * -------H Low Slow CLK_000_D_11_ - H2 H 1 DFF * * -------H Low Slow CLK_000_D_12_ - C6 C 1 DFF * * ---D--G- Low Slow CLK_000_D_1_ - G11 G 1 DFF * * ------G- Low Slow CLK_000_D_2_ - G7 G 1 DFF * * --C----- Low Slow CLK_000_D_3_ + C13 C 1 DFF * * ABCD-FGH Low Slow CLK_000_D_0_ + C14 C 1 DFF * * -------H Low Slow CLK_000_D_10_ + H0 H 1 DFF * * ------GH Low Slow CLK_000_D_11_ + G14 G 1 DFF * * -------H Low Slow CLK_000_D_12_ + H3 H 1 DFF * * ABCDEFGH Low Slow CLK_000_D_1_ + E2 E 1 DFF * * --C-EF-- Low Slow CLK_000_D_2_ + E9 E 1 DFF * * --C----- Low Slow CLK_000_D_3_ C11 C 1 DFF * * ----E--- Low Slow CLK_000_D_4_ - E13 E 1 DFF * * -B------ Low Slow CLK_000_D_5_ - B11 B 1 DFF * * ------G- Low Slow CLK_000_D_6_ - G3 G 1 DFF * * -B------ Low Slow CLK_000_D_7_ - B7 B 1 DFF * * ---D---- Low Slow CLK_000_D_8_ - D11 D 1 DFF * * ------G- Low Slow CLK_000_D_9_ - D2 D 1 DFF * * --C-EF-- Low Slow CLK_000_N_SYNC_0_ - C14 C 1 DFF * * --C----- Low Slow CLK_000_N_SYNC_10_ - C10 C 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_11_ - D13 D 1 DFF * * ---DEF-- Low Slow CLK_000_N_SYNC_12_ - E9 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_1_ - A3 A 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_2_ - F7 F 1 DFF * * A------- Low Slow CLK_000_N_SYNC_3_ - A14 A 1 DFF * * A------- Low Slow CLK_000_N_SYNC_4_ - A6 A 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_5_ - B3 B 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_6_ - G6 G 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_7_ - B14 B 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_8_ - F3 F 1 DFF * * --C----- Low Slow CLK_000_N_SYNC_9_ - D7 D 1 DFF * * A------- Low Slow CLK_000_P_SYNC_0_ - A8 A 1 DFF * * A-CD-F-H Low Slow CLK_000_P_SYNC_10_ - A15 A 1 DFF * * -----F-- Low Slow CLK_000_P_SYNC_1_ - F11 F 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_2_ - C7 C 1 DFF * * A------- Low Slow CLK_000_P_SYNC_3_ - A11 A 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_4_ - G14 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_5_ - G10 G 1 DFF * * ---D---- Low Slow CLK_000_P_SYNC_6_ - D3 D 1 DFF * * A------- Low Slow CLK_000_P_SYNC_7_ - A7 A 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_8_ - C3 C 1 DFF * * A------- Low Slow CLK_000_P_SYNC_9_ - A10 A 2 DFF * * A------- Low Slow CYCLE_DMA_0_ - A2 A 3 DFF * * A------- Low Slow CYCLE_DMA_1_ - D15 D 1 DFF * * -B------ Low Slow IPL_D0_0_ - F15 F 1 DFF * * -B------ Low Slow IPL_D0_1_ - B15 B 1 DFF * * -B------ Low Slow IPL_D0_2_ - F14 F 3 COM -----F-- Low Slow N_226 + E5 E 1 DFF * * ---D---- Low Slow CLK_000_D_5_ + D14 D 1 DFF * * A------- Low Slow CLK_000_D_6_ + A14 A 1 DFF * * ------G- Low Slow CLK_000_D_7_ + G3 G 1 DFF * * A------- Low Slow CLK_000_D_8_ + A10 A 1 DFF * * --C----- Low Slow CLK_000_D_9_ + A13 A 3 DFF * * A------- Low Slow CYCLE_DMA_0_ + A9 A 4 DFF * * A------- Low Slow CYCLE_DMA_1_ + B3 B 1 DFF * * -B------ Low Slow IPL_D0_0_ + B14 B 1 DFF * * -B------ Low Slow IPL_D0_1_ + A3 A 1 DFF * * -B------ Low Slow IPL_D0_2_ G8 G 3 DFF * * ------G- Low - RN_A_0_ --> A_0_ - H6 H 3 DFF * * ABCDE-GH Low - RN_BGACK_030 --> BGACK_030 + H4 H 3 DFF * * ABCDE-GH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF * * ---D---- Low - RN_BG_000 --> BG_000 H9 H 4 DFF * * -------H Low - RN_DSACK1 --> DSACK1 - B8 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ + B5 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ B9 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ B4 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ G0 G 2 DFF * * ------G- Low - RN_RW --> RW - H0 H 3 DFF * * -------H Low - RN_RW_000 --> RW_000 + H1 H 4 DFF * * -------H Low - RN_RW_000 --> RW_000 D0 D 3 TFF * * ---D-F-- Low - RN_VMA --> VMA - D10 D 3 DFF * * ---D---- Low Slow RST_DLY_0_ - D6 D 4 DFF * * ---D---- Low Slow RST_DLY_1_ - D14 D 2 DFF * * ---D---- Low Slow RST_DLY_2_ - G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_ - G5 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_ - F5 F 2 DFF * * ---D-F-H Low Slow SM_AMIGA_0_ - F13 F 3 DFF * * -----F-H Low Slow SM_AMIGA_1_ + F0 F 4 DFF * * A----F-- Low Slow RST_DLY_0_ + F13 F 2 DFF * * A----F-- Low Slow RST_DLY_1_ + F9 F 2 DFF * * A----F-- Low Slow RST_DLY_2_ + G2 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_ + G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_ + G5 G 3 DFF * * -B---FGH Low Slow SM_AMIGA_0_ + F1 F 3 DFF * * -----FGH Low Slow SM_AMIGA_1_ F6 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_ - F2 F 5 TFF * * -----F-- Low Slow SM_AMIGA_3_ - F10 F 3 DFF * * -----F-- Low Slow SM_AMIGA_4_ - F8 F 3 DFF * * -----FGH Low Slow SM_AMIGA_5_ - C9 C 3 DFF * * ABC--F-- Low Slow SM_AMIGA_6_ - F0 F 14 DFF * * --CD-F-H Low Slow SM_AMIGA_i_7_ - B2 B 2 DFF * * -B-D-F-- Low Slow cpu_est_0_ - F12 F 3 DFF * * ---D-FG- Low Slow cpu_est_1_ - F4 F 4 DFF * * ---D-FG- Low Slow cpu_est_2_ - F1 F 3 DFF * * ---D-FG- Low Slow cpu_est_3_ - C2 C 2 DFF * * --CD---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - B10 B 2 DFF * * -BC----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + F10 F 4 DFF * * -----F-- Low Slow SM_AMIGA_3_ + B10 B 3 DFF * * -B---F-- Low Slow SM_AMIGA_4_ + F5 F 3 DFF * * -B---F-- Low Slow SM_AMIGA_5_ + C2 C 3 DFF * * -BCD-F-H Low Slow SM_AMIGA_6_ + F4 F 13 DFF * * -BC----H Low Slow SM_AMIGA_i_7_ + D2 D 3 DFF * * ---D-F-- Low Slow cpu_est_0_ + F8 F 4 DFF * * ---D-FG- Low Slow cpu_est_1_ + D13 D 1 DFF * * ---D-FG- Low Slow cpu_est_2_ + D9 D 4 DFF * * ---D-FG- Low Slow cpu_est_3_ + G6 G 2 DFF * * ---D--G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + G10 G 2 DFF * * --C---G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW A12 A 7 DFF * * A------H Low Slow inst_AS_000_DMA - G2 G 2 DFF * * ----E-G- Low Slow inst_AS_000_INT - C13 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC - H1 H 1 DFF * * --CDEFGH Low Slow inst_AS_030_D0 - H13 H 1 DFF * * -BC---G- Low Slow inst_BGACK_030_INT_D - E5 E 1 DFF * * -B---F-- Low Slow inst_CLK_000_NE_D0 - A13 A 8 DFF * * A------- Low Slow inst_CLK_030_H - E2 E 1 DFF * * ----E--- Low Slow inst_CLK_OUT_PRE_50 + C15 C 2 DFF * * --C-E--- Low Slow inst_AS_000_INT + C6 C 7 DFF * * --CD-F-- Low Slow inst_AS_030_000_SYNC + A6 A 1 DFF * * -BCDE--H Low Slow inst_AS_030_D0 + H13 H 1 DFF * * --C---G- Low Slow inst_BGACK_030_INT_D + A5 A 8 DFF * * A------- Low Slow inst_CLK_030_H + E6 E 1 DFF * * ----E--- Low Slow inst_CLK_OUT_PRE_50 E8 E 1 DFF * * -B----GH Low Slow inst_CLK_OUT_PRE_D - A9 A 9 DFF * * A------- Low Slow inst_DS_000_DMA - F9 F 5 DFF * * ---D-F-- Low Slow inst_DS_000_ENABLE - C15 C 1 DFF * * -----F-- Low Slow inst_DTACK_D0 - A1 A 3 DFF * * A--D---- Low Slow inst_LDS_000_INT - D9 D 2 DFF * * ABCDE-GH Low Slow inst_RESET_OUT - B6 B 2 DFF * * -B-D---- Low Slow inst_UDS_000_INT - A5 A 1 DFF * * ---D-F-- Low Slow inst_VPA_D + A1 A 9 DFF * * A------- Low Slow inst_DS_000_DMA + B6 B 4 DFF * * -B-D---- Low Slow inst_DS_000_ENABLE + G7 G 1 DFF * * -----F-- Low Slow inst_DTACK_D0 + D6 D 3 DFF * * ---D---- Low Slow inst_LDS_000_INT + A8 A 2 DFF * * ABCDE-GH Low Slow inst_RESET_OUT + D10 D 2 DFF * * ---D---- Low Slow inst_UDS_000_INT + F2 F 1 DFF * * ---D-F-- Low Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -496,21 +470,14 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- -A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E} -A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E} - SIZE_1_{ I}:inst_LDS_000_INT{ A} -A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E} -A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + SIZE_1_{ I}:inst_LDS_000_INT{ D} AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E} -A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} -A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E} -A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_2_{ B} + : IPL_D0_2_{ A} FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} - : inst_AS_030_D0{ H} + : inst_AS_030_D0{ A} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} : BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} @@ -519,99 +486,106 @@ A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} SIZE_DMA_0_{ G} : SIZE_DMA_1_{ G} inst_CLK_030_H{ A} nEXP_SPACE{. }: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H} - : DS_030{ A}AMIGA_BUS_DATA_DIR{ E} SIZE_0_{ G} - : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} - : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} - : AHIGH_24_{ C} A_0_{ G} BG_000{ D} - : DSACK1{ H} N_226{ F}inst_AS_030_000_SYNC{ C} - : SM_AMIGA_6_{ C} CIIN_0{ E} - BERR{ F}: DSACK1{ H}inst_AS_000_INT{ G}inst_AS_030_000_SYNC{ C} - : SM_AMIGA_5_{ F} SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} - :inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ C} SM_AMIGA_1_{ F} + : DS_030{ A} SIZE_0_{ G} AHIGH_30_{ B} + : AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C} + : AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C} + :AMIGA_BUS_DATA_DIR{ E} BG_000{ D} DSACK1{ H} + : A_0_{ G}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C} + : SM_AMIGA_i_7_{ F} CIIN_0{ E} + BERR{ F}: DSACK1{ H}inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C} + :inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_0_{ G} + : SM_AMIGA_4_{ B} SM_AMIGA_1_{ F} SM_AMIGA_5_{ F} : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} BG_030{ D}: BG_000{ D} - IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_1_{ F} - IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_0_{ D} + SIZE_0_{ H}:inst_LDS_000_INT{ D} + AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E} BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} - FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E} CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : inst_CLK_030_H{ A} - A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} - CLK_000{. }:AMIGA_BUS_ENABLE_HIGH{ D} CLK_000_D_0_{ G} - FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} - DTACK{ E}: inst_DTACK_D0{ C} - VPA{. }: inst_VPA_D{ A} - RST{. }: IPL_030_2_{ B} RW_000{ H} A_0_{ G} - : IPL_030_1_{ B} IPL_030_0_{ B} BG_000{ D} - : BGACK_030{ H} DSACK1{ H} VMA{ D} - : RW{ G}inst_AS_000_INT{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} - : inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H} - :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} - : CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} - : inst_VPA_D{ A}inst_UDS_000_INT{ B}inst_LDS_000_INT{ A} - : inst_DTACK_D0{ C} inst_RESET_OUT{ D} SM_AMIGA_5_{ F} - : IPL_D0_0_{ D} IPL_D0_1_{ F} IPL_D0_2_{ B} - : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} - : RST_DLY_0_{ D} RST_DLY_1_{ D} RST_DLY_2_{ D} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} SM_AMIGA_6_{ C} inst_CLK_030_H{ A} - : SM_AMIGA_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} - SIZE_0_{ H}:inst_LDS_000_INT{ A} - AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E} - AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E} AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E} + CLK_000{. }: CLK_000_D_0_{ C} AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E} AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E} AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E} AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E} +A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E} + FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} +A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E} +A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E} + DTACK{ E}: inst_DTACK_D0{ G} +A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} +A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} +A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + VPA{. }: inst_VPA_D{ F} +A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + RST{. }: IPL_030_2_{ B} RW_000{ H} BG_000{ D} + : BGACK_030{ H} DSACK1{ H} VMA{ D} + : RW{ G} A_0_{ G} IPL_030_1_{ B} + : IPL_030_0_{ B}inst_AS_000_INT{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} + : inst_AS_030_D0{ A}inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H} + :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} + : inst_VPA_D{ F}inst_UDS_000_INT{ D}inst_LDS_000_INT{ D} + : inst_DTACK_D0{ G} inst_RESET_OUT{ A} IPL_D0_0_{ B} + : IPL_D0_1_{ B} IPL_D0_2_{ A}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} + :inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_0_{ G} + : SM_AMIGA_4_{ B} RST_DLY_0_{ F} RST_DLY_1_{ F} + : RST_DLY_2_{ F} inst_CLK_030_H{ A} SM_AMIGA_1_{ F} + : SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} + IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_1_{ B} + IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_0_{ B} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} RN_IPL_030_2_{ C}: IPL_030_2_{ B} RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A} RN_RW_000{ I}: RW_000{ H} - A_0_{ H}:inst_UDS_000_INT{ B}inst_LDS_000_INT{ A} - RN_A_0_{ H}: A_0_{ G} -RN_IPL_030_1_{ C}: IPL_030_1_{ B} -RN_IPL_030_0_{ C}: IPL_030_0_{ B} RN_BG_000{ E}: BG_000{ D} RN_BGACK_030{ I}: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H} : AS_000{ E} DS_030{ A} UDS_000{ D} - : LDS_000{ D}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} - :AMIGA_BUS_ENABLE_HIGH{ D} SIZE_0_{ G} AHIGH_30_{ B} + : LDS_000{ D} SIZE_0_{ G} AHIGH_30_{ B} : AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C} : AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C} - : RW_000{ H} A_0_{ G} BGACK_030{ H} - : RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AS_030_000_SYNC{ C} + :AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} + : RW_000{ H} BGACK_030{ H} RW{ G} + : A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AS_030_000_SYNC{ C} :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} - : SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} inst_CLK_030_H{ A} + : SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} inst_CLK_030_H{ A} RN_DSACK1{ I}: DSACK1{ H} RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} - RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ F} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ B} RN_RW{ H}: RW{ G} - N_226{ G}: SM_AMIGA_i_7_{ F} - cpu_est_2_{ G}: E{ G} VMA{ D} cpu_est_2_{ F} - : cpu_est_3_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} - cpu_est_3_{ G}: E{ G} VMA{ D} cpu_est_3_{ F} + A_0_{ H}:inst_UDS_000_INT{ D}inst_LDS_000_INT{ D} + RN_A_0_{ H}: A_0_{ G} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} + cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_3_{ D} : cpu_est_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} - cpu_est_0_{ C}: VMA{ D} cpu_est_2_{ F} cpu_est_3_{ F} - : cpu_est_0_{ B} cpu_est_1_{ F} SM_AMIGA_3_{ F} + cpu_est_0_{ E}: VMA{ D} cpu_est_3_{ D} cpu_est_0_{ D} + : cpu_est_1_{ F} cpu_est_2_{ D} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} - cpu_est_1_{ G}: E{ G} VMA{ D} cpu_est_2_{ F} - : cpu_est_3_{ F} cpu_est_1_{ F} SM_AMIGA_3_{ F} + cpu_est_1_{ G}: E{ G} VMA{ D} cpu_est_3_{ D} + : cpu_est_1_{ F} cpu_est_2_{ D} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -inst_AS_000_INT{ H}: AS_000{ E}inst_AS_000_INT{ G} -inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} -inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D} DSACK1{ H} - :inst_AS_000_INT{ G}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ F} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_3_{ D} + : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ H}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} +inst_AS_030_D0{ B}: CIIN{ E} BG_000{ D} DSACK1{ H} + :inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ B} : CIIN_0{ E} -inst_AS_030_000_SYNC{ D}: N_226{ F}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C} -inst_BGACK_030_INT_D{ I}: A_0_{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} +inst_AS_030_000_SYNC{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C} + : SM_AMIGA_i_7_{ F} +inst_BGACK_030_INT_D{ I}: RW{ G} A_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} :inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : inst_CLK_030_H{ A} inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A} @@ -621,97 +595,74 @@ CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ A} : inst_CLK_030_H{ A} SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G} SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G} - inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} -inst_UDS_000_INT{ C}: UDS_000{ D}inst_UDS_000_INT{ B} -inst_LDS_000_INT{ B}: LDS_000{ D}inst_LDS_000_INT{ A} +inst_UDS_000_INT{ E}: UDS_000{ D}inst_UDS_000_INT{ D} +inst_LDS_000_INT{ E}: LDS_000{ D}inst_LDS_000_INT{ D} inst_CLK_OUT_PRE_D{ F}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H} -CLK_000_D_10_{ H}: DSACK1{ H} CLK_000_D_11_{ H} -CLK_000_D_11_{ I}: DSACK1{ H} CLK_000_D_12_{ H} -inst_DTACK_D0{ D}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -inst_RESET_OUT{ E}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} +CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} VMA{ D} + : cpu_est_3_{ D} cpu_est_0_{ D} cpu_est_1_{ F} + : cpu_est_2_{ D}inst_AS_000_INT{ C} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} inst_RESET_OUT{ A} CLK_000_D_2_{ E} + :inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} SM_AMIGA_0_{ G} + : SM_AMIGA_4_{ B} RST_DLY_0_{ F} RST_DLY_1_{ F} + : RST_DLY_2_{ F} SM_AMIGA_1_{ F} SM_AMIGA_5_{ F} + : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} +CLK_000_D_10_{ D}: DSACK1{ H} CLK_000_D_11_{ H} +CLK_000_D_11_{ I}: DSACK1{ H} CLK_000_D_12_{ G} +inst_DTACK_D0{ H}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} +inst_RESET_OUT{ B}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} : DS_030{ A} UDS_000{ D} LDS_000{ D} - : RESET{ B} AHIGH_30_{ B} AHIGH_29_{ B} - : AHIGH_28_{ C} AHIGH_27_{ C} AHIGH_26_{ C} - : AHIGH_25_{ C} AHIGH_24_{ C} RW_000{ H} - : A_0_{ G} RW{ G} inst_RESET_OUT{ D} + : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} + : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} + : AHIGH_24_{ C} RESET{ B} RW_000{ H} + : RW{ G} A_0_{ G} inst_RESET_OUT{ A} +CLK_000_D_0_{ D}: RW_000{ H} BG_000{ D} BGACK_030{ H} + : VMA{ D} cpu_est_3_{ D} cpu_est_0_{ D} + : cpu_est_1_{ F} cpu_est_2_{ D}inst_AS_000_INT{ C} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} CLK_000_D_1_{ H} + : inst_RESET_OUT{ A}inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} + : SM_AMIGA_0_{ G} SM_AMIGA_4_{ B} RST_DLY_0_{ F} + : RST_DLY_1_{ F} RST_DLY_2_{ F} SM_AMIGA_1_{ F} + : SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_D{ E}inst_CLK_OUT_PRE_50{ E} -CLK_000_D_1_{ D}: CLK_000_D_2_{ G}CLK_000_N_SYNC_0_{ D}CLK_000_P_SYNC_0_{ D} -CLK_000_D_0_{ H}: BG_000{ D} CLK_000_D_1_{ C}CLK_000_N_SYNC_0_{ D} - :CLK_000_P_SYNC_0_{ D} -CLK_000_P_SYNC_10_{ B}: RW_000{ H} BGACK_030{ H} VMA{ D} - : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SM_AMIGA_5_{ F} - : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} - : SM_AMIGA_6_{ C} SM_AMIGA_1_{ F} SM_AMIGA_3_{ F} - : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -SM_AMIGA_5_{ G}: RW_000{ H} N_226{ F}inst_AS_000_INT{ G} - : SM_AMIGA_5_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} - : SM_AMIGA_i_7_{ F} - IPL_D0_0_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_2_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} -CLK_000_D_2_{ H}: CLK_000_D_3_{ G} -CLK_000_D_3_{ H}: CLK_000_D_4_{ C} + IPL_D0_0_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +CLK_000_D_2_{ F}: CLK_000_D_3_{ E} SM_AMIGA_6_{ C} SM_AMIGA_i_7_{ F} +CLK_000_D_3_{ F}: CLK_000_D_4_{ C} CLK_000_D_4_{ D}: CLK_000_D_5_{ E} -CLK_000_D_5_{ F}: CLK_000_D_6_{ B} -CLK_000_D_6_{ C}: CLK_000_D_7_{ G} -CLK_000_D_7_{ H}: CLK_000_D_8_{ B} -CLK_000_D_8_{ C}: CLK_000_D_9_{ D} -CLK_000_D_9_{ E}: CLK_000_D_10_{ G} -CLK_000_D_12_{ I}: DSACK1{ H} -SM_AMIGA_0_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H} N_226{ F} - : SM_AMIGA_0_{ F}inst_DS_000_ENABLE{ F} SM_AMIGA_i_7_{ F} -CLK_000_N_SYNC_0_{ E}: N_226{ F}CLK_000_N_SYNC_1_{ E} SM_AMIGA_6_{ C} -SM_AMIGA_4_{ G}: N_226{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} - : SM_AMIGA_3_{ F} SM_AMIGA_i_7_{ F} -inst_DS_000_ENABLE{ G}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ F} -CLK_000_N_SYNC_12_{ E}: VMA{ D} inst_RESET_OUT{ D} SM_AMIGA_5_{ F} - : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} RST_DLY_0_{ D} - : RST_DLY_1_{ D} RST_DLY_2_{ D}inst_CLK_000_NE_D0{ E} - : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} - RST_DLY_0_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D} - : RST_DLY_2_{ D} - RST_DLY_1_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D} - : RST_DLY_2_{ D} - RST_DLY_2_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D} - : RST_DLY_2_{ D} -CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ A} -CLK_000_P_SYNC_1_{ B}:CLK_000_P_SYNC_2_{ F} -CLK_000_P_SYNC_2_{ G}:CLK_000_P_SYNC_3_{ C} -CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ A} -CLK_000_P_SYNC_4_{ B}:CLK_000_P_SYNC_5_{ G} -CLK_000_P_SYNC_5_{ H}:CLK_000_P_SYNC_6_{ G} -CLK_000_P_SYNC_6_{ H}:CLK_000_P_SYNC_7_{ D} -CLK_000_P_SYNC_7_{ E}:CLK_000_P_SYNC_8_{ A} -CLK_000_P_SYNC_8_{ B}:CLK_000_P_SYNC_9_{ C} -CLK_000_P_SYNC_9_{ D}:CLK_000_P_SYNC_10_{ A} -CLK_000_N_SYNC_1_{ F}:CLK_000_N_SYNC_2_{ A} -CLK_000_N_SYNC_2_{ B}:CLK_000_N_SYNC_3_{ F} -CLK_000_N_SYNC_3_{ G}:CLK_000_N_SYNC_4_{ A} -CLK_000_N_SYNC_4_{ B}:CLK_000_N_SYNC_5_{ A} -CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ B} -CLK_000_N_SYNC_6_{ C}:CLK_000_N_SYNC_7_{ G} -CLK_000_N_SYNC_7_{ H}:CLK_000_N_SYNC_8_{ B} -CLK_000_N_SYNC_8_{ C}:CLK_000_N_SYNC_9_{ F} -CLK_000_N_SYNC_9_{ G}:CLK_000_N_SYNC_10_{ C} -CLK_000_N_SYNC_10_{ D}:CLK_000_N_SYNC_11_{ C} -CLK_000_N_SYNC_11_{ D}:CLK_000_N_SYNC_12_{ D} -inst_CLK_000_NE_D0{ F}: cpu_est_2_{ F} cpu_est_3_{ F} cpu_est_0_{ B} - : cpu_est_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +CLK_000_D_5_{ F}: CLK_000_D_6_{ D} +CLK_000_D_6_{ E}: CLK_000_D_7_{ A} +CLK_000_D_7_{ B}: CLK_000_D_8_{ G} +CLK_000_D_8_{ H}: CLK_000_D_9_{ A} +CLK_000_D_9_{ B}: CLK_000_D_10_{ C} +CLK_000_D_12_{ H}: DSACK1{ H} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ H}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} +inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B} +SM_AMIGA_6_{ D}: RW_000{ H}inst_AS_000_INT{ C}inst_UDS_000_INT{ D} + :inst_LDS_000_INT{ D}inst_DS_000_ENABLE{ B} SM_AMIGA_6_{ C} + : SM_AMIGA_5_{ F} SM_AMIGA_i_7_{ F} +SM_AMIGA_0_{ H}: RW_000{ H}inst_DS_000_ENABLE{ B} SM_AMIGA_0_{ G} : SM_AMIGA_i_7_{ F} -inst_AMIGA_BUS_ENABLE_DMA_HIGH{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} -SM_AMIGA_6_{ D}: N_226{ F}inst_UDS_000_INT{ B}inst_LDS_000_INT{ A} - : SM_AMIGA_5_{ F}inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ C} +SM_AMIGA_4_{ C}:inst_DS_000_ENABLE{ B} SM_AMIGA_4_{ B} SM_AMIGA_3_{ F} : SM_AMIGA_i_7_{ F} + RST_DLY_0_{ G}: inst_RESET_OUT{ A} RST_DLY_0_{ F} RST_DLY_1_{ F} + : RST_DLY_2_{ F} + RST_DLY_1_{ G}: inst_RESET_OUT{ A} RST_DLY_0_{ F} RST_DLY_1_{ F} + : RST_DLY_2_{ F} + RST_DLY_2_{ G}: inst_RESET_OUT{ A} RST_DLY_0_{ F} RST_DLY_1_{ F} + : RST_DLY_2_{ F} inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A} -SM_AMIGA_1_{ G}: DSACK1{ H} N_226{ F} SM_AMIGA_0_{ F} - : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} -SM_AMIGA_3_{ G}: N_226{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +SM_AMIGA_1_{ G}: DSACK1{ H} SM_AMIGA_0_{ G} SM_AMIGA_1_{ F} : SM_AMIGA_i_7_{ F} -SM_AMIGA_2_{ G}: N_226{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} +SM_AMIGA_5_{ G}:inst_DS_000_ENABLE{ B} SM_AMIGA_4_{ B} SM_AMIGA_5_{ F} : SM_AMIGA_i_7_{ F} -SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H}inst_AS_030_000_SYNC{ C} - :inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ C} +SM_AMIGA_3_{ G}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} +SM_AMIGA_2_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} +SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ B} + : SM_AMIGA_6_{ C} CIIN_0{ F}: CIIN{ E} ----------------------------------------------------------------------------- @@ -730,20 +681,16 @@ Equations : +-----+-----+-----+-----+------------------------ | | | | | DS_030 | | | | | AVEC -| * | S | BS | BR | CLK_000_P_SYNC_10_ +| * | S | BS | BR | inst_RESET_OUT +| * | S | BS | BR | inst_AS_030_D0 | * | S | BS | BR | inst_AS_000_DMA -| * | S | BS | BR | inst_LDS_000_INT -| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | inst_DS_000_DMA | * | S | BS | BR | inst_CLK_030_H | * | S | BS | BR | CYCLE_DMA_1_ | * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | CLK_000_N_SYNC_5_ -| * | S | BS | BR | CLK_000_N_SYNC_4_ -| * | S | BS | BR | CLK_000_N_SYNC_2_ -| * | S | BS | BR | CLK_000_P_SYNC_8_ -| * | S | BS | BR | CLK_000_P_SYNC_4_ -| * | S | BS | BR | CLK_000_P_SYNC_1_ +| * | S | BS | BR | CLK_000_D_9_ +| * | S | BS | BR | CLK_000_D_7_ +| * | S | BS | BR | IPL_D0_2_ | | | | | A_DECODE_19_ | | | | | A_DECODE_16_ | | | | | A_DECODE_18_ @@ -767,17 +714,13 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | S | BS | BR | CLK_EXP | | | | | RESET -| * | S | BS | BR | cpu_est_0_ -| * | S | BS | BR | inst_UDS_000_INT -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW +| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | SM_AMIGA_4_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ -| * | S | BS | BR | CLK_000_N_SYNC_8_ -| * | S | BS | BR | CLK_000_N_SYNC_6_ -| * | S | BS | BR | CLK_000_D_8_ -| * | S | BS | BR | CLK_000_D_6_ -| * | S | BS | BR | IPL_D0_2_ +| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | IPL_D0_0_ Block C @@ -793,16 +736,12 @@ Equations : | | | | | AHIGH_27_ | | | | | AHIGH_28_ | | | | | AMIGA_BUS_ENABLE_LOW +| * | S | BS | BR | CLK_000_D_0_ | * | S | BS | BR | SM_AMIGA_6_ | * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH -| * | S | BS | BR | CLK_000_D_1_ -| * | S | BS | BR | CLK_000_N_SYNC_11_ -| * | S | BS | BR | CLK_000_N_SYNC_10_ -| * | S | BS | BR | CLK_000_P_SYNC_9_ -| * | S | BS | BR | CLK_000_P_SYNC_3_ +| * | S | BS | BR | inst_AS_000_INT | * | S | BS | BR | CLK_000_D_4_ -| * | S | BS | BR | inst_DTACK_D0 +| * | S | BS | BR | CLK_000_D_10_ | | | | | BG_030 @@ -819,18 +758,14 @@ Equations : | | | | | AMIGA_BUS_ENABLE_HIGH | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE -| * | S | BS | BR | inst_RESET_OUT -| * | S | BS | BR | CLK_000_N_SYNC_12_ -| * | S | BS | BR | CLK_000_N_SYNC_0_ +| * | S | BS | BR | cpu_est_3_ +| * | S | BS | BR | cpu_est_2_ | * | S | BS | BR | RN_VMA -| * | S | BS | BR | RST_DLY_1_ -| * | S | BS | BR | RST_DLY_0_ +| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | inst_LDS_000_INT | * | S | BS | BR | RN_BG_000 -| * | S | BS | BR | RST_DLY_2_ -| * | S | BS | BR | CLK_000_P_SYNC_7_ -| * | S | BS | BR | CLK_000_P_SYNC_0_ -| * | S | BS | BR | CLK_000_D_9_ -| * | S | BS | BR | IPL_D0_0_ +| * | S | BS | BR | inst_UDS_000_INT +| * | S | BS | BR | CLK_000_D_6_ | | | | | BGACK_000 | | | | | DTACK @@ -846,11 +781,11 @@ Equations : | | | | | AS_000 | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN +| * | S | BS | BR | CLK_000_D_2_ | * | S | BS | BR | inst_CLK_OUT_PRE_D -| * | S | BS | BR | inst_CLK_000_NE_D0 | | | | | CIIN_0 -| * | S | BS | BR | CLK_000_N_SYNC_1_ | * | S | BS | BR | CLK_000_D_5_ +| * | S | BS | BR | CLK_000_D_3_ | * | S | BS | BR | inst_CLK_OUT_PRE_50 @@ -862,21 +797,15 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | SM_AMIGA_i_7_ -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | SM_AMIGA_5_ | * | S | BS | BR | cpu_est_1_ -| * | S | BS | BR | cpu_est_3_ -| * | S | BS | BR | SM_AMIGA_0_ -| * | S | BS | BR | inst_DS_000_ENABLE | * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | RST_DLY_0_ +| * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BR | RST_DLY_2_ +| * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | SM_AMIGA_2_ -| * | S | BS | BR | SM_AMIGA_4_ -| | | | | N_226 -| * | S | BS | BR | CLK_000_N_SYNC_9_ -| * | S | BS | BR | CLK_000_N_SYNC_3_ -| * | S | BS | BR | CLK_000_P_SYNC_2_ -| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | SM_AMIGA_3_ | | | | | A_DECODE_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -891,26 +820,23 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | A_0_ | * | S | BS | BR | RW +| * | S | BS | BR | A_0_ | | | | | SIZE_0_ | | | | | E | * | S | BS | BR | CLK_DIV_OUT +| * | S | BS | BR | SM_AMIGA_0_ | * | S | BS | BR | SIZE_DMA_1_ | * | S | BS | BR | SIZE_DMA_0_ -| * | S | BS | BR | inst_AS_000_INT -| * | S | BS | BR | CLK_000_D_0_ +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | * | S | BS | BR | RN_A_0_ | * | S | BS | BR | RN_RW -| * | S | BS | BR | CLK_000_N_SYNC_7_ -| * | S | BS | BR | CLK_000_P_SYNC_6_ -| * | S | BS | BR | CLK_000_P_SYNC_5_ -| * | S | BS | BR | CLK_000_D_7_ -| * | S | BS | BR | CLK_000_D_3_ -| * | S | BS | BR | CLK_000_D_2_ -| * | S | BS | BR | CLK_000_D_10_ -| | | | | IPL_0_ +| * | S | BS | BR | CLK_000_D_12_ +| * | S | BS | BR | CLK_000_D_8_ +| * | S | BS | BR | inst_DTACK_D0 | | | | | IPL_2_ +| | | | | IPL_0_ Block H @@ -926,13 +852,12 @@ Equations : | * | S | BS | BR | DSACK1 | * | S | BS | BR | BGACK_030 | | | | | FPU_CS +| * | S | BS | BR | CLK_000_D_1_ | * | S | BS | BR | RN_BGACK_030 -| * | S | BS | BR | inst_AS_030_D0 +| * | S | BS | BR | CLK_000_D_11_ | * | S | BS | BR | inst_BGACK_030_INT_D | * | S | BS | BR | RN_DSACK1 | * | S | BS | BR | RN_RW_000 -| * | S | BS | BR | CLK_000_D_12_ -| * | S | BS | BR | CLK_000_D_11_ | | | | | A_DECODE_23_ | | | | | A_DECODE_22_ @@ -951,23 +876,23 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 A_0_ pin 69 mx A17 SIZE_0_ pin 70 -mx A1 ... ... mx A18CLK_000_P_SYNC_10_ mcell A8 -mx A2CLK_000_N_SYNC_1_ mcell E9 mx A19 inst_DS_000_DMA mcell A9 -mx A3CLK_000_N_SYNC_4_ mcell A14 mx A20 SIZE_1_ pin 79 -mx A4 CLK_030 pin 64 mx A21inst_LDS_000_INT mcell A1 -mx A5 nEXP_SPACE pin 14 mx A22 CYCLE_DMA_1_ mcell A2 -mx A6CLK_000_P_SYNC_3_ mcell C7 mx A23 SM_AMIGA_6_ mcell C9 -mx A7 inst_RESET_OUT mcell D9 mx A24 RST pin 86 -mx A8 UDS_000 pin 32 mx A25 inst_CLK_030_H mcell A13 -mx A9CLK_000_P_SYNC_7_ mcell D3 mx A26 AS_000 pin 42 -mx A10 VPA pin 36 mx A27 LDS_000 pin 31 -mx A11 ... ... mx A28 RW_000 pin 80 -mx A12CLK_000_P_SYNC_9_ mcell C3 mx A29 ... ... -mx A13CLK_000_P_SYNC_0_ mcell D7 mx A30 RN_BGACK_030 mcell H6 -mx A14 CYCLE_DMA_0_ mcell A10 mx A31 ... ... +mx A0 RST pin 86 mx A17 CLK_000_D_6_ mcell D14 +mx A1 RST_DLY_2_ mcell F9 mx A18 inst_CLK_030_H mcell A5 +mx A2 CYCLE_DMA_1_ mcell A9 mx A19 AS_030 pin 82 +mx A3 inst_RESET_OUT mcell A8 mx A20 RN_BGACK_030 mcell H4 +mx A4 CLK_030 pin 64 mx A21 RW_000 pin 80 +mx A5 nEXP_SPACE pin 14 mx A22 IPL_2_ pin 68 +mx A6 RST_DLY_1_ mcell F13 mx A23 ... ... +mx A7 ... ... mx A24 CLK_000_D_8_ mcell G3 +mx A8 UDS_000 pin 32 mx A25 CYCLE_DMA_0_ mcell A13 +mx A9 inst_DS_000_DMA mcell A1 mx A26 ... ... +mx A10 CLK_000_D_1_ mcell H3 mx A27 LDS_000 pin 31 +mx A11 CLK_000_D_0_ mcell C13 mx A28 ... ... +mx A12 ... ... mx A29 ... ... +mx A13 ... ... mx A30 ... ... +mx A14 ... ... mx A31 RST_DLY_0_ mcell F0 mx A15 inst_AS_000_DMA mcell A12 mx A32 ... ... -mx A16CLK_000_N_SYNC_3_ mcell F7 +mx A16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -975,23 +900,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 IPL_0_ pin 67 mx B17 RN_IPL_030_0_ mcell B8 -mx B1 ... ... mx B18 A_0_ pin 69 -mx B2 IPL_D0_0_ mcell D15 mx B19 IPL_D0_1_ mcell F15 -mx B3 SM_AMIGA_6_ mcell C9 mx B20 ... ... +mx B0 RN_BGACK_030 mcell H4 mx B17 ... ... +mx B1 BERR pin 41 mx B18 inst_RESET_OUT mcell A8 +mx B2inst_DS_000_ENABLE mcell B6 mx B19 ... ... +mx B3 IPL_1_ pin 56 mx B20 IPL_D0_1_ mcell B14 mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5CLK_000_N_SYNC_7_ mcell G6 mx B22CLK_000_N_SYNC_5_ mcell A6 -mx B6 RN_IPL_030_1_ mcell B9 mx B23 A_1_ pin 60 -mx B7inst_BGACK_030_INT_D mcell H13 mx B24 CLK_000_D_7_ mcell G3 -mx B8 IPL_D0_2_ mcell B15 mx B25 inst_RESET_OUT mcell D9 -mx B9 ... ... mx B26 ... ... -mx B10 cpu_est_0_ mcell B2 mx B27 RN_IPL_030_2_ mcell B4 -mx B11inst_UDS_000_INT mcell B6 mx B28 ... ... -mx B12inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B10 mx B29 ... ... -mx B13 CLK_000_D_5_ mcell E13 mx B30 RN_BGACK_030 mcell H6 -mx B14inst_CLK_000_NE_D0 mcell E5 mx B31 IPL_1_ pin 56 -mx B15 nEXP_SPACE pin 14 mx B32 ... ... -mx B16inst_CLK_OUT_PRE_D mcell E8 +mx B5 nEXP_SPACE pin 14 mx B22 SM_AMIGA_0_ mcell G5 +mx B6 RN_IPL_030_1_ mcell B9 mx B23 ... ... +mx B7 ... ... mx B24 ... ... +mx B8 RW pin 71 mx B25 IPL_D0_2_ mcell A3 +mx B9 SM_AMIGA_5_ mcell F5 mx B26 ... ... +mx B10 CLK_000_D_1_ mcell H3 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 CLK_000_D_0_ mcell C13 mx B28 RN_IPL_030_0_ mcell B5 +mx B12 SM_AMIGA_4_ mcell B10 mx B29 ... ... +mx B13 IPL_D0_0_ mcell B3 mx B30inst_CLK_OUT_PRE_D mcell E8 +mx B14 SM_AMIGA_i_7_ mcell F4 mx B31 ... ... +mx B15 inst_AS_030_D0 mcell A6 mx B32 SM_AMIGA_6_ mcell C2 +mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -999,23 +924,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 RST pin 86 mx C17CLK_000_N_SYNC_9_ mcell F3 -mx C1 BERR pin 41 mx C18CLK_000_P_SYNC_10_ mcell A8 -mx C2inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B10 mx C19inst_BGACK_030_INT_D mcell H13 -mx C3 A_1_ pin 60 mx C20CLK_000_P_SYNC_2_ mcell F11 -mx C4 A_DECODE_18_ pin 95 mx C21 RN_BGACK_030 mcell H6 -mx C5 SM_AMIGA_i_7_ mcell F0 mx C22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C2 +mx C0 RST pin 86 mx C17 BERR pin 41 +mx C1 FC_1_ pin 58 mx C18 inst_RESET_OUT mcell A8 +mx C2 CLK_000_D_3_ mcell E9 mx C19 ... ... +mx C3 CLK_000_D_2_ mcell E2 mx C20 RN_BGACK_030 mcell H4 +mx C4 A_DECODE_18_ pin 95 mx C21 ... ... +mx C5 nEXP_SPACE pin 14 mx C22inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G10 mx C6 FC_0_ pin 57 mx C23 ... ... -mx C7 inst_RESET_OUT mcell D9 mx C24 ... ... -mx C8 A_DECODE_17_ pin 59 mx C25 CLK_000_D_0_ mcell G13 -mx C9 DTACK pin 30 mx C26 CLK_000_D_3_ mcell G7 -mx C10 inst_AS_030_D0 mcell H1 mx C27 A_DECODE_19_ pin 97 -mx C11 A_DECODE_16_ pin 96 mx C28CLK_000_P_SYNC_8_ mcell A7 -mx C12 FC_1_ pin 58 mx C29 ... ... -mx C13 SM_AMIGA_6_ mcell C9 mx C30inst_AS_030_000_SYNC mcell C13 -mx C14 ... ... mx C31CLK_000_N_SYNC_10_ mcell C14 -mx C15 nEXP_SPACE pin 14 mx C32 ... ... -mx C16CLK_000_N_SYNC_0_ mcell D2 +mx C7inst_BGACK_030_INT_D mcell H13 mx C24 ... ... +mx C8 CLK_000_D_9_ mcell A10 mx C25 ... ... +mx C9inst_AS_030_000_SYNC mcell C6 mx C26 ... ... +mx C10 CLK_000_D_1_ mcell H3 mx C27 ... ... +mx C11 A_DECODE_16_ pin 96 mx C28 ... ... +mx C12 A_DECODE_19_ pin 97 mx C29 SM_AMIGA_i_7_ mcell F4 +mx C13 A_DECODE_17_ pin 59 mx C30 CLK_000_D_0_ mcell C13 +mx C14 CLK_000 pin 11 mx C31 ... ... +mx C15 inst_AS_030_D0 mcell A6 mx C32 SM_AMIGA_6_ mcell C2 +mx C16 inst_AS_000_INT mcell C15 ---------------------------------------------------------------------------- @@ -1023,23 +948,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RST pin 86 mx D17 RN_BG_000 mcell D1 -mx D1inst_DS_000_ENABLE mcell F9 mx D18 CLK_000_D_1_ mcell C6 -mx D2 inst_VPA_D mcell A5 mx D19 inst_AS_030_D0 mcell H1 -mx D3 CLK_000 pin 11 mx D20 RST_DLY_0_ mcell D10 -mx D4 RST_DLY_1_ mcell D6 mx D21 nEXP_SPACE pin 14 -mx D5 SM_AMIGA_i_7_ mcell F0 mx D22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C2 -mx D6 ... ... mx D23 BG_030 pin 21 -mx D7 RN_BGACK_030 mcell H6 mx D24 RST_DLY_2_ mcell D14 -mx D8CLK_000_N_SYNC_11_ mcell C10 mx D25 CLK_000_D_0_ mcell G13 -mx D9inst_LDS_000_INT mcell A1 mx D26 RN_VMA mcell D0 -mx D10 cpu_est_0_ mcell B2 mx D27 SM_AMIGA_0_ mcell F5 -mx D11inst_UDS_000_INT mcell B6 mx D28CLK_000_P_SYNC_6_ mcell G10 -mx D12 inst_RESET_OUT mcell D9 mx D29CLK_000_N_SYNC_12_ mcell D13 -mx D13 ... ... mx D30CLK_000_P_SYNC_10_ mcell A8 -mx D14 cpu_est_2_ mcell F4 mx D31 cpu_est_1_ mcell F12 -mx D15 cpu_est_3_ mcell F1 mx D32 CLK_000_D_8_ mcell B7 -mx D16 IPL_0_ pin 67 +mx D0 A_0_ pin 69 mx D17 SIZE_0_ pin 70 +mx D1 RN_VMA mcell D0 mx D18 inst_RESET_OUT mcell A8 +mx D2inst_UDS_000_INT mcell D10 mx D19 ... ... +mx D3 cpu_est_0_ mcell D2 mx D20 RN_BGACK_030 mcell H4 +mx D4 BG_030 pin 21 mx D21 cpu_est_2_ mcell D13 +mx D5 nEXP_SPACE pin 14 mx D22 SM_AMIGA_6_ mcell C2 +mx D6 SIZE_1_ pin 79 mx D23inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G6 +mx D7 cpu_est_3_ mcell D9 mx D24 RST pin 86 +mx D8 ... ... mx D25 ... ... +mx D9inst_AS_030_000_SYNC mcell C6 mx D26 ... ... +mx D10 CLK_000_D_1_ mcell H3 mx D27 RN_BG_000 mcell D1 +mx D11inst_DS_000_ENABLE mcell B6 mx D28 inst_VPA_D mcell F2 +mx D12 ... ... mx D29 ... ... +mx D13 ... ... mx D30 CLK_000_D_0_ mcell C13 +mx D14 CLK_000_D_5_ mcell E5 mx D31 ... ... +mx D15 inst_AS_030_D0 mcell A6 mx D32 cpu_est_1_ mcell F8 +mx D16inst_LDS_000_INT mcell D6 ---------------------------------------------------------------------------- @@ -1047,23 +972,23 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 CLK_000_D_4_ mcell C11 mx E17 A_DECODE_18_ pin 95 +mx E0inst_CLK_OUT_PRE_50 mcell E6 mx E17 A_DECODE_20_ pin 93 mx E1 FC_1_ pin 58 mx E18 A_DECODE_23_ pin 85 -mx E2 AS_000 pin 42 mx E19 AS_030 pin 82 -mx E3 A_DECODE_20_ pin 93 mx E20 A_DECODE_22_ pin 84 -mx E4 AHIGH_29_ pin 6 mx E21 RW_000 pin 80 -mx E5 AHIGH_24_ pin 19 mx E22 AHIGH_25_ pin 18 -mx E6 A_DECODE_19_ pin 97 mx E23 inst_AS_000_INT mcell G2 -mx E7 inst_RESET_OUT mcell D9 mx E24 FC_0_ pin 57 -mx E8 FPU_SENSE pin 91 mx E25 AHIGH_31_ pin 4 -mx E9 AHIGH_26_ pin 17 mx E26 A_DECODE_16_ pin 96 -mx E10 inst_AS_030_D0 mcell H1 mx E27inst_CLK_OUT_PRE_50 mcell E2 -mx E11 AHIGH_27_ pin 16 mx E28 AHIGH_30_ pin 5 -mx E12 CIIN_0 mcell E10 mx E29CLK_000_N_SYNC_12_ mcell D13 -mx E13 A_DECODE_17_ pin 59 mx E30 RN_BGACK_030 mcell H6 -mx E14 AHIGH_28_ pin 15 mx E31 A_DECODE_21_ pin 94 -mx E15 nEXP_SPACE pin 14 mx E32 BGACK_000 pin 28 -mx E16CLK_000_N_SYNC_0_ mcell D2 +mx E2 AS_000 pin 42 mx E19 AHIGH_30_ pin 5 +mx E3 AHIGH_27_ pin 16 mx E20 A_DECODE_22_ pin 84 +mx E4 FPU_SENSE pin 91 mx E21 nEXP_SPACE pin 14 +mx E5 A_DECODE_21_ pin 94 mx E22 AHIGH_25_ pin 18 +mx E6 FC_0_ pin 57 mx E23 RN_BGACK_030 mcell H4 +mx E7 AHIGH_28_ pin 15 mx E24 CIIN_0 mcell E10 +mx E8 A_DECODE_17_ pin 59 mx E25 AHIGH_31_ pin 4 +mx E9 AS_030 pin 82 mx E26 AHIGH_26_ pin 17 +mx E10 CLK_000_D_1_ mcell H3 mx E27 CLK_000_D_2_ mcell E2 +mx E11 A_DECODE_16_ pin 96 mx E28 RW_000 pin 80 +mx E12 A_DECODE_19_ pin 97 mx E29 CLK_000_D_4_ mcell C11 +mx E13 AHIGH_29_ pin 6 mx E30 inst_RESET_OUT mcell A8 +mx E14 AHIGH_24_ pin 19 mx E31 A_DECODE_18_ pin 95 +mx E15 inst_AS_030_D0 mcell A6 mx E32 BGACK_000 pin 28 +mx E16 inst_AS_000_INT mcell C15 ---------------------------------------------------------------------------- @@ -1071,23 +996,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0inst_AS_030_000_SYNC mcell C13 mx F17 cpu_est_1_ mcell F12 -mx F1 BERR pin 41 mx F18 cpu_est_0_ mcell B2 -mx F2 SM_AMIGA_5_ mcell F8 mx F19 SM_AMIGA_4_ mcell F10 -mx F3CLK_000_P_SYNC_10_ mcell A8 mx F20CLK_000_N_SYNC_8_ mcell B14 -mx F4 ... ... mx F21 RST pin 86 -mx F5 SM_AMIGA_i_7_ mcell F0 mx F22 inst_DTACK_D0 mcell C15 -mx F6 SM_AMIGA_1_ mcell F13 mx F23 SM_AMIGA_6_ mcell C9 -mx F7 ... ... mx F24 N_226 mcell F14 -mx F8 RW pin 71 mx F25CLK_000_N_SYNC_2_ mcell A3 -mx F9 SM_AMIGA_3_ mcell F2 mx F26 RN_VMA mcell D0 -mx F10 cpu_est_2_ mcell F4 mx F27 SM_AMIGA_0_ mcell F5 -mx F11 SM_AMIGA_2_ mcell F6 mx F28 inst_VPA_D mcell A5 -mx F12 inst_AS_030_D0 mcell H1 mx F29CLK_000_N_SYNC_12_ mcell D13 -mx F13CLK_000_P_SYNC_1_ mcell A15 mx F30 cpu_est_3_ mcell F1 -mx F14inst_CLK_000_NE_D0 mcell E5 mx F31 IPL_1_ pin 56 -mx F15 nEXP_SPACE pin 14 mx F32inst_DS_000_ENABLE mcell F9 -mx F16CLK_000_N_SYNC_0_ mcell D2 +mx F0 RST pin 86 mx F17 BERR pin 41 +mx F1 SM_AMIGA_2_ mcell F6 mx F18 RST_DLY_2_ mcell F9 +mx F2 SM_AMIGA_3_ mcell F10 mx F19 ... ... +mx F3 cpu_est_0_ mcell D2 mx F20 cpu_est_1_ mcell F8 +mx F4 ... ... mx F21 cpu_est_2_ mcell D13 +mx F5 nEXP_SPACE pin 14 mx F22 SM_AMIGA_0_ mcell G5 +mx F6 RST_DLY_1_ mcell F13 mx F23 ... ... +mx F7 cpu_est_3_ mcell D9 mx F24 ... ... +mx F8 inst_DTACK_D0 mcell G7 mx F25 RST_DLY_0_ mcell F0 +mx F9 inst_VPA_D mcell F2 mx F26 RN_VMA mcell D0 +mx F10 CLK_000_D_1_ mcell H3 mx F27inst_AS_030_000_SYNC mcell C6 +mx F11 CLK_000_D_0_ mcell C13 mx F28 ... ... +mx F12 SM_AMIGA_4_ mcell B10 mx F29 ... ... +mx F13 VPA pin 36 mx F30 SM_AMIGA_1_ mcell F1 +mx F14 SM_AMIGA_5_ mcell F5 mx F31 ... ... +mx F15 CLK_000_D_2_ mcell E2 mx F32 SM_AMIGA_6_ mcell C2 +mx F16 ... ... ---------------------------------------------------------------------------- @@ -1095,23 +1020,23 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RN_RW mcell G0 mx G17 cpu_est_1_ mcell F12 -mx G1 BERR pin 41 mx G18 CLK_000_D_1_ mcell C6 -mx G2 SM_AMIGA_5_ mcell F8 mx G19inst_BGACK_030_INT_D mcell H13 -mx G3 CLK_000_D_9_ mcell D11 mx G20 UDS_000 pin 32 -mx G4 inst_AS_000_INT mcell G2 mx G21 RST pin 86 -mx G5CLK_000_N_SYNC_6_ mcell B3 mx G22 SIZE_DMA_1_ mcell G5 -mx G6 RW_000 pin 80 mx G23 ... ... -mx G7 CLK_000_D_6_ mcell B11 mx G24 LDS_000 pin 31 -mx G8inst_CLK_OUT_PRE_D mcell E8 mx G25 inst_RESET_OUT mcell D9 -mx G9 CLK_000_D_2_ mcell G11 mx G26 ... ... -mx G10 cpu_est_3_ mcell F1 mx G27 SIZE_DMA_0_ mcell G9 -mx G11CLK_000_P_SYNC_5_ mcell G14 mx G28 RN_A_0_ mcell G8 -mx G12 inst_AS_030_D0 mcell H1 mx G29 cpu_est_2_ mcell F4 -mx G13CLK_000_P_SYNC_4_ mcell A11 mx G30 RN_BGACK_030 mcell H6 -mx G14 CLK_000 pin 11 mx G31 ... ... -mx G15 nEXP_SPACE pin 14 mx G32 ... ... -mx G16 ... ... +mx G0 RN_BGACK_030 mcell H4 mx G17 RN_RW mcell G0 +mx G1 BERR pin 41 mx G18 inst_RESET_OUT mcell A8 +mx G2 cpu_est_1_ mcell F8 mx G19 ... ... +mx G3 A_1_ pin 60 mx G20 CLK_000_D_7_ mcell A14 +mx G4 SIZE_DMA_0_ mcell G2 mx G21 cpu_est_2_ mcell D13 +mx G5inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G6 mx G22inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G10 +mx G6 RW_000 pin 80 mx G23 CLK_000_D_11_ mcell H0 +mx G7inst_BGACK_030_INT_D mcell H13 mx G24 RST pin 86 +mx G8 UDS_000 pin 32 mx G25 cpu_est_3_ mcell D9 +mx G9 DTACK pin 30 mx G26 ... ... +mx G10 SM_AMIGA_1_ mcell F1 mx G27 LDS_000 pin 31 +mx G11 CLK_000_D_1_ mcell H3 mx G28 ... ... +mx G12 SIZE_DMA_1_ mcell G9 mx G29 ... ... +mx G13 RN_A_0_ mcell G8 mx G30 CLK_000_D_0_ mcell C13 +mx G14 ... ... mx G31 ... ... +mx G15 nEXP_SPACE pin 14 mx G32 SM_AMIGA_0_ mcell G5 +mx G16inst_CLK_OUT_PRE_D mcell E8 ---------------------------------------------------------------------------- @@ -1119,23 +1044,23 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RST pin 86 mx H17 A_DECODE_18_ pin 95 -mx H1 BERR pin 41 mx H18 CLK_000_D_11_ mcell H10 -mx H2 AS_000 pin 42 mx H19 inst_AS_030_D0 mcell H1 -mx H3CLK_000_P_SYNC_10_ mcell A8 mx H20 SM_AMIGA_5_ mcell F8 -mx H4 CLK_000_D_12_ mcell H2 mx H21 RN_BGACK_030 mcell H6 -mx H5 nEXP_SPACE pin 14 mx H22 SIZE_DMA_1_ mcell G5 -mx H6 FC_0_ pin 57 mx H23 RN_RW_000 mcell H0 -mx H7 inst_RESET_OUT mcell D9 mx H24 inst_AS_000_DMA mcell A12 -mx H8 FPU_SENSE pin 91 mx H25 RW pin 71 -mx H9 AS_030 pin 82 mx H26 A_DECODE_16_ pin 96 -mx H10 SIZE_DMA_0_ mcell G9 mx H27 A_DECODE_19_ pin 97 -mx H11 RN_DSACK1 mcell H9 mx H28 CLK_030 pin 64 -mx H12 FC_1_ pin 58 mx H29 ... ... -mx H13 A_DECODE_17_ pin 59 mx H30 CLK_000_D_10_ mcell G15 -mx H14 SM_AMIGA_0_ mcell F5 mx H31 SM_AMIGA_i_7_ mcell F0 -mx H15 SM_AMIGA_1_ mcell F13 mx H32 BGACK_000 pin 28 -mx H16inst_CLK_OUT_PRE_D mcell E8 +mx H0 CLK_000_D_0_ mcell C13 mx H17 A_DECODE_18_ pin 95 +mx H1 BERR pin 41 mx H18 inst_RESET_OUT mcell A8 +mx H2 SM_AMIGA_6_ mcell C2 mx H19 RN_RW_000 mcell H1 +mx H3 SM_AMIGA_0_ mcell G5 mx H20 RN_BGACK_030 mcell H4 +mx H4 BGACK_000 pin 28 mx H21 RST pin 86 +mx H5 RN_DSACK1 mcell H9 mx H22 inst_AS_030_D0 mcell A6 +mx H6 A_DECODE_16_ pin 96 mx H23 CLK_000_D_11_ mcell H0 +mx H7 CLK_000_D_10_ mcell C14 mx H24 FC_0_ pin 57 +mx H8inst_CLK_OUT_PRE_D mcell E8 mx H25 RW pin 71 +mx H9 inst_AS_000_DMA mcell A12 mx H26 CLK_000_D_12_ mcell G14 +mx H10 SIZE_DMA_1_ mcell G9 mx H27 A_DECODE_19_ pin 97 +mx H11 CLK_000_D_1_ mcell H3 mx H28 CLK_030 pin 64 +mx H12 FC_1_ pin 58 mx H29 FPU_SENSE pin 91 +mx H13 A_DECODE_17_ pin 59 mx H30 SM_AMIGA_1_ mcell F1 +mx H14 SM_AMIGA_i_7_ mcell F4 mx H31 SIZE_DMA_0_ mcell G2 +mx H15 nEXP_SPACE pin 14 mx H32 AS_030 pin 82 +mx H16 AS_000 pin 42 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -1166,19 +1091,6 @@ PostFit_Equations 1 2 1 Pin LDS_000.OE 0 0 1 Pin BERR 1 9 1 Pin BERR.OE - 1 1 1 Pin CLK_DIV_OUT.D - 1 1 1 Pin CLK_DIV_OUT.C - 1 9 1 Pin FPU_CS- - 1 0 1 Pin AVEC - 2 3 1 Pin E - 0 0 1 Pin RESET - 1 1 1 Pin RESET.OE - 0 0 1 Pin AMIGA_ADDR_ENABLE - 2 4 1 Pin AMIGA_BUS_DATA_DIR - 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- - 3 5 1 Pin AMIGA_BUS_ENABLE_HIGH - 1 13 1 Pin CIIN - 1 1 1 Pin CIIN.OE 1 2 1 Pin SIZE_0_ 1 2 1 Pin SIZE_0_.OE 0 0 1 Pin AHIGH_30_ @@ -1191,25 +1103,31 @@ PostFit_Equations 1 3 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ 1 3 1 Pin AHIGH_26_.OE + 1 1 1 Pin CLK_DIV_OUT.D + 1 1 1 Pin CLK_DIV_OUT.C 0 0 1 Pin AHIGH_25_ 1 3 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 3 1 Pin AHIGH_24_.OE + 1 9 1 Pin FPU_CS- + 1 0 1 Pin AVEC + 2 3 1 Pin E + 0 0 1 Pin RESET + 1 1 1 Pin RESET.OE + 0 0 1 Pin AMIGA_ADDR_ENABLE + 2 4 1 Pin AMIGA_BUS_DATA_DIR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- + 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE - 3 7 1 Pin RW_000.D- + 4 8 1 Pin RW_000.D- 1 1 1 Pin RW_000.C - 1 3 1 Pin A_0_.OE - 3 5 1 Pin A_0_.D - 1 1 1 Pin A_0_.C - 10 8 1 Pin IPL_030_1_.D- - 1 1 1 Pin IPL_030_1_.C - 10 8 1 Pin IPL_030_0_.D- - 1 1 1 Pin IPL_030_0_.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C - 3 5 1 Pin BGACK_030.D + 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C @@ -1221,16 +1139,23 @@ PostFit_Equations 1 2 1 Pin RW.OE 2 5 1 Pin RW.D- 1 1 1 Pin RW.C - 3 10 1 Node N_226 - 4 4 1 Node cpu_est_2_.D - 1 1 1 Node cpu_est_2_.C - 3 5 1 Node cpu_est_3_.D + 1 3 1 Pin A_0_.OE + 3 5 1 Pin A_0_.D + 1 1 1 Pin A_0_.C + 10 8 1 Pin IPL_030_1_.D- + 1 1 1 Pin IPL_030_1_.C + 10 8 1 Pin IPL_030_0_.D- + 1 1 1 Pin IPL_030_0_.C + 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C - 2 2 1 Node cpu_est_0_.D + 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C - 3 4 1 Node cpu_est_1_.D + 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 2 5 1 Node inst_AS_000_INT.D- + 1 4 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 + 1 1 1 Node cpu_est_2_.C + 2 7 1 Node inst_AS_000_INT.D- 1 1 1 Node inst_AS_000_INT.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C @@ -1244,9 +1169,9 @@ PostFit_Equations 1 1 1 Node inst_AS_000_DMA.C 9 12 1 Node inst_DS_000_DMA.D 1 1 1 Node inst_DS_000_DMA.C - 2 5 1 Node CYCLE_DMA_0_.D + 3 6 1 Node CYCLE_DMA_0_.D 1 1 1 Node CYCLE_DMA_0_.C - 3 6 1 Node CYCLE_DMA_1_.D + 4 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C 3 6 1 Node SIZE_DMA_0_.D- 1 1 1 Node SIZE_DMA_0_.C @@ -1260,24 +1185,20 @@ PostFit_Equations 1 1 1 Node inst_LDS_000_INT.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 1 1 Node CLK_000_D_1_.D + 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_10_.D 1 1 1 Node CLK_000_D_10_.C 1 1 1 Node CLK_000_D_11_.D 1 1 1 Node CLK_000_D_11_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C - 2 6 1 Node inst_RESET_OUT.D + 2 7 1 Node inst_RESET_OUT.D 1 1 1 Node inst_RESET_OUT.C - 1 1 1 Node inst_CLK_OUT_PRE_50.D - 1 1 1 Node inst_CLK_OUT_PRE_50.C - 1 1 1 Node CLK_000_D_1_.D - 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C - 1 1 1 Node CLK_000_P_SYNC_10_.D - 1 1 1 Node CLK_000_P_SYNC_10_.C - 3 6 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C + 1 1 1 Node inst_CLK_OUT_PRE_50.D + 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 2 1 Node IPL_D0_0_.D- 1 1 1 Node IPL_D0_0_.C 1 2 1 Node IPL_D0_1_.D- @@ -1302,85 +1223,42 @@ PostFit_Equations 1 1 1 Node CLK_000_D_9_.C 1 1 1 Node CLK_000_D_12_.D 1 1 1 Node CLK_000_D_12_.C - 2 6 1 Node SM_AMIGA_0_.D - 1 1 1 Node SM_AMIGA_0_.C - 1 2 1 Node CLK_000_N_SYNC_0_.D - 1 1 1 Node CLK_000_N_SYNC_0_.C - 3 6 1 Node SM_AMIGA_4_.D - 1 1 1 Node SM_AMIGA_4_.C - 5 11 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C - 1 1 1 Node CLK_000_N_SYNC_12_.D - 1 1 1 Node CLK_000_N_SYNC_12_.C - 3 5 1 Node RST_DLY_0_.D - 1 1 1 Node RST_DLY_0_.C - 4 5 1 Node RST_DLY_1_.D - 1 1 1 Node RST_DLY_1_.C - 2 5 1 Node RST_DLY_2_.D - 1 1 1 Node RST_DLY_2_.C - 1 2 1 Node CLK_000_P_SYNC_0_.D - 1 1 1 Node CLK_000_P_SYNC_0_.C - 1 1 1 Node CLK_000_P_SYNC_1_.D - 1 1 1 Node CLK_000_P_SYNC_1_.C - 1 1 1 Node CLK_000_P_SYNC_2_.D - 1 1 1 Node CLK_000_P_SYNC_2_.C - 1 1 1 Node CLK_000_P_SYNC_3_.D - 1 1 1 Node CLK_000_P_SYNC_3_.C - 1 1 1 Node CLK_000_P_SYNC_4_.D - 1 1 1 Node CLK_000_P_SYNC_4_.C - 1 1 1 Node CLK_000_P_SYNC_5_.D - 1 1 1 Node CLK_000_P_SYNC_5_.C - 1 1 1 Node CLK_000_P_SYNC_6_.D - 1 1 1 Node CLK_000_P_SYNC_6_.C - 1 1 1 Node CLK_000_P_SYNC_7_.D - 1 1 1 Node CLK_000_P_SYNC_7_.C - 1 1 1 Node CLK_000_P_SYNC_8_.D - 1 1 1 Node CLK_000_P_SYNC_8_.C - 1 1 1 Node CLK_000_P_SYNC_9_.D - 1 1 1 Node CLK_000_P_SYNC_9_.C - 1 1 1 Node CLK_000_N_SYNC_1_.D - 1 1 1 Node CLK_000_N_SYNC_1_.C - 1 1 1 Node CLK_000_N_SYNC_2_.D - 1 1 1 Node CLK_000_N_SYNC_2_.C - 1 1 1 Node CLK_000_N_SYNC_3_.D - 1 1 1 Node CLK_000_N_SYNC_3_.C - 1 1 1 Node CLK_000_N_SYNC_4_.D - 1 1 1 Node CLK_000_N_SYNC_4_.C - 1 1 1 Node CLK_000_N_SYNC_5_.D - 1 1 1 Node CLK_000_N_SYNC_5_.C - 1 1 1 Node CLK_000_N_SYNC_6_.D - 1 1 1 Node CLK_000_N_SYNC_6_.C - 1 1 1 Node CLK_000_N_SYNC_7_.D - 1 1 1 Node CLK_000_N_SYNC_7_.C - 1 1 1 Node CLK_000_N_SYNC_8_.D - 1 1 1 Node CLK_000_N_SYNC_8_.C - 1 1 1 Node CLK_000_N_SYNC_9_.D - 1 1 1 Node CLK_000_N_SYNC_9_.C - 1 1 1 Node CLK_000_N_SYNC_10_.D - 1 1 1 Node CLK_000_N_SYNC_10_.C - 1 1 1 Node CLK_000_N_SYNC_11_.D - 1 1 1 Node CLK_000_N_SYNC_11_.C - 1 1 1 Node inst_CLK_000_NE_D0.D - 1 1 1 Node inst_CLK_000_NE_D0.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 3 8 1 Node SM_AMIGA_6_.D + 4 12 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C + 3 6 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 3 6 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C + 4 6 1 Node RST_DLY_0_.D + 1 1 1 Node RST_DLY_0_.C + 2 6 1 NodeX1 RST_DLY_1_.D.X1 + 1 2 1 NodeX2 RST_DLY_1_.D.X2 + 1 1 1 Node RST_DLY_1_.C + 2 6 1 Node RST_DLY_2_.D + 1 1 1 Node RST_DLY_2_.C 8 10 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C 3 6 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C - 5 13 1 Node SM_AMIGA_3_.T + 3 6 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C + 4 13 1 NodeX1 SM_AMIGA_3_.D.X1 + 1 3 1 NodeX2 SM_AMIGA_3_.D.X2 1 1 1 Node SM_AMIGA_3_.C 4 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C - 14 20 1 Node SM_AMIGA_i_7_.D + 13 21 1 NodeX1 SM_AMIGA_i_7_.D.X1 + 1 2 1 NodeX2 SM_AMIGA_i_7_.D.X2 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 351 P-Term Total: 351 + 301 P-Term Total: 301 Total Pins: 61 - Total Nodes: 79 + Total Nodes: 53 Average P-Term/Output: 2 @@ -1418,36 +1296,6 @@ BERR = (0); BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_DIV_OUT.C = (CLK_OSZI); - -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); - -AVEC = (1); - -E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q); - -RESET = (0); - -RESET.OE = (!inst_RESET_OUT.Q); - -AMIGA_ADDR_ENABLE = (0); - -AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN - # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); - -!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); - -AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q - # BGACK_030.Q & !SM_AMIGA_i_7_.Q - # CLK_000 & BGACK_030.Q & SM_AMIGA_0_.Q); - -CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); - -CIIN.OE = (CIIN_0); - SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); @@ -1472,6 +1320,10 @@ AHIGH_26_ = (0); AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_DIV_OUT.C = (CLK_OSZI); + AHIGH_25_ = (0); AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); @@ -1480,6 +1332,31 @@ AHIGH_24_ = (0); AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); + +AVEC = (1); + +E = (!cpu_est_3_.Q & cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_3_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q); + +RESET = (0); + +RESET.OE = (!inst_RESET_OUT.Q); + +AMIGA_ADDR_ENABLE = (0); + +AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN + # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); + +!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); + +AMIGA_BUS_ENABLE_HIGH = (BGACK_030.Q & inst_AS_030_000_SYNC.Q + # !BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); + +CIIN.OE = (CIIN_0); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -1495,12 +1372,50 @@ IPL_030_2_.C = (CLK_OSZI); RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); -!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN - # RST & !CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); +!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); RW_000.C = (CLK_OSZI); +!BG_000.D = (!BG_030 & RST & !BG_000.Q + # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); + +BG_000.C = (CLK_OSZI); + +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & AS_000.PIN); + +BGACK_030.C = (CLK_OSZI); + +CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_EXP.C = (CLK_OSZI); + +DSACK1.OE = (nEXP_SPACE); + +!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q + # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN + # !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q + # RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q); + +DSACK1.C = (CLK_OSZI); + +VMA.T = (!RST & !VMA.Q + # !VMA.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q + # RST & VMA.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +VMA.C = (CLK_OSZI); + +RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); + +!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); + +RW.C = (CLK_OSZI); + A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); A_0_.D = (!RST @@ -1535,72 +1450,33 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -!BG_000.D = (!BG_030 & RST & !BG_000.Q - # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); - -BG_000.C = (CLK_OSZI); - -BGACK_030.D = (!RST - # BGACK_000 & BGACK_030.Q - # BGACK_000 & CLK_000_P_SYNC_10_.Q & AS_000.PIN); - -BGACK_030.C = (CLK_OSZI); - -CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_EXP.C = (CLK_OSZI); - -DSACK1.OE = (nEXP_SPACE); - -!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q - # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN - # !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q - # RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q); - -DSACK1.C = (CLK_OSZI); - -VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_P_SYNC_10_.Q - # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_N_SYNC_12_.Q); - -VMA.C = (CLK_OSZI); - -RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); - -!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); - -RW.C = (CLK_OSZI); - -N_226 = (!nEXP_SPACE & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # inst_AS_030_000_SYNC.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !CLK_000_N_SYNC_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); - -cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q - # cpu_est_2_.Q & !cpu_est_1_.Q - # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q - # !cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); - -cpu_est_2_.C = (CLK_OSZI); - -cpu_est_3_.D = (cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q - # cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); +cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q + # cpu_est_3_.Q & CLK_000_D_0_.Q + # cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_2_.Q + # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_3_.C = (CLK_OSZI); -cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q - # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); +cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q + # cpu_est_0_.Q & CLK_000_D_0_.Q + # !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q - # cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q - # !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); + # cpu_est_1_.Q & !CLK_000_D_1_.Q + # cpu_est_1_.Q & CLK_000_D_0_.Q + # !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); cpu_est_1_.C = (CLK_OSZI); -!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q +cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN); inst_AS_000_INT.C = (CLK_OSZI); @@ -1650,14 +1526,16 @@ inst_DS_000_DMA.D = (!RST inst_DS_000_DMA.C = (CLK_OSZI); -CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN); +CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CLK_000_D_1_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_D_0_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN); CYCLE_DMA_0_.C = (CLK_OSZI); CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN); + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & CLK_000_D_1_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_D_0_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !AS_000.PIN); CYCLE_DMA_1_.C = (CLK_OSZI); @@ -1692,6 +1570,10 @@ inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); +CLK_000_D_1_.D = (CLK_000_D_0_.Q); + +CLK_000_D_1_.C = (CLK_OSZI); + CLK_000_D_10_.D = (CLK_000_D_9_.Q); CLK_000_D_10_.C = (CLK_OSZI); @@ -1705,31 +1587,17 @@ CLK_000_D_11_.C = (CLK_OSZI); inst_DTACK_D0.C = (CLK_OSZI); inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q - # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); inst_RESET_OUT.C = (CLK_OSZI); -inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); - -inst_CLK_OUT_PRE_50.C = (CLK_OSZI); - -CLK_000_D_1_.D = (CLK_000_D_0_.Q); - -CLK_000_D_1_.C = (CLK_OSZI); - CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); -CLK_000_P_SYNC_10_.D = (CLK_000_P_SYNC_9_.Q); +inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); -CLK_000_P_SYNC_10_.C = (CLK_OSZI); - -SM_AMIGA_5_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_6_.Q - # RST & SM_AMIGA_5_.Q & !CLK_000_N_SYNC_12_.Q & BERR.PIN - # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); - -SM_AMIGA_5_.C = (CLK_OSZI); +inst_CLK_OUT_PRE_50.C = (CLK_OSZI); !IPL_D0_0_.D = (RST & !IPL_0_); @@ -1779,150 +1647,55 @@ CLK_000_D_12_.D = (CLK_000_D_11_.Q); CLK_000_D_12_.C = (CLK_OSZI); -SM_AMIGA_0_.D = (RST & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_0_.Q & BERR.PIN); - -SM_AMIGA_0_.C = (CLK_OSZI); - -CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -CLK_000_N_SYNC_0_.C = (CLK_OSZI); - -SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q - # RST & SM_AMIGA_5_.Q & CLK_000_N_SYNC_12_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & BERR.PIN); - -SM_AMIGA_4_.C = (CLK_OSZI); - -inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN - # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q - # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN - # RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN); - -inst_DS_000_ENABLE.C = (CLK_OSZI); - -CLK_000_N_SYNC_12_.D = (CLK_000_N_SYNC_11_.Q); - -CLK_000_N_SYNC_12_.C = (CLK_OSZI); - -RST_DLY_0_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q - # RST & CLK_000_N_SYNC_12_.Q & !RST_DLY_0_.Q - # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); - -RST_DLY_0_.C = (CLK_OSZI); - -RST_DLY_1_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_1_.Q - # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q - # RST & RST_DLY_1_.Q & RST_DLY_2_.Q - # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q); - -RST_DLY_1_.C = (CLK_OSZI); - -RST_DLY_2_.D = (RST & RST_DLY_2_.Q - # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); - -RST_DLY_2_.C = (CLK_OSZI); - -CLK_000_P_SYNC_0_.D = (!CLK_000_D_1_.Q & CLK_000_D_0_.Q); - -CLK_000_P_SYNC_0_.C = (CLK_OSZI); - -CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); - -CLK_000_P_SYNC_1_.C = (CLK_OSZI); - -CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); - -CLK_000_P_SYNC_2_.C = (CLK_OSZI); - -CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); - -CLK_000_P_SYNC_3_.C = (CLK_OSZI); - -CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); - -CLK_000_P_SYNC_4_.C = (CLK_OSZI); - -CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); - -CLK_000_P_SYNC_5_.C = (CLK_OSZI); - -CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); - -CLK_000_P_SYNC_6_.C = (CLK_OSZI); - -CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); - -CLK_000_P_SYNC_7_.C = (CLK_OSZI); - -CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); - -CLK_000_P_SYNC_8_.C = (CLK_OSZI); - -CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); - -CLK_000_P_SYNC_9_.C = (CLK_OSZI); - -CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); - -CLK_000_N_SYNC_1_.C = (CLK_OSZI); - -CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); - -CLK_000_N_SYNC_2_.C = (CLK_OSZI); - -CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); - -CLK_000_N_SYNC_3_.C = (CLK_OSZI); - -CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); - -CLK_000_N_SYNC_4_.C = (CLK_OSZI); - -CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); - -CLK_000_N_SYNC_5_.C = (CLK_OSZI); - -CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); - -CLK_000_N_SYNC_6_.C = (CLK_OSZI); - -CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); - -CLK_000_N_SYNC_7_.C = (CLK_OSZI); - -CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); - -CLK_000_N_SYNC_8_.C = (CLK_OSZI); - -CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); - -CLK_000_N_SYNC_9_.C = (CLK_OSZI); - -CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); - -CLK_000_N_SYNC_10_.C = (CLK_OSZI); - -CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); - -CLK_000_N_SYNC_11_.C = (CLK_OSZI); - -inst_CLK_000_NE_D0.D = (CLK_000_N_SYNC_12_.Q); - -inst_CLK_000_NE_D0.C = (CLK_OSZI); - !inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); -SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_6_.Q & BERR.PIN - # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_N_SYNC_0_.Q & !SM_AMIGA_i_7_.Q); +inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN + # RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_i_7_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); +SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q + # RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q & BERR.PIN); + +SM_AMIGA_0_.C = (CLK_OSZI); + +SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q + # RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q & BERR.PIN); + +SM_AMIGA_4_.C = (CLK_OSZI); + +RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q + # RST & CLK_000_D_0_.Q & RST_DLY_0_.Q + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q + # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); + +RST_DLY_0_.C = (CLK_OSZI); + +RST_DLY_1_.D.X1 = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_2_.Q); + +RST_DLY_1_.D.X2 = (RST & RST_DLY_1_.Q); + +RST_DLY_1_.C = (CLK_OSZI); + +RST_DLY_2_.D = (RST & RST_DLY_2_.Q + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); + +RST_DLY_2_.C = (CLK_OSZI); + inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN @@ -1934,41 +1707,49 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); -SM_AMIGA_1_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q & BERR.PIN - # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN); +SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & BERR.PIN + # RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & BERR.PIN); SM_AMIGA_1_.C = (CLK_OSZI); -SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q - # SM_AMIGA_3_.Q & !BERR.PIN - # RST & CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q - # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); +SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q + # RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q & BERR.PIN + # RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q & BERR.PIN); + +SM_AMIGA_5_.C = (CLK_OSZI); + +SM_AMIGA_3_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN + # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & BERR.PIN); + +SM_AMIGA_3_.D.X2 = (RST & SM_AMIGA_3_.Q & BERR.PIN); SM_AMIGA_3_.C = (CLK_OSZI); -SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q - # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_2_.Q & BERR.PIN - # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q - # RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); +SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_i_7_.D = (RST & !N_226 & !CLK_000_P_SYNC_10_.Q & BERR.PIN - # RST & !N_226 & !SM_AMIGA_0_.Q & BERR.PIN - # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_3_.Q - # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q - # RST & !N_226 & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q - # RST & !N_226 & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); +SM_AMIGA_i_7_.D.X1 = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !BERR.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !BERR.PIN + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !BERR.PIN + # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q & !BERR.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q & !BERR.PIN + # RST & inst_VPA_D.Q & CLK_000_D_1_.Q & !inst_DTACK_D0.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # !nEXP_SPACE & RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & CLK_000_D_1_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & BERR.PIN + # RST & !VMA.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_1_.Q & CLK_000_D_2_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q & !BERR.PIN); + +SM_AMIGA_i_7_.D.X2 = (RST & BERR.PIN); SM_AMIGA_i_7_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 88fdb9d..0748a43 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -40,7 +40,6 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. BGACK_030 1 2 0 1 .. .. 1 1 RN_BGACK_030 1 2 0 1 .. .. 1 1 inst_AS_030_D0 1 2 1 1 .. .. 1 1 -inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 inst_DS_000_DMA 1 2 1 1 .. .. .. .. CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1 @@ -48,31 +47,15 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 SIZE_DMA_1_ 1 1 1 1 .. .. 2 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 inst_LDS_000_INT 1 1 1 1 .. .. 2 2 - SM_AMIGA_5_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_0_ 1 1 1 1 .. .. 1 2 -CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 2 - SM_AMIGA_4_ 1 1 .. .. .. .. 1 2 inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 - SM_AMIGA_6_ 1 1 .. .. .. .. 1 2 inst_CLK_030_H 1 2 .. .. .. .. 1 1 - SM_AMIGA_1_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_3_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_2_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_i_7_ 1 2 1 1 .. .. 1 1 AS_030 .. .. .. .. 1 1 .. .. AS_000 .. .. .. .. 1 1 .. .. -AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 RW_000 1 1 0 0 .. .. 1 1 RN_RW_000 1 1 0 0 .. .. 1 1 - A_0_ 1 1 0 0 .. .. 1 1 - RN_A_0_ 1 1 0 0 .. .. 1 1 - IPL_030_1_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 - IPL_030_0_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 DSACK1 1 1 0 0 .. .. 1 1 @@ -81,23 +64,28 @@ AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 1 .. .. RN_VMA 1 1 0 0 .. .. 1 1 RW 1 1 0 0 .. .. 1 1 RN_RW 1 1 0 0 .. .. 1 1 - N_226 .. .. .. .. 1 1 .. .. - cpu_est_2_ .. .. 1 1 .. .. 1 1 + A_0_ 1 1 0 0 .. .. 1 1 + RN_A_0_ 1 1 0 0 .. .. 1 1 + IPL_030_1_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 + IPL_030_0_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 cpu_est_3_ .. .. 1 1 .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. 1 1 .. .. 1 1 + cpu_est_2_ .. .. 1 1 .. .. 1 1 inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. +inst_AS_030_000_SYNC 1 1 1 1 .. .. 1 1 inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 + CLK_000_D_1_ .. .. .. .. .. .. 1 1 CLK_000_D_10_ .. .. .. .. .. .. 1 1 CLK_000_D_11_ .. .. .. .. .. .. 1 1 inst_DTACK_D0 1 1 .. .. .. .. 1 1 inst_RESET_OUT 1 1 .. .. .. .. .. .. -inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 - CLK_000_D_1_ .. .. .. .. .. .. 1 1 CLK_000_D_0_ 1 1 .. .. .. .. 1 1 -CLK_000_P_SYNC_10_ .. .. .. .. .. .. 1 1 +inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 IPL_D0_0_ 1 1 .. .. .. .. 1 1 IPL_D0_1_ 1 1 .. .. .. .. 1 1 IPL_D0_2_ 1 1 .. .. .. .. 1 1 @@ -110,31 +98,16 @@ CLK_000_P_SYNC_10_ .. .. .. .. .. .. 1 1 CLK_000_D_8_ .. .. .. .. .. .. 1 1 CLK_000_D_9_ .. .. .. .. .. .. 1 1 CLK_000_D_12_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_12_ .. .. .. .. .. .. 1 1 +inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. + SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_0_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_4_ 1 1 .. .. .. .. 1 1 RST_DLY_0_ 1 1 .. .. .. .. 1 1 RST_DLY_1_ 1 1 .. .. .. .. 1 1 RST_DLY_2_ 1 1 .. .. .. .. 1 1 -CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 -inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 -inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. + SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_5_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_3_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_2_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1 CIIN_0 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 243740c..ce48372 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,588 +1,590 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE 68030_tk -#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 78 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 SIZE_0_ AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 52 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_4_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 130 -.o 226 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C CLK_000_D_6_.C CLK_000_D_7_.C CLK_000_D_8_.C CLK_000_D_9_.C CLK_000_D_10_.C CLK_000_D_11_.C CLK_000_D_12_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C VMA.C inst_UDS_000_INT.C A_0_.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D CLK_000_D_10_.D CLK_000_D_11_.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D CLK_000_P_SYNC_10_.D SM_AMIGA_5_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_3_.D CLK_000_D_4_.D CLK_000_D_5_.D CLK_000_D_6_.D CLK_000_D_7_.D CLK_000_D_8_.D CLK_000_D_9_.D CLK_000_D_12_.D SM_AMIGA_0_.D DSACK1.D CLK_000_N_SYNC_0_.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D CLK_000_N_SYNC_12_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_9_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_11_.D RW_000.D RW.D inst_CLK_000_NE_D0.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D A_0_.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 576 ----------------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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-------------1------------0-----------001---------------------------------------------------------------0---------0-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------0-----------010---------------------------------------------------------------0---------0-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------0------------01-------------------------------------------------------------------------010-------------- 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--------------------------------------------------------------------------------------------------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------1-----1------------0------------01-------------------------------------------------------------------------0--0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------0----------0-01-------------------------------------------------------------------------0--0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0-----1------------0-----------001-------------------------------------------------------------------------0--0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1-----1------------0------------10-------------------------------------------------------------------------0--0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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-------------1------------0-----------010---------------------------------------------------------------0---------0--0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------0------------01-------------------------------------------------------------------------01-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------0------------10-------------------------------------------------------------------------01-0------------- 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----0-----------------------------------------------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------------------------------------------------------------------1----- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0------------------------------------------------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------------------------------------------------------1---- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------------------------------------------------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------------------------------------------------1--- ~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------------------------------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1-----------------------------------------------------------------------------------------1------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1-----------------------------------------------------------------------------------------1------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------------0-0----------------------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1--------------------00---------------------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1--------------------0----------------------------------0-----------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1-------------1---------------0--------------------------------------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1--------------1--------------0--------------------------------------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1---------------0-------------0--------------------------------------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1----------------1------------0--------------------------------------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1-----------------1-----------0--------------------------------------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1-----------------------------1-----1--------------------------------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1---------------------------------------------------------1----------------------------------1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------1--------------------------------------------------------------------------------------0-----1----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---01--------1------------1-------0-1-----------------------------------------------------------------------0--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------1---1--------1-------0-1-----------------------------------------------------------------------0--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------1----1-------1-------0-1-----------------------------------------------------------------------0--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------1-----0------1-------0-1-----------------------------------------------------------------------0--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------1------1-----1-------0-1-----------------------------------------------------------------------0--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------1---------0--1-------0-1-----------------------------------------------------------------------0--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------1-------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------0-------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------1------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------------------0----------------1---------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------1-----------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------------------------------------------------1-------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0------------------------------------------------1-------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------------------------------------------------------------------1-----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------------------------------------------------------------------------0-------------------------------1-----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------1---------------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------1--------------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------0-------------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------1------------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------1-----------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1-----1--------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------------------------------------------0-----1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------------------------------------------------0----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------------------------------0----------------------------------------------------1---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------------------------------------------------------------------------1--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------------------------------------------------------------------------------------------------------------0--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1-----------------------------------------1--------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------1--------------------1--------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------1----------------0---------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------1-------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 104 +.o 177 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q CLK_000_D_1_.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_D_6_.C CLK_000_D_7_.C CLK_000_D_8_.C CLK_000_D_9_.C CLK_000_D_10_.C CLK_000_D_11_.C CLK_000_D_12_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C RST_DLY_0_.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C VMA.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D CLK_000_D_1_.D CLK_000_D_10_.D CLK_000_D_11_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_3_.D CLK_000_D_4_.D CLK_000_D_5_.D CLK_000_D_6_.D CLK_000_D_7_.D CLK_000_D_8_.D CLK_000_D_9_.D CLK_000_D_12_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D inst_DS_000_ENABLE.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_4_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_5_.D SM_AMIGA_2_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 578 +-------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0----------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1---------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----0-------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1----------------------------------------------------------------------------------------------- ~~~~~~~~~~111111111111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1---------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1--------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1-------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1111111~~11111~~~~1~~~111~~~~~~~~~11~~~~11~~~1~~~~1~111 +----------------1--------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1-------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1----------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1---------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------0--------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1------------------------------------------------------------------------------- ~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1------------------1------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------0------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------10------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-----------------------00------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0------------0------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------01--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------0-1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0-11-------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------01-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------10-0-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-00-------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1------------------------------------------------------------------------ ~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1------1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----------------------------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1-------------0010--1----------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1--------1---------------------------------------------------------------------- ~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0--------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1---------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~ +---------------------------------10--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1------------------------------------------------------------------- 1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------11----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------00----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1---------1----1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1---------1-----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------10--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +---------------------------------------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1--------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1------------------0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1-----------------0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1----------------0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1---------------0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------1-----------0--1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------1-------------11-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1------------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0------------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------0------------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~111111111~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-----------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1----------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1---------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------00000---------------0----1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1-------------------0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1-----------------0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------0-----------------1----0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------010----------------1----0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------111---------------1----0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------110---------------1----0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------10110-----------0---1----0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------11------------------------------111------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111 +-1------------------10------------------------------011------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11 +-1------------------01------------------------------101------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1 +-1------------------00------------------------------001------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-0------------------11------------------------------110------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~ +-0------------------10------------------------------010------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-0------------------01------------------------------100------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---0-----------------------------------------0---------------------0-0----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1-----------0---------------------0-0----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---------0-----------0-0----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---------------------010----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------------1--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------------0--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +--------------------------------1----------------------------------1-----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------01-----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------1--------------------------------0----1----------------10------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-------------------------------------------------------------------1----------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 6e0ed44..7716294 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,588 +1,590 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE 68030_tk -#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 78 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 SIZE_0_ AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 52 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_4_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 130 -.o 226 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C CLK_000_D_6_.C CLK_000_D_7_.C CLK_000_D_8_.C CLK_000_D_9_.C CLK_000_D_10_.C CLK_000_D_11_.C CLK_000_D_12_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C VMA.C inst_UDS_000_INT.C A_0_.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D CLK_000_D_10_.D CLK_000_D_11_.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D CLK_000_P_SYNC_10_.D SM_AMIGA_5_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_3_.D CLK_000_D_4_.D CLK_000_D_5_.D CLK_000_D_6_.D CLK_000_D_7_.D CLK_000_D_8_.D CLK_000_D_9_.D CLK_000_D_12_.D SM_AMIGA_0_.D DSACK1.D CLK_000_N_SYNC_0_.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D CLK_000_N_SYNC_12_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_9_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_11_.D RW_000.D RW.D inst_CLK_000_NE_D0.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D A_0_.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 576 ----------------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1-------------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------1-------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 104 +.o 177 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q CLK_000_D_1_.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_D_6_.C CLK_000_D_7_.C CLK_000_D_8_.C CLK_000_D_9_.C CLK_000_D_10_.C CLK_000_D_11_.C CLK_000_D_12_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C RST_DLY_0_.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C VMA.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D CLK_000_D_1_.D CLK_000_D_10_.D CLK_000_D_11_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_3_.D CLK_000_D_4_.D CLK_000_D_5_.D CLK_000_D_6_.D CLK_000_D_7_.D CLK_000_D_8_.D CLK_000_D_9_.D CLK_000_D_12_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D inst_DS_000_ENABLE.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_4_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_5_.D SM_AMIGA_2_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 578 +-------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0----------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1---------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1111111~~11111~~~~1~~~111~~~~~~~~~11~~~~11~~~1~~~~1~111 +----------------1--------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1-------------------------------------------------------------------------------------- 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~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1------------------1------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------0------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------10------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------0-1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0-11-------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------01-------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11 +-1------------------01------------------------------101------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1 +-1------------------00------------------------------001------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-0------------------11------------------------------110------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~ +-0------------------10------------------------------010------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-0------------------01------------------------------100------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-------------------------------------------------------1------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1--------------------1---------------------------------000-------0000---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1--------------------------------1---------------------000-------0000---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------0-----------000-------0000---------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1--------------------------------1---------------------1-------------1--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +------------1-------------------------------------0----------------1-------------1--------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------------------------------0- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0---------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------0---------------0--------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------------1--------------------------------0----1----------------1----------------------------------0- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------1-------------------------------000----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---0-----------------------------------------0---------------------0-0----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1-----------0---------------------0-0----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---------0-----------0-0----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---------------------010----------0---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------------1--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------------0--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +--------------------------------1----------------------------------1-----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------01-----------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------1--------------------------------0----1----------------10------------1---------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-------------------------------------------------------------------1----------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index a2dbaf1..52d16ca 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,72 +1,59 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE BUS68030 -#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ - AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ - AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ - BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK - AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW - AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ - AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ - BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 79 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT +#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 + UDS_000 LDS_000 nEXP_SPACE BERR BG_030 SIZE_0_ AHIGH_30_ BGACK_000 AHIGH_29_ + CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ + AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ A_DECODE_20_ DTACK + A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH + CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 + VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 53 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT - inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT - inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ - IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ - CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ - SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ - RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ - CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ - CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ - CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ - CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ - CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 - inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ - SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 + inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 + inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ + CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ + CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_4_ RST_DLY_0_ RST_DLY_1_ + RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ + SM_AMIGA_i_7_ CIIN_0 .type f -.i 131 -.o 227 +.i 105 +.o 180 .ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ - N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q + BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q - CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q - inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q - SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q - CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q - CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q - SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q - RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q - CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q - CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q - CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q - CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q - CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q - inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q - inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q - BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN - UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN - AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN - AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 + CLK_000_D_1_.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q + CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q + CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q + CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q + SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q + A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q + SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN + AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN + AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN + AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 .ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE - CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ - AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ - AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% - RW_000.C RW_000.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% - IPL_030_0_.C BG_000.D% BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C - DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE N_226 cpu_est_2_.D - cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D - cpu_est_1_.C inst_AS_000_INT.D% inst_AS_000_INT.C + AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE CLK_DIV_OUT.D + CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE FPU_CS% AVEC E RESET + RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% + AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C + RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C + DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE A_0_.D A_0_.C A_0_.OE + IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C cpu_est_3_.D cpu_est_3_.C + cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1 + cpu_est_2_.D.X2 cpu_est_2_.C inst_AS_000_INT.D% inst_AS_000_INT.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C @@ -74,265 +61,226 @@ CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_10_.D CLK_000_D_10_.C - CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D% inst_DTACK_D0.C - inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_P_SYNC_10_.D - CLK_000_P_SYNC_10_.C SM_AMIGA_5_.D SM_AMIGA_5_.C IPL_D0_0_.D% IPL_D0_0_.C - IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_1_.D CLK_000_D_1_.C + CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D% + inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C + inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% + IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D - CLK_000_D_12_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CLK_000_N_SYNC_0_.D - CLK_000_N_SYNC_0_.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D - inst_DS_000_ENABLE.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C RST_DLY_0_.D - RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C - CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C - CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C - CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C - CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C - CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C - CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C - CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C - CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C - CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C - CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D - CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C - inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% - inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D - inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T SM_AMIGA_3_.C - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0 -.phase 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index f1cb9fb..cf6e697 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,72 +1,59 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE BUS68030 -#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ - AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ - AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ - BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK - AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW - AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ - AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ - BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 79 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT +#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 + UDS_000 LDS_000 nEXP_SPACE BERR BG_030 SIZE_0_ AHIGH_30_ BGACK_000 AHIGH_29_ + CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ + AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ A_DECODE_20_ DTACK + A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH + CIIN IPL_1_ IPL_0_ FC_0_ A_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 CLK_EXP DSACK1 + VMA RW A_0_ IPL_030_1_ IPL_030_0_ +#$ NODES 53 cpu_est_3_ cpu_est_0_ cpu_est_1_ cpu_est_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT - inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT - inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ - IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ - CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ - SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ - RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ - CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ - CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ - CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ - CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ - CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 - inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ - SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 + inst_CLK_OUT_PRE_D CLK_000_D_1_ CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 + inst_RESET_OUT CLK_000_D_0_ inst_CLK_OUT_PRE_50 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ + CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ + CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_DS_000_ENABLE SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_4_ RST_DLY_0_ RST_DLY_1_ + RST_DLY_2_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ + SM_AMIGA_i_7_ CIIN_0 .type f -.i 131 -.o 227 +.i 105 +.o 180 .ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ - N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q + BGACK_030.Q VMA.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q - CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q - inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q - SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q - CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q - CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q - SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q - RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q - CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q - CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q - CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q - CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q - CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q - inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q - inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q - BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN - UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN - AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN - AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 + CLK_000_D_1_.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q + CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q + CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q + CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q + inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q inst_DS_000_ENABLE.Q SM_AMIGA_6_.Q + SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q + A_0_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q + SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN + AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN + AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN + AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 .ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE - CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ - AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ - AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- - RW_000.C RW_000.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- - IPL_030_0_.C BG_000.D- BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C - DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE N_226 cpu_est_2_.D - cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D - cpu_est_1_.C inst_AS_000_INT.D- inst_AS_000_INT.C + AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE CLK_DIV_OUT.D + CLK_DIV_OUT.C AHIGH_25_ AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE FPU_CS- AVEC E RESET + RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- + AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C + RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C + DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE A_0_.D A_0_.C A_0_.OE + IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C cpu_est_3_.D cpu_est_3_.C + cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D.X1 + cpu_est_2_.D.X2 cpu_est_2_.C inst_AS_000_INT.D- inst_AS_000_INT.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C @@ -74,265 +61,226 @@ CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_10_.D CLK_000_D_10_.C - CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D- inst_DTACK_D0.C - inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_P_SYNC_10_.D - CLK_000_P_SYNC_10_.C SM_AMIGA_5_.D SM_AMIGA_5_.C IPL_D0_0_.D- IPL_D0_0_.C - IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_1_.D CLK_000_D_1_.C + CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D- + inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C CLK_000_D_0_.D CLK_000_D_0_.C + inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- + IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D - CLK_000_D_12_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CLK_000_N_SYNC_0_.D - CLK_000_N_SYNC_0_.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D - inst_DS_000_ENABLE.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C RST_DLY_0_.D - RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C - CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C - CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C - CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C - CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C - CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C - CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C - CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C - CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C - CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C - CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D - CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C - inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- - inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D - inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T SM_AMIGA_3_.C - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0 -.phase 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000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index d4186e5..85c57ca 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 8/19/16; -TIME = 00:20:46; +TIME = 00:39:39; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -138,12 +138,12 @@ layer = OFF; Layer = OFF BERR = OUTPUT,41,4,-; RW_000 = BIDIR,80,7,-; -AS_000 = OUTPUT,42,4,-; -A_0_ = BIDIR,69,6,-; -RW = BIDIR,71,6,-; AS_030 = OUTPUT,82,7,-; +AS_000 = OUTPUT,42,4,-; +RW = BIDIR,71,6,-; UDS_000 = OUTPUT,32,3,-; LDS_000 = OUTPUT,31,3,-; +A_0_ = BIDIR,69,6,-; SIZE_1_ = OUTPUT,79,7,-; SIZE_0_ = OUTPUT,70,6,-; AHIGH_24_ = OUTPUT,19,2,-; @@ -160,9 +160,9 @@ IPL_030_1_ = OUTPUT,7,1,-; DSACK1 = OUTPUT,81,7,-; BGACK_030 = OUTPUT,83,7,-; VMA = OUTPUT,35,3,-; -AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; E = OUTPUT,66,6,-; AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; +AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; BG_000 = OUTPUT,29,3,-; DS_030 = OUTPUT,98,0,-; AVEC = OUTPUT,92,0,-; @@ -173,93 +173,67 @@ AMIGA_ADDR_ENABLE = OUTPUT,33,3,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; +CLK_000_D_1_ = NODE,*,7,-; RN_BGACK_030 = NODE,-1,7,-; -inst_RESET_OUT = NODE,*,3,-; -inst_AS_030_D0 = NODE,*,7,-; -CLK_000_P_SYNC_10_ = NODE,*,0,-; -SM_AMIGA_i_7_ = NODE,*,5,-; +inst_RESET_OUT = NODE,*,0,-; +CLK_000_D_0_ = NODE,*,2,-; SM_AMIGA_6_ = NODE,*,2,-; -cpu_est_2_ = NODE,*,5,-; -SM_AMIGA_5_ = NODE,*,5,-; -cpu_est_1_ = NODE,*,5,-; -cpu_est_3_ = NODE,*,5,-; -SM_AMIGA_0_ = NODE,*,5,-; -cpu_est_0_ = NODE,*,1,-; -CLK_000_N_SYNC_12_ = NODE,*,3,-; -CLK_000_N_SYNC_0_ = NODE,*,3,-; -inst_CLK_OUT_PRE_D = NODE,*,4,-; -inst_BGACK_030_INT_D = NODE,*,7,-; -inst_AS_000_DMA = NODE,*,0,-; +inst_AS_030_D0 = NODE,*,0,-; +SM_AMIGA_0_ = NODE,*,6,-; +SM_AMIGA_i_7_ = NODE,*,5,-; inst_AS_030_000_SYNC = NODE,*,2,-; -inst_DS_000_ENABLE = NODE,*,5,-; -RN_VMA = NODE,-1,3,-; +cpu_est_1_ = NODE,*,5,-; +cpu_est_3_ = NODE,*,3,-; SM_AMIGA_1_ = NODE,*,5,-; -inst_LDS_000_INT = NODE,*,0,-; +CLK_000_D_2_ = NODE,*,4,-; +inst_CLK_OUT_PRE_D = NODE,*,4,-; +cpu_est_2_ = NODE,*,3,-; +inst_AS_000_DMA = NODE,*,0,-; +RST_DLY_0_ = NODE,*,5,-; +inst_DS_000_ENABLE = NODE,*,1,-; +RN_VMA = NODE,-1,3,-; +SM_AMIGA_5_ = NODE,*,5,-; +SM_AMIGA_4_ = NODE,*,1,-; SIZE_DMA_1_ = NODE,*,6,-; SIZE_DMA_0_ = NODE,*,6,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-; -inst_UDS_000_INT = NODE,*,1,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,1,-; -inst_AS_000_INT = NODE,*,6,-; -inst_CLK_000_NE_D0 = NODE,*,4,-; -CLK_000_D_0_ = NODE,*,6,-; -CLK_000_D_1_ = NODE,*,2,-; -inst_VPA_D = NODE,*,0,-; +cpu_est_0_ = NODE,*,3,-; +RST_DLY_2_ = NODE,*,5,-; +RST_DLY_1_ = NODE,*,5,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-; +inst_AS_000_INT = NODE,*,2,-; +CLK_000_D_11_ = NODE,*,7,-; +inst_VPA_D = NODE,*,5,-; +inst_BGACK_030_INT_D = NODE,*,7,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; inst_DS_000_DMA = NODE,*,0,-; inst_CLK_030_H = NODE,*,0,-; -SM_AMIGA_3_ = NODE,*,5,-; RN_DSACK1 = NODE,-1,7,-; -SM_AMIGA_2_ = NODE,*,5,-; -RST_DLY_1_ = NODE,*,3,-; -RN_A_0_ = NODE,-1,6,-; RN_RW_000 = NODE,-1,7,-; -RST_DLY_0_ = NODE,*,3,-; -SM_AMIGA_4_ = NODE,*,5,-; +SM_AMIGA_2_ = NODE,*,5,-; +SM_AMIGA_3_ = NODE,*,5,-; CYCLE_DMA_1_ = NODE,*,0,-; -N_226 = NODE,*,5,-; +RN_A_0_ = NODE,-1,6,-; +inst_LDS_000_INT = NODE,*,3,-; +CYCLE_DMA_0_ = NODE,*,0,-; RN_RW = NODE,-1,6,-; RN_BG_000 = NODE,-1,3,-; CIIN_0 = NODE,*,4,-; -RST_DLY_2_ = NODE,*,3,-; -CYCLE_DMA_0_ = NODE,*,0,-; -CLK_000_N_SYNC_11_ = NODE,*,2,-; -CLK_000_N_SYNC_10_ = NODE,*,2,-; -CLK_000_N_SYNC_9_ = NODE,*,5,-; -CLK_000_N_SYNC_8_ = NODE,*,1,-; -CLK_000_N_SYNC_7_ = NODE,*,6,-; -CLK_000_N_SYNC_6_ = NODE,*,1,-; -CLK_000_N_SYNC_5_ = NODE,*,0,-; -CLK_000_N_SYNC_4_ = NODE,*,0,-; -CLK_000_N_SYNC_3_ = NODE,*,5,-; -CLK_000_N_SYNC_2_ = NODE,*,0,-; -CLK_000_N_SYNC_1_ = NODE,*,4,-; -CLK_000_P_SYNC_9_ = NODE,*,2,-; -CLK_000_P_SYNC_8_ = NODE,*,0,-; -CLK_000_P_SYNC_7_ = NODE,*,3,-; -CLK_000_P_SYNC_6_ = NODE,*,6,-; -CLK_000_P_SYNC_5_ = NODE,*,6,-; -CLK_000_P_SYNC_4_ = NODE,*,0,-; -CLK_000_P_SYNC_3_ = NODE,*,2,-; -CLK_000_P_SYNC_2_ = NODE,*,5,-; -CLK_000_P_SYNC_1_ = NODE,*,0,-; -CLK_000_P_SYNC_0_ = NODE,*,3,-; -CLK_000_D_12_ = NODE,*,7,-; -CLK_000_D_9_ = NODE,*,3,-; -CLK_000_D_8_ = NODE,*,1,-; -CLK_000_D_7_ = NODE,*,6,-; -CLK_000_D_6_ = NODE,*,1,-; +inst_UDS_000_INT = NODE,*,3,-; +CLK_000_D_12_ = NODE,*,6,-; +CLK_000_D_9_ = NODE,*,0,-; +CLK_000_D_8_ = NODE,*,6,-; +CLK_000_D_7_ = NODE,*,0,-; +CLK_000_D_6_ = NODE,*,3,-; CLK_000_D_5_ = NODE,*,4,-; CLK_000_D_4_ = NODE,*,2,-; -CLK_000_D_3_ = NODE,*,6,-; -CLK_000_D_2_ = NODE,*,6,-; -IPL_D0_2_ = NODE,*,1,-; -IPL_D0_1_ = NODE,*,5,-; -IPL_D0_0_ = NODE,*,3,-; +CLK_000_D_3_ = NODE,*,4,-; +IPL_D0_2_ = NODE,*,0,-; +IPL_D0_1_ = NODE,*,1,-; +IPL_D0_0_ = NODE,*,1,-; inst_CLK_OUT_PRE_50 = NODE,*,4,-; -inst_DTACK_D0 = NODE,*,2,-; -CLK_000_D_11_ = NODE,*,7,-; -CLK_000_D_10_ = NODE,*,6,-; +inst_DTACK_D0 = NODE,*,6,-; +CLK_000_D_10_ = NODE,*,2,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 1ec2132..44248ee 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 8/19/16; -TIME = 00:20:46; +TIME = 00:39:40; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -136,16 +136,9 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; -A_DECODE_22_ = INPUT,84, H,-; -A_DECODE_21_ = INPUT,94, A,-; SIZE_1_ = BIDIR,79, H,-; -A_DECODE_20_ = INPUT,93, A,-; -A_DECODE_19_ = INPUT,97, A,-; AHIGH_31_ = BIDIR,4, B,-; -A_DECODE_18_ = INPUT,95, A,-; -A_DECODE_17_ = INPUT,59, F,-; A_DECODE_23_ = INPUT,85, H,-; -A_DECODE_16_ = INPUT,96, A,-; IPL_2_ = INPUT,68, G,-; FC_1_ = INPUT,58, F,-; AS_030 = BIDIR,82, H,-; @@ -156,21 +149,32 @@ LDS_000 = BIDIR,31, D,-; nEXP_SPACE = INPUT,14,-,-; BERR = BIDIR,41, E,-; BG_030 = INPUT,21, C,-; -IPL_1_ = INPUT,56, F,-; -IPL_0_ = INPUT,67, G,-; +SIZE_0_ = BIDIR,70, G,-; +AHIGH_30_ = BIDIR,5, B,-; BGACK_000 = INPUT,28, D,-; -FC_0_ = INPUT,57, F,-; +AHIGH_29_ = BIDIR,6, B,-; CLK_030 = INPUT,64,-,-; -A_1_ = INPUT,60, F,-; +AHIGH_28_ = BIDIR,15, C,-; CLK_000 = INPUT,11,-,-; +AHIGH_27_ = BIDIR,16, C,-; CLK_OSZI = INPUT,61,-,-; +AHIGH_26_ = BIDIR,17, C,-; CLK_DIV_OUT = OUTPUT,65, G,-; +AHIGH_25_ = BIDIR,18, C,-; +AHIGH_24_ = BIDIR,19, C,-; FPU_CS = OUTPUT,78, H,-; +A_DECODE_22_ = INPUT,84, H,-; FPU_SENSE = INPUT,91, A,-; +A_DECODE_21_ = INPUT,94, A,-; +A_DECODE_20_ = INPUT,93, A,-; DTACK = INPUT,30, D,-; +A_DECODE_19_ = INPUT,97, A,-; AVEC = OUTPUT,92, A,-; +A_DECODE_18_ = INPUT,95, A,-; E = OUTPUT,66, G,-; +A_DECODE_17_ = INPUT,59, F,-; VPA = INPUT,36,-,-; +A_DECODE_16_ = INPUT,96, A,-; RST = INPUT,86,-,-; RESET = OUTPUT,3, B,-; AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; @@ -178,101 +182,71 @@ AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; CIIN = OUTPUT,47, E,-; -SIZE_0_ = BIDIR,70, G,-; -AHIGH_30_ = BIDIR,5, B,-; -AHIGH_29_ = BIDIR,6, B,-; -AHIGH_28_ = BIDIR,15, C,-; -AHIGH_27_ = BIDIR,16, C,-; -AHIGH_26_ = BIDIR,17, C,-; -AHIGH_25_ = BIDIR,18, C,-; -AHIGH_24_ = BIDIR,19, C,-; +IPL_1_ = INPUT,56, F,-; +IPL_0_ = INPUT,67, G,-; +FC_0_ = INPUT,57, F,-; +A_1_ = INPUT,60, F,-; IPL_030_2_ = OUTPUT,9, B,-; RW_000 = BIDIR,80, H,-; -A_0_ = BIDIR,69, G,-; -IPL_030_1_ = OUTPUT,7, B,-; -IPL_030_0_ = OUTPUT,8, B,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; CLK_EXP = OUTPUT,10, B,-; DSACK1 = OUTPUT,81, H,-; VMA = OUTPUT,35, D,-; RW = BIDIR,71, G,-; -N_226 = NODE,14, F,-; -cpu_est_2_ = NODE,4, F,-; -cpu_est_3_ = NODE,1, F,-; -cpu_est_0_ = NODE,2, B,-; -cpu_est_1_ = NODE,12, F,-; -inst_AS_000_INT = NODE,2, G,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, B,-; -inst_AS_030_D0 = NODE,1, H,-; -inst_AS_030_000_SYNC = NODE,13, C,-; +A_0_ = BIDIR,69, G,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; +cpu_est_3_ = NODE,9, D,-; +cpu_est_0_ = NODE,2, D,-; +cpu_est_1_ = NODE,8, F,-; +cpu_est_2_ = NODE,13, D,-; +inst_AS_000_INT = NODE,15, C,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, G,-; +inst_AS_030_D0 = NODE,6, A,-; +inst_AS_030_000_SYNC = NODE,6, C,-; inst_BGACK_030_INT_D = NODE,13, H,-; inst_AS_000_DMA = NODE,12, A,-; -inst_DS_000_DMA = NODE,9, A,-; -CYCLE_DMA_0_ = NODE,10, A,-; -CYCLE_DMA_1_ = NODE,2, A,-; -SIZE_DMA_0_ = NODE,9, G,-; -SIZE_DMA_1_ = NODE,5, G,-; -inst_VPA_D = NODE,5, A,-; -inst_UDS_000_INT = NODE,6, B,-; -inst_LDS_000_INT = NODE,1, A,-; +inst_DS_000_DMA = NODE,1, A,-; +CYCLE_DMA_0_ = NODE,13, A,-; +CYCLE_DMA_1_ = NODE,9, A,-; +SIZE_DMA_0_ = NODE,2, G,-; +SIZE_DMA_1_ = NODE,9, G,-; +inst_VPA_D = NODE,2, F,-; +inst_UDS_000_INT = NODE,10, D,-; +inst_LDS_000_INT = NODE,6, D,-; inst_CLK_OUT_PRE_D = NODE,8, E,-; -CLK_000_D_10_ = NODE,15, G,-; -CLK_000_D_11_ = NODE,10, H,-; -inst_DTACK_D0 = NODE,15, C,-; -inst_RESET_OUT = NODE,9, D,-; -inst_CLK_OUT_PRE_50 = NODE,2, E,-; -CLK_000_D_1_ = NODE,6, C,-; -CLK_000_D_0_ = NODE,13, G,-; -CLK_000_P_SYNC_10_ = NODE,8, A,-; -SM_AMIGA_5_ = NODE,8, F,-; -IPL_D0_0_ = NODE,15, D,-; -IPL_D0_1_ = NODE,15, F,-; -IPL_D0_2_ = NODE,15, B,-; -CLK_000_D_2_ = NODE,11, G,-; -CLK_000_D_3_ = NODE,7, G,-; +CLK_000_D_1_ = NODE,3, H,-; +CLK_000_D_10_ = NODE,14, C,-; +CLK_000_D_11_ = NODE,0, H,-; +inst_DTACK_D0 = NODE,7, G,-; +inst_RESET_OUT = NODE,8, A,-; +CLK_000_D_0_ = NODE,13, C,-; +inst_CLK_OUT_PRE_50 = NODE,6, E,-; +IPL_D0_0_ = NODE,3, B,-; +IPL_D0_1_ = NODE,14, B,-; +IPL_D0_2_ = NODE,3, A,-; +CLK_000_D_2_ = NODE,2, E,-; +CLK_000_D_3_ = NODE,9, E,-; CLK_000_D_4_ = NODE,11, C,-; -CLK_000_D_5_ = NODE,13, E,-; -CLK_000_D_6_ = NODE,11, B,-; -CLK_000_D_7_ = NODE,3, G,-; -CLK_000_D_8_ = NODE,7, B,-; -CLK_000_D_9_ = NODE,11, D,-; -CLK_000_D_12_ = NODE,2, H,-; -SM_AMIGA_0_ = NODE,5, F,-; -CLK_000_N_SYNC_0_ = NODE,2, D,-; -SM_AMIGA_4_ = NODE,10, F,-; -inst_DS_000_ENABLE = NODE,9, F,-; -CLK_000_N_SYNC_12_ = NODE,13, D,-; -RST_DLY_0_ = NODE,10, D,-; -RST_DLY_1_ = NODE,6, D,-; -RST_DLY_2_ = NODE,14, D,-; -CLK_000_P_SYNC_0_ = NODE,7, D,-; -CLK_000_P_SYNC_1_ = NODE,15, A,-; -CLK_000_P_SYNC_2_ = NODE,11, F,-; -CLK_000_P_SYNC_3_ = NODE,7, C,-; -CLK_000_P_SYNC_4_ = NODE,11, A,-; -CLK_000_P_SYNC_5_ = NODE,14, G,-; -CLK_000_P_SYNC_6_ = NODE,10, G,-; -CLK_000_P_SYNC_7_ = NODE,3, D,-; -CLK_000_P_SYNC_8_ = NODE,7, A,-; -CLK_000_P_SYNC_9_ = NODE,3, C,-; -CLK_000_N_SYNC_1_ = NODE,9, E,-; -CLK_000_N_SYNC_2_ = NODE,3, A,-; -CLK_000_N_SYNC_3_ = NODE,7, F,-; -CLK_000_N_SYNC_4_ = NODE,14, A,-; -CLK_000_N_SYNC_5_ = NODE,6, A,-; -CLK_000_N_SYNC_6_ = NODE,3, B,-; -CLK_000_N_SYNC_7_ = NODE,6, G,-; -CLK_000_N_SYNC_8_ = NODE,14, B,-; -CLK_000_N_SYNC_9_ = NODE,3, F,-; -CLK_000_N_SYNC_10_ = NODE,14, C,-; -CLK_000_N_SYNC_11_ = NODE,10, C,-; -inst_CLK_000_NE_D0 = NODE,5, E,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,2, C,-; -SM_AMIGA_6_ = NODE,9, C,-; -inst_CLK_030_H = NODE,13, A,-; -SM_AMIGA_1_ = NODE,13, F,-; -SM_AMIGA_3_ = NODE,2, F,-; +CLK_000_D_5_ = NODE,5, E,-; +CLK_000_D_6_ = NODE,14, D,-; +CLK_000_D_7_ = NODE,14, A,-; +CLK_000_D_8_ = NODE,3, G,-; +CLK_000_D_9_ = NODE,10, A,-; +CLK_000_D_12_ = NODE,14, G,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,6, G,-; +inst_DS_000_ENABLE = NODE,6, B,-; +SM_AMIGA_6_ = NODE,2, C,-; +SM_AMIGA_0_ = NODE,5, G,-; +SM_AMIGA_4_ = NODE,10, B,-; +RST_DLY_0_ = NODE,0, F,-; +RST_DLY_1_ = NODE,13, F,-; +RST_DLY_2_ = NODE,9, F,-; +inst_CLK_030_H = NODE,5, A,-; +SM_AMIGA_1_ = NODE,1, F,-; +SM_AMIGA_5_ = NODE,5, F,-; +SM_AMIGA_3_ = NODE,10, F,-; SM_AMIGA_2_ = NODE,6, F,-; -SM_AMIGA_i_7_ = NODE,0, F,-; +SM_AMIGA_i_7_ = NODE,4, F,-; CIIN_0 = NODE,10, E,-; diff --git a/Logic/68030_tk.vho b/Logic/68030_tk.vho new file mode 100644 index 0000000..6838ef2 --- /dev/null +++ b/Logic/68030_tk.vho @@ -0,0 +1,3983 @@ +-- VHDL netlist-file +library mach; +use mach.components.all; + +library ieee; +use ieee.std_logic_1164.all; +entity BUS68030 is + port ( + SIZE : inout std_logic_vector(1 downto 0); + AHIGH : inout std_logic_vector(31 downto 24); + A_DECODE : in std_logic_vector(23 downto 2); + IPL : in std_logic_vector(2 downto 0); + FC : in std_logic_vector(1 downto 0); + AS_030 : inout std_logic; + AS_000 : inout std_logic; + DS_030 : out std_logic; + UDS_000 : inout std_logic; + LDS_000 : inout std_logic; + nEXP_SPACE : in std_logic; + BERR : inout std_logic; + BG_030 : in std_logic; + BGACK_000 : in std_logic; + CLK_030 : in std_logic; + CLK_000 : in std_logic; + CLK_OSZI : in std_logic; + CLK_DIV_OUT : out std_logic; + FPU_CS : out std_logic; + FPU_SENSE : in std_logic; + DTACK : in std_logic; + AVEC : out std_logic; + E : out std_logic; + VPA : in std_logic; + RST : in std_logic; + RESET : out std_logic; + AMIGA_ADDR_ENABLE : out std_logic; + AMIGA_BUS_DATA_DIR : out std_logic; + AMIGA_BUS_ENABLE_LOW : out std_logic; + AMIGA_BUS_ENABLE_HIGH : out std_logic; + CIIN : out std_logic; + A : inout std_logic_vector(1 downto 0); + IPL_030 : out std_logic_vector(2 downto 0); + RW_000 : inout std_logic; + BG_000 : out std_logic; + BGACK_030 : out std_logic; + CLK_EXP : out std_logic; + DSACK1 : out std_logic; + VMA : out std_logic; + RW : inout std_logic + ); +end BUS68030; + +architecture NetList of BUS68030 is + + signal SIZE_1XPIN : std_logic; + signal SIZE_1XCOM : std_logic; + signal AHIGH_31XPIN : std_logic; + signal A_DECODE_23XPIN : std_logic; + signal IPL_2XPIN : std_logic; + signal FC_1XPIN : std_logic; + signal AS_030PIN : std_logic; + signal AS_030COM : std_logic; + signal AS_000PIN : std_logic; + signal AS_000COM : std_logic; + signal DS_030COM : std_logic; + signal UDS_000PIN : std_logic; + signal UDS_000COM : std_logic; + signal LDS_000PIN : std_logic; + signal LDS_000COM : std_logic; + signal nEXP_SPACEPIN : std_logic; + signal BERRPIN : std_logic; + signal BG_030PIN : std_logic; + signal SIZE_0XPIN : std_logic; + signal SIZE_0XCOM : std_logic; + signal AHIGH_30XPIN : std_logic; + signal BGACK_000PIN : std_logic; + signal AHIGH_29XPIN : std_logic; + signal CLK_030PIN : std_logic; + signal AHIGH_28XPIN : std_logic; + signal CLK_000PIN : std_logic; + signal AHIGH_27XPIN : std_logic; + signal CLK_OSZIPIN : std_logic; + signal AHIGH_26XPIN : std_logic; + signal CLK_DIV_OUTQ : std_logic; + signal AHIGH_25XPIN : std_logic; + signal AHIGH_24XPIN : std_logic; + signal FPU_CSCOM : std_logic; + signal A_DECODE_22XPIN : std_logic; + signal FPU_SENSEPIN : std_logic; + signal A_DECODE_21XPIN : std_logic; + signal A_DECODE_20XPIN : std_logic; + signal DTACKPIN : std_logic; + signal A_DECODE_19XPIN : std_logic; + signal A_DECODE_18XPIN : std_logic; + signal ECOM : std_logic; + signal A_DECODE_17XPIN : std_logic; + signal VPAPIN : std_logic; + signal A_DECODE_16XPIN : std_logic; + signal RSTPIN : std_logic; + signal AMIGA_BUS_DATA_DIRCOM : std_logic; + signal AMIGA_BUS_ENABLE_LOWCOM : std_logic; + signal AMIGA_BUS_ENABLE_HIGHCOM : std_logic; + signal CIINCOM : std_logic; + signal IPL_1XPIN : std_logic; + signal IPL_0XPIN : std_logic; + signal FC_0XPIN : std_logic; + signal A_1XPIN : std_logic; + signal IPL_030_2XQ : std_logic; + signal RW_000PIN : std_logic; + signal RW_000Q : std_logic; + signal BG_000Q : std_logic; + signal BGACK_030Q : std_logic; + signal CLK_EXPQ : std_logic; + signal DSACK1Q : std_logic; + signal VMAQ : std_logic; + signal RWPIN : std_logic; + signal RWQ : std_logic; + signal A_0XPIN : std_logic; + signal A_0XQ : std_logic; + signal IPL_030_1XQ : std_logic; + signal IPL_030_0XQ : std_logic; + signal cpu_est_3_busQ : std_logic; + signal cpu_est_0_busQ : std_logic; + signal cpu_est_1_busQ : std_logic; + signal cpu_est_2_busQ : std_logic; + signal inst_AS_000_INTQ : std_logic; + signal inst_AMIGA_BUS_ENABLE_DMA_LOWQ : std_logic; + signal inst_AS_030_D0Q : std_logic; + signal inst_AS_030_000_SYNCQ : std_logic; + signal inst_BGACK_030_INT_DQ : std_logic; + signal inst_AS_000_DMAQ : std_logic; + signal inst_DS_000_DMAQ : std_logic; + signal CYCLE_DMA_0_busQ : std_logic; + signal CYCLE_DMA_1_busQ : std_logic; + signal SIZE_DMA_0_busQ : std_logic; + signal SIZE_DMA_1_busQ : std_logic; + signal inst_VPA_DQ : std_logic; + signal inst_UDS_000_INTQ : std_logic; + signal inst_LDS_000_INTQ : std_logic; + signal inst_CLK_OUT_PRE_DQ : std_logic; + signal CLK_000_D_1_busQ : std_logic; + signal CLK_000_D_10_busQ : std_logic; + signal CLK_000_D_11_busQ : std_logic; + signal inst_DTACK_D0Q : std_logic; + signal inst_RESET_OUTQ : std_logic; + signal CLK_000_D_0_busQ : std_logic; + signal inst_CLK_OUT_PRE_50Q : std_logic; + signal IPL_D0_0_busQ : std_logic; + signal IPL_D0_1_busQ : std_logic; + signal IPL_D0_2_busQ : std_logic; + signal CLK_000_D_2_busQ : std_logic; + signal CLK_000_D_3_busQ : std_logic; + signal CLK_000_D_4_busQ : std_logic; + signal CLK_000_D_5_busQ : std_logic; + signal CLK_000_D_6_busQ : std_logic; + signal CLK_000_D_7_busQ : std_logic; + signal CLK_000_D_8_busQ : std_logic; + signal CLK_000_D_9_busQ : std_logic; + signal CLK_000_D_12_busQ : std_logic; + signal inst_AMIGA_BUS_ENABLE_DMA_HIGHQ : std_logic; + signal inst_DS_000_ENABLEQ : std_logic; + signal SM_AMIGA_6_busQ : std_logic; + signal SM_AMIGA_0_busQ : std_logic; + signal SM_AMIGA_4_busQ : std_logic; + signal RST_DLY_0_busQ : std_logic; + signal RST_DLY_1_busQ : std_logic; + signal RST_DLY_2_busQ : std_logic; + signal inst_CLK_030_HQ : std_logic; + signal SM_AMIGA_1_busQ : std_logic; + signal SM_AMIGA_5_busQ : std_logic; + signal SM_AMIGA_3_busQ : std_logic; + signal SM_AMIGA_2_busQ : std_logic; + signal SM_AMIGA_i_7_busQ : std_logic; + signal SIZE_1X_OE : std_logic; + signal AHIGH_31X_OE : std_logic; + signal T_0 : std_logic; + signal AS_030_OE : std_logic; + signal T_1 : std_logic; + signal AS_000_OE : std_logic; + signal T_2 : std_logic; + signal DS_030_OE : std_logic; + signal T_3 : std_logic; + signal UDS_000_OE : std_logic; + signal T_4 : std_logic; + signal LDS_000_OE : std_logic; + signal BERR_OE : std_logic; + signal SIZE_0X_OE : std_logic; + signal AHIGH_30X_OE : std_logic; + signal AHIGH_29X_OE : std_logic; + signal AHIGH_28X_OE : std_logic; + signal AHIGH_27X_OE : std_logic; + signal AHIGH_26X_OE : std_logic; + signal AHIGH_25X_OE : std_logic; + signal AHIGH_24X_OE : std_logic; + signal T_5 : std_logic; + signal RESET_OE : std_logic; + signal T_6 : std_logic; + signal T_7 : std_logic; + signal T_8 : std_logic; + signal RW_000_OE : std_logic; + signal T_9 : std_logic; + signal BGACK_030_D : std_logic; + signal T_10 : std_logic; + signal VMA_T : std_logic; + signal T_11 : std_logic; + signal RW_OE : std_logic; + signal A_0X_D : std_logic; + signal A_0X_OE : std_logic; + signal T_12 : std_logic; + signal T_13 : std_logic; + signal cpu_est_3_bus_D : std_logic; + signal cpu_est_0_bus_D : std_logic; + signal cpu_est_1_bus_D : std_logic; + signal cpu_est_2_bus_D_X1 : std_logic; + signal T_14 : std_logic; + signal T_15 : std_logic; + signal T_16 : std_logic; + signal T_17 : std_logic; + signal T_18 : std_logic; + signal inst_AS_000_DMA_D : std_logic; + signal inst_DS_000_DMA_D : std_logic; + signal CYCLE_DMA_0_bus_D : std_logic; + signal CYCLE_DMA_1_bus_D : std_logic; + signal T_19 : std_logic; + signal SIZE_DMA_1_bus_D : std_logic; + signal T_20 : std_logic; + signal T_21 : std_logic; + signal inst_LDS_000_INT_D : std_logic; + signal T_22 : std_logic; + signal inst_RESET_OUT_D : std_logic; + signal inst_CLK_OUT_PRE_50_D : std_logic; + signal T_23 : std_logic; + signal T_24 : std_logic; + signal T_25 : std_logic; + signal T_26 : std_logic; + signal inst_DS_000_ENABLE_D : std_logic; + signal SM_AMIGA_6_bus_D : std_logic; + signal SM_AMIGA_0_bus_D : std_logic; + signal SM_AMIGA_4_bus_D : std_logic; + signal RST_DLY_0_bus_D : std_logic; + signal RST_DLY_1_bus_D_X1 : std_logic; + signal RST_DLY_1_bus_D_X2 : std_logic; + signal RST_DLY_2_bus_D : std_logic; + signal inst_CLK_030_H_D : std_logic; + signal SM_AMIGA_1_bus_D : std_logic; + signal SM_AMIGA_5_bus_D : std_logic; + signal SM_AMIGA_3_bus_D_X1 : std_logic; + signal SM_AMIGA_3_bus_D_X2 : std_logic; + signal SM_AMIGA_2_bus_D : std_logic; + signal SM_AMIGA_i_7_bus_D_X1 : std_logic; + signal SM_AMIGA_i_7_bus_D_X2 : std_logic; + signal CIIN_OE : std_logic; + signal cpu_est_2_bus_D : std_logic; + signal RST_DLY_1_bus_D : std_logic; + signal SM_AMIGA_3_bus_D : std_logic; + signal SM_AMIGA_i_7_bus_D : std_logic; + signal IPL_030_2X_D : std_logic; + signal RW_000_D : std_logic; + signal BG_000_D : std_logic; + signal DSACK1_D : std_logic; + signal RW_D : std_logic; + signal IPL_030_1X_D : std_logic; + signal IPL_030_0X_D : std_logic; + signal inst_AS_000_INT_D : std_logic; + signal inst_AMIGA_BUS_ENABLE_DMA_LOW_D : std_logic; + signal inst_AS_030_D0_D : std_logic; + signal inst_AS_030_000_SYNC_D : std_logic; + signal inst_BGACK_030_INT_D_D : std_logic; + signal SIZE_DMA_0_bus_D : std_logic; + signal inst_VPA_D_D : std_logic; + signal inst_UDS_000_INT_D : std_logic; + signal inst_DTACK_D0_D : std_logic; + signal IPL_D0_0_bus_D : std_logic; + signal IPL_D0_1_bus_D : std_logic; + signal IPL_D0_2_bus_D : std_logic; + signal inst_AMIGA_BUS_ENABLE_DMA_HIGH_D : std_logic; + signal T_27 : std_logic; + signal T_28 : std_logic; + signal T_29 : std_logic; + signal T_30 : std_logic; + signal T_31 : std_logic; + signal T_32 : std_logic; + signal T_33 : std_logic; + signal T_34 : std_logic; + signal T_35 : std_logic; + signal T_36 : std_logic; + signal T_37 : std_logic; + signal T_38 : std_logic; + signal T_39 : std_logic; + signal T_40 : std_logic; + signal T_41 : std_logic; + signal T_42 : std_logic; + signal T_43 : std_logic; + signal T_44 : std_logic; + signal T_45 : std_logic; + signal T_46 : std_logic; + signal T_47 : std_logic; + signal T_48 : std_logic; + signal T_49 : std_logic; + signal T_50 : std_logic; + signal T_51 : std_logic; + signal T_52 : std_logic; + signal T_53 : std_logic; + signal T_54 : std_logic; + signal T_55 : std_logic; + signal T_56 : std_logic; + signal T_57 : std_logic; + signal T_58 : std_logic; + signal T_59 : std_logic; + signal T_60 : std_logic; + signal T_61 : std_logic; + signal T_62 : std_logic; + signal T_63 : std_logic; + signal T_64 : std_logic; + signal T_65 : std_logic; + signal T_66 : std_logic; + signal T_67 : std_logic; + signal T_68 : std_logic; + signal T_69 : std_logic; + signal T_70 : std_logic; + signal T_71 : std_logic; + signal T_72 : std_logic; + signal T_73 : std_logic; + signal T_74 : std_logic; + signal T_75 : std_logic; + signal T_76 : std_logic; + signal T_77 : std_logic; + signal T_78 : std_logic; + signal T_79 : std_logic; + signal T_80 : std_logic; + signal T_81 : std_logic; + signal T_82 : std_logic; + signal T_83 : std_logic; + signal T_84 : std_logic; + signal T_85 : std_logic; + signal T_86 : std_logic; + signal T_87 : std_logic; + signal T_88 : std_logic; + signal T_89 : std_logic; + signal T_90 : std_logic; + signal T_91 : std_logic; + signal T_92 : std_logic; + signal T_93 : std_logic; + signal T_94 : std_logic; + signal T_95 : std_logic; + signal T_96 : std_logic; + signal T_97 : std_logic; + signal T_98 : std_logic; + signal T_99 : std_logic; + signal T_100 : std_logic; + signal T_101 : std_logic; + signal T_102 : std_logic; + signal T_103 : std_logic; + signal T_104 : std_logic; + signal T_105 : std_logic; + signal T_106 : std_logic; + signal T_107 : std_logic; + signal T_108 : std_logic; + signal T_109 : std_logic; + signal T_110 : std_logic; + signal T_111 : std_logic; + signal T_112 : std_logic; + signal T_113 : std_logic; + signal T_114 : std_logic; + signal T_115 : std_logic; + signal T_116 : std_logic; + signal T_117 : std_logic; + signal T_118 : std_logic; + signal T_119 : std_logic; + signal T_120 : std_logic; + signal T_121 : std_logic; + signal T_122 : std_logic; + signal T_123 : std_logic; + signal T_124 : std_logic; + signal T_125 : std_logic; + signal T_126 : std_logic; + signal T_127 : std_logic; + signal T_128 : std_logic; + signal T_129 : std_logic; + signal T_130 : std_logic; + signal T_131 : std_logic; + signal T_132 : std_logic; + signal T_133 : std_logic; + signal T_134 : std_logic; + signal T_135 : std_logic; + signal T_136 : std_logic; + signal T_137 : std_logic; + signal T_138 : std_logic; + signal T_139 : std_logic; + signal T_140 : std_logic; + signal T_141 : std_logic; + signal T_142 : std_logic; + signal T_143 : std_logic; + signal T_144 : std_logic; + signal T_145 : std_logic; + signal T_146 : std_logic; + signal T_147 : std_logic; + signal T_148 : std_logic; + signal T_149 : std_logic; + signal T_150 : std_logic; + signal T_151 : std_logic; + signal T_152 : std_logic; + signal T_153 : std_logic; + signal T_154 : std_logic; + signal T_155 : std_logic; + signal T_156 : std_logic; + signal T_157 : std_logic; + signal T_158 : std_logic; + signal T_159 : std_logic; + signal T_160 : std_logic; + signal T_161 : std_logic; + signal T_162 : std_logic; + signal T_163 : std_logic; + signal T_164 : std_logic; + signal T_165 : std_logic; + signal T_166 : std_logic; + signal T_167 : std_logic; + signal T_168 : std_logic; + signal T_169 : std_logic; + signal T_170 : std_logic; + signal T_171 : std_logic; + signal T_172 : std_logic; + signal T_173 : std_logic; + signal T_174 : std_logic; + signal T_175 : std_logic; + signal T_176 : std_logic; + signal T_177 : std_logic; + signal T_178 : std_logic; + signal T_179 : std_logic; + signal T_180 : std_logic; + signal T_181 : std_logic; + signal T_182 : std_logic; + signal T_183 : std_logic; + signal T_184 : std_logic; + signal T_185 : std_logic; + signal T_186 : std_logic; + signal T_187 : std_logic; + signal T_188 : std_logic; + signal T_189 : std_logic; + signal T_190 : std_logic; + signal T_191 : std_logic; + signal T_192 : std_logic; + signal T_193 : std_logic; + signal T_194 : std_logic; + signal T_195 : std_logic; + signal T_196 : std_logic; + signal T_197 : std_logic; + signal T_198 : std_logic; + signal T_199 : std_logic; + signal T_200 : std_logic; + signal T_201 : std_logic; + signal T_202 : std_logic; + signal T_203 : std_logic; + signal T_204 : std_logic; + signal T_205 : std_logic; + signal T_206 : std_logic; + signal T_207 : std_logic; + signal T_208 : std_logic; + signal T_209 : std_logic; + signal T_210 : std_logic; + signal T_211 : std_logic; + signal T_212 : std_logic; + signal T_213 : std_logic; + signal T_214 : std_logic; + signal T_215 : std_logic; + signal T_216 : std_logic; + signal T_217 : std_logic; + signal T_218 : std_logic; + signal T_219 : std_logic; + signal T_220 : std_logic; + signal T_221 : std_logic; + signal T_222 : std_logic; + signal T_223 : std_logic; + signal T_224 : std_logic; + signal T_225 : std_logic; + signal T_226 : std_logic; + signal T_227 : std_logic; + signal T_228 : std_logic; + signal T_229 : std_logic; + signal T_230 : std_logic; + signal T_231 : std_logic; + signal T_232 : std_logic; + signal T_233 : std_logic; + signal T_234 : std_logic; + signal T_235 : std_logic; + signal T_236 : std_logic; + signal T_237 : std_logic; + signal T_238 : std_logic; + signal T_239 : std_logic; + signal T_240 : std_logic; + signal T_241 : std_logic; + signal T_242 : std_logic; + signal T_243 : std_logic; + signal T_244 : std_logic; + signal T_245 : std_logic; + signal T_246 : std_logic; + signal T_247 : std_logic; + signal T_248 : std_logic; + signal T_249 : std_logic; + signal T_250 : std_logic; + signal T_251 : std_logic; + signal T_252 : std_logic; + signal T_253 : std_logic; + signal T_254 : std_logic; + signal T_255 : std_logic; + signal T_256 : std_logic; + signal T_257 : std_logic; + signal T_258 : std_logic; + signal T_259 : std_logic; + signal T_260 : std_logic; + signal T_261 : std_logic; + signal T_262 : std_logic; + signal T_263 : std_logic; + signal T_264 : std_logic; + signal T_265 : std_logic; + signal T_266 : std_logic; + signal T_267 : std_logic; + signal T_268 : std_logic; + signal T_269 : std_logic; + signal T_270 : std_logic; + signal T_271 : std_logic; + signal T_272 : std_logic; + signal T_273 : std_logic; + signal T_274 : std_logic; + signal T_275 : std_logic; + signal T_276 : std_logic; + signal T_277 : std_logic; + signal T_278 : std_logic; + signal T_279 : std_logic; + signal T_280 : std_logic; + signal T_281 : std_logic; + signal T_282 : std_logic; + signal T_283 : std_logic; + signal T_284 : std_logic; + signal T_285 : std_logic; + signal T_286 : std_logic; + signal T_287 : std_logic; + signal T_288 : std_logic; + signal T_289 : std_logic; + signal T_290 : std_logic; + signal T_291 : std_logic; + signal T_292 : std_logic; + signal T_293 : std_logic; + signal T_294 : std_logic; + signal T_295 : std_logic; + signal T_296 : std_logic; + signal T_297 : std_logic; + signal T_298 : std_logic; + signal T_299 : std_logic; + signal T_300 : std_logic; + signal T_301 : std_logic; + signal T_302 : std_logic; + signal T_303 : std_logic; + signal T_304 : std_logic; + signal T_305 : std_logic; + signal T_306 : std_logic; + signal T_307 : std_logic; + signal T_308 : std_logic; + signal T_309 : std_logic; + signal T_310 : std_logic; + signal T_311 : std_logic; + signal T_312 : std_logic; + signal T_313 : std_logic; + signal T_314 : std_logic; + signal T_315 : std_logic; + signal T_316 : std_logic; + signal T_317 : std_logic; + signal T_318 : std_logic; + signal T_319 : std_logic; + signal T_320 : std_logic; + signal T_321 : std_logic; + signal T_322 : std_logic; + signal T_323 : std_logic; + signal T_324 : std_logic; + signal T_325 : std_logic; + signal T_326 : std_logic; + signal T_327 : std_logic; + signal T_328 : std_logic; + signal T_329 : std_logic; + signal T_330 : std_logic; + signal T_331 : std_logic; + signal T_332 : std_logic; + signal T_333 : std_logic; + signal T_334 : std_logic; + signal T_335 : std_logic; + signal T_336 : std_logic; + signal T_337 : std_logic; + signal T_338 : std_logic; + signal T_339 : std_logic; + signal T_340 : std_logic; + signal T_341 : std_logic; + signal T_342 : std_logic; + signal T_343 : std_logic; + signal T_344 : std_logic; + signal T_345 : std_logic; + signal T_346 : std_logic; + signal T_347 : std_logic; + signal T_348 : std_logic; + signal T_349 : std_logic; + signal T_350 : std_logic; + signal T_351 : std_logic; + signal T_352 : std_logic; + signal T_353 : std_logic; + signal T_354 : std_logic; + signal T_355 : std_logic; + signal T_356 : std_logic; + signal T_357 : std_logic; + signal T_358 : std_logic; + signal T_359 : std_logic; + signal T_360 : std_logic; + signal T_361 : std_logic; + signal T_362 : std_logic; + signal T_363 : std_logic; + signal T_364 : std_logic; + signal T_365 : std_logic; + signal T_366 : std_logic; + signal T_367 : std_logic; + signal T_368 : std_logic; + signal T_369 : std_logic; + signal T_370 : std_logic; + signal T_371 : std_logic; + signal T_372 : std_logic; + signal T_373 : std_logic; + signal T_374 : std_logic; + signal T_375 : std_logic; + signal T_376 : std_logic; + signal T_377 : std_logic; + signal T_378 : std_logic; + signal T_379 : std_logic; + signal T_380 : std_logic; + signal T_381 : std_logic; + signal T_382 : std_logic; + signal T_383 : std_logic; + signal T_384 : std_logic; + signal T_385 : std_logic; + signal T_386 : std_logic; + signal T_387 : std_logic; + signal T_388 : std_logic; + signal T_389 : std_logic; + signal T_390 : std_logic; + signal T_391 : std_logic; + signal T_392 : std_logic; + signal T_393 : std_logic; + signal T_394 : std_logic; + signal T_395 : std_logic; + signal T_396 : std_logic; + signal T_397 : std_logic; + signal T_398 : std_logic; + signal T_399 : std_logic; + signal T_400 : std_logic; + signal T_401 : std_logic; + signal T_402 : std_logic; + signal T_403 : std_logic; + signal T_404 : std_logic; + signal T_405 : std_logic; + signal T_406 : std_logic; + signal T_407 : std_logic; + signal T_408 : std_logic; + signal T_409 : std_logic; + signal T_410 : std_logic; + signal T_411 : std_logic; + signal T_412 : std_logic; + signal T_413 : std_logic; + signal T_414 : std_logic; + signal T_415 : std_logic; + signal T_416 : std_logic; + signal T_417 : std_logic; + signal T_418 : std_logic; + signal T_419 : std_logic; + signal T_420 : std_logic; + signal T_421 : std_logic; + signal T_422 : std_logic; + signal T_423 : std_logic; + signal T_424 : std_logic; + signal T_425 : std_logic; + signal T_426 : std_logic; + signal T_427 : std_logic; + signal T_428 : std_logic; + signal T_429 : std_logic; + signal T_430 : std_logic; + signal VCC_net : std_logic; + signal GND_net : std_logic; + signal GATE_SIZE_1_XA : std_logic; + signal GATE_AHIGH_31X_OE_A : std_logic; + signal GATE_AHIGH_31X_OE_B : std_logic; + signal GATE_AS_030_OE_A : std_logic; + signal GATE_AS_030_OE_B : std_logic; + signal GATE_DS_030_OE_A : std_logic; + signal GATE_DS_030_OE_B : std_logic; + signal GATE_T_3_A : std_logic; + signal GATE_T_4_A : std_logic; + signal GATE_SIZE_0_XA : std_logic; + signal GATE_AHIGH_30X_OE_A : std_logic; + signal GATE_AHIGH_30X_OE_B : std_logic; + signal GATE_AHIGH_29X_OE_A : std_logic; + signal GATE_AHIGH_29X_OE_B : std_logic; + signal GATE_AHIGH_28X_OE_A : std_logic; + signal GATE_AHIGH_28X_OE_B : std_logic; + signal GATE_AHIGH_27X_OE_A : std_logic; + signal GATE_AHIGH_27X_OE_B : std_logic; + signal GATE_AHIGH_26X_OE_A : std_logic; + signal GATE_AHIGH_26X_OE_B : std_logic; + signal GATE_AHIGH_25X_OE_A : std_logic; + signal GATE_AHIGH_25X_OE_B : std_logic; + signal GATE_AHIGH_24X_OE_A : std_logic; + signal GATE_AHIGH_24X_OE_B : std_logic; + signal GATE_CIIN_A : std_logic; + signal GATE_BGACK_030_D_B : std_logic; + signal GATE_BGACK_030_D_A : std_logic; + signal GATE_RW_OE_A : std_logic; + signal GATE_A_0X_D_B : std_logic; + signal GATE_A_0X_D_A : std_logic; + signal GATE_A_0X_OE_A : std_logic; + signal GATE_A_0X_OE_B : std_logic; + signal GATE_cpu_est_2_bus_D_X1_A : std_logic; + signal GATE_T_16_A : std_logic; + signal GATE_T_18_A : std_logic; + signal GATE_inst_AS_000_DMA_D_C : std_logic; + signal GATE_inst_AS_000_DMA_D_B : std_logic; + signal GATE_inst_AS_000_DMA_D_A : std_logic; + signal GATE_SIZE_DMA_1_bus_D_B : std_logic; + signal GATE_SIZE_DMA_1_bus_D_A : std_logic; + signal GATE_T_20_A : std_logic; + signal GATE_inst_LDS_000_INT_D_B : std_logic; + signal GATE_inst_LDS_000_INT_D_A : std_logic; + signal GATE_T_22_A : std_logic; + signal GATE_T_23_A : std_logic; + signal GATE_T_24_A : std_logic; + signal GATE_T_25_A : std_logic; + signal GATE_T_27_A : std_logic; + signal GATE_T_34_A : std_logic; + signal GATE_T_35_A : std_logic; + signal GATE_T_36_A : std_logic; + signal GATE_T_37_A : std_logic; + signal GATE_T_38_A : std_logic; + signal GATE_T_39_A : std_logic; + signal GATE_T_42_A : std_logic; + signal GATE_T_43_A : std_logic; + signal GATE_T_44_A : std_logic; + signal GATE_T_45_A : std_logic; + signal GATE_T_48_A : std_logic; + signal GATE_T_51_A : std_logic; + signal GATE_T_52_A : std_logic; + signal GATE_T_54_A : std_logic; + signal GATE_T_55_A : std_logic; + signal GATE_T_60_A : std_logic; + signal GATE_T_61_A : std_logic; + signal GATE_T_62_A : std_logic; + signal GATE_T_63_A : std_logic; + signal GATE_T_67_B : std_logic; + signal GATE_T_67_A : std_logic; + signal GATE_T_69_A : std_logic; + signal GATE_T_70_A : std_logic; + signal GATE_T_72_A : std_logic; + signal GATE_T_73_A : std_logic; + signal GATE_T_75_A : std_logic; + signal GATE_T_82_A : std_logic; + signal GATE_T_83_A : std_logic; + signal GATE_T_84_A : std_logic; + signal GATE_T_84_B : std_logic; + signal GATE_T_87_B : std_logic; + signal GATE_T_87_A : std_logic; + signal GATE_T_88_A : std_logic; + signal GATE_T_89_A : std_logic; + signal GATE_T_90_A : std_logic; + signal GATE_T_90_B : std_logic; + signal GATE_T_93_DN : std_logic; + signal GATE_T_94_A : std_logic; + signal GATE_T_95_A : std_logic; + signal GATE_T_96_A : std_logic; + signal GATE_T_97_A : std_logic; + signal GATE_T_98_A : std_logic; + signal GATE_T_99_A : std_logic; + signal GATE_T_101_A : std_logic; + signal GATE_T_102_A : std_logic; + signal GATE_T_103_A : std_logic; + signal GATE_T_104_A : std_logic; + signal GATE_T_104_B : std_logic; + signal GATE_T_105_A : std_logic; + signal GATE_T_105_B : std_logic; + signal GATE_T_112_A : std_logic; + signal GATE_T_119_B : std_logic; + signal GATE_T_119_A : std_logic; + signal GATE_T_120_A : std_logic; + signal GATE_T_121_A : std_logic; + signal GATE_T_122_B : std_logic; + signal GATE_T_122_A : std_logic; + signal GATE_T_123_A : std_logic; + signal GATE_T_124_A : std_logic; + signal GATE_T_126_A : std_logic; + signal GATE_T_127_A : std_logic; + signal GATE_T_128_A : std_logic; + signal GATE_T_128_B : std_logic; + signal GATE_T_130_A : std_logic; + signal GATE_T_131_A : std_logic; + signal GATE_T_132_A : std_logic; + signal GATE_T_132_B : std_logic; + signal GATE_T_134_A : std_logic; + signal GATE_T_135_A : std_logic; + signal GATE_T_136_A : std_logic; + signal GATE_T_139_B : std_logic; + signal GATE_T_139_A : std_logic; + signal GATE_T_140_B : std_logic; + signal GATE_T_140_A : std_logic; + signal GATE_T_141_B : std_logic; + signal GATE_T_141_A : std_logic; + signal GATE_T_142_B : std_logic; + signal GATE_T_142_A : std_logic; + signal GATE_T_143_A : std_logic; + signal GATE_T_143_B : std_logic; + signal GATE_T_144_A : std_logic; + signal GATE_T_144_B : std_logic; + signal GATE_T_145_A : std_logic; + signal GATE_T_146_A : std_logic; + signal GATE_T_149_B : std_logic; + signal GATE_T_149_A : std_logic; + signal GATE_T_150_B : std_logic; + signal GATE_T_150_A : std_logic; + signal GATE_T_151_B : std_logic; + signal GATE_T_151_A : std_logic; + signal GATE_T_152_B : std_logic; + signal GATE_T_152_A : std_logic; + signal GATE_T_153_A : std_logic; + signal GATE_T_153_B : std_logic; + signal GATE_T_154_A : std_logic; + signal GATE_T_154_B : std_logic; + signal GATE_T_156_A : std_logic; + signal GATE_T_157_A : std_logic; + signal GATE_T_158_A : std_logic; + signal GATE_T_158_B : std_logic; + signal GATE_T_164_B : std_logic; + signal GATE_T_164_A : std_logic; + signal GATE_T_165_A : std_logic; + signal GATE_T_166_A : std_logic; + signal GATE_T_169_A : std_logic; + signal GATE_T_169_B : std_logic; + signal GATE_T_170_A : std_logic; + signal GATE_T_172_B : std_logic; + signal GATE_T_172_A : std_logic; + signal GATE_T_173_A : std_logic; + signal GATE_T_174_A : std_logic; + signal GATE_T_175_A : std_logic; + signal GATE_T_176_A : std_logic; + signal GATE_T_177_A : std_logic; + signal GATE_T_178_B : std_logic; + signal GATE_T_178_A : std_logic; + signal GATE_T_179_B : std_logic; + signal GATE_T_179_A : std_logic; + signal GATE_T_180_B : std_logic; + signal GATE_T_180_A : std_logic; + signal GATE_T_181_B : std_logic; + signal GATE_T_181_A : std_logic; + signal GATE_T_182_A : std_logic; + signal GATE_T_182_B : std_logic; + signal GATE_T_183_A : std_logic; + signal GATE_T_183_B : std_logic; + signal GATE_T_184_A : std_logic; + signal GATE_T_185_A : std_logic; + signal GATE_T_187_DN : std_logic; + signal GATE_T_188_A : std_logic; + signal GATE_T_189_A : std_logic; + signal GATE_T_189_B : std_logic; + signal GATE_T_190_A : std_logic; + signal GATE_T_195_A : std_logic; + signal GATE_T_197_A : std_logic; + signal GATE_T_198_A : std_logic; + signal GATE_T_200_A : std_logic; + signal GATE_T_203_A : std_logic; + signal GATE_T_204_A : std_logic; + signal GATE_T_205_A : std_logic; + signal GATE_T_209_A : std_logic; + signal GATE_T_209_B : std_logic; + signal GATE_T_212_A : std_logic; + signal GATE_T_215_A : std_logic; + signal GATE_T_218_A : std_logic; + signal GATE_T_218_B : std_logic; + signal GATE_T_219_A : std_logic; + signal GATE_T_221_A : std_logic; + signal GATE_T_221_B : std_logic; + signal GATE_T_222_A : std_logic; + signal GATE_T_223_A : std_logic; + signal GATE_T_224_A : std_logic; + signal GATE_T_224_B : std_logic; + signal GATE_T_226_A : std_logic; + signal GATE_T_228_DN : std_logic; + signal GATE_T_229_B : std_logic; + signal GATE_T_229_A : std_logic; + signal GATE_T_231_A : std_logic; + signal GATE_T_233_A : std_logic; + signal GATE_T_234_A : std_logic; + signal GATE_T_235_A : std_logic; + signal GATE_T_238_A : std_logic; + signal GATE_T_238_B : std_logic; + signal GATE_T_240_A : std_logic; + signal GATE_T_241_A : std_logic; + signal GATE_T_243_A : std_logic; + signal GATE_T_245_A : std_logic; + signal GATE_T_246_A : std_logic; + signal GATE_T_248_A : std_logic; + signal GATE_T_248_B : std_logic; + signal GATE_T_250_A : std_logic; + signal GATE_T_255_A : std_logic; + signal GATE_T_256_A : std_logic; + signal GATE_T_257_A : std_logic; + signal GATE_T_258_A : std_logic; + signal GATE_T_259_A : std_logic; + signal GATE_T_260_A : std_logic; + signal GATE_T_261_A : std_logic; + signal GATE_T_262_A : std_logic; + signal GATE_T_263_A : std_logic; + signal GATE_T_264_A : std_logic; + signal GATE_T_265_A : std_logic; + signal GATE_T_266_A : std_logic; + signal GATE_T_268_A : std_logic; + signal GATE_T_270_A : std_logic; + signal GATE_T_272_A : std_logic; + signal GATE_T_274_A : std_logic; + signal GATE_T_276_A : std_logic; + signal GATE_T_278_A : std_logic; + signal GATE_T_280_A : std_logic; + signal GATE_T_282_A : std_logic; + signal GATE_T_283_A : std_logic; + signal GATE_T_288_A : std_logic; + signal GATE_T_289_A : std_logic; + signal GATE_T_292_A : std_logic; + signal GATE_T_294_A : std_logic; + signal GATE_T_296_A : std_logic; + signal GATE_T_297_A : std_logic; + signal GATE_T_298_A : std_logic; + signal GATE_T_299_A : std_logic; + signal GATE_T_300_A : std_logic; + signal GATE_T_302_A : std_logic; + signal GATE_T_304_A : std_logic; + signal GATE_T_305_A : std_logic; + signal GATE_T_307_A : std_logic; + signal GATE_T_308_A : std_logic; + signal GATE_T_309_A : std_logic; + signal GATE_T_310_A : std_logic; + signal GATE_T_311_A : std_logic; + signal GATE_T_312_A : std_logic; + signal GATE_T_314_A : std_logic; + signal GATE_T_315_A : std_logic; + signal GATE_T_316_A : std_logic; + signal GATE_T_317_A : std_logic; + signal GATE_T_319_A : std_logic; + signal GATE_T_320_B : std_logic; + signal GATE_T_320_A : std_logic; + signal GATE_T_329_A : std_logic; + signal GATE_T_330_A : std_logic; + signal GATE_T_332_A : std_logic; + signal GATE_T_333_A : std_logic; + signal GATE_T_334_A : std_logic; + signal GATE_T_337_A : std_logic; + signal GATE_T_338_A : std_logic; + signal GATE_T_341_A : std_logic; + signal GATE_T_342_A : std_logic; + signal GATE_T_343_A : std_logic; + signal GATE_T_345_A : std_logic; + signal GATE_T_346_A : std_logic; + signal GATE_T_349_A : std_logic; + signal GATE_T_350_A : std_logic; + signal GATE_T_351_A : std_logic; + signal GATE_T_353_A : std_logic; + signal GATE_T_354_A : std_logic; + signal GATE_T_360_A : std_logic; + signal GATE_T_361_A : std_logic; + signal GATE_T_366_A : std_logic; + signal GATE_T_367_A : std_logic; + signal GATE_T_368_A : std_logic; + signal GATE_T_371_A : std_logic; + signal GATE_T_375_A : std_logic; + signal GATE_T_376_A : std_logic; + signal GATE_T_381_A : std_logic; + signal GATE_T_382_A : std_logic; + signal GATE_T_383_A : std_logic; + signal GATE_T_386_A : std_logic; + signal GATE_T_390_A : std_logic; + signal GATE_T_390_B : std_logic; + signal GATE_T_391_A : std_logic; + signal GATE_T_392_A : std_logic; + signal GATE_T_393_A : std_logic; + signal GATE_T_394_A : std_logic; + signal GATE_T_395_A : std_logic; + signal GATE_T_398_A : std_logic; + signal GATE_T_400_A : std_logic; + signal GATE_T_401_A : std_logic; + signal GATE_T_403_A : std_logic; + signal GATE_T_409_A : std_logic; + signal GATE_T_410_A : std_logic; + signal GATE_T_411_A : std_logic; + signal GATE_T_412_A : std_logic; + signal GATE_T_413_A : std_logic; + signal GATE_T_414_A : std_logic; + signal GATE_T_415_A : std_logic; + signal GATE_T_418_A : std_logic; + signal GATE_T_425_A : std_logic; + signal GATE_T_425_B : std_logic; + signal GATE_T_426_A : std_logic; + signal GATE_T_426_B : std_logic; + signal GATE_T_427_A : std_logic; + signal GATE_T_428_A : std_logic; + signal GATE_T_428_B : std_logic; + signal GATE_T_429_A : std_logic; + signal GATE_T_429_B : std_logic; + +begin + VCC_I_I_1: VCC port map ( X=>VCC_net ); + GND_I_I_1: GND port map ( X=>GND_net ); + OUT_SIZE_1_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>SIZE_1XPIN, + I0=>SIZE_1XCOM, + IO=>SIZE(1), + OE=>SIZE_1X_OE ); + OUT_AHIGH_31_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_31XPIN, + I0=>GND_net, + IO=>AHIGH(31), + OE=>AHIGH_31X_OE ); + IN_A_DECODE_23_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_23XPIN, + I0=>A_DECODE(23) ); + IN_IPL_2_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>IPL_2XPIN, + I0=>IPL(2) ); + IN_FC_1_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>FC_1XPIN, + I0=>FC(1) ); + OUT_AS_030_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AS_030PIN, + I0=>AS_030COM, + IO=>AS_030, + OE=>AS_030_OE ); + OUT_AS_000_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AS_000PIN, + I0=>AS_000COM, + IO=>AS_000, + OE=>AS_000_OE ); + OUT_DS_030_I_1: BUFTH port map ( I0=>DS_030COM, + O=>DS_030, + OE=>DS_030_OE ); + OUT_UDS_000_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>UDS_000PIN, + I0=>UDS_000COM, + IO=>UDS_000, + OE=>UDS_000_OE ); + OUT_LDS_000_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>LDS_000PIN, + I0=>LDS_000COM, + IO=>LDS_000, + OE=>LDS_000_OE ); + IN_nEXP_SPACE_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>nEXP_SPACEPIN, + I0=>nEXP_SPACE ); + OUT_BERR_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>BERRPIN, + I0=>GND_net, + IO=>BERR, + OE=>BERR_OE ); + IN_BG_030_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>BG_030PIN, + I0=>BG_030 ); + OUT_SIZE_0_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>SIZE_0XPIN, + I0=>SIZE_0XCOM, + IO=>SIZE(0), + OE=>SIZE_0X_OE ); + OUT_AHIGH_30_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_30XPIN, + I0=>GND_net, + IO=>AHIGH(30), + OE=>AHIGH_30X_OE ); + IN_BGACK_000_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>BGACK_000PIN, + I0=>BGACK_000 ); + OUT_AHIGH_29_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_29XPIN, + I0=>GND_net, + IO=>AHIGH(29), + OE=>AHIGH_29X_OE ); + IN_CLK_030_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>CLK_030PIN, + I0=>CLK_030 ); + OUT_AHIGH_28_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_28XPIN, + I0=>GND_net, + IO=>AHIGH(28), + OE=>AHIGH_28X_OE ); + IN_CLK_000_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>CLK_000PIN, + I0=>CLK_000 ); + OUT_AHIGH_27_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_27XPIN, + I0=>GND_net, + IO=>AHIGH(27), + OE=>AHIGH_27X_OE ); + IN_CLK_OSZI_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>CLK_OSZIPIN, + I0=>CLK_OSZI ); + OUT_AHIGH_26_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_26XPIN, + I0=>GND_net, + IO=>AHIGH(26), + OE=>AHIGH_26X_OE ); + OUT_CLK_DIV_OUT_I_1: OBUF port map ( O=>CLK_DIV_OUT, + I0=>CLK_DIV_OUTQ ); + OUT_AHIGH_25_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_25XPIN, + I0=>GND_net, + IO=>AHIGH(25), + OE=>AHIGH_25X_OE ); + OUT_AHIGH_24_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>AHIGH_24XPIN, + I0=>GND_net, + IO=>AHIGH(24), + OE=>AHIGH_24X_OE ); + OUT_FPU_CS_I_1: OBUF port map ( O=>FPU_CS, + I0=>FPU_CSCOM ); + IN_A_DECODE_22_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_22XPIN, + I0=>A_DECODE(22) ); + IN_FPU_SENSE_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>FPU_SENSEPIN, + I0=>FPU_SENSE ); + IN_A_DECODE_21_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_21XPIN, + I0=>A_DECODE(21) ); + IN_A_DECODE_20_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_20XPIN, + I0=>A_DECODE(20) ); + IN_DTACK_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>DTACKPIN, + I0=>DTACK ); + IN_A_DECODE_19_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_19XPIN, + I0=>A_DECODE(19) ); + OUT_AVEC_I_1: OBUF port map ( O=>AVEC, + I0=>VCC_net ); + IN_A_DECODE_18_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_18XPIN, + I0=>A_DECODE(18) ); + OUT_E_I_1: OBUF port map ( O=>E, + I0=>ECOM ); + IN_A_DECODE_17_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_17XPIN, + I0=>A_DECODE(17) ); + IN_VPA_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>VPAPIN, + I0=>VPA ); + IN_A_DECODE_16_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_DECODE_16XPIN, + I0=>A_DECODE(16) ); + IN_RST_I_1: IBUF + generic map( PULL => "Up") + port map ( O=>RSTPIN, + I0=>RST ); + OUT_RESET_I_1: BUFTH port map ( I0=>GND_net, + O=>RESET, + OE=>RESET_OE ); + OUT_AMIGA_ADDR_ENABLE_I_1: OBUF port map ( O=>AMIGA_ADDR_ENABLE, + I0=>GND_net ); + OUT_AMIGA_BUS_DATA_DIR_I_1: OBUF port map ( O=>AMIGA_BUS_DATA_DIR, + I0=>AMIGA_BUS_DATA_DIRCOM ); + OUT_AMIGA_BUS_ENABLE_LOW_I_1: OBUF port map ( O=>AMIGA_BUS_ENABLE_LOW, + I0=>AMIGA_BUS_ENABLE_LOWCOM ); + OUT_AMIGA_BUS_ENABLE_HIGH_I_1: OBUF port map ( O=>AMIGA_BUS_ENABLE_HIGH, + I0=>AMIGA_BUS_ENABLE_HIGHCOM ); + OUT_CIIN_I_1: BUFTH port map ( I0=>CIINCOM, + O=>CIIN, + OE=>CIIN_OE ); + IN_IPL_1_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>IPL_1XPIN, + I0=>IPL(1) ); + IN_IPL_0_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>IPL_0XPIN, + I0=>IPL(0) ); + IN_FC_0_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>FC_0XPIN, + I0=>FC(0) ); + IN_A_1_XI_1: IBUF + generic map( PULL => "Up") + port map ( O=>A_1XPIN, + I0=>A(1) ); + OUT_IPL_030_2_XI_1: OBUF port map ( O=>IPL_030(2), + I0=>IPL_030_2XQ ); + OUT_RW_000_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>RW_000PIN, + I0=>RW_000Q, + IO=>RW_000, + OE=>RW_000_OE ); + OUT_BG_000_I_1: OBUF port map ( O=>BG_000, + I0=>BG_000Q ); + OUT_BGACK_030_I_1: OBUF port map ( O=>BGACK_030, + I0=>BGACK_030Q ); + OUT_CLK_EXP_I_1: OBUF port map ( O=>CLK_EXP, + I0=>CLK_EXPQ ); + OUT_DSACK1_I_1: BUFTH port map ( I0=>DSACK1Q, + O=>DSACK1, + OE=>nEXP_SPACEPIN ); + OUT_VMA_I_1: OBUF port map ( O=>VMA, + I0=>VMAQ ); + OUT_RW_I_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>RWPIN, + I0=>RWQ, + IO=>RW, + OE=>RW_OE ); + OUT_A_0_XI_1: BI_DIR + generic map( PULL => "Up") + port map ( O=>A_0XPIN, + I0=>A_0XQ, + IO=>A(0), + OE=>A_0X_OE ); + OUT_IPL_030_1_XI_1: OBUF port map ( O=>IPL_030(1), + I0=>IPL_030_1XQ ); + OUT_IPL_030_0_XI_1: OBUF port map ( O=>IPL_030(0), + I0=>IPL_030_0XQ ); + FF_CLK_DIV_OUT_I_1: DFF port map ( D=>inst_CLK_OUT_PRE_DQ, + Q=>CLK_DIV_OUTQ, + CLK=>CLK_OSZIPIN ); + FF_IPL_030_2_XI_1: DFF port map ( D=>IPL_030_2X_D, + Q=>IPL_030_2XQ, + CLK=>CLK_OSZIPIN ); + FF_RW_000_I_1: DFF port map ( D=>RW_000_D, + Q=>RW_000Q, + CLK=>CLK_OSZIPIN ); + FF_BG_000_I_1: DFF port map ( D=>BG_000_D, + Q=>BG_000Q, + CLK=>CLK_OSZIPIN ); + FF_BGACK_030_I_1: DFF port map ( D=>BGACK_030_D, + Q=>BGACK_030Q, + CLK=>CLK_OSZIPIN ); + FF_CLK_EXP_I_1: DFF port map ( D=>inst_CLK_OUT_PRE_DQ, + Q=>CLK_EXPQ, + CLK=>CLK_OSZIPIN ); + FF_DSACK1_I_1: DFF port map ( D=>DSACK1_D, + Q=>DSACK1Q, + CLK=>CLK_OSZIPIN ); + FF_VMA_I_1: TFF port map ( T=>VMA_T, + Q=>VMAQ, + CLK=>CLK_OSZIPIN ); + FF_RW_I_1: DFF port map ( D=>RW_D, + Q=>RWQ, + CLK=>CLK_OSZIPIN ); + FF_A_0_XI_1: DFF port map ( D=>A_0X_D, + Q=>A_0XQ, + CLK=>CLK_OSZIPIN ); + FF_IPL_030_1_XI_1: DFF port map ( D=>IPL_030_1X_D, + Q=>IPL_030_1XQ, + CLK=>CLK_OSZIPIN ); + FF_IPL_030_0_XI_1: DFF port map ( D=>IPL_030_0X_D, + Q=>IPL_030_0XQ, + CLK=>CLK_OSZIPIN ); + FF_cpu_est_3_bus_I_1: DFF port map ( D=>cpu_est_3_bus_D, + Q=>cpu_est_3_busQ, + CLK=>CLK_OSZIPIN ); + FF_cpu_est_0_bus_I_1: DFF port map ( D=>cpu_est_0_bus_D, + Q=>cpu_est_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_cpu_est_1_bus_I_1: DFF port map ( D=>cpu_est_1_bus_D, + Q=>cpu_est_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_cpu_est_2_bus_I_1: DFF port map ( D=>cpu_est_2_bus_D, + Q=>cpu_est_2_busQ, + CLK=>CLK_OSZIPIN ); + FF_inst_AS_000_INT_I_1: DFF port map ( D=>inst_AS_000_INT_D, + Q=>inst_AS_000_INTQ, + CLK=>CLK_OSZIPIN ); + FF_inst_AMIGA_BUS_ENABLE_DMA_LOW_I_1: DFF port map ( D=>inst_AMIGA_BUS_ENABLE_DMA_LOW_D, + Q=>inst_AMIGA_BUS_ENABLE_DMA_LOWQ, + CLK=>CLK_OSZIPIN ); + FF_inst_AS_030_D0_I_1: DFF port map ( D=>inst_AS_030_D0_D, + Q=>inst_AS_030_D0Q, + CLK=>CLK_OSZIPIN ); + FF_inst_AS_030_000_SYNC_I_1: DFF port map ( D=>inst_AS_030_000_SYNC_D, + Q=>inst_AS_030_000_SYNCQ, + CLK=>CLK_OSZIPIN ); + FF_inst_BGACK_030_INT_D_I_1: DFF port map ( D=>inst_BGACK_030_INT_D_D, + Q=>inst_BGACK_030_INT_DQ, + CLK=>CLK_OSZIPIN ); + FF_inst_AS_000_DMA_I_1: DFF port map ( D=>inst_AS_000_DMA_D, + Q=>inst_AS_000_DMAQ, + CLK=>CLK_OSZIPIN ); + FF_inst_DS_000_DMA_I_1: DFF port map ( D=>inst_DS_000_DMA_D, + Q=>inst_DS_000_DMAQ, + CLK=>CLK_OSZIPIN ); + FF_CYCLE_DMA_0_bus_I_1: DFF port map ( D=>CYCLE_DMA_0_bus_D, + Q=>CYCLE_DMA_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_CYCLE_DMA_1_bus_I_1: DFF port map ( D=>CYCLE_DMA_1_bus_D, + Q=>CYCLE_DMA_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_SIZE_DMA_0_bus_I_1: DFF port map ( D=>SIZE_DMA_0_bus_D, + Q=>SIZE_DMA_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_SIZE_DMA_1_bus_I_1: DFF port map ( D=>SIZE_DMA_1_bus_D, + Q=>SIZE_DMA_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_inst_VPA_D_I_1: DFF port map ( D=>inst_VPA_D_D, + Q=>inst_VPA_DQ, + CLK=>CLK_OSZIPIN ); + FF_inst_UDS_000_INT_I_1: DFF port map ( D=>inst_UDS_000_INT_D, + Q=>inst_UDS_000_INTQ, + CLK=>CLK_OSZIPIN ); + FF_inst_LDS_000_INT_I_1: DFF port map ( D=>inst_LDS_000_INT_D, + Q=>inst_LDS_000_INTQ, + CLK=>CLK_OSZIPIN ); + FF_inst_CLK_OUT_PRE_D_I_1: DFF port map ( D=>inst_CLK_OUT_PRE_50Q, + Q=>inst_CLK_OUT_PRE_DQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_1_bus_I_1: DFF port map ( D=>CLK_000_D_0_busQ, + Q=>CLK_000_D_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_10_bus_I_1: DFF port map ( D=>CLK_000_D_9_busQ, + Q=>CLK_000_D_10_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_11_bus_I_1: DFF port map ( D=>CLK_000_D_10_busQ, + Q=>CLK_000_D_11_busQ, + CLK=>CLK_OSZIPIN ); + FF_inst_DTACK_D0_I_1: DFF port map ( D=>inst_DTACK_D0_D, + Q=>inst_DTACK_D0Q, + CLK=>CLK_OSZIPIN ); + FF_inst_RESET_OUT_I_1: DFF port map ( D=>inst_RESET_OUT_D, + Q=>inst_RESET_OUTQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_0_bus_I_1: DFF port map ( D=>CLK_000PIN, + Q=>CLK_000_D_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_inst_CLK_OUT_PRE_50_I_1: DFF port map ( D=>inst_CLK_OUT_PRE_50_D, + Q=>inst_CLK_OUT_PRE_50Q, + CLK=>CLK_OSZIPIN ); + FF_IPL_D0_0_bus_I_1: DFF port map ( D=>IPL_D0_0_bus_D, + Q=>IPL_D0_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_IPL_D0_1_bus_I_1: DFF port map ( D=>IPL_D0_1_bus_D, + Q=>IPL_D0_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_IPL_D0_2_bus_I_1: DFF port map ( D=>IPL_D0_2_bus_D, + Q=>IPL_D0_2_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_2_bus_I_1: DFF port map ( D=>CLK_000_D_1_busQ, + Q=>CLK_000_D_2_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_3_bus_I_1: DFF port map ( D=>CLK_000_D_2_busQ, + Q=>CLK_000_D_3_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_4_bus_I_1: DFF port map ( D=>CLK_000_D_3_busQ, + Q=>CLK_000_D_4_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_5_bus_I_1: DFF port map ( D=>CLK_000_D_4_busQ, + Q=>CLK_000_D_5_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_6_bus_I_1: DFF port map ( D=>CLK_000_D_5_busQ, + Q=>CLK_000_D_6_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_7_bus_I_1: DFF port map ( D=>CLK_000_D_6_busQ, + Q=>CLK_000_D_7_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_8_bus_I_1: DFF port map ( D=>CLK_000_D_7_busQ, + Q=>CLK_000_D_8_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_9_bus_I_1: DFF port map ( D=>CLK_000_D_8_busQ, + Q=>CLK_000_D_9_busQ, + CLK=>CLK_OSZIPIN ); + FF_CLK_000_D_12_bus_I_1: DFF port map ( D=>CLK_000_D_11_busQ, + Q=>CLK_000_D_12_busQ, + CLK=>CLK_OSZIPIN ); + FF_inst_AMIGA_BUS_ENABLE_DMA_HIGH_I_1: DFF port map ( D=>inst_AMIGA_BUS_ENABLE_DMA_HIGH_D, + Q=>inst_AMIGA_BUS_ENABLE_DMA_HIGHQ, + CLK=>CLK_OSZIPIN ); + FF_inst_DS_000_ENABLE_I_1: DFF port map ( D=>inst_DS_000_ENABLE_D, + Q=>inst_DS_000_ENABLEQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_6_bus_I_1: DFF port map ( D=>SM_AMIGA_6_bus_D, + Q=>SM_AMIGA_6_busQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_0_bus_I_1: DFF port map ( D=>SM_AMIGA_0_bus_D, + Q=>SM_AMIGA_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_4_bus_I_1: DFF port map ( D=>SM_AMIGA_4_bus_D, + Q=>SM_AMIGA_4_busQ, + CLK=>CLK_OSZIPIN ); + FF_RST_DLY_0_bus_I_1: DFF port map ( D=>RST_DLY_0_bus_D, + Q=>RST_DLY_0_busQ, + CLK=>CLK_OSZIPIN ); + FF_RST_DLY_1_bus_I_1: DFF port map ( D=>RST_DLY_1_bus_D, + Q=>RST_DLY_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_RST_DLY_2_bus_I_1: DFF port map ( D=>RST_DLY_2_bus_D, + Q=>RST_DLY_2_busQ, + CLK=>CLK_OSZIPIN ); + FF_inst_CLK_030_H_I_1: DFF port map ( D=>inst_CLK_030_H_D, + Q=>inst_CLK_030_HQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_1_bus_I_1: DFF port map ( D=>SM_AMIGA_1_bus_D, + Q=>SM_AMIGA_1_busQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_5_bus_I_1: DFF port map ( D=>SM_AMIGA_5_bus_D, + Q=>SM_AMIGA_5_busQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_3_bus_I_1: DFF port map ( D=>SM_AMIGA_3_bus_D, + Q=>SM_AMIGA_3_busQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_2_bus_I_1: DFF port map ( D=>SM_AMIGA_2_bus_D, + Q=>SM_AMIGA_2_busQ, + CLK=>CLK_OSZIPIN ); + FF_SM_AMIGA_i_7_bus_I_1: DFF port map ( D=>SM_AMIGA_i_7_bus_D, + Q=>SM_AMIGA_i_7_busQ, + CLK=>CLK_OSZIPIN ); + GATE_SIZE_1_XI_1: AND2 port map ( O=>SIZE_1XCOM, + I1=>SIZE_DMA_1_busQ, + I0=>GATE_SIZE_1_XA ); + GATE_SIZE_1_XI_2: INV port map ( O=>GATE_SIZE_1_XA, + I0=>SIZE_DMA_0_busQ ); + GATE_SIZE_1X_OE_I_1: NOR2 port map ( O=>SIZE_1X_OE, + I1=>BGACK_030Q, + I0=>nEXP_SPACEPIN ); + GATE_AHIGH_31X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_31X_OE_A ); + GATE_AHIGH_31X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_31X_OE_B ); + GATE_AHIGH_31X_OE_I_3: AND3 port map ( O=>AHIGH_31X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_31X_OE_A, + I1=>GATE_AHIGH_31X_OE_B ); + GATE_T_0_I_1: NOR2 port map ( O=>T_0, + I1=>AS_000PIN, + I0=>inst_AS_000_DMAQ ); + GATE_AS_030_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AS_030_OE_A ); + GATE_AS_030_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AS_030_OE_B ); + GATE_AS_030_OE_I_3: AND3 port map ( O=>AS_030_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AS_030_OE_A, + I1=>GATE_AS_030_OE_B ); + GATE_T_1_I_1: NOR2 port map ( O=>T_1, + I1=>AS_030PIN, + I0=>inst_AS_000_INTQ ); + GATE_AS_000_OE_I_1: AND2 port map ( O=>AS_000_OE, + I1=>inst_RESET_OUTQ, + I0=>BGACK_030Q ); + GATE_T_2_I_1: NOR2 port map ( O=>T_2, + I1=>AS_000PIN, + I0=>inst_DS_000_DMAQ ); + GATE_DS_030_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_DS_030_OE_A ); + GATE_DS_030_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_DS_030_OE_B ); + GATE_DS_030_OE_I_3: AND3 port map ( O=>DS_030_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_DS_030_OE_A, + I1=>GATE_DS_030_OE_B ); + GATE_T_3_I_1: AND2 port map ( O=>T_3, + I1=>inst_DS_000_ENABLEQ, + I0=>GATE_T_3_A ); + GATE_T_3_I_2: INV port map ( O=>GATE_T_3_A, + I0=>inst_UDS_000_INTQ ); + GATE_UDS_000_OE_I_1: AND2 port map ( O=>UDS_000_OE, + I1=>inst_RESET_OUTQ, + I0=>BGACK_030Q ); + GATE_T_4_I_1: AND2 port map ( O=>T_4, + I1=>inst_DS_000_ENABLEQ, + I0=>GATE_T_4_A ); + GATE_T_4_I_2: INV port map ( O=>GATE_T_4_A, + I0=>inst_LDS_000_INTQ ); + GATE_LDS_000_OE_I_1: AND2 port map ( O=>LDS_000_OE, + I1=>inst_RESET_OUTQ, + I0=>BGACK_030Q ); + GATE_BERR_OE_I_1: AND3 port map ( O=>BERR_OE, + I2=>T_429, + I1=>T_430, + I0=>T_428 ); + GATE_SIZE_0_XI_1: AND2 port map ( O=>SIZE_0XCOM, + I1=>SIZE_DMA_0_busQ, + I0=>GATE_SIZE_0_XA ); + GATE_SIZE_0_XI_2: INV port map ( O=>GATE_SIZE_0_XA, + I0=>SIZE_DMA_1_busQ ); + GATE_SIZE_0X_OE_I_1: NOR2 port map ( O=>SIZE_0X_OE, + I1=>BGACK_030Q, + I0=>nEXP_SPACEPIN ); + GATE_AHIGH_30X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_30X_OE_A ); + GATE_AHIGH_30X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_30X_OE_B ); + GATE_AHIGH_30X_OE_I_3: AND3 port map ( O=>AHIGH_30X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_30X_OE_A, + I1=>GATE_AHIGH_30X_OE_B ); + GATE_AHIGH_29X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_29X_OE_A ); + GATE_AHIGH_29X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_29X_OE_B ); + GATE_AHIGH_29X_OE_I_3: AND3 port map ( O=>AHIGH_29X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_29X_OE_A, + I1=>GATE_AHIGH_29X_OE_B ); + GATE_AHIGH_28X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_28X_OE_A ); + GATE_AHIGH_28X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_28X_OE_B ); + GATE_AHIGH_28X_OE_I_3: AND3 port map ( O=>AHIGH_28X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_28X_OE_A, + I1=>GATE_AHIGH_28X_OE_B ); + GATE_AHIGH_27X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_27X_OE_A ); + GATE_AHIGH_27X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_27X_OE_B ); + GATE_AHIGH_27X_OE_I_3: AND3 port map ( O=>AHIGH_27X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_27X_OE_A, + I1=>GATE_AHIGH_27X_OE_B ); + GATE_AHIGH_26X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_26X_OE_A ); + GATE_AHIGH_26X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_26X_OE_B ); + GATE_AHIGH_26X_OE_I_3: AND3 port map ( O=>AHIGH_26X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_26X_OE_A, + I1=>GATE_AHIGH_26X_OE_B ); + GATE_AHIGH_25X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_25X_OE_A ); + GATE_AHIGH_25X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_25X_OE_B ); + GATE_AHIGH_25X_OE_I_3: AND3 port map ( O=>AHIGH_25X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_25X_OE_A, + I1=>GATE_AHIGH_25X_OE_B ); + GATE_AHIGH_24X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_AHIGH_24X_OE_A ); + GATE_AHIGH_24X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_AHIGH_24X_OE_B ); + GATE_AHIGH_24X_OE_I_3: AND3 port map ( O=>AHIGH_24X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_AHIGH_24X_OE_A, + I1=>GATE_AHIGH_24X_OE_B ); + GATE_T_5_I_1: AND3 port map ( O=>T_5, + I2=>T_426, + I1=>T_427, + I0=>T_425 ); + GATE_E_I_1: OR2 port map ( O=>ECOM, + I1=>T_190, + I0=>T_189 ); + GATE_RESET_OE_I_1: INV port map ( I0=>inst_RESET_OUTQ, + O=>RESET_OE ); + GATE_AMIGA_BUS_DATA_DIR_I_1: OR2 port map ( O=>AMIGA_BUS_DATA_DIRCOM, + I1=>T_188, + I0=>T_187 ); + GATE_T_6_I_1: NOR2 port map ( O=>T_6, + I1=>inst_AMIGA_BUS_ENABLE_DMA_LOWQ, + I0=>BGACK_030Q ); + GATE_AMIGA_BUS_ENABLE_HIGH_I_1: OR2 port map ( O=>AMIGA_BUS_ENABLE_HIGHCOM, + I1=>T_186, + I0=>T_185 ); + GATE_CIIN_I_1: AND4 port map ( O=>CIINCOM, + I3=>T_422, + I2=>T_423, + I1=>T_424, + I0=>GATE_CIIN_A ); + GATE_CIIN_I_2: INV port map ( I0=>AHIGH_31XPIN, + O=>GATE_CIIN_A ); + GATE_T_7_I_1: OR4 port map ( I0=>T_183, + I1=>T_406, + O=>T_7, + I2=>T_405, + I3=>T_404 ); + GATE_T_8_I_1: OR4 port map ( I0=>T_170, + I1=>T_171, + O=>T_8, + I2=>T_172, + I3=>T_173 ); + GATE_RW_000_OE_I_1: AND2 port map ( O=>RW_000_OE, + I1=>inst_RESET_OUTQ, + I0=>BGACK_030Q ); + GATE_T_9_I_1: OR2 port map ( O=>T_9, + I1=>T_169, + I0=>T_168 ); + GATE_BGACK_030_D_I_3: NAN3 port map ( O=>BGACK_030_D, + I2=>RSTPIN, + I1=>GATE_BGACK_030_D_B, + I0=>GATE_BGACK_030_D_A ); + GATE_BGACK_030_D_I_2: INV port map ( I0=>T_166, + O=>GATE_BGACK_030_D_B ); + GATE_BGACK_030_D_I_1: INV port map ( I0=>T_167, + O=>GATE_BGACK_030_D_A ); + GATE_T_10_I_1: OR4 port map ( I0=>T_162, + I1=>T_163, + O=>T_10, + I2=>T_164, + I3=>T_165 ); + GATE_VMA_T_I_1: OR3 port map ( O=>VMA_T, + I2=>T_160, + I1=>T_159, + I0=>T_161 ); + GATE_T_11_I_1: OR2 port map ( O=>T_11, + I1=>T_158, + I0=>T_157 ); + GATE_RW_OE_I_1: AND2 port map ( O=>RW_OE, + I1=>inst_RESET_OUTQ, + I0=>GATE_RW_OE_A ); + GATE_RW_OE_I_2: INV port map ( O=>GATE_RW_OE_A, + I0=>BGACK_030Q ); + GATE_A_0X_D_I_3: NAN3 port map ( O=>A_0X_D, + I2=>RSTPIN, + I1=>GATE_A_0X_D_B, + I0=>GATE_A_0X_D_A ); + GATE_A_0X_D_I_2: INV port map ( I0=>T_155, + O=>GATE_A_0X_D_B ); + GATE_A_0X_D_I_1: INV port map ( I0=>T_156, + O=>GATE_A_0X_D_A ); + GATE_A_0X_OE_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_A_0X_OE_A ); + GATE_A_0X_OE_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_A_0X_OE_B ); + GATE_A_0X_OE_I_3: AND3 port map ( O=>A_0X_OE, + I0=>inst_RESET_OUTQ, + I2=>GATE_A_0X_OE_A, + I1=>GATE_A_0X_OE_B ); + GATE_T_12_I_1: OR4 port map ( I0=>T_154, + I1=>T_374, + O=>T_12, + I2=>T_373, + I3=>T_372 ); + GATE_T_13_I_1: OR4 port map ( I0=>T_144, + I1=>T_359, + O=>T_13, + I2=>T_358, + I3=>T_357 ); + GATE_cpu_est_3_bus_D_I_1: OR4 port map ( I0=>T_131, + I1=>T_132, + O=>cpu_est_3_bus_D, + I2=>T_133, + I3=>T_134 ); + GATE_cpu_est_0_bus_D_I_1: OR3 port map ( O=>cpu_est_0_bus_D, + I2=>T_129, + I1=>T_128, + I0=>T_130 ); + GATE_cpu_est_1_bus_D_I_1: OR4 port map ( I0=>T_124, + I1=>T_125, + O=>cpu_est_1_bus_D, + I2=>T_126, + I3=>T_127 ); + GATE_cpu_est_2_bus_D_X1_I_1: AND4 port map ( O=>cpu_est_2_bus_D_X1, + I3=>cpu_est_1_busQ, + I2=>cpu_est_0_busQ, + I1=>CLK_000_D_1_busQ, + I0=>GATE_cpu_est_2_bus_D_X1_A ); + GATE_cpu_est_2_bus_D_X1_I_2: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_cpu_est_2_bus_D_X1_A ); + GATE_T_14_I_1: OR2 port map ( O=>T_14, + I1=>T_123, + I0=>T_122 ); + GATE_T_15_I_1: OR2 port map ( O=>T_15, + I1=>T_121, + I0=>T_120 ); + GATE_T_16_I_1: AND2 port map ( O=>T_16, + I1=>RSTPIN, + I0=>GATE_T_16_A ); + GATE_T_16_I_2: INV port map ( O=>GATE_T_16_A, + I0=>AS_030PIN ); + GATE_T_17_I_1: OR4 port map ( I0=>T_119, + I1=>T_328, + O=>T_17, + I2=>T_327, + I3=>T_326 ); + GATE_T_18_I_1: AND2 port map ( O=>T_18, + I1=>RSTPIN, + I0=>GATE_T_18_A ); + GATE_T_18_I_2: INV port map ( O=>GATE_T_18_A, + I0=>BGACK_030Q ); + GATE_inst_AS_000_DMA_D_I_1: NAN4 port map ( I3=>RSTPIN, + O=>inst_AS_000_DMA_D, + I2=>GATE_inst_AS_000_DMA_D_C, + I1=>GATE_inst_AS_000_DMA_D_B, + I0=>GATE_inst_AS_000_DMA_D_A ); + GATE_inst_AS_000_DMA_D_I_2: INV port map ( I0=>T_324, + O=>GATE_inst_AS_000_DMA_D_A ); + GATE_inst_AS_000_DMA_D_I_3: INV port map ( I0=>T_323, + O=>GATE_inst_AS_000_DMA_D_B ); + GATE_inst_AS_000_DMA_D_I_4: INV port map ( I0=>T_325, + O=>GATE_inst_AS_000_DMA_D_C ); + GATE_inst_DS_000_DMA_D_I_1: OR3 port map ( O=>inst_DS_000_DMA_D, + I2=>T_321, + I1=>T_322, + I0=>T_320 ); + GATE_CYCLE_DMA_0_bus_D_I_1: OR3 port map ( O=>CYCLE_DMA_0_bus_D, + I2=>T_101, + I1=>T_100, + I0=>T_102 ); + GATE_CYCLE_DMA_1_bus_D_I_1: OR4 port map ( I0=>T_96, + I1=>T_97, + O=>CYCLE_DMA_1_bus_D, + I2=>T_98, + I3=>T_99 ); + GATE_T_19_I_1: OR3 port map ( O=>T_19, + I2=>T_94, + I1=>T_93, + I0=>T_95 ); + GATE_SIZE_DMA_1_bus_D_I_3: NAN3 port map ( O=>SIZE_DMA_1_bus_D, + I2=>RSTPIN, + I1=>GATE_SIZE_DMA_1_bus_D_B, + I0=>GATE_SIZE_DMA_1_bus_D_A ); + GATE_SIZE_DMA_1_bus_D_I_2: INV port map ( I0=>T_91, + O=>GATE_SIZE_DMA_1_bus_D_B ); + GATE_SIZE_DMA_1_bus_D_I_1: INV port map ( I0=>T_92, + O=>GATE_SIZE_DMA_1_bus_D_A ); + GATE_T_20_I_1: AND2 port map ( O=>T_20, + I1=>RSTPIN, + I0=>GATE_T_20_A ); + GATE_T_20_I_2: INV port map ( O=>GATE_T_20_A, + I0=>VPAPIN ); + GATE_T_21_I_1: OR2 port map ( O=>T_21, + I1=>T_90, + I0=>T_89 ); + GATE_inst_LDS_000_INT_D_I_3: NAN3 port map ( O=>inst_LDS_000_INT_D, + I2=>RSTPIN, + I1=>GATE_inst_LDS_000_INT_D_B, + I0=>GATE_inst_LDS_000_INT_D_A ); + GATE_inst_LDS_000_INT_D_I_2: INV port map ( I0=>T_87, + O=>GATE_inst_LDS_000_INT_D_B ); + GATE_inst_LDS_000_INT_D_I_1: INV port map ( I0=>T_88, + O=>GATE_inst_LDS_000_INT_D_A ); + GATE_T_22_I_1: AND2 port map ( O=>T_22, + I1=>RSTPIN, + I0=>GATE_T_22_A ); + GATE_T_22_I_2: INV port map ( O=>GATE_T_22_A, + I0=>DTACKPIN ); + GATE_inst_RESET_OUT_D_I_1: OR2 port map ( O=>inst_RESET_OUT_D, + I1=>T_86, + I0=>T_85 ); + GATE_inst_CLK_OUT_PRE_50_D_I_1: INV port map ( I0=>inst_CLK_OUT_PRE_50Q, + O=>inst_CLK_OUT_PRE_50_D ); + GATE_T_23_I_1: AND2 port map ( O=>T_23, + I1=>RSTPIN, + I0=>GATE_T_23_A ); + GATE_T_23_I_2: INV port map ( O=>GATE_T_23_A, + I0=>IPL_0XPIN ); + GATE_T_24_I_1: AND2 port map ( O=>T_24, + I1=>RSTPIN, + I0=>GATE_T_24_A ); + GATE_T_24_I_2: INV port map ( O=>GATE_T_24_A, + I0=>IPL_1XPIN ); + GATE_T_25_I_1: AND2 port map ( O=>T_25, + I1=>RSTPIN, + I0=>GATE_T_25_A ); + GATE_T_25_I_2: INV port map ( O=>GATE_T_25_A, + I0=>IPL_2XPIN ); + GATE_T_26_I_1: OR2 port map ( O=>T_26, + I1=>T_84, + I0=>T_83 ); + GATE_inst_DS_000_ENABLE_D_I_1: OR4 port map ( I0=>T_79, + I1=>T_80, + O=>inst_DS_000_ENABLE_D, + I2=>T_81, + I3=>T_82 ); + GATE_SM_AMIGA_6_bus_D_I_1: OR3 port map ( O=>SM_AMIGA_6_bus_D, + I2=>T_77, + I1=>T_76, + I0=>T_78 ); + GATE_SM_AMIGA_0_bus_D_I_1: OR3 port map ( O=>SM_AMIGA_0_bus_D, + I2=>T_74, + I1=>T_73, + I0=>T_75 ); + GATE_SM_AMIGA_4_bus_D_I_1: OR3 port map ( O=>SM_AMIGA_4_bus_D, + I2=>T_71, + I1=>T_70, + I0=>T_72 ); + GATE_RST_DLY_0_bus_D_I_1: OR4 port map ( I0=>T_66, + I1=>T_67, + O=>RST_DLY_0_bus_D, + I2=>T_68, + I3=>T_69 ); + GATE_RST_DLY_1_bus_D_X1_I_1: OR2 port map ( O=>RST_DLY_1_bus_D_X1, + I1=>T_45, + I0=>T_44 ); + GATE_RST_DLY_1_bus_D_X2_I_1: AND2 port map ( O=>RST_DLY_1_bus_D_X2, + I1=>RST_DLY_1_busQ, + I0=>RSTPIN ); + GATE_RST_DLY_2_bus_D_I_1: OR2 port map ( O=>RST_DLY_2_bus_D, + I1=>T_65, + I0=>T_64 ); + GATE_inst_CLK_030_H_D_I_1: OR4 port map ( I0=>T_254, + I1=>T_253, + O=>inst_CLK_030_H_D, + I2=>T_252, + I3=>T_251 ); + GATE_SM_AMIGA_1_bus_D_I_1: OR3 port map ( O=>SM_AMIGA_1_bus_D, + I2=>T_54, + I1=>T_53, + I0=>T_55 ); + GATE_SM_AMIGA_5_bus_D_I_1: OR3 port map ( O=>SM_AMIGA_5_bus_D, + I2=>T_51, + I1=>T_50, + I0=>T_52 ); + GATE_SM_AMIGA_3_bus_D_X1_I_1: OR4 port map ( I0=>T_40, + I1=>T_41, + O=>SM_AMIGA_3_bus_D_X1, + I2=>T_42, + I3=>T_43 ); + GATE_SM_AMIGA_3_bus_D_X2_I_1: AND3 port map ( O=>SM_AMIGA_3_bus_D_X2, + I2=>SM_AMIGA_3_busQ, + I1=>RSTPIN, + I0=>BERRPIN ); + GATE_SM_AMIGA_2_bus_D_I_1: OR4 port map ( I0=>T_46, + I1=>T_47, + O=>SM_AMIGA_2_bus_D, + I2=>T_48, + I3=>T_49 ); + GATE_SM_AMIGA_i_7_bus_D_X1_I_1: OR4 port map ( I0=>T_39, + I1=>T_193, + O=>SM_AMIGA_i_7_bus_D_X1, + I2=>T_192, + I3=>T_191 ); + GATE_SM_AMIGA_i_7_bus_D_X2_I_1: AND2 port map ( O=>SM_AMIGA_i_7_bus_D_X2, + I1=>BERRPIN, + I0=>RSTPIN ); + GATE_CIIN_OE_I_1: OR2 port map ( O=>CIIN_OE, + I1=>T_184, + I0=>nEXP_SPACEPIN ); + GATE_cpu_est_2_bus_D_I_1: XOR2 port map ( O=>cpu_est_2_bus_D, + I1=>cpu_est_2_bus_D_X1, + I0=>cpu_est_2_busQ ); + GATE_RST_DLY_1_bus_D_I_1: XOR2 port map ( O=>RST_DLY_1_bus_D, + I1=>RST_DLY_1_bus_D_X2, + I0=>RST_DLY_1_bus_D_X1 ); + GATE_SM_AMIGA_3_bus_D_I_1: XOR2 port map ( O=>SM_AMIGA_3_bus_D, + I1=>SM_AMIGA_3_bus_D_X2, + I0=>SM_AMIGA_3_bus_D_X1 ); + GATE_SM_AMIGA_i_7_bus_D_I_1: XOR2 port map ( O=>SM_AMIGA_i_7_bus_D, + I1=>SM_AMIGA_i_7_bus_D_X2, + I0=>SM_AMIGA_i_7_bus_D_X1 ); + GATE_AS_030_I_1: INV port map ( I0=>T_0, + O=>AS_030COM ); + GATE_AS_000_I_1: INV port map ( I0=>T_1, + O=>AS_000COM ); + GATE_DS_030_I_1: INV port map ( I0=>T_2, + O=>DS_030COM ); + GATE_UDS_000_I_1: INV port map ( I0=>T_3, + O=>UDS_000COM ); + GATE_LDS_000_I_1: INV port map ( I0=>T_4, + O=>LDS_000COM ); + GATE_FPU_CS_I_1: INV port map ( I0=>T_5, + O=>FPU_CSCOM ); + GATE_AMIGA_BUS_ENABLE_LOW_I_1: INV port map ( I0=>T_6, + O=>AMIGA_BUS_ENABLE_LOWCOM ); + GATE_IPL_030_2X_D_I_1: INV port map ( I0=>T_7, + O=>IPL_030_2X_D ); + GATE_RW_000_D_I_1: INV port map ( I0=>T_8, + O=>RW_000_D ); + GATE_BG_000_D_I_1: INV port map ( I0=>T_9, + O=>BG_000_D ); + GATE_DSACK1_D_I_1: INV port map ( I0=>T_10, + O=>DSACK1_D ); + GATE_RW_D_I_1: INV port map ( I0=>T_11, + O=>RW_D ); + GATE_IPL_030_1X_D_I_1: INV port map ( I0=>T_12, + O=>IPL_030_1X_D ); + GATE_IPL_030_0X_D_I_1: INV port map ( I0=>T_13, + O=>IPL_030_0X_D ); + GATE_inst_AS_000_INT_D_I_1: INV port map ( I0=>T_14, + O=>inst_AS_000_INT_D ); + GATE_inst_AMIGA_BUS_ENABLE_DMA_LOW_D_I_1: INV port map ( I0=>T_15, + O=>inst_AMIGA_BUS_ENABLE_DMA_LOW_D ); + GATE_inst_AS_030_D0_D_I_1: INV port map ( I0=>T_16, + O=>inst_AS_030_D0_D ); + GATE_inst_AS_030_000_SYNC_D_I_1: INV port map ( I0=>T_17, + O=>inst_AS_030_000_SYNC_D ); + GATE_inst_BGACK_030_INT_D_D_I_1: INV port map ( I0=>T_18, + O=>inst_BGACK_030_INT_D_D ); + GATE_SIZE_DMA_0_bus_D_I_1: INV port map ( I0=>T_19, + O=>SIZE_DMA_0_bus_D ); + GATE_inst_VPA_D_D_I_1: INV port map ( I0=>T_20, + O=>inst_VPA_D_D ); + GATE_inst_UDS_000_INT_D_I_1: INV port map ( I0=>T_21, + O=>inst_UDS_000_INT_D ); + GATE_inst_DTACK_D0_D_I_1: INV port map ( I0=>T_22, + O=>inst_DTACK_D0_D ); + GATE_IPL_D0_0_bus_D_I_1: INV port map ( I0=>T_23, + O=>IPL_D0_0_bus_D ); + GATE_IPL_D0_1_bus_D_I_1: INV port map ( I0=>T_24, + O=>IPL_D0_1_bus_D ); + GATE_IPL_D0_2_bus_D_I_1: INV port map ( I0=>T_25, + O=>IPL_D0_2_bus_D ); + GATE_inst_AMIGA_BUS_ENABLE_DMA_HIGH_D_I_1: INV port map ( I0=>T_26, + O=>inst_AMIGA_BUS_ENABLE_DMA_HIGH_D ); + GATE_T_27_I_1: AND4 port map ( O=>T_27, + I3=>T_227, + I2=>T_228, + I1=>T_229, + I0=>GATE_T_27_A ); + GATE_T_27_I_2: INV port map ( I0=>BERRPIN, + O=>GATE_T_27_A ); + GATE_T_28_I_1: AND4 port map ( O=>T_28, + I3=>T_223, + I2=>T_224, + I1=>T_225, + I0=>T_226 ); + GATE_T_29_I_1: AND4 port map ( O=>T_29, + I3=>T_219, + I2=>T_220, + I1=>T_221, + I0=>T_222 ); + GATE_T_30_I_1: AND4 port map ( O=>T_30, + I3=>T_216, + I2=>T_217, + I1=>T_218, + I0=>BERRPIN ); + GATE_T_31_I_1: AND4 port map ( O=>T_31, + I3=>T_213, + I2=>T_214, + I1=>T_215, + I0=>BERRPIN ); + GATE_T_32_I_1: AND4 port map ( O=>T_32, + I3=>T_210, + I2=>T_211, + I1=>T_212, + I0=>BERRPIN ); + GATE_T_33_I_1: AND4 port map ( O=>T_33, + I3=>T_207, + I2=>T_208, + I1=>T_209, + I0=>BERRPIN ); + GATE_T_34_I_1: AND4 port map ( O=>T_34, + I3=>T_204, + I2=>T_205, + I1=>T_206, + I0=>GATE_T_34_A ); + GATE_T_34_I_2: INV port map ( I0=>BERRPIN, + O=>GATE_T_34_A ); + GATE_T_35_I_1: INV port map ( I0=>BERRPIN, + O=>GATE_T_35_A ); + GATE_T_35_I_2: AND3 port map ( O=>T_35, + I2=>T_203, + I1=>T_202, + I0=>GATE_T_35_A ); + GATE_T_36_I_1: INV port map ( I0=>BERRPIN, + O=>GATE_T_36_A ); + GATE_T_36_I_2: AND3 port map ( O=>T_36, + I2=>T_201, + I1=>T_200, + I0=>GATE_T_36_A ); + GATE_T_37_I_1: INV port map ( I0=>BERRPIN, + O=>GATE_T_37_A ); + GATE_T_37_I_2: AND3 port map ( O=>T_37, + I2=>T_199, + I1=>T_198, + I0=>GATE_T_37_A ); + GATE_T_38_I_1: INV port map ( I0=>BERRPIN, + O=>GATE_T_38_A ); + GATE_T_38_I_2: AND3 port map ( O=>T_38, + I2=>T_197, + I1=>T_196, + I0=>GATE_T_38_A ); + GATE_T_39_I_1: INV port map ( I0=>BERRPIN, + O=>GATE_T_39_A ); + GATE_T_39_I_2: AND3 port map ( O=>T_39, + I2=>T_195, + I1=>T_194, + I0=>GATE_T_39_A ); + GATE_T_40_I_1: AND4 port map ( O=>T_40, + I3=>T_237, + I2=>T_238, + I1=>T_239, + I0=>T_240 ); + GATE_T_41_I_1: AND4 port map ( O=>T_41, + I3=>T_234, + I2=>T_235, + I1=>T_236, + I0=>BERRPIN ); + GATE_T_42_I_1: INV port map ( I0=>BERRPIN, + O=>GATE_T_42_A ); + GATE_T_42_I_2: AND3 port map ( O=>T_42, + I2=>T_233, + I1=>T_232, + I0=>GATE_T_42_A ); + GATE_T_43_I_1: INV port map ( I0=>SM_AMIGA_3_busQ, + O=>GATE_T_43_A ); + GATE_T_43_I_2: AND3 port map ( O=>T_43, + I2=>T_231, + I1=>T_230, + I0=>GATE_T_43_A ); + GATE_T_44_I_1: INV port map ( I0=>RST_DLY_2_busQ, + O=>GATE_T_44_A ); + GATE_T_44_I_2: AND3 port map ( O=>T_44, + I2=>T_244, + I1=>T_243, + I0=>GATE_T_44_A ); + GATE_T_45_I_1: INV port map ( I0=>RST_DLY_1_busQ, + O=>GATE_T_45_A ); + GATE_T_45_I_2: AND3 port map ( O=>T_45, + I2=>T_242, + I1=>T_241, + I0=>GATE_T_45_A ); + GATE_T_46_I_1: AND4 port map ( O=>T_46, + I3=>T_248, + I2=>T_249, + I1=>T_250, + I0=>SM_AMIGA_3_busQ ); + GATE_T_47_I_1: AND3 port map ( O=>T_47, + I2=>T_246, + I1=>T_247, + I0=>T_245 ); + GATE_T_48_I_1: AND4 port map ( O=>T_48, + I3=>BERRPIN, + I2=>SM_AMIGA_2_busQ, + I1=>RSTPIN, + I0=>GATE_T_48_A ); + GATE_T_48_I_2: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_48_A ); + GATE_T_49_I_1: AND4 port map ( O=>T_49, + I3=>BERRPIN, + I2=>SM_AMIGA_2_busQ, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_50_I_1: AND4 port map ( O=>T_50, + I3=>BERRPIN, + I2=>SM_AMIGA_5_busQ, + I1=>CLK_000_D_0_busQ, + I0=>RSTPIN ); + GATE_T_51_I_1: AND4 port map ( O=>T_51, + I3=>BERRPIN, + I2=>SM_AMIGA_5_busQ, + I1=>RSTPIN, + I0=>GATE_T_51_A ); + GATE_T_51_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_51_A ); + GATE_T_52_I_1: AND4 port map ( O=>T_52, + I3=>SM_AMIGA_6_busQ, + I2=>CLK_000_D_0_busQ, + I1=>RSTPIN, + I0=>GATE_T_52_A ); + GATE_T_52_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_52_A ); + GATE_T_53_I_1: AND4 port map ( O=>T_53, + I3=>BERRPIN, + I2=>SM_AMIGA_1_busQ, + I1=>CLK_000_D_0_busQ, + I0=>RSTPIN ); + GATE_T_54_I_1: AND4 port map ( O=>T_54, + I3=>BERRPIN, + I2=>SM_AMIGA_1_busQ, + I1=>RSTPIN, + I0=>GATE_T_54_A ); + GATE_T_54_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_54_A ); + GATE_T_55_I_1: AND4 port map ( O=>T_55, + I3=>SM_AMIGA_2_busQ, + I2=>CLK_000_D_0_busQ, + I1=>RSTPIN, + I0=>GATE_T_55_A ); + GATE_T_55_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_55_A ); + GATE_T_56_I_1: AND4 port map ( O=>T_56, + I3=>T_279, + I2=>T_280, + I1=>T_281, + I0=>T_282 ); + GATE_T_57_I_1: AND4 port map ( O=>T_57, + I3=>T_275, + I2=>T_276, + I1=>T_277, + I0=>T_278 ); + GATE_T_58_I_1: AND4 port map ( O=>T_58, + I3=>T_271, + I2=>T_272, + I1=>T_273, + I0=>T_274 ); + GATE_T_59_I_1: AND4 port map ( O=>T_59, + I3=>T_267, + I2=>T_268, + I1=>T_269, + I0=>T_270 ); + GATE_T_60_I_1: AND4 port map ( O=>T_60, + I3=>T_264, + I2=>T_265, + I1=>T_266, + I0=>GATE_T_60_A ); + GATE_T_60_I_2: INV port map ( I0=>LDS_000PIN, + O=>GATE_T_60_A ); + GATE_T_61_I_1: AND4 port map ( O=>T_61, + I3=>T_261, + I2=>T_262, + I1=>T_263, + I0=>GATE_T_61_A ); + GATE_T_61_I_2: INV port map ( I0=>LDS_000PIN, + O=>GATE_T_61_A ); + GATE_T_62_I_1: AND4 port map ( O=>T_62, + I3=>T_258, + I2=>T_259, + I1=>T_260, + I0=>GATE_T_62_A ); + GATE_T_62_I_2: INV port map ( I0=>UDS_000PIN, + O=>GATE_T_62_A ); + GATE_T_63_I_1: AND4 port map ( O=>T_63, + I3=>T_255, + I2=>T_256, + I1=>T_257, + I0=>GATE_T_63_A ); + GATE_T_63_I_2: INV port map ( I0=>UDS_000PIN, + O=>GATE_T_63_A ); + GATE_T_64_I_1: AND3 port map ( O=>T_64, + I2=>T_284, + I1=>RST_DLY_1_busQ, + I0=>T_283 ); + GATE_T_65_I_1: AND2 port map ( O=>T_65, + I1=>RST_DLY_2_busQ, + I0=>RSTPIN ); + GATE_T_66_I_1: AND4 port map ( O=>T_66, + I3=>RST_DLY_2_busQ, + I2=>RST_DLY_1_busQ, + I1=>RST_DLY_0_busQ, + I0=>RSTPIN ); + GATE_T_67_I_3: AND4 port map ( O=>T_67, + I3=>CLK_000_D_1_busQ, + I2=>RSTPIN, + I1=>GATE_T_67_B, + I0=>GATE_T_67_A ); + GATE_T_67_I_2: INV port map ( I0=>RST_DLY_0_busQ, + O=>GATE_T_67_B ); + GATE_T_67_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_67_A ); + GATE_T_68_I_1: AND3 port map ( O=>T_68, + I2=>CLK_000_D_0_busQ, + I1=>RSTPIN, + I0=>RST_DLY_0_busQ ); + GATE_T_69_I_1: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_69_A ); + GATE_T_69_I_2: AND3 port map ( O=>T_69, + I2=>RSTPIN, + I1=>RST_DLY_0_busQ, + I0=>GATE_T_69_A ); + GATE_T_70_I_1: AND4 port map ( O=>T_70, + I3=>BERRPIN, + I2=>SM_AMIGA_4_busQ, + I1=>RSTPIN, + I0=>GATE_T_70_A ); + GATE_T_70_I_2: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_70_A ); + GATE_T_71_I_1: AND4 port map ( O=>T_71, + I3=>BERRPIN, + I2=>SM_AMIGA_4_busQ, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_72_I_1: AND4 port map ( O=>T_72, + I3=>CLK_000_D_1_busQ, + I2=>RSTPIN, + I1=>SM_AMIGA_5_busQ, + I0=>GATE_T_72_A ); + GATE_T_72_I_2: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_72_A ); + GATE_T_73_I_1: AND4 port map ( O=>T_73, + I3=>BERRPIN, + I2=>SM_AMIGA_0_busQ, + I1=>RSTPIN, + I0=>GATE_T_73_A ); + GATE_T_73_I_2: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_73_A ); + GATE_T_74_I_1: AND4 port map ( O=>T_74, + I3=>BERRPIN, + I2=>SM_AMIGA_0_busQ, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_75_I_1: AND4 port map ( O=>T_75, + I3=>CLK_000_D_1_busQ, + I2=>RSTPIN, + I1=>SM_AMIGA_1_busQ, + I0=>GATE_T_75_A ); + GATE_T_75_I_2: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_75_A ); + GATE_T_76_I_1: AND3 port map ( O=>T_76, + I2=>T_290, + I1=>T_291, + I0=>T_289 ); + GATE_T_77_I_1: AND3 port map ( O=>T_77, + I2=>T_288, + I1=>BERRPIN, + I0=>T_287 ); + GATE_T_78_I_1: AND3 port map ( O=>T_78, + I2=>T_286, + I1=>BERRPIN, + I0=>T_285 ); + GATE_T_79_I_1: AND4 port map ( O=>T_79, + I3=>T_298, + I2=>T_299, + I1=>T_300, + I0=>RWPIN ); + GATE_T_80_I_1: AND4 port map ( O=>T_80, + I3=>T_295, + I2=>T_296, + I1=>T_297, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_81_I_1: AND3 port map ( O=>T_81, + I2=>T_293, + I1=>T_294, + I0=>T_292 ); + GATE_T_82_I_1: AND4 port map ( O=>T_82, + I3=>BERRPIN, + I2=>inst_DS_000_ENABLEQ, + I1=>RSTPIN, + I0=>GATE_T_82_A ); + GATE_T_82_I_2: INV port map ( I0=>inst_AS_030_D0Q, + O=>GATE_T_82_A ); + GATE_T_83_I_1: AND4 port map ( O=>T_83, + I3=>BGACK_030Q, + I2=>RSTPIN, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_83_A ); + GATE_T_83_I_2: INV port map ( I0=>inst_AMIGA_BUS_ENABLE_DMA_HIGHQ, + O=>GATE_T_83_A ); + GATE_T_84_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_T_84_A ); + GATE_T_84_I_2: INV port map ( I0=>A_1XPIN, + O=>GATE_T_84_B ); + GATE_T_84_I_3: AND3 port map ( O=>T_84, + I0=>RSTPIN, + I2=>GATE_T_84_A, + I1=>GATE_T_84_B ); + GATE_T_85_I_1: AND3 port map ( O=>T_85, + I2=>T_302, + I1=>T_303, + I0=>T_301 ); + GATE_T_86_I_1: AND2 port map ( O=>T_86, + I1=>inst_RESET_OUTQ, + I0=>RSTPIN ); + GATE_T_87_I_3: AND4 port map ( O=>T_87, + I3=>SIZE_0XPIN, + I2=>SM_AMIGA_6_busQ, + I1=>GATE_T_87_B, + I0=>GATE_T_87_A ); + GATE_T_87_I_2: INV port map ( I0=>A_0XPIN, + O=>GATE_T_87_B ); + GATE_T_87_I_1: INV port map ( I0=>SIZE_1XPIN, + O=>GATE_T_87_A ); + GATE_T_88_I_1: AND2 port map ( O=>T_88, + I1=>inst_LDS_000_INTQ, + I0=>GATE_T_88_A ); + GATE_T_88_I_2: INV port map ( O=>GATE_T_88_A, + I0=>SM_AMIGA_6_busQ ); + GATE_T_89_I_1: INV port map ( I0=>A_0XPIN, + O=>GATE_T_89_A ); + GATE_T_89_I_2: AND3 port map ( O=>T_89, + I2=>SM_AMIGA_6_busQ, + I1=>RSTPIN, + I0=>GATE_T_89_A ); + GATE_T_90_I_1: INV port map ( I0=>SM_AMIGA_6_busQ, + O=>GATE_T_90_A ); + GATE_T_90_I_2: INV port map ( I0=>inst_UDS_000_INTQ, + O=>GATE_T_90_B ); + GATE_T_90_I_3: AND3 port map ( O=>T_90, + I0=>RSTPIN, + I2=>GATE_T_90_A, + I1=>GATE_T_90_B ); + GATE_T_91_I_1: NOR3 port map ( O=>T_91, + I2=>UDS_000PIN, + I1=>BGACK_030Q, + I0=>LDS_000PIN ); + GATE_T_92_I_1: AND3 port map ( O=>T_92, + I2=>inst_BGACK_030_INT_DQ, + I1=>BGACK_030Q, + I0=>SIZE_DMA_1_busQ ); + GATE_T_93_I_1: NOR4 port map ( I0=>UDS_000PIN, + I1=>LDS_000PIN, + O=>T_93, + I2=>BGACK_030Q, + I3=>GATE_T_93_DN ); + GATE_T_93_I_2: INV port map ( I0=>RSTPIN, + O=>GATE_T_93_DN ); + GATE_T_94_I_1: INV port map ( I0=>SIZE_DMA_0_busQ, + O=>GATE_T_94_A ); + GATE_T_94_I_2: AND3 port map ( O=>T_94, + I2=>BGACK_030Q, + I1=>RSTPIN, + I0=>GATE_T_94_A ); + GATE_T_95_I_1: INV port map ( I0=>inst_BGACK_030_INT_DQ, + O=>GATE_T_95_A ); + GATE_T_95_I_2: AND3 port map ( O=>T_95, + I2=>BGACK_030Q, + I1=>RSTPIN, + I0=>GATE_T_95_A ); + GATE_T_96_I_1: AND4 port map ( O=>T_96, + I3=>T_310, + I2=>T_311, + I1=>T_312, + I0=>GATE_T_96_A ); + GATE_T_96_I_2: INV port map ( I0=>AS_000PIN, + O=>GATE_T_96_A ); + GATE_T_97_I_1: INV port map ( I0=>AS_000PIN, + O=>GATE_T_97_A ); + GATE_T_97_I_2: AND3 port map ( O=>T_97, + I2=>T_309, + I1=>T_308, + I0=>GATE_T_97_A ); + GATE_T_98_I_1: INV port map ( I0=>AS_000PIN, + O=>GATE_T_98_A ); + GATE_T_98_I_2: AND3 port map ( O=>T_98, + I2=>T_307, + I1=>T_306, + I0=>GATE_T_98_A ); + GATE_T_99_I_1: INV port map ( I0=>AS_000PIN, + O=>GATE_T_99_A ); + GATE_T_99_I_2: AND3 port map ( O=>T_99, + I2=>T_305, + I1=>T_304, + I0=>GATE_T_99_A ); + GATE_T_100_I_1: AND3 port map ( O=>T_100, + I2=>T_318, + I1=>T_319, + I0=>T_317 ); + GATE_T_101_I_1: INV port map ( I0=>AS_000PIN, + O=>GATE_T_101_A ); + GATE_T_101_I_2: AND3 port map ( O=>T_101, + I2=>T_316, + I1=>T_315, + I0=>GATE_T_101_A ); + GATE_T_102_I_1: INV port map ( I0=>AS_000PIN, + O=>GATE_T_102_A ); + GATE_T_102_I_2: AND3 port map ( O=>T_102, + I2=>T_314, + I1=>T_313, + I0=>GATE_T_102_A ); + GATE_T_103_I_1: AND4 port map ( O=>T_103, + I3=>inst_AS_000_DMAQ, + I2=>CLK_030PIN, + I1=>inst_CLK_030_HQ, + I0=>GATE_T_103_A ); + GATE_T_103_I_2: INV port map ( I0=>RW_000PIN, + O=>GATE_T_103_A ); + GATE_T_104_I_1: INV port map ( I0=>RW_000PIN, + O=>GATE_T_104_A ); + GATE_T_104_I_2: INV port map ( I0=>inst_CLK_030_HQ, + O=>GATE_T_104_B ); + GATE_T_104_I_3: AND3 port map ( O=>T_104, + I0=>inst_DS_000_DMAQ, + I2=>GATE_T_104_A, + I1=>GATE_T_104_B ); + GATE_T_105_I_1: INV port map ( I0=>RW_000PIN, + O=>GATE_T_105_A ); + GATE_T_105_I_2: INV port map ( I0=>CLK_030PIN, + O=>GATE_T_105_B ); + GATE_T_105_I_3: AND3 port map ( O=>T_105, + I0=>inst_DS_000_DMAQ, + I2=>GATE_T_105_A, + I1=>GATE_T_105_B ); + GATE_T_106_I_1: AND2 port map ( O=>T_106, + I1=>LDS_000PIN, + I0=>UDS_000PIN ); + GATE_T_107_I_1: NOR2 port map ( O=>T_107, + I1=>CYCLE_DMA_1_busQ, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_108_I_1: AND2 port map ( O=>T_108, + I1=>CYCLE_DMA_1_busQ, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_109_I_1: AND2 port map ( O=>T_109, + I1=>LDS_000PIN, + I0=>UDS_000PIN ); + GATE_T_110_I_1: NOR2 port map ( O=>T_110, + I1=>CYCLE_DMA_1_busQ, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_111_I_1: AND2 port map ( O=>T_111, + I1=>CYCLE_DMA_1_busQ, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_112_I_1: AND2 port map ( O=>T_112, + I1=>inst_AS_000_DMAQ, + I0=>GATE_T_112_A ); + GATE_T_112_I_2: INV port map ( O=>GATE_T_112_A, + I0=>CLK_030PIN ); + GATE_T_113_I_1: AND4 port map ( O=>T_113, + I3=>T_349, + I2=>T_350, + I1=>T_351, + I0=>T_352 ); + GATE_T_114_I_1: AND4 port map ( O=>T_114, + I3=>T_345, + I2=>T_346, + I1=>T_347, + I0=>T_348 ); + GATE_T_115_I_1: AND4 port map ( O=>T_115, + I3=>T_341, + I2=>T_342, + I1=>T_343, + I0=>T_344 ); + GATE_T_116_I_1: AND4 port map ( O=>T_116, + I3=>T_337, + I2=>T_338, + I1=>T_339, + I0=>T_340 ); + GATE_T_117_I_1: AND4 port map ( O=>T_117, + I3=>T_333, + I2=>T_334, + I1=>T_335, + I0=>T_336 ); + GATE_T_118_I_1: AND4 port map ( O=>T_118, + I3=>T_329, + I2=>T_330, + I1=>T_331, + I0=>T_332 ); + GATE_T_119_I_3: AND4 port map ( O=>T_119, + I3=>BERRPIN, + I2=>RSTPIN, + I1=>GATE_T_119_B, + I0=>GATE_T_119_A ); + GATE_T_119_I_2: INV port map ( I0=>inst_AS_030_000_SYNCQ, + O=>GATE_T_119_B ); + GATE_T_119_I_1: INV port map ( I0=>inst_AS_030_D0Q, + O=>GATE_T_119_A ); + GATE_T_120_I_1: AND4 port map ( O=>T_120, + I3=>BGACK_030Q, + I2=>RSTPIN, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_120_A ); + GATE_T_120_I_2: INV port map ( I0=>inst_AMIGA_BUS_ENABLE_DMA_LOWQ, + O=>GATE_T_120_A ); + GATE_T_121_I_1: INV port map ( I0=>BGACK_030Q, + O=>GATE_T_121_A ); + GATE_T_121_I_2: AND3 port map ( O=>T_121, + I2=>A_1XPIN, + I1=>RSTPIN, + I0=>GATE_T_121_A ); + GATE_T_122_I_3: AND4 port map ( O=>T_122, + I3=>BERRPIN, + I2=>RSTPIN, + I1=>GATE_T_122_B, + I0=>GATE_T_122_A ); + GATE_T_122_I_2: INV port map ( I0=>inst_AS_030_D0Q, + O=>GATE_T_122_B ); + GATE_T_122_I_1: INV port map ( I0=>inst_AS_000_INTQ, + O=>GATE_T_122_A ); + GATE_T_123_I_1: AND4 port map ( O=>T_123, + I3=>SM_AMIGA_6_busQ, + I2=>CLK_000_D_0_busQ, + I1=>RSTPIN, + I0=>GATE_T_123_A ); + GATE_T_123_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_123_A ); + GATE_T_124_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_124_A ); + GATE_T_124_I_2: AND3 port map ( O=>T_124, + I2=>T_354, + I1=>T_353, + I0=>GATE_T_124_A ); + GATE_T_125_I_1: AND2 port map ( O=>T_125, + I1=>CLK_000_D_0_busQ, + I0=>cpu_est_1_busQ ); + GATE_T_126_I_1: AND2 port map ( O=>T_126, + I1=>cpu_est_1_busQ, + I0=>GATE_T_126_A ); + GATE_T_126_I_2: INV port map ( O=>GATE_T_126_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_127_I_1: AND2 port map ( O=>T_127, + I1=>cpu_est_1_busQ, + I0=>GATE_T_127_A ); + GATE_T_127_I_2: INV port map ( O=>GATE_T_127_A, + I0=>cpu_est_0_busQ ); + GATE_T_128_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_128_A ); + GATE_T_128_I_2: INV port map ( I0=>cpu_est_0_busQ, + O=>GATE_T_128_B ); + GATE_T_128_I_3: AND3 port map ( O=>T_128, + I0=>CLK_000_D_1_busQ, + I2=>GATE_T_128_A, + I1=>GATE_T_128_B ); + GATE_T_129_I_1: AND2 port map ( O=>T_129, + I1=>CLK_000_D_0_busQ, + I0=>cpu_est_0_busQ ); + GATE_T_130_I_1: AND2 port map ( O=>T_130, + I1=>cpu_est_0_busQ, + I0=>GATE_T_130_A ); + GATE_T_130_I_2: INV port map ( O=>GATE_T_130_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_131_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_131_A ); + GATE_T_131_I_2: AND3 port map ( O=>T_131, + I2=>T_356, + I1=>T_355, + I0=>GATE_T_131_A ); + GATE_T_132_I_1: INV port map ( I0=>cpu_est_2_busQ, + O=>GATE_T_132_A ); + GATE_T_132_I_2: INV port map ( I0=>cpu_est_0_busQ, + O=>GATE_T_132_B ); + GATE_T_132_I_3: AND3 port map ( O=>T_132, + I0=>cpu_est_3_busQ, + I2=>GATE_T_132_A, + I1=>GATE_T_132_B ); + GATE_T_133_I_1: AND2 port map ( O=>T_133, + I1=>CLK_000_D_0_busQ, + I0=>cpu_est_3_busQ ); + GATE_T_134_I_1: AND2 port map ( O=>T_134, + I1=>cpu_est_3_busQ, + I0=>GATE_T_134_A ); + GATE_T_134_I_2: INV port map ( O=>GATE_T_134_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_135_I_1: AND4 port map ( O=>T_135, + I3=>T_369, + I2=>T_370, + I1=>T_371, + I0=>GATE_T_135_A ); + GATE_T_135_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_135_A ); + GATE_T_136_I_1: AND4 port map ( O=>T_136, + I3=>T_366, + I2=>T_367, + I1=>T_368, + I0=>GATE_T_136_A ); + GATE_T_136_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_136_A ); + GATE_T_137_I_1: AND4 port map ( O=>T_137, + I3=>T_363, + I2=>T_364, + I1=>T_365, + I0=>IPL_D0_2_busQ ); + GATE_T_138_I_1: AND4 port map ( O=>T_138, + I3=>T_360, + I2=>T_361, + I1=>T_362, + I0=>IPL_D0_2_busQ ); + GATE_T_139_I_3: AND4 port map ( O=>T_139, + I3=>RSTPIN, + I2=>IPL_2XPIN, + I1=>GATE_T_139_B, + I0=>GATE_T_139_A ); + GATE_T_139_I_2: INV port map ( I0=>IPL_030_0XQ, + O=>GATE_T_139_B ); + GATE_T_139_I_1: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_139_A ); + GATE_T_140_I_3: AND4 port map ( O=>T_140, + I3=>IPL_D0_2_busQ, + I2=>RSTPIN, + I1=>GATE_T_140_B, + I0=>GATE_T_140_A ); + GATE_T_140_I_2: INV port map ( I0=>IPL_030_0XQ, + O=>GATE_T_140_B ); + GATE_T_140_I_1: INV port map ( I0=>IPL_2XPIN, + O=>GATE_T_140_A ); + GATE_T_141_I_3: AND4 port map ( O=>T_141, + I3=>IPL_1XPIN, + I2=>RSTPIN, + I1=>GATE_T_141_B, + I0=>GATE_T_141_A ); + GATE_T_141_I_2: INV port map ( I0=>IPL_030_0XQ, + O=>GATE_T_141_B ); + GATE_T_141_I_1: INV port map ( I0=>IPL_D0_1_busQ, + O=>GATE_T_141_A ); + GATE_T_142_I_3: AND4 port map ( O=>T_142, + I3=>IPL_D0_1_busQ, + I2=>RSTPIN, + I1=>GATE_T_142_B, + I0=>GATE_T_142_A ); + GATE_T_142_I_2: INV port map ( I0=>IPL_030_0XQ, + O=>GATE_T_142_B ); + GATE_T_142_I_1: INV port map ( I0=>IPL_1XPIN, + O=>GATE_T_142_A ); + GATE_T_143_I_1: INV port map ( I0=>IPL_030_0XQ, + O=>GATE_T_143_A ); + GATE_T_143_I_2: INV port map ( I0=>IPL_D0_0_busQ, + O=>GATE_T_143_B ); + GATE_T_143_I_3: AND3 port map ( O=>T_143, + I0=>RSTPIN, + I2=>GATE_T_143_A, + I1=>GATE_T_143_B ); + GATE_T_144_I_1: INV port map ( I0=>IPL_030_0XQ, + O=>GATE_T_144_A ); + GATE_T_144_I_2: INV port map ( I0=>IPL_0XPIN, + O=>GATE_T_144_B ); + GATE_T_144_I_3: AND3 port map ( O=>T_144, + I0=>RSTPIN, + I2=>GATE_T_144_A, + I1=>GATE_T_144_B ); + GATE_T_145_I_1: AND4 port map ( O=>T_145, + I3=>T_384, + I2=>T_385, + I1=>T_386, + I0=>GATE_T_145_A ); + GATE_T_145_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_145_A ); + GATE_T_146_I_1: AND4 port map ( O=>T_146, + I3=>T_381, + I2=>T_382, + I1=>T_383, + I0=>GATE_T_146_A ); + GATE_T_146_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_146_A ); + GATE_T_147_I_1: AND4 port map ( O=>T_147, + I3=>T_378, + I2=>T_379, + I1=>T_380, + I0=>IPL_D0_2_busQ ); + GATE_T_148_I_1: AND4 port map ( O=>T_148, + I3=>T_375, + I2=>T_376, + I1=>T_377, + I0=>IPL_D0_2_busQ ); + GATE_T_149_I_3: AND4 port map ( O=>T_149, + I3=>RSTPIN, + I2=>IPL_2XPIN, + I1=>GATE_T_149_B, + I0=>GATE_T_149_A ); + GATE_T_149_I_2: INV port map ( I0=>IPL_030_1XQ, + O=>GATE_T_149_B ); + GATE_T_149_I_1: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_149_A ); + GATE_T_150_I_3: AND4 port map ( O=>T_150, + I3=>IPL_D0_2_busQ, + I2=>RSTPIN, + I1=>GATE_T_150_B, + I0=>GATE_T_150_A ); + GATE_T_150_I_2: INV port map ( I0=>IPL_030_1XQ, + O=>GATE_T_150_B ); + GATE_T_150_I_1: INV port map ( I0=>IPL_2XPIN, + O=>GATE_T_150_A ); + GATE_T_151_I_3: AND4 port map ( O=>T_151, + I3=>IPL_0XPIN, + I2=>RSTPIN, + I1=>GATE_T_151_B, + I0=>GATE_T_151_A ); + GATE_T_151_I_2: INV port map ( I0=>IPL_030_1XQ, + O=>GATE_T_151_B ); + GATE_T_151_I_1: INV port map ( I0=>IPL_D0_0_busQ, + O=>GATE_T_151_A ); + GATE_T_152_I_3: AND4 port map ( O=>T_152, + I3=>IPL_D0_0_busQ, + I2=>RSTPIN, + I1=>GATE_T_152_B, + I0=>GATE_T_152_A ); + GATE_T_152_I_2: INV port map ( I0=>IPL_030_1XQ, + O=>GATE_T_152_B ); + GATE_T_152_I_1: INV port map ( I0=>IPL_0XPIN, + O=>GATE_T_152_A ); + GATE_T_153_I_1: INV port map ( I0=>IPL_030_1XQ, + O=>GATE_T_153_A ); + GATE_T_153_I_2: INV port map ( I0=>IPL_D0_1_busQ, + O=>GATE_T_153_B ); + GATE_T_153_I_3: AND3 port map ( O=>T_153, + I0=>RSTPIN, + I2=>GATE_T_153_A, + I1=>GATE_T_153_B ); + GATE_T_154_I_1: INV port map ( I0=>IPL_030_1XQ, + O=>GATE_T_154_A ); + GATE_T_154_I_2: INV port map ( I0=>IPL_1XPIN, + O=>GATE_T_154_B ); + GATE_T_154_I_3: AND3 port map ( O=>T_154, + I0=>RSTPIN, + I2=>GATE_T_154_A, + I1=>GATE_T_154_B ); + GATE_T_155_I_1: AND3 port map ( O=>T_155, + I2=>inst_BGACK_030_INT_DQ, + I1=>BGACK_030Q, + I0=>A_0XQ ); + GATE_T_156_I_1: AND2 port map ( O=>T_156, + I1=>UDS_000PIN, + I0=>GATE_T_156_A ); + GATE_T_156_I_2: INV port map ( O=>GATE_T_156_A, + I0=>BGACK_030Q ); + GATE_T_157_I_1: AND4 port map ( O=>T_157, + I3=>BGACK_030Q, + I2=>RSTPIN, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_157_A ); + GATE_T_157_I_2: INV port map ( I0=>RWQ, + O=>GATE_T_157_A ); + GATE_T_158_I_1: INV port map ( I0=>RW_000PIN, + O=>GATE_T_158_A ); + GATE_T_158_I_2: INV port map ( I0=>BGACK_030Q, + O=>GATE_T_158_B ); + GATE_T_158_I_3: AND3 port map ( O=>T_158, + I0=>RSTPIN, + I2=>GATE_T_158_A, + I1=>GATE_T_158_B ); + GATE_T_159_I_1: AND3 port map ( O=>T_159, + I2=>T_391, + I1=>T_392, + I0=>T_390 ); + GATE_T_160_I_1: AND4 port map ( O=>T_160, + I3=>T_387, + I2=>T_388, + I1=>T_389, + I0=>CLK_000_D_0_busQ ); + GATE_T_161_I_1: NOR2 port map ( O=>T_161, + I1=>VMAQ, + I0=>RSTPIN ); + GATE_T_162_I_1: AND3 port map ( O=>T_162, + I2=>T_396, + I1=>SM_AMIGA_1_busQ, + I0=>T_395 ); + GATE_T_163_I_1: AND3 port map ( O=>T_163, + I2=>T_394, + I1=>SM_AMIGA_1_busQ, + I0=>T_393 ); + GATE_T_164_I_3: AND4 port map ( O=>T_164, + I3=>BERRPIN, + I2=>RSTPIN, + I1=>GATE_T_164_B, + I0=>GATE_T_164_A ); + GATE_T_164_I_2: INV port map ( I0=>DSACK1Q, + O=>GATE_T_164_B ); + GATE_T_164_I_1: INV port map ( I0=>inst_AS_030_D0Q, + O=>GATE_T_164_A ); + GATE_T_165_I_1: AND4 port map ( O=>T_165, + I3=>SM_AMIGA_1_busQ, + I2=>CLK_000_D_12_busQ, + I1=>RSTPIN, + I0=>GATE_T_165_A ); + GATE_T_165_I_2: INV port map ( I0=>CLK_000_D_11_busQ, + O=>GATE_T_165_A ); + GATE_T_166_I_1: AND4 port map ( O=>T_166, + I3=>AS_000PIN, + I2=>CLK_000_D_0_busQ, + I1=>BGACK_000PIN, + I0=>GATE_T_166_A ); + GATE_T_166_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_166_A ); + GATE_T_167_I_1: AND2 port map ( O=>T_167, + I1=>BGACK_030Q, + I0=>BGACK_000PIN ); + GATE_T_168_I_1: AND3 port map ( O=>T_168, + I2=>T_398, + I1=>CLK_000_D_0_busQ, + I0=>T_397 ); + GATE_T_169_I_1: INV port map ( I0=>BG_000Q, + O=>GATE_T_169_A ); + GATE_T_169_I_2: INV port map ( I0=>BG_030PIN, + O=>GATE_T_169_B ); + GATE_T_169_I_3: AND3 port map ( O=>T_169, + I0=>RSTPIN, + I2=>GATE_T_169_A, + I1=>GATE_T_169_B ); + GATE_T_170_I_1: AND4 port map ( O=>T_170, + I3=>T_401, + I2=>T_402, + I1=>T_403, + I0=>GATE_T_170_A ); + GATE_T_170_I_2: INV port map ( I0=>RWPIN, + O=>GATE_T_170_A ); + GATE_T_171_I_1: AND3 port map ( O=>T_171, + I2=>T_400, + I1=>SM_AMIGA_i_7_busQ, + I0=>T_399 ); + GATE_T_172_I_3: AND4 port map ( O=>T_172, + I3=>SM_AMIGA_i_7_busQ, + I2=>RSTPIN, + I1=>GATE_T_172_B, + I0=>GATE_T_172_A ); + GATE_T_172_I_2: INV port map ( I0=>RW_000Q, + O=>GATE_T_172_B ); + GATE_T_172_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_172_A ); + GATE_T_173_I_1: AND4 port map ( O=>T_173, + I3=>CLK_000_D_1_busQ, + I2=>RSTPIN, + I1=>SM_AMIGA_i_7_busQ, + I0=>GATE_T_173_A ); + GATE_T_173_I_2: INV port map ( I0=>RW_000Q, + O=>GATE_T_173_A ); + GATE_T_174_I_1: AND4 port map ( O=>T_174, + I3=>T_416, + I2=>T_417, + I1=>T_418, + I0=>GATE_T_174_A ); + GATE_T_174_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_174_A ); + GATE_T_175_I_1: AND4 port map ( O=>T_175, + I3=>T_413, + I2=>T_414, + I1=>T_415, + I0=>GATE_T_175_A ); + GATE_T_175_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_175_A ); + GATE_T_176_I_1: AND4 port map ( O=>T_176, + I3=>T_410, + I2=>T_411, + I1=>T_412, + I0=>GATE_T_176_A ); + GATE_T_176_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_176_A ); + GATE_T_177_I_1: AND4 port map ( O=>T_177, + I3=>T_407, + I2=>T_408, + I1=>T_409, + I0=>GATE_T_177_A ); + GATE_T_177_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_177_A ); + GATE_T_178_I_3: AND4 port map ( O=>T_178, + I3=>IPL_1XPIN, + I2=>RSTPIN, + I1=>GATE_T_178_B, + I0=>GATE_T_178_A ); + GATE_T_178_I_2: INV port map ( I0=>IPL_030_2XQ, + O=>GATE_T_178_B ); + GATE_T_178_I_1: INV port map ( I0=>IPL_D0_1_busQ, + O=>GATE_T_178_A ); + GATE_T_179_I_3: AND4 port map ( O=>T_179, + I3=>IPL_D0_1_busQ, + I2=>RSTPIN, + I1=>GATE_T_179_B, + I0=>GATE_T_179_A ); + GATE_T_179_I_2: INV port map ( I0=>IPL_030_2XQ, + O=>GATE_T_179_B ); + GATE_T_179_I_1: INV port map ( I0=>IPL_1XPIN, + O=>GATE_T_179_A ); + GATE_T_180_I_3: AND4 port map ( O=>T_180, + I3=>IPL_0XPIN, + I2=>RSTPIN, + I1=>GATE_T_180_B, + I0=>GATE_T_180_A ); + GATE_T_180_I_2: INV port map ( I0=>IPL_030_2XQ, + O=>GATE_T_180_B ); + GATE_T_180_I_1: INV port map ( I0=>IPL_D0_0_busQ, + O=>GATE_T_180_A ); + GATE_T_181_I_3: AND4 port map ( O=>T_181, + I3=>IPL_D0_0_busQ, + I2=>RSTPIN, + I1=>GATE_T_181_B, + I0=>GATE_T_181_A ); + GATE_T_181_I_2: INV port map ( I0=>IPL_030_2XQ, + O=>GATE_T_181_B ); + GATE_T_181_I_1: INV port map ( I0=>IPL_0XPIN, + O=>GATE_T_181_A ); + GATE_T_182_I_1: INV port map ( I0=>IPL_030_2XQ, + O=>GATE_T_182_A ); + GATE_T_182_I_2: INV port map ( I0=>IPL_D0_2_busQ, + O=>GATE_T_182_B ); + GATE_T_182_I_3: AND3 port map ( O=>T_182, + I0=>RSTPIN, + I2=>GATE_T_182_A, + I1=>GATE_T_182_B ); + GATE_T_183_I_1: INV port map ( I0=>IPL_030_2XQ, + O=>GATE_T_183_A ); + GATE_T_183_I_2: INV port map ( I0=>IPL_2XPIN, + O=>GATE_T_183_B ); + GATE_T_183_I_3: AND3 port map ( O=>T_183, + I0=>RSTPIN, + I2=>GATE_T_183_A, + I1=>GATE_T_183_B ); + GATE_T_184_I_1: AND4 port map ( O=>T_184, + I3=>T_419, + I2=>T_420, + I1=>T_421, + I0=>GATE_T_184_A ); + GATE_T_184_I_2: INV port map ( I0=>AHIGH_31XPIN, + O=>GATE_T_184_A ); + GATE_T_185_I_1: AND2 port map ( O=>T_185, + I1=>inst_AMIGA_BUS_ENABLE_DMA_HIGHQ, + I0=>GATE_T_185_A ); + GATE_T_185_I_2: INV port map ( O=>GATE_T_185_A, + I0=>BGACK_030Q ); + GATE_T_186_I_1: AND2 port map ( O=>T_186, + I1=>inst_AS_030_000_SYNCQ, + I0=>BGACK_030Q ); + GATE_T_187_I_1: NOR4 port map ( I0=>nEXP_SPACEPIN, + I1=>BGACK_030Q, + O=>T_187, + I2=>AS_000PIN, + I3=>GATE_T_187_DN ); + GATE_T_187_I_2: INV port map ( I0=>RW_000PIN, + O=>GATE_T_187_DN ); + GATE_T_188_I_1: AND2 port map ( O=>T_188, + I1=>BGACK_030Q, + I0=>GATE_T_188_A ); + GATE_T_188_I_2: INV port map ( O=>GATE_T_188_A, + I0=>RW_000PIN ); + GATE_T_189_I_1: INV port map ( I0=>cpu_est_2_busQ, + O=>GATE_T_189_A ); + GATE_T_189_I_2: INV port map ( I0=>cpu_est_1_busQ, + O=>GATE_T_189_B ); + GATE_T_189_I_3: AND3 port map ( O=>T_189, + I0=>cpu_est_3_busQ, + I2=>GATE_T_189_A, + I1=>GATE_T_189_B ); + GATE_T_190_I_1: INV port map ( I0=>cpu_est_3_busQ, + O=>GATE_T_190_A ); + GATE_T_190_I_2: AND3 port map ( O=>T_190, + I2=>cpu_est_1_busQ, + I1=>cpu_est_2_busQ, + I0=>GATE_T_190_A ); + GATE_T_191_I_1: OR4 port map ( I0=>T_35, + I1=>T_36, + O=>T_191, + I2=>T_37, + I3=>T_38 ); + GATE_T_192_I_1: OR4 port map ( I0=>T_31, + I1=>T_32, + O=>T_192, + I2=>T_33, + I3=>T_34 ); + GATE_T_193_I_1: OR4 port map ( I0=>T_27, + I1=>T_28, + O=>T_193, + I2=>T_29, + I3=>T_30 ); + GATE_T_194_I_1: AND2 port map ( O=>T_194, + I1=>SM_AMIGA_6_busQ, + I0=>CLK_000_D_0_busQ ); + GATE_T_195_I_1: AND2 port map ( O=>T_195, + I1=>RSTPIN, + I0=>GATE_T_195_A ); + GATE_T_195_I_2: INV port map ( O=>GATE_T_195_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_196_I_1: AND2 port map ( O=>T_196, + I1=>SM_AMIGA_4_busQ, + I0=>CLK_000_D_0_busQ ); + GATE_T_197_I_1: AND2 port map ( O=>T_197, + I1=>RSTPIN, + I0=>GATE_T_197_A ); + GATE_T_197_I_2: INV port map ( O=>GATE_T_197_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_198_I_1: AND2 port map ( O=>T_198, + I1=>SM_AMIGA_1_busQ, + I0=>GATE_T_198_A ); + GATE_T_198_I_2: INV port map ( O=>GATE_T_198_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_199_I_1: AND2 port map ( O=>T_199, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_200_I_1: AND2 port map ( O=>T_200, + I1=>SM_AMIGA_5_busQ, + I0=>GATE_T_200_A ); + GATE_T_200_I_2: INV port map ( O=>GATE_T_200_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_201_I_1: AND2 port map ( O=>T_201, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_202_I_1: AND2 port map ( O=>T_202, + I1=>SM_AMIGA_2_busQ, + I0=>CLK_000_D_0_busQ ); + GATE_T_203_I_1: AND2 port map ( O=>T_203, + I1=>RSTPIN, + I0=>GATE_T_203_A ); + GATE_T_203_I_2: INV port map ( O=>GATE_T_203_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_204_I_1: AND2 port map ( O=>T_204, + I1=>SM_AMIGA_3_busQ, + I0=>GATE_T_204_A ); + GATE_T_204_I_2: INV port map ( O=>GATE_T_204_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_205_I_1: AND2 port map ( O=>T_205, + I1=>CLK_000_D_1_busQ, + I0=>GATE_T_205_A ); + GATE_T_205_I_2: INV port map ( O=>GATE_T_205_A, + I0=>inst_DTACK_D0Q ); + GATE_T_206_I_1: AND2 port map ( O=>T_206, + I1=>inst_VPA_DQ, + I0=>RSTPIN ); + GATE_T_207_I_1: NOR3 port map ( O=>T_207, + I2=>SM_AMIGA_3_busQ, + I1=>SM_AMIGA_5_busQ, + I0=>SM_AMIGA_2_busQ ); + GATE_T_208_I_1: NOR3 port map ( O=>T_208, + I2=>SM_AMIGA_4_busQ, + I1=>SM_AMIGA_0_busQ, + I0=>SM_AMIGA_1_busQ ); + GATE_T_209_I_1: INV port map ( I0=>SM_AMIGA_6_busQ, + O=>GATE_T_209_A ); + GATE_T_209_I_2: INV port map ( I0=>nEXP_SPACEPIN, + O=>GATE_T_209_B ); + GATE_T_209_I_3: AND3 port map ( O=>T_209, + I0=>RSTPIN, + I2=>GATE_T_209_A, + I1=>GATE_T_209_B ); + GATE_T_210_I_1: NOR3 port map ( O=>T_210, + I2=>SM_AMIGA_3_busQ, + I1=>SM_AMIGA_5_busQ, + I0=>SM_AMIGA_2_busQ ); + GATE_T_211_I_1: NOR3 port map ( O=>T_211, + I2=>SM_AMIGA_4_busQ, + I1=>SM_AMIGA_0_busQ, + I0=>SM_AMIGA_1_busQ ); + GATE_T_212_I_1: INV port map ( I0=>SM_AMIGA_6_busQ, + O=>GATE_T_212_A ); + GATE_T_212_I_2: AND3 port map ( O=>T_212, + I2=>inst_AS_030_000_SYNCQ, + I1=>RSTPIN, + I0=>GATE_T_212_A ); + GATE_T_213_I_1: NOR3 port map ( O=>T_213, + I2=>SM_AMIGA_3_busQ, + I1=>SM_AMIGA_5_busQ, + I0=>SM_AMIGA_2_busQ ); + GATE_T_214_I_1: NOR3 port map ( O=>T_214, + I2=>SM_AMIGA_4_busQ, + I1=>SM_AMIGA_0_busQ, + I0=>SM_AMIGA_1_busQ ); + GATE_T_215_I_1: INV port map ( I0=>SM_AMIGA_6_busQ, + O=>GATE_T_215_A ); + GATE_T_215_I_2: AND3 port map ( O=>T_215, + I2=>CLK_000_D_1_busQ, + I1=>RSTPIN, + I0=>GATE_T_215_A ); + GATE_T_216_I_1: NOR3 port map ( O=>T_216, + I2=>SM_AMIGA_3_busQ, + I1=>SM_AMIGA_5_busQ, + I0=>SM_AMIGA_2_busQ ); + GATE_T_217_I_1: NOR3 port map ( O=>T_217, + I2=>SM_AMIGA_4_busQ, + I1=>SM_AMIGA_0_busQ, + I0=>SM_AMIGA_1_busQ ); + GATE_T_218_I_1: INV port map ( I0=>SM_AMIGA_6_busQ, + O=>GATE_T_218_A ); + GATE_T_218_I_2: INV port map ( I0=>CLK_000_D_2_busQ, + O=>GATE_T_218_B ); + GATE_T_218_I_3: AND3 port map ( O=>T_218, + I0=>RSTPIN, + I2=>GATE_T_218_A, + I1=>GATE_T_218_B ); + GATE_T_219_I_1: AND2 port map ( O=>T_219, + I1=>BERRPIN, + I0=>GATE_T_219_A ); + GATE_T_219_I_2: INV port map ( O=>GATE_T_219_A, + I0=>SM_AMIGA_2_busQ ); + GATE_T_220_I_1: NOR3 port map ( O=>T_220, + I2=>SM_AMIGA_5_busQ, + I1=>SM_AMIGA_1_busQ, + I0=>SM_AMIGA_3_busQ ); + GATE_T_221_I_1: INV port map ( I0=>SM_AMIGA_4_busQ, + O=>GATE_T_221_A ); + GATE_T_221_I_2: INV port map ( I0=>SM_AMIGA_6_busQ, + O=>GATE_T_221_B ); + GATE_T_221_I_3: AND3 port map ( O=>T_221, + I0=>SM_AMIGA_0_busQ, + I2=>GATE_T_221_A, + I1=>GATE_T_221_B ); + GATE_T_222_I_1: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_222_A ); + GATE_T_222_I_2: AND3 port map ( O=>T_222, + I2=>RSTPIN, + I1=>CLK_000_D_0_busQ, + I0=>GATE_T_222_A ); + GATE_T_223_I_1: AND2 port map ( O=>T_223, + I1=>SM_AMIGA_3_busQ, + I0=>GATE_T_223_A ); + GATE_T_223_I_2: INV port map ( O=>GATE_T_223_A, + I0=>BERRPIN ); + GATE_T_224_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_224_A ); + GATE_T_224_I_2: INV port map ( I0=>inst_VPA_DQ, + O=>GATE_T_224_B ); + GATE_T_224_I_3: AND3 port map ( O=>T_224, + I0=>CLK_000_D_1_busQ, + I2=>GATE_T_224_A, + I1=>GATE_T_224_B ); + GATE_T_225_I_1: NOR3 port map ( O=>T_225, + I2=>cpu_est_1_busQ, + I1=>cpu_est_0_busQ, + I0=>cpu_est_2_busQ ); + GATE_T_226_I_1: INV port map ( I0=>VMAQ, + O=>GATE_T_226_A ); + GATE_T_226_I_2: AND3 port map ( O=>T_226, + I2=>RSTPIN, + I1=>cpu_est_3_busQ, + I0=>GATE_T_226_A ); + GATE_T_227_I_14: NOR4 port map ( O=>T_227, + I3=>SM_AMIGA_2_busQ, + I2=>SM_AMIGA_3_busQ, + I1=>SM_AMIGA_5_busQ, + I0=>SM_AMIGA_1_busQ ); + GATE_T_228_I_1: NOR4 port map ( I0=>SM_AMIGA_0_busQ, + I1=>SM_AMIGA_4_busQ, + O=>T_228, + I2=>SM_AMIGA_6_busQ, + I3=>GATE_T_228_DN ); + GATE_T_228_I_2: INV port map ( I0=>CLK_000_D_2_busQ, + O=>GATE_T_228_DN ); + GATE_T_229_I_3: AND4 port map ( O=>T_229, + I3=>RSTPIN, + I2=>nEXP_SPACEPIN, + I1=>GATE_T_229_B, + I0=>GATE_T_229_A ); + GATE_T_229_I_2: INV port map ( I0=>CLK_000_D_1_busQ, + O=>GATE_T_229_B ); + GATE_T_229_I_1: INV port map ( I0=>inst_AS_030_000_SYNCQ, + O=>GATE_T_229_A ); + GATE_T_230_I_1: AND2 port map ( O=>T_230, + I1=>SM_AMIGA_4_busQ, + I0=>CLK_000_D_0_busQ ); + GATE_T_231_I_1: AND2 port map ( O=>T_231, + I1=>RSTPIN, + I0=>GATE_T_231_A ); + GATE_T_231_I_2: INV port map ( O=>GATE_T_231_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_232_I_1: AND2 port map ( O=>T_232, + I1=>SM_AMIGA_4_busQ, + I0=>CLK_000_D_0_busQ ); + GATE_T_233_I_1: AND2 port map ( O=>T_233, + I1=>RSTPIN, + I0=>GATE_T_233_A ); + GATE_T_233_I_2: INV port map ( O=>GATE_T_233_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_234_I_1: AND2 port map ( O=>T_234, + I1=>SM_AMIGA_3_busQ, + I0=>GATE_T_234_A ); + GATE_T_234_I_2: INV port map ( O=>GATE_T_234_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_235_I_1: AND2 port map ( O=>T_235, + I1=>CLK_000_D_1_busQ, + I0=>GATE_T_235_A ); + GATE_T_235_I_2: INV port map ( O=>GATE_T_235_A, + I0=>inst_DTACK_D0Q ); + GATE_T_236_I_1: AND2 port map ( O=>T_236, + I1=>inst_VPA_DQ, + I0=>RSTPIN ); + GATE_T_237_I_1: AND2 port map ( O=>T_237, + I1=>BERRPIN, + I0=>SM_AMIGA_3_busQ ); + GATE_T_238_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_238_A ); + GATE_T_238_I_2: INV port map ( I0=>inst_VPA_DQ, + O=>GATE_T_238_B ); + GATE_T_238_I_3: AND3 port map ( O=>T_238, + I0=>CLK_000_D_1_busQ, + I2=>GATE_T_238_A, + I1=>GATE_T_238_B ); + GATE_T_239_I_1: NOR3 port map ( O=>T_239, + I2=>cpu_est_1_busQ, + I1=>cpu_est_0_busQ, + I0=>cpu_est_2_busQ ); + GATE_T_240_I_1: INV port map ( I0=>VMAQ, + O=>GATE_T_240_A ); + GATE_T_240_I_2: AND3 port map ( O=>T_240, + I2=>RSTPIN, + I1=>cpu_est_3_busQ, + I0=>GATE_T_240_A ); + GATE_T_241_I_1: AND2 port map ( O=>T_241, + I1=>RST_DLY_0_busQ, + I0=>GATE_T_241_A ); + GATE_T_241_I_2: INV port map ( O=>GATE_T_241_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_242_I_1: AND2 port map ( O=>T_242, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_243_I_1: AND2 port map ( O=>T_243, + I1=>RST_DLY_0_busQ, + I0=>GATE_T_243_A ); + GATE_T_243_I_2: INV port map ( O=>GATE_T_243_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_244_I_1: AND2 port map ( O=>T_244, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_245_I_1: AND2 port map ( O=>T_245, + I1=>SM_AMIGA_3_busQ, + I0=>GATE_T_245_A ); + GATE_T_245_I_2: INV port map ( O=>GATE_T_245_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_246_I_1: AND2 port map ( O=>T_246, + I1=>CLK_000_D_1_busQ, + I0=>GATE_T_246_A ); + GATE_T_246_I_2: INV port map ( O=>GATE_T_246_A, + I0=>inst_DTACK_D0Q ); + GATE_T_247_I_1: AND2 port map ( O=>T_247, + I1=>inst_VPA_DQ, + I0=>RSTPIN ); + GATE_T_248_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_248_A ); + GATE_T_248_I_2: INV port map ( I0=>inst_VPA_DQ, + O=>GATE_T_248_B ); + GATE_T_248_I_3: AND3 port map ( O=>T_248, + I0=>CLK_000_D_1_busQ, + I2=>GATE_T_248_A, + I1=>GATE_T_248_B ); + GATE_T_249_I_1: NOR3 port map ( O=>T_249, + I2=>cpu_est_1_busQ, + I1=>cpu_est_0_busQ, + I0=>cpu_est_2_busQ ); + GATE_T_250_I_1: INV port map ( I0=>VMAQ, + O=>GATE_T_250_A ); + GATE_T_250_I_2: AND3 port map ( O=>T_250, + I2=>RSTPIN, + I1=>cpu_est_3_busQ, + I0=>GATE_T_250_A ); + GATE_T_251_I_1: OR2 port map ( O=>T_251, + I1=>T_63, + I0=>T_62 ); + GATE_T_252_I_1: OR2 port map ( O=>T_252, + I1=>T_61, + I0=>T_60 ); + GATE_T_253_I_1: OR2 port map ( O=>T_253, + I1=>T_59, + I0=>T_58 ); + GATE_T_254_I_1: OR2 port map ( O=>T_254, + I1=>T_57, + I0=>T_56 ); + GATE_T_255_I_1: AND2 port map ( O=>T_255, + I1=>inst_CLK_030_HQ, + I0=>GATE_T_255_A ); + GATE_T_255_I_2: INV port map ( O=>GATE_T_255_A, + I0=>AS_000PIN ); + GATE_T_256_I_1: AND2 port map ( O=>T_256, + I1=>CYCLE_DMA_1_busQ, + I0=>GATE_T_256_A ); + GATE_T_256_I_2: INV port map ( O=>GATE_T_256_A, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_257_I_1: AND2 port map ( O=>T_257, + I1=>RSTPIN, + I0=>GATE_T_257_A ); + GATE_T_257_I_2: INV port map ( O=>GATE_T_257_A, + I0=>BGACK_030Q ); + GATE_T_258_I_1: AND2 port map ( O=>T_258, + I1=>inst_CLK_030_HQ, + I0=>GATE_T_258_A ); + GATE_T_258_I_2: INV port map ( O=>GATE_T_258_A, + I0=>AS_000PIN ); + GATE_T_259_I_1: AND2 port map ( O=>T_259, + I1=>CYCLE_DMA_0_busQ, + I0=>GATE_T_259_A ); + GATE_T_259_I_2: INV port map ( O=>GATE_T_259_A, + I0=>CYCLE_DMA_1_busQ ); + GATE_T_260_I_1: AND2 port map ( O=>T_260, + I1=>RSTPIN, + I0=>GATE_T_260_A ); + GATE_T_260_I_2: INV port map ( O=>GATE_T_260_A, + I0=>BGACK_030Q ); + GATE_T_261_I_1: AND2 port map ( O=>T_261, + I1=>inst_CLK_030_HQ, + I0=>GATE_T_261_A ); + GATE_T_261_I_2: INV port map ( O=>GATE_T_261_A, + I0=>AS_000PIN ); + GATE_T_262_I_1: AND2 port map ( O=>T_262, + I1=>CYCLE_DMA_1_busQ, + I0=>GATE_T_262_A ); + GATE_T_262_I_2: INV port map ( O=>GATE_T_262_A, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_263_I_1: AND2 port map ( O=>T_263, + I1=>RSTPIN, + I0=>GATE_T_263_A ); + GATE_T_263_I_2: INV port map ( O=>GATE_T_263_A, + I0=>BGACK_030Q ); + GATE_T_264_I_1: AND2 port map ( O=>T_264, + I1=>inst_CLK_030_HQ, + I0=>GATE_T_264_A ); + GATE_T_264_I_2: INV port map ( O=>GATE_T_264_A, + I0=>AS_000PIN ); + GATE_T_265_I_1: AND2 port map ( O=>T_265, + I1=>CYCLE_DMA_0_busQ, + I0=>GATE_T_265_A ); + GATE_T_265_I_2: INV port map ( O=>GATE_T_265_A, + I0=>CYCLE_DMA_1_busQ ); + GATE_T_266_I_1: AND2 port map ( O=>T_266, + I1=>RSTPIN, + I0=>GATE_T_266_A ); + GATE_T_266_I_2: INV port map ( O=>GATE_T_266_A, + I0=>BGACK_030Q ); + GATE_T_267_I_1: NOR2 port map ( O=>T_267, + I1=>UDS_000PIN, + I0=>AS_000PIN ); + GATE_T_268_I_1: AND2 port map ( O=>T_268, + I1=>CYCLE_DMA_1_busQ, + I0=>GATE_T_268_A ); + GATE_T_268_I_2: INV port map ( O=>GATE_T_268_A, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_269_I_1: NOR2 port map ( O=>T_269, + I1=>inst_AS_000_DMAQ, + I0=>BGACK_030Q ); + GATE_T_270_I_1: AND2 port map ( O=>T_270, + I1=>RSTPIN, + I0=>GATE_T_270_A ); + GATE_T_270_I_2: INV port map ( O=>GATE_T_270_A, + I0=>CLK_030PIN ); + GATE_T_271_I_1: NOR2 port map ( O=>T_271, + I1=>UDS_000PIN, + I0=>AS_000PIN ); + GATE_T_272_I_1: AND2 port map ( O=>T_272, + I1=>CYCLE_DMA_0_busQ, + I0=>GATE_T_272_A ); + GATE_T_272_I_2: INV port map ( O=>GATE_T_272_A, + I0=>CYCLE_DMA_1_busQ ); + GATE_T_273_I_1: NOR2 port map ( O=>T_273, + I1=>inst_AS_000_DMAQ, + I0=>BGACK_030Q ); + GATE_T_274_I_1: AND2 port map ( O=>T_274, + I1=>RSTPIN, + I0=>GATE_T_274_A ); + GATE_T_274_I_2: INV port map ( O=>GATE_T_274_A, + I0=>CLK_030PIN ); + GATE_T_275_I_1: NOR2 port map ( O=>T_275, + I1=>LDS_000PIN, + I0=>AS_000PIN ); + GATE_T_276_I_1: AND2 port map ( O=>T_276, + I1=>CYCLE_DMA_1_busQ, + I0=>GATE_T_276_A ); + GATE_T_276_I_2: INV port map ( O=>GATE_T_276_A, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_277_I_1: NOR2 port map ( O=>T_277, + I1=>inst_AS_000_DMAQ, + I0=>BGACK_030Q ); + GATE_T_278_I_1: AND2 port map ( O=>T_278, + I1=>RSTPIN, + I0=>GATE_T_278_A ); + GATE_T_278_I_2: INV port map ( O=>GATE_T_278_A, + I0=>CLK_030PIN ); + GATE_T_279_I_1: NOR2 port map ( O=>T_279, + I1=>LDS_000PIN, + I0=>AS_000PIN ); + GATE_T_280_I_1: AND2 port map ( O=>T_280, + I1=>CYCLE_DMA_0_busQ, + I0=>GATE_T_280_A ); + GATE_T_280_I_2: INV port map ( O=>GATE_T_280_A, + I0=>CYCLE_DMA_1_busQ ); + GATE_T_281_I_1: NOR2 port map ( O=>T_281, + I1=>inst_AS_000_DMAQ, + I0=>BGACK_030Q ); + GATE_T_282_I_1: AND2 port map ( O=>T_282, + I1=>RSTPIN, + I0=>GATE_T_282_A ); + GATE_T_282_I_2: INV port map ( O=>GATE_T_282_A, + I0=>CLK_030PIN ); + GATE_T_283_I_1: AND2 port map ( O=>T_283, + I1=>RST_DLY_0_busQ, + I0=>GATE_T_283_A ); + GATE_T_283_I_2: INV port map ( O=>GATE_T_283_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_284_I_1: AND2 port map ( O=>T_284, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_285_I_1: AND2 port map ( O=>T_285, + I1=>SM_AMIGA_i_7_busQ, + I0=>SM_AMIGA_6_busQ ); + GATE_T_286_I_1: AND2 port map ( O=>T_286, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_287_I_1: AND2 port map ( O=>T_287, + I1=>SM_AMIGA_i_7_busQ, + I0=>SM_AMIGA_6_busQ ); + GATE_T_288_I_1: AND2 port map ( O=>T_288, + I1=>RSTPIN, + I0=>GATE_T_288_A ); + GATE_T_288_I_2: INV port map ( O=>GATE_T_288_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_289_I_1: AND2 port map ( O=>T_289, + I1=>CLK_000_D_2_busQ, + I0=>GATE_T_289_A ); + GATE_T_289_I_2: INV port map ( O=>GATE_T_289_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_290_I_1: NOR2 port map ( O=>T_290, + I1=>CLK_000_D_1_busQ, + I0=>inst_AS_030_000_SYNCQ ); + GATE_T_291_I_1: AND2 port map ( O=>T_291, + I1=>RSTPIN, + I0=>nEXP_SPACEPIN ); + GATE_T_292_I_1: AND2 port map ( O=>T_292, + I1=>SM_AMIGA_i_7_busQ, + I0=>GATE_T_292_A ); + GATE_T_292_I_2: INV port map ( O=>GATE_T_292_A, + I0=>SM_AMIGA_5_busQ ); + GATE_T_293_I_1: NOR2 port map ( O=>T_293, + I1=>SM_AMIGA_4_busQ, + I0=>SM_AMIGA_0_busQ ); + GATE_T_294_I_1: AND2 port map ( O=>T_294, + I1=>RSTPIN, + I0=>GATE_T_294_A ); + GATE_T_294_I_2: INV port map ( O=>GATE_T_294_A, + I0=>SM_AMIGA_6_busQ ); + GATE_T_295_I_1: NOR2 port map ( O=>T_295, + I1=>SM_AMIGA_5_busQ, + I0=>SM_AMIGA_0_busQ ); + GATE_T_296_I_1: AND2 port map ( O=>T_296, + I1=>CLK_000_D_0_busQ, + I0=>GATE_T_296_A ); + GATE_T_296_I_2: INV port map ( O=>GATE_T_296_A, + I0=>SM_AMIGA_6_busQ ); + GATE_T_297_I_1: AND2 port map ( O=>T_297, + I1=>RSTPIN, + I0=>GATE_T_297_A ); + GATE_T_297_I_2: INV port map ( O=>GATE_T_297_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_298_I_1: AND2 port map ( O=>T_298, + I1=>SM_AMIGA_i_7_busQ, + I0=>GATE_T_298_A ); + GATE_T_298_I_2: INV port map ( O=>GATE_T_298_A, + I0=>SM_AMIGA_5_busQ ); + GATE_T_299_I_1: AND2 port map ( O=>T_299, + I1=>CLK_000_D_0_busQ, + I0=>GATE_T_299_A ); + GATE_T_299_I_2: INV port map ( O=>GATE_T_299_A, + I0=>SM_AMIGA_0_busQ ); + GATE_T_300_I_1: AND2 port map ( O=>T_300, + I1=>RSTPIN, + I0=>GATE_T_300_A ); + GATE_T_300_I_2: INV port map ( O=>GATE_T_300_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_301_I_1: AND2 port map ( O=>T_301, + I1=>RST_DLY_2_busQ, + I0=>RST_DLY_1_busQ ); + GATE_T_302_I_1: AND2 port map ( O=>T_302, + I1=>RST_DLY_0_busQ, + I0=>GATE_T_302_A ); + GATE_T_302_I_2: INV port map ( O=>GATE_T_302_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_303_I_1: AND2 port map ( O=>T_303, + I1=>CLK_000_D_1_busQ, + I0=>RSTPIN ); + GATE_T_304_I_1: AND2 port map ( O=>T_304, + I1=>CYCLE_DMA_1_busQ, + I0=>GATE_T_304_A ); + GATE_T_304_I_2: INV port map ( O=>GATE_T_304_A, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_305_I_1: AND2 port map ( O=>T_305, + I1=>RSTPIN, + I0=>GATE_T_305_A ); + GATE_T_305_I_2: INV port map ( O=>GATE_T_305_A, + I0=>BGACK_030Q ); + GATE_T_306_I_1: AND2 port map ( O=>T_306, + I1=>CLK_000_D_1_busQ, + I0=>CYCLE_DMA_1_busQ ); + GATE_T_307_I_1: AND2 port map ( O=>T_307, + I1=>RSTPIN, + I0=>GATE_T_307_A ); + GATE_T_307_I_2: INV port map ( O=>GATE_T_307_A, + I0=>BGACK_030Q ); + GATE_T_308_I_1: AND2 port map ( O=>T_308, + I1=>CYCLE_DMA_1_busQ, + I0=>GATE_T_308_A ); + GATE_T_308_I_2: INV port map ( O=>GATE_T_308_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_309_I_1: AND2 port map ( O=>T_309, + I1=>RSTPIN, + I0=>GATE_T_309_A ); + GATE_T_309_I_2: INV port map ( O=>GATE_T_309_A, + I0=>BGACK_030Q ); + GATE_T_310_I_1: AND2 port map ( O=>T_310, + I1=>CLK_000_D_0_busQ, + I0=>GATE_T_310_A ); + GATE_T_310_I_2: INV port map ( O=>GATE_T_310_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_311_I_1: AND2 port map ( O=>T_311, + I1=>CYCLE_DMA_0_busQ, + I0=>GATE_T_311_A ); + GATE_T_311_I_2: INV port map ( O=>GATE_T_311_A, + I0=>CYCLE_DMA_1_busQ ); + GATE_T_312_I_1: AND2 port map ( O=>T_312, + I1=>RSTPIN, + I0=>GATE_T_312_A ); + GATE_T_312_I_2: INV port map ( O=>GATE_T_312_A, + I0=>BGACK_030Q ); + GATE_T_313_I_1: AND2 port map ( O=>T_313, + I1=>CLK_000_D_1_busQ, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_314_I_1: AND2 port map ( O=>T_314, + I1=>RSTPIN, + I0=>GATE_T_314_A ); + GATE_T_314_I_2: INV port map ( O=>GATE_T_314_A, + I0=>BGACK_030Q ); + GATE_T_315_I_1: AND2 port map ( O=>T_315, + I1=>CYCLE_DMA_0_busQ, + I0=>GATE_T_315_A ); + GATE_T_315_I_2: INV port map ( O=>GATE_T_315_A, + I0=>CLK_000_D_0_busQ ); + GATE_T_316_I_1: AND2 port map ( O=>T_316, + I1=>RSTPIN, + I0=>GATE_T_316_A ); + GATE_T_316_I_2: INV port map ( O=>GATE_T_316_A, + I0=>BGACK_030Q ); + GATE_T_317_I_1: AND2 port map ( O=>T_317, + I1=>CLK_000_D_0_busQ, + I0=>GATE_T_317_A ); + GATE_T_317_I_2: INV port map ( O=>GATE_T_317_A, + I0=>AS_000PIN ); + GATE_T_318_I_1: NOR2 port map ( O=>T_318, + I1=>CLK_000_D_1_busQ, + I0=>CYCLE_DMA_0_busQ ); + GATE_T_319_I_1: AND2 port map ( O=>T_319, + I1=>RSTPIN, + I0=>GATE_T_319_A ); + GATE_T_319_I_2: INV port map ( O=>GATE_T_319_A, + I0=>BGACK_030Q ); + GATE_T_320_I_3: NAN3 port map ( O=>T_320, + I2=>RSTPIN, + I1=>GATE_T_320_B, + I0=>GATE_T_320_A ); + GATE_T_320_I_2: INV port map ( I0=>BGACK_030Q, + O=>GATE_T_320_B ); + GATE_T_320_I_1: INV port map ( I0=>AS_000PIN, + O=>GATE_T_320_A ); + GATE_T_321_I_1: OR3 port map ( O=>T_321, + I2=>T_107, + I1=>T_106, + I0=>T_108 ); + GATE_T_322_I_1: OR3 port map ( O=>T_322, + I2=>T_104, + I1=>T_103, + I0=>T_105 ); + GATE_T_323_I_1: OR2 port map ( O=>T_323, + I1=>AS_000PIN, + I0=>BGACK_030Q ); + GATE_T_324_I_1: OR2 port map ( O=>T_324, + I1=>T_112, + I0=>T_111 ); + GATE_T_325_I_1: OR2 port map ( O=>T_325, + I1=>T_110, + I0=>T_109 ); + GATE_T_326_I_1: OR2 port map ( O=>T_326, + I1=>T_118, + I0=>T_117 ); + GATE_T_327_I_1: OR2 port map ( O=>T_327, + I1=>T_116, + I0=>T_115 ); + GATE_T_328_I_1: OR2 port map ( O=>T_328, + I1=>T_114, + I0=>T_113 ); + GATE_T_329_I_1: AND2 port map ( O=>T_329, + I1=>BERRPIN, + I0=>GATE_T_329_A ); + GATE_T_329_I_2: INV port map ( O=>GATE_T_329_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_330_I_1: AND2 port map ( O=>T_330, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_330_A ); + GATE_T_330_I_2: INV port map ( O=>GATE_T_330_A, + I0=>inst_AS_030_D0Q ); + GATE_T_331_I_1: AND2 port map ( O=>T_331, + I1=>BGACK_030Q, + I0=>RSTPIN ); + GATE_T_332_I_1: AND2 port map ( O=>T_332, + I1=>nEXP_SPACEPIN, + I0=>GATE_T_332_A ); + GATE_T_332_I_2: INV port map ( O=>GATE_T_332_A, + I0=>FC_1XPIN ); + GATE_T_333_I_1: AND2 port map ( O=>T_333, + I1=>BERRPIN, + I0=>GATE_T_333_A ); + GATE_T_333_I_2: INV port map ( O=>GATE_T_333_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_334_I_1: AND2 port map ( O=>T_334, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_334_A ); + GATE_T_334_I_2: INV port map ( O=>GATE_T_334_A, + I0=>inst_AS_030_D0Q ); + GATE_T_335_I_1: AND2 port map ( O=>T_335, + I1=>BGACK_030Q, + I0=>A_DECODE_19XPIN ); + GATE_T_336_I_1: AND2 port map ( O=>T_336, + I1=>RSTPIN, + I0=>nEXP_SPACEPIN ); + GATE_T_337_I_1: AND2 port map ( O=>T_337, + I1=>BERRPIN, + I0=>GATE_T_337_A ); + GATE_T_337_I_2: INV port map ( O=>GATE_T_337_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_338_I_1: AND2 port map ( O=>T_338, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_338_A ); + GATE_T_338_I_2: INV port map ( O=>GATE_T_338_A, + I0=>inst_AS_030_D0Q ); + GATE_T_339_I_1: AND2 port map ( O=>T_339, + I1=>BGACK_030Q, + I0=>A_DECODE_18XPIN ); + GATE_T_340_I_1: AND2 port map ( O=>T_340, + I1=>RSTPIN, + I0=>nEXP_SPACEPIN ); + GATE_T_341_I_1: AND2 port map ( O=>T_341, + I1=>BERRPIN, + I0=>GATE_T_341_A ); + GATE_T_341_I_2: INV port map ( O=>GATE_T_341_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_342_I_1: AND2 port map ( O=>T_342, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_342_A ); + GATE_T_342_I_2: INV port map ( O=>GATE_T_342_A, + I0=>inst_AS_030_D0Q ); + GATE_T_343_I_1: AND2 port map ( O=>T_343, + I1=>BGACK_030Q, + I0=>GATE_T_343_A ); + GATE_T_343_I_2: INV port map ( O=>GATE_T_343_A, + I0=>A_DECODE_17XPIN ); + GATE_T_344_I_1: AND2 port map ( O=>T_344, + I1=>RSTPIN, + I0=>nEXP_SPACEPIN ); + GATE_T_345_I_1: AND2 port map ( O=>T_345, + I1=>BERRPIN, + I0=>GATE_T_345_A ); + GATE_T_345_I_2: INV port map ( O=>GATE_T_345_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_346_I_1: AND2 port map ( O=>T_346, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_346_A ); + GATE_T_346_I_2: INV port map ( O=>GATE_T_346_A, + I0=>inst_AS_030_D0Q ); + GATE_T_347_I_1: AND2 port map ( O=>T_347, + I1=>BGACK_030Q, + I0=>A_DECODE_16XPIN ); + GATE_T_348_I_1: AND2 port map ( O=>T_348, + I1=>RSTPIN, + I0=>nEXP_SPACEPIN ); + GATE_T_349_I_1: AND2 port map ( O=>T_349, + I1=>BERRPIN, + I0=>GATE_T_349_A ); + GATE_T_349_I_2: INV port map ( O=>GATE_T_349_A, + I0=>SM_AMIGA_i_7_busQ ); + GATE_T_350_I_1: AND2 port map ( O=>T_350, + I1=>inst_BGACK_030_INT_DQ, + I0=>GATE_T_350_A ); + GATE_T_350_I_2: INV port map ( O=>GATE_T_350_A, + I0=>inst_AS_030_D0Q ); + GATE_T_351_I_1: AND2 port map ( O=>T_351, + I1=>BGACK_030Q, + I0=>GATE_T_351_A ); + GATE_T_351_I_2: INV port map ( O=>GATE_T_351_A, + I0=>FC_0XPIN ); + GATE_T_352_I_1: AND2 port map ( O=>T_352, + I1=>RSTPIN, + I0=>nEXP_SPACEPIN ); + GATE_T_353_I_1: AND2 port map ( O=>T_353, + I1=>CLK_000_D_1_busQ, + I0=>GATE_T_353_A ); + GATE_T_353_I_2: INV port map ( O=>GATE_T_353_A, + I0=>cpu_est_1_busQ ); + GATE_T_354_I_1: AND2 port map ( O=>T_354, + I1=>cpu_est_0_busQ, + I0=>GATE_T_354_A ); + GATE_T_354_I_2: INV port map ( O=>GATE_T_354_A, + I0=>cpu_est_3_busQ ); + GATE_T_355_I_1: AND2 port map ( O=>T_355, + I1=>CLK_000_D_1_busQ, + I0=>cpu_est_2_busQ ); + GATE_T_356_I_1: AND2 port map ( O=>T_356, + I1=>cpu_est_1_busQ, + I0=>cpu_est_0_busQ ); + GATE_T_357_I_1: OR3 port map ( O=>T_357, + I2=>T_142, + I1=>T_141, + I0=>T_143 ); + GATE_T_358_I_1: OR3 port map ( O=>T_358, + I2=>T_139, + I1=>T_138, + I0=>T_140 ); + GATE_T_359_I_1: OR3 port map ( O=>T_359, + I2=>T_136, + I1=>T_135, + I0=>T_137 ); + GATE_T_360_I_1: AND2 port map ( O=>T_360, + I1=>IPL_D0_1_busQ, + I0=>GATE_T_360_A ); + GATE_T_360_I_2: INV port map ( O=>GATE_T_360_A, + I0=>IPL_D0_0_busQ ); + GATE_T_361_I_1: AND2 port map ( O=>T_361, + I1=>IPL_1XPIN, + I0=>GATE_T_361_A ); + GATE_T_361_I_2: INV port map ( O=>GATE_T_361_A, + I0=>IPL_0XPIN ); + GATE_T_362_I_1: AND2 port map ( O=>T_362, + I1=>RSTPIN, + I0=>IPL_2XPIN ); + GATE_T_363_I_1: NOR2 port map ( O=>T_363, + I1=>IPL_D0_1_busQ, + I0=>IPL_D0_0_busQ ); + GATE_T_364_I_1: NOR2 port map ( O=>T_364, + I1=>IPL_0XPIN, + I0=>IPL_1XPIN ); + GATE_T_365_I_1: AND2 port map ( O=>T_365, + I1=>RSTPIN, + I0=>IPL_2XPIN ); + GATE_T_366_I_1: AND2 port map ( O=>T_366, + I1=>IPL_D0_1_busQ, + I0=>GATE_T_366_A ); + GATE_T_366_I_2: INV port map ( O=>GATE_T_366_A, + I0=>IPL_D0_0_busQ ); + GATE_T_367_I_1: AND2 port map ( O=>T_367, + I1=>IPL_1XPIN, + I0=>GATE_T_367_A ); + GATE_T_367_I_2: INV port map ( O=>GATE_T_367_A, + I0=>IPL_0XPIN ); + GATE_T_368_I_1: AND2 port map ( O=>T_368, + I1=>RSTPIN, + I0=>GATE_T_368_A ); + GATE_T_368_I_2: INV port map ( O=>GATE_T_368_A, + I0=>IPL_2XPIN ); + GATE_T_369_I_1: NOR2 port map ( O=>T_369, + I1=>IPL_D0_1_busQ, + I0=>IPL_D0_0_busQ ); + GATE_T_370_I_1: NOR2 port map ( O=>T_370, + I1=>IPL_0XPIN, + I0=>IPL_1XPIN ); + GATE_T_371_I_1: AND2 port map ( O=>T_371, + I1=>RSTPIN, + I0=>GATE_T_371_A ); + GATE_T_371_I_2: INV port map ( O=>GATE_T_371_A, + I0=>IPL_2XPIN ); + GATE_T_372_I_1: OR3 port map ( O=>T_372, + I2=>T_152, + I1=>T_151, + I0=>T_153 ); + GATE_T_373_I_1: OR3 port map ( O=>T_373, + I2=>T_149, + I1=>T_148, + I0=>T_150 ); + GATE_T_374_I_1: OR3 port map ( O=>T_374, + I2=>T_146, + I1=>T_145, + I0=>T_147 ); + GATE_T_375_I_1: AND2 port map ( O=>T_375, + I1=>IPL_D0_0_busQ, + I0=>GATE_T_375_A ); + GATE_T_375_I_2: INV port map ( O=>GATE_T_375_A, + I0=>IPL_D0_1_busQ ); + GATE_T_376_I_1: AND2 port map ( O=>T_376, + I1=>IPL_0XPIN, + I0=>GATE_T_376_A ); + GATE_T_376_I_2: INV port map ( O=>GATE_T_376_A, + I0=>IPL_1XPIN ); + GATE_T_377_I_1: AND2 port map ( O=>T_377, + I1=>RSTPIN, + I0=>IPL_2XPIN ); + GATE_T_378_I_1: NOR2 port map ( O=>T_378, + I1=>IPL_D0_1_busQ, + I0=>IPL_D0_0_busQ ); + GATE_T_379_I_1: NOR2 port map ( O=>T_379, + I1=>IPL_0XPIN, + I0=>IPL_1XPIN ); + GATE_T_380_I_1: AND2 port map ( O=>T_380, + I1=>RSTPIN, + I0=>IPL_2XPIN ); + GATE_T_381_I_1: AND2 port map ( O=>T_381, + I1=>IPL_D0_0_busQ, + I0=>GATE_T_381_A ); + GATE_T_381_I_2: INV port map ( O=>GATE_T_381_A, + I0=>IPL_D0_1_busQ ); + GATE_T_382_I_1: AND2 port map ( O=>T_382, + I1=>IPL_0XPIN, + I0=>GATE_T_382_A ); + GATE_T_382_I_2: INV port map ( O=>GATE_T_382_A, + I0=>IPL_1XPIN ); + GATE_T_383_I_1: AND2 port map ( O=>T_383, + I1=>RSTPIN, + I0=>GATE_T_383_A ); + GATE_T_383_I_2: INV port map ( O=>GATE_T_383_A, + I0=>IPL_2XPIN ); + GATE_T_384_I_1: NOR2 port map ( O=>T_384, + I1=>IPL_D0_1_busQ, + I0=>IPL_D0_0_busQ ); + GATE_T_385_I_1: NOR2 port map ( O=>T_385, + I1=>IPL_0XPIN, + I0=>IPL_1XPIN ); + GATE_T_386_I_1: AND2 port map ( O=>T_386, + I1=>RSTPIN, + I0=>GATE_T_386_A ); + GATE_T_386_I_2: INV port map ( O=>GATE_T_386_A, + I0=>IPL_2XPIN ); + GATE_T_387_I_1: NOR2 port map ( O=>T_387, + I1=>CLK_000_D_1_busQ, + I0=>cpu_est_2_busQ ); + GATE_T_388_I_1: NOR2 port map ( O=>T_388, + I1=>cpu_est_1_busQ, + I0=>cpu_est_0_busQ ); + GATE_T_389_I_1: NOR2 port map ( O=>T_389, + I1=>cpu_est_3_busQ, + I0=>VMAQ ); + GATE_T_390_I_1: INV port map ( I0=>CLK_000_D_0_busQ, + O=>GATE_T_390_A ); + GATE_T_390_I_2: INV port map ( I0=>inst_VPA_DQ, + O=>GATE_T_390_B ); + GATE_T_390_I_3: AND3 port map ( O=>T_390, + I0=>CLK_000_D_1_busQ, + I2=>GATE_T_390_A, + I1=>GATE_T_390_B ); + GATE_T_391_I_1: INV port map ( I0=>cpu_est_2_busQ, + O=>GATE_T_391_A ); + GATE_T_391_I_2: AND3 port map ( O=>T_391, + I2=>cpu_est_1_busQ, + I1=>cpu_est_0_busQ, + I0=>GATE_T_391_A ); + GATE_T_392_I_1: INV port map ( I0=>cpu_est_3_busQ, + O=>GATE_T_392_A ); + GATE_T_392_I_2: AND3 port map ( O=>T_392, + I2=>VMAQ, + I1=>RSTPIN, + I0=>GATE_T_392_A ); + GATE_T_393_I_1: AND2 port map ( O=>T_393, + I1=>CLK_000_D_11_busQ, + I0=>GATE_T_393_A ); + GATE_T_393_I_2: INV port map ( O=>GATE_T_393_A, + I0=>CLK_000_D_10_busQ ); + GATE_T_394_I_1: AND2 port map ( O=>T_394, + I1=>RSTPIN, + I0=>GATE_T_394_A ); + GATE_T_394_I_2: INV port map ( O=>GATE_T_394_A, + I0=>CLK_030PIN ); + GATE_T_395_I_1: AND2 port map ( O=>T_395, + I1=>CLK_000_D_11_busQ, + I0=>GATE_T_395_A ); + GATE_T_395_I_2: INV port map ( O=>GATE_T_395_A, + I0=>CLK_000_D_10_busQ ); + GATE_T_396_I_1: AND2 port map ( O=>T_396, + I1=>inst_CLK_OUT_PRE_DQ, + I0=>RSTPIN ); + GATE_T_397_I_1: AND2 port map ( O=>T_397, + I1=>inst_AS_030_D0Q, + I0=>RSTPIN ); + GATE_T_398_I_1: AND2 port map ( O=>T_398, + I1=>nEXP_SPACEPIN, + I0=>GATE_T_398_A ); + GATE_T_398_I_2: INV port map ( O=>GATE_T_398_A, + I0=>BG_030PIN ); + GATE_T_399_I_1: NOR2 port map ( O=>T_399, + I1=>RW_000Q, + I0=>SM_AMIGA_0_busQ ); + GATE_T_400_I_1: AND2 port map ( O=>T_400, + I1=>RSTPIN, + I0=>GATE_T_400_A ); + GATE_T_400_I_2: INV port map ( O=>GATE_T_400_A, + I0=>SM_AMIGA_6_busQ ); + GATE_T_401_I_1: AND2 port map ( O=>T_401, + I1=>SM_AMIGA_i_7_busQ, + I0=>GATE_T_401_A ); + GATE_T_401_I_2: INV port map ( O=>GATE_T_401_A, + I0=>SM_AMIGA_0_busQ ); + GATE_T_402_I_1: AND2 port map ( O=>T_402, + I1=>SM_AMIGA_6_busQ, + I0=>CLK_000_D_0_busQ ); + GATE_T_403_I_1: AND2 port map ( O=>T_403, + I1=>RSTPIN, + I0=>GATE_T_403_A ); + GATE_T_403_I_2: INV port map ( O=>GATE_T_403_A, + I0=>CLK_000_D_1_busQ ); + GATE_T_404_I_1: OR3 port map ( O=>T_404, + I2=>T_181, + I1=>T_180, + I0=>T_182 ); + GATE_T_405_I_1: OR3 port map ( O=>T_405, + I2=>T_178, + I1=>T_177, + I0=>T_179 ); + GATE_T_406_I_1: OR3 port map ( O=>T_406, + I2=>T_175, + I1=>T_174, + I0=>T_176 ); + GATE_T_407_I_1: AND2 port map ( O=>T_407, + I1=>IPL_D0_1_busQ, + I0=>IPL_D0_0_busQ ); + GATE_T_408_I_1: AND2 port map ( O=>T_408, + I1=>IPL_0XPIN, + I0=>IPL_1XPIN ); + GATE_T_409_I_1: AND2 port map ( O=>T_409, + I1=>RSTPIN, + I0=>GATE_T_409_A ); + GATE_T_409_I_2: INV port map ( O=>GATE_T_409_A, + I0=>IPL_2XPIN ); + GATE_T_410_I_1: AND2 port map ( O=>T_410, + I1=>IPL_D0_1_busQ, + I0=>GATE_T_410_A ); + GATE_T_410_I_2: INV port map ( O=>GATE_T_410_A, + I0=>IPL_D0_0_busQ ); + GATE_T_411_I_1: AND2 port map ( O=>T_411, + I1=>IPL_1XPIN, + I0=>GATE_T_411_A ); + GATE_T_411_I_2: INV port map ( O=>GATE_T_411_A, + I0=>IPL_0XPIN ); + GATE_T_412_I_1: AND2 port map ( O=>T_412, + I1=>RSTPIN, + I0=>GATE_T_412_A ); + GATE_T_412_I_2: INV port map ( O=>GATE_T_412_A, + I0=>IPL_2XPIN ); + GATE_T_413_I_1: AND2 port map ( O=>T_413, + I1=>IPL_D0_0_busQ, + I0=>GATE_T_413_A ); + GATE_T_413_I_2: INV port map ( O=>GATE_T_413_A, + I0=>IPL_D0_1_busQ ); + GATE_T_414_I_1: AND2 port map ( O=>T_414, + I1=>IPL_0XPIN, + I0=>GATE_T_414_A ); + GATE_T_414_I_2: INV port map ( O=>GATE_T_414_A, + I0=>IPL_1XPIN ); + GATE_T_415_I_1: AND2 port map ( O=>T_415, + I1=>RSTPIN, + I0=>GATE_T_415_A ); + GATE_T_415_I_2: INV port map ( O=>GATE_T_415_A, + I0=>IPL_2XPIN ); + GATE_T_416_I_1: NOR2 port map ( O=>T_416, + I1=>IPL_D0_1_busQ, + I0=>IPL_D0_0_busQ ); + GATE_T_417_I_1: NOR2 port map ( O=>T_417, + I1=>IPL_0XPIN, + I0=>IPL_1XPIN ); + GATE_T_418_I_1: AND2 port map ( O=>T_418, + I1=>RSTPIN, + I0=>GATE_T_418_A ); + GATE_T_418_I_2: INV port map ( O=>GATE_T_418_A, + I0=>IPL_2XPIN ); + GATE_T_419_I_14: NOR4 port map ( O=>T_419, + I3=>AHIGH_30XPIN, + I2=>AHIGH_29XPIN, + I1=>AHIGH_28XPIN, + I0=>AHIGH_27XPIN ); + GATE_T_420_I_14: NOR4 port map ( O=>T_420, + I3=>AHIGH_26XPIN, + I2=>AHIGH_25XPIN, + I1=>AHIGH_24XPIN, + I0=>inst_AS_030_D0Q ); + GATE_T_421_I_1: AND4 port map ( O=>T_421, + I3=>A_DECODE_20XPIN, + I2=>A_DECODE_21XPIN, + I1=>A_DECODE_22XPIN, + I0=>A_DECODE_23XPIN ); + GATE_T_422_I_14: NOR4 port map ( O=>T_422, + I3=>AHIGH_30XPIN, + I2=>AHIGH_29XPIN, + I1=>AHIGH_28XPIN, + I0=>AHIGH_27XPIN ); + GATE_T_423_I_14: NOR4 port map ( O=>T_423, + I3=>AHIGH_26XPIN, + I2=>AHIGH_25XPIN, + I1=>AHIGH_24XPIN, + I0=>inst_AS_030_D0Q ); + GATE_T_424_I_1: AND4 port map ( O=>T_424, + I3=>A_DECODE_20XPIN, + I2=>A_DECODE_21XPIN, + I1=>A_DECODE_22XPIN, + I0=>A_DECODE_23XPIN ); + GATE_T_425_I_1: INV port map ( I0=>AS_030PIN, + O=>GATE_T_425_A ); + GATE_T_425_I_2: INV port map ( I0=>A_DECODE_16XPIN, + O=>GATE_T_425_B ); + GATE_T_425_I_3: AND3 port map ( O=>T_425, + I0=>FC_0XPIN, + I2=>GATE_T_425_A, + I1=>GATE_T_425_B ); + GATE_T_426_I_1: INV port map ( I0=>A_DECODE_18XPIN, + O=>GATE_T_426_A ); + GATE_T_426_I_2: INV port map ( I0=>A_DECODE_19XPIN, + O=>GATE_T_426_B ); + GATE_T_426_I_3: AND3 port map ( O=>T_426, + I0=>A_DECODE_17XPIN, + I2=>GATE_T_426_A, + I1=>GATE_T_426_B ); + GATE_T_427_I_1: INV port map ( I0=>FPU_SENSEPIN, + O=>GATE_T_427_A ); + GATE_T_427_I_2: AND3 port map ( O=>T_427, + I2=>BGACK_000PIN, + I1=>FC_1XPIN, + I0=>GATE_T_427_A ); + GATE_T_428_I_1: INV port map ( I0=>AS_030PIN, + O=>GATE_T_428_A ); + GATE_T_428_I_2: INV port map ( I0=>A_DECODE_16XPIN, + O=>GATE_T_428_B ); + GATE_T_428_I_3: AND3 port map ( O=>T_428, + I0=>FC_0XPIN, + I2=>GATE_T_428_A, + I1=>GATE_T_428_B ); + GATE_T_429_I_1: INV port map ( I0=>A_DECODE_18XPIN, + O=>GATE_T_429_A ); + GATE_T_429_I_2: INV port map ( I0=>A_DECODE_19XPIN, + O=>GATE_T_429_B ); + GATE_T_429_I_3: AND3 port map ( O=>T_429, + I0=>A_DECODE_17XPIN, + I2=>GATE_T_429_A, + I1=>GATE_T_429_B ); + GATE_T_430_I_1: AND3 port map ( O=>T_430, + I2=>BGACK_000PIN, + I1=>FC_1XPIN, + I0=>FPU_SENSEPIN ); + +end NetList; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index e6cfb84..eedb248 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Fri Aug 19 00:20:41 2016 +Design '68030_tk' created Fri Aug 19 00:39:35 2016 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index f539379..d82f5d4 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,238 +1,226 @@ -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ IPL_030_2_ A_DECODE_12_ A_DECODE_11_ IPL_2_ A_DECODE_10_ A_DECODE_9_ FC_1_ A_DECODE_8_ AS_030 A_DECODE_7_ AS_000 A_DECODE_6_ RW_000 A_DECODE_5_ DS_030 A_DECODE_4_ UDS_000 A_DECODE_3_ LDS_000 A_DECODE_2_ nEXP_SPACE A_0_ BERR IPL_030_1_ BG_030 IPL_030_0_ BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ -#$ NODES 694 N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 \ -# pos_clk_un10_sm_amiga_i_n cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i \ -# sm_amiga_srsts_i_0_m2_1__un0_n N_220 cpu_est_2_0_2__n vma_int_0_un3_n inst_BGACK_030_INTreg N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 \ -# N_291_0 vma_int_0_un0_n inst_VMA_INTreg N_192 AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n \ -# un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n \ -# N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ -# un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 rw_000_int_0_un0_n un4_as_000 N_27 \ -# N_228_i bgack_030_int_0_un3_n un10_ciin N_4 N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ -# un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n cpu_est_2_ pos_clk_un9_bg_030_n N_225_i \ -# as_000_int_0_un0_n cpu_est_3_ un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n cpu_est_0_ un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n cpu_est_1_ \ -# N_275_i ds_000_enable_0_un0_n inst_AS_000_INT clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ -# inst_AS_030_D0 rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n inst_AS_030_000_SYNC BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n inst_BGACK_030_INT_D cpu_est_i_2__n N_217_i \ -# un1_amiga_bus_enable_dma_high_0_m2_0__un1_n inst_AS_000_DMA nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n inst_DS_000_DMA rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n CYCLE_DMA_0_ \ -# cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n CYCLE_DMA_1_ cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n SIZE_DMA_0_ VPA_D_i N_195_0 amiga_bus_enable_dma_high_0_un3_n \ -# SIZE_DMA_1_ sm_amiga_i_3__n N_190_0 amiga_bus_enable_dma_high_0_un1_n inst_VPA_D sm_amiga_i_0__n N_157_i amiga_bus_enable_dma_high_0_un0_n inst_UDS_000_INT cpu_est_i_3__n \ -# N_154_i size_dma_0_0__un3_n inst_LDS_000_INT sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n inst_CLK_OUT_PRE_D RESET_OUT_i N_141_0 size_dma_0_0__un0_n \ -# CLK_000_D_10_ BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n CLK_000_D_11_ sm_amiga_i_2__n N_216_i size_dma_0_1__un1_n inst_DTACK_D0 sm_amiga_i_4__n \ -# N_337_i size_dma_0_1__un0_n inst_RESET_OUT clk_000_p_sync_i_10__n ds_000_dma_0_un3_n inst_CLK_OUT_PRE_50 sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n CLK_000_D_1_ \ -# sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n CLK_000_D_0_ clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n CLK_000_P_SYNC_10_ sm_amiga_i_6__n N_284_i \ -# as_000_dma_0_un1_n SM_AMIGA_5_ RW_i N_285_i as_000_dma_0_un0_n IPL_D0_0_ DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n IPL_D0_1_ \ -# LDS_000_INT_i N_280_i rw_000_dma_0_un1_n IPL_D0_2_ UDS_000_INT_i N_277_i rw_000_dma_0_un0_n CLK_000_D_2_ AS_030_i N_257_0 \ -# a0_dma_0_un3_n CLK_000_D_3_ AS_000_INT_i N_235_i a0_dma_0_un1_n CLK_000_D_4_ a_decode_i_19__n N_236_i a0_dma_0_un0_n CLK_000_D_5_ \ -# a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n CLK_000_D_6_ a_decode_i_16__n N_231_i CLK_000_D_7_ AS_000_i N_230_i a_decode_14__n \ -# CLK_000_D_8_ FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n CLK_000_D_9_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_000_D_12_ CLK_030_i N_37_0 \ -# pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n SM_AMIGA_0_ clk_000_d_i_10__n N_334_i inst_DSACK1_INTreg RW_000_i N_335_i a_decode_11__n \ -# a_i_1__n N_194_0 CLK_030_H_i N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i CLK_000_N_SYNC_0_ clk_000_d_i_0__n \ -# N_346_i a_decode_9__n SM_AMIGA_4_ clk_000_d_i_1__n N_163_i inst_DS_000_ENABLE AS_030_D0_i N_345_i a_decode_8__n CLK_000_N_SYNC_12_ \ -# size_dma_i_0__n N_344_i RST_DLY_0_ size_dma_i_1__n N_153_0 a_decode_7__n RST_DLY_1_ ahigh_i_30__n pos_clk_un3_as_030_d0_i_n RST_DLY_2_ \ -# ahigh_i_31__n N_293_0 a_decode_6__n CLK_000_P_SYNC_0_ ahigh_i_28__n N_233_i CLK_000_P_SYNC_1_ ahigh_i_29__n N_232_i a_decode_5__n \ -# CLK_000_P_SYNC_2_ ahigh_i_26__n N_290_0 CLK_000_P_SYNC_3_ ahigh_i_27__n VPA_c_i a_decode_4__n CLK_000_P_SYNC_4_ ahigh_i_24__n N_54_0 \ -# CLK_000_P_SYNC_5_ ahigh_i_25__n N_5_i a_decode_3__n CLK_000_P_SYNC_6_ N_212_i N_47_0 CLK_000_P_SYNC_7_ N_213_i N_7_i \ -# a_decode_2__n CLK_000_P_SYNC_8_ N_214_i N_46_0 CLK_000_P_SYNC_9_ N_18_i CLK_000_N_SYNC_1_ N_41_0 CLK_000_N_SYNC_2_ N_321_i \ -# N_10_i CLK_000_N_SYNC_3_ N_322_i N_43_0 CLK_000_N_SYNC_4_ un6_ds_030_i DTACK_c_i CLK_000_N_SYNC_5_ DS_000_DMA_i N_55_0 \ -# CLK_000_N_SYNC_6_ un4_as_000_i pos_clk_un6_bgack_000_0_n CLK_000_N_SYNC_7_ un6_as_030_i N_137_i CLK_000_N_SYNC_8_ un4_lds_000_i N_184_0 CLK_000_N_SYNC_9_ \ -# un4_uds_000_i N_349_i CLK_000_N_SYNC_10_ AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i CLK_000_N_SYNC_11_ AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i \ -# inst_RW_000_INT AS_000_c N_324_i inst_RW_000_DMA inst_CLK_000_NE_D0 RW_000_c N_199_0 inst_AMIGA_BUS_ENABLE_DMA_HIGH N_197_0 inst_A0_DMA \ -# N_196_0 pos_clk_a0_dma_3_n UDS_000_c LDS_000_c_i SM_AMIGA_6_ UDS_000_c_i inst_CLK_030_H LDS_000_c N_181_i SM_AMIGA_1_ \ -# N_347_i SM_AMIGA_3_ size_c_0__n N_348_i SM_AMIGA_2_ N_178_i pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 \ -# pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 N_341_i ahigh_c_26__n N_338_i \ -# N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 ahigh_c_28__n N_122_0 N_25 N_211_i \ -# ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n \ -# N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i \ -# un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i SM_AMIGA_i_7_ N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n G_134 \ -# N_3_i G_135 N_49_0 G_136 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i N_292 N_40_0 \ -# N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 N_35_0 \ -# N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n N_194_0_1 N_157 N_237_i_1 \ -# N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 \ -# N_184 a_decode_c_22__n N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 \ -# a_c_0__n N_176_i_1 N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 \ -# nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 \ -# BG_030_c un10_ciin_6 N_236 un10_ciin_7 N_277 BG_000DFFreg un10_ciin_8 N_281 un10_ciin_9 N_282 \ -# un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 CLK_030_c N_347_2 N_319 \ -# pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c un22_berr_1_0 N_323 \ -# N_366_1 N_325 N_366_2 N_327 CLK_OUT_INTreg N_366_3 N_328 N_366_4 N_329 un1_SM_AMIGA_5_i_1 \ -# N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 IPL_030DFF_0_reg N_142_i_2 N_336 N_339_1 \ -# N_338 IPL_030DFF_1_reg N_280_1 N_339 N_280_2 N_341 IPL_030DFF_2_reg N_231_1 N_344 N_231_2 \ -# N_347 ipl_c_0__n N_230_1 N_348 N_230_2 pos_clk_un23_bgack_030_int_i_0_x2 ipl_c_1__n N_230_3 cpu_est_0_0_x2_0_x2_0_ N_226_1 \ -# pos_clk_CYCLE_DMA_5_0_i_x2 ipl_c_2__n N_226_2 pos_clk_CYCLE_DMA_5_1_i_x2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 \ -# un22_berr_1 N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 \ -# N_92_i_1 N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n \ -# N_10 RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 \ -# un1_SM_AMIGA_5 fc_c_1__n N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 \ -# N_290 N_222_1 N_18 N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i \ -# bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n \ -# N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 lds_000_int_0_un1_n N_345 \ -# N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 \ -# dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n \ -# N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 ipl_030_0_1__un0_n N_195 \ -# N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 \ -# cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n +#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 662 N_28 N_246_i bgack_030_int_0_un1_n N_17 sm_amiga_nss_i_0_0__n bgack_030_int_0_un0_n N_19 dsack1_int_0_un3_n N_23 N_220_i \ +# dsack1_int_0_un1_n N_24 N_219_i dsack1_int_0_un0_n N_25 N_218_i cpu_est_0_3__un3_n un1_amiga_bus_enable_low_i cpu_est_0_3__un1_n un21_fpu_cs_i \ +# N_224_i cpu_est_0_3__un0_n inst_BGACK_030_INTreg BGACK_030_INT_i N_222_i cpu_est_0_2__un3_n vcc_n_n AMIGA_BUS_ENABLE_DMA_LOW_i N_223_i cpu_est_0_2__un1_n \ +# inst_VMA_INTreg UDS_000_INT_i N_322_i cpu_est_0_2__un0_n gnd_n_n LDS_000_INT_i N_312_i cpu_est_0_1__un3_n un1_amiga_bus_enable_low N_131_i \ +# N_139_0 cpu_est_0_1__un1_n un6_as_030 N_132_i N_108_i cpu_est_0_1__un0_n un3_size RW_000_i N_258_i vma_int_0_un3_n \ +# un4_size a_i_1__n N_257_i vma_int_0_un1_n un4_uds_000 clk_000_d_i_11__n vma_int_0_un0_n un4_lds_000 sm_amiga_i_6__n N_245_i \ +# ipl_030_0_0__un3_n un4_as_000 clk_000_d_i_1__n nEXP_SPACE_c_i ipl_030_0_0__un1_n un10_ciin AS_030_000_SYNC_i un1_as_030_i ipl_030_0_0__un0_n un21_fpu_cs \ +# sm_amiga_i_0__n pos_clk_un3_as_030_d0_0_n ds_000_dma_0_un3_n un22_berr sm_amiga_i_3__n N_107_0 ds_000_dma_0_un1_n un6_ds_030 sm_amiga_i_i_7__n N_115_i \ +# ds_000_dma_0_un0_n cpu_est_3_ sm_amiga_i_5__n N_63_0 as_000_dma_0_un3_n cpu_est_0_ rst_dly_i_0__n N_278_0 as_000_dma_0_un1_n cpu_est_1_ \ +# rst_dly_i_1__n N_279_0 as_000_dma_0_un0_n cpu_est_2_ N_364_i_0 N_260_i a_decode_15__n inst_AS_000_INT cpu_est_i_0__n N_67_0 \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n pos_clk_rw_000_int_5_0_n a_decode_14__n inst_AS_030_D0 AS_030_i un1_SM_AMIGA_0_sqmuxa_1_0 inst_AS_030_000_SYNC FPU_SENSE_i un10_ciin_i \ +# a_decode_13__n inst_BGACK_030_INT_D N_157_i N_313_0 inst_AS_000_DMA a_decode_i_16__n N_4_i a_decode_12__n inst_DS_000_DMA a_decode_i_18__n \ +# N_48_0 CYCLE_DMA_0_ a_decode_i_19__n N_5_i a_decode_11__n CYCLE_DMA_1_ N_113_i N_47_0 SIZE_DMA_0_ N_114_i \ +# N_7_i a_decode_10__n SIZE_DMA_1_ AS_000_INT_i N_46_0 inst_VPA_D size_dma_i_1__n N_18_i a_decode_9__n inst_UDS_000_INT \ +# size_dma_i_0__n N_41_0 inst_LDS_000_INT RESET_OUT_i N_22_i a_decode_8__n inst_CLK_OUT_PRE_D cpu_est_i_1__n N_37_0 CLK_000_D_1_ \ +# cpu_est_i_2__n N_26_i a_decode_7__n CLK_000_D_10_ VPA_D_i N_33_0 CLK_000_D_11_ DTACK_D0_i BG_030_c_i a_decode_6__n \ +# inst_DTACK_D0 cpu_est_i_3__n pos_clk_un6_bg_030_i_n inst_RESET_OUT CLK_030_i pos_clk_un9_bg_030_0_n a_decode_5__n CLK_000_D_0_ clk_000_d_i_0__n N_10_i \ +# inst_CLK_OUT_PRE_50 clk_000_d_i_10__n N_43_0 a_decode_4__n IPL_D0_0_ AS_000_DMA_i VPA_c_i IPL_D0_1_ AS_000_i N_54_0 \ +# a_decode_3__n IPL_D0_2_ CLK_030_H_i un3_as_030_i CLK_000_D_2_ cycle_dma_i_0__n N_370_i a_decode_2__n CLK_000_D_3_ AS_030_D0_i \ +# pos_clk_un6_bgack_000_0_n CLK_000_D_4_ ahigh_i_30__n N_283_i CLK_000_D_5_ ahigh_i_31__n pos_clk_size_dma_6_0_0__n CLK_000_D_6_ ahigh_i_28__n N_345_i \ +# CLK_000_D_7_ ahigh_i_29__n pos_clk_size_dma_6_0_1__n CLK_000_D_8_ ahigh_i_26__n UDS_000_c_i CLK_000_D_9_ ahigh_i_27__n LDS_000_c_i CLK_000_D_12_ \ +# ahigh_i_24__n N_171_i pos_clk_un6_bg_030_n ahigh_i_25__n N_21_i inst_AMIGA_BUS_ENABLE_DMA_HIGH N_241_i N_38_0 inst_DSACK1_INTreg N_242_i \ +# DTACK_c_i pos_clk_ipl_n N_243_i N_55_0 inst_DS_000_ENABLE N_249_i SM_AMIGA_6_ un6_ds_030_i N_248_i SM_AMIGA_0_ \ +# DS_000_DMA_i pos_clk_un9_clk_000_pe_0_n SM_AMIGA_4_ un4_as_000_i N_250_i inst_RW_000_INT un6_as_030_i N_251_i inst_RW_000_DMA un4_lds_000_i \ +# cpu_est_2_0_1__n RST_DLY_0_ un4_uds_000_i N_253_i RST_DLY_1_ AS_030_c N_369_i RST_DLY_2_ cpu_est_2_0_2__n inst_A0_DMA \ +# AS_000_c N_254_i inst_CLK_030_H N_316_i SM_AMIGA_1_ RW_000_c N_256_i SM_AMIGA_5_ N_255_i SM_AMIGA_3_ \ +# N_317_i SM_AMIGA_2_ UDS_000_c N_267_i pos_clk_ds_000_dma_4_n N_266_i N_3 LDS_000_c N_57_0 N_8 \ +# N_151_0 size_c_0__n N_321_i N_158_i size_c_1__n VMA_INT_i N_361_i ahigh_c_24__n N_362_i N_27 \ +# N_169_i ahigh_c_25__n N_186_0 N_195_0 ahigh_c_26__n N_196_0 ahigh_c_27__n N_263_i N_262_i ahigh_c_28__n \ +# N_323_0 N_101_i ahigh_c_29__n N_366_i N_182_i ahigh_c_30__n pos_clk_un23_bgack_030_int_i_0_0_n N_310_i ahigh_c_31__n N_359_i \ +# N_144_0 CLK_OUT_PRE_D_i N_142_0 N_311_i N_319_i N_93_i N_272_0 N_290_i N_273_0 N_346_i \ +# pos_clk_ds_000_dma_4_0_n N_268_i N_269_i SM_AMIGA_i_7_ sm_amiga_nss_0_3__n N_341_i N_238_i N_239_i sm_amiga_nss_0_2__n N_263 \ +# N_235_i G_116 N_236_i G_117 sm_amiga_nss_0_4__n G_118 N_234_i pos_clk_un23_bgack_030_int_i_0_n sm_amiga_nss_0_5__n N_272 \ +# N_231_i N_273 N_232_i sm_amiga_nss_0_6__n N_313 N_230_i a_decode_c_16__n sm_amiga_nss_0_7__n N_226_i N_108 \ +# a_decode_c_17__n N_331_i N_319 N_142 a_decode_c_18__n un1_as_000_i N_144 N_27_i N_322 a_decode_c_19__n \ +# N_30_0 N_169 ipl_c_i_0__n N_195 a_decode_c_20__n N_51_0 N_323 N_3_i N_209 a_decode_c_21__n \ +# N_49_0 N_218 N_8_i N_224 a_decode_c_22__n N_45_0 N_226 sm_amiga_nss_i_0_1_0__n N_331 a_decode_c_23__n \ +# sm_amiga_nss_i_0_2_0__n N_229 sm_amiga_nss_i_0_3_0__n N_230 a_c_0__n sm_amiga_nss_i_0_4_0__n N_231 sm_amiga_nss_i_0_5_0__n N_232 a_c_1__n \ +# pos_clk_un10_sm_amiga_i_1_n N_233 un10_ciin_1 N_234 nEXP_SPACE_c un10_ciin_2 N_235 un10_ciin_3 N_236 BERR_c \ +# un10_ciin_4 N_238 un10_ciin_5 N_239 BG_030_c un10_ciin_6 N_240 un10_ciin_7 N_251 BG_000DFFreg \ +# un10_ciin_8 N_262 un10_ciin_9 N_341 un10_ciin_10 N_268 BGACK_000_c un10_ciin_11 N_269 pos_clk_un23_bgack_030_int_i_0_0_1_n \ +# N_282 CLK_030_c pos_clk_un23_bgack_030_int_i_0_0_2_n N_346 N_60_i_1 N_290 N_60_i_2 N_310 N_248_1 N_311 \ +# CLK_OSZI_c N_248_2 N_355 N_249_1 N_356 N_249_2 N_359 CLK_OUT_INTreg N_361_1 N_360 \ +# N_361_2 N_365 N_157_1 N_366 FPU_SENSE_c N_157_2 pos_clk_un23_bgack_030_int_i_0_o2_2_x2 N_157_3 pos_clk_CYCLE_DMA_5_1_i_0_x2 IPL_030DFF_0_reg \ +# N_157_4 N_248 N_260_1 N_249 IPL_030DFF_1_reg N_260_2 N_369 un21_fpu_cs_1 N_196 IPL_030DFF_2_reg \ +# un22_berr_1_0 N_186 N_275_i_1 N_361 ipl_c_0__n N_275_i_2 N_362 N_274_i_1 N_151 ipl_c_1__n \ +# N_274_i_2 N_321 N_115_1 N_266 ipl_c_2__n N_115_2 N_267 N_332_1 N_255 N_246_1 \ +# N_256 DTACK_c N_246_2 N_253 N_246_3 N_254 N_246_4 cpu_est_2_2__n N_332_4_1 cpu_est_2_1__n \ +# VPA_c N_332_4_2 N_250 N_273_0_1 pos_clk_un9_clk_000_pe_n N_276_i_1 N_364 RST_c N_277_i_1 N_21 \ +# N_314_i_1 N_171 N_356_1 pos_clk_size_dma_6_1__n RW_c N_282_1 N_345 N_251_1 pos_clk_size_dma_6_0__n fc_c_0__n \ +# pos_clk_un6_bg_030_1_n N_283 N_240_1 pos_clk_un6_bgack_000_n fc_c_1__n N_238_1 N_370 N_233_1 N_259 N_231_1 \ +# N_10 AMIGA_BUS_DATA_DIR_c N_224_1 pos_clk_un9_bg_030_n N_218_1 N_4 pos_clk_ipl_1_n N_114 rw_000_dma_0_un3_n N_278 \ +# rw_000_dma_0_un1_n N_5 N_25_i rw_000_dma_0_un0_n N_113 N_34_0 lds_000_int_0_un3_n N_279 N_24_i lds_000_int_0_un1_n \ +# N_6 N_35_0 lds_000_int_0_un0_n N_115 N_23_i ipl_030_0_1__un3_n N_63 N_36_0 ipl_030_0_1__un1_n N_7 \ +# N_19_i ipl_030_0_1__un0_n pos_clk_un3_as_030_d0_n N_40_0 amiga_bus_enable_dma_high_0_un3_n N_67 N_17_i amiga_bus_enable_dma_high_0_un1_n N_18 N_42_0 \ +# amiga_bus_enable_dma_high_0_un0_n pos_clk_rw_000_int_5_n ipl_c_i_1__n amiga_bus_enable_dma_low_0_un3_n un1_SM_AMIGA_0_sqmuxa_1 N_52_0 amiga_bus_enable_dma_low_0_un1_n N_22 ipl_c_i_2__n amiga_bus_enable_dma_low_0_un0_n \ +# pos_clk_a0_dma_3_n N_53_0 uds_000_int_0_un3_n N_363 N_28_i uds_000_int_0_un1_n N_26 N_31_0 uds_000_int_0_un0_n N_157 \ +# N_29_i ipl_030_0_2__un3_n N_260 N_32_0 ipl_030_0_2__un1_n un22_berr_1 a_c_i_0__n ipl_030_0_2__un0_n N_219 size_c_i_1__n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_139 pos_clk_un10_sm_amiga_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_220 N_332_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_222 N_240_i as_000_int_0_un3_n \ +# N_223 N_315_0 as_000_int_0_un1_n N_368 N_281_0 as_000_int_0_un0_n N_257 N_270_i ds_000_enable_0_un3_n N_258 \ +# N_282_i ds_000_enable_0_un1_n N_312 AMIGA_BUS_DATA_DIR_c_0 ds_000_enable_0_un0_n N_143 RW_c_i as_030_000_sync_0_un3_n N_332 N_140_0 \ +# as_030_000_sync_0_un1_n N_332_4 N_353_i as_030_000_sync_0_un0_n N_246 N_143_0 rw_000_int_0_un3_n N_180 sm_amiga_i_1__n rw_000_int_0_un1_n \ +# N_320 N_320_i rw_000_int_0_un0_n N_244 N_357_i a0_dma_0_un3_n N_334 N_356_i a0_dma_0_un1_n N_335 \ +# N_156_0 a0_dma_0_un0_n N_159 sm_amiga_i_4__n bg_000_0_un3_n N_156 N_159_i bg_000_0_un1_n N_357 sm_amiga_i_2__n \ +# bg_000_0_un0_n N_353 N_180_i size_dma_0_1__un3_n N_140 N_334_i size_dma_0_1__un1_n N_270 N_335_i size_dma_0_1__un0_n \ +# N_281 N_244_i size_dma_0_0__un3_n N_131 N_233_i size_dma_0_0__un1_n N_132 N_355_i size_dma_0_0__un0_n N_29 \ +# N_229_i bgack_030_int_0_un3_n .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ A_DECODE_17_.BLIF A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ - FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_166.BLIF N_32_0.BLIF cpu_est_0_3__un0_n.BLIF N_141.BLIF a_c_i_0__n.BLIF cpu_est_0_2__un3_n.BLIF N_226.BLIF \ - size_c_i_1__n.BLIF cpu_est_0_2__un1_n.BLIF N_357.BLIF pos_clk_un10_sm_amiga_i_n.BLIF cpu_est_0_2__un0_n.BLIF N_219.BLIF N_258_0.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_217.BLIF \ - N_357_i.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_221.BLIF N_254_i.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_220.BLIF cpu_est_2_0_2__n.BLIF vma_int_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF \ - N_223.BLIF N_315_i.BLIF vma_int_0_un1_n.BLIF vcc_n_n.BLIF N_343.BLIF N_291_0.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.BLIF N_192.BLIF \ - AS_030_000_SYNC_i.BLIF cpu_est_0_1__un3_n.BLIF gnd_n_n.BLIF N_164.BLIF N_146_0.BLIF cpu_est_0_1__un1_n.BLIF un1_amiga_bus_enable_dma_high_0__n.BLIF N_291.BLIF N_149_i.BLIF \ - cpu_est_0_1__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_315.BLIF N_164_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF un6_as_030.BLIF cpu_est_2_2__n.BLIF N_166_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF \ - un3_size.BLIF N_254.BLIF N_172_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF un4_size.BLIF N_258.BLIF N_176_i.BLIF rw_000_int_0_un3_n.BLIF un4_uds_000.BLIF \ - N_29.BLIF N_186_0.BLIF rw_000_int_0_un1_n.BLIF un4_lds_000.BLIF N_28.BLIF N_192_0.BLIF rw_000_int_0_un0_n.BLIF un4_as_000.BLIF N_27.BLIF \ - N_228_i.BLIF bgack_030_int_0_un3_n.BLIF un10_ciin.BLIF N_4.BLIF N_227_i.BLIF bgack_030_int_0_un1_n.BLIF un21_fpu_cs.BLIF N_17.BLIF N_343_i.BLIF \ - bgack_030_int_0_un0_n.BLIF un22_berr.BLIF N_21.BLIF as_000_int_0_un3_n.BLIF un6_ds_030.BLIF N_26.BLIF N_223_i.BLIF as_000_int_0_un1_n.BLIF cpu_est_2_.BLIF \ - pos_clk_un9_bg_030_n.BLIF N_225_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_3_.BLIF un1_amiga_bus_enable_low_i.BLIF N_224_i.BLIF ds_000_enable_0_un3_n.BLIF cpu_est_0_.BLIF un21_fpu_cs_i.BLIF \ - N_226_i.BLIF ds_000_enable_0_un1_n.BLIF cpu_est_1_.BLIF N_275_i.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_000_INT.BLIF clk_000_n_sync_i_12__n.BLIF N_220_i.BLIF as_030_000_sync_0_un3_n.BLIF \ - inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF N_221_i.BLIF as_030_000_sync_0_un1_n.BLIF inst_AS_030_D0.BLIF rst_dly_i_1__n.BLIF N_222_i.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ - BERR_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF inst_BGACK_030_INT_D.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_AS_000_DMA.BLIF nEXP_SPACE_i.BLIF N_215_i.BLIF \ - un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF inst_DS_000_DMA.BLIF rst_dly_i_0__n.BLIF N_219_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF CYCLE_DMA_0_.BLIF cpu_est_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF CYCLE_DMA_1_.BLIF \ - cpu_est_i_0__n.BLIF N_200_i.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF SIZE_DMA_0_.BLIF VPA_D_i.BLIF N_195_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SIZE_DMA_1_.BLIF sm_amiga_i_3__n.BLIF \ - N_190_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF inst_VPA_D.BLIF sm_amiga_i_0__n.BLIF N_157_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF inst_UDS_000_INT.BLIF cpu_est_i_3__n.BLIF N_154_i.BLIF \ - size_dma_0_0__un3_n.BLIF inst_LDS_000_INT.BLIF sm_amiga_i_1__n.BLIF N_340_i.BLIF size_dma_0_0__un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF RESET_OUT_i.BLIF N_141_0.BLIF size_dma_0_0__un0_n.BLIF \ - CLK_000_D_10_.BLIF BGACK_030_INT_i.BLIF un3_as_030_i.BLIF size_dma_0_1__un3_n.BLIF CLK_000_D_11_.BLIF sm_amiga_i_2__n.BLIF N_216_i.BLIF size_dma_0_1__un1_n.BLIF inst_DTACK_D0.BLIF \ - sm_amiga_i_4__n.BLIF N_337_i.BLIF size_dma_0_1__un0_n.BLIF inst_RESET_OUT.BLIF clk_000_p_sync_i_10__n.BLIF ds_000_dma_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF sm_amiga_i_5__n.BLIF un10_ciin_i.BLIF \ - ds_000_dma_0_un1_n.BLIF CLK_000_D_1_.BLIF sm_amiga_i_i_7__n.BLIF N_296_0.BLIF ds_000_dma_0_un0_n.BLIF CLK_000_D_0_.BLIF clk_000_d_i_11__n.BLIF un1_as_000_i.BLIF as_000_dma_0_un3_n.BLIF \ - CLK_000_P_SYNC_10_.BLIF sm_amiga_i_6__n.BLIF N_284_i.BLIF as_000_dma_0_un1_n.BLIF SM_AMIGA_5_.BLIF RW_i.BLIF N_285_i.BLIF as_000_dma_0_un0_n.BLIF IPL_D0_0_.BLIF \ - DS_000_ENABLE_1_sqmuxa_i.BLIF N_292_0.BLIF rw_000_dma_0_un3_n.BLIF IPL_D0_1_.BLIF LDS_000_INT_i.BLIF N_280_i.BLIF rw_000_dma_0_un1_n.BLIF IPL_D0_2_.BLIF UDS_000_INT_i.BLIF \ - N_277_i.BLIF rw_000_dma_0_un0_n.BLIF CLK_000_D_2_.BLIF AS_030_i.BLIF N_257_0.BLIF a0_dma_0_un3_n.BLIF CLK_000_D_3_.BLIF AS_000_INT_i.BLIF N_235_i.BLIF \ - a0_dma_0_un1_n.BLIF CLK_000_D_4_.BLIF a_decode_i_19__n.BLIF N_236_i.BLIF a0_dma_0_un0_n.BLIF CLK_000_D_5_.BLIF a_decode_i_18__n.BLIF cpu_est_2_0_1__n.BLIF a_decode_15__n.BLIF \ - CLK_000_D_6_.BLIF a_decode_i_16__n.BLIF N_231_i.BLIF CLK_000_D_7_.BLIF AS_000_i.BLIF N_230_i.BLIF a_decode_14__n.BLIF CLK_000_D_8_.BLIF FPU_SENSE_i.BLIF \ - pos_clk_un4_clk_000_pe_0_n.BLIF CLK_000_D_9_.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_22_i.BLIF a_decode_13__n.BLIF CLK_000_D_12_.BLIF CLK_030_i.BLIF N_37_0.BLIF pos_clk_un6_bg_030_n.BLIF \ - DTACK_D0_i.BLIF a_decode_12__n.BLIF SM_AMIGA_0_.BLIF clk_000_d_i_10__n.BLIF N_334_i.BLIF inst_DSACK1_INTreg.BLIF RW_000_i.BLIF N_335_i.BLIF a_decode_11__n.BLIF \ - a_i_1__n.BLIF N_194_0.BLIF CLK_030_H_i.BLIF N_191_0.BLIF a_decode_10__n.BLIF pos_clk_ipl_n.BLIF AS_000_DMA_i.BLIF un1_SM_AMIGA_5_i.BLIF CLK_000_N_SYNC_0_.BLIF \ - clk_000_d_i_0__n.BLIF N_346_i.BLIF a_decode_9__n.BLIF SM_AMIGA_4_.BLIF clk_000_d_i_1__n.BLIF N_163_i.BLIF inst_DS_000_ENABLE.BLIF AS_030_D0_i.BLIF N_345_i.BLIF \ - a_decode_8__n.BLIF CLK_000_N_SYNC_12_.BLIF size_dma_i_0__n.BLIF N_344_i.BLIF RST_DLY_0_.BLIF size_dma_i_1__n.BLIF N_153_0.BLIF a_decode_7__n.BLIF RST_DLY_1_.BLIF \ - ahigh_i_30__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF RST_DLY_2_.BLIF ahigh_i_31__n.BLIF N_293_0.BLIF a_decode_6__n.BLIF CLK_000_P_SYNC_0_.BLIF ahigh_i_28__n.BLIF N_233_i.BLIF \ - CLK_000_P_SYNC_1_.BLIF ahigh_i_29__n.BLIF N_232_i.BLIF a_decode_5__n.BLIF CLK_000_P_SYNC_2_.BLIF ahigh_i_26__n.BLIF N_290_0.BLIF CLK_000_P_SYNC_3_.BLIF ahigh_i_27__n.BLIF \ - VPA_c_i.BLIF a_decode_4__n.BLIF CLK_000_P_SYNC_4_.BLIF ahigh_i_24__n.BLIF N_54_0.BLIF CLK_000_P_SYNC_5_.BLIF ahigh_i_25__n.BLIF N_5_i.BLIF a_decode_3__n.BLIF \ - CLK_000_P_SYNC_6_.BLIF N_212_i.BLIF N_47_0.BLIF CLK_000_P_SYNC_7_.BLIF N_213_i.BLIF N_7_i.BLIF a_decode_2__n.BLIF CLK_000_P_SYNC_8_.BLIF N_214_i.BLIF \ - N_46_0.BLIF CLK_000_P_SYNC_9_.BLIF N_18_i.BLIF CLK_000_N_SYNC_1_.BLIF N_41_0.BLIF CLK_000_N_SYNC_2_.BLIF N_321_i.BLIF N_10_i.BLIF CLK_000_N_SYNC_3_.BLIF \ - N_322_i.BLIF N_43_0.BLIF CLK_000_N_SYNC_4_.BLIF un6_ds_030_i.BLIF DTACK_c_i.BLIF CLK_000_N_SYNC_5_.BLIF DS_000_DMA_i.BLIF N_55_0.BLIF CLK_000_N_SYNC_6_.BLIF \ - un4_as_000_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF CLK_000_N_SYNC_7_.BLIF un6_as_030_i.BLIF N_137_i.BLIF CLK_000_N_SYNC_8_.BLIF un4_lds_000_i.BLIF N_184_0.BLIF CLK_000_N_SYNC_9_.BLIF \ - un4_uds_000_i.BLIF N_349_i.BLIF CLK_000_N_SYNC_10_.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_185_i.BLIF CLK_000_N_SYNC_11_.BLIF AS_030_c.BLIF N_187_0.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ - N_203_i.BLIF inst_RW_000_INT.BLIF AS_000_c.BLIF N_324_i.BLIF inst_RW_000_DMA.BLIF inst_CLK_000_NE_D0.BLIF RW_000_c.BLIF N_199_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ - N_197_0.BLIF inst_A0_DMA.BLIF N_196_0.BLIF pos_clk_a0_dma_3_n.BLIF UDS_000_c.BLIF LDS_000_c_i.BLIF SM_AMIGA_6_.BLIF UDS_000_c_i.BLIF inst_CLK_030_H.BLIF \ - LDS_000_c.BLIF N_181_i.BLIF SM_AMIGA_1_.BLIF N_347_i.BLIF SM_AMIGA_3_.BLIF size_c_0__n.BLIF N_348_i.BLIF SM_AMIGA_2_.BLIF N_178_i.BLIF \ - pos_clk_ds_000_dma_4_n.BLIF size_c_1__n.BLIF VMA_INT_i.BLIF N_3.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_8.BLIF ahigh_c_24__n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF CLK_OUT_PRE_D_i.BLIF \ - ahigh_c_25__n.BLIF N_148_0.BLIF N_341_i.BLIF ahigh_c_26__n.BLIF N_338_i.BLIF N_339_i.BLIF N_19.BLIF ahigh_c_27__n.BLIF N_20.BLIF \ - N_336_i.BLIF N_24.BLIF ahigh_c_28__n.BLIF N_122_0.BLIF N_25.BLIF N_211_i.BLIF ahigh_c_29__n.BLIF N_332_i.BLIF ahigh_c_30__n.BLIF \ - N_331_i.BLIF N_120_0.BLIF ahigh_c_31__n.BLIF N_330_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_329_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_328_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ - N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_320_i.BLIF N_298_0.BLIF N_295_0.BLIF N_294_0.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ - N_206_i.BLIF N_283_i.BLIF SM_AMIGA_i_7_.BLIF N_122.BLIF N_281_i.BLIF pos_clk_size_dma_6_0__n.BLIF N_282_i.BLIF pos_clk_size_dma_6_1__n.BLIF G_134.BLIF \ - N_3_i.BLIF G_135.BLIF N_49_0.BLIF G_136.BLIF N_8_i.BLIF N_45_0.BLIF pos_clk_un23_bgack_030_int_i_1_n.BLIF N_19_i.BLIF N_292.BLIF \ - N_40_0.BLIF N_294.BLIF a_decode_c_16__n.BLIF N_20_i.BLIF N_295.BLIF N_39_0.BLIF N_296.BLIF a_decode_c_17__n.BLIF N_24_i.BLIF \ - N_298.BLIF N_35_0.BLIF N_120.BLIF a_decode_c_18__n.BLIF N_25_i.BLIF N_148.BLIF N_34_0.BLIF N_149.BLIF a_decode_c_19__n.BLIF \ - N_194_0_1.BLIF N_157.BLIF N_237_i_1.BLIF N_172.BLIF a_decode_c_20__n.BLIF N_237_i_2.BLIF N_176.BLIF N_238_i_1.BLIF N_178.BLIF \ - a_decode_c_21__n.BLIF N_238_i_2.BLIF N_181.BLIF N_144_i_1.BLIF N_184.BLIF a_decode_c_22__n.BLIF N_144_i_2.BLIF N_144_i_3.BLIF N_196.BLIF \ - a_decode_c_23__n.BLIF N_136_i_1.BLIF N_197.BLIF N_136_i_2.BLIF N_206.BLIF a_c_0__n.BLIF N_176_i_1.BLIF N_207.BLIF N_146_0_1.BLIF \ - N_211.BLIF a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_215.BLIF un10_ciin_1.BLIF N_222.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_224.BLIF \ - un10_ciin_3.BLIF N_225.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_227.BLIF un10_ciin_5.BLIF N_228.BLIF BG_030_c.BLIF un10_ciin_6.BLIF \ - N_236.BLIF un10_ciin_7.BLIF N_277.BLIF BG_000DFFreg.BLIF un10_ciin_8.BLIF N_281.BLIF un10_ciin_9.BLIF N_282.BLIF un10_ciin_10.BLIF \ - N_283.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_285.BLIF N_347_1.BLIF N_318.BLIF CLK_030_c.BLIF N_347_2.BLIF N_319.BLIF \ - pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF N_320.BLIF CLK_000_c.BLIF pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF N_321.BLIF un21_fpu_cs_1.BLIF N_322.BLIF CLK_OSZI_c.BLIF un22_berr_1_0.BLIF \ - N_323.BLIF N_366_1.BLIF N_325.BLIF N_366_2.BLIF N_327.BLIF CLK_OUT_INTreg.BLIF N_366_3.BLIF N_328.BLIF N_366_4.BLIF \ - N_329.BLIF un1_SM_AMIGA_5_i_1.BLIF N_330.BLIF FPU_SENSE_c.BLIF un1_SM_AMIGA_5_i_2.BLIF N_331.BLIF N_142_i_1.BLIF N_332.BLIF IPL_030DFF_0_reg.BLIF \ - N_142_i_2.BLIF N_336.BLIF N_339_1.BLIF N_338.BLIF IPL_030DFF_1_reg.BLIF N_280_1.BLIF N_339.BLIF N_280_2.BLIF N_341.BLIF \ - IPL_030DFF_2_reg.BLIF N_231_1.BLIF N_344.BLIF N_231_2.BLIF N_347.BLIF ipl_c_0__n.BLIF N_230_1.BLIF N_348.BLIF N_230_2.BLIF \ - pos_clk_un23_bgack_030_int_i_0_x2.BLIF ipl_c_1__n.BLIF N_230_3.BLIF cpu_est_0_0_x2_0_x2_0_.BLIF N_226_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF ipl_c_2__n.BLIF N_226_2.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ - N_226_3.BLIF N_199.BLIF N_239_i_1.BLIF N_324.BLIF DTACK_c.BLIF N_122_0_1.BLIF un22_berr_1.BLIF N_132_i_1.BLIF N_366.BLIF \ - N_120_0_1.BLIF N_335.BLIF N_106_i_1.BLIF N_208.BLIF VPA_c.BLIF N_103_i_1.BLIF N_203.BLIF N_92_i_1.BLIF N_187.BLIF \ - N_140_i_1.BLIF N_137.BLIF RST_c.BLIF N_138_i_1.BLIF N_349.BLIF N_344_1.BLIF pos_clk_un6_bgack_000_n.BLIF pos_clk_un6_bg_030_1_n.BLIF N_10.BLIF \ - RW_c.BLIF N_327_1.BLIF N_5.BLIF N_319_1.BLIF N_293.BLIF fc_c_0__n.BLIF N_285_1.BLIF N_6.BLIF N_277_1.BLIF \ - un1_SM_AMIGA_5.BLIF fc_c_1__n.BLIF N_236_1.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_228_1.BLIF N_7.BLIF N_225_1.BLIF pos_clk_un3_as_030_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ - N_224_1.BLIF N_290.BLIF N_222_1.BLIF N_18.BLIF N_215_1.BLIF DS_000_ENABLE_1_sqmuxa.BLIF pos_clk_ipl_1_n.BLIF N_232.BLIF bg_000_0_un3_n.BLIF \ - N_194.BLIF BG_030_c_i.BLIF bg_000_0_un1_n.BLIF N_233.BLIF pos_clk_un6_bg_030_i_n.BLIF bg_000_0_un0_n.BLIF N_275.BLIF pos_clk_un9_bg_030_0_n.BLIF uds_000_int_0_un3_n.BLIF \ - N_153.BLIF N_26_i.BLIF uds_000_int_0_un1_n.BLIF N_191.BLIF N_33_0.BLIF uds_000_int_0_un0_n.BLIF N_334.BLIF N_21_i.BLIF lds_000_int_0_un3_n.BLIF \ - N_146.BLIF N_38_0.BLIF lds_000_int_0_un1_n.BLIF N_345.BLIF N_17_i.BLIF lds_000_int_0_un0_n.BLIF N_346.BLIF N_42_0.BLIF dsack1_int_0_un3_n.BLIF \ - N_163.BLIF N_4_i.BLIF dsack1_int_0_un1_n.BLIF N_22.BLIF N_48_0.BLIF dsack1_int_0_un0_n.BLIF pos_clk_un4_clk_000_pe_n.BLIF ipl_c_i_0__n.BLIF ipl_030_0_2__un3_n.BLIF \ - cpu_est_2_1__n.BLIF N_51_0.BLIF ipl_030_0_2__un1_n.BLIF N_235.BLIF ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_284.BLIF N_52_0.BLIF ipl_030_0_1__un3_n.BLIF \ - N_190.BLIF ipl_c_i_2__n.BLIF ipl_030_0_1__un1_n.BLIF N_337.BLIF N_53_0.BLIF ipl_030_0_1__un0_n.BLIF N_195.BLIF N_27_i.BLIF ipl_030_0_0__un3_n.BLIF \ - N_340.BLIF N_30_0.BLIF ipl_030_0_0__un1_n.BLIF N_231.BLIF N_28_i.BLIF ipl_030_0_0__un0_n.BLIF N_230.BLIF N_31_0.BLIF cpu_est_0_3__un3_n.BLIF \ - N_280.BLIF N_29_i.BLIF cpu_est_0_3__un1_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN \ - SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN \ - A_0_.PIN BERR.PIN RW.PIN + FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_28.BLIF N_246_i.BLIF bgack_030_int_0_un1_n.BLIF N_17.BLIF sm_amiga_nss_i_0_0__n.BLIF bgack_030_int_0_un0_n.BLIF N_19.BLIF \ + dsack1_int_0_un3_n.BLIF N_23.BLIF N_220_i.BLIF dsack1_int_0_un1_n.BLIF N_24.BLIF N_219_i.BLIF dsack1_int_0_un0_n.BLIF N_25.BLIF N_218_i.BLIF \ + cpu_est_0_3__un3_n.BLIF un1_amiga_bus_enable_low_i.BLIF cpu_est_0_3__un1_n.BLIF un21_fpu_cs_i.BLIF N_224_i.BLIF cpu_est_0_3__un0_n.BLIF inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i.BLIF N_222_i.BLIF \ + cpu_est_0_2__un3_n.BLIF vcc_n_n.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_223_i.BLIF cpu_est_0_2__un1_n.BLIF inst_VMA_INTreg.BLIF UDS_000_INT_i.BLIF N_322_i.BLIF cpu_est_0_2__un0_n.BLIF \ + gnd_n_n.BLIF LDS_000_INT_i.BLIF N_312_i.BLIF cpu_est_0_1__un3_n.BLIF un1_amiga_bus_enable_low.BLIF N_131_i.BLIF N_139_0.BLIF cpu_est_0_1__un1_n.BLIF un6_as_030.BLIF \ + N_132_i.BLIF N_108_i.BLIF cpu_est_0_1__un0_n.BLIF un3_size.BLIF RW_000_i.BLIF N_258_i.BLIF vma_int_0_un3_n.BLIF un4_size.BLIF a_i_1__n.BLIF \ + N_257_i.BLIF vma_int_0_un1_n.BLIF un4_uds_000.BLIF clk_000_d_i_11__n.BLIF vma_int_0_un0_n.BLIF un4_lds_000.BLIF sm_amiga_i_6__n.BLIF N_245_i.BLIF ipl_030_0_0__un3_n.BLIF \ + un4_as_000.BLIF clk_000_d_i_1__n.BLIF nEXP_SPACE_c_i.BLIF ipl_030_0_0__un1_n.BLIF un10_ciin.BLIF AS_030_000_SYNC_i.BLIF un1_as_030_i.BLIF ipl_030_0_0__un0_n.BLIF un21_fpu_cs.BLIF \ + sm_amiga_i_0__n.BLIF pos_clk_un3_as_030_d0_0_n.BLIF ds_000_dma_0_un3_n.BLIF un22_berr.BLIF sm_amiga_i_3__n.BLIF N_107_0.BLIF ds_000_dma_0_un1_n.BLIF un6_ds_030.BLIF sm_amiga_i_i_7__n.BLIF \ + N_115_i.BLIF ds_000_dma_0_un0_n.BLIF cpu_est_3_.BLIF sm_amiga_i_5__n.BLIF N_63_0.BLIF as_000_dma_0_un3_n.BLIF cpu_est_0_.BLIF rst_dly_i_0__n.BLIF N_278_0.BLIF \ + as_000_dma_0_un1_n.BLIF cpu_est_1_.BLIF rst_dly_i_1__n.BLIF N_279_0.BLIF as_000_dma_0_un0_n.BLIF cpu_est_2_.BLIF N_364_i_0.BLIF N_260_i.BLIF a_decode_15__n.BLIF \ + inst_AS_000_INT.BLIF cpu_est_i_0__n.BLIF N_67_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF pos_clk_rw_000_int_5_0_n.BLIF a_decode_14__n.BLIF inst_AS_030_D0.BLIF AS_030_i.BLIF \ + un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_AS_030_000_SYNC.BLIF FPU_SENSE_i.BLIF un10_ciin_i.BLIF a_decode_13__n.BLIF inst_BGACK_030_INT_D.BLIF N_157_i.BLIF N_313_0.BLIF inst_AS_000_DMA.BLIF \ + a_decode_i_16__n.BLIF N_4_i.BLIF a_decode_12__n.BLIF inst_DS_000_DMA.BLIF a_decode_i_18__n.BLIF N_48_0.BLIF CYCLE_DMA_0_.BLIF a_decode_i_19__n.BLIF N_5_i.BLIF \ + a_decode_11__n.BLIF CYCLE_DMA_1_.BLIF N_113_i.BLIF N_47_0.BLIF SIZE_DMA_0_.BLIF N_114_i.BLIF N_7_i.BLIF a_decode_10__n.BLIF SIZE_DMA_1_.BLIF \ + AS_000_INT_i.BLIF N_46_0.BLIF inst_VPA_D.BLIF size_dma_i_1__n.BLIF N_18_i.BLIF a_decode_9__n.BLIF inst_UDS_000_INT.BLIF size_dma_i_0__n.BLIF N_41_0.BLIF \ + inst_LDS_000_INT.BLIF RESET_OUT_i.BLIF N_22_i.BLIF a_decode_8__n.BLIF inst_CLK_OUT_PRE_D.BLIF cpu_est_i_1__n.BLIF N_37_0.BLIF CLK_000_D_1_.BLIF cpu_est_i_2__n.BLIF \ + N_26_i.BLIF a_decode_7__n.BLIF CLK_000_D_10_.BLIF VPA_D_i.BLIF N_33_0.BLIF CLK_000_D_11_.BLIF DTACK_D0_i.BLIF BG_030_c_i.BLIF a_decode_6__n.BLIF \ + inst_DTACK_D0.BLIF cpu_est_i_3__n.BLIF pos_clk_un6_bg_030_i_n.BLIF inst_RESET_OUT.BLIF CLK_030_i.BLIF pos_clk_un9_bg_030_0_n.BLIF a_decode_5__n.BLIF CLK_000_D_0_.BLIF clk_000_d_i_0__n.BLIF \ + N_10_i.BLIF inst_CLK_OUT_PRE_50.BLIF clk_000_d_i_10__n.BLIF N_43_0.BLIF a_decode_4__n.BLIF IPL_D0_0_.BLIF AS_000_DMA_i.BLIF VPA_c_i.BLIF IPL_D0_1_.BLIF \ + AS_000_i.BLIF N_54_0.BLIF a_decode_3__n.BLIF IPL_D0_2_.BLIF CLK_030_H_i.BLIF un3_as_030_i.BLIF CLK_000_D_2_.BLIF cycle_dma_i_0__n.BLIF N_370_i.BLIF \ + a_decode_2__n.BLIF CLK_000_D_3_.BLIF AS_030_D0_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF CLK_000_D_4_.BLIF ahigh_i_30__n.BLIF N_283_i.BLIF CLK_000_D_5_.BLIF ahigh_i_31__n.BLIF \ + pos_clk_size_dma_6_0_0__n.BLIF CLK_000_D_6_.BLIF ahigh_i_28__n.BLIF N_345_i.BLIF CLK_000_D_7_.BLIF ahigh_i_29__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF CLK_000_D_8_.BLIF ahigh_i_26__n.BLIF \ + UDS_000_c_i.BLIF CLK_000_D_9_.BLIF ahigh_i_27__n.BLIF LDS_000_c_i.BLIF CLK_000_D_12_.BLIF ahigh_i_24__n.BLIF N_171_i.BLIF pos_clk_un6_bg_030_n.BLIF ahigh_i_25__n.BLIF \ + N_21_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_241_i.BLIF N_38_0.BLIF inst_DSACK1_INTreg.BLIF N_242_i.BLIF DTACK_c_i.BLIF pos_clk_ipl_n.BLIF N_243_i.BLIF \ + N_55_0.BLIF inst_DS_000_ENABLE.BLIF N_249_i.BLIF SM_AMIGA_6_.BLIF un6_ds_030_i.BLIF N_248_i.BLIF SM_AMIGA_0_.BLIF DS_000_DMA_i.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF \ + SM_AMIGA_4_.BLIF un4_as_000_i.BLIF N_250_i.BLIF inst_RW_000_INT.BLIF un6_as_030_i.BLIF N_251_i.BLIF inst_RW_000_DMA.BLIF un4_lds_000_i.BLIF cpu_est_2_0_1__n.BLIF \ + RST_DLY_0_.BLIF un4_uds_000_i.BLIF N_253_i.BLIF RST_DLY_1_.BLIF AS_030_c.BLIF N_369_i.BLIF RST_DLY_2_.BLIF cpu_est_2_0_2__n.BLIF inst_A0_DMA.BLIF \ + AS_000_c.BLIF N_254_i.BLIF inst_CLK_030_H.BLIF N_316_i.BLIF SM_AMIGA_1_.BLIF RW_000_c.BLIF N_256_i.BLIF SM_AMIGA_5_.BLIF N_255_i.BLIF \ + SM_AMIGA_3_.BLIF N_317_i.BLIF SM_AMIGA_2_.BLIF UDS_000_c.BLIF N_267_i.BLIF pos_clk_ds_000_dma_4_n.BLIF N_266_i.BLIF N_3.BLIF LDS_000_c.BLIF \ + N_57_0.BLIF N_8.BLIF N_151_0.BLIF size_c_0__n.BLIF N_321_i.BLIF N_158_i.BLIF size_c_1__n.BLIF VMA_INT_i.BLIF N_361_i.BLIF \ + ahigh_c_24__n.BLIF N_362_i.BLIF N_27.BLIF N_169_i.BLIF ahigh_c_25__n.BLIF N_186_0.BLIF N_195_0.BLIF ahigh_c_26__n.BLIF N_196_0.BLIF \ + ahigh_c_27__n.BLIF N_263_i.BLIF N_262_i.BLIF ahigh_c_28__n.BLIF N_323_0.BLIF N_101_i.BLIF ahigh_c_29__n.BLIF N_366_i.BLIF N_182_i.BLIF \ + ahigh_c_30__n.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_310_i.BLIF ahigh_c_31__n.BLIF N_359_i.BLIF N_144_0.BLIF CLK_OUT_PRE_D_i.BLIF N_142_0.BLIF N_311_i.BLIF \ + N_319_i.BLIF N_93_i.BLIF N_272_0.BLIF N_290_i.BLIF N_273_0.BLIF N_346_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_268_i.BLIF N_269_i.BLIF \ + SM_AMIGA_i_7_.BLIF sm_amiga_nss_0_3__n.BLIF N_341_i.BLIF N_238_i.BLIF N_239_i.BLIF sm_amiga_nss_0_2__n.BLIF N_263.BLIF N_235_i.BLIF G_116.BLIF \ + N_236_i.BLIF G_117.BLIF sm_amiga_nss_0_4__n.BLIF G_118.BLIF N_234_i.BLIF pos_clk_un23_bgack_030_int_i_0_n.BLIF sm_amiga_nss_0_5__n.BLIF N_272.BLIF N_231_i.BLIF \ + N_273.BLIF N_232_i.BLIF sm_amiga_nss_0_6__n.BLIF N_313.BLIF N_230_i.BLIF a_decode_c_16__n.BLIF sm_amiga_nss_0_7__n.BLIF N_226_i.BLIF N_108.BLIF \ + a_decode_c_17__n.BLIF N_331_i.BLIF N_319.BLIF N_142.BLIF a_decode_c_18__n.BLIF un1_as_000_i.BLIF N_144.BLIF N_27_i.BLIF N_322.BLIF \ + a_decode_c_19__n.BLIF N_30_0.BLIF N_169.BLIF ipl_c_i_0__n.BLIF N_195.BLIF a_decode_c_20__n.BLIF N_51_0.BLIF N_323.BLIF N_3_i.BLIF \ + N_209.BLIF a_decode_c_21__n.BLIF N_49_0.BLIF N_218.BLIF N_8_i.BLIF N_224.BLIF a_decode_c_22__n.BLIF N_45_0.BLIF N_226.BLIF \ + sm_amiga_nss_i_0_1_0__n.BLIF N_331.BLIF a_decode_c_23__n.BLIF sm_amiga_nss_i_0_2_0__n.BLIF N_229.BLIF sm_amiga_nss_i_0_3_0__n.BLIF N_230.BLIF a_c_0__n.BLIF sm_amiga_nss_i_0_4_0__n.BLIF \ + N_231.BLIF sm_amiga_nss_i_0_5_0__n.BLIF N_232.BLIF a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_233.BLIF un10_ciin_1.BLIF N_234.BLIF nEXP_SPACE_c.BLIF \ + un10_ciin_2.BLIF N_235.BLIF un10_ciin_3.BLIF N_236.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_238.BLIF un10_ciin_5.BLIF N_239.BLIF \ + BG_030_c.BLIF un10_ciin_6.BLIF N_240.BLIF un10_ciin_7.BLIF N_251.BLIF BG_000DFFreg.BLIF un10_ciin_8.BLIF N_262.BLIF un10_ciin_9.BLIF \ + N_341.BLIF un10_ciin_10.BLIF N_268.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_269.BLIF pos_clk_un23_bgack_030_int_i_0_0_1_n.BLIF N_282.BLIF CLK_030_c.BLIF \ + pos_clk_un23_bgack_030_int_i_0_0_2_n.BLIF N_346.BLIF N_60_i_1.BLIF N_290.BLIF N_60_i_2.BLIF N_310.BLIF N_248_1.BLIF N_311.BLIF CLK_OSZI_c.BLIF \ + N_248_2.BLIF N_355.BLIF N_249_1.BLIF N_356.BLIF N_249_2.BLIF N_359.BLIF CLK_OUT_INTreg.BLIF N_361_1.BLIF N_360.BLIF \ + N_361_2.BLIF N_365.BLIF N_157_1.BLIF N_366.BLIF FPU_SENSE_c.BLIF N_157_2.BLIF pos_clk_un23_bgack_030_int_i_0_o2_2_x2.BLIF N_157_3.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF \ + IPL_030DFF_0_reg.BLIF N_157_4.BLIF N_248.BLIF N_260_1.BLIF N_249.BLIF IPL_030DFF_1_reg.BLIF N_260_2.BLIF N_369.BLIF un21_fpu_cs_1.BLIF \ + N_196.BLIF IPL_030DFF_2_reg.BLIF un22_berr_1_0.BLIF N_186.BLIF N_275_i_1.BLIF N_361.BLIF ipl_c_0__n.BLIF N_275_i_2.BLIF N_362.BLIF \ + N_274_i_1.BLIF N_151.BLIF ipl_c_1__n.BLIF N_274_i_2.BLIF N_321.BLIF N_115_1.BLIF N_266.BLIF ipl_c_2__n.BLIF N_115_2.BLIF \ + N_267.BLIF N_332_1.BLIF N_255.BLIF N_246_1.BLIF N_256.BLIF DTACK_c.BLIF N_246_2.BLIF N_253.BLIF N_246_3.BLIF \ + N_254.BLIF N_246_4.BLIF cpu_est_2_2__n.BLIF N_332_4_1.BLIF cpu_est_2_1__n.BLIF VPA_c.BLIF N_332_4_2.BLIF N_250.BLIF N_273_0_1.BLIF \ + pos_clk_un9_clk_000_pe_n.BLIF N_276_i_1.BLIF N_364.BLIF RST_c.BLIF N_277_i_1.BLIF N_21.BLIF N_314_i_1.BLIF N_171.BLIF N_356_1.BLIF \ + pos_clk_size_dma_6_1__n.BLIF RW_c.BLIF N_282_1.BLIF N_345.BLIF N_251_1.BLIF pos_clk_size_dma_6_0__n.BLIF fc_c_0__n.BLIF pos_clk_un6_bg_030_1_n.BLIF N_283.BLIF \ + N_240_1.BLIF pos_clk_un6_bgack_000_n.BLIF fc_c_1__n.BLIF N_238_1.BLIF N_370.BLIF N_233_1.BLIF N_259.BLIF N_231_1.BLIF N_10.BLIF \ + AMIGA_BUS_DATA_DIR_c.BLIF N_224_1.BLIF pos_clk_un9_bg_030_n.BLIF N_218_1.BLIF N_4.BLIF pos_clk_ipl_1_n.BLIF N_114.BLIF rw_000_dma_0_un3_n.BLIF N_278.BLIF \ + rw_000_dma_0_un1_n.BLIF N_5.BLIF N_25_i.BLIF rw_000_dma_0_un0_n.BLIF N_113.BLIF N_34_0.BLIF lds_000_int_0_un3_n.BLIF N_279.BLIF N_24_i.BLIF \ + lds_000_int_0_un1_n.BLIF N_6.BLIF N_35_0.BLIF lds_000_int_0_un0_n.BLIF N_115.BLIF N_23_i.BLIF ipl_030_0_1__un3_n.BLIF N_63.BLIF N_36_0.BLIF \ + ipl_030_0_1__un1_n.BLIF N_7.BLIF N_19_i.BLIF ipl_030_0_1__un0_n.BLIF pos_clk_un3_as_030_d0_n.BLIF N_40_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF N_67.BLIF N_17_i.BLIF \ + amiga_bus_enable_dma_high_0_un1_n.BLIF N_18.BLIF N_42_0.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF pos_clk_rw_000_int_5_n.BLIF ipl_c_i_1__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF N_52_0.BLIF \ + amiga_bus_enable_dma_low_0_un1_n.BLIF N_22.BLIF ipl_c_i_2__n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF pos_clk_a0_dma_3_n.BLIF N_53_0.BLIF uds_000_int_0_un3_n.BLIF N_363.BLIF N_28_i.BLIF \ + uds_000_int_0_un1_n.BLIF N_26.BLIF N_31_0.BLIF uds_000_int_0_un0_n.BLIF N_157.BLIF N_29_i.BLIF ipl_030_0_2__un3_n.BLIF N_260.BLIF N_32_0.BLIF \ + ipl_030_0_2__un1_n.BLIF un22_berr_1.BLIF a_c_i_0__n.BLIF ipl_030_0_2__un0_n.BLIF N_219.BLIF size_c_i_1__n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_139.BLIF pos_clk_un10_sm_amiga_i_n.BLIF \ + un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_220.BLIF N_332_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_222.BLIF N_240_i.BLIF as_000_int_0_un3_n.BLIF N_223.BLIF N_315_0.BLIF \ + as_000_int_0_un1_n.BLIF N_368.BLIF N_281_0.BLIF as_000_int_0_un0_n.BLIF N_257.BLIF N_270_i.BLIF ds_000_enable_0_un3_n.BLIF N_258.BLIF N_282_i.BLIF \ + ds_000_enable_0_un1_n.BLIF N_312.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF ds_000_enable_0_un0_n.BLIF N_143.BLIF RW_c_i.BLIF as_030_000_sync_0_un3_n.BLIF N_332.BLIF N_140_0.BLIF \ + as_030_000_sync_0_un1_n.BLIF N_332_4.BLIF N_353_i.BLIF as_030_000_sync_0_un0_n.BLIF N_246.BLIF N_143_0.BLIF rw_000_int_0_un3_n.BLIF N_180.BLIF sm_amiga_i_1__n.BLIF \ + rw_000_int_0_un1_n.BLIF N_320.BLIF N_320_i.BLIF rw_000_int_0_un0_n.BLIF N_244.BLIF N_357_i.BLIF a0_dma_0_un3_n.BLIF N_334.BLIF N_356_i.BLIF \ + a0_dma_0_un1_n.BLIF N_335.BLIF N_156_0.BLIF a0_dma_0_un0_n.BLIF N_159.BLIF sm_amiga_i_4__n.BLIF bg_000_0_un3_n.BLIF N_156.BLIF N_159_i.BLIF \ + bg_000_0_un1_n.BLIF N_357.BLIF sm_amiga_i_2__n.BLIF bg_000_0_un0_n.BLIF N_353.BLIF N_180_i.BLIF size_dma_0_1__un3_n.BLIF N_140.BLIF N_334_i.BLIF \ + size_dma_0_1__un1_n.BLIF N_270.BLIF N_335_i.BLIF size_dma_0_1__un0_n.BLIF N_281.BLIF N_244_i.BLIF size_dma_0_0__un3_n.BLIF N_131.BLIF N_233_i.BLIF \ + size_dma_0_0__un1_n.BLIF N_132.BLIF N_355_i.BLIF size_dma_0_0__un0_n.BLIF N_29.BLIF N_229_i.BLIF bgack_030_int_0_un3_n.BLIF AS_030.PIN AS_000.PIN \ + RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN \ + AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ - IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ - CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D \ + IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ + CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D CLK_000_D_12_.C CYCLE_DMA_0_.D \ CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ - CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ - CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ - CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D \ - CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C \ - CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ - CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ - inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ - inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D \ - inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ - inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C G_136.X1 G_136.X2 G_135.X1 \ - G_135.X2 G_134.X1 G_134.X2 cpu_est_0_0_x2_0_x2_0_.X1 cpu_est_0_0_x2_0_x2_0_.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 pos_clk_CYCLE_DMA_5_0_i_x2.X1 pos_clk_CYCLE_DMA_5_0_i_x2.X2 pos_clk_un23_bgack_030_int_i_0_x2.X1 pos_clk_un23_bgack_030_int_i_0_x2.X2 \ - SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 pos_clk_un10_sm_amiga_i_n \ - cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 \ - cpu_est_2_0_2__n vma_int_0_un3_n N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 N_291_0 vma_int_0_un0_n N_192 AS_030_000_SYNC_i \ - cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 \ - N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size \ - N_258 N_176_i rw_000_int_0_un3_n un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 rw_000_int_0_un0_n \ - un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i \ - bgack_030_int_0_un0_n un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n \ - un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n N_275_i ds_000_enable_0_un0_n clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n \ - rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n cpu_est_i_2__n N_217_i un1_amiga_bus_enable_dma_high_0_m2_0__un1_n \ - nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n \ - VPA_D_i N_195_0 amiga_bus_enable_dma_high_0_un3_n sm_amiga_i_3__n N_190_0 amiga_bus_enable_dma_high_0_un1_n sm_amiga_i_0__n N_157_i amiga_bus_enable_dma_high_0_un0_n cpu_est_i_3__n N_154_i \ - size_dma_0_0__un3_n sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n RESET_OUT_i N_141_0 size_dma_0_0__un0_n BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n sm_amiga_i_2__n \ - N_216_i size_dma_0_1__un1_n sm_amiga_i_4__n N_337_i size_dma_0_1__un0_n clk_000_p_sync_i_10__n ds_000_dma_0_un3_n sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n \ - N_296_0 ds_000_dma_0_un0_n clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n sm_amiga_i_6__n N_284_i as_000_dma_0_un1_n RW_i N_285_i as_000_dma_0_un0_n \ - DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n LDS_000_INT_i N_280_i rw_000_dma_0_un1_n UDS_000_INT_i N_277_i rw_000_dma_0_un0_n AS_030_i N_257_0 \ - a0_dma_0_un3_n AS_000_INT_i N_235_i a0_dma_0_un1_n a_decode_i_19__n N_236_i a0_dma_0_un0_n a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n a_decode_i_16__n \ - N_231_i AS_000_i N_230_i a_decode_14__n FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_030_i N_37_0 \ - pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n clk_000_d_i_10__n N_334_i RW_000_i N_335_i a_decode_11__n a_i_1__n N_194_0 CLK_030_H_i \ - N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i clk_000_d_i_0__n N_346_i a_decode_9__n clk_000_d_i_1__n N_163_i AS_030_D0_i \ - N_345_i a_decode_8__n size_dma_i_0__n N_344_i size_dma_i_1__n N_153_0 a_decode_7__n ahigh_i_30__n pos_clk_un3_as_030_d0_i_n ahigh_i_31__n N_293_0 \ - a_decode_6__n ahigh_i_28__n N_233_i ahigh_i_29__n N_232_i a_decode_5__n ahigh_i_26__n N_290_0 ahigh_i_27__n VPA_c_i a_decode_4__n \ - ahigh_i_24__n N_54_0 ahigh_i_25__n N_5_i a_decode_3__n N_212_i N_47_0 N_213_i N_7_i a_decode_2__n N_214_i \ - N_46_0 N_18_i N_41_0 N_321_i N_10_i N_322_i N_43_0 un6_ds_030_i DTACK_c_i DS_000_DMA_i N_55_0 \ - un4_as_000_i pos_clk_un6_bgack_000_0_n un6_as_030_i N_137_i un4_lds_000_i N_184_0 un4_uds_000_i N_349_i AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i AS_030_c \ - N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i AS_000_c N_324_i RW_000_c N_199_0 N_197_0 N_196_0 pos_clk_a0_dma_3_n UDS_000_c \ - LDS_000_c_i UDS_000_c_i LDS_000_c N_181_i N_347_i size_c_0__n N_348_i N_178_i pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i \ - N_3 pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 N_341_i ahigh_c_26__n N_338_i \ - N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n \ - N_332_i ahigh_c_30__n N_331_i N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n N_328_i pos_clk_size_dma_6_0_0__n \ - N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i \ - N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n N_3_i N_49_0 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i \ - N_292 N_40_0 N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 \ - N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n N_194_0_1 N_157 N_237_i_1 \ - N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 \ - a_decode_c_22__n N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 a_c_0__n N_176_i_1 \ - N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 nEXP_SPACE_c un10_ciin_2 N_224 \ - un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 BG_030_c un10_ciin_6 N_236 un10_ciin_7 \ - N_277 un10_ciin_8 N_281 un10_ciin_9 N_282 un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 \ - N_318 CLK_030_c N_347_2 N_319 pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 \ - CLK_OSZI_c un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 N_366_3 N_328 N_366_4 N_329 \ - un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 N_142_i_2 N_336 N_339_1 N_338 \ - N_280_1 N_339 N_280_2 N_341 N_231_1 N_344 N_231_2 N_347 ipl_c_0__n N_230_1 N_348 \ - N_230_2 ipl_c_1__n N_230_3 N_226_1 ipl_c_2__n N_226_2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c \ - N_122_0_1 un22_berr_1 N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 \ - N_92_i_1 N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n N_10 \ - RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n \ - N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 N_18 \ - N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n \ - N_275 pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i \ - lds_000_int_0_un3_n N_146 N_38_0 lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n N_163 \ - N_4_i dsack1_int_0_un1_n N_22 N_48_0 dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n \ - N_235 ipl_c_i_1__n ipl_030_0_2__un0_n N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 \ - ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 \ - N_31_0 cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ - LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \ - AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE + RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ + CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ + inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ + inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ + inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ + inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ + inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C G_118.X1 G_118.X2 G_117.X1 G_117.X2 pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 pos_clk_un23_bgack_030_int_i_0_o2_2_x2.X1 pos_clk_un23_bgack_030_int_i_0_o2_2_x2.X2 G_116.X1 \ + G_116.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_28 N_246_i bgack_030_int_0_un1_n N_17 sm_amiga_nss_i_0_0__n bgack_030_int_0_un0_n N_19 dsack1_int_0_un3_n N_23 N_220_i \ + dsack1_int_0_un1_n N_24 N_219_i dsack1_int_0_un0_n N_25 N_218_i cpu_est_0_3__un3_n un1_amiga_bus_enable_low_i cpu_est_0_3__un1_n un21_fpu_cs_i N_224_i \ + cpu_est_0_3__un0_n BGACK_030_INT_i N_222_i cpu_est_0_2__un3_n vcc_n_n AMIGA_BUS_ENABLE_DMA_LOW_i N_223_i cpu_est_0_2__un1_n UDS_000_INT_i N_322_i cpu_est_0_2__un0_n \ + gnd_n_n LDS_000_INT_i N_312_i cpu_est_0_1__un3_n un1_amiga_bus_enable_low N_131_i N_139_0 cpu_est_0_1__un1_n un6_as_030 N_132_i N_108_i \ + cpu_est_0_1__un0_n un3_size RW_000_i N_258_i vma_int_0_un3_n un4_size a_i_1__n N_257_i vma_int_0_un1_n un4_uds_000 clk_000_d_i_11__n \ + vma_int_0_un0_n un4_lds_000 sm_amiga_i_6__n N_245_i ipl_030_0_0__un3_n un4_as_000 clk_000_d_i_1__n nEXP_SPACE_c_i ipl_030_0_0__un1_n un10_ciin AS_030_000_SYNC_i \ + un1_as_030_i ipl_030_0_0__un0_n un21_fpu_cs sm_amiga_i_0__n pos_clk_un3_as_030_d0_0_n ds_000_dma_0_un3_n un22_berr sm_amiga_i_3__n N_107_0 ds_000_dma_0_un1_n un6_ds_030 \ + sm_amiga_i_i_7__n N_115_i ds_000_dma_0_un0_n sm_amiga_i_5__n N_63_0 as_000_dma_0_un3_n rst_dly_i_0__n N_278_0 as_000_dma_0_un1_n rst_dly_i_1__n N_279_0 \ + as_000_dma_0_un0_n N_364_i_0 N_260_i a_decode_15__n cpu_est_i_0__n N_67_0 rst_dly_i_2__n pos_clk_rw_000_int_5_0_n a_decode_14__n AS_030_i un1_SM_AMIGA_0_sqmuxa_1_0 \ + FPU_SENSE_i un10_ciin_i a_decode_13__n N_157_i N_313_0 a_decode_i_16__n N_4_i a_decode_12__n a_decode_i_18__n N_48_0 a_decode_i_19__n \ + N_5_i a_decode_11__n N_113_i N_47_0 N_114_i N_7_i a_decode_10__n AS_000_INT_i N_46_0 size_dma_i_1__n N_18_i \ + a_decode_9__n size_dma_i_0__n N_41_0 RESET_OUT_i N_22_i a_decode_8__n cpu_est_i_1__n N_37_0 cpu_est_i_2__n N_26_i a_decode_7__n \ + VPA_D_i N_33_0 DTACK_D0_i BG_030_c_i a_decode_6__n cpu_est_i_3__n pos_clk_un6_bg_030_i_n CLK_030_i pos_clk_un9_bg_030_0_n a_decode_5__n clk_000_d_i_0__n \ + N_10_i clk_000_d_i_10__n N_43_0 a_decode_4__n AS_000_DMA_i VPA_c_i AS_000_i N_54_0 a_decode_3__n CLK_030_H_i un3_as_030_i \ + cycle_dma_i_0__n N_370_i a_decode_2__n AS_030_D0_i pos_clk_un6_bgack_000_0_n ahigh_i_30__n N_283_i ahigh_i_31__n pos_clk_size_dma_6_0_0__n ahigh_i_28__n N_345_i \ + ahigh_i_29__n pos_clk_size_dma_6_0_1__n ahigh_i_26__n UDS_000_c_i ahigh_i_27__n LDS_000_c_i ahigh_i_24__n N_171_i pos_clk_un6_bg_030_n ahigh_i_25__n N_21_i \ + N_241_i N_38_0 N_242_i DTACK_c_i pos_clk_ipl_n N_243_i N_55_0 N_249_i un6_ds_030_i N_248_i DS_000_DMA_i \ + pos_clk_un9_clk_000_pe_0_n un4_as_000_i N_250_i un6_as_030_i N_251_i un4_lds_000_i cpu_est_2_0_1__n un4_uds_000_i N_253_i AS_030_c N_369_i \ + cpu_est_2_0_2__n AS_000_c N_254_i N_316_i RW_000_c N_256_i N_255_i N_317_i UDS_000_c N_267_i pos_clk_ds_000_dma_4_n \ + N_266_i N_3 LDS_000_c N_57_0 N_8 N_151_0 size_c_0__n N_321_i N_158_i size_c_1__n VMA_INT_i \ + N_361_i ahigh_c_24__n N_362_i N_27 N_169_i ahigh_c_25__n N_186_0 N_195_0 ahigh_c_26__n N_196_0 ahigh_c_27__n \ + N_263_i N_262_i ahigh_c_28__n N_323_0 N_101_i ahigh_c_29__n N_366_i N_182_i ahigh_c_30__n pos_clk_un23_bgack_030_int_i_0_0_n N_310_i \ + ahigh_c_31__n N_359_i N_144_0 CLK_OUT_PRE_D_i N_142_0 N_311_i N_319_i N_93_i N_272_0 N_290_i N_273_0 \ + N_346_i pos_clk_ds_000_dma_4_0_n N_268_i N_269_i sm_amiga_nss_0_3__n N_341_i N_238_i N_239_i sm_amiga_nss_0_2__n N_263 N_235_i \ + N_236_i sm_amiga_nss_0_4__n N_234_i pos_clk_un23_bgack_030_int_i_0_n sm_amiga_nss_0_5__n N_272 N_231_i N_273 N_232_i sm_amiga_nss_0_6__n N_313 \ + N_230_i a_decode_c_16__n sm_amiga_nss_0_7__n N_226_i N_108 a_decode_c_17__n N_331_i N_319 N_142 a_decode_c_18__n un1_as_000_i \ + N_144 N_27_i N_322 a_decode_c_19__n N_30_0 N_169 ipl_c_i_0__n N_195 a_decode_c_20__n N_51_0 N_323 \ + N_3_i N_209 a_decode_c_21__n N_49_0 N_218 N_8_i N_224 a_decode_c_22__n N_45_0 N_226 sm_amiga_nss_i_0_1_0__n \ + N_331 a_decode_c_23__n sm_amiga_nss_i_0_2_0__n N_229 sm_amiga_nss_i_0_3_0__n N_230 a_c_0__n sm_amiga_nss_i_0_4_0__n N_231 sm_amiga_nss_i_0_5_0__n N_232 \ + a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_233 un10_ciin_1 N_234 nEXP_SPACE_c un10_ciin_2 N_235 un10_ciin_3 N_236 BERR_c \ + un10_ciin_4 N_238 un10_ciin_5 N_239 BG_030_c un10_ciin_6 N_240 un10_ciin_7 N_251 un10_ciin_8 N_262 \ + un10_ciin_9 N_341 un10_ciin_10 N_268 BGACK_000_c un10_ciin_11 N_269 pos_clk_un23_bgack_030_int_i_0_0_1_n N_282 CLK_030_c pos_clk_un23_bgack_030_int_i_0_0_2_n \ + N_346 N_60_i_1 N_290 N_60_i_2 N_310 N_248_1 N_311 CLK_OSZI_c N_248_2 N_355 N_249_1 \ + N_356 N_249_2 N_359 N_361_1 N_360 N_361_2 N_365 N_157_1 N_366 FPU_SENSE_c N_157_2 \ + N_157_3 N_157_4 N_248 N_260_1 N_249 N_260_2 N_369 un21_fpu_cs_1 N_196 un22_berr_1_0 N_186 \ + N_275_i_1 N_361 ipl_c_0__n N_275_i_2 N_362 N_274_i_1 N_151 ipl_c_1__n N_274_i_2 N_321 N_115_1 \ + N_266 ipl_c_2__n N_115_2 N_267 N_332_1 N_255 N_246_1 N_256 DTACK_c N_246_2 N_253 \ + N_246_3 N_254 N_246_4 cpu_est_2_2__n N_332_4_1 cpu_est_2_1__n VPA_c N_332_4_2 N_250 N_273_0_1 pos_clk_un9_clk_000_pe_n \ + N_276_i_1 N_364 RST_c N_277_i_1 N_21 N_314_i_1 N_171 N_356_1 pos_clk_size_dma_6_1__n RW_c N_282_1 \ + N_345 N_251_1 pos_clk_size_dma_6_0__n fc_c_0__n pos_clk_un6_bg_030_1_n N_283 N_240_1 pos_clk_un6_bgack_000_n fc_c_1__n N_238_1 N_370 \ + N_233_1 N_259 N_231_1 N_10 AMIGA_BUS_DATA_DIR_c N_224_1 pos_clk_un9_bg_030_n N_218_1 N_4 pos_clk_ipl_1_n N_114 \ + rw_000_dma_0_un3_n N_278 rw_000_dma_0_un1_n N_5 N_25_i rw_000_dma_0_un0_n N_113 N_34_0 lds_000_int_0_un3_n N_279 N_24_i \ + lds_000_int_0_un1_n N_6 N_35_0 lds_000_int_0_un0_n N_115 N_23_i ipl_030_0_1__un3_n N_63 N_36_0 ipl_030_0_1__un1_n N_7 \ + N_19_i ipl_030_0_1__un0_n pos_clk_un3_as_030_d0_n N_40_0 amiga_bus_enable_dma_high_0_un3_n N_67 N_17_i amiga_bus_enable_dma_high_0_un1_n N_18 N_42_0 amiga_bus_enable_dma_high_0_un0_n \ + pos_clk_rw_000_int_5_n ipl_c_i_1__n amiga_bus_enable_dma_low_0_un3_n un1_SM_AMIGA_0_sqmuxa_1 N_52_0 amiga_bus_enable_dma_low_0_un1_n N_22 ipl_c_i_2__n amiga_bus_enable_dma_low_0_un0_n pos_clk_a0_dma_3_n N_53_0 \ + uds_000_int_0_un3_n N_363 N_28_i uds_000_int_0_un1_n N_26 N_31_0 uds_000_int_0_un0_n N_157 N_29_i ipl_030_0_2__un3_n N_260 \ + N_32_0 ipl_030_0_2__un1_n un22_berr_1 a_c_i_0__n ipl_030_0_2__un0_n N_219 size_c_i_1__n un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_139 pos_clk_un10_sm_amiga_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n \ + N_220 N_332_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_222 N_240_i as_000_int_0_un3_n N_223 N_315_0 as_000_int_0_un1_n N_368 N_281_0 \ + as_000_int_0_un0_n N_257 N_270_i ds_000_enable_0_un3_n N_258 N_282_i ds_000_enable_0_un1_n N_312 AMIGA_BUS_DATA_DIR_c_0 ds_000_enable_0_un0_n N_143 \ + RW_c_i as_030_000_sync_0_un3_n N_332 N_140_0 as_030_000_sync_0_un1_n N_332_4 N_353_i as_030_000_sync_0_un0_n N_246 N_143_0 rw_000_int_0_un3_n \ + N_180 sm_amiga_i_1__n rw_000_int_0_un1_n N_320 N_320_i rw_000_int_0_un0_n N_244 N_357_i a0_dma_0_un3_n N_334 N_356_i \ + a0_dma_0_un1_n N_335 N_156_0 a0_dma_0_un0_n N_159 sm_amiga_i_4__n bg_000_0_un3_n N_156 N_159_i bg_000_0_un1_n N_357 \ + sm_amiga_i_2__n bg_000_0_un0_n N_353 N_180_i size_dma_0_1__un3_n N_140 N_334_i size_dma_0_1__un1_n N_270 N_335_i size_dma_0_1__un0_n \ + N_281 N_244_i size_dma_0_0__un3_n N_131 N_233_i size_dma_0_0__un1_n N_132 N_355_i size_dma_0_0__un0_n N_29 N_229_i \ + bgack_030_int_0_un3_n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ + AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE \ + RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE .names un6_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c @@ -267,13 +255,13 @@ 1 1 .names SIZE_0_.PIN size_c_0__n 1 1 -.names N_200_i.BLIF SIZE_0_.OE +.names un1_as_030_i.BLIF SIZE_0_.OE 1 1 .names un3_size.BLIF SIZE_1_ 1 1 .names SIZE_1_.PIN size_c_1__n 1 1 -.names N_200_i.BLIF SIZE_1_.OE +.names un1_as_030_i.BLIF SIZE_1_.OE 1 1 .names gnd_n_n.BLIF AHIGH_24_ 1 1 @@ -339,7 +327,7 @@ 1 1 .names RW.PIN RW_c 1 1 -.names N_318.BLIF RW.OE +.names N_93_i.BLIF RW.OE 1 1 .names un6_ds_030_i.BLIF DS_030 1 1 @@ -355,1604 +343,1484 @@ 1 1 .names un10_ciin.BLIF CIIN 1 1 -.names N_296.BLIF CIIN.OE +.names N_313.BLIF CIIN.OE 1 1 -.names N_338_i.BLIF N_339_i.BLIF N_239_i_1 +.names N_157_4.BLIF N_157_3.BLIF N_157 11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 -1- 1 --1 1 -.names CLK_000_D_5_.BLIF CLK_000_D_6_.D -1 1 -.names N_239_i_1.BLIF RST_c.BLIF RST_DLY_0_.D -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +.names N_272.BLIF as_000_dma_0_un3_n 0 1 -.names N_25_i.BLIF RST_c.BLIF N_34_0 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names CLK_000_D_6_.BLIF CLK_000_D_7_.D -1 1 -.names N_336_i.BLIF sm_amiga_i_5__n.BLIF N_122_0_1 +.names pos_clk_un23_bgack_030_int_i_0_n.BLIF N_272.BLIF as_000_dma_0_un1_n 11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names N_24_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C -1 1 -.names CLK_000_D_7_.BLIF CLK_000_D_8_.D -1 1 -.names N_122_0_1.BLIF SM_AMIGA_i_7_.BLIF N_122_0 -11 1 -.names CLK_000_N_SYNC_12_.BLIF clk_000_n_sync_i_12__n -0 1 -.names N_20_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names CLK_000_D_8_.BLIF CLK_000_D_9_.D -1 1 -.names N_211_i.BLIF N_332_i.BLIF N_132_i_1 -11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_19_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names CLK_000_D_9_.BLIF CLK_000_D_10_.D -1 1 -.names N_132_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_2__n.BLIF N_219 -11 1 -.names N_8_i.BLIF RST_c.BLIF N_45_0 -11 1 -.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D -1 1 -.names N_331_i.BLIF RW_000_i.BLIF N_120_0_1 -11 1 -.names N_141.BLIF N_166_i.BLIF N_217 -11 1 -.names N_3_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C -1 1 -.names N_366_4.BLIF N_366_3.BLIF N_366 -11 1 -.names N_294.BLIF size_dma_0_0__un3_n -0 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_163_i.BLIF un1_SM_AMIGA_5_i_1 -11 1 -.names pos_clk_size_dma_6_0__n.BLIF N_294.BLIF size_dma_0_0__un1_n -11 1 -.names N_346_i.BLIF sm_amiga_i_0__n.BLIF un1_SM_AMIGA_5_i_2 -11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 .names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n 0 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C -1 1 -.names N_163.BLIF N_334_i.BLIF N_142_i_1 -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names N_294.BLIF size_dma_0_1__un3_n -0 1 -.names N_335_i.BLIF RST_c.BLIF N_142_i_2 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_294.BLIF size_dma_0_1__un1_n -11 1 -.names N_142_i_1.BLIF N_142_i_2.BLIF SM_AMIGA_6_.D -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 -1- 1 --1 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names CLK_000_c.BLIF CLK_000_D_0_.D -1 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_0__n.BLIF N_339_1 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names N_339_1.BLIF RST_c.BLIF N_339 -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_280_1 -11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low -11 1 -.names RST_c.BLIF SM_AMIGA_3_.BLIF N_280_2 -11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 -1- 1 --1 1 -.names un4_uds_000.BLIF un4_uds_000_i -0 1 -.names N_280_1.BLIF N_280_2.BLIF N_280 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names un4_lds_000.BLIF un4_lds_000_i -0 1 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -.names CLK_000_N_SYNC_12_.BLIF N_357.BLIF N_231_1 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names un6_as_030.BLIF un6_as_030_i -0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_231_2 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -.names N_231_1.BLIF N_231_2.BLIF N_231 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 -1- 1 --1 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names N_157_i.BLIF VMA_INT_i.BLIF N_347_1 -11 1 -.names N_291.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n -11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_347_2 -11 1 -.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_120.BLIF ds_000_dma_0_un3_n -0 1 -.names N_347_1.BLIF N_347_2.BLIF N_347 -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names pos_clk_ds_000_dma_4_n.BLIF N_120.BLIF ds_000_dma_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_1_n -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names pos_clk_un23_bgack_030_int_i_0_x2.BLIF N_341_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_2_n -11 1 -.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n -11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n -11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_298.BLIF as_000_dma_0_un3_n -0 1 -.names FPU_SENSE_i.BLIF N_366.BLIF un21_fpu_cs_1 -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names pos_clk_un23_bgack_030_int_i_1_n.BLIF N_298.BLIF as_000_dma_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_3_.C -1 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 -.names N_29_i.BLIF RST_c.BLIF N_32_0 -11 1 .names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 -.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names N_28_i.BLIF RST_c.BLIF N_31_0 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 1- 1 -1 1 -.names un22_berr_1_0.BLIF N_366.BLIF un22_berr -11 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_366_1 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_295.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_4_.C -1 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_366_2 -11 1 -.names N_157.BLIF N_315_i.BLIF N_291_0 -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_366_3 -11 1 -.names N_254_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n -11 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_366_1.BLIF N_366_2.BLIF N_366_4 -11 1 -.names N_275_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_258_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n -0 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_0_.BLIF N_146_0_1 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_5_.C -1 1 -.names N_146_0_1.BLIF nEXP_SPACE_c.BLIF N_146_0 -11 1 -.names N_164_i.BLIF cpu_est_i_2__n.BLIF N_357 -11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n -11 1 -.names BERR_c.BLIF BERR_i -0 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n -11 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_343 -11 1 -.names vcc_n_n -1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 -11 1 -.names N_141.BLIF RST_DLY_0_.BLIF N_338 -11 1 -.names gnd_n_n -.names CLK_OSZI_c.BLIF CLK_000_D_6_.C -1 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 -11 1 -.names N_164_i.BLIF cpu_est_2_.BLIF N_315 -11 1 -.names A_DECODE_15_.BLIF a_decode_15__n -1 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 -11 1 -.names N_164.BLIF cpu_est_2_.BLIF N_254 -11 1 -.names A_DECODE_14_.BLIF a_decode_14__n -1 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 -11 1 -.names N_192.BLIF N_343.BLIF N_223 -11 1 -.names A_DECODE_13_.BLIF a_decode_13__n -1 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 -11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names A_DECODE_12_.BLIF a_decode_12__n -1 1 -.names CLK_OSZI_c.BLIF CLK_000_D_7_.C -1 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_1__n.BLIF N_221 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_8_i.BLIF RST_c.BLIF N_45_0 11 1 -.names A_DECODE_11_.BLIF a_decode_11__n -1 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names N_149_i.BLIF N_340.BLIF N_220 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +1- 1 +-1 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 11 1 -.names A_DECODE_10_.BLIF a_decode_10__n -1 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_200_i -11 1 -.names A_DECODE_9_.BLIF a_decode_9__n -1 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 -11 1 -.names A_DECODE_8_.BLIF a_decode_8__n -1 1 -.names CLK_OSZI_c.BLIF CLK_000_D_8_.C -1 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names A_DECODE_7_.BLIF a_decode_7__n -1 1 -.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names A_DECODE_6_.BLIF a_decode_6__n -1 1 -.names N_215_i.BLIF N_217_i.BLIF N_237_i_1 -11 1 .names SM_AMIGA_0_.BLIF sm_amiga_i_0__n 0 1 -.names A_DECODE_5_.BLIF a_decode_5__n -1 1 -.names N_219_i.BLIF RST_c.BLIF N_237_i_2 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 11 1 -.names inst_VPA_D.BLIF VPA_D_i +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names A_DECODE_4_.BLIF a_decode_4__n -1 1 -.names CLK_OSZI_c.BLIF CLK_000_D_9_.C -1 1 -.names N_237_i_1.BLIF N_237_i_2.BLIF RST_DLY_2_.D +.names N_27_i.BLIF RST_c.BLIF N_30_0 11 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_192_0 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 -.names A_DECODE_3_.BLIF a_decode_3__n -1 1 -.names N_220_i.BLIF RST_c.BLIF N_238_i_1 -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_186_0 -11 1 -.names A_DECODE_2_.BLIF a_decode_2__n -1 1 -.names N_221_i.BLIF N_222_i.BLIF N_238_i_2 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_172_i -11 1 -.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_149_i.BLIF RST_DLY_2_.BLIF N_166_i -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_10_.C -1 1 -.names N_185_i.BLIF N_223_i.BLIF N_144_i_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n 0 1 -.names N_224_i.BLIF N_225_i.BLIF N_144_i_2 +.names vcc_n_n +1 +.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names N_144_i_1.BLIF N_144_i_2.BLIF N_144_i_3 +.names gnd_n_n +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_164_i +.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n 11 1 -.names CLK_000_D_10_.BLIF CLK_000_D_11_.D +.names A_DECODE_15_.BLIF a_decode_15__n 1 1 -.names N_144_i_3.BLIF N_226_i.BLIF SM_AMIGA_i_7_.D -11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_227_i.BLIF N_228_i.BLIF N_136_i_1 -11 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_149_i -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_11_.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 1 -.names N_343_i.BLIF RST_c.BLIF N_136_i_2 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_1_n 11 1 -.names N_277_i.BLIF N_280_i.BLIF N_257_0 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n 11 1 -.names N_136_i_1.BLIF N_136_i_2.BLIF SM_AMIGA_3_.D -11 1 -.names N_284_i.BLIF N_285_i.BLIF N_292_0 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_176_i_1 -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names CLK_000_D_11_.BLIF CLK_000_D_12_.D +.names A_DECODE_14_.BLIF a_decode_14__n 1 1 -.names N_176_i_1.BLIF sm_amiga_i_2__n.BLIF N_176_i +.names pos_clk_un23_bgack_030_int_i_0_o2_2_x2.BLIF N_311_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_2_n 11 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_209 +1- 1 +-1 1 +.names A_DECODE_13_.BLIF a_decode_13__n +1 1 +.names pos_clk_un23_bgack_030_int_i_0_0_1_n.BLIF pos_clk_un23_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_0_0_n 11 1 -.names N_282.BLIF N_282_i +.names N_159_i.BLIF sm_amiga_i_2__n.BLIF N_180_i +11 1 +.names A_DECODE_12_.BLIF a_decode_12__n +1 1 +.names AS_000_i.BLIF N_101_i.BLIF N_60_i_1 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_159_i +11 1 +.names A_DECODE_11_.BLIF a_decode_11__n +1 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +.names N_262_i.BLIF N_263_i.BLIF N_60_i_2 +11 1 +.names N_356_i.BLIF N_357_i.BLIF N_156_0 +11 1 +.names A_DECODE_10_.BLIF a_decode_10__n +1 1 +.names N_51_0.BLIF IPL_D0_0_.D 0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_296_0 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_320_i 11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_12_.C +.names A_DECODE_9_.BLIF a_decode_9__n 1 1 .names N_3.BLIF N_3_i 0 1 -.names N_337_i.BLIF RST_c.BLIF inst_RESET_OUT.D +.names N_159.BLIF N_353_i.BLIF N_143_0 11 1 +.names A_DECODE_8_.BLIF a_decode_8__n +1 1 .names N_49_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_166.BLIF RST_c.BLIF N_216_i -11 1 -.names N_8.BLIF N_8_i -0 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_45_0.BLIF inst_AS_000_DMA.D -0 1 -.names N_200_i.BLIF inst_RESET_OUT.BLIF un3_as_030_i -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C -1 1 -.names N_19.BLIF N_19_i -0 1 -.names N_340_i.BLIF RST_c.BLIF N_141_0 -11 1 -.names N_40_0.BLIF inst_RW_000_DMA.D -0 1 -.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_154_i -11 1 -.names N_20.BLIF N_20_i -0 1 -.names N_154_i.BLIF cpu_est_i_0__n.BLIF N_157_i -11 1 -.names N_39_0.BLIF inst_A0_DMA.D -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C -1 1 -.names N_24.BLIF N_24_i -0 1 -.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_1_.BLIF N_190_0 -11 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names CLK_000_N_SYNC_12_.BLIF N_166_i.BLIF N_195_0 -11 1 -.names N_25.BLIF N_25_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C -1 1 -.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_194_0_1 -11 1 -.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_194_0_1.BLIF nEXP_SPACE_c.BLIF N_194_0 -11 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_211 -1- 1 --1 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_328.BLIF N_328_i -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C -1 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names N_325.BLIF N_325_i -0 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names N_327.BLIF N_327_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n -0 1 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -.names N_320.BLIF N_320_i -0 1 -.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n -11 1 -.names N_298_0.BLIF N_298 -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names N_295_0.BLIF N_295 -0 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names N_294_0.BLIF N_294 -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_235 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names N_319.BLIF N_319_i -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names un1_amiga_bus_enable_dma_high_0_0__n.BLIF un1_amiga_bus_enable_dma_high_0__n -0 1 -.names clk_000_n_sync_i_12__n.BLIF sm_amiga_i_4__n.BLIF N_282 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -.names N_206.BLIF N_206_i -0 1 -.names N_154_i.BLIF cpu_est_i_1__n.BLIF N_284 -11 1 -.names N_283.BLIF N_283_i -0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_318 -11 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -.names N_281.BLIF N_281_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names pos_clk_un23_bgack_030_int_i_1_0_n.BLIF pos_clk_un23_bgack_030_int_i_1_n -0 1 -.names N_190.BLIF sm_amiga_i_2__n.BLIF N_332 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names N_195.BLIF RESET_OUT_i.BLIF N_337 -11 1 -.names N_148_0.BLIF N_148 -0 1 -.names CLK_000_N_SYNC_12_.BLIF N_166.BLIF N_340 -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -.names N_341.BLIF N_341_i -0 1 -.names N_230_i.BLIF N_231_i.BLIF pos_clk_un4_clk_000_pe_0_n -11 1 -.names N_338.BLIF N_338_i -0 1 -.names N_235_i.BLIF N_236_i.BLIF cpu_est_2_0_1__n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names N_339.BLIF N_339_i -0 1 -.names N_146.BLIF sm_amiga_i_6__n.BLIF N_334 -11 1 -.names N_336.BLIF N_336_i -0 1 -.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF N_336 -11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names N_122_0.BLIF N_122 -0 1 -.names CLK_000_D_11_.BLIF clk_000_d_i_11__n -0 1 -.names N_211.BLIF N_211_i -0 1 -.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_345 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_332.BLIF N_332_i -0 1 -.names clk_000_p_sync_i_10__n.BLIF SM_AMIGA_4_.BLIF N_346 -11 1 -.names N_331.BLIF N_331_i -0 1 -.names N_232_i.BLIF N_233_i.BLIF N_290_0 -11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names N_120_0.BLIF N_120 -0 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_293_0 -11 1 -.names N_330.BLIF N_330_i -0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n -0 1 -.names N_344_i.BLIF N_345_i.BLIF N_153_0 -11 1 -.names N_329.BLIF N_329_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names N_349.BLIF N_349_i -0 1 -.names sm_amiga_i_6__n.BLIF SM_AMIGA_i_7_.BLIF N_163_i -11 1 -.names N_187_0.BLIF N_187 -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names N_203_i.BLIF N_203 -0 1 -.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_5_.BLIF N_191_0 -11 1 -.names N_324.BLIF N_324_i -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -.names N_199_0.BLIF N_199 -0 1 -.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n -11 1 -.names N_197_0.BLIF N_197 -0 1 -.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names N_196_0.BLIF N_196 -0 1 -.names sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF N_206 -1- 1 --1 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names CLK_000_P_SYNC_10_.BLIF clk_000_p_sync_i_10__n -0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i -0 1 -.names N_181_i.BLIF N_181 -0 1 -.names N_122.BLIF rw_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names N_347.BLIF N_347_i -0 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_122.BLIF rw_000_int_0_un1_n -11 1 -.names N_348.BLIF N_348_i -0 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names N_178_i.BLIF N_178 -0 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names N_18_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names N_7_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names N_54_0.BLIF inst_VPA_D.D -0 1 -.names N_5_i.BLIF RST_c.BLIF N_47_0 -11 1 -.names N_5.BLIF N_5_i -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_54_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -.names N_47_0.BLIF inst_AS_000_INT.D -0 1 -.names RW_c.BLIF RW_i -0 1 -.names N_7.BLIF N_7_i -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names N_46_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_194.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_232 -11 1 -.names N_18.BLIF N_18_i -0 1 -.names N_366.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_233 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names N_41_0.BLIF inst_RW_000_INT.D -0 1 -.names N_153.BLIF SM_AMIGA_1_.BLIF N_275 -11 1 -.names N_10.BLIF N_10_i -0 1 -.names N_191.BLIF sm_amiga_i_6__n.BLIF N_283 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_43_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF DS_000_ENABLE_1_sqmuxa_1 -11 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 .names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +.names A_DECODE_7_.BLIF a_decode_7__n 1 1 -.names N_55_0.BLIF inst_DTACK_D0.D -0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names CLK_000_P_SYNC_10_.BLIF CYCLE_DMA_0_.BLIF N_208 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 -.names N_137_i.BLIF N_137 +.names N_8.BLIF N_8_i 0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +.names RW_c_i.BLIF SM_AMIGA_6_.BLIF N_140_0 11 1 -.names N_184_0.BLIF N_184 -0 1 -.names N_10_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +.names A_DECODE_6_.BLIF a_decode_6__n 1 1 -.names N_334.BLIF N_334_i +.names N_45_0.BLIF inst_AS_000_DMA.D 0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_335.BLIF N_335_i -0 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +.names N_270_i.BLIF N_282_i.BLIF AMIGA_BUS_DATA_DIR_c_0 11 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +.names A_DECODE_5_.BLIF a_decode_5__n 1 1 -.names N_194_0.BLIF N_194 -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +.names N_334_i.BLIF N_335_i.BLIF sm_amiga_nss_i_0_1_0__n 11 1 -.names N_191_0.BLIF N_191 -0 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_281_0 +11 1 +.names A_DECODE_4_.BLIF a_decode_4__n 1 1 -.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 +.names N_233_i.BLIF N_244_i.BLIF sm_amiga_nss_i_0_2_0__n +11 1 +.names N_240_i.BLIF N_332_i.BLIF N_315_0 +11 1 +.names A_DECODE_3_.BLIF a_decode_3__n +1 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names N_246_i.BLIF N_229_i.BLIF sm_amiga_nss_i_0_3_0__n +11 1 +.names CLK_000_D_11_.BLIF clk_000_d_i_11__n +0 1 +.names A_DECODE_2_.BLIF a_decode_2__n +1 1 +.names sm_amiga_nss_i_0_1_0__n.BLIF sm_amiga_nss_i_0_2_0__n.BLIF sm_amiga_nss_i_0_4_0__n +11 1 +.names N_364.BLIF N_364_i_0 +0 1 +.names sm_amiga_nss_i_0_3_0__n.BLIF N_355_i.BLIF sm_amiga_nss_i_0_5_0__n +11 1 +.names N_108_i.BLIF N_364_i_0.BLIF N_312 +11 1 +.names sm_amiga_nss_i_0_4_0__n.BLIF sm_amiga_nss_i_0_5_0__n.BLIF sm_amiga_nss_i_0_0__n +11 1 +.names N_108_i.BLIF RST_c.BLIF N_360 +11 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +11 1 +.names N_322_i.BLIF RST_DLY_2_.BLIF N_364 +11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n +11 1 +.names N_108.BLIF RST_c.BLIF N_368 +11 1 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 +11 1 +.names N_364_i_0.BLIF RST_c.BLIF N_245_i +11 1 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 +11 1 +.names N_257_i.BLIF N_258_i.BLIF cpu_est_0_.D +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names N_235.BLIF N_235_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_108_i +11 1 +.names N_236.BLIF N_236_i +0 1 +.names N_312_i.BLIF RST_c.BLIF N_139_0 +11 1 +.names sm_amiga_nss_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names N_234.BLIF N_234_i +0 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names sm_amiga_nss_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_322_i +11 1 +.names N_231.BLIF N_231_i +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_232.BLIF N_232_i +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names sm_amiga_nss_0_6__n.BLIF SM_AMIGA_1_.D +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_230.BLIF N_230_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_c_i.BLIF un1_as_030_i +11 1 +.names sm_amiga_nss_0_7__n.BLIF SM_AMIGA_0_.D +0 1 +.names N_157.BLIF N_157_i +0 1 +.names N_226.BLIF N_226_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_331.BLIF N_331_i 0 1 .names AS_030_c.BLIF AS_030_i 0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names N_27.BLIF N_27_i +0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names N_30_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_139.BLIF N_364.BLIF N_219 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_142_0.BLIF N_142 +0 1 +.names N_108.BLIF rst_dly_i_2__n.BLIF N_220 +11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names N_311.BLIF N_311_i +0 1 +.names N_139.BLIF N_322_i.BLIF N_222 +11 1 +.names N_319_i.BLIF N_319 +0 1 +.names N_368.BLIF rst_dly_i_1__n.BLIF N_223 +11 1 +.names N_272_0.BLIF N_272 +0 1 +.names N_139.BLIF RST_DLY_0_.BLIF N_226 +11 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names N_290.BLIF N_290_i +0 1 +.names N_368.BLIF rst_dly_i_0__n.BLIF N_331 +11 1 +.names N_273_0.BLIF N_273 +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 .names N_346.BLIF N_346_i 0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names N_163_i.BLIF N_163 -0 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +.names N_108.BLIF cpu_est_i_0__n.BLIF N_257 11 1 -.names N_345.BLIF N_345_i +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n 0 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C -1 1 -.names N_344.BLIF N_344_i -0 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 +.names N_108_i.BLIF cpu_est_0_.BLIF N_258 11 1 -.names N_153_0.BLIF N_153 +.names N_268.BLIF N_268_i 0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i +.names a_decode_c_19__n.BLIF a_decode_i_19__n 0 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +.names N_269.BLIF N_269_i 0 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names sm_amiga_nss_0_3__n.BLIF SM_AMIGA_4_.D +0 1 +.names N_319_i.BLIF SM_AMIGA_6_.BLIF N_113 11 1 -.names N_293_0.BLIF N_293 -0 1 -.names N_293.BLIF as_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 -.names N_233.BLIF N_233_i +.names N_341.BLIF N_341_i 0 1 -.names sm_amiga_i_5__n.BLIF N_293.BLIF as_000_int_0_un1_n +.names N_363.BLIF RST_c.BLIF N_259 11 1 -.names N_232.BLIF N_232_i +.names N_238.BLIF N_238_i +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names N_239.BLIF N_239_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_363 +11 1 +.names sm_amiga_nss_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names nEXP_SPACE_c_i.BLIF un10_ciin_i.BLIF N_313_0 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names N_362.BLIF N_362_i +0 1 +.names N_113_i.BLIF N_182_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +.names N_169_i.BLIF N_169 +0 1 +.names N_182_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names N_186_0.BLIF N_186 +0 1 +.names N_260_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_67_0 +11 1 +.names IPL_D0_2_.BLIF G_118.X1 +1 1 +.names N_195_0.BLIF N_195 +0 1 +.names N_113_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_279_0 +11 1 +.names N_196_0.BLIF N_196 +0 1 +.names N_114_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_278_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names ipl_c_2__n.BLIF G_118.X2 +1 1 +.names N_263.BLIF N_263_i +0 1 +.names N_115_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_63_0 +11 1 +.names N_262.BLIF N_262_i +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_107_0 +11 1 +.names N_323_0.BLIF N_323 +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_0_n +11 1 +.names IPL_D0_1_.BLIF G_117.X1 +1 1 +.names N_101_i.BLIF inst_BGACK_030_INT_D.D +0 1 +.names N_113.BLIF N_113_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_366.BLIF N_366_i +0 1 +.names N_279.BLIF as_000_int_0_un3_n +0 1 +.names ipl_c_1__n.BLIF G_117.X2 +1 1 +.names pos_clk_un23_bgack_030_int_i_0_0_n.BLIF pos_clk_un23_bgack_030_int_i_0_n +0 1 +.names N_113_i.BLIF N_279.BLIF as_000_int_0_un1_n +11 1 +.names N_310.BLIF N_310_i 0 1 .names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names N_290_0.BLIF N_290 +.names N_359.BLIF N_359_i 0 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 1- 1 -1 1 -.names N_296_0.BLIF N_296 -0 1 -.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 -.names N_284.BLIF N_284_i -0 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un1_n -11 1 -.names N_285.BLIF N_285_i -0 1 -.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 1 1 -.names N_292_0.BLIF N_292 +.names N_144_0.BLIF N_144 +0 1 +.names N_63.BLIF ds_000_enable_0_un3_n +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names N_115.BLIF N_63.BLIF ds_000_enable_0_un1_n +11 1 +.names N_263.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 +1 1 +.names N_251.BLIF N_251_i +0 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_280.BLIF N_280_i -0 1 -.names N_290.BLIF as_030_000_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 -.names N_277.BLIF N_277_i +.names N_253.BLIF N_253_i 0 1 -.names inst_AS_030_000_SYNC.BLIF N_290.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_257_0.BLIF SM_AMIGA_2_.D +.names N_67.BLIF as_030_000_sync_0_un3_n 0 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C +.names CYCLE_DMA_0_.BLIF pos_clk_un23_bgack_030_int_i_0_o2_2_x2.X1 1 1 -.names N_235.BLIF N_235_i +.names N_369.BLIF N_369_i +0 1 +.names pos_clk_un3_as_030_d0_n.BLIF N_67.BLIF as_030_000_sync_0_un1_n +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_o2_2_x2.X2 +1 1 +.names N_254.BLIF N_254_i 0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 1- 1 -1 1 -.names N_236.BLIF N_236_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C 1 1 -.names A_DECODE_16_.BLIF a_decode_c_16__n -1 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +.names N_256.BLIF N_256_i 0 1 -.names A_DECODE_17_.BLIF a_decode_c_17__n -1 1 -.names N_231.BLIF N_231_i +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names AS_000_c.BLIF AS_000_i +.names N_255.BLIF N_255_i 0 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -.names A_DECODE_18_.BLIF a_decode_c_18__n -1 1 -.names N_230.BLIF N_230_i -0 1 -.names AS_000_c.BLIF CLK_000_P_SYNC_10_.BLIF N_203_i +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names A_DECODE_19_.BLIF a_decode_c_19__n +.names IPL_D0_0_.BLIF G_116.X1 1 1 -.names pos_clk_un4_clk_000_pe_0_n.BLIF pos_clk_un4_clk_000_pe_n +.names N_267.BLIF N_267_i 0 1 -.names N_137_i.BLIF SM_AMIGA_4_.BLIF N_187_0 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -.names A_DECODE_20_.BLIF a_decode_c_20__n -1 1 -.names N_22.BLIF N_22_i +.names N_266.BLIF N_266_i 0 1 -.names N_349_i.BLIF RST_c.BLIF N_185_i -11 1 -.names A_DECODE_21_.BLIF a_decode_c_21__n -1 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_137.BLIF sm_amiga_i_3__n.BLIF N_184_0 -11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -.names A_DECODE_22_.BLIF a_decode_c_22__n -1 1 -.names N_224.BLIF N_224_i -0 1 -.names BERR_c.BLIF clk_000_p_sync_i_10__n.BLIF N_137_i -11 1 -.names A_DECODE_23_.BLIF a_decode_c_23__n -1 1 -.names N_226.BLIF N_226_i -0 1 -.names BGACK_000_c.BLIF N_203.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 -.names N_220.BLIF N_220_i -0 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D -1 1 -.names A_1_.BLIF a_c_1__n -1 1 -.names N_221.BLIF N_221_i -0 1 -.names N_137.BLIF SM_AMIGA_0_.BLIF N_349 -11 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names N_222.BLIF N_222_i -0 1 -.names N_137.BLIF SM_AMIGA_i_7_.BLIF N_335 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C -1 1 -.names N_217.BLIF N_217_i -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_323 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C -1 1 -.names BG_030.BLIF BG_030_c -1 1 -.names N_215.BLIF N_215_i -0 1 -.names N_187.BLIF sm_amiga_i_5__n.BLIF N_281 -11 1 -.names BG_000DFFreg.BLIF BG_000 -1 1 -.names N_219.BLIF N_219_i -0 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names N_195_0.BLIF N_195 -0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names N_190_0.BLIF N_190 -0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_12_.C -1 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names N_157_i.BLIF N_157 -0 1 -.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_148_0 -11 1 -.names CLK_000.BLIF CLK_000_c -1 1 -.names N_340.BLIF N_340_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_un5_bgack_030_int_d_i_n -11 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D -1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names N_141_0.BLIF N_141 -0 1 -.names N_347_i.BLIF N_348_i.BLIF N_178_i -11 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names N_337.BLIF N_337_i -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_181_i -11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C -1 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF N_196_0 -11 1 -.names un21_fpu_cs_i.BLIF FPU_CS -1 1 -.names N_291_0.BLIF N_291 -0 1 -.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_197_0 -11 1 -.names FPU_SENSE.BLIF FPU_SENSE_c -1 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D -1 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ -1 1 -.names N_146_0.BLIF N_146 -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n -0 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ -1 1 -.names N_149_i.BLIF N_149 -0 1 -.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un1_n -11 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ -1 1 -.names N_164_i.BLIF N_164 -0 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n -11 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names N_166_i.BLIF N_166 -0 1 -.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_207 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names IPL_1_.BLIF ipl_c_1__n +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C 1 1 -.names N_172_i.BLIF N_172 -0 1 -.names CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF N_199_0 -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +.names ipl_c_0__n.BLIF G_116.X2 1 1 -.names IPL_2_.BLIF ipl_c_2__n +.names N_57_0.BLIF inst_RESET_OUT.D +0 1 +.names N_363.BLIF a0_dma_0_un3_n +0 1 +.names N_151_0.BLIF N_151 +0 1 +.names inst_A0_DMA.BLIF N_363.BLIF a0_dma_0_un1_n +11 1 +.names N_321_i.BLIF N_321 +0 1 +.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names CLK_000_D_5_.BLIF CLK_000_D_6_.D 1 1 -.names N_176_i.BLIF N_176 +.names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names N_185_i.BLIF N_324_i.BLIF SM_AMIGA_0_.D -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 -.names N_186_0.BLIF inst_BGACK_030_INT_D.D -0 1 -.names N_199.BLIF sm_amiga_i_0__n.BLIF N_324 -11 1 -.names DTACK.BLIF DTACK_c +.names CLK_000_D_6_.BLIF CLK_000_D_7_.D 1 1 -.names N_192_0.BLIF N_192 +.names N_361.BLIF N_361_i 0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names N_228.BLIF N_228_i -0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names IPL_D0_2_.BLIF G_136.X1 -1 1 -.names N_292.BLIF E -1 1 -.names N_227.BLIF N_227_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names VPA.BLIF VPA_c -1 1 -.names N_343.BLIF N_343_i -0 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 -11 1 -.names ipl_c_2__n.BLIF G_136.X2 -1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names N_223.BLIF N_223_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 -11 1 -.names RST.BLIF RST_c -1 1 -.names N_225.BLIF N_225_i -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_341 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names CLK_000_D_10_.BLIF clk_000_d_i_10__n -0 1 -.names IPL_D0_1_.BLIF G_135.X1 -1 1 -.names N_53_0.BLIF IPL_D0_2_.D -0 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names N_27.BLIF N_27_i -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 -11 1 -.names ipl_c_1__n.BLIF G_135.X2 -1 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names N_30_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names N_207.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE -1 1 -.names N_28.BLIF N_28_i -0 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_294_0 -11 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names N_31_0.BLIF IPL_030DFF_1_reg.D -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_295_0 -11 1 -.names IPL_D0_0_.BLIF G_134.X1 -1 1 -.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names N_29.BLIF N_29_i -0 1 -.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_298_0 -11 1 -.names un1_amiga_bus_enable_dma_high_0__n.BLIF AMIGA_BUS_ENABLE_HIGH -1 1 -.names N_32_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 -.names ipl_c_0__n.BLIF G_134.X2 -1 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names N_328_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_224_1.BLIF clk_000_p_sync_i_10__n.BLIF N_224 -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names N_329_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names N_216_i.BLIF rst_dly_i_0__n.BLIF N_222_1 -11 1 -.names N_258_0.BLIF N_258 -0 1 -.names N_330_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF pos_clk_ds_000_dma_4_0_n -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_.X1 -1 1 -.names N_222_1.BLIF rst_dly_i_1__n.BLIF N_222 -11 1 -.names N_357.BLIF N_357_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 -.names N_149.BLIF N_216_i.BLIF N_215_1 -11 1 -.names N_254.BLIF N_254_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D -11 1 -.names cpu_est_0_.BLIF cpu_est_0_0_x2_0_x2_0_.X2 -1 1 -.names N_215_1.BLIF rst_dly_i_2__n.BLIF N_215 -11 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_214_i.BLIF N_212_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_315.BLIF N_315_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF CLK_000_N_SYNC_0_.D -11 1 -.names pos_clk_ipl_1_n.BLIF N_213_i.BLIF pos_clk_ipl_n -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 -.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 -1 1 -.names AS_000_i.BLIF N_200_i.BLIF N_327_1 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names N_327_1.BLIF RW_000_c.BLIF N_327 -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 -1 1 -.names inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF N_319_1 -11 1 -.names N_26.BLIF N_26_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names N_319_1.BLIF SM_AMIGA_0_.BLIF N_319 -11 1 -.names N_33_0.BLIF BG_000DFFreg.D -0 1 -.names CLK_030_H_i.BLIF N_197.BLIF N_320 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C -1 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_285_1 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names CLK_000_P_SYNC_10_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X1 -1 1 -.names N_285_1.BLIF cpu_est_i_3__n.BLIF N_285 -11 1 -.names N_38_0.BLIF inst_UDS_000_INT.D -0 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_321 -11 1 -.names N_184.BLIF RST_c.BLIF N_277_1 -11 1 -.names N_17.BLIF N_17_i -0 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_322 -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X2 -1 1 -.names N_277_1.BLIF SM_AMIGA_2_.BLIF N_277 -11 1 -.names N_42_0.BLIF inst_LDS_000_INT.D -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_325 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C -1 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_236_1 -11 1 -.names N_4.BLIF N_4_i -0 1 -.names BGACK_030_INT_i.BLIF N_181.BLIF N_328 -11 1 -.names N_236_1.BLIF cpu_est_i_3__n.BLIF N_236 -11 1 -.names N_48_0.BLIF inst_DSACK1_INTreg.D -0 1 -.names BGACK_030_INT_i.BLIF N_181_i.BLIF N_329 -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un23_bgack_030_int_i_0_x2.X1 -1 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_228_1 -11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names G_136.BLIF N_214_i -0 1 -.names N_228_1.BLIF sm_amiga_i_4__n.BLIF N_228 -11 1 -.names N_51_0.BLIF IPL_D0_0_.D -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C -1 1 -.names CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_x2.X2 -1 1 -.names N_172.BLIF BERR_i.BLIF N_225_1 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_225_1.BLIF clk_000_n_sync_i_12__n.BLIF N_225 -11 1 -.names N_52_0.BLIF IPL_D0_1_.D -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_176.BLIF BERR_i.BLIF N_224_1 -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -.names N_120_0_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_120_0 -11 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 -11 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C -1 1 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -.names N_320_i.BLIF RST_c.BLIF N_106_i_1 -11 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -.names N_106_i_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF inst_CLK_030_H.D -11 1 -.names N_4_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -.names AS_000_i.BLIF N_186_0.BLIF N_103_i_1 -11 1 -.names N_17_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -.names N_103_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D -11 1 -.names N_21_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C -1 1 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -.names AS_000_i.BLIF N_186_0.BLIF N_92_i_1 -11 1 -.names N_26_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D -1 1 -.names N_92_i_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF CYCLE_DMA_0_.D -11 1 .names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D +.names CLK_000_D_7_.BLIF CLK_000_D_8_.D 1 1 -.names N_206_i.BLIF N_283_i.BLIF N_140_i_1 -11 1 +.names N_283.BLIF N_283_i +0 1 .names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +.names CLK_000_D_8_.BLIF CLK_000_D_9_.D 1 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 .names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i +.names CLK_000_D_9_.BLIF CLK_000_D_10_.D +1 1 +.names N_345.BLIF N_345_i 0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_10_.C -1 1 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -.names N_281_i.BLIF N_282_i.BLIF N_138_i_1 -11 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 1- 1 -1 1 -.names N_196.BLIF sm_amiga_i_3__n.BLIF N_227 -11 1 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 -.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n 0 1 -.names N_323.BLIF inst_AS_030_D0.D +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +.names UDS_000_c.BLIF UDS_000_c_i 0 1 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D -1 1 -.names N_148.BLIF CLK_000_D_11_.BLIF N_344_1 +.names N_26_i.BLIF RST_c.BLIF N_33_0 11 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +.names LDS_000_c.BLIF LDS_000_c_i 0 1 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D -1 1 -.names N_344_1.BLIF clk_000_d_i_10__n.BLIF N_344 +.names N_22_i.BLIF RST_c.BLIF N_37_0 11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names G_134.BLIF N_212_i +.names N_171_i.BLIF N_171 0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C -1 1 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +.names N_18_i.BLIF RST_c.BLIF N_41_0 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +.names N_21.BLIF N_21_i +0 1 +.names N_7_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names N_38_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_5_i.BLIF RST_c.BLIF N_47_0 +11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names N_4_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names N_55_0.BLIF inst_DTACK_D0.D +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names N_249.BLIF N_249_i +0 1 +.names BGACK_030_INT_i.BLIF N_171.BLIF N_283 +11 1 +.names N_248.BLIF N_248_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names N_250.BLIF N_250_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names N_18.BLIF N_18_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names N_259.BLIF size_dma_0_1__un3_n +0 1 +.names N_22.BLIF N_22_i +0 1 +.names SIZE_DMA_1_.BLIF N_259.BLIF size_dma_0_1__un1_n +11 1 +.names N_37_0.BLIF inst_A0_DMA.D +0 1 +.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names N_26.BLIF N_26_i +0 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 -.names G_135.BLIF N_213_i +.names N_33_0.BLIF BG_000DFFreg.D 0 1 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +.names N_259.BLIF size_dma_0_0__un3_n +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names SIZE_DMA_0_.BLIF N_259.BLIF size_dma_0_0__un1_n +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C 1 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names N_10.BLIF N_10_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_54_0 +11 1 +.names N_43_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_10_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names N_54_0.BLIF inst_VPA_D.D +0 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names N_370.BLIF N_370_i +0 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names N_63_0.BLIF N_63 +0 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +.names N_278_0.BLIF N_278 +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_279_0.BLIF N_279 +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names N_260.BLIF N_260_i +0 1 +.names N_114.BLIF N_114_i +0 1 +.names N_67_0.BLIF N_67 +0 1 +.names N_278.BLIF dsack1_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_6_.C +1 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names N_114_i.BLIF N_278.BLIF dsack1_int_0_un1_n +11 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_313_0.BLIF N_313 +0 1 +.names N_108.BLIF cpu_est_0_3__un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_7_.C +1 1 +.names N_4.BLIF N_4_i +0 1 +.names cpu_est_3_.BLIF N_108.BLIF cpu_est_0_3__un1_n +11 1 +.names N_48_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names N_316_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_5.BLIF N_5_i +0 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 +.names N_47_0.BLIF inst_AS_000_INT.D +0 1 +.names N_108.BLIF cpu_est_0_2__un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_8_.C +1 1 +.names N_7.BLIF N_7_i +0 1 +.names cpu_est_2_.BLIF N_108.BLIF cpu_est_0_2__un1_n +11 1 +.names N_46_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_219.BLIF N_219_i +0 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names N_218.BLIF N_218_i +0 1 +.names N_108.BLIF cpu_est_0_1__un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_9_.C +1 1 +.names N_224.BLIF N_224_i +0 1 +.names cpu_est_1_.BLIF N_108.BLIF cpu_est_0_1__un1_n +11 1 +.names N_222.BLIF N_222_i +0 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_223.BLIF N_223_i +0 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names A_DECODE_16_.BLIF a_decode_c_16__n +1 1 +.names N_322_i.BLIF N_322 +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_10_.C +1 1 +.names A_DECODE_17_.BLIF a_decode_c_17__n +1 1 +.names N_312.BLIF N_312_i +0 1 +.names N_21_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names A_DECODE_18_.BLIF a_decode_c_18__n +1 1 +.names N_139_0.BLIF N_139 +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names A_DECODE_19_.BLIF a_decode_c_19__n +1 1 +.names N_108_i.BLIF N_108 +0 1 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names CLK_000_D_10_.BLIF CLK_000_D_11_.D +1 1 +.names A_DECODE_20_.BLIF a_decode_c_20__n +1 1 +.names N_258.BLIF N_258_i +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names A_DECODE_21_.BLIF a_decode_c_21__n +1 1 +.names N_257.BLIF N_257_i +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_11_.C +1 1 +.names A_DECODE_22_.BLIF a_decode_c_22__n +1 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names A_DECODE_23_.BLIF a_decode_c_23__n +1 1 +.names pos_clk_un3_as_030_d0_0_n.BLIF pos_clk_un3_as_030_d0_n +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_171_i +11 1 +.names N_107_0.BLIF inst_AS_030_D0.D +0 1 +.names N_345_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names CLK_000_D_11_.BLIF CLK_000_D_12_.D +1 1 +.names A_1_.BLIF a_c_1__n +1 1 +.names N_115.BLIF N_115_i +0 1 +.names N_283_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names N_356.BLIF N_356_i +0 1 +.names BGACK_000_c.BLIF N_370_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_12_.C +1 1 +.names N_156_0.BLIF N_156 +0 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names BG_030.BLIF BG_030_c +1 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names inst_RESET_OUT.BLIF un1_as_030_i.BLIF un3_as_030_i +11 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names N_159_i.BLIF N_159 +0 1 +.names AS_000_c.BLIF N_319_i.BLIF N_370 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names BGACK_030_INT_i.BLIF N_171_i.BLIF N_345 +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_180_i.BLIF N_180 +0 1 +.names N_253_i.BLIF N_369_i.BLIF cpu_est_2_0_2__n +11 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names N_334.BLIF N_334_i +0 1 +.names N_250_i.BLIF N_251_i.BLIF cpu_est_2_0_1__n +11 1 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +.names N_335.BLIF N_335_i +0 1 +.names N_248_i.BLIF N_249_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names N_244.BLIF N_244_i +0 1 +.names N_321_i.BLIF cpu_est_i_2__n.BLIF N_369 +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names N_233.BLIF N_233_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names N_355.BLIF N_355_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_362 +11 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names N_229.BLIF N_229_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names N_246.BLIF N_246_i +0 1 +.names N_360.BLIF N_364.BLIF N_267 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names sm_amiga_nss_i_0_0__n.BLIF SM_AMIGA_i_7_.D +0 1 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_266 +11 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names N_220.BLIF N_220_i +0 1 +.names N_151.BLIF cpu_est_i_2__n.BLIF N_256 +11 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_186.BLIF cpu_est_2_.BLIF N_255 +11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names N_332.BLIF N_332_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names N_240.BLIF N_240_i +0 1 +.names N_196.BLIF cpu_est_i_2__n.BLIF N_254 +11 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names N_315_0.BLIF SM_AMIGA_6_.D +0 1 +.names N_321.BLIF cpu_est_2_.BLIF N_253 +11 1 +.names N_281_0.BLIF N_281 +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_250 +11 1 +.names DTACK.BLIF DTACK_c +1 1 +.names N_270.BLIF N_270_i +0 1 +.names N_366_i.BLIF SM_AMIGA_i_7_.BLIF N_182_i +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names N_282.BLIF N_282_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_101_i +11 1 +.names N_317_i.BLIF E +1 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_323_0 +11 1 +.names VPA.BLIF VPA_c +1 1 +.names RW_c.BLIF RW_c_i +0 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names N_140_0.BLIF N_140 +0 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_196_0 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names RST.BLIF RST_c +1 1 +.names N_353.BLIF N_353_i +0 1 +.names N_108_i.BLIF N_169.BLIF N_195_0 +11 1 +.names N_143_0.BLIF N_143 +0 1 +.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_186_0 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_361_i.BLIF N_362_i.BLIF N_169_i +11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_320_i.BLIF N_320 +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_2__n.BLIF N_158_i +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C +1 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names N_357.BLIF N_357_i +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_321_i +11 1 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +.names N_23.BLIF N_23_i +0 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names N_36_0.BLIF inst_UDS_000_INT.D +0 1 +.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_151_0 +11 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names N_19.BLIF N_19_i +0 1 +.names N_266_i.BLIF N_267_i.BLIF N_57_0 +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +.names N_209.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +.names N_40_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_255_i.BLIF N_256_i.BLIF N_317_i +11 1 +.names N_17.BLIF N_17_i +0 1 +.names N_253_i.BLIF N_254_i.BLIF N_316_i +11 1 +.names N_238_1.BLIF SM_AMIGA_5_.BLIF N_238 +11 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_229_i.BLIF N_230_i.BLIF sm_amiga_nss_0_7__n +11 1 +.names N_169.BLIF N_360.BLIF N_233_1 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names N_231_i.BLIF N_232_i.BLIF sm_amiga_nss_0_6__n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +.names N_233_1.BLIF SM_AMIGA_3_.BLIF N_233 +11 1 +.names N_52_0.BLIF IPL_D0_1_.D +0 1 +.names N_233_i.BLIF N_234_i.BLIF sm_amiga_nss_0_5__n +11 1 +.names N_108.BLIF N_310.BLIF N_231_1 +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names N_235_i.BLIF N_236_i.BLIF sm_amiga_nss_0_4__n +11 1 +.names N_231_1.BLIF SM_AMIGA_1_.BLIF N_231 +11 1 +.names N_53_0.BLIF IPL_D0_2_.D +0 1 +.names N_238_i.BLIF N_239_i.BLIF sm_amiga_nss_0_2__n +11 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +.names N_245_i.BLIF rst_dly_i_0__n.BLIF N_224_1 +11 1 +.names N_28.BLIF N_28_i +0 1 +.names N_268_i.BLIF N_269_i.BLIF sm_amiga_nss_0_3__n +11 1 +.names N_224_1.BLIF rst_dly_i_1__n.BLIF N_224 +11 1 +.names N_31_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_346_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF pos_clk_ds_000_dma_4_0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +.names N_245_i.BLIF N_322.BLIF N_218_1 +11 1 +.names N_29.BLIF N_29_i +0 1 +.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_272_0 +11 1 +.names N_218_1.BLIF rst_dly_i_2__n.BLIF N_218 +11 1 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_93_i +11 1 +.names N_243_i.BLIF N_241_i.BLIF pos_clk_ipl_1_n +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +.names pos_clk_ipl_1_n.BLIF N_242_i.BLIF pos_clk_ipl_n +11 1 +.names N_25.BLIF N_25_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_319_i +11 1 +.names pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF AS_000_i.BLIF N_277_i_1 +11 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +.names N_277_i_1.BLIF N_101_i.BLIF CYCLE_DMA_1_.D +11 1 +.names N_24.BLIF N_24_i +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names N_226_i.BLIF N_331_i.BLIF N_314_i_1 +11 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_142_0 +11 1 +.names N_314_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +11 1 +.names N_363.BLIF rw_000_dma_0_un3_n +0 1 +.names N_310_i.BLIF N_359_i.BLIF N_144_0 +11 1 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +.names N_142.BLIF CLK_000_D_11_.BLIF N_356_1 +11 1 +.names inst_RW_000_DMA.BLIF N_363.BLIF rw_000_dma_0_un1_n +11 1 +.names CLK_030_H_i.BLIF N_323.BLIF N_341 +11 1 +.names N_356_1.BLIF clk_000_d_i_10__n.BLIF N_356 +11 1 +.names N_281.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_365.BLIF SM_AMIGA_4_.BLIF N_268 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +.names AS_000_i.BLIF RW_000_c.BLIF N_282_1 +11 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names N_360.BLIF SM_AMIGA_5_.BLIF N_269 +11 1 +.names N_282_1.BLIF un1_as_030_i.BLIF N_282 11 1 .names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names N_322.BLIF N_322_i -0 1 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D -1 1 -.names CLK_000_P_SYNC_10_.BLIF cpu_est_i_0__n.BLIF N_230_1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_346 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_251_1 11 1 .names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D -1 1 -.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D -1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_230_2 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_290 +11 1 +.names N_251_1.BLIF cpu_est_i_3__n.BLIF N_251 11 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names N_322_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n -11 1 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 -.names N_230_1.BLIF N_230_2.BLIF N_230_3 +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C -1 1 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D -1 1 -.names N_230_3.BLIF cpu_est_i_3__n.BLIF N_230 -11 1 -.names N_275.BLIF N_275_i +.names AS_000_c.BLIF AS_000_i 0 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names N_365.BLIF SM_AMIGA_6_.BLIF N_240_1 +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_311 +11 1 +.names N_240_1.BLIF SM_AMIGA_i_7_.BLIF N_240 +11 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names N_310.BLIF SM_AMIGA_3_.BLIF N_355 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +1 1 +.names N_108.BLIF N_310.BLIF N_238_1 +11 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 +11 1 +.names CLK_000_D_10_.BLIF clk_000_d_i_10__n +0 1 +.names N_115_1.BLIF N_115_2.BLIF N_115 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_319_i.BLIF RST_c.BLIF N_359 +11 1 +.names CLK_000_D_2_.BLIF N_332_4.BLIF N_332_1 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_310.BLIF N_319.BLIF N_365 +11 1 +.names N_332_1.BLIF sm_amiga_i_i_7__n.BLIF N_332 +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low +11 1 +.names N_319_i.BLIF SM_AMIGA_0_.BLIF N_366 +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_246_1 +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +11 1 +.names CLK_000_D_2_.BLIF N_180_i.BLIF N_246_2 +11 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_320_i.BLIF N_332_4.BLIF N_246_3 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names N_246_1.BLIF N_246_2.BLIF N_246_4 +11 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names N_246_4.BLIF N_246_3.BLIF N_246 +11 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names AS_030_000_SYNC_i.BLIF clk_000_d_i_1__n.BLIF N_332_4_1 +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +1- 1 +-1 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names RST_c.BLIF nEXP_SPACE_c.BLIF N_332_4_2 +11 1 +.names N_29_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names N_365.BLIF SM_AMIGA_0_.BLIF N_229 +11 1 +.names N_332_4_1.BLIF N_332_4_2.BLIF N_332_4 +11 1 +.names N_28_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_360.BLIF SM_AMIGA_1_.BLIF N_230 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names N_290_i.BLIF RW_000_i.BLIF N_273_0_1 +11 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names N_359.BLIF SM_AMIGA_2_.BLIF N_232 +11 1 +.names N_273_0_1.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_273_0 +11 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names N_365.BLIF SM_AMIGA_2_.BLIF N_234 +11 1 +.names N_341_i.BLIF RST_c.BLIF N_276_i_1 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names N_195.BLIF N_355.BLIF N_235 +11 1 +.names N_276_i_1.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_19_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names N_359.BLIF SM_AMIGA_4_.BLIF N_236 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names N_157_i.BLIF N_363.BLIF N_260_1 +11 1 +.names N_23_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names N_359.BLIF SM_AMIGA_6_.BLIF N_239 +11 1 +.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_260_2 +11 1 +.names N_24_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names N_260_1.BLIF N_260_2.BLIF N_260 +11 1 +.names N_25_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names cycle_dma_i_0__n.BLIF N_319.BLIF N_262 +11 1 +.names FPU_SENSE_i.BLIF N_157.BLIF un21_fpu_cs_1 +11 1 +.names N_132.BLIF N_132_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names N_363.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_363.BLIF amiga_bus_enable_dma_high_0_un1_n +11 1 +.names CYCLE_DMA_0_.BLIF N_319_i.BLIF N_263 +11 1 +.names un22_berr_1_0.BLIF N_157.BLIF un22_berr +11 1 +.names N_132_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names G_116.BLIF N_241_i +0 1 +.names N_222_i.BLIF N_223_i.BLIF N_275_i_1 +11 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names G_117.BLIF N_242_i +0 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names N_224_i.BLIF RST_c.BLIF N_275_i_2 +11 1 +.names N_131.BLIF N_131_i +0 1 +.names G_118.BLIF N_243_i +0 1 +.names N_275_i_1.BLIF N_275_i_2.BLIF RST_DLY_1_.D +11 1 +.names N_363.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_218_i.BLIF N_219_i.BLIF N_274_i_1 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_363.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_220_i.BLIF RST_c.BLIF N_274_i_2 +11 1 +.names N_131_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names N_274_i_1.BLIF N_274_i_2.BLIF RST_DLY_2_.D +11 1 .names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 1- 1 -1 1 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D -1 1 -.names N_146.BLIF N_172_i.BLIF N_226_1 -11 1 -.names N_258.BLIF dsack1_int_0_un3_n +.names ahigh_c_27__n.BLIF ahigh_i_27__n 0 1 -.names N_321.BLIF N_321_i +.names N_143.BLIF sm_amiga_i_0__n.BLIF N_115_1 +11 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D -1 1 -.names N_176_i.BLIF sm_amiga_i_0__n.BLIF N_226_2 -11 1 -.names N_275_i.BLIF N_258.BLIF dsack1_int_0_un1_n -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +.names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +.names sm_amiga_i_5__n.BLIF SM_AMIGA_i_7_.BLIF N_115_2 +11 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_60_i_1.BLIF N_60_i_2.BLIF CYCLE_DMA_0_.D +11 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 -.names N_226_1.BLIF N_226_2.BLIF N_226_3 +.names N_158_i.BLIF N_319_i.BLIF N_248_1 11 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names N_321_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C -1 1 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D -1 1 -.names N_226_3.BLIF sm_amiga_i_3__n.BLIF N_226 -11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_23 1- 1 -1 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_248_2 +11 1 +.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_357 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 +1- 1 +-1 1 +.names N_248_1.BLIF N_248_2.BLIF N_248 +11 1 +.names N_140.BLIF N_319_i.BLIF N_353 +11 1 +.names un4_uds_000.BLIF un4_uds_000_i +0 1 +.names N_108_i.BLIF N_369.BLIF N_249_1 +11 1 +.names BERR_c.BLIF RST_c.BLIF N_310 +11 1 +.names un4_lds_000.BLIF un4_lds_000_i +0 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C 1 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_249_2 +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_131 +11 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names N_249_1.BLIF N_249_2.BLIF N_249 +11 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names N_151_0.BLIF N_158_i.BLIF N_361_1 +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_132 +11 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_361_2 +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names N_361_1.BLIF N_361_2.BLIF N_361 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_270 +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_157_1 +11 1 +.names N_156.BLIF SM_AMIGA_1_.BLIF N_114 +11 1 +.names N_273.BLIF ds_000_dma_0_un3_n +0 1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_157_2 +11 1 +.names N_320.BLIF N_360.BLIF N_244 +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_273.BLIF ds_000_dma_0_un1_n +11 1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_157_3 +11 1 +.names N_310.BLIF N_320.BLIF N_335 +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +1 1 +.names N_157_1.BLIF N_157_2.BLIF N_157_4 +11 1 +.names N_144.BLIF N_180.BLIF N_334 +11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 455e408..db003c3 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,128 +1,121 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Fri Aug 19 00:20:41 2016 +#$ DATE Fri Aug 19 00:39:35 2016 #$ MODULE bus68030 -#$ PINS 75 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \ -# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ \ -# A_DECODE_13_ IPL_030_2_ A_DECODE_12_ A_DECODE_11_ IPL_2_ A_DECODE_10_ A_DECODE_9_ \ -# FC_1_ A_DECODE_8_ AS_030 A_DECODE_7_ AS_000 A_DECODE_6_ RW_000 A_DECODE_5_ DS_030 \ -# A_DECODE_4_ UDS_000 A_DECODE_3_ LDS_000 A_DECODE_2_ nEXP_SPACE A_0_ BERR IPL_030_1_ \ -# BG_030 IPL_030_0_ BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 \ -# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW \ -# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ -# CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ -#$ NODES 694 N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n \ -# N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 pos_clk_un10_sm_amiga_i_n \ -# cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i \ -# sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 \ -# cpu_est_2_0_2__n vma_int_0_un3_n inst_BGACK_030_INTreg N_223 N_315_i \ -# vma_int_0_un1_n vcc_n_n N_343 N_291_0 vma_int_0_un0_n inst_VMA_INTreg N_192 \ -# AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n \ -# un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n \ -# un1_amiga_bus_enable_low N_315 N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 \ -# cpu_est_2_2__n N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ -# sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ -# un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ -# rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ -# N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ -# un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ -# cpu_est_2_ pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n cpu_est_3_ \ -# un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n cpu_est_0_ un21_fpu_cs_i \ -# N_226_i ds_000_enable_0_un1_n cpu_est_1_ N_275_i ds_000_enable_0_un0_n \ -# inst_AS_000_INT clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n \ -# inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ -# inst_AS_030_D0 rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n inst_AS_030_000_SYNC \ -# BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n inst_BGACK_030_INT_D \ -# cpu_est_i_2__n N_217_i un1_amiga_bus_enable_dma_high_0_m2_0__un1_n \ -# inst_AS_000_DMA nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n \ -# inst_DS_000_DMA rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n \ -# CYCLE_DMA_0_ cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n CYCLE_DMA_1_ \ -# cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n SIZE_DMA_0_ VPA_D_i N_195_0 \ -# amiga_bus_enable_dma_high_0_un3_n SIZE_DMA_1_ sm_amiga_i_3__n N_190_0 \ -# amiga_bus_enable_dma_high_0_un1_n inst_VPA_D sm_amiga_i_0__n N_157_i \ -# amiga_bus_enable_dma_high_0_un0_n inst_UDS_000_INT cpu_est_i_3__n N_154_i \ -# size_dma_0_0__un3_n inst_LDS_000_INT sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n \ -# inst_CLK_OUT_PRE_D RESET_OUT_i N_141_0 size_dma_0_0__un0_n CLK_000_D_10_ \ -# BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n CLK_000_D_11_ sm_amiga_i_2__n \ -# N_216_i size_dma_0_1__un1_n inst_DTACK_D0 sm_amiga_i_4__n N_337_i \ -# size_dma_0_1__un0_n inst_RESET_OUT clk_000_p_sync_i_10__n ds_000_dma_0_un3_n \ -# inst_CLK_OUT_PRE_50 sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n CLK_000_D_1_ \ -# sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n CLK_000_D_0_ clk_000_d_i_11__n \ -# un1_as_000_i as_000_dma_0_un3_n CLK_000_P_SYNC_10_ sm_amiga_i_6__n N_284_i \ -# as_000_dma_0_un1_n SM_AMIGA_5_ RW_i N_285_i as_000_dma_0_un0_n IPL_D0_0_ \ -# DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n IPL_D0_1_ LDS_000_INT_i N_280_i \ -# rw_000_dma_0_un1_n IPL_D0_2_ UDS_000_INT_i N_277_i rw_000_dma_0_un0_n CLK_000_D_2_ \ -# AS_030_i N_257_0 a0_dma_0_un3_n CLK_000_D_3_ AS_000_INT_i N_235_i a0_dma_0_un1_n \ -# CLK_000_D_4_ a_decode_i_19__n N_236_i a0_dma_0_un0_n CLK_000_D_5_ a_decode_i_18__n \ -# cpu_est_2_0_1__n a_decode_15__n CLK_000_D_6_ a_decode_i_16__n N_231_i CLK_000_D_7_ \ -# AS_000_i N_230_i a_decode_14__n CLK_000_D_8_ FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ -# CLK_000_D_9_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_000_D_12_ \ -# CLK_030_i N_37_0 pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n SM_AMIGA_0_ \ -# clk_000_d_i_10__n N_334_i inst_DSACK1_INTreg RW_000_i N_335_i a_decode_11__n \ -# a_i_1__n N_194_0 CLK_030_H_i N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i \ -# un1_SM_AMIGA_5_i CLK_000_N_SYNC_0_ clk_000_d_i_0__n N_346_i a_decode_9__n \ -# SM_AMIGA_4_ clk_000_d_i_1__n N_163_i inst_DS_000_ENABLE AS_030_D0_i N_345_i \ -# a_decode_8__n CLK_000_N_SYNC_12_ size_dma_i_0__n N_344_i RST_DLY_0_ size_dma_i_1__n \ -# N_153_0 a_decode_7__n RST_DLY_1_ ahigh_i_30__n pos_clk_un3_as_030_d0_i_n RST_DLY_2_ \ -# ahigh_i_31__n N_293_0 a_decode_6__n CLK_000_P_SYNC_0_ ahigh_i_28__n N_233_i \ -# CLK_000_P_SYNC_1_ ahigh_i_29__n N_232_i a_decode_5__n CLK_000_P_SYNC_2_ \ -# ahigh_i_26__n N_290_0 CLK_000_P_SYNC_3_ ahigh_i_27__n VPA_c_i a_decode_4__n \ -# CLK_000_P_SYNC_4_ ahigh_i_24__n N_54_0 CLK_000_P_SYNC_5_ ahigh_i_25__n N_5_i \ -# a_decode_3__n CLK_000_P_SYNC_6_ N_212_i N_47_0 CLK_000_P_SYNC_7_ N_213_i N_7_i \ -# a_decode_2__n CLK_000_P_SYNC_8_ N_214_i N_46_0 CLK_000_P_SYNC_9_ N_18_i \ -# CLK_000_N_SYNC_1_ N_41_0 CLK_000_N_SYNC_2_ N_321_i N_10_i CLK_000_N_SYNC_3_ N_322_i \ -# N_43_0 CLK_000_N_SYNC_4_ un6_ds_030_i DTACK_c_i CLK_000_N_SYNC_5_ DS_000_DMA_i \ -# N_55_0 CLK_000_N_SYNC_6_ un4_as_000_i pos_clk_un6_bgack_000_0_n CLK_000_N_SYNC_7_ \ -# un6_as_030_i N_137_i CLK_000_N_SYNC_8_ un4_lds_000_i N_184_0 CLK_000_N_SYNC_9_ \ -# un4_uds_000_i N_349_i CLK_000_N_SYNC_10_ AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i \ -# CLK_000_N_SYNC_11_ AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i \ -# inst_RW_000_INT AS_000_c N_324_i inst_RW_000_DMA inst_CLK_000_NE_D0 RW_000_c N_199_0 \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_197_0 inst_A0_DMA N_196_0 pos_clk_a0_dma_3_n \ -# UDS_000_c LDS_000_c_i SM_AMIGA_6_ UDS_000_c_i inst_CLK_030_H LDS_000_c N_181_i \ -# SM_AMIGA_1_ N_347_i SM_AMIGA_3_ size_c_0__n N_348_i SM_AMIGA_2_ N_178_i \ -# pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 pos_clk_un5_bgack_030_int_d_i_n \ -# N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n \ -# N_148_0 N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ -# ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i N_120_0 \ -# ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n \ -# N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i \ -# N_298_0 N_295_0 N_294_0 N_319_i un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i \ -# SM_AMIGA_i_7_ N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n \ -# G_134 N_3_i G_135 N_49_0 G_136 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i \ -# N_292 N_40_0 N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i \ -# N_298 N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ -# N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 \ -# a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n N_144_i_2 N_144_i_3 \ -# N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 a_c_0__n N_176_i_1 N_207 \ -# N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 \ -# nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 \ -# N_228 BG_030_c un10_ciin_6 N_236 un10_ciin_7 N_277 BG_000DFFreg un10_ciin_8 N_281 \ -# un10_ciin_9 N_282 un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 \ -# CLK_030_c N_347_2 N_319 pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ -# pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ -# un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 CLK_OUT_INTreg N_366_3 N_328 N_366_4 \ -# N_329 un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ -# IPL_030DFF_0_reg N_142_i_2 N_336 N_339_1 N_338 IPL_030DFF_1_reg N_280_1 N_339 N_280_2 \ -# N_341 IPL_030DFF_2_reg N_231_1 N_344 N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 \ -# pos_clk_un23_bgack_030_int_i_0_x2 ipl_c_1__n N_230_3 cpu_est_0_0_x2_0_x2_0_ \ -# N_226_1 pos_clk_CYCLE_DMA_5_0_i_x2 ipl_c_2__n N_226_2 pos_clk_CYCLE_DMA_5_1_i_x2 \ -# N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 N_132_i_1 N_366 N_120_0_1 \ -# N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 N_187 N_140_i_1 N_137 RST_c \ -# N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n N_10 RW_c \ -# N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 \ -# DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n \ -# AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 N_18 N_215_1 DS_000_ENABLE_1_sqmuxa \ -# pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i bg_000_0_un1_n N_233 \ -# pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 pos_clk_un9_bg_030_0_n \ -# uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n N_191 N_33_0 \ -# uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ -# lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n \ -# N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 dsack1_int_0_un0_n \ -# pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 \ -# ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n N_284 N_52_0 \ -# ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 \ -# ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n \ -# N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 cpu_est_0_3__un3_n N_280 N_29_i \ -# cpu_est_0_3__un1_n +#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \ +# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \ +# BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT \ +# AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 \ +# A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA \ +# A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE \ +# A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ \ +# AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ \ +# A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_ +#$ NODES 662 N_28 N_246_i bgack_030_int_0_un1_n N_17 sm_amiga_nss_i_0_0__n \ +# bgack_030_int_0_un0_n N_19 dsack1_int_0_un3_n N_23 N_220_i dsack1_int_0_un1_n N_24 \ +# N_219_i dsack1_int_0_un0_n N_25 N_218_i cpu_est_0_3__un3_n \ +# un1_amiga_bus_enable_low_i cpu_est_0_3__un1_n un21_fpu_cs_i N_224_i \ +# cpu_est_0_3__un0_n inst_BGACK_030_INTreg BGACK_030_INT_i N_222_i \ +# cpu_est_0_2__un3_n vcc_n_n AMIGA_BUS_ENABLE_DMA_LOW_i N_223_i cpu_est_0_2__un1_n \ +# inst_VMA_INTreg UDS_000_INT_i N_322_i cpu_est_0_2__un0_n gnd_n_n LDS_000_INT_i \ +# N_312_i cpu_est_0_1__un3_n un1_amiga_bus_enable_low N_131_i N_139_0 \ +# cpu_est_0_1__un1_n un6_as_030 N_132_i N_108_i cpu_est_0_1__un0_n un3_size RW_000_i \ +# N_258_i vma_int_0_un3_n un4_size a_i_1__n N_257_i vma_int_0_un1_n un4_uds_000 \ +# clk_000_d_i_11__n vma_int_0_un0_n un4_lds_000 sm_amiga_i_6__n N_245_i \ +# ipl_030_0_0__un3_n un4_as_000 clk_000_d_i_1__n nEXP_SPACE_c_i ipl_030_0_0__un1_n \ +# un10_ciin AS_030_000_SYNC_i un1_as_030_i ipl_030_0_0__un0_n un21_fpu_cs \ +# sm_amiga_i_0__n pos_clk_un3_as_030_d0_0_n ds_000_dma_0_un3_n un22_berr \ +# sm_amiga_i_3__n N_107_0 ds_000_dma_0_un1_n un6_ds_030 sm_amiga_i_i_7__n N_115_i \ +# ds_000_dma_0_un0_n cpu_est_3_ sm_amiga_i_5__n N_63_0 as_000_dma_0_un3_n cpu_est_0_ \ +# rst_dly_i_0__n N_278_0 as_000_dma_0_un1_n cpu_est_1_ rst_dly_i_1__n N_279_0 \ +# as_000_dma_0_un0_n cpu_est_2_ N_364_i_0 N_260_i a_decode_15__n inst_AS_000_INT \ +# cpu_est_i_0__n N_67_0 inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n \ +# pos_clk_rw_000_int_5_0_n a_decode_14__n inst_AS_030_D0 AS_030_i \ +# un1_SM_AMIGA_0_sqmuxa_1_0 inst_AS_030_000_SYNC FPU_SENSE_i un10_ciin_i \ +# a_decode_13__n inst_BGACK_030_INT_D N_157_i N_313_0 inst_AS_000_DMA \ +# a_decode_i_16__n N_4_i a_decode_12__n inst_DS_000_DMA a_decode_i_18__n N_48_0 \ +# CYCLE_DMA_0_ a_decode_i_19__n N_5_i a_decode_11__n CYCLE_DMA_1_ N_113_i N_47_0 \ +# SIZE_DMA_0_ N_114_i N_7_i a_decode_10__n SIZE_DMA_1_ AS_000_INT_i N_46_0 inst_VPA_D \ +# size_dma_i_1__n N_18_i a_decode_9__n inst_UDS_000_INT size_dma_i_0__n N_41_0 \ +# inst_LDS_000_INT RESET_OUT_i N_22_i a_decode_8__n inst_CLK_OUT_PRE_D cpu_est_i_1__n \ +# N_37_0 CLK_000_D_1_ cpu_est_i_2__n N_26_i a_decode_7__n CLK_000_D_10_ VPA_D_i N_33_0 \ +# CLK_000_D_11_ DTACK_D0_i BG_030_c_i a_decode_6__n inst_DTACK_D0 cpu_est_i_3__n \ +# pos_clk_un6_bg_030_i_n inst_RESET_OUT CLK_030_i pos_clk_un9_bg_030_0_n \ +# a_decode_5__n CLK_000_D_0_ clk_000_d_i_0__n N_10_i inst_CLK_OUT_PRE_50 \ +# clk_000_d_i_10__n N_43_0 a_decode_4__n IPL_D0_0_ AS_000_DMA_i VPA_c_i IPL_D0_1_ \ +# AS_000_i N_54_0 a_decode_3__n IPL_D0_2_ CLK_030_H_i un3_as_030_i CLK_000_D_2_ \ +# cycle_dma_i_0__n N_370_i a_decode_2__n CLK_000_D_3_ AS_030_D0_i \ +# pos_clk_un6_bgack_000_0_n CLK_000_D_4_ ahigh_i_30__n N_283_i CLK_000_D_5_ \ +# ahigh_i_31__n pos_clk_size_dma_6_0_0__n CLK_000_D_6_ ahigh_i_28__n N_345_i \ +# CLK_000_D_7_ ahigh_i_29__n pos_clk_size_dma_6_0_1__n CLK_000_D_8_ ahigh_i_26__n \ +# UDS_000_c_i CLK_000_D_9_ ahigh_i_27__n LDS_000_c_i CLK_000_D_12_ ahigh_i_24__n \ +# N_171_i pos_clk_un6_bg_030_n ahigh_i_25__n N_21_i inst_AMIGA_BUS_ENABLE_DMA_HIGH \ +# N_241_i N_38_0 inst_DSACK1_INTreg N_242_i DTACK_c_i pos_clk_ipl_n N_243_i N_55_0 \ +# inst_DS_000_ENABLE N_249_i SM_AMIGA_6_ un6_ds_030_i N_248_i SM_AMIGA_0_ DS_000_DMA_i \ +# pos_clk_un9_clk_000_pe_0_n SM_AMIGA_4_ un4_as_000_i N_250_i inst_RW_000_INT \ +# un6_as_030_i N_251_i inst_RW_000_DMA un4_lds_000_i cpu_est_2_0_1__n RST_DLY_0_ \ +# un4_uds_000_i N_253_i RST_DLY_1_ AS_030_c N_369_i RST_DLY_2_ cpu_est_2_0_2__n \ +# inst_A0_DMA AS_000_c N_254_i inst_CLK_030_H N_316_i SM_AMIGA_1_ RW_000_c N_256_i \ +# SM_AMIGA_5_ N_255_i SM_AMIGA_3_ N_317_i SM_AMIGA_2_ UDS_000_c N_267_i \ +# pos_clk_ds_000_dma_4_n N_266_i N_3 LDS_000_c N_57_0 N_8 N_151_0 size_c_0__n N_321_i \ +# N_158_i size_c_1__n VMA_INT_i N_361_i ahigh_c_24__n N_362_i N_27 N_169_i ahigh_c_25__n \ +# N_186_0 N_195_0 ahigh_c_26__n N_196_0 ahigh_c_27__n N_263_i N_262_i ahigh_c_28__n \ +# N_323_0 N_101_i ahigh_c_29__n N_366_i N_182_i ahigh_c_30__n \ +# pos_clk_un23_bgack_030_int_i_0_0_n N_310_i ahigh_c_31__n N_359_i N_144_0 \ +# CLK_OUT_PRE_D_i N_142_0 N_311_i N_319_i N_93_i N_272_0 N_290_i N_273_0 N_346_i \ +# pos_clk_ds_000_dma_4_0_n N_268_i N_269_i SM_AMIGA_i_7_ sm_amiga_nss_0_3__n N_341_i \ +# N_238_i N_239_i sm_amiga_nss_0_2__n N_263 N_235_i G_116 N_236_i G_117 \ +# sm_amiga_nss_0_4__n G_118 N_234_i pos_clk_un23_bgack_030_int_i_0_n \ +# sm_amiga_nss_0_5__n N_272 N_231_i N_273 N_232_i sm_amiga_nss_0_6__n N_313 N_230_i \ +# a_decode_c_16__n sm_amiga_nss_0_7__n N_226_i N_108 a_decode_c_17__n N_331_i N_319 \ +# N_142 a_decode_c_18__n un1_as_000_i N_144 N_27_i N_322 a_decode_c_19__n N_30_0 N_169 \ +# ipl_c_i_0__n N_195 a_decode_c_20__n N_51_0 N_323 N_3_i N_209 a_decode_c_21__n N_49_0 \ +# N_218 N_8_i N_224 a_decode_c_22__n N_45_0 N_226 sm_amiga_nss_i_0_1_0__n N_331 \ +# a_decode_c_23__n sm_amiga_nss_i_0_2_0__n N_229 sm_amiga_nss_i_0_3_0__n N_230 \ +# a_c_0__n sm_amiga_nss_i_0_4_0__n N_231 sm_amiga_nss_i_0_5_0__n N_232 a_c_1__n \ +# pos_clk_un10_sm_amiga_i_1_n N_233 un10_ciin_1 N_234 nEXP_SPACE_c un10_ciin_2 N_235 \ +# un10_ciin_3 N_236 BERR_c un10_ciin_4 N_238 un10_ciin_5 N_239 BG_030_c un10_ciin_6 N_240 \ +# un10_ciin_7 N_251 BG_000DFFreg un10_ciin_8 N_262 un10_ciin_9 N_341 un10_ciin_10 N_268 \ +# BGACK_000_c un10_ciin_11 N_269 pos_clk_un23_bgack_030_int_i_0_0_1_n N_282 CLK_030_c \ +# pos_clk_un23_bgack_030_int_i_0_0_2_n N_346 N_60_i_1 N_290 N_60_i_2 N_310 N_248_1 \ +# N_311 CLK_OSZI_c N_248_2 N_355 N_249_1 N_356 N_249_2 N_359 CLK_OUT_INTreg N_361_1 N_360 \ +# N_361_2 N_365 N_157_1 N_366 FPU_SENSE_c N_157_2 \ +# pos_clk_un23_bgack_030_int_i_0_o2_2_x2 N_157_3 pos_clk_CYCLE_DMA_5_1_i_0_x2 \ +# IPL_030DFF_0_reg N_157_4 N_248 N_260_1 N_249 IPL_030DFF_1_reg N_260_2 N_369 \ +# un21_fpu_cs_1 N_196 IPL_030DFF_2_reg un22_berr_1_0 N_186 N_275_i_1 N_361 ipl_c_0__n \ +# N_275_i_2 N_362 N_274_i_1 N_151 ipl_c_1__n N_274_i_2 N_321 N_115_1 N_266 ipl_c_2__n \ +# N_115_2 N_267 N_332_1 N_255 N_246_1 N_256 DTACK_c N_246_2 N_253 N_246_3 N_254 N_246_4 \ +# cpu_est_2_2__n N_332_4_1 cpu_est_2_1__n VPA_c N_332_4_2 N_250 N_273_0_1 \ +# pos_clk_un9_clk_000_pe_n N_276_i_1 N_364 RST_c N_277_i_1 N_21 N_314_i_1 N_171 N_356_1 \ +# pos_clk_size_dma_6_1__n RW_c N_282_1 N_345 N_251_1 pos_clk_size_dma_6_0__n fc_c_0__n \ +# pos_clk_un6_bg_030_1_n N_283 N_240_1 pos_clk_un6_bgack_000_n fc_c_1__n N_238_1 N_370 \ +# N_233_1 N_259 N_231_1 N_10 AMIGA_BUS_DATA_DIR_c N_224_1 pos_clk_un9_bg_030_n N_218_1 \ +# N_4 pos_clk_ipl_1_n N_114 rw_000_dma_0_un3_n N_278 rw_000_dma_0_un1_n N_5 N_25_i \ +# rw_000_dma_0_un0_n N_113 N_34_0 lds_000_int_0_un3_n N_279 N_24_i lds_000_int_0_un1_n \ +# N_6 N_35_0 lds_000_int_0_un0_n N_115 N_23_i ipl_030_0_1__un3_n N_63 N_36_0 \ +# ipl_030_0_1__un1_n N_7 N_19_i ipl_030_0_1__un0_n pos_clk_un3_as_030_d0_n N_40_0 \ +# amiga_bus_enable_dma_high_0_un3_n N_67 N_17_i amiga_bus_enable_dma_high_0_un1_n \ +# N_18 N_42_0 amiga_bus_enable_dma_high_0_un0_n pos_clk_rw_000_int_5_n ipl_c_i_1__n \ +# amiga_bus_enable_dma_low_0_un3_n un1_SM_AMIGA_0_sqmuxa_1 N_52_0 \ +# amiga_bus_enable_dma_low_0_un1_n N_22 ipl_c_i_2__n \ +# amiga_bus_enable_dma_low_0_un0_n pos_clk_a0_dma_3_n N_53_0 uds_000_int_0_un3_n \ +# N_363 N_28_i uds_000_int_0_un1_n N_26 N_31_0 uds_000_int_0_un0_n N_157 N_29_i \ +# ipl_030_0_2__un3_n N_260 N_32_0 ipl_030_0_2__un1_n un22_berr_1 a_c_i_0__n \ +# ipl_030_0_2__un0_n N_219 size_c_i_1__n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_139 pos_clk_un10_sm_amiga_i_n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_220 N_332_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_222 N_240_i as_000_int_0_un3_n N_223 \ +# N_315_0 as_000_int_0_un1_n N_368 N_281_0 as_000_int_0_un0_n N_257 N_270_i \ +# ds_000_enable_0_un3_n N_258 N_282_i ds_000_enable_0_un1_n N_312 \ +# AMIGA_BUS_DATA_DIR_c_0 ds_000_enable_0_un0_n N_143 RW_c_i as_030_000_sync_0_un3_n \ +# N_332 N_140_0 as_030_000_sync_0_un1_n N_332_4 N_353_i as_030_000_sync_0_un0_n N_246 \ +# N_143_0 rw_000_int_0_un3_n N_180 sm_amiga_i_1__n rw_000_int_0_un1_n N_320 N_320_i \ +# rw_000_int_0_un0_n N_244 N_357_i a0_dma_0_un3_n N_334 N_356_i a0_dma_0_un1_n N_335 \ +# N_156_0 a0_dma_0_un0_n N_159 sm_amiga_i_4__n bg_000_0_un3_n N_156 N_159_i \ +# bg_000_0_un1_n N_357 sm_amiga_i_2__n bg_000_0_un0_n N_353 N_180_i \ +# size_dma_0_1__un3_n N_140 N_334_i size_dma_0_1__un1_n N_270 N_335_i \ +# size_dma_0_1__un0_n N_281 N_244_i size_dma_0_0__un3_n N_131 N_233_i \ +# size_dma_0_0__un1_n N_132 N_355_i size_dma_0_0__un0_n N_29 N_229_i \ +# bgack_030_int_0_un3_n .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -135,186 +128,175 @@ A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ -AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_166.BLIF N_32_0.BLIF \ -cpu_est_0_3__un0_n.BLIF N_141.BLIF a_c_i_0__n.BLIF cpu_est_0_2__un3_n.BLIF \ -N_226.BLIF size_c_i_1__n.BLIF cpu_est_0_2__un1_n.BLIF N_357.BLIF \ -pos_clk_un10_sm_amiga_i_n.BLIF cpu_est_0_2__un0_n.BLIF N_219.BLIF N_258_0.BLIF \ -sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_217.BLIF N_357_i.BLIF \ -sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_221.BLIF N_254_i.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_220.BLIF cpu_est_2_0_2__n.BLIF \ -vma_int_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF N_223.BLIF N_315_i.BLIF \ -vma_int_0_un1_n.BLIF vcc_n_n.BLIF N_343.BLIF N_291_0.BLIF vma_int_0_un0_n.BLIF \ -inst_VMA_INTreg.BLIF N_192.BLIF AS_030_000_SYNC_i.BLIF cpu_est_0_1__un3_n.BLIF \ -gnd_n_n.BLIF N_164.BLIF N_146_0.BLIF cpu_est_0_1__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_0__n.BLIF N_291.BLIF N_149_i.BLIF \ -cpu_est_0_1__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_315.BLIF N_164_i.BLIF \ -sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF un6_as_030.BLIF cpu_est_2_2__n.BLIF \ -N_166_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF un3_size.BLIF N_254.BLIF \ -N_172_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF un4_size.BLIF N_258.BLIF \ -N_176_i.BLIF rw_000_int_0_un3_n.BLIF un4_uds_000.BLIF N_29.BLIF N_186_0.BLIF \ -rw_000_int_0_un1_n.BLIF un4_lds_000.BLIF N_28.BLIF N_192_0.BLIF \ -rw_000_int_0_un0_n.BLIF un4_as_000.BLIF N_27.BLIF N_228_i.BLIF \ -bgack_030_int_0_un3_n.BLIF un10_ciin.BLIF N_4.BLIF N_227_i.BLIF \ -bgack_030_int_0_un1_n.BLIF un21_fpu_cs.BLIF N_17.BLIF N_343_i.BLIF \ -bgack_030_int_0_un0_n.BLIF un22_berr.BLIF N_21.BLIF as_000_int_0_un3_n.BLIF \ -un6_ds_030.BLIF N_26.BLIF N_223_i.BLIF as_000_int_0_un1_n.BLIF cpu_est_2_.BLIF \ -pos_clk_un9_bg_030_n.BLIF N_225_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_3_.BLIF \ -un1_amiga_bus_enable_low_i.BLIF N_224_i.BLIF ds_000_enable_0_un3_n.BLIF \ -cpu_est_0_.BLIF un21_fpu_cs_i.BLIF N_226_i.BLIF ds_000_enable_0_un1_n.BLIF \ -cpu_est_1_.BLIF N_275_i.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_000_INT.BLIF \ -clk_000_n_sync_i_12__n.BLIF N_220_i.BLIF as_030_000_sync_0_un3_n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF N_221_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF inst_AS_030_D0.BLIF rst_dly_i_1__n.BLIF \ -N_222_i.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ -BERR_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ -inst_BGACK_030_INT_D.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_AS_000_DMA.BLIF \ -nEXP_SPACE_i.BLIF N_215_i.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF inst_DS_000_DMA.BLIF \ -rst_dly_i_0__n.BLIF N_219_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ -CYCLE_DMA_0_.BLIF cpu_est_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ -CYCLE_DMA_1_.BLIF cpu_est_i_0__n.BLIF N_200_i.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF SIZE_DMA_0_.BLIF VPA_D_i.BLIF \ -N_195_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SIZE_DMA_1_.BLIF \ -sm_amiga_i_3__n.BLIF N_190_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ -inst_VPA_D.BLIF sm_amiga_i_0__n.BLIF N_157_i.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF inst_UDS_000_INT.BLIF \ -cpu_est_i_3__n.BLIF N_154_i.BLIF size_dma_0_0__un3_n.BLIF \ -inst_LDS_000_INT.BLIF sm_amiga_i_1__n.BLIF N_340_i.BLIF \ -size_dma_0_0__un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF RESET_OUT_i.BLIF N_141_0.BLIF \ -size_dma_0_0__un0_n.BLIF CLK_000_D_10_.BLIF BGACK_030_INT_i.BLIF \ -un3_as_030_i.BLIF size_dma_0_1__un3_n.BLIF CLK_000_D_11_.BLIF \ -sm_amiga_i_2__n.BLIF N_216_i.BLIF size_dma_0_1__un1_n.BLIF inst_DTACK_D0.BLIF \ -sm_amiga_i_4__n.BLIF N_337_i.BLIF size_dma_0_1__un0_n.BLIF inst_RESET_OUT.BLIF \ -clk_000_p_sync_i_10__n.BLIF ds_000_dma_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF \ -sm_amiga_i_5__n.BLIF un10_ciin_i.BLIF ds_000_dma_0_un1_n.BLIF \ -CLK_000_D_1_.BLIF sm_amiga_i_i_7__n.BLIF N_296_0.BLIF ds_000_dma_0_un0_n.BLIF \ -CLK_000_D_0_.BLIF clk_000_d_i_11__n.BLIF un1_as_000_i.BLIF \ -as_000_dma_0_un3_n.BLIF CLK_000_P_SYNC_10_.BLIF sm_amiga_i_6__n.BLIF \ -N_284_i.BLIF as_000_dma_0_un1_n.BLIF SM_AMIGA_5_.BLIF RW_i.BLIF N_285_i.BLIF \ -as_000_dma_0_un0_n.BLIF IPL_D0_0_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF \ -N_292_0.BLIF rw_000_dma_0_un3_n.BLIF IPL_D0_1_.BLIF LDS_000_INT_i.BLIF \ -N_280_i.BLIF rw_000_dma_0_un1_n.BLIF IPL_D0_2_.BLIF UDS_000_INT_i.BLIF \ -N_277_i.BLIF rw_000_dma_0_un0_n.BLIF CLK_000_D_2_.BLIF AS_030_i.BLIF \ -N_257_0.BLIF a0_dma_0_un3_n.BLIF CLK_000_D_3_.BLIF AS_000_INT_i.BLIF \ -N_235_i.BLIF a0_dma_0_un1_n.BLIF CLK_000_D_4_.BLIF a_decode_i_19__n.BLIF \ -N_236_i.BLIF a0_dma_0_un0_n.BLIF CLK_000_D_5_.BLIF a_decode_i_18__n.BLIF \ -cpu_est_2_0_1__n.BLIF a_decode_15__n.BLIF CLK_000_D_6_.BLIF \ -a_decode_i_16__n.BLIF N_231_i.BLIF CLK_000_D_7_.BLIF AS_000_i.BLIF \ -N_230_i.BLIF a_decode_14__n.BLIF CLK_000_D_8_.BLIF FPU_SENSE_i.BLIF \ -pos_clk_un4_clk_000_pe_0_n.BLIF CLK_000_D_9_.BLIF \ -AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_22_i.BLIF a_decode_13__n.BLIF \ -CLK_000_D_12_.BLIF CLK_030_i.BLIF N_37_0.BLIF pos_clk_un6_bg_030_n.BLIF \ -DTACK_D0_i.BLIF a_decode_12__n.BLIF SM_AMIGA_0_.BLIF clk_000_d_i_10__n.BLIF \ -N_334_i.BLIF inst_DSACK1_INTreg.BLIF RW_000_i.BLIF N_335_i.BLIF \ -a_decode_11__n.BLIF a_i_1__n.BLIF N_194_0.BLIF CLK_030_H_i.BLIF N_191_0.BLIF \ -a_decode_10__n.BLIF pos_clk_ipl_n.BLIF AS_000_DMA_i.BLIF un1_SM_AMIGA_5_i.BLIF \ -CLK_000_N_SYNC_0_.BLIF clk_000_d_i_0__n.BLIF N_346_i.BLIF a_decode_9__n.BLIF \ -SM_AMIGA_4_.BLIF clk_000_d_i_1__n.BLIF N_163_i.BLIF inst_DS_000_ENABLE.BLIF \ -AS_030_D0_i.BLIF N_345_i.BLIF a_decode_8__n.BLIF CLK_000_N_SYNC_12_.BLIF \ -size_dma_i_0__n.BLIF N_344_i.BLIF RST_DLY_0_.BLIF size_dma_i_1__n.BLIF \ -N_153_0.BLIF a_decode_7__n.BLIF RST_DLY_1_.BLIF ahigh_i_30__n.BLIF \ -pos_clk_un3_as_030_d0_i_n.BLIF RST_DLY_2_.BLIF ahigh_i_31__n.BLIF N_293_0.BLIF \ -a_decode_6__n.BLIF CLK_000_P_SYNC_0_.BLIF ahigh_i_28__n.BLIF N_233_i.BLIF \ -CLK_000_P_SYNC_1_.BLIF ahigh_i_29__n.BLIF N_232_i.BLIF a_decode_5__n.BLIF \ -CLK_000_P_SYNC_2_.BLIF ahigh_i_26__n.BLIF N_290_0.BLIF CLK_000_P_SYNC_3_.BLIF \ -ahigh_i_27__n.BLIF VPA_c_i.BLIF a_decode_4__n.BLIF CLK_000_P_SYNC_4_.BLIF \ -ahigh_i_24__n.BLIF N_54_0.BLIF CLK_000_P_SYNC_5_.BLIF ahigh_i_25__n.BLIF \ -N_5_i.BLIF a_decode_3__n.BLIF CLK_000_P_SYNC_6_.BLIF N_212_i.BLIF N_47_0.BLIF \ -CLK_000_P_SYNC_7_.BLIF N_213_i.BLIF N_7_i.BLIF a_decode_2__n.BLIF \ -CLK_000_P_SYNC_8_.BLIF N_214_i.BLIF N_46_0.BLIF CLK_000_P_SYNC_9_.BLIF \ -N_18_i.BLIF CLK_000_N_SYNC_1_.BLIF N_41_0.BLIF CLK_000_N_SYNC_2_.BLIF \ -N_321_i.BLIF N_10_i.BLIF CLK_000_N_SYNC_3_.BLIF N_322_i.BLIF N_43_0.BLIF \ -CLK_000_N_SYNC_4_.BLIF un6_ds_030_i.BLIF DTACK_c_i.BLIF CLK_000_N_SYNC_5_.BLIF \ -DS_000_DMA_i.BLIF N_55_0.BLIF CLK_000_N_SYNC_6_.BLIF un4_as_000_i.BLIF \ -pos_clk_un6_bgack_000_0_n.BLIF CLK_000_N_SYNC_7_.BLIF un6_as_030_i.BLIF \ -N_137_i.BLIF CLK_000_N_SYNC_8_.BLIF un4_lds_000_i.BLIF N_184_0.BLIF \ -CLK_000_N_SYNC_9_.BLIF un4_uds_000_i.BLIF N_349_i.BLIF CLK_000_N_SYNC_10_.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_185_i.BLIF CLK_000_N_SYNC_11_.BLIF \ -AS_030_c.BLIF N_187_0.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_203_i.BLIF \ -inst_RW_000_INT.BLIF AS_000_c.BLIF N_324_i.BLIF inst_RW_000_DMA.BLIF \ -inst_CLK_000_NE_D0.BLIF RW_000_c.BLIF N_199_0.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_197_0.BLIF inst_A0_DMA.BLIF N_196_0.BLIF \ -pos_clk_a0_dma_3_n.BLIF UDS_000_c.BLIF LDS_000_c_i.BLIF SM_AMIGA_6_.BLIF \ -UDS_000_c_i.BLIF inst_CLK_030_H.BLIF LDS_000_c.BLIF N_181_i.BLIF \ -SM_AMIGA_1_.BLIF N_347_i.BLIF SM_AMIGA_3_.BLIF size_c_0__n.BLIF N_348_i.BLIF \ -SM_AMIGA_2_.BLIF N_178_i.BLIF pos_clk_ds_000_dma_4_n.BLIF size_c_1__n.BLIF \ -VMA_INT_i.BLIF N_3.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_8.BLIF \ -ahigh_c_24__n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ -CLK_OUT_PRE_D_i.BLIF ahigh_c_25__n.BLIF N_148_0.BLIF N_341_i.BLIF \ -ahigh_c_26__n.BLIF N_338_i.BLIF N_339_i.BLIF N_19.BLIF ahigh_c_27__n.BLIF \ -N_20.BLIF N_336_i.BLIF N_24.BLIF ahigh_c_28__n.BLIF N_122_0.BLIF N_25.BLIF \ -N_211_i.BLIF ahigh_c_29__n.BLIF N_332_i.BLIF ahigh_c_30__n.BLIF N_331_i.BLIF \ -N_120_0.BLIF ahigh_c_31__n.BLIF N_330_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ -N_329_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_328_i.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF N_325_i.BLIF N_327_i.BLIF \ -AMIGA_BUS_DATA_DIR_c_0.BLIF N_320_i.BLIF N_298_0.BLIF N_295_0.BLIF \ -N_294_0.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ -N_206_i.BLIF N_283_i.BLIF SM_AMIGA_i_7_.BLIF N_122.BLIF N_281_i.BLIF \ -pos_clk_size_dma_6_0__n.BLIF N_282_i.BLIF pos_clk_size_dma_6_1__n.BLIF \ -G_134.BLIF N_3_i.BLIF G_135.BLIF N_49_0.BLIF G_136.BLIF N_8_i.BLIF N_45_0.BLIF \ -pos_clk_un23_bgack_030_int_i_1_n.BLIF N_19_i.BLIF N_292.BLIF N_40_0.BLIF \ -N_294.BLIF a_decode_c_16__n.BLIF N_20_i.BLIF N_295.BLIF N_39_0.BLIF N_296.BLIF \ -a_decode_c_17__n.BLIF N_24_i.BLIF N_298.BLIF N_35_0.BLIF N_120.BLIF \ -a_decode_c_18__n.BLIF N_25_i.BLIF N_148.BLIF N_34_0.BLIF N_149.BLIF \ -a_decode_c_19__n.BLIF N_194_0_1.BLIF N_157.BLIF N_237_i_1.BLIF N_172.BLIF \ -a_decode_c_20__n.BLIF N_237_i_2.BLIF N_176.BLIF N_238_i_1.BLIF N_178.BLIF \ -a_decode_c_21__n.BLIF N_238_i_2.BLIF N_181.BLIF N_144_i_1.BLIF N_184.BLIF \ -a_decode_c_22__n.BLIF N_144_i_2.BLIF N_144_i_3.BLIF N_196.BLIF \ -a_decode_c_23__n.BLIF N_136_i_1.BLIF N_197.BLIF N_136_i_2.BLIF N_206.BLIF \ -a_c_0__n.BLIF N_176_i_1.BLIF N_207.BLIF N_146_0_1.BLIF N_211.BLIF \ -a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_215.BLIF un10_ciin_1.BLIF \ -N_222.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_224.BLIF un10_ciin_3.BLIF \ -N_225.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_227.BLIF un10_ciin_5.BLIF N_228.BLIF \ -BG_030_c.BLIF un10_ciin_6.BLIF N_236.BLIF un10_ciin_7.BLIF N_277.BLIF \ -BG_000DFFreg.BLIF un10_ciin_8.BLIF N_281.BLIF un10_ciin_9.BLIF N_282.BLIF \ -un10_ciin_10.BLIF N_283.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_285.BLIF \ -N_347_1.BLIF N_318.BLIF CLK_030_c.BLIF N_347_2.BLIF N_319.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF N_320.BLIF CLK_000_c.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF N_321.BLIF un21_fpu_cs_1.BLIF \ -N_322.BLIF CLK_OSZI_c.BLIF un22_berr_1_0.BLIF N_323.BLIF N_366_1.BLIF \ -N_325.BLIF N_366_2.BLIF N_327.BLIF CLK_OUT_INTreg.BLIF N_366_3.BLIF N_328.BLIF \ -N_366_4.BLIF N_329.BLIF un1_SM_AMIGA_5_i_1.BLIF N_330.BLIF FPU_SENSE_c.BLIF \ -un1_SM_AMIGA_5_i_2.BLIF N_331.BLIF N_142_i_1.BLIF N_332.BLIF \ -IPL_030DFF_0_reg.BLIF N_142_i_2.BLIF N_336.BLIF N_339_1.BLIF N_338.BLIF \ -IPL_030DFF_1_reg.BLIF N_280_1.BLIF N_339.BLIF N_280_2.BLIF N_341.BLIF \ -IPL_030DFF_2_reg.BLIF N_231_1.BLIF N_344.BLIF N_231_2.BLIF N_347.BLIF \ -ipl_c_0__n.BLIF N_230_1.BLIF N_348.BLIF N_230_2.BLIF \ -pos_clk_un23_bgack_030_int_i_0_x2.BLIF ipl_c_1__n.BLIF N_230_3.BLIF \ -cpu_est_0_0_x2_0_x2_0_.BLIF N_226_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ -ipl_c_2__n.BLIF N_226_2.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_226_3.BLIF \ -N_199.BLIF N_239_i_1.BLIF N_324.BLIF DTACK_c.BLIF N_122_0_1.BLIF \ -un22_berr_1.BLIF N_132_i_1.BLIF N_366.BLIF N_120_0_1.BLIF N_335.BLIF \ -N_106_i_1.BLIF N_208.BLIF VPA_c.BLIF N_103_i_1.BLIF N_203.BLIF N_92_i_1.BLIF \ -N_187.BLIF N_140_i_1.BLIF N_137.BLIF RST_c.BLIF N_138_i_1.BLIF N_349.BLIF \ -N_344_1.BLIF pos_clk_un6_bgack_000_n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ -N_10.BLIF RW_c.BLIF N_327_1.BLIF N_5.BLIF N_319_1.BLIF N_293.BLIF \ -fc_c_0__n.BLIF N_285_1.BLIF N_6.BLIF N_277_1.BLIF un1_SM_AMIGA_5.BLIF \ -fc_c_1__n.BLIF N_236_1.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_228_1.BLIF \ -N_7.BLIF N_225_1.BLIF pos_clk_un3_as_030_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -N_224_1.BLIF N_290.BLIF N_222_1.BLIF N_18.BLIF N_215_1.BLIF \ -DS_000_ENABLE_1_sqmuxa.BLIF pos_clk_ipl_1_n.BLIF N_232.BLIF \ -bg_000_0_un3_n.BLIF N_194.BLIF BG_030_c_i.BLIF bg_000_0_un1_n.BLIF N_233.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF bg_000_0_un0_n.BLIF N_275.BLIF \ -pos_clk_un9_bg_030_0_n.BLIF uds_000_int_0_un3_n.BLIF N_153.BLIF N_26_i.BLIF \ -uds_000_int_0_un1_n.BLIF N_191.BLIF N_33_0.BLIF uds_000_int_0_un0_n.BLIF \ -N_334.BLIF N_21_i.BLIF lds_000_int_0_un3_n.BLIF N_146.BLIF N_38_0.BLIF \ -lds_000_int_0_un1_n.BLIF N_345.BLIF N_17_i.BLIF lds_000_int_0_un0_n.BLIF \ -N_346.BLIF N_42_0.BLIF dsack1_int_0_un3_n.BLIF N_163.BLIF N_4_i.BLIF \ -dsack1_int_0_un1_n.BLIF N_22.BLIF N_48_0.BLIF dsack1_int_0_un0_n.BLIF \ -pos_clk_un4_clk_000_pe_n.BLIF ipl_c_i_0__n.BLIF ipl_030_0_2__un3_n.BLIF \ -cpu_est_2_1__n.BLIF N_51_0.BLIF ipl_030_0_2__un1_n.BLIF N_235.BLIF \ -ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_284.BLIF N_52_0.BLIF \ -ipl_030_0_1__un3_n.BLIF N_190.BLIF ipl_c_i_2__n.BLIF ipl_030_0_1__un1_n.BLIF \ -N_337.BLIF N_53_0.BLIF ipl_030_0_1__un0_n.BLIF N_195.BLIF N_27_i.BLIF \ -ipl_030_0_0__un3_n.BLIF N_340.BLIF N_30_0.BLIF ipl_030_0_0__un1_n.BLIF \ -N_231.BLIF N_28_i.BLIF ipl_030_0_0__un0_n.BLIF N_230.BLIF N_31_0.BLIF \ -cpu_est_0_3__un3_n.BLIF N_280.BLIF N_29_i.BLIF cpu_est_0_3__un1_n.BLIF \ -AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ -AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ -AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ -BERR.PIN.BLIF RW.PIN.BLIF +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_28.BLIF N_246_i.BLIF \ +bgack_030_int_0_un1_n.BLIF N_17.BLIF sm_amiga_nss_i_0_0__n.BLIF \ +bgack_030_int_0_un0_n.BLIF N_19.BLIF dsack1_int_0_un3_n.BLIF N_23.BLIF \ +N_220_i.BLIF dsack1_int_0_un1_n.BLIF N_24.BLIF N_219_i.BLIF \ +dsack1_int_0_un0_n.BLIF N_25.BLIF N_218_i.BLIF cpu_est_0_3__un3_n.BLIF \ +un1_amiga_bus_enable_low_i.BLIF cpu_est_0_3__un1_n.BLIF un21_fpu_cs_i.BLIF \ +N_224_i.BLIF cpu_est_0_3__un0_n.BLIF inst_BGACK_030_INTreg.BLIF \ +BGACK_030_INT_i.BLIF N_222_i.BLIF cpu_est_0_2__un3_n.BLIF vcc_n_n.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_223_i.BLIF cpu_est_0_2__un1_n.BLIF \ +inst_VMA_INTreg.BLIF UDS_000_INT_i.BLIF N_322_i.BLIF cpu_est_0_2__un0_n.BLIF \ +gnd_n_n.BLIF LDS_000_INT_i.BLIF N_312_i.BLIF cpu_est_0_1__un3_n.BLIF \ +un1_amiga_bus_enable_low.BLIF N_131_i.BLIF N_139_0.BLIF \ +cpu_est_0_1__un1_n.BLIF un6_as_030.BLIF N_132_i.BLIF N_108_i.BLIF \ +cpu_est_0_1__un0_n.BLIF un3_size.BLIF RW_000_i.BLIF N_258_i.BLIF \ +vma_int_0_un3_n.BLIF un4_size.BLIF a_i_1__n.BLIF N_257_i.BLIF \ +vma_int_0_un1_n.BLIF un4_uds_000.BLIF clk_000_d_i_11__n.BLIF \ +vma_int_0_un0_n.BLIF un4_lds_000.BLIF sm_amiga_i_6__n.BLIF N_245_i.BLIF \ +ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF clk_000_d_i_1__n.BLIF \ +nEXP_SPACE_c_i.BLIF ipl_030_0_0__un1_n.BLIF un10_ciin.BLIF \ +AS_030_000_SYNC_i.BLIF un1_as_030_i.BLIF ipl_030_0_0__un0_n.BLIF \ +un21_fpu_cs.BLIF sm_amiga_i_0__n.BLIF pos_clk_un3_as_030_d0_0_n.BLIF \ +ds_000_dma_0_un3_n.BLIF un22_berr.BLIF sm_amiga_i_3__n.BLIF N_107_0.BLIF \ +ds_000_dma_0_un1_n.BLIF un6_ds_030.BLIF sm_amiga_i_i_7__n.BLIF N_115_i.BLIF \ +ds_000_dma_0_un0_n.BLIF cpu_est_3_.BLIF sm_amiga_i_5__n.BLIF N_63_0.BLIF \ +as_000_dma_0_un3_n.BLIF cpu_est_0_.BLIF rst_dly_i_0__n.BLIF N_278_0.BLIF \ +as_000_dma_0_un1_n.BLIF cpu_est_1_.BLIF rst_dly_i_1__n.BLIF N_279_0.BLIF \ +as_000_dma_0_un0_n.BLIF cpu_est_2_.BLIF N_364_i_0.BLIF N_260_i.BLIF \ +a_decode_15__n.BLIF inst_AS_000_INT.BLIF cpu_est_i_0__n.BLIF N_67_0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF \ +pos_clk_rw_000_int_5_0_n.BLIF a_decode_14__n.BLIF inst_AS_030_D0.BLIF \ +AS_030_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF inst_AS_030_000_SYNC.BLIF \ +FPU_SENSE_i.BLIF un10_ciin_i.BLIF a_decode_13__n.BLIF \ +inst_BGACK_030_INT_D.BLIF N_157_i.BLIF N_313_0.BLIF inst_AS_000_DMA.BLIF \ +a_decode_i_16__n.BLIF N_4_i.BLIF a_decode_12__n.BLIF inst_DS_000_DMA.BLIF \ +a_decode_i_18__n.BLIF N_48_0.BLIF CYCLE_DMA_0_.BLIF a_decode_i_19__n.BLIF \ +N_5_i.BLIF a_decode_11__n.BLIF CYCLE_DMA_1_.BLIF N_113_i.BLIF N_47_0.BLIF \ +SIZE_DMA_0_.BLIF N_114_i.BLIF N_7_i.BLIF a_decode_10__n.BLIF SIZE_DMA_1_.BLIF \ +AS_000_INT_i.BLIF N_46_0.BLIF inst_VPA_D.BLIF size_dma_i_1__n.BLIF N_18_i.BLIF \ +a_decode_9__n.BLIF inst_UDS_000_INT.BLIF size_dma_i_0__n.BLIF N_41_0.BLIF \ +inst_LDS_000_INT.BLIF RESET_OUT_i.BLIF N_22_i.BLIF a_decode_8__n.BLIF \ +inst_CLK_OUT_PRE_D.BLIF cpu_est_i_1__n.BLIF N_37_0.BLIF CLK_000_D_1_.BLIF \ +cpu_est_i_2__n.BLIF N_26_i.BLIF a_decode_7__n.BLIF CLK_000_D_10_.BLIF \ +VPA_D_i.BLIF N_33_0.BLIF CLK_000_D_11_.BLIF DTACK_D0_i.BLIF BG_030_c_i.BLIF \ +a_decode_6__n.BLIF inst_DTACK_D0.BLIF cpu_est_i_3__n.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF inst_RESET_OUT.BLIF CLK_030_i.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF a_decode_5__n.BLIF CLK_000_D_0_.BLIF \ +clk_000_d_i_0__n.BLIF N_10_i.BLIF inst_CLK_OUT_PRE_50.BLIF \ +clk_000_d_i_10__n.BLIF N_43_0.BLIF a_decode_4__n.BLIF IPL_D0_0_.BLIF \ +AS_000_DMA_i.BLIF VPA_c_i.BLIF IPL_D0_1_.BLIF AS_000_i.BLIF N_54_0.BLIF \ +a_decode_3__n.BLIF IPL_D0_2_.BLIF CLK_030_H_i.BLIF un3_as_030_i.BLIF \ +CLK_000_D_2_.BLIF cycle_dma_i_0__n.BLIF N_370_i.BLIF a_decode_2__n.BLIF \ +CLK_000_D_3_.BLIF AS_030_D0_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ +CLK_000_D_4_.BLIF ahigh_i_30__n.BLIF N_283_i.BLIF CLK_000_D_5_.BLIF \ +ahigh_i_31__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF CLK_000_D_6_.BLIF \ +ahigh_i_28__n.BLIF N_345_i.BLIF CLK_000_D_7_.BLIF ahigh_i_29__n.BLIF \ +pos_clk_size_dma_6_0_1__n.BLIF CLK_000_D_8_.BLIF ahigh_i_26__n.BLIF \ +UDS_000_c_i.BLIF CLK_000_D_9_.BLIF ahigh_i_27__n.BLIF LDS_000_c_i.BLIF \ +CLK_000_D_12_.BLIF ahigh_i_24__n.BLIF N_171_i.BLIF pos_clk_un6_bg_030_n.BLIF \ +ahigh_i_25__n.BLIF N_21_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +N_241_i.BLIF N_38_0.BLIF inst_DSACK1_INTreg.BLIF N_242_i.BLIF DTACK_c_i.BLIF \ +pos_clk_ipl_n.BLIF N_243_i.BLIF N_55_0.BLIF inst_DS_000_ENABLE.BLIF \ +N_249_i.BLIF SM_AMIGA_6_.BLIF un6_ds_030_i.BLIF N_248_i.BLIF SM_AMIGA_0_.BLIF \ +DS_000_DMA_i.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF SM_AMIGA_4_.BLIF \ +un4_as_000_i.BLIF N_250_i.BLIF inst_RW_000_INT.BLIF un6_as_030_i.BLIF \ +N_251_i.BLIF inst_RW_000_DMA.BLIF un4_lds_000_i.BLIF cpu_est_2_0_1__n.BLIF \ +RST_DLY_0_.BLIF un4_uds_000_i.BLIF N_253_i.BLIF RST_DLY_1_.BLIF AS_030_c.BLIF \ +N_369_i.BLIF RST_DLY_2_.BLIF cpu_est_2_0_2__n.BLIF inst_A0_DMA.BLIF \ +AS_000_c.BLIF N_254_i.BLIF inst_CLK_030_H.BLIF N_316_i.BLIF SM_AMIGA_1_.BLIF \ +RW_000_c.BLIF N_256_i.BLIF SM_AMIGA_5_.BLIF N_255_i.BLIF SM_AMIGA_3_.BLIF \ +N_317_i.BLIF SM_AMIGA_2_.BLIF UDS_000_c.BLIF N_267_i.BLIF \ +pos_clk_ds_000_dma_4_n.BLIF N_266_i.BLIF N_3.BLIF LDS_000_c.BLIF N_57_0.BLIF \ +N_8.BLIF N_151_0.BLIF size_c_0__n.BLIF N_321_i.BLIF N_158_i.BLIF \ +size_c_1__n.BLIF VMA_INT_i.BLIF N_361_i.BLIF ahigh_c_24__n.BLIF N_362_i.BLIF \ +N_27.BLIF N_169_i.BLIF ahigh_c_25__n.BLIF N_186_0.BLIF N_195_0.BLIF \ +ahigh_c_26__n.BLIF N_196_0.BLIF ahigh_c_27__n.BLIF N_263_i.BLIF N_262_i.BLIF \ +ahigh_c_28__n.BLIF N_323_0.BLIF N_101_i.BLIF ahigh_c_29__n.BLIF N_366_i.BLIF \ +N_182_i.BLIF ahigh_c_30__n.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF \ +N_310_i.BLIF ahigh_c_31__n.BLIF N_359_i.BLIF N_144_0.BLIF CLK_OUT_PRE_D_i.BLIF \ +N_142_0.BLIF N_311_i.BLIF N_319_i.BLIF N_93_i.BLIF N_272_0.BLIF N_290_i.BLIF \ +N_273_0.BLIF N_346_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_268_i.BLIF \ +N_269_i.BLIF SM_AMIGA_i_7_.BLIF sm_amiga_nss_0_3__n.BLIF N_341_i.BLIF \ +N_238_i.BLIF N_239_i.BLIF sm_amiga_nss_0_2__n.BLIF N_263.BLIF N_235_i.BLIF \ +G_116.BLIF N_236_i.BLIF G_117.BLIF sm_amiga_nss_0_4__n.BLIF G_118.BLIF \ +N_234_i.BLIF pos_clk_un23_bgack_030_int_i_0_n.BLIF sm_amiga_nss_0_5__n.BLIF \ +N_272.BLIF N_231_i.BLIF N_273.BLIF N_232_i.BLIF sm_amiga_nss_0_6__n.BLIF \ +N_313.BLIF N_230_i.BLIF a_decode_c_16__n.BLIF sm_amiga_nss_0_7__n.BLIF \ +N_226_i.BLIF N_108.BLIF a_decode_c_17__n.BLIF N_331_i.BLIF N_319.BLIF \ +N_142.BLIF a_decode_c_18__n.BLIF un1_as_000_i.BLIF N_144.BLIF N_27_i.BLIF \ +N_322.BLIF a_decode_c_19__n.BLIF N_30_0.BLIF N_169.BLIF ipl_c_i_0__n.BLIF \ +N_195.BLIF a_decode_c_20__n.BLIF N_51_0.BLIF N_323.BLIF N_3_i.BLIF N_209.BLIF \ +a_decode_c_21__n.BLIF N_49_0.BLIF N_218.BLIF N_8_i.BLIF N_224.BLIF \ +a_decode_c_22__n.BLIF N_45_0.BLIF N_226.BLIF sm_amiga_nss_i_0_1_0__n.BLIF \ +N_331.BLIF a_decode_c_23__n.BLIF sm_amiga_nss_i_0_2_0__n.BLIF N_229.BLIF \ +sm_amiga_nss_i_0_3_0__n.BLIF N_230.BLIF a_c_0__n.BLIF \ +sm_amiga_nss_i_0_4_0__n.BLIF N_231.BLIF sm_amiga_nss_i_0_5_0__n.BLIF \ +N_232.BLIF a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_233.BLIF \ +un10_ciin_1.BLIF N_234.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_235.BLIF \ +un10_ciin_3.BLIF N_236.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_238.BLIF \ +un10_ciin_5.BLIF N_239.BLIF BG_030_c.BLIF un10_ciin_6.BLIF N_240.BLIF \ +un10_ciin_7.BLIF N_251.BLIF BG_000DFFreg.BLIF un10_ciin_8.BLIF N_262.BLIF \ +un10_ciin_9.BLIF N_341.BLIF un10_ciin_10.BLIF N_268.BLIF BGACK_000_c.BLIF \ +un10_ciin_11.BLIF N_269.BLIF pos_clk_un23_bgack_030_int_i_0_0_1_n.BLIF \ +N_282.BLIF CLK_030_c.BLIF pos_clk_un23_bgack_030_int_i_0_0_2_n.BLIF N_346.BLIF \ +N_60_i_1.BLIF N_290.BLIF N_60_i_2.BLIF N_310.BLIF N_248_1.BLIF N_311.BLIF \ +CLK_OSZI_c.BLIF N_248_2.BLIF N_355.BLIF N_249_1.BLIF N_356.BLIF N_249_2.BLIF \ +N_359.BLIF CLK_OUT_INTreg.BLIF N_361_1.BLIF N_360.BLIF N_361_2.BLIF N_365.BLIF \ +N_157_1.BLIF N_366.BLIF FPU_SENSE_c.BLIF N_157_2.BLIF \ +pos_clk_un23_bgack_030_int_i_0_o2_2_x2.BLIF N_157_3.BLIF \ +pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF IPL_030DFF_0_reg.BLIF N_157_4.BLIF \ +N_248.BLIF N_260_1.BLIF N_249.BLIF IPL_030DFF_1_reg.BLIF N_260_2.BLIF \ +N_369.BLIF un21_fpu_cs_1.BLIF N_196.BLIF IPL_030DFF_2_reg.BLIF \ +un22_berr_1_0.BLIF N_186.BLIF N_275_i_1.BLIF N_361.BLIF ipl_c_0__n.BLIF \ +N_275_i_2.BLIF N_362.BLIF N_274_i_1.BLIF N_151.BLIF ipl_c_1__n.BLIF \ +N_274_i_2.BLIF N_321.BLIF N_115_1.BLIF N_266.BLIF ipl_c_2__n.BLIF N_115_2.BLIF \ +N_267.BLIF N_332_1.BLIF N_255.BLIF N_246_1.BLIF N_256.BLIF DTACK_c.BLIF \ +N_246_2.BLIF N_253.BLIF N_246_3.BLIF N_254.BLIF N_246_4.BLIF \ +cpu_est_2_2__n.BLIF N_332_4_1.BLIF cpu_est_2_1__n.BLIF VPA_c.BLIF \ +N_332_4_2.BLIF N_250.BLIF N_273_0_1.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ +N_276_i_1.BLIF N_364.BLIF RST_c.BLIF N_277_i_1.BLIF N_21.BLIF N_314_i_1.BLIF \ +N_171.BLIF N_356_1.BLIF pos_clk_size_dma_6_1__n.BLIF RW_c.BLIF N_282_1.BLIF \ +N_345.BLIF N_251_1.BLIF pos_clk_size_dma_6_0__n.BLIF fc_c_0__n.BLIF \ +pos_clk_un6_bg_030_1_n.BLIF N_283.BLIF N_240_1.BLIF \ +pos_clk_un6_bgack_000_n.BLIF fc_c_1__n.BLIF N_238_1.BLIF N_370.BLIF \ +N_233_1.BLIF N_259.BLIF N_231_1.BLIF N_10.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +N_224_1.BLIF pos_clk_un9_bg_030_n.BLIF N_218_1.BLIF N_4.BLIF \ +pos_clk_ipl_1_n.BLIF N_114.BLIF rw_000_dma_0_un3_n.BLIF N_278.BLIF \ +rw_000_dma_0_un1_n.BLIF N_5.BLIF N_25_i.BLIF rw_000_dma_0_un0_n.BLIF \ +N_113.BLIF N_34_0.BLIF lds_000_int_0_un3_n.BLIF N_279.BLIF N_24_i.BLIF \ +lds_000_int_0_un1_n.BLIF N_6.BLIF N_35_0.BLIF lds_000_int_0_un0_n.BLIF \ +N_115.BLIF N_23_i.BLIF ipl_030_0_1__un3_n.BLIF N_63.BLIF N_36_0.BLIF \ +ipl_030_0_1__un1_n.BLIF N_7.BLIF N_19_i.BLIF ipl_030_0_1__un0_n.BLIF \ +pos_clk_un3_as_030_d0_n.BLIF N_40_0.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF N_67.BLIF N_17_i.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF N_18.BLIF N_42_0.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF pos_clk_rw_000_int_5_n.BLIF \ +ipl_c_i_1__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1.BLIF N_52_0.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ +N_22.BLIF ipl_c_i_2__n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF \ +pos_clk_a0_dma_3_n.BLIF N_53_0.BLIF uds_000_int_0_un3_n.BLIF N_363.BLIF \ +N_28_i.BLIF uds_000_int_0_un1_n.BLIF N_26.BLIF N_31_0.BLIF \ +uds_000_int_0_un0_n.BLIF N_157.BLIF N_29_i.BLIF ipl_030_0_2__un3_n.BLIF \ +N_260.BLIF N_32_0.BLIF ipl_030_0_2__un1_n.BLIF un22_berr_1.BLIF \ +a_c_i_0__n.BLIF ipl_030_0_2__un0_n.BLIF N_219.BLIF size_c_i_1__n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF N_139.BLIF \ +pos_clk_un10_sm_amiga_i_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_220.BLIF N_332_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_222.BLIF N_240_i.BLIF \ +as_000_int_0_un3_n.BLIF N_223.BLIF N_315_0.BLIF as_000_int_0_un1_n.BLIF \ +N_368.BLIF N_281_0.BLIF as_000_int_0_un0_n.BLIF N_257.BLIF N_270_i.BLIF \ +ds_000_enable_0_un3_n.BLIF N_258.BLIF N_282_i.BLIF ds_000_enable_0_un1_n.BLIF \ +N_312.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF ds_000_enable_0_un0_n.BLIF N_143.BLIF \ +RW_c_i.BLIF as_030_000_sync_0_un3_n.BLIF N_332.BLIF N_140_0.BLIF \ +as_030_000_sync_0_un1_n.BLIF N_332_4.BLIF N_353_i.BLIF \ +as_030_000_sync_0_un0_n.BLIF N_246.BLIF N_143_0.BLIF rw_000_int_0_un3_n.BLIF \ +N_180.BLIF sm_amiga_i_1__n.BLIF rw_000_int_0_un1_n.BLIF N_320.BLIF \ +N_320_i.BLIF rw_000_int_0_un0_n.BLIF N_244.BLIF N_357_i.BLIF \ +a0_dma_0_un3_n.BLIF N_334.BLIF N_356_i.BLIF a0_dma_0_un1_n.BLIF N_335.BLIF \ +N_156_0.BLIF a0_dma_0_un0_n.BLIF N_159.BLIF sm_amiga_i_4__n.BLIF \ +bg_000_0_un3_n.BLIF N_156.BLIF N_159_i.BLIF bg_000_0_un1_n.BLIF N_357.BLIF \ +sm_amiga_i_2__n.BLIF bg_000_0_un0_n.BLIF N_353.BLIF N_180_i.BLIF \ +size_dma_0_1__un3_n.BLIF N_140.BLIF N_334_i.BLIF size_dma_0_1__un1_n.BLIF \ +N_270.BLIF N_335_i.BLIF size_dma_0_1__un0_n.BLIF N_281.BLIF N_244_i.BLIF \ +size_dma_0_0__un3_n.BLIF N_131.BLIF N_233_i.BLIF size_dma_0_0__un1_n.BLIF \ +N_132.BLIF N_355_i.BLIF size_dma_0_0__un0_n.BLIF N_29.BLIF N_229_i.BLIF \ +bgack_030_int_0_un3_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ +AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ +A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ @@ -324,171 +306,150 @@ SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \ -CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \ -CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ -CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \ -CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ -CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ -SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ -CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ -CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ -CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ -CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \ -CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \ -CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ -CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ -CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \ -CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ -CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \ -CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ +IPL_D0_2_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \ CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ -CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ -CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ -RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ -inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D \ +CLK_000_D_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C \ +SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D \ +cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \ +RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ +CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ +CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C RST_DLY_0_.D RST_DLY_0_.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ -inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 \ -BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ \ -AHIGH_24_ A_0_ N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n \ -cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 \ -pos_clk_un10_sm_amiga_i_n cpu_est_0_2__un0_n N_219 N_258_0 \ -sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n \ -N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 cpu_est_2_0_2__n \ -vma_int_0_un3_n N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 N_291_0 \ -vma_int_0_un0_n N_192 AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 \ -N_146_0 cpu_est_0_1__un1_n un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i \ -cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 N_164_i \ -sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n N_166_i \ -sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ -sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ -un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ -rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ -N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ -un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ -pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n un1_amiga_bus_enable_low_i \ -N_224_i ds_000_enable_0_un3_n un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n \ -N_275_i ds_000_enable_0_un0_n clk_000_n_sync_i_12__n N_220_i \ -as_030_000_sync_0_un3_n rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ -rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n BERR_i \ -un1_amiga_bus_enable_dma_high_0_m2_0__un3_n cpu_est_i_2__n N_217_i \ -un1_amiga_bus_enable_dma_high_0_m2_0__un1_n nEXP_SPACE_i N_215_i \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n rst_dly_i_0__n N_219_i \ -amiga_bus_enable_dma_low_0_un3_n cpu_est_i_1__n \ -amiga_bus_enable_dma_low_0_un1_n cpu_est_i_0__n N_200_i \ -amiga_bus_enable_dma_low_0_un0_n VPA_D_i N_195_0 \ -amiga_bus_enable_dma_high_0_un3_n sm_amiga_i_3__n N_190_0 \ -amiga_bus_enable_dma_high_0_un1_n sm_amiga_i_0__n N_157_i \ -amiga_bus_enable_dma_high_0_un0_n cpu_est_i_3__n N_154_i size_dma_0_0__un3_n \ -sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n RESET_OUT_i N_141_0 \ -size_dma_0_0__un0_n BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n \ -sm_amiga_i_2__n N_216_i size_dma_0_1__un1_n sm_amiga_i_4__n N_337_i \ -size_dma_0_1__un0_n clk_000_p_sync_i_10__n ds_000_dma_0_un3_n sm_amiga_i_5__n \ -un10_ciin_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n \ -clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n sm_amiga_i_6__n N_284_i \ -as_000_dma_0_un1_n RW_i N_285_i as_000_dma_0_un0_n DS_000_ENABLE_1_sqmuxa_i \ -N_292_0 rw_000_dma_0_un3_n LDS_000_INT_i N_280_i rw_000_dma_0_un1_n \ -UDS_000_INT_i N_277_i rw_000_dma_0_un0_n AS_030_i N_257_0 a0_dma_0_un3_n \ -AS_000_INT_i N_235_i a0_dma_0_un1_n a_decode_i_19__n N_236_i a0_dma_0_un0_n \ -a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n a_decode_i_16__n N_231_i \ -AS_000_i N_230_i a_decode_14__n FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ -AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_030_i N_37_0 \ -pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n clk_000_d_i_10__n N_334_i \ -RW_000_i N_335_i a_decode_11__n a_i_1__n N_194_0 CLK_030_H_i N_191_0 \ -a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i clk_000_d_i_0__n \ -N_346_i a_decode_9__n clk_000_d_i_1__n N_163_i AS_030_D0_i N_345_i \ -a_decode_8__n size_dma_i_0__n N_344_i size_dma_i_1__n N_153_0 a_decode_7__n \ -ahigh_i_30__n pos_clk_un3_as_030_d0_i_n ahigh_i_31__n N_293_0 a_decode_6__n \ -ahigh_i_28__n N_233_i ahigh_i_29__n N_232_i a_decode_5__n ahigh_i_26__n \ -N_290_0 ahigh_i_27__n VPA_c_i a_decode_4__n ahigh_i_24__n N_54_0 ahigh_i_25__n \ -N_5_i a_decode_3__n N_212_i N_47_0 N_213_i N_7_i a_decode_2__n N_214_i N_46_0 \ -N_18_i N_41_0 N_321_i N_10_i N_322_i N_43_0 un6_ds_030_i DTACK_c_i \ -DS_000_DMA_i N_55_0 un4_as_000_i pos_clk_un6_bgack_000_0_n un6_as_030_i \ -N_137_i un4_lds_000_i N_184_0 un4_uds_000_i N_349_i AMIGA_BUS_ENABLE_DMA_LOW_i \ -N_185_i AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i AS_000_c \ -N_324_i RW_000_c N_199_0 N_197_0 N_196_0 pos_clk_a0_dma_3_n UDS_000_c \ -LDS_000_c_i UDS_000_c_i LDS_000_c N_181_i N_347_i size_c_0__n N_348_i N_178_i \ -pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 \ -pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n \ -pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 \ -N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ -ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i \ -N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i \ -pos_clk_size_dma_6_0_1__n N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i \ -AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i \ -un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i N_122 N_281_i \ -pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n N_3_i N_49_0 N_8_i \ -N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i N_292 N_40_0 N_294 \ -a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 \ -N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ -N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 \ -N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n \ -N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 \ -a_c_0__n N_176_i_1 N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n \ -N_215 un10_ciin_1 N_222 nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 \ -BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 BG_030_c un10_ciin_6 N_236 \ -un10_ciin_7 N_277 un10_ciin_8 N_281 un10_ciin_9 N_282 un10_ciin_10 N_283 \ -BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 CLK_030_c N_347_2 N_319 \ -pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ -pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ -un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 N_366_3 N_328 N_366_4 N_329 \ -un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ -N_142_i_2 N_336 N_339_1 N_338 N_280_1 N_339 N_280_2 N_341 N_231_1 N_344 \ -N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 ipl_c_1__n N_230_3 N_226_1 \ -ipl_c_2__n N_226_2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 \ -N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 \ -N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n \ -pos_clk_un6_bg_030_1_n N_10 RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 \ -N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 \ -N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 \ -N_18 N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 \ -BG_030_c_i bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 \ -pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n \ -N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ -lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 \ -dsack1_int_0_un3_n N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 \ -dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n \ -cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n \ -N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 \ -N_53_0 ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 \ -ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 \ -cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n AS_030.OE AS_000.OE \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ +RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_28 N_246_i bgack_030_int_0_un1_n N_17 \ +sm_amiga_nss_i_0_0__n bgack_030_int_0_un0_n N_19 dsack1_int_0_un3_n N_23 \ +N_220_i dsack1_int_0_un1_n N_24 N_219_i dsack1_int_0_un0_n N_25 N_218_i \ +cpu_est_0_3__un3_n un1_amiga_bus_enable_low_i cpu_est_0_3__un1_n un21_fpu_cs_i \ +N_224_i cpu_est_0_3__un0_n BGACK_030_INT_i N_222_i cpu_est_0_2__un3_n vcc_n_n \ +AMIGA_BUS_ENABLE_DMA_LOW_i N_223_i cpu_est_0_2__un1_n UDS_000_INT_i N_322_i \ +cpu_est_0_2__un0_n gnd_n_n LDS_000_INT_i N_312_i cpu_est_0_1__un3_n \ +un1_amiga_bus_enable_low N_131_i N_139_0 cpu_est_0_1__un1_n un6_as_030 N_132_i \ +N_108_i cpu_est_0_1__un0_n un3_size RW_000_i N_258_i vma_int_0_un3_n un4_size \ +a_i_1__n N_257_i vma_int_0_un1_n un4_uds_000 clk_000_d_i_11__n vma_int_0_un0_n \ +un4_lds_000 sm_amiga_i_6__n N_245_i ipl_030_0_0__un3_n un4_as_000 \ +clk_000_d_i_1__n nEXP_SPACE_c_i ipl_030_0_0__un1_n un10_ciin AS_030_000_SYNC_i \ +un1_as_030_i ipl_030_0_0__un0_n un21_fpu_cs sm_amiga_i_0__n \ +pos_clk_un3_as_030_d0_0_n ds_000_dma_0_un3_n un22_berr sm_amiga_i_3__n N_107_0 \ +ds_000_dma_0_un1_n un6_ds_030 sm_amiga_i_i_7__n N_115_i ds_000_dma_0_un0_n \ +sm_amiga_i_5__n N_63_0 as_000_dma_0_un3_n rst_dly_i_0__n N_278_0 \ +as_000_dma_0_un1_n rst_dly_i_1__n N_279_0 as_000_dma_0_un0_n N_364_i_0 N_260_i \ +a_decode_15__n cpu_est_i_0__n N_67_0 rst_dly_i_2__n pos_clk_rw_000_int_5_0_n \ +a_decode_14__n AS_030_i un1_SM_AMIGA_0_sqmuxa_1_0 FPU_SENSE_i un10_ciin_i \ +a_decode_13__n N_157_i N_313_0 a_decode_i_16__n N_4_i a_decode_12__n \ +a_decode_i_18__n N_48_0 a_decode_i_19__n N_5_i a_decode_11__n N_113_i N_47_0 \ +N_114_i N_7_i a_decode_10__n AS_000_INT_i N_46_0 size_dma_i_1__n N_18_i \ +a_decode_9__n size_dma_i_0__n N_41_0 RESET_OUT_i N_22_i a_decode_8__n \ +cpu_est_i_1__n N_37_0 cpu_est_i_2__n N_26_i a_decode_7__n VPA_D_i N_33_0 \ +DTACK_D0_i BG_030_c_i a_decode_6__n cpu_est_i_3__n pos_clk_un6_bg_030_i_n \ +CLK_030_i pos_clk_un9_bg_030_0_n a_decode_5__n clk_000_d_i_0__n N_10_i \ +clk_000_d_i_10__n N_43_0 a_decode_4__n AS_000_DMA_i VPA_c_i AS_000_i N_54_0 \ +a_decode_3__n CLK_030_H_i un3_as_030_i cycle_dma_i_0__n N_370_i a_decode_2__n \ +AS_030_D0_i pos_clk_un6_bgack_000_0_n ahigh_i_30__n N_283_i ahigh_i_31__n \ +pos_clk_size_dma_6_0_0__n ahigh_i_28__n N_345_i ahigh_i_29__n \ +pos_clk_size_dma_6_0_1__n ahigh_i_26__n UDS_000_c_i ahigh_i_27__n LDS_000_c_i \ +ahigh_i_24__n N_171_i pos_clk_un6_bg_030_n ahigh_i_25__n N_21_i N_241_i N_38_0 \ +N_242_i DTACK_c_i pos_clk_ipl_n N_243_i N_55_0 N_249_i un6_ds_030_i N_248_i \ +DS_000_DMA_i pos_clk_un9_clk_000_pe_0_n un4_as_000_i N_250_i un6_as_030_i \ +N_251_i un4_lds_000_i cpu_est_2_0_1__n un4_uds_000_i N_253_i AS_030_c N_369_i \ +cpu_est_2_0_2__n AS_000_c N_254_i N_316_i RW_000_c N_256_i N_255_i N_317_i \ +UDS_000_c N_267_i pos_clk_ds_000_dma_4_n N_266_i N_3 LDS_000_c N_57_0 N_8 \ +N_151_0 size_c_0__n N_321_i N_158_i size_c_1__n VMA_INT_i N_361_i \ +ahigh_c_24__n N_362_i N_27 N_169_i ahigh_c_25__n N_186_0 N_195_0 ahigh_c_26__n \ +N_196_0 ahigh_c_27__n N_263_i N_262_i ahigh_c_28__n N_323_0 N_101_i \ +ahigh_c_29__n N_366_i N_182_i ahigh_c_30__n pos_clk_un23_bgack_030_int_i_0_0_n \ +N_310_i ahigh_c_31__n N_359_i N_144_0 CLK_OUT_PRE_D_i N_142_0 N_311_i N_319_i \ +N_93_i N_272_0 N_290_i N_273_0 N_346_i pos_clk_ds_000_dma_4_0_n N_268_i \ +N_269_i sm_amiga_nss_0_3__n N_341_i N_238_i N_239_i sm_amiga_nss_0_2__n N_263 \ +N_235_i N_236_i sm_amiga_nss_0_4__n N_234_i pos_clk_un23_bgack_030_int_i_0_n \ +sm_amiga_nss_0_5__n N_272 N_231_i N_273 N_232_i sm_amiga_nss_0_6__n N_313 \ +N_230_i a_decode_c_16__n sm_amiga_nss_0_7__n N_226_i N_108 a_decode_c_17__n \ +N_331_i N_319 N_142 a_decode_c_18__n un1_as_000_i N_144 N_27_i N_322 \ +a_decode_c_19__n N_30_0 N_169 ipl_c_i_0__n N_195 a_decode_c_20__n N_51_0 N_323 \ +N_3_i N_209 a_decode_c_21__n N_49_0 N_218 N_8_i N_224 a_decode_c_22__n N_45_0 \ +N_226 sm_amiga_nss_i_0_1_0__n N_331 a_decode_c_23__n sm_amiga_nss_i_0_2_0__n \ +N_229 sm_amiga_nss_i_0_3_0__n N_230 a_c_0__n sm_amiga_nss_i_0_4_0__n N_231 \ +sm_amiga_nss_i_0_5_0__n N_232 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_233 \ +un10_ciin_1 N_234 nEXP_SPACE_c un10_ciin_2 N_235 un10_ciin_3 N_236 BERR_c \ +un10_ciin_4 N_238 un10_ciin_5 N_239 BG_030_c un10_ciin_6 N_240 un10_ciin_7 \ +N_251 un10_ciin_8 N_262 un10_ciin_9 N_341 un10_ciin_10 N_268 BGACK_000_c \ +un10_ciin_11 N_269 pos_clk_un23_bgack_030_int_i_0_0_1_n N_282 CLK_030_c \ +pos_clk_un23_bgack_030_int_i_0_0_2_n N_346 N_60_i_1 N_290 N_60_i_2 N_310 \ +N_248_1 N_311 CLK_OSZI_c N_248_2 N_355 N_249_1 N_356 N_249_2 N_359 N_361_1 \ +N_360 N_361_2 N_365 N_157_1 N_366 FPU_SENSE_c N_157_2 N_157_3 N_157_4 N_248 \ +N_260_1 N_249 N_260_2 N_369 un21_fpu_cs_1 N_196 un22_berr_1_0 N_186 N_275_i_1 \ +N_361 ipl_c_0__n N_275_i_2 N_362 N_274_i_1 N_151 ipl_c_1__n N_274_i_2 N_321 \ +N_115_1 N_266 ipl_c_2__n N_115_2 N_267 N_332_1 N_255 N_246_1 N_256 DTACK_c \ +N_246_2 N_253 N_246_3 N_254 N_246_4 cpu_est_2_2__n N_332_4_1 cpu_est_2_1__n \ +VPA_c N_332_4_2 N_250 N_273_0_1 pos_clk_un9_clk_000_pe_n N_276_i_1 N_364 RST_c \ +N_277_i_1 N_21 N_314_i_1 N_171 N_356_1 pos_clk_size_dma_6_1__n RW_c N_282_1 \ +N_345 N_251_1 pos_clk_size_dma_6_0__n fc_c_0__n pos_clk_un6_bg_030_1_n N_283 \ +N_240_1 pos_clk_un6_bgack_000_n fc_c_1__n N_238_1 N_370 N_233_1 N_259 N_231_1 \ +N_10 AMIGA_BUS_DATA_DIR_c N_224_1 pos_clk_un9_bg_030_n N_218_1 N_4 \ +pos_clk_ipl_1_n N_114 rw_000_dma_0_un3_n N_278 rw_000_dma_0_un1_n N_5 N_25_i \ +rw_000_dma_0_un0_n N_113 N_34_0 lds_000_int_0_un3_n N_279 N_24_i \ +lds_000_int_0_un1_n N_6 N_35_0 lds_000_int_0_un0_n N_115 N_23_i \ +ipl_030_0_1__un3_n N_63 N_36_0 ipl_030_0_1__un1_n N_7 N_19_i \ +ipl_030_0_1__un0_n pos_clk_un3_as_030_d0_n N_40_0 \ +amiga_bus_enable_dma_high_0_un3_n N_67 N_17_i \ +amiga_bus_enable_dma_high_0_un1_n N_18 N_42_0 \ +amiga_bus_enable_dma_high_0_un0_n pos_clk_rw_000_int_5_n ipl_c_i_1__n \ +amiga_bus_enable_dma_low_0_un3_n un1_SM_AMIGA_0_sqmuxa_1 N_52_0 \ +amiga_bus_enable_dma_low_0_un1_n N_22 ipl_c_i_2__n \ +amiga_bus_enable_dma_low_0_un0_n pos_clk_a0_dma_3_n N_53_0 uds_000_int_0_un3_n \ +N_363 N_28_i uds_000_int_0_un1_n N_26 N_31_0 uds_000_int_0_un0_n N_157 N_29_i \ +ipl_030_0_2__un3_n N_260 N_32_0 ipl_030_0_2__un1_n un22_berr_1 a_c_i_0__n \ +ipl_030_0_2__un0_n N_219 size_c_i_1__n \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n N_139 pos_clk_un10_sm_amiga_i_n \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_220 N_332_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n N_222 N_240_i as_000_int_0_un3_n \ +N_223 N_315_0 as_000_int_0_un1_n N_368 N_281_0 as_000_int_0_un0_n N_257 \ +N_270_i ds_000_enable_0_un3_n N_258 N_282_i ds_000_enable_0_un1_n N_312 \ +AMIGA_BUS_DATA_DIR_c_0 ds_000_enable_0_un0_n N_143 RW_c_i \ +as_030_000_sync_0_un3_n N_332 N_140_0 as_030_000_sync_0_un1_n N_332_4 N_353_i \ +as_030_000_sync_0_un0_n N_246 N_143_0 rw_000_int_0_un3_n N_180 sm_amiga_i_1__n \ +rw_000_int_0_un1_n N_320 N_320_i rw_000_int_0_un0_n N_244 N_357_i \ +a0_dma_0_un3_n N_334 N_356_i a0_dma_0_un1_n N_335 N_156_0 a0_dma_0_un0_n N_159 \ +sm_amiga_i_4__n bg_000_0_un3_n N_156 N_159_i bg_000_0_un1_n N_357 \ +sm_amiga_i_2__n bg_000_0_un0_n N_353 N_180_i size_dma_0_1__un3_n N_140 N_334_i \ +size_dma_0_1__un1_n N_270 N_335_i size_dma_0_1__un0_n N_281 N_244_i \ +size_dma_0_0__un3_n N_131 N_233_i size_dma_0_0__un1_n N_132 N_355_i \ +size_dma_0_0__un0_n N_29 N_229_i bgack_030_int_0_un3_n AS_030.OE AS_000.OE \ RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ -AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 \ -G_135 G_136 pos_clk_un23_bgack_030_int_i_0_x2 cpu_est_0_0_x2_0_x2_0_ \ -pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 -.names N_144_i_3.BLIF N_226_i.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_142_i_1.BLIF N_142_i_2.BLIF SM_AMIGA_6_.D -11 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 -.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_136_i_1.BLIF N_136_i_2.BLIF SM_AMIGA_3_.D -11 1 -.names N_257_0.BLIF SM_AMIGA_2_.D +AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_116 \ +G_117 G_118 pos_clk_un23_bgack_030_int_i_0_o2_2_x2 \ +pos_clk_CYCLE_DMA_5_1_i_0_x2 +.names sm_amiga_nss_i_0_0__n.BLIF SM_AMIGA_i_7_.D +0 1 +.names N_315_0.BLIF SM_AMIGA_6_.D +0 1 +.names sm_amiga_nss_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names sm_amiga_nss_0_3__n.BLIF SM_AMIGA_4_.D +0 1 +.names sm_amiga_nss_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names sm_amiga_nss_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names sm_amiga_nss_0_6__n.BLIF SM_AMIGA_1_.D +0 1 +.names sm_amiga_nss_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names N_132_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names N_185_i.BLIF N_324_i.BLIF SM_AMIGA_0_.D -11 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 @@ -507,9 +468,9 @@ pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_53_0.BLIF IPL_D0_2_.D 0 1 -.names N_92_i_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF CYCLE_DMA_0_.D +.names N_60_i_1.BLIF N_60_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_103_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D +.names N_277_i_1.BLIF N_101_i.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -517,39 +478,17 @@ pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 +.names N_257_i.BLIF N_258_i.BLIF cpu_est_0_.D +11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF CLK_000_N_SYNC_0_.D +.names N_275_i_1.BLIF N_275_i_2.BLIF RST_DLY_1_.D 11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D +.names N_274_i_1.BLIF N_274_i_2.BLIF RST_DLY_2_.D 11 1 -.names N_239_i_1.BLIF RST_c.BLIF RST_DLY_0_.D +.names N_314_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_237_i_1.BLIF N_237_i_2.BLIF RST_DLY_2_.D -11 1 -.names N_106_i_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF inst_CLK_030_H.D -11 1 -.names N_337_i.BLIF RST_c.BLIF inst_RESET_OUT.D -11 1 -.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_38_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_39_0.BLIF inst_A0_DMA.D -0 1 -.names N_40_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_41_0.BLIF inst_RW_000_INT.D -0 1 -.names N_42_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_43_0.BLIF inst_BGACK_030_INTreg.D -0 1 .names N_45_0.BLIF inst_AS_000_DMA.D 0 1 .names N_46_0.BLIF inst_AS_030_000_SYNC.D @@ -560,1156 +499,1163 @@ pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_49_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_323.BLIF inst_AS_030_D0.D +.names N_107_0.BLIF inst_AS_030_D0.D 0 1 .names N_54_0.BLIF inst_VPA_D.D 0 1 .names N_55_0.BLIF inst_DTACK_D0.D 0 1 +.names N_276_i_1.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_57_0.BLIF inst_RESET_OUT.D +0 1 +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 .names N_33_0.BLIF BG_000DFFreg.D 0 1 .names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 .names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_186_0.BLIF inst_BGACK_030_INT_D.D +.names N_36_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_37_0.BLIF inst_A0_DMA.D +0 1 +.names N_38_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_40_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_43_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_101_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_166_i.BLIF N_166 -0 1 -.names N_29_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_141_0.BLIF N_141 -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names N_226_3.BLIF sm_amiga_i_3__n.BLIF N_226 -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n -11 1 -.names N_164_i.BLIF cpu_est_i_2__n.BLIF N_357 -11 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_2__n.BLIF N_219 -11 1 -.names N_275_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_258_0 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names N_141.BLIF N_166_i.BLIF N_217 -11 1 -.names N_357.BLIF N_357_i -0 1 -.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_1__n.BLIF N_221 -11 1 -.names N_254.BLIF N_254_i -0 1 -.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_149_i.BLIF N_340.BLIF N_220 -11 1 -.names N_254_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n -11 1 -.names pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_192.BLIF N_343.BLIF N_223 -11 1 -.names N_315.BLIF N_315_i -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names vcc_n_n - 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_343 -11 1 -.names N_157.BLIF N_315_i.BLIF N_291_0 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names N_192_0.BLIF N_192 -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n -0 1 -.names gnd_n_n -.names N_164_i.BLIF N_164 -0 1 -.names N_146_0_1.BLIF nEXP_SPACE_c.BLIF N_146_0 -11 1 -.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n -11 1 -.names un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ -un1_amiga_bus_enable_dma_high_0__n -0 1 -.names N_291_0.BLIF N_291 -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_149_i -11 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ -un1_amiga_bus_enable_low -11 1 -.names N_164_i.BLIF cpu_est_2_.BLIF N_315 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_164_i -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n -0 1 -.names N_149_i.BLIF RST_DLY_2_.BLIF N_166_i -11 1 -.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names N_164.BLIF cpu_est_2_.BLIF N_254 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_172_i -11 1 -.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF \ -sm_amiga_srsts_i_0_0_m2_5__un0_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names N_258_0.BLIF N_258 -0 1 -.names N_176_i_1.BLIF sm_amiga_i_2__n.BLIF N_176_i -11 1 -.names N_122.BLIF rw_000_int_0_un3_n -0 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 -1- 1 --1 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_186_0 -11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_122.BLIF rw_000_int_0_un1_n -11 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 -11 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 1- 1 -1 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_192_0 -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 -1- 1 --1 1 -.names N_228.BLIF N_228_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_227.BLIF N_227_i +.names N_246.BLIF N_246_i 0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_343.BLIF N_343_i -0 1 +.names sm_amiga_nss_i_0_4_0__n.BLIF sm_amiga_nss_i_0_5_0__n.BLIF \ +sm_amiga_nss_i_0_0__n +11 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names un22_berr_1_0.BLIF N_366.BLIF un22_berr -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_293.BLIF as_000_int_0_un3_n -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names N_223.BLIF N_223_i -0 1 -.names sm_amiga_i_5__n.BLIF N_293.BLIF as_000_int_0_un1_n -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names N_225.BLIF N_225_i -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names N_224.BLIF N_224_i -0 1 -.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n -0 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names N_226.BLIF N_226_i -0 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ -ds_000_enable_0_un1_n -11 1 -.names N_275.BLIF N_275_i -0 1 -.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names CLK_000_N_SYNC_12_.BLIF clk_000_n_sync_i_12__n -0 1 -.names N_220.BLIF N_220_i -0 1 -.names N_290.BLIF as_030_000_sync_0_un3_n -0 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_221.BLIF N_221_i -0 1 -.names inst_AS_030_000_SYNC.BLIF N_290.BLIF as_030_000_sync_0_un1_n -11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names N_222.BLIF N_222_i -0 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names BERR_c.BLIF BERR_i -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_217.BLIF N_217_i -0 1 -.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un1_n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names N_215.BLIF N_215_i -0 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n -11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names N_219.BLIF N_219_i -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_322_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_low_0_un1_n -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_200_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names CLK_000_N_SYNC_12_.BLIF N_166_i.BLIF N_195_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_1_.BLIF N_190_0 -11 1 -.names N_321_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_high_0_un1_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_154_i.BLIF cpu_est_i_0__n.BLIF N_157_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_154_i -11 1 -.names N_294.BLIF size_dma_0_0__un3_n -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_340.BLIF N_340_i -0 1 -.names pos_clk_size_dma_6_0__n.BLIF N_294.BLIF size_dma_0_0__un1_n -11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_340_i.BLIF RST_c.BLIF N_141_0 -11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_200_i.BLIF inst_RESET_OUT.BLIF un3_as_030_i -11 1 -.names N_294.BLIF size_dma_0_1__un3_n -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_166.BLIF RST_c.BLIF N_216_i -11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_294.BLIF size_dma_0_1__un1_n -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names N_337.BLIF N_337_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names CLK_000_P_SYNC_10_.BLIF clk_000_p_sync_i_10__n -0 1 -.names N_120.BLIF ds_000_dma_0_un3_n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names pos_clk_ds_000_dma_4_n.BLIF N_120.BLIF ds_000_dma_0_un1_n -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_296_0 -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names CLK_000_D_11_.BLIF clk_000_d_i_11__n -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names N_298.BLIF as_000_dma_0_un3_n -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_284.BLIF N_284_i -0 1 -.names pos_clk_un23_bgack_030_int_i_1_n.BLIF N_298.BLIF as_000_dma_0_un1_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names N_285.BLIF N_285_i -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i -0 1 -.names N_284_i.BLIF N_285_i.BLIF N_292_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_280.BLIF N_280_i -0 1 -.names N_295.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n -11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names N_277.BLIF N_277_i -0 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_277_i.BLIF N_280_i.BLIF N_257_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n -0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_235.BLIF N_235_i -0 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -a0_dma_0_un1_n -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_236.BLIF N_236_i -0 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_235_i.BLIF N_236_i.BLIF cpu_est_2_0_1__n -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names N_231.BLIF N_231_i -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names N_230.BLIF N_230_i -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names N_230_i.BLIF N_231_i.BLIF pos_clk_un4_clk_000_pe_0_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names N_22.BLIF N_22_i -0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CLK_000_D_10_.BLIF clk_000_d_i_10__n -0 1 -.names N_334.BLIF N_334_i -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_335.BLIF N_335_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names N_194_0_1.BLIF nEXP_SPACE_c.BLIF N_194_0 -11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_5_.BLIF N_191_0 -11 1 -.names pos_clk_ipl_1_n.BLIF N_213_i.BLIF pos_clk_ipl_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names N_346.BLIF N_346_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names sm_amiga_i_6__n.BLIF SM_AMIGA_i_7_.BLIF N_163_i -11 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_345.BLIF N_345_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names N_344.BLIF N_344_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_344_i.BLIF N_345_i.BLIF N_153_0 -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n -11 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_293_0 -11 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_233.BLIF N_233_i -0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names N_232.BLIF N_232_i -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_232_i.BLIF N_233_i.BLIF N_290_0 -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_54_0 -11 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_5.BLIF N_5_i -0 1 -.names G_134.BLIF N_212_i -0 1 -.names N_5_i.BLIF RST_c.BLIF N_47_0 -11 1 -.names G_135.BLIF N_213_i -0 1 -.names N_7.BLIF N_7_i -0 1 -.names G_136.BLIF N_214_i -0 1 -.names N_7_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_18.BLIF N_18_i -0 1 -.names N_18_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names N_321.BLIF N_321_i -0 1 -.names N_10.BLIF N_10_i -0 1 -.names N_322.BLIF N_322_i -0 1 -.names N_10_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 -11 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names BGACK_000_c.BLIF N_203.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names un6_as_030.BLIF un6_as_030_i -0 1 -.names BERR_c.BLIF clk_000_p_sync_i_10__n.BLIF N_137_i -11 1 -.names un4_lds_000.BLIF un4_lds_000_i -0 1 -.names N_137.BLIF sm_amiga_i_3__n.BLIF N_184_0 -11 1 -.names un4_uds_000.BLIF un4_uds_000_i -0 1 -.names N_349.BLIF N_349_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_349_i.BLIF RST_c.BLIF N_185_i -11 1 -.names N_137_i.BLIF SM_AMIGA_4_.BLIF N_187_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names AS_000_c.BLIF CLK_000_P_SYNC_10_.BLIF N_203_i -11 1 -.names N_324.BLIF N_324_i -0 1 -.names CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF N_199_0 -11 1 -.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_197_0 -11 1 -.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF N_196_0 -11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_181_i -11 1 -.names N_347.BLIF N_347_i -0 1 -.names N_348.BLIF N_348_i -0 1 -.names N_347_i.BLIF N_348_i.BLIF N_178_i -11 1 -.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -pos_clk_un5_bgack_030_int_d_i_n -11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n -11 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_148_0 -11 1 -.names N_341.BLIF N_341_i -0 1 -.names N_338.BLIF N_338_i -0 1 -.names N_339.BLIF N_339_i -0 1 .names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +.names N_278.BLIF dsack1_int_0_un3_n +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_23 1- 1 -1 1 -.names N_336.BLIF N_336_i +.names N_220.BLIF N_220_i 0 1 +.names N_114_i.BLIF N_278.BLIF dsack1_int_0_un1_n +11 1 .names amiga_bus_enable_dma_low_0_un1_n.BLIF \ amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 1- 1 -1 1 -.names N_122_0_1.BLIF SM_AMIGA_i_7_.BLIF N_122_0 +.names N_219.BLIF N_219_i +0 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 .names amiga_bus_enable_dma_high_0_un1_n.BLIF \ amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 1- 1 -1 1 -.names N_211.BLIF N_211_i +.names N_218.BLIF N_218_i 0 1 -.names N_332.BLIF N_332_i +.names N_108.BLIF cpu_est_0_3__un3_n 0 1 -.names N_331.BLIF N_331_i +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names N_120_0_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_120_0 +.names cpu_est_3_.BLIF N_108.BLIF cpu_est_0_3__un1_n 11 1 -.names N_330.BLIF N_330_i +.names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names N_330_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ -pos_clk_ds_000_dma_4_0_n -11 1 -.names N_329.BLIF N_329_i +.names N_224.BLIF N_224_i 0 1 -.names N_329_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names N_316_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names N_328.BLIF N_328_i +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names N_328_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_325.BLIF N_325_i +.names N_222.BLIF N_222_i 0 1 -.names N_327.BLIF N_327_i +.names N_108.BLIF cpu_est_0_2__un3_n 0 1 -.names N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_320.BLIF N_320_i +.names vcc_n_n + 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i 0 1 -.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_298_0 -11 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_295_0 -11 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_294_0 -11 1 -.names N_319.BLIF N_319_i +.names N_223.BLIF N_223_i 0 1 -.names N_207.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n +.names cpu_est_2_.BLIF N_108.BLIF cpu_est_0_2__un1_n 11 1 -.names N_206.BLIF N_206_i +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_322_i +11 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names gnd_n_n +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_312.BLIF N_312_i +0 1 +.names N_108.BLIF cpu_est_0_1__un3_n +0 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low +11 1 +.names N_131.BLIF N_131_i +0 1 +.names N_312_i.BLIF RST_c.BLIF N_139_0 +11 1 +.names cpu_est_1_.BLIF N_108.BLIF cpu_est_0_1__un1_n +11 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names N_132.BLIF N_132_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_108_i +11 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_258.BLIF N_258_i +0 1 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names N_257.BLIF N_257_i +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 +11 1 +.names CLK_000_D_11_.BLIF clk_000_d_i_11__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_364_i_0.BLIF RST_c.BLIF N_245_i +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_c_i.BLIF un1_as_030_i +11 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_0_n +11 1 +.names N_273.BLIF ds_000_dma_0_un3_n +0 1 +.names un22_berr_1_0.BLIF N_157.BLIF un22_berr +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_107_0 +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_273.BLIF ds_000_dma_0_un1_n +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_115.BLIF N_115_i +0 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_115_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_63_0 +11 1 +.names N_272.BLIF as_000_dma_0_un3_n +0 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names N_114_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_278_0 +11 1 +.names pos_clk_un23_bgack_030_int_i_0_n.BLIF N_272.BLIF as_000_dma_0_un1_n +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names N_113_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_279_0 +11 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names N_364.BLIF N_364_i_0 +0 1 +.names N_260.BLIF N_260_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names N_260_i.BLIF pos_clk_un3_as_030_d0_0_n.BLIF N_67_0 +11 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_182_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_113_i.BLIF N_182_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names N_157.BLIF N_157_i +0 1 +.names nEXP_SPACE_c_i.BLIF un10_ciin_i.BLIF N_313_0 +11 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_4.BLIF N_4_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_4_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_5.BLIF N_5_i +0 1 +.names N_113.BLIF N_113_i +0 1 +.names N_5_i.BLIF RST_c.BLIF N_47_0 +11 1 +.names N_114.BLIF N_114_i +0 1 +.names N_7.BLIF N_7_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_7_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names N_18.BLIF N_18_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names N_18_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names N_22.BLIF N_22_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_22_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_26.BLIF N_26_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_26_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_10.BLIF N_10_i +0 1 +.names CLK_000_D_10_.BLIF clk_000_d_i_10__n +0 1 +.names N_10_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_54_0 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names inst_RESET_OUT.BLIF un1_as_030_i.BLIF un3_as_030_i +11 1 +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names N_370.BLIF N_370_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names BGACK_000_c.BLIF N_370_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 .names N_283.BLIF N_283_i 0 1 -.names N_122_0.BLIF N_122 +.names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names N_281.BLIF N_281_i +.names N_283_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +.names N_345.BLIF N_345_i 0 1 -.names N_282.BLIF N_282_i +.names ahigh_c_29__n.BLIF ahigh_i_29__n 0 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names N_345_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_171_i +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_21.BLIF N_21_i +0 1 +.names G_116.BLIF N_241_i +0 1 +.names N_21_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names G_117.BLIF N_242_i +0 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names pos_clk_ipl_1_n.BLIF N_242_i.BLIF pos_clk_ipl_n +11 1 +.names G_118.BLIF N_243_i +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +11 1 +.names N_249.BLIF N_249_i +0 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_248.BLIF N_248_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names N_248_i.BLIF N_249_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names N_250.BLIF N_250_i +0 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names N_251.BLIF N_251_i +0 1 +.names un4_lds_000.BLIF un4_lds_000_i +0 1 +.names N_250_i.BLIF N_251_i.BLIF cpu_est_2_0_1__n +11 1 +.names un4_uds_000.BLIF un4_uds_000_i +0 1 +.names N_253.BLIF N_253_i +0 1 +.names N_369.BLIF N_369_i +0 1 +.names N_253_i.BLIF N_369_i.BLIF cpu_est_2_0_2__n +11 1 +.names N_254.BLIF N_254_i +0 1 +.names N_253_i.BLIF N_254_i.BLIF N_316_i +11 1 +.names N_256.BLIF N_256_i +0 1 +.names N_255.BLIF N_255_i +0 1 +.names N_255_i.BLIF N_256_i.BLIF N_317_i +11 1 +.names N_267.BLIF N_267_i +0 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names N_266.BLIF N_266_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names N_266_i.BLIF N_267_i.BLIF N_57_0 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names cpu_est_3_.BLIF cpu_est_i_1__n.BLIF N_151_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_321_i +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_2__n.BLIF N_158_i +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_361.BLIF N_361_i +0 1 +.names N_362.BLIF N_362_i +0 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 +1- 1 +-1 1 +.names N_361_i.BLIF N_362_i.BLIF N_169_i +11 1 +.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_186_0 +11 1 +.names N_108_i.BLIF N_169.BLIF N_195_0 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_196_0 +11 1 +.names N_263.BLIF N_263_i +0 1 +.names N_262.BLIF N_262_i +0 1 +.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_323_0 +11 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_101_i +11 1 +.names N_366.BLIF N_366_i +0 1 +.names N_366_i.BLIF SM_AMIGA_i_7_.BLIF N_182_i +11 1 +.names pos_clk_un23_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un23_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_0_0_n +11 1 +.names N_310.BLIF N_310_i +0 1 +.names N_359.BLIF N_359_i +0 1 +.names N_310_i.BLIF N_359_i.BLIF N_144_0 +11 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_142_0 +11 1 +.names N_311.BLIF N_311_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_319_i +11 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_93_i +11 1 +.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_272_0 +11 1 +.names N_290.BLIF N_290_i +0 1 +.names N_273_0_1.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF N_273_0 +11 1 +.names N_346.BLIF N_346_i +0 1 +.names N_346_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names N_268.BLIF N_268_i +0 1 +.names N_269.BLIF N_269_i +0 1 +.names N_268_i.BLIF N_269_i.BLIF sm_amiga_nss_0_3__n +11 1 +.names N_341.BLIF N_341_i +0 1 +.names N_238.BLIF N_238_i +0 1 +.names N_239.BLIF N_239_i +0 1 +.names N_238_i.BLIF N_239_i.BLIF sm_amiga_nss_0_2__n +11 1 +.names CYCLE_DMA_0_.BLIF N_319_i.BLIF N_263 +11 1 +.names N_235.BLIF N_235_i +0 1 +.names N_236.BLIF N_236_i +0 1 +.names N_235_i.BLIF N_236_i.BLIF sm_amiga_nss_0_4__n +11 1 +.names N_234.BLIF N_234_i +0 1 +.names pos_clk_un23_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_un23_bgack_030_int_i_0_n +0 1 +.names N_233_i.BLIF N_234_i.BLIF sm_amiga_nss_0_5__n +11 1 +.names N_272_0.BLIF N_272 +0 1 +.names N_231.BLIF N_231_i +0 1 +.names N_273_0.BLIF N_273 +0 1 +.names N_232.BLIF N_232_i +0 1 +.names N_231_i.BLIF N_232_i.BLIF sm_amiga_nss_0_6__n +11 1 +.names N_313_0.BLIF N_313 +0 1 +.names N_230.BLIF N_230_i +0 1 +.names N_229_i.BLIF N_230_i.BLIF sm_amiga_nss_0_7__n +11 1 +.names N_226.BLIF N_226_i +0 1 +.names N_108_i.BLIF N_108 +0 1 +.names N_331.BLIF N_331_i +0 1 +.names N_319_i.BLIF N_319 +0 1 +.names N_142_0.BLIF N_142 +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +11 1 +.names N_144_0.BLIF N_144 +0 1 +.names N_27.BLIF N_27_i +0 1 +.names N_322_i.BLIF N_322 +0 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_169_i.BLIF N_169 +0 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names N_195_0.BLIF N_195 +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names N_323_0.BLIF N_323 0 1 .names N_3.BLIF N_3_i 0 1 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_209 +1- 1 +-1 1 .names N_3_i.BLIF RST_c.BLIF N_49_0 11 1 +.names N_218_1.BLIF rst_dly_i_2__n.BLIF N_218 +11 1 .names N_8.BLIF N_8_i 0 1 +.names N_224_1.BLIF rst_dly_i_1__n.BLIF N_224 +11 1 .names N_8_i.BLIF RST_c.BLIF N_45_0 11 1 -.names pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ -pos_clk_un23_bgack_030_int_i_1_n -0 1 -.names N_19.BLIF N_19_i -0 1 -.names N_292_0.BLIF N_292 -0 1 -.names N_19_i.BLIF RST_c.BLIF N_40_0 +.names N_139.BLIF RST_DLY_0_.BLIF N_226 11 1 -.names N_294_0.BLIF N_294 -0 1 -.names N_20.BLIF N_20_i -0 1 -.names N_295_0.BLIF N_295 -0 1 -.names N_20_i.BLIF RST_c.BLIF N_39_0 +.names N_334_i.BLIF N_335_i.BLIF sm_amiga_nss_i_0_1_0__n 11 1 -.names N_296_0.BLIF N_296 -0 1 -.names N_24.BLIF N_24_i -0 1 -.names N_298_0.BLIF N_298 -0 1 -.names N_24_i.BLIF RST_c.BLIF N_35_0 +.names N_368.BLIF rst_dly_i_0__n.BLIF N_331 11 1 -.names N_120_0.BLIF N_120 -0 1 -.names N_25.BLIF N_25_i -0 1 -.names N_148_0.BLIF N_148 -0 1 -.names N_25_i.BLIF RST_c.BLIF N_34_0 +.names N_233_i.BLIF N_244_i.BLIF sm_amiga_nss_i_0_2_0__n 11 1 -.names N_149_i.BLIF N_149 -0 1 -.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_194_0_1 +.names N_365.BLIF SM_AMIGA_0_.BLIF N_229 11 1 -.names N_157_i.BLIF N_157 -0 1 -.names N_215_i.BLIF N_217_i.BLIF N_237_i_1 +.names N_246_i.BLIF N_229_i.BLIF sm_amiga_nss_i_0_3_0__n 11 1 -.names N_172_i.BLIF N_172 -0 1 -.names N_219_i.BLIF RST_c.BLIF N_237_i_2 +.names N_360.BLIF SM_AMIGA_1_.BLIF N_230 11 1 -.names N_176_i.BLIF N_176 -0 1 -.names N_220_i.BLIF RST_c.BLIF N_238_i_1 +.names sm_amiga_nss_i_0_1_0__n.BLIF sm_amiga_nss_i_0_2_0__n.BLIF \ +sm_amiga_nss_i_0_4_0__n 11 1 -.names N_178_i.BLIF N_178 -0 1 -.names N_221_i.BLIF N_222_i.BLIF N_238_i_2 +.names N_231_1.BLIF SM_AMIGA_1_.BLIF N_231 11 1 -.names N_181_i.BLIF N_181 -0 1 -.names N_185_i.BLIF N_223_i.BLIF N_144_i_1 +.names sm_amiga_nss_i_0_3_0__n.BLIF N_355_i.BLIF sm_amiga_nss_i_0_5_0__n 11 1 -.names N_184_0.BLIF N_184 -0 1 -.names N_224_i.BLIF N_225_i.BLIF N_144_i_2 +.names N_359.BLIF SM_AMIGA_2_.BLIF N_232 11 1 -.names N_144_i_1.BLIF N_144_i_2.BLIF N_144_i_3 -11 1 -.names N_196_0.BLIF N_196 -0 1 -.names N_227_i.BLIF N_228_i.BLIF N_136_i_1 -11 1 -.names N_197_0.BLIF N_197 -0 1 -.names N_343_i.BLIF RST_c.BLIF N_136_i_2 -11 1 -.names sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF \ -sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF N_206 -1- 1 --1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_176_i_1 -11 1 -.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_207 -1- 1 --1 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_0_.BLIF N_146_0_1 -11 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_211 -1- 1 --1 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_215_1.BLIF rst_dly_i_2__n.BLIF N_215 +.names N_233_1.BLIF SM_AMIGA_3_.BLIF N_233 11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names N_222_1.BLIF rst_dly_i_1__n.BLIF N_222 +.names N_365.BLIF SM_AMIGA_2_.BLIF N_234 11 1 .names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names N_224_1.BLIF clk_000_p_sync_i_10__n.BLIF N_224 +.names N_195.BLIF N_355.BLIF N_235 11 1 .names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names N_225_1.BLIF clk_000_n_sync_i_12__n.BLIF N_225 +.names N_359.BLIF SM_AMIGA_4_.BLIF N_236 11 1 .names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 -.names N_196.BLIF sm_amiga_i_3__n.BLIF N_227 +.names N_238_1.BLIF SM_AMIGA_5_.BLIF N_238 11 1 .names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names N_228_1.BLIF sm_amiga_i_4__n.BLIF N_228 +.names N_359.BLIF SM_AMIGA_6_.BLIF N_239 11 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names N_236_1.BLIF cpu_est_i_3__n.BLIF N_236 +.names N_240_1.BLIF SM_AMIGA_i_7_.BLIF N_240 11 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names N_277_1.BLIF SM_AMIGA_2_.BLIF N_277 +.names N_251_1.BLIF cpu_est_i_3__n.BLIF N_251 11 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names N_187.BLIF sm_amiga_i_5__n.BLIF N_281 +.names cycle_dma_i_0__n.BLIF N_319.BLIF N_262 11 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 -.names clk_000_n_sync_i_12__n.BLIF sm_amiga_i_4__n.BLIF N_282 +.names CLK_030_H_i.BLIF N_323.BLIF N_341 11 1 .names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 -.names N_191.BLIF sm_amiga_i_6__n.BLIF N_283 +.names N_365.BLIF SM_AMIGA_4_.BLIF N_268 11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names N_285_1.BLIF cpu_est_i_3__n.BLIF N_285 +.names N_360.BLIF SM_AMIGA_5_.BLIF N_269 11 1 -.names N_157_i.BLIF VMA_INT_i.BLIF N_347_1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_0_0_1_n 11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_318 +.names N_282_1.BLIF un1_as_030_i.BLIF N_282 11 1 -.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_347_2 +.names pos_clk_un23_bgack_030_int_i_0_o2_2_x2.BLIF N_311_i.BLIF \ +pos_clk_un23_bgack_030_int_i_0_0_2_n 11 1 -.names N_319_1.BLIF SM_AMIGA_0_.BLIF N_319 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_346 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_1_n +.names AS_000_i.BLIF N_101_i.BLIF N_60_i_1 11 1 -.names CLK_030_H_i.BLIF N_197.BLIF N_320 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_290 11 1 -.names pos_clk_un23_bgack_030_int_i_0_x2.BLIF N_341_i.BLIF \ -pos_clk_un23_bgack_030_int_i_1_0_2_n +.names N_262_i.BLIF N_263_i.BLIF N_60_i_2 11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_321 +.names BERR_c.BLIF RST_c.BLIF N_310 11 1 -.names FPU_SENSE_i.BLIF N_366.BLIF un21_fpu_cs_1 +.names N_158_i.BLIF N_319_i.BLIF N_248_1 11 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_322 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_311 11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_248_2 +11 1 +.names N_310.BLIF SM_AMIGA_3_.BLIF N_355 +11 1 +.names N_108_i.BLIF N_369.BLIF N_249_1 +11 1 +.names N_356_1.BLIF clk_000_d_i_10__n.BLIF N_356 +11 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_249_2 +11 1 +.names N_319_i.BLIF RST_c.BLIF N_359 +11 1 +.names N_151_0.BLIF N_158_i.BLIF N_361_1 +11 1 +.names N_108_i.BLIF RST_c.BLIF N_360 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_361_2 +11 1 +.names N_310.BLIF N_319.BLIF N_365 +11 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_157_1 +11 1 +.names N_319_i.BLIF SM_AMIGA_0_.BLIF N_366 +11 1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_157_2 +11 1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_157_3 +11 1 +.names N_157_1.BLIF N_157_2.BLIF N_157_4 +11 1 +.names N_248_1.BLIF N_248_2.BLIF N_248 +11 1 +.names N_157_i.BLIF N_363.BLIF N_260_1 +11 1 +.names N_249_1.BLIF N_249_2.BLIF N_249 +11 1 +.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_260_2 +11 1 +.names N_321_i.BLIF cpu_est_i_2__n.BLIF N_369 +11 1 +.names FPU_SENSE_i.BLIF N_157.BLIF un21_fpu_cs_1 +11 1 +.names N_196_0.BLIF N_196 +0 1 .names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_323 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_366_1 -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_325 -11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_366_2 -11 1 -.names N_327_1.BLIF RW_000_c.BLIF N_327 -11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_366_3 -11 1 -.names BGACK_030_INT_i.BLIF N_181.BLIF N_328 -11 1 -.names N_366_1.BLIF N_366_2.BLIF N_366_4 -11 1 -.names BGACK_030_INT_i.BLIF N_181_i.BLIF N_329 -11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_163_i.BLIF un1_SM_AMIGA_5_i_1 -11 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 -11 1 -.names N_346_i.BLIF sm_amiga_i_0__n.BLIF un1_SM_AMIGA_5_i_2 -11 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 -11 1 -.names N_163.BLIF N_334_i.BLIF N_142_i_1 -11 1 -.names N_190.BLIF sm_amiga_i_2__n.BLIF N_332 -11 1 -.names N_335_i.BLIF RST_c.BLIF N_142_i_2 -11 1 -.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF N_336 -11 1 -.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_0__n.BLIF N_339_1 -11 1 -.names N_141.BLIF RST_DLY_0_.BLIF N_338 -11 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_280_1 -11 1 -.names N_339_1.BLIF RST_c.BLIF N_339 -11 1 -.names RST_c.BLIF SM_AMIGA_3_.BLIF N_280_2 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_341 -11 1 -.names CLK_000_N_SYNC_12_.BLIF N_357.BLIF N_231_1 -11 1 -.names N_344_1.BLIF clk_000_d_i_10__n.BLIF N_344 -11 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_231_2 -11 1 -.names N_347_1.BLIF N_347_2.BLIF N_347 -11 1 -.names CLK_000_P_SYNC_10_.BLIF cpu_est_i_0__n.BLIF N_230_1 -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_230_2 -11 1 -.names N_230_1.BLIF N_230_2.BLIF N_230_3 -11 1 -.names N_146.BLIF N_172_i.BLIF N_226_1 -11 1 -.names N_176_i.BLIF sm_amiga_i_0__n.BLIF N_226_2 -11 1 -.names N_226_1.BLIF N_226_2.BLIF N_226_3 -11 1 -.names N_199_0.BLIF N_199 +.names N_186_0.BLIF N_186 0 1 -.names N_338_i.BLIF N_339_i.BLIF N_239_i_1 +.names N_222_i.BLIF N_223_i.BLIF N_275_i_1 11 1 -.names N_199.BLIF sm_amiga_i_0__n.BLIF N_324 +.names N_361_1.BLIF N_361_2.BLIF N_361 11 1 -.names N_336_i.BLIF sm_amiga_i_5__n.BLIF N_122_0_1 +.names N_224_i.BLIF RST_c.BLIF N_275_i_2 11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_362 11 1 -.names N_211_i.BLIF N_332_i.BLIF N_132_i_1 +.names N_218_i.BLIF N_219_i.BLIF N_274_i_1 11 1 -.names N_366_4.BLIF N_366_3.BLIF N_366 -11 1 -.names N_331_i.BLIF RW_000_i.BLIF N_120_0_1 -11 1 -.names N_137.BLIF SM_AMIGA_i_7_.BLIF N_335 -11 1 -.names N_320_i.BLIF RST_c.BLIF N_106_i_1 -11 1 -.names CLK_000_P_SYNC_10_.BLIF CYCLE_DMA_0_.BLIF N_208 -11 1 -.names AS_000_i.BLIF N_186_0.BLIF N_103_i_1 -11 1 -.names N_203_i.BLIF N_203 +.names N_151_0.BLIF N_151 0 1 -.names AS_000_i.BLIF N_186_0.BLIF N_92_i_1 +.names N_220_i.BLIF RST_c.BLIF N_274_i_2 11 1 -.names N_187_0.BLIF N_187 +.names N_321_i.BLIF N_321 0 1 -.names N_206_i.BLIF N_283_i.BLIF N_140_i_1 +.names N_143.BLIF sm_amiga_i_0__n.BLIF N_115_1 11 1 -.names N_137_i.BLIF N_137 +.names inst_RESET_OUT.BLIF RST_c.BLIF N_266 +11 1 +.names sm_amiga_i_5__n.BLIF SM_AMIGA_i_7_.BLIF N_115_2 +11 1 +.names N_360.BLIF N_364.BLIF N_267 +11 1 +.names CLK_000_D_2_.BLIF N_332_4.BLIF N_332_1 +11 1 +.names N_186.BLIF cpu_est_2_.BLIF N_255 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_246_1 +11 1 +.names N_151.BLIF cpu_est_i_2__n.BLIF N_256 +11 1 +.names CLK_000_D_2_.BLIF N_180_i.BLIF N_246_2 +11 1 +.names N_321.BLIF cpu_est_2_.BLIF N_253 +11 1 +.names N_320_i.BLIF N_332_4.BLIF N_246_3 +11 1 +.names N_196.BLIF cpu_est_i_2__n.BLIF N_254 +11 1 +.names N_246_1.BLIF N_246_2.BLIF N_246_4 +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names N_281_i.BLIF N_282_i.BLIF N_138_i_1 +.names AS_030_000_SYNC_i.BLIF clk_000_d_i_1__n.BLIF N_332_4_1 11 1 -.names N_137.BLIF SM_AMIGA_0_.BLIF N_349 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names RST_c.BLIF nEXP_SPACE_c.BLIF N_332_4_2 11 1 -.names N_148.BLIF CLK_000_D_11_.BLIF N_344_1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_250 +11 1 +.names N_290_i.BLIF RW_000_i.BLIF N_273_0_1 +11 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names N_341_i.BLIF RST_c.BLIF N_276_i_1 +11 1 +.names N_322_i.BLIF RST_DLY_2_.BLIF N_364 +11 1 +.names pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF AS_000_i.BLIF N_277_i_1 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names N_226_i.BLIF N_331_i.BLIF N_314_i_1 +11 1 +.names N_171_i.BLIF N_171 +0 1 +.names N_142.BLIF CLK_000_D_11_.BLIF N_356_1 +11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names AS_000_i.BLIF RW_000_c.BLIF N_282_1 +11 1 +.names BGACK_030_INT_i.BLIF N_171_i.BLIF N_345 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_251_1 +11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names BGACK_030_INT_i.BLIF N_171.BLIF N_283 +11 1 +.names N_365.BLIF SM_AMIGA_6_.BLIF N_240_1 11 1 .names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +.names N_108.BLIF N_310.BLIF N_238_1 +11 1 +.names AS_000_c.BLIF N_319_i.BLIF N_370 +11 1 +.names N_169.BLIF N_360.BLIF N_233_1 +11 1 +.names N_363.BLIF RST_c.BLIF N_259 +11 1 +.names N_108.BLIF N_310.BLIF N_231_1 11 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 1- 1 -1 1 -.names AS_000_i.BLIF N_200_i.BLIF N_327_1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names N_245_i.BLIF rst_dly_i_0__n.BLIF N_224_1 +11 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 +.names N_245_i.BLIF N_322.BLIF N_218_1 +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_243_i.BLIF N_241_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_156.BLIF SM_AMIGA_1_.BLIF N_114 +11 1 +.names N_363.BLIF rw_000_dma_0_un3_n +0 1 +.names N_278_0.BLIF N_278 +0 1 +.names inst_RW_000_DMA.BLIF N_363.BLIF rw_000_dma_0_un1_n 11 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 1- 1 -1 1 -.names inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF N_319_1 -11 1 -.names N_293_0.BLIF N_293 +.names N_25.BLIF N_25_i 0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_285_1 +.names N_281.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_319_i.BLIF SM_AMIGA_6_.BLIF N_113 +11 1 +.names N_25_i.BLIF RST_c.BLIF N_34_0 +11 1 +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +0 1 +.names N_279_0.BLIF N_279 +0 1 +.names N_24.BLIF N_24_i +0 1 +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_184.BLIF RST_c.BLIF N_277_1 +.names N_24_i.BLIF RST_c.BLIF N_35_0 11 1 -.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names N_115_1.BLIF N_115_2.BLIF N_115 +11 1 +.names N_23.BLIF N_23_i 0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_236_1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_63_0.BLIF N_63 +0 1 +.names N_23_i.BLIF RST_c.BLIF N_36_0 11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \ -DS_000_ENABLE_1_sqmuxa_1 -11 1 -.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_228_1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n 11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 1- 1 -1 1 -.names N_172.BLIF BERR_i.BLIF N_225_1 +.names N_19.BLIF N_19_i +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +.names pos_clk_un3_as_030_d0_0_n.BLIF pos_clk_un3_as_030_d0_n 0 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_176.BLIF BERR_i.BLIF N_224_1 +.names N_19_i.BLIF RST_c.BLIF N_40_0 11 1 -.names N_290_0.BLIF N_290 +.names N_363.BLIF amiga_bus_enable_dma_high_0_un3_n 0 1 -.names N_216_i.BLIF rst_dly_i_0__n.BLIF N_222_1 +.names N_67_0.BLIF N_67 +0 1 +.names N_17.BLIF N_17_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_363.BLIF \ +amiga_bus_enable_dma_high_0_un1_n 11 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names N_149.BLIF N_216_i.BLIF N_215_1 -11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names N_214_i.BLIF N_212_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_194.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_232 -11 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names N_194_0.BLIF N_194 -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names N_366.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_233 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names N_153.BLIF SM_AMIGA_1_.BLIF N_275 -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 -.names N_153_0.BLIF N_153 -0 1 -.names N_26.BLIF N_26_i -0 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names N_191_0.BLIF N_191 -0 1 -.names N_26_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_146.BLIF sm_amiga_i_6__n.BLIF N_334 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n -0 1 -.names N_146_0.BLIF N_146 -0 1 -.names N_21_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_345 -11 1 -.names N_17.BLIF N_17_i -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names clk_000_p_sync_i_10__n.BLIF SM_AMIGA_4_.BLIF N_346 -11 1 .names N_17_i.BLIF RST_c.BLIF N_42_0 11 1 -.names N_258.BLIF dsack1_int_0_un3_n -0 1 -.names N_163_i.BLIF N_163 -0 1 -.names N_4.BLIF N_4_i -0 1 -.names N_275_i.BLIF N_258.BLIF dsack1_int_0_un1_n +.names N_132_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n 11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names N_4_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names pos_clk_un4_clk_000_pe_0_n.BLIF pos_clk_un4_clk_000_pe_n +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n 0 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_235 -11 1 .names ipl_c_1__n.BLIF ipl_c_i_1__n 0 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_154_i.BLIF cpu_est_i_1__n.BLIF N_284 -11 1 +.names N_363.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 .names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names N_190_0.BLIF N_190 -0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_363.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_22 +1- 1 +-1 1 .names ipl_c_2__n.BLIF ipl_c_i_2__n 0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names N_131_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n 11 1 -.names N_195.BLIF RESET_OUT_i.BLIF N_337 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 .names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_195_0.BLIF N_195 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names N_27.BLIF N_27_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names CLK_000_N_SYNC_12_.BLIF N_166.BLIF N_340 -11 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names N_231_1.BLIF N_231_2.BLIF N_231 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_363 11 1 .names N_28.BLIF N_28_i 0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_230_3.BLIF cpu_est_i_3__n.BLIF N_230 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 +1- 1 +-1 1 .names N_28_i.BLIF RST_c.BLIF N_31_0 11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names N_280_1.BLIF N_280_2.BLIF N_280 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_157_4.BLIF N_157_3.BLIF N_157 11 1 .names N_29.BLIF N_29_i 0 1 -.names N_291.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names N_260_1.BLIF N_260_2.BLIF N_260 11 1 +.names N_29_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_139.BLIF N_364.BLIF N_219 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n +0 1 +.names N_139_0.BLIF N_139 +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names N_108.BLIF rst_dly_i_2__n.BLIF N_220 +11 1 +.names N_332.BLIF N_332_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n +11 1 +.names N_139.BLIF N_322_i.BLIF N_222 +11 1 +.names N_240.BLIF N_240_i +0 1 +.names N_279.BLIF as_000_int_0_un3_n +0 1 +.names N_368.BLIF rst_dly_i_1__n.BLIF N_223 +11 1 +.names N_240_i.BLIF N_332_i.BLIF N_315_0 +11 1 +.names N_113_i.BLIF N_279.BLIF as_000_int_0_un1_n +11 1 +.names N_108.BLIF RST_c.BLIF N_368 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_281_0 +11 1 +.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names N_108.BLIF cpu_est_i_0__n.BLIF N_257 +11 1 +.names N_270.BLIF N_270_i +0 1 +.names N_63.BLIF ds_000_enable_0_un3_n +0 1 +.names N_108_i.BLIF cpu_est_0_.BLIF N_258 +11 1 +.names N_282.BLIF N_282_i +0 1 +.names N_115.BLIF N_63.BLIF ds_000_enable_0_un1_n +11 1 +.names N_108_i.BLIF N_364_i_0.BLIF N_312 +11 1 +.names N_270_i.BLIF N_282_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n +11 1 +.names N_143_0.BLIF N_143 +0 1 +.names RW_c.BLIF RW_c_i +0 1 +.names N_67.BLIF as_030_000_sync_0_un3_n +0 1 +.names N_332_1.BLIF sm_amiga_i_i_7__n.BLIF N_332 +11 1 +.names RW_c_i.BLIF SM_AMIGA_6_.BLIF N_140_0 +11 1 +.names pos_clk_un3_as_030_d0_n.BLIF N_67.BLIF as_030_000_sync_0_un1_n +11 1 +.names N_332_4_1.BLIF N_332_4_2.BLIF N_332_4 +11 1 +.names N_353.BLIF N_353_i +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names N_246_4.BLIF N_246_3.BLIF N_246 +11 1 +.names N_159.BLIF N_353_i.BLIF N_143_0 +11 1 +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +0 1 +.names N_180_i.BLIF N_180 +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +rw_000_int_0_un1_n +11 1 +.names N_320_i.BLIF N_320 +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_320_i +11 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names N_320.BLIF N_360.BLIF N_244 +11 1 +.names N_357.BLIF N_357_i +0 1 +.names N_363.BLIF a0_dma_0_un3_n +0 1 +.names N_144.BLIF N_180.BLIF N_334 +11 1 +.names N_356.BLIF N_356_i +0 1 +.names inst_A0_DMA.BLIF N_363.BLIF a0_dma_0_un1_n +11 1 +.names N_310.BLIF N_320.BLIF N_335 +11 1 +.names N_356_i.BLIF N_357_i.BLIF N_156_0 +11 1 +.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names N_159_i.BLIF N_159 +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names N_156_0.BLIF N_156 +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_159_i +11 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_357 +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names N_140.BLIF N_319_i.BLIF N_353 +11 1 +.names N_159_i.BLIF sm_amiga_i_2__n.BLIF N_180_i +11 1 +.names N_259.BLIF size_dma_0_1__un3_n +0 1 +.names N_140_0.BLIF N_140 +0 1 +.names N_334.BLIF N_334_i +0 1 +.names SIZE_DMA_1_.BLIF N_259.BLIF size_dma_0_1__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_270 +11 1 +.names N_335.BLIF N_335_i +0 1 +.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ +size_dma_0_1__un0_n +11 1 +.names N_281_0.BLIF N_281 +0 1 +.names N_244.BLIF N_244_i +0 1 +.names N_259.BLIF size_dma_0_0__un3_n +0 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_131 +11 1 +.names N_233.BLIF N_233_i +0 1 +.names SIZE_DMA_0_.BLIF N_259.BLIF size_dma_0_0__un1_n +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_132 +11 1 +.names N_355.BLIF N_355_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \ +size_dma_0_0__un0_n +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +1- 1 +-1 1 +.names N_229.BLIF N_229_i +0 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -1737,7 +1683,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_292.BLIF E +.names N_317_i.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1755,7 +1701,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names un1_amiga_bus_enable_dma_high_0__n.BLIF AMIGA_BUS_ENABLE_HIGH +.names N_209.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 .names un10_ciin.BLIF CIIN @@ -1815,192 +1761,6 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C -1 1 -0 0 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C -1 1 -0 0 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C -1 1 -0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 -0 0 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C -1 1 -0 0 -.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_12_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -0 0 -.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 -0 0 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 -0 0 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 -0 0 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C -1 1 -0 0 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C -1 1 -0 0 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C -1 1 -0 0 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C -1 1 -0 0 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C -1 1 -0 0 -.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_10_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C -1 1 -0 0 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C -1 1 -0 0 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C -1 1 -0 0 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C -1 1 -0 0 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C -1 1 -0 0 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C -1 1 -0 0 -.names CLK_000_c.BLIF CLK_000_D_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -0 0 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -0 0 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -0 0 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_3_.C -1 1 -0 0 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_4_.C -1 1 -0 0 -.names CLK_000_D_4_.BLIF CLK_000_D_5_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_5_.C -1 1 -0 0 .names CLK_000_D_5_.BLIF CLK_000_D_6_.D 1 1 0 0 @@ -2043,16 +1803,22 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF CLK_000_D_12_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 -.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_1_.C @@ -2061,34 +1827,43 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +0 0 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_AS_000_DMA.C @@ -2115,6 +1890,15 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF inst_DTACK_D0.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -2124,10 +1908,25 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 0 0 -.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C @@ -2334,9 +2133,6 @@ DS_000_ENABLE_1_sqmuxa_1 .names CLK_030.BLIF CLK_030_c 1 1 0 0 -.names CLK_000.BLIF CLK_000_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -2385,10 +2181,10 @@ DS_000_ENABLE_1_sqmuxa_1 .names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 -.names N_200_i.BLIF SIZE_0_.OE +.names un1_as_030_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_200_i.BLIF SIZE_1_.OE +.names un1_as_030_i.BLIF SIZE_1_.OE 1 1 0 0 .names un3_as_030_i.BLIF AHIGH_24_.OE @@ -2421,7 +2217,7 @@ DS_000_ENABLE_1_sqmuxa_1 .names un22_berr.BLIF BERR.OE 1 1 0 0 -.names N_318.BLIF RW.OE +.names N_93_i.BLIF RW.OE 1 1 0 0 .names un3_as_030_i.BLIF DS_030.OE @@ -2433,40 +2229,31 @@ DS_000_ENABLE_1_sqmuxa_1 .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_296.BLIF CIIN.OE +.names N_313.BLIF CIIN.OE 1 1 0 0 -.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_134 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_116 01 1 10 1 11 0 00 0 -.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_135 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_117 01 1 10 1 11 0 00 0 -.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_136 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_118 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_x2 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +pos_clk_un23_bgack_030_int_i_0_o2_2_x2 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_ -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_0_.BLIF CLK_000_P_SYNC_10_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_1_.BLIF N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +.names CYCLE_DMA_1_.BLIF N_263.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index c87028c..b146d36 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 8 19 0 20 36) + (timeStamp 2016 8 19 0 39 30) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -172,74 +172,6 @@ ) (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_12 "CLK_000_N_SYNC[12]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_10 "CLK_000_P_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_2 "CLK_000_D[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_3 "CLK_000_D[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_4 "CLK_000_D[4]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_5 "CLK_000_D[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename CLK_000_D_6 "CLK_000_D[6]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_D_7 "CLK_000_D[7]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -254,35 +186,35 @@ ) (instance (rename CLK_000_D_12 "CLK_000_D[12]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_2 "CLK_000_D[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_3 "CLK_000_D[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_4 "CLK_000_D[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_5 "CLK_000_D[5]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -300,13 +232,31 @@ ) (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -391,460 +341,402 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_0 "SM_AMIGA_nss_i_i_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_137_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_137 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a2_1_2 "SM_AMIGA_srsts_i_i_0_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a2_2 "SM_AMIGA_srsts_i_i_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_1_1_1 "cpu_est_2_0_0_a2_1_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_1_1 "cpu_est_2_0_0_a2_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_1_3 "SM_AMIGA_srsts_i_0_0_a2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_1_1_0 "SM_AMIGA_nss_i_i_0_0_a2_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_1_0 "SM_AMIGA_nss_i_i_0_0_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_1_0 "SM_AMIGA_nss_i_i_0_0_a2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_1 "pos_clk.CYCLE_DMA_5_1_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i "pos_clk.CYCLE_DMA_5_1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_5 "SM_AMIGA_srsts_i_0_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_1 "pos_clk.un6_bg_030_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2 "pos_clk.un6_bg_030_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_1 "pos_clk.un4_clk_000_pe_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_2 "pos_clk.un4_clk_000_pe_0_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_3 "pos_clk.un4_clk_000_pe_0_0_a2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2 "pos_clk.un4_clk_000_pe_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_1_0 "SM_AMIGA_nss_i_i_0_0_a2_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_2_0 "SM_AMIGA_nss_i_i_0_0_a2_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_3_0 "SM_AMIGA_nss_i_i_0_0_a2_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_0 "SM_AMIGA_nss_i_i_0_0_a2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1 "pos_clk.un37_as_030_d0_0_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o2_2_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o2_2_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o2_2_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_6 "SM_AMIGA_srsts_i_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_2_6 "SM_AMIGA_srsts_i_0_2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_6 "SM_AMIGA_srsts_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a2_0_1_2 "SM_AMIGA_srsts_i_i_0_a2_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a2_0_2_2 "SM_AMIGA_srsts_i_i_0_a2_0_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a2_0_2 "SM_AMIGA_srsts_i_i_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_0_1 "pos_clk.un4_clk_000_pe_0_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_0_2 "pos_clk.un4_clk_000_pe_0_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_0 "pos_clk.un4_clk_000_pe_0_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_1_3 "SM_AMIGA_srsts_i_0_0_a2_2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_1 "pos_clk.un23_bgack_030_int_i_0_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2 "pos_clk.un23_bgack_030_int_i_0_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_0_o2 "pos_clk.un23_bgack_030_int_i_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_1 "pos_clk.un37_as_030_d0_0_i_a2_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_2 "pos_clk.un37_as_030_d0_0_i_a2_1_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_3 "pos_clk.un37_as_030_d0_0_i_a2_1_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_4 "pos_clk.un37_as_030_d0_0_i_a2_1_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_1_0 "SM_AMIGA_nss_i_i_0_0_o2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_0 "SM_AMIGA_nss_i_i_0_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_5 "SM_AMIGA_srsts_0_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_1_2 "SM_AMIGA_srsts_0_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_2 "SM_AMIGA_srsts_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_1_1 "SM_AMIGA_srsts_0_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_1 "SM_AMIGA_srsts_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_119_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_119 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_1 "pos_clk.CYCLE_DMA_5_1_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_0 "pos_clk.CYCLE_DMA_5_1_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_1_1_1 "cpu_est_2_0_0_a3_1_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_1_1 "cpu_est_2_0_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a3_1 "pos_clk.un6_bg_030_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a3 "pos_clk.un6_bg_030_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a3_1_6 "SM_AMIGA_srsts_i_i_a3_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a3_6 "SM_AMIGA_srsts_i_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_1_5 "SM_AMIGA_srsts_0_0_a3_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a3_0_1_6 "SM_AMIGA_srsts_i_i_a3_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_a3_0_6 "SM_AMIGA_srsts_i_i_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_1_0 "SM_AMIGA_nss_i_0_0_a3_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_2_0 "SM_AMIGA_nss_i_0_0_a3_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_3_0 "SM_AMIGA_nss_i_0_0_a3_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_4_0 "SM_AMIGA_nss_i_0_0_a3_2_4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_0 "SM_AMIGA_nss_i_0_0_a3_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_5_1_0 "SM_AMIGA_nss_i_0_0_a3_2_5_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_5_2_0 "SM_AMIGA_nss_i_0_0_a3_2_5_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_2_5_0 "SM_AMIGA_nss_i_0_0_a3_2_5[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i_a3_1 "pos_clk.un37_as_030_d0_i_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i_a3_2 "pos_clk.un37_as_030_d0_i_i_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i_a3 "pos_clk.un37_as_030_d0_i_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_2_0 "SM_AMIGA_nss_i_i_0_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_3_0 "SM_AMIGA_nss_i_i_0_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_2_3 "SM_AMIGA_srsts_i_0_0_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_0 "SM_AMIGA_nss_i_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0 "pos_clk.CYCLE_DMA_5_0_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_1 "pos_clk.un9_clk_000_pe_0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_2 "pos_clk.un9_clk_000_pe_0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3 "pos_clk.un9_clk_000_pe_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0_1 "pos_clk.un9_clk_000_pe_0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0_2 "pos_clk.un9_clk_000_pe_0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a3_0 "pos_clk.un9_clk_000_pe_0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_1_2 "SM_AMIGA_srsts_0_0_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_2_2 "SM_AMIGA_srsts_0_0_a2_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_2 "SM_AMIGA_srsts_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_1 "pos_clk.un37_as_030_d0_i_a2_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_2 "pos_clk.un37_as_030_d0_i_a2_1_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_3 "pos_clk.un37_as_030_d0_i_a2_1_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1_4 "pos_clk.un37_as_030_d0_i_a2_1_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_1 "pos_clk.un37_as_030_d0_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2_o3_1 "pos_clk.un23_bgack_030_int_i_0_o2_2_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2_o3_2 "pos_clk.un23_bgack_030_int_i_0_o2_2_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2_o3 "pos_clk.un23_bgack_030_int_i_0_o2_2_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_1 "pos_clk.CYCLE_DMA_5_0_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_2 "pos_clk.CYCLE_DMA_5_0_i_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_o2_1 "pos_clk.un37_as_030_d0_0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_o2 "pos_clk.un37_as_030_d0_0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_328_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_325_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_327_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_320_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_319_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_283_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_281_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_i "pos_clk.un23_bgack_030_int_i_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_341_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_338_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_339_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_336_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_211_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_1_0 "SM_AMIGA_nss_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_2_0 "SM_AMIGA_nss_i_0_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_3_0 "SM_AMIGA_nss_i_0_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_4_0 "SM_AMIGA_nss_i_0_0_4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_5_0 "SM_AMIGA_nss_i_0_0_5[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_0 "SM_AMIGA_nss_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_235_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_236_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_i_3 "SM_AMIGA_srsts_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_234_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_i_2 "SM_AMIGA_srsts_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_232_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_i_1 "SM_AMIGA_srsts_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_230_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_i_0 "SM_AMIGA_srsts_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_331_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_330_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_0_i "pos_clk.DS_000_DMA_4_f0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_329_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_349_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un4_bgack_000_i_o2_i "pos_clk.un4_bgack_000_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_324_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_347_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_348_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_311_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_290_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_346_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_0_i "pos_clk.DS_000_DMA_4_f0_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_268_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_269_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_0_i_4 "SM_AMIGA_srsts_0_0_0_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_341_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_238_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_239_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_i_5 "SM_AMIGA_srsts_0_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_362_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_o2_i_2 "SM_AMIGA_srsts_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_0_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_o2_i_3 "SM_AMIGA_srsts_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_i_i_o2_i_3 "cpu_est_2_i_i_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_263_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_262_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_o2_0_o3_i "pos_clk.CYCLE_DMA_5_1_i_o2_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_366_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2_o3_i "pos_clk.un23_bgack_030_int_i_0_o2_2_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_310_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_359_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_i_0 "SM_AMIGA_nss_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_251_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_253_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_369_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_254_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_256_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_255_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_266_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_0_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_361_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_283_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_249_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_248_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_i "pos_clk.un9_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_250_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_10_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_370_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_i "pos_clk.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_1_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_260_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i_i "pos_clk.un37_as_030_d0_i_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0_i "pos_clk.RW_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_5_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_7_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_10_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_i "pos_clk.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_6 "SM_AMIGA_srsts_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_o2_i_2 "SM_AMIGA_srsts_i_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_218_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_312_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_170_i_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_258_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_257_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o3_i "pos_clk.un3_as_030_d0_0_o2_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_0_i_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_356_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_2_i_0 "SM_AMIGA_nss_i_0_0_o2_2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_1_i_0 "SM_AMIGA_nss_i_0_0_o2_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_334_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_335_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_o2_i "pos_clk.un37_as_030_d0_0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_5 "SM_AMIGA_srsts_i_0_0_o2_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o2_2_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_346_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0_i_6 "SM_AMIGA_srsts_i_0_o2_0_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_344_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o2_i "pos_clk.un3_as_030_d0_0_o2_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_244_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_233_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_232_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_i "pos_clk.un37_as_030_d0_0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un13_ciin_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_284_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_285_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_i_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_280_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_277_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_i_2 "SM_AMIGA_srsts_i_i_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_235_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_236_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_230_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0_i "pos_clk.un4_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_355_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_229_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_246_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_i_0 "SM_AMIGA_nss_i_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_217_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_2_0_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_1 "SM_AMIGA_srsts_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_o2_i_3 "cpu_est_2_i_0_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_340_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_337_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_i_3 "cpu_est_2_i_0_i_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_i_0 "SM_AMIGA_nss_i_i_0_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_i_0 "SM_AMIGA_nss_i_i_0_0_o2_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_3_i_0 "SM_AMIGA_nss_i_i_0_0_o2_3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_343_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_240_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_i_6 "SM_AMIGA_srsts_i_i_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_270_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_353_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_0_i_0 "SM_AMIGA_nss_i_0_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_357_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_28_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_29_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_357_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_254_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_315_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_275_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_N_SYNC_i_12 "CLK_000_N_SYNC_i[12]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_136 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_135 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_134 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_3 "cpu_est_2_i_0_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_2 "cpu_est_2_0_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_252 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_a2_3 "cpu_est_2_i_0_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0 "SM_AMIGA_nss_i_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_i_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_x2_0_x2_0 "cpu_est_0_0_x2_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_1 "SM_AMIGA_srsts_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_226 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_1_0 "SM_AMIGA_nss_i_0_0_a3_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_0_0 "SM_AMIGA_nss_i_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a3_0 "SM_AMIGA_nss_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_118 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_117 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_3_0 "SM_AMIGA_nss_i_i_0_0_o2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_2 "SM_AMIGA_srsts_i_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un3_as_030_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_o2_3 "cpu_est_2_i_0_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_1 "SM_AMIGA_srsts_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__r "SM_AMIGA_srsts_i_0_m2_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__m "SM_AMIGA_srsts_i_0_m2_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__n "SM_AMIGA_srsts_i_0_m2_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__p "SM_AMIGA_srsts_i_0_m2_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_1 "cpu_est_2_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_4 "SM_AMIGA_srsts_i_0_0_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un2_rw_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_1 "SM_AMIGA_srsts_i_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_clk_000_pe_0_0 "pos_clk.un4_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_6 "SM_AMIGA_srsts_i_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_11 "CLK_000_D_i[11]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o2_2_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i "pos_clk.un37_as_030_d0_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o2 "pos_clk.un3_as_030_d0_0_o2_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_1_0 "SM_AMIGA_nss_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_2_0 "SM_AMIGA_nss_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DSACK1_INT_1_sqmuxa_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0_6 "SM_AMIGA_srsts_i_0_o2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_5 "SM_AMIGA_srsts_i_0_0_o2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__r "SM_AMIGA_srsts_i_0_0_m2_5_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__m "SM_AMIGA_srsts_i_0_0_m2_5_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__n "SM_AMIGA_srsts_i_0_0_m2_5_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__p "SM_AMIGA_srsts_i_0_0_m2_5_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_i_10 "CLK_000_P_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_253 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2 "pos_clk.un37_as_030_d0_0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_0_i_a2_0 "pos_clk.un37_as_030_d0_0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_5 "SM_AMIGA_srsts_i_0_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_1_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_0_0 "SM_AMIGA_nss_i_0_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance I_254 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_1_i_a2_3_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_6 "SM_AMIGA_srsts_i_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_11 "CLK_000_D_i[11]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_364_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_0 "SM_AMIGA_srsts_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_126_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_126_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_i_i_0 "cpu_est_0_i_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_170_i_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_157_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_227 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un22_berr_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_i_i_a3_0 "cpu_est_0_i_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_i_i_a3_0_0 "cpu_est_0_i_i_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_A0_DMA_3_0_a2_0_a3 "pos_clk.A0_DMA_3_0_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i "pos_clk.un37_as_030_d0_i_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o3 "pos_clk.un3_as_030_d0_0_o2_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_113_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -857,114 +749,169 @@ (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_x2 "pos_clk.CYCLE_DMA_5_0_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance I_255 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un4_bgack_000_i_o2 "pos_clk.un4_bgack_000_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_o2_2 "SM_AMIGA_srsts_i_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_6 "SM_AMIGA_srsts_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_3_0 "SM_AMIGA_nss_i_i_0_0_a2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_0_6 "SM_AMIGA_srsts_i_0_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_4 "SM_AMIGA_srsts_i_0_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_0_x2 "pos_clk.un23_bgack_030_int_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0 "SM_AMIGA_srsts_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_256 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_0_a2 "pos_clk.DS_000_DMA_4_f0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_0_a2 "pos_clk.un23_bgack_030_int_i_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_10 "CLK_000_D_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_3_3 "SM_AMIGA_srsts_i_0_0_a2_3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_0 "pos_clk.DS_000_DMA_4_f0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a2_0 "pos_clk.CLK_000_P_SYNC_2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CLK_000_N_SYNC_2_0_a2_0 "pos_clk.CLK_000_N_SYNC_2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_as_030_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_263 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_264 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_261 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_262 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_259 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_260 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_257 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_258 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_0 "pos_clk.SIZE_DMA_6_0_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_323_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_212_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_322_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_321_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_1 "pos_clk.SIZE_DMA_6_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_0 "pos_clk.SIZE_DMA_6_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un3_as_030_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_a2 "pos_clk.un6_bgack_000_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_1 "pos_clk.SIZE_DMA_6_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0 "pos_clk.un9_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_0_2 "SM_AMIGA_srsts_0_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_i_i_a3_3 "cpu_est_2_i_i_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a3_2 "cpu_est_2_0_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a3_1 "cpu_est_2_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_o2_0_o3 "pos_clk.CYCLE_DMA_5_1_i_o2_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_x2 "pos_clk.CYCLE_DMA_5_1_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_i_i_o2_3 "cpu_est_2_i_i_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_o2_3 "SM_AMIGA_srsts_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_o2_2 "SM_AMIGA_srsts_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_o2 "pos_clk.un9_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_0_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_i_i_3 "cpu_est_2_i_i_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_0 "SM_AMIGA_srsts_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_1 "SM_AMIGA_srsts_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_2 "SM_AMIGA_srsts_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_3 "SM_AMIGA_srsts_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_5 "SM_AMIGA_srsts_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_0_4 "SM_AMIGA_srsts_0_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_0 "pos_clk.DS_000_DMA_4_f0_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_rw_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2_x2 "pos_clk.un23_bgack_030_int_i_0_o2_2_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_o2_0 "SM_AMIGA_nss_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_0_a3_4 "SM_AMIGA_srsts_0_0_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_0_a3_0_4 "SM_AMIGA_srsts_0_0_0_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_0_a3 "pos_clk.DS_000_DMA_4_f0_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_229 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_as_030_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2_a2 "pos_clk.un23_bgack_030_int_i_0_o2_2_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_0_0_a2_0 "SM_AMIGA_nss_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_10 "CLK_000_D_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_0_1 "SM_AMIGA_srsts_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a2_0_0 "SM_AMIGA_srsts_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_233 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_230 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_231 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_116 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_0 "SM_AMIGA_srsts_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_0_0 "SM_AMIGA_srsts_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_0_1 "SM_AMIGA_srsts_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_0_2 "SM_AMIGA_srsts_0_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_3 "SM_AMIGA_srsts_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_0_3 "SM_AMIGA_srsts_0_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_0_0_a3_0_5 "SM_AMIGA_srsts_0_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_a3 "pos_clk.CYCLE_DMA_5_0_i_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_111 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_241_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_242_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_243_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_236 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_237 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_234 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_235 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_232 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance un4_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un4_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un6_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -980,24 +927,19 @@ (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) - (portRef I0 (instanceRef BGACK_030_INT_0_n)) (portRef I0 (instanceRef un1_as_000_0)) + (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_a2)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3)) (portRef I0 (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0)) (portRef I0 (instanceRef BGACK_030)) )) (net VCC (joined @@ -1022,16 +964,12 @@ (portRef I0 (instanceRef BERR)) (portRef I0 (instanceRef RESET)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH[0]") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) - )) (net un1_amiga_bus_enable_low (joined (portRef O (instanceRef un1_amiga_bus_enable_low)) (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) )) (net un6_as_030 (joined - (portRef O (instanceRef un6_as_030_0_a2)) + (portRef O (instanceRef un6_as_030_0_a2_0_a3)) (portRef I0 (instanceRef un6_as_030_i)) )) (net un3_size (joined @@ -1055,80 +993,81 @@ (portRef I0 (instanceRef un4_as_000_i)) )) (net un10_ciin (joined - (portRef O (instanceRef un10_ciin_0_a2)) + (portRef O (instanceRef un10_ciin_0_a3)) (portRef I0 (instanceRef un10_ciin_i)) (portRef I0 (instanceRef CIIN)) )) (net un21_fpu_cs (joined - (portRef O (instanceRef un21_fpu_cs_0_a2)) + (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3)) (portRef I0 (instanceRef un21_fpu_cs_i)) )) (net un22_berr (joined - (portRef O (instanceRef un22_berr_0_a2)) + (portRef O (instanceRef un22_berr_0_a2_0_a3)) (portRef OE (instanceRef BERR)) )) (net un6_ds_030 (joined (portRef O (instanceRef un6_ds_030)) (portRef I0 (instanceRef un6_ds_030_i)) )) - (net (rename cpu_est_2 "cpu_est[2]") (joined - (portRef Q (instanceRef cpu_est_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I1 (instanceRef cpu_est_2_i_0_i_a2_3)) - (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef un5_e_i_i_a2_0_1)) - )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef un5_e_i_i_o2)) + (portRef I0 (instanceRef un5_e_0_i_o2)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__n)) + (portRef I0 (instanceRef cpu_est_2_i_i_i_o2_3)) + (portRef I0 (instanceRef cpu_est_0_3__m)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I1 (instanceRef cpu_est_0_i_i_a3_0_0)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_0_0_x2_0_x2_0)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_1_1_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_1_1_1)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I0 (instanceRef un5_e_0_i_o2_0)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_1)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef un5_e_i_i_a2_0_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + )) + (net (rename cpu_est_2 "cpu_est[2]") (joined + (portRef Q (instanceRef cpu_est_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_2)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef un5_e_0_i_a3)) + (portRef I0 (instanceRef cpu_est_0_2__m)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef AS_000_INT_0_n)) (portRef I0 (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef AS_000_INT_0_n)) )) (net AMIGA_BUS_ENABLE_DMA_LOW (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) (portRef I0 (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a3_1)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_a2)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) (portRef I0 (instanceRef AS_000_DMA_0_n)) (portRef I0 (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_a3)) )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) @@ -1137,36 +1076,36 @@ )) (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_x2)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) - (portRef I1 (instanceRef G_129)) + (portRef I0 (instanceRef G_111)) + (portRef I0 (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_x2)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_x2)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_x2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) )) (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined (portRef Q (instanceRef SIZE_DMA_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__n)) - (portRef I0 (instanceRef SIZE_DMA_i_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__m)) (portRef I0 (instanceRef un4_size)) + (portRef I0 (instanceRef SIZE_DMA_i_0)) )) (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined (portRef Q (instanceRef SIZE_DMA_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__n)) - (portRef I0 (instanceRef un3_size)) + (portRef I0 (instanceRef SIZE_DMA_0_1__m)) (portRef I0 (instanceRef SIZE_DMA_i_1)) + (portRef I0 (instanceRef un3_size)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3_3)) (portRef I0 (instanceRef VPA_D_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_0_2)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) - (portRef I0 (instanceRef UDS_000_INT_i)) (portRef I0 (instanceRef UDS_000_INT_0_n)) + (portRef I0 (instanceRef UDS_000_INT_i)) )) (net LDS_000_INT (joined (portRef Q (instanceRef LDS_000_INT)) @@ -1178,6 +1117,12 @@ (portRef I0 (instanceRef CLK_OUT_PRE_D_i)) (portRef D (instanceRef CLK_OUT_INT)) )) + (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined + (portRef Q (instanceRef CLK_000_D_1)) + (portRef I0 (instanceRef N_170_i_0_o2_i_o2)) + (portRef I0 (instanceRef CLK_000_D_i_1)) + (portRef D (instanceRef CLK_000_D_2)) + )) (net (rename CLK_000_D_10 "CLK_000_D[10]") (joined (portRef Q (instanceRef CLK_000_D_10)) (portRef I0 (instanceRef CLK_000_D_i_10)) @@ -1186,7 +1131,7 @@ (net (rename CLK_000_D_11 "CLK_000_D[11]") (joined (portRef Q (instanceRef CLK_000_D_11)) (portRef I0 (instanceRef CLK_000_D_i_11)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0_1)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) (portRef D (instanceRef CLK_000_D_12)) )) (net DTACK_D0 (joined @@ -1195,61 +1140,40 @@ )) (net RESET_OUT (joined (portRef Q (instanceRef RESET_OUT)) - (portRef I1 (instanceRef un2_rw_i_a2)) - (portRef I1 (instanceRef un3_as_030_0)) - (portRef I0 (instanceRef RESET_OUT_i)) (portRef I1 (instanceRef un1_as_000_0)) + (portRef I1 (instanceRef un1_rw_i_a2_i)) + (portRef I0 (instanceRef RESET_OUT_2_0_0_a3)) + (portRef I0 (instanceRef un3_as_030_0)) + (portRef I0 (instanceRef RESET_OUT_i)) + )) + (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined + (portRef Q (instanceRef CLK_000_D_0)) + (portRef I0 (instanceRef N_88_i_0_o2)) + (portRef I0 (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a3)) + (portRef D (instanceRef CLK_000_D_1)) )) (net CLK_OUT_PRE_50 (joined (portRef Q (instanceRef CLK_OUT_PRE_50)) (portRef I0 (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_D)) )) - (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined - (portRef Q (instanceRef CLK_000_D_1)) - (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a2_0)) - (portRef I0 (instanceRef CLK_000_D_i_1)) - (portRef D (instanceRef CLK_000_D_2)) - )) - (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined - (portRef Q (instanceRef CLK_000_D_0)) - (portRef I0 (instanceRef CLK_000_D_i_0)) - (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2)) - (portRef D (instanceRef CLK_000_D_1)) - )) - (net (rename CLK_000_P_SYNC_10 "CLK_000_P_SYNC[10]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_10)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I1 (instanceRef pos_clk_un4_bgack_000_i_o2)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) - (portRef I0 (instanceRef G_129)) - (portRef I0 (instanceRef CLK_000_P_SYNC_i_10)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_a2)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_1)) - )) - (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined - (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_5)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) - )) (net (rename IPL_D0_0 "IPL_D0[0]") (joined (portRef Q (instanceRef IPL_D0_0)) - (portRef I0 (instanceRef G_134)) + (portRef I0 (instanceRef G_116)) )) (net (rename IPL_D0_1 "IPL_D0[1]") (joined (portRef Q (instanceRef IPL_D0_1)) - (portRef I0 (instanceRef G_135)) + (portRef I0 (instanceRef G_117)) )) (net (rename IPL_D0_2 "IPL_D0[2]") (joined (portRef Q (instanceRef IPL_D0_2)) - (portRef I0 (instanceRef G_136)) + (portRef I0 (instanceRef G_118)) )) (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined (portRef Q (instanceRef CLK_000_D_2)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_0_1_6)) (portRef D (instanceRef CLK_000_D_3)) )) (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined @@ -1282,178 +1206,60 @@ )) (net (rename CLK_000_D_12 "CLK_000_D[12]") (joined (portRef Q (instanceRef CLK_000_D_12)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) )) (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a3)) (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) )) - (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined - (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_3_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_a2)) - (portRef I0 (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0)) + (net AMIGA_BUS_ENABLE_DMA_HIGH (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) (portRef I0 (instanceRef DSACK1_INT_0_n)) (portRef I0 (instanceRef DSACK1)) )) - (net (rename pos_clk_CLK_000_P_SYNC_2_0 "pos_clk.CLK_000_P_SYNC_2[0]") (joined - (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) - (portRef D (instanceRef CLK_000_P_SYNC_0)) - )) - (net (rename pos_clk_CLK_000_N_SYNC_2_0 "pos_clk.CLK_000_N_SYNC_2[0]") (joined - (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a2_0)) - (portRef D (instanceRef CLK_000_N_SYNC_0)) - )) (net (rename pos_clk_ipl "pos_clk.ipl") (joined - (portRef O (instanceRef G_137)) + (portRef O (instanceRef G_119)) (portRef I1 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__r)) (portRef I1 (instanceRef IPL_030_0_2__m)) (portRef I0 (instanceRef IPL_030_0_2__r)) - )) - (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) - (portRef D (instanceRef CLK_000_N_SYNC_1)) - )) - (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined - (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_a2)) - (portRef I0 (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) )) (net DS_000_ENABLE (joined (portRef Q (instanceRef DS_000_ENABLE)) - (portRef I0 (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef un4_lds_000)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) (portRef I0 (instanceRef un4_uds_000)) + (portRef I0 (instanceRef un4_lds_000)) )) - (net (rename CLK_000_N_SYNC_12 "CLK_000_N_SYNC[12]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_12)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_3)) - (portRef I0 (instanceRef RESET_OUT_2_0_i_o2)) - (portRef I0 (instanceRef CLK_000_N_SYNC_i_12)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_1)) - (portRef D (instanceRef CLK_000_NE_D0)) + (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined + (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_0_5)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_a3)) + (portRef I1 (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_1_6)) )) - (net (rename RST_DLY_0 "RST_DLY[0]") (joined - (portRef Q (instanceRef RST_DLY_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0)) - (portRef I0 (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a2)) + (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined + (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_i_0)) )) - (net (rename RST_DLY_1 "RST_DLY[1]") (joined - (portRef Q (instanceRef RST_DLY_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_o2_0)) - (portRef I0 (instanceRef RST_DLY_i_1)) - )) - (net (rename RST_DLY_2 "RST_DLY[2]") (joined - (portRef Q (instanceRef RST_DLY_2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) - (portRef I0 (instanceRef RST_DLY_i_2)) - )) - (net (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_0)) - (portRef D (instanceRef CLK_000_P_SYNC_1)) - )) - (net (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_1)) - (portRef D (instanceRef CLK_000_P_SYNC_2)) - )) - (net (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_2)) - (portRef D (instanceRef CLK_000_P_SYNC_3)) - )) - (net (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_3)) - (portRef D (instanceRef CLK_000_P_SYNC_4)) - )) - (net (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_4)) - (portRef D (instanceRef CLK_000_P_SYNC_5)) - )) - (net (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_5)) - (portRef D (instanceRef CLK_000_P_SYNC_6)) - )) - (net (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_6)) - (portRef D (instanceRef CLK_000_P_SYNC_7)) - )) - (net (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_7)) - (portRef D (instanceRef CLK_000_P_SYNC_8)) - )) - (net (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_8)) - (portRef D (instanceRef CLK_000_P_SYNC_9)) - )) - (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_9)) - (portRef D (instanceRef CLK_000_P_SYNC_10)) - )) - (net (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_1)) - (portRef D (instanceRef CLK_000_N_SYNC_2)) - )) - (net (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_2)) - (portRef D (instanceRef CLK_000_N_SYNC_3)) - )) - (net (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_3)) - (portRef D (instanceRef CLK_000_N_SYNC_4)) - )) - (net (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_4)) - (portRef D (instanceRef CLK_000_N_SYNC_5)) - )) - (net (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_5)) - (portRef D (instanceRef CLK_000_N_SYNC_6)) - )) - (net (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_6)) - (portRef D (instanceRef CLK_000_N_SYNC_7)) - )) - (net (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_7)) - (portRef D (instanceRef CLK_000_N_SYNC_8)) - )) - (net (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_8)) - (portRef D (instanceRef CLK_000_N_SYNC_9)) - )) - (net (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_9)) - (portRef D (instanceRef CLK_000_N_SYNC_10)) - )) - (net (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_10)) - (portRef D (instanceRef CLK_000_N_SYNC_11)) - )) - (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_11)) - (portRef D (instanceRef CLK_000_N_SYNC_12)) - )) - (net (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) - (portRef I1 (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined + (portRef Q (instanceRef SM_AMIGA_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_0_a3_4)) + (portRef I0 (instanceRef SM_AMIGA_i_4)) )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) @@ -1462,71 +1268,62 @@ )) (net RW_000_DMA (joined (portRef Q (instanceRef RW_000_DMA)) - (portRef I0 (instanceRef RW_000_DMA_0_n)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) (portRef I0 (instanceRef RW)) )) - (net CLK_000_NE_D0 (joined - (portRef Q (instanceRef CLK_000_NE_D0)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_0)) - (portRef I0 (instanceRef cpu_est_0_0_x2_0_x2_0)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3)) + (net (rename RST_DLY_0 "RST_DLY[0]") (joined + (portRef Q (instanceRef RST_DLY_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_a3)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0)) + (portRef I0 (instanceRef RST_DLY_i_0)) )) - (net AMIGA_BUS_ENABLE_DMA_HIGH (joined - (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) + (net (rename RST_DLY_1 "RST_DLY[1]") (joined + (portRef Q (instanceRef RST_DLY_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_o2_0)) + (portRef I0 (instanceRef RST_DLY_i_1)) + )) + (net (rename RST_DLY_2 "RST_DLY[2]") (joined + (portRef Q (instanceRef RST_DLY_2)) + (portRef I0 (instanceRef RST_DLY_i_2)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_126_0_a2)) )) (net A0_DMA (joined (portRef Q (instanceRef A0_DMA)) - (portRef I0 (instanceRef A0_DMA_0_n)) - (portRef I0 (instanceRef A_0)) - )) - (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined - (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) (portRef I0 (instanceRef A0_DMA_0_m)) - )) - (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined - (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I0 (instanceRef A_0)) )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) (portRef I0 (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_a3)) )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_0_0)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a3)) (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_1)) + )) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_0_a3_0_4)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_5)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a2_0)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a3_0_1)) (portRef I0 (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_2)) )) (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_i)) (portRef I0 (instanceRef DS_000_DMA_0_m)) )) (net N_3 (joined @@ -1557,21 +1354,9 @@ (portRef O (instanceRef cpu_est_0_3__p)) (portRef D (instanceRef cpu_est_3)) )) - (net N_19 (joined - (portRef O (instanceRef RW_000_DMA_0_p)) - (portRef I0 (instanceRef N_19_i)) - )) - (net N_20 (joined - (portRef O (instanceRef A0_DMA_0_p)) - (portRef I0 (instanceRef N_20_i)) - )) - (net N_24 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - (portRef I0 (instanceRef N_24_i)) - )) - (net N_25 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - (portRef I0 (instanceRef N_25_i)) + (net N_27 (joined + (portRef O (instanceRef IPL_030_0_0__p)) + (portRef I0 (instanceRef N_27_i)) )) (net N_30 (joined (portRef O (instanceRef IPL_030_1_i_0)) @@ -1597,24 +1382,24 @@ (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) )) - (net N_37 (joined - (portRef O (instanceRef VMA_INT_1_i)) - (portRef D (instanceRef VMA_INT)) - )) - (net N_38 (joined + (net N_36 (joined (portRef O (instanceRef UDS_000_INT_1_i)) (portRef D (instanceRef UDS_000_INT)) )) - (net N_39 (joined + (net N_37 (joined (portRef O (instanceRef A0_DMA_1_i)) (portRef D (instanceRef A0_DMA)) )) + (net N_38 (joined + (portRef O (instanceRef VMA_INT_1_i)) + (portRef D (instanceRef VMA_INT)) + )) (net N_40 (joined (portRef O (instanceRef RW_000_DMA_2_i)) (portRef D (instanceRef RW_000_DMA)) )) (net N_41 (joined - (portRef O (instanceRef RW_000_INT_2_i)) + (portRef O (instanceRef RW_000_INT_1_i)) (portRef D (instanceRef RW_000_INT)) )) (net N_42 (joined @@ -1665,342 +1450,448 @@ (portRef O (instanceRef DTACK_D0_0_i)) (portRef D (instanceRef DTACK_D0)) )) + (net N_57 (joined + (portRef O (instanceRef RESET_OUT_2_0_0_i)) + (portRef D (instanceRef RESET_OUT)) + )) (net N_58 (joined (portRef O (instanceRef DS_000_ENABLE_1)) (portRef D (instanceRef DS_000_ENABLE)) )) + (net (rename SM_AMIGA_nss_i_0 "SM_AMIGA_nss_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_i_0)) + (portRef D (instanceRef SM_AMIGA_i_7)) + )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef Q (instanceRef SM_AMIGA_i_7)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o3)) (portRef I0 (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_1_i_a2_3_a3_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_6)) )) - (net N_122 (joined - (portRef O (instanceRef un1_SM_AMIGA_3_i_0_i)) - (portRef I1 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_r)) + (net (rename SM_AMIGA_nss_2 "SM_AMIGA_nss[2]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_i_5)) + (portRef D (instanceRef SM_AMIGA_5)) )) - (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__m)) + (net (rename SM_AMIGA_nss_3 "SM_AMIGA_nss[3]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_0_i_4)) + (portRef D (instanceRef SM_AMIGA_4)) )) - (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__m)) + (net (rename SM_AMIGA_nss_4 "SM_AMIGA_nss[4]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_i_3)) + (portRef D (instanceRef SM_AMIGA_3)) )) - (net N_212 (joined - (portRef O (instanceRef G_134)) - (portRef I0 (instanceRef N_212_i)) - )) - (net N_213 (joined - (portRef O (instanceRef G_135)) - (portRef I0 (instanceRef N_213_i)) - )) - (net N_214 (joined - (portRef O (instanceRef G_136)) - (portRef I0 (instanceRef N_214_i)) - )) - (net N_257 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_i_2)) + (net (rename SM_AMIGA_nss_5 "SM_AMIGA_nss[5]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_i_2)) (portRef D (instanceRef SM_AMIGA_2)) )) - (net (rename pos_clk_un23_bgack_030_int_i_1 "pos_clk.un23_bgack_030_int_i_1") (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_i)) + (net (rename SM_AMIGA_nss_6 "SM_AMIGA_nss[6]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_i_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net (rename SM_AMIGA_nss_7 "SM_AMIGA_nss[7]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_i_0)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_263 (joined + (portRef O (instanceRef G_111)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2)) + (portRef I0 (instanceRef N_263_i)) + )) + (net N_241 (joined + (portRef O (instanceRef G_116)) + (portRef I0 (instanceRef N_241_i)) + )) + (net N_242 (joined + (portRef O (instanceRef G_117)) + (portRef I0 (instanceRef N_242_i)) + )) + (net N_243 (joined + (portRef O (instanceRef G_118)) + (portRef I0 (instanceRef N_243_i)) + )) + (net (rename pos_clk_un23_bgack_030_int_i_0 "pos_clk.un23_bgack_030_int_i_0") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_i)) (portRef I0 (instanceRef AS_000_DMA_0_m)) )) - (net N_292 (joined - (portRef O (instanceRef un5_e_i_i_i)) - (portRef I0 (instanceRef E)) - )) - (net N_294 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_i)) - (portRef I1 (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__r)) - (portRef I1 (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_0_0__r)) - )) - (net N_295 (joined - (portRef O (instanceRef un14_amiga_bus_data_dir_i_0_i)) - (portRef I0 (instanceRef RW_000_DMA_0_m)) - )) - (net N_296 (joined - (portRef O (instanceRef un13_ciin_i_0_i)) - (portRef OE (instanceRef CIIN)) - )) - (net N_298 (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_i)) + (net N_272 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0_i)) (portRef I1 (instanceRef AS_000_DMA_0_m)) (portRef I0 (instanceRef AS_000_DMA_0_r)) )) - (net N_120 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + (net N_273 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0_i)) (portRef I1 (instanceRef DS_000_DMA_0_m)) (portRef I0 (instanceRef DS_000_DMA_0_r)) )) - (net N_148 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0_1)) - )) - (net N_149 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_0_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_1)) - )) - (net N_157 (joined - (portRef O (instanceRef cpu_est_2_i_0_i_o2_i_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_i_3)) - )) - (net N_172 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_1_0)) - )) - (net N_176 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_1_0)) - )) - (net N_178 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_1_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3)) - )) - (net N_181 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) - )) - (net N_184 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_1_2)) - )) - (net N_186 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2_i)) + (net N_101 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_0_o3_i)) (portRef D (instanceRef BGACK_030_INT_D)) )) - (net N_196 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) - (portRef I0 (instanceRef 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(instanceRef SM_AMIGA_srsts_i_i_0_o2_2)) + (net N_369 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I0 (instanceRef N_369_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) )) - (net N_349 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_3_0)) - (portRef I0 (instanceRef N_349_i)) + (net N_196 (joined + (portRef O (instanceRef cpu_est_2_i_i_i_o2_i_3)) + (portRef I0 (instanceRef cpu_est_2_i_i_i_a3_3)) + )) + (net N_186 (joined + (portRef O (instanceRef un5_e_0_i_o2_0_i)) + (portRef I0 (instanceRef un5_e_0_i_a3)) + )) + (net N_361 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a2_2)) + (portRef I0 (instanceRef N_361_i)) + )) + (net N_362 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a2_0_2)) + (portRef I0 (instanceRef N_362_i)) + )) + (net N_151 (joined + (portRef O (instanceRef un5_e_0_i_o2_i)) + (portRef I0 (instanceRef un5_e_0_i_a3_0)) + )) + (net N_321 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_2)) + )) + (net N_266 (joined + (portRef O (instanceRef RESET_OUT_2_0_0_a3)) + (portRef I0 (instanceRef N_266_i)) + )) + (net N_267 (joined + (portRef O (instanceRef RESET_OUT_2_0_0_a3_0)) + (portRef I0 (instanceRef N_267_i)) + )) + (net N_255 (joined + (portRef O (instanceRef un5_e_0_i_a3)) + (portRef I0 (instanceRef N_255_i)) + )) + (net N_256 (joined + (portRef O (instanceRef un5_e_0_i_a3_0)) + (portRef I0 (instanceRef N_256_i)) + )) + (net N_253 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a3_2)) + (portRef I0 (instanceRef N_253_i)) + )) + (net N_254 (joined + (portRef O (instanceRef cpu_est_2_i_i_i_a3_3)) + (portRef I0 (instanceRef N_254_i)) + )) + (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__n)) + )) + (net N_250 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a3_1)) + (portRef I0 (instanceRef N_250_i)) + )) + (net (rename pos_clk_un9_clk_000_pe "pos_clk.un9_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) + (net N_364 (joined + (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_126_0_a2)) + (portRef I1 (instanceRef RESET_OUT_2_0_0_a3_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_0)) + (portRef I0 (instanceRef N_364_i)) + )) + (net N_21 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef I0 (instanceRef N_21_i)) + )) + (net N_171 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__n)) + )) + (net N_345 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1)) + (portRef I0 (instanceRef N_345_i)) + )) + (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__n)) + )) + (net N_283 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) + (portRef I0 (instanceRef N_283_i)) )) (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined (portRef O (instanceRef pos_clk_un6_bgack_000_0_i)) (portRef I1 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) + (net N_370 (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_a2)) + (portRef I0 (instanceRef N_370_i)) + )) + (net N_259 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3)) + (portRef I1 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__r)) + )) (net N_10 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) (portRef I0 (instanceRef N_10_i)) )) + (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined + (portRef O (instanceRef pos_clk_un9_bg_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) + (net N_4 (joined + (portRef O (instanceRef DSACK1_INT_0_p)) + (portRef I0 (instanceRef N_4_i)) + )) + (net N_114 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a3)) + (portRef I0 (instanceRef N_114_i)) + )) + (net N_278 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) + )) (net N_5 (joined (portRef O (instanceRef AS_000_INT_0_p)) (portRef I0 (instanceRef N_5_i)) )) - (net N_293 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a2_i_i)) + (net N_113 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_a3)) + (portRef I0 (instanceRef N_113_i)) + )) + (net N_279 (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_0_i)) (portRef I1 (instanceRef AS_000_INT_0_m)) (portRef I0 (instanceRef AS_000_INT_0_r)) )) @@ -2008,12 +1899,13 @@ (portRef O (instanceRef DS_000_ENABLE_0_p)) (portRef I0 (instanceRef DS_000_ENABLE_1)) )) - (net un1_SM_AMIGA_5 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_i)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a2)) + (net N_115 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_a3)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef N_115_i)) )) - (net DS_000_ENABLE_1_sqmuxa_1 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a2)) + (net N_63 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_0_i)) (portRef I1 (instanceRef DS_000_ENABLE_0_m)) (portRef I0 (instanceRef DS_000_ENABLE_0_r)) )) @@ -2022,11 +1914,11 @@ (portRef I0 (instanceRef N_7_i)) )) (net (rename pos_clk_un3_as_030_d0 "pos_clk.un3_as_030_d0") (joined - (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) - (net N_290 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_i)) + (net N_67 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_i)) (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) @@ -2034,177 +1926,167 @@ (portRef O (instanceRef RW_000_INT_0_p)) (portRef I0 (instanceRef N_18_i)) )) - (net DS_000_ENABLE_1_sqmuxa (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a2)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) )) - (net N_232 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2)) - (portRef I0 (instanceRef N_232_i)) - )) - (net N_194 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_o2_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2)) - )) - (net N_233 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_0)) - (portRef I0 (instanceRef N_233_i)) - )) - (net N_275 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) - (portRef I0 (instanceRef N_275_i)) - )) - (net N_153 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) - )) - (net N_191 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) - )) - (net N_334 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_6)) - (portRef I0 (instanceRef N_334_i)) - )) - (net N_146 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_1_0)) - )) - (net N_345 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) - (portRef I0 (instanceRef N_345_i)) - )) - (net N_346 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_a2)) - (portRef I0 (instanceRef N_346_i)) - )) - (net N_163 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_6)) + (net un1_SM_AMIGA_0_sqmuxa_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) )) (net N_22 (joined - (portRef O (instanceRef VMA_INT_0_p)) + (portRef O (instanceRef A0_DMA_0_p)) (portRef I0 (instanceRef N_22_i)) )) - (net (rename pos_clk_un4_clk_000_pe "pos_clk.un4_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) + (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined + (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3)) + (portRef I0 (instanceRef A0_DMA_0_n)) )) - (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) + (net N_363 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_a2)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_1)) )) - (net N_235 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a2_1)) - (portRef I0 (instanceRef N_235_i)) + (net N_26 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef I0 (instanceRef N_26_i)) )) - (net N_284 (joined - (portRef O (instanceRef un5_e_i_i_a2)) - (portRef I0 (instanceRef N_284_i)) + (net N_157 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + (portRef I0 (instanceRef N_157_i)) + (portRef I1 (instanceRef un22_berr_0_a2_0_a3)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a3_1)) )) - (net N_190 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + (net N_260 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_a3)) + (portRef I0 (instanceRef N_260_i)) )) - (net N_337 (joined - (portRef O (instanceRef RESET_OUT_2_0_i_a2)) - (portRef I0 (instanceRef N_337_i)) - )) - (net N_195 (joined - (portRef O (instanceRef RESET_OUT_2_0_i_o2_i)) - (portRef I0 (instanceRef RESET_OUT_2_0_i_a2)) - )) - (net N_340 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2_3)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2)) - (portRef I0 (instanceRef N_340_i)) - )) - (net N_231 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0)) - (portRef I0 (instanceRef N_231_i)) - )) - (net N_230 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2)) - (portRef I0 (instanceRef N_230_i)) - )) - (net N_280 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2)) - (portRef I0 (instanceRef N_280_i)) - )) - (net N_166 (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_3)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) - )) - (net N_141 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_i)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a2)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_0)) - )) - (net N_226 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_0)) - (portRef I0 (instanceRef N_226_i)) - )) - (net N_357 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I0 (instanceRef N_357_i)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_1)) + (net un22_berr_1 (joined + (portRef O (instanceRef un22_berr_0_a2_0_a3_1)) + (portRef I0 (instanceRef un22_berr_0_a2_0_a3_1_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a3)) )) (net N_219 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2_2)) + (portRef O (instanceRef RST_DLY_e2_i_0_a3_0)) (portRef I0 (instanceRef N_219_i)) )) - (net N_217 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2_0)) - (portRef I0 (instanceRef N_217_i)) - )) - (net N_221 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a2_0)) - (portRef I0 (instanceRef N_221_i)) + (net N_139 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_o2_i)) + (portRef I0 (instanceRef RST_DLY_e0_i_a3)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a3)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_0)) )) (net N_220 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a2)) + (portRef O (instanceRef RST_DLY_e2_i_0_a3_1)) (portRef I0 (instanceRef N_220_i)) )) + (net N_222 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_a3)) + (portRef I0 (instanceRef N_222_i)) + )) (net N_223 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (portRef O (instanceRef RST_DLY_e1_i_0_a3_0)) (portRef I0 (instanceRef N_223_i)) )) - (net N_343 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) - (portRef I0 (instanceRef N_343_i)) + (net N_368 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a2_0)) + (portRef I0 (instanceRef RST_DLY_e0_i_a3_0)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_0)) )) - (net N_192 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) - )) - (net N_164 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) - )) - (net N_291 (joined - (portRef O (instanceRef cpu_est_2_i_0_i_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__m)) - )) - (net N_315 (joined - (portRef O (instanceRef cpu_est_2_i_0_i_a2_3)) - (portRef I0 (instanceRef N_315_i)) - )) - (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) - )) - (net N_254 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I0 (instanceRef N_254_i)) + (net N_257 (joined + (portRef O (instanceRef cpu_est_0_i_i_a3_0)) + (portRef I0 (instanceRef N_257_i)) )) (net N_258 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) - (portRef I1 (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_r)) + (portRef O (instanceRef cpu_est_0_i_i_a3_0_0)) + (portRef I0 (instanceRef N_258_i)) + )) + (net N_312 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a2)) + (portRef I0 (instanceRef N_312_i)) + )) + (net N_143 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_a3_1)) + )) + (net N_332 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_0_6)) + (portRef I0 (instanceRef N_332_i)) + )) + (net N_332_4 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_3_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_0_1_6)) + )) + (net N_246 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_0)) + (portRef I0 (instanceRef N_246_i)) + )) + (net N_180 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_o2_1_i_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_0)) + )) + (net N_320 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_o2_0_i_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_1_0)) + )) + (net N_244 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_1_0)) + (portRef I0 (instanceRef N_244_i)) + )) + (net N_334 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_0)) + (portRef I0 (instanceRef N_334_i)) + )) + (net N_335 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_0_0)) + (portRef I0 (instanceRef N_335_i)) + )) + (net N_159 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_o2_2_i_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_o2)) + )) + (net N_156 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a3)) + )) + (net N_357 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) + (portRef I0 (instanceRef N_357_i)) + )) + (net N_353 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_a2)) + (portRef I0 (instanceRef N_353_i)) + )) + (net N_140 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_0_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_a2)) + )) + (net N_270 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3)) + (portRef I0 (instanceRef N_270_i)) + )) + (net N_281 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0_0_i)) + (portRef I0 (instanceRef RW_000_DMA_0_n)) + )) + (net N_131 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3)) + (portRef I0 (instanceRef N_131_i)) + )) + (net N_132 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3)) + (portRef I0 (instanceRef N_132_i)) )) (net N_29 (joined (portRef O (instanceRef IPL_030_0_2__p)) @@ -2214,30 +2096,25 @@ (portRef O (instanceRef IPL_030_0_1__p)) (portRef I0 (instanceRef N_28_i)) )) - (net N_27 (joined - (portRef O (instanceRef IPL_030_0_0__p)) - (portRef I0 (instanceRef N_27_i)) - )) - (net N_4 (joined - (portRef O (instanceRef DSACK1_INT_0_p)) - (portRef I0 (instanceRef N_4_i)) - )) (net N_17 (joined (portRef O (instanceRef LDS_000_INT_0_p)) (portRef I0 (instanceRef N_17_i)) )) - (net N_21 (joined + (net N_19 (joined + (portRef O (instanceRef RW_000_DMA_0_p)) + (portRef I0 (instanceRef N_19_i)) + )) + (net N_23 (joined (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef I0 (instanceRef N_21_i)) + (portRef I0 (instanceRef N_23_i)) )) - (net N_26 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef I0 (instanceRef N_26_i)) + (net N_24 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef I0 (instanceRef N_24_i)) )) - (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined - (portRef O (instanceRef pos_clk_un9_bg_030_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) + (net N_25 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (portRef I0 (instanceRef N_25_i)) )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) @@ -2247,328 +2124,285 @@ (portRef O (instanceRef un21_fpu_cs_i)) (portRef I0 (instanceRef FPU_CS)) )) - (net N_275_i (joined - (portRef O (instanceRef N_275_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DSACK1_INT_0_m)) - )) - (net (rename CLK_000_N_SYNC_i_12 "CLK_000_N_SYNC_i[12]") (joined - (portRef O (instanceRef CLK_000_N_SYNC_i_12)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_2)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a2_0_1)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_0)) - )) - (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined - (portRef O (instanceRef RST_DLY_i_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2)) - )) - (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined - (portRef O (instanceRef RST_DLY_i_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_1)) - )) - (net BERR_i (joined - (portRef O (instanceRef I_252)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_1_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_1_0)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef un5_e_i_i_o2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_2)) - )) - (net nEXP_SPACE_i (joined - (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef un13_ciin_i_0)) - (portRef I1 (instanceRef un1_as_030_i_a2_i_o2)) - )) - (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined - (portRef O (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a2_0_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_1_1)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef un5_e_i_i_a2)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_2_3)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_1_1_1)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_1)) - (portRef I1 (instanceRef cpu_est_2_i_0_i_o2_3)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_1)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_2_3)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_2)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_o2_2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_0)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_2_0)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_1_1)) - (portRef I1 (instanceRef un5_e_i_i_a2_0)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) - )) - (net RESET_OUT_i (joined - (portRef O (instanceRef RESET_OUT_i)) - (portRef I1 (instanceRef RESET_OUT_2_0_i_a2)) - (portRef OE (instanceRef RESET)) - )) (net BGACK_030_INT_i (joined (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef un1_rw_i_a2_i)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_0_o3)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0)) + (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3)) + (portRef I0 (instanceRef un1_as_030_0_o3)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_0)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3)) (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) - (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0)) - (portRef I0 (instanceRef un2_rw_i_a2)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2)) - (portRef I0 (instanceRef un1_as_030_i_a2_i_o2)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_1)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_1)) )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_4)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_1_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) - )) - (net (rename CLK_000_P_SYNC_i_10 "CLK_000_P_SYNC_i[10]") (joined - (portRef O (instanceRef CLK_000_P_SYNC_i_10)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__n)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) - (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a2_i)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_1)) - )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_o2_1)) - )) - (net (rename CLK_000_D_i_11 "CLK_000_D_i[11]") (joined - (portRef O (instanceRef CLK_000_D_i_11)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_1_0)) - )) - (net RW_i (joined - (portRef O (instanceRef I_253)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a2)) - )) - (net DS_000_ENABLE_1_sqmuxa_i (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_1)) - )) - (net LDS_000_INT_i (joined - (portRef O (instanceRef LDS_000_INT_i)) - (portRef I1 (instanceRef un4_lds_000)) + (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef un1_amiga_bus_enable_low)) )) (net UDS_000_INT_i (joined (portRef O (instanceRef UDS_000_INT_i)) (portRef I1 (instanceRef un4_uds_000)) )) + (net LDS_000_INT_i (joined + (portRef O (instanceRef LDS_000_INT_i)) + (portRef I1 (instanceRef un4_lds_000)) + )) + (net N_131_i (joined + (portRef O (instanceRef N_131_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + )) + (net N_132_i (joined + (portRef O (instanceRef N_132_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_226)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_a3)) + (portRef I1 (instanceRef un14_amiga_bus_data_dir_i_0_0)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + )) + (net (rename A_i_1 "A_i[1]") (joined + (portRef O (instanceRef A_i_1)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3)) + )) + (net (rename CLK_000_D_i_11 "CLK_000_D_i[11]") (joined + (portRef O (instanceRef CLK_000_D_i_11)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_o2_2_0)) + )) + (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined + (portRef O (instanceRef CLK_000_D_i_1)) + (portRef I1 (instanceRef N_88_i_0_o2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_1_0)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_1_0)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_1_i_a2_3_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_1_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_1_0)) + )) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_0_6)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_o2_0_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_a3_2)) + )) + (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined + (portRef O (instanceRef RST_DLY_i_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_a3_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1_1)) + )) + (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined + (portRef O (instanceRef RST_DLY_i_1)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1)) + )) + (net N_364_i_0 (joined + (portRef O (instanceRef N_364_i)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_126_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a2)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I1 (instanceRef cpu_est_2_i_i_i_o2_3)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_1)) + (portRef I1 (instanceRef cpu_est_0_i_i_a3_0)) + )) + (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined + (portRef O (instanceRef RST_DLY_i_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a3)) + )) (net AS_030_i (joined - (portRef O (instanceRef I_254)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_1)) - (portRef I0 (instanceRef AS_030_D0_0_i_a2)) + (portRef O (instanceRef I_227)) (portRef I1 (instanceRef un4_as_000)) + (portRef I0 (instanceRef AS_030_D0_0_i_a2_i)) + (portRef I0 (instanceRef un22_berr_0_a2_0_a3_1)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3_1)) + )) + (net N_157_i (joined + (portRef O (instanceRef N_157_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_1)) + )) + (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined + (portRef O (instanceRef A_DECODE_i_16)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) + )) + (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined + (portRef O (instanceRef A_DECODE_i_18)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + )) + (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined + (portRef O (instanceRef A_DECODE_i_19)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + )) + (net N_113_i (joined + (portRef O (instanceRef N_113_i)) + (portRef I0 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + )) + (net N_114_i (joined + (portRef O (instanceRef N_114_i)) + (portRef I0 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) )) (net AS_000_INT_i (joined (portRef O (instanceRef AS_000_INT_i)) (portRef I0 (instanceRef un4_as_000)) )) - (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined - (portRef O (instanceRef A_DECODE_i_19)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_3)) - )) - (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined - (portRef O (instanceRef A_DECODE_i_18)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_3)) - )) - (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined - (portRef O (instanceRef A_DECODE_i_16)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_2)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_255)) - (portRef I0 (instanceRef un6_ds_030)) - (portRef I1 (instanceRef un6_as_030_0_a2)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) - )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_1_0)) - )) - (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) - )) - (net CLK_030_i (joined - (portRef O (instanceRef CLK_030_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i)) - (portRef I1 (instanceRef CLK_030_H_2_i_o2)) - )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3_3)) - )) - (net (rename CLK_000_D_i_10 "CLK_000_D_i[10]") (joined - (portRef O (instanceRef CLK_000_D_i_10)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) - )) - (net RW_000_i (joined - (portRef O (instanceRef I_256)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) - (portRef I1 (instanceRef un14_amiga_bus_data_dir_i_0)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) - )) - (net (rename A_i_1 "A_i[1]") (joined - (portRef O (instanceRef A_i_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) - )) - (net CLK_030_H_i (joined - (portRef O (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef CLK_030_H_2_i_a2)) - )) - (net AS_000_DMA_i (joined - (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef un6_as_030_0_a2)) - (portRef I0 (instanceRef CLK_030_H_2_i_o2)) - )) - (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined - (portRef O (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a2_0)) - )) - (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined - (portRef O (instanceRef CLK_000_D_i_1)) - (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) - )) - (net AS_030_D0_i (joined - (portRef O (instanceRef AS_030_D0_i)) - (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2)) - (portRef I1 (instanceRef un10_ciin_0_a2_5)) + (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined + (portRef O (instanceRef SIZE_DMA_i_1)) + (portRef I1 (instanceRef un4_size)) )) (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined (portRef O (instanceRef SIZE_DMA_i_0)) (portRef I1 (instanceRef un3_size)) )) - (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined - (portRef O (instanceRef SIZE_DMA_i_1)) - (portRef I1 (instanceRef un4_size)) + (net RESET_OUT_i (joined + (portRef O (instanceRef RESET_OUT_i)) + (portRef OE (instanceRef RESET)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef un5_e_0_i_o2)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_1_1_1)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I1 (instanceRef cpu_est_2_i_i_i_a3_3)) + (portRef I1 (instanceRef un5_e_0_i_a3_0)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_2_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a2_0_2)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef un5_e_0_i_o2_0)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_1_1)) + )) + (net CLK_030_i (joined + (portRef O (instanceRef CLK_030_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I1 (instanceRef CLK_030_H_2_i_0_o2)) + )) + (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined + (portRef O (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef N_170_i_0_o2_i_o2)) + )) + (net (rename CLK_000_D_i_10 "CLK_000_D_i[10]") (joined + (portRef O (instanceRef CLK_000_D_i_10)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef un6_as_030_0_a2_0_a3)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_o2)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_229)) + (portRef I0 (instanceRef un6_ds_030)) + (portRef I1 (instanceRef un6_as_030_0_a2_0_a3)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) + )) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_a3)) + )) + (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined + (portRef O (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_a3)) + )) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3)) + (portRef I1 (instanceRef un10_ciin_0_a3_5)) )) (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined - (portRef O (instanceRef I_257)) - (portRef I0 (instanceRef un10_ciin_0_a2_4)) + (portRef O (instanceRef I_230)) + (portRef I0 (instanceRef un10_ciin_0_a3_4)) )) (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined - (portRef O (instanceRef I_258)) - (portRef I1 (instanceRef un10_ciin_0_a2_4)) + (portRef O (instanceRef I_231)) + (portRef I1 (instanceRef un10_ciin_0_a3_4)) )) (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined - (portRef O (instanceRef I_259)) - (portRef I0 (instanceRef un10_ciin_0_a2_3)) + (portRef O (instanceRef I_232)) + (portRef I0 (instanceRef un10_ciin_0_a3_3)) )) (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined - (portRef O (instanceRef I_260)) - (portRef I1 (instanceRef un10_ciin_0_a2_3)) + (portRef O (instanceRef I_233)) + (portRef I1 (instanceRef un10_ciin_0_a3_3)) )) (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined - (portRef O (instanceRef I_261)) - (portRef I0 (instanceRef un10_ciin_0_a2_2)) + (portRef O (instanceRef I_234)) + (portRef I0 (instanceRef un10_ciin_0_a3_2)) )) (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined - (portRef O (instanceRef I_262)) - (portRef I1 (instanceRef un10_ciin_0_a2_2)) + (portRef O (instanceRef I_235)) + (portRef I1 (instanceRef un10_ciin_0_a3_2)) )) (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined - (portRef O (instanceRef I_263)) - (portRef I0 (instanceRef un10_ciin_0_a2_1)) + (portRef O (instanceRef I_236)) + (portRef I0 (instanceRef un10_ciin_0_a3_1)) )) (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined - (portRef O (instanceRef I_264)) - (portRef I1 (instanceRef un10_ciin_0_a2_1)) + (portRef O (instanceRef I_237)) + (portRef I1 (instanceRef un10_ciin_0_a3_1)) )) - (net N_212_i (joined - (portRef O (instanceRef N_212_i)) - (portRef I1 (instanceRef G_137_1)) + (net N_241_i (joined + (portRef O (instanceRef N_241_i)) + (portRef I1 (instanceRef G_119_1)) )) - (net N_213_i (joined - (portRef O (instanceRef N_213_i)) - (portRef I1 (instanceRef G_137)) + (net N_242_i (joined + (portRef O (instanceRef N_242_i)) + (portRef I1 (instanceRef G_119)) )) - (net N_214_i (joined - (portRef O (instanceRef N_214_i)) - (portRef I0 (instanceRef G_137_1)) + (net N_243_i (joined + (portRef O (instanceRef N_243_i)) + (portRef I0 (instanceRef G_119_1)) )) (net CLK_OUT_PRE_50_i (joined (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net N_323_i (joined - (portRef O (instanceRef N_323_i)) - (portRef D (instanceRef AS_030_D0)) - )) - (net N_321_i (joined - (portRef O (instanceRef N_321_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - )) - (net N_322_i (joined - (portRef O (instanceRef N_322_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - )) (net un6_ds_030_i (joined (portRef O (instanceRef un6_ds_030_i)) (portRef I0 (instanceRef DS_030)) @@ -2593,13 +2427,9 @@ (portRef O (instanceRef un4_uds_000_i)) (portRef I0 (instanceRef UDS_000)) )) - (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) - (portRef I0 (instanceRef un1_amiga_bus_enable_low)) - )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef I_254)) + (portRef I0 (instanceRef I_227)) )) (net AS_030 (joined (portRef AS_030) @@ -2607,8 +2437,8 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_o2)) - (portRef I0 (instanceRef I_255)) + (portRef I0 (instanceRef I_229)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_a2)) )) (net AS_000 (joined (portRef AS_000) @@ -2616,8 +2446,8 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_256)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + (portRef I0 (instanceRef I_226)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -2629,8 +2459,8 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_a2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_a2)) + (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3)) (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined @@ -2639,7 +2469,7 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_a2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_a2)) (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined @@ -2664,7 +2494,7 @@ )) (net (rename AHIGH_c_24 "AHIGH_c[24]") (joined (portRef O (instanceRef AHIGH_24)) - (portRef I0 (instanceRef I_263)) + (portRef I0 (instanceRef I_236)) )) (net (rename AHIGH_24 "AHIGH[24]") (joined (portRef IO (instanceRef AHIGH_24)) @@ -2672,7 +2502,7 @@ )) (net (rename AHIGH_c_25 "AHIGH_c[25]") (joined (portRef O (instanceRef AHIGH_25)) - (portRef I0 (instanceRef I_264)) + (portRef I0 (instanceRef I_237)) )) (net (rename AHIGH_25 "AHIGH[25]") (joined (portRef IO (instanceRef AHIGH_25)) @@ -2680,7 +2510,7 @@ )) (net (rename AHIGH_c_26 "AHIGH_c[26]") (joined (portRef O (instanceRef AHIGH_26)) - (portRef I0 (instanceRef I_261)) + (portRef I0 (instanceRef I_234)) )) (net (rename AHIGH_26 "AHIGH[26]") (joined (portRef IO (instanceRef AHIGH_26)) @@ -2688,7 +2518,7 @@ )) (net (rename AHIGH_c_27 "AHIGH_c[27]") (joined (portRef O (instanceRef AHIGH_27)) - (portRef I0 (instanceRef I_262)) + (portRef I0 (instanceRef I_235)) )) (net (rename AHIGH_27 "AHIGH[27]") (joined (portRef IO (instanceRef AHIGH_27)) @@ -2696,7 +2526,7 @@ )) (net (rename AHIGH_c_28 "AHIGH_c[28]") (joined (portRef O (instanceRef AHIGH_28)) - (portRef I0 (instanceRef I_259)) + (portRef I0 (instanceRef I_232)) )) (net (rename AHIGH_28 "AHIGH[28]") (joined (portRef IO (instanceRef AHIGH_28)) @@ -2704,7 +2534,7 @@ )) (net (rename AHIGH_c_29 "AHIGH_c[29]") (joined (portRef O (instanceRef AHIGH_29)) - (portRef I0 (instanceRef I_260)) + (portRef I0 (instanceRef I_233)) )) (net (rename AHIGH_29 "AHIGH[29]") (joined (portRef IO (instanceRef AHIGH_29)) @@ -2712,7 +2542,7 @@ )) (net (rename AHIGH_c_30 "AHIGH_c[30]") (joined (portRef O (instanceRef AHIGH_30)) - (portRef I0 (instanceRef I_257)) + (portRef I0 (instanceRef I_230)) )) (net (rename AHIGH_30 "AHIGH[30]") (joined (portRef IO (instanceRef AHIGH_30)) @@ -2720,7 +2550,7 @@ )) (net (rename AHIGH_c_31 "AHIGH_c[31]") (joined (portRef O (instanceRef AHIGH_31)) - (portRef I0 (instanceRef I_258)) + (portRef I0 (instanceRef I_231)) )) (net (rename AHIGH_31 "AHIGH[31]") (joined (portRef (member ahigh 0)) @@ -2834,7 +2664,7 @@ )) (net (rename A_DECODE_c_17 "A_DECODE_c[17]") (joined (portRef O (instanceRef A_DECODE_17)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_2)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) )) (net (rename A_DECODE_17 "A_DECODE[17]") (joined (portRef (member a_decode 6)) @@ -2858,7 +2688,7 @@ )) (net (rename A_DECODE_c_20 "A_DECODE_c[20]") (joined (portRef O (instanceRef A_DECODE_20)) - (portRef I0 (instanceRef un10_ciin_0_a2_6)) + (portRef I0 (instanceRef un10_ciin_0_a3_6)) )) (net (rename A_DECODE_20 "A_DECODE[20]") (joined (portRef (member a_decode 3)) @@ -2866,7 +2696,7 @@ )) (net (rename A_DECODE_c_21 "A_DECODE_c[21]") (joined (portRef O (instanceRef A_DECODE_21)) - (portRef I1 (instanceRef un10_ciin_0_a2_6)) + (portRef I1 (instanceRef un10_ciin_0_a3_6)) )) (net (rename A_DECODE_21 "A_DECODE[21]") (joined (portRef (member a_decode 2)) @@ -2874,7 +2704,7 @@ )) (net (rename A_DECODE_c_22 "A_DECODE_c[22]") (joined (portRef O (instanceRef A_DECODE_22)) - (portRef I1 (instanceRef un10_ciin_0_a2_11)) + (portRef I1 (instanceRef un10_ciin_0_a3_11)) )) (net (rename A_DECODE_22 "A_DECODE[22]") (joined (portRef (member a_decode 1)) @@ -2882,7 +2712,7 @@ )) (net (rename A_DECODE_c_23 "A_DECODE_c[23]") (joined (portRef O (instanceRef A_DECODE_23)) - (portRef I0 (instanceRef un10_ciin_0_a2_5)) + (portRef I0 (instanceRef un10_ciin_0_a3_5)) )) (net (rename A_DECODE_23 "A_DECODE[23]") (joined (portRef (member a_decode 0)) @@ -2899,8 +2729,8 @@ )) (net (rename A_c_1 "A_c[1]") (joined (portRef O (instanceRef A_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) (portRef I0 (instanceRef A_i_1)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3)) )) (net (rename A_1 "A[1]") (joined (portRef (member a 0)) @@ -2908,10 +2738,10 @@ )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) - (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_o2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef I0 (instanceRef nEXP_SPACE_c_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_2_0)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_1)) (portRef OE (instanceRef DSACK1)) )) (net nEXP_SPACE (joined @@ -2920,9 +2750,8 @@ )) (net BERR_c (joined (portRef O (instanceRef BERR)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) - (portRef I1 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2)) - (portRef I0 (instanceRef I_252)) + (portRef I1 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a2_1)) )) (net BERR (joined (portRef BERR) @@ -2952,9 +2781,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) (portRef I0 (instanceRef pos_clk_un6_bgack_000_0)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I1 (instanceRef un22_berr_0_a2_0_a3_1)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -2962,7 +2791,7 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0_a3)) (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0)) (portRef I0 (instanceRef CLK_030_i)) )) @@ -2972,7 +2801,6 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0)) (portRef D (instanceRef CLK_000_D_0)) )) (net CLK_000 (joined @@ -3004,31 +2832,6 @@ (portRef CLK (instanceRef CLK_000_D_10)) (portRef CLK (instanceRef CLK_000_D_11)) (portRef CLK (instanceRef CLK_000_D_12)) - (portRef CLK (instanceRef CLK_000_NE_D0)) - (portRef CLK (instanceRef CLK_000_N_SYNC_0)) - (portRef CLK (instanceRef CLK_000_N_SYNC_1)) - (portRef CLK (instanceRef CLK_000_N_SYNC_2)) - (portRef CLK (instanceRef CLK_000_N_SYNC_3)) - (portRef CLK (instanceRef CLK_000_N_SYNC_4)) - (portRef CLK (instanceRef CLK_000_N_SYNC_5)) - (portRef CLK (instanceRef CLK_000_N_SYNC_6)) - (portRef CLK (instanceRef CLK_000_N_SYNC_7)) - (portRef CLK (instanceRef CLK_000_N_SYNC_8)) - (portRef CLK (instanceRef CLK_000_N_SYNC_9)) - (portRef CLK (instanceRef CLK_000_N_SYNC_10)) - (portRef CLK (instanceRef CLK_000_N_SYNC_11)) - (portRef CLK (instanceRef CLK_000_N_SYNC_12)) - (portRef CLK (instanceRef CLK_000_P_SYNC_0)) - (portRef CLK (instanceRef CLK_000_P_SYNC_1)) - (portRef CLK (instanceRef CLK_000_P_SYNC_2)) - (portRef CLK (instanceRef CLK_000_P_SYNC_3)) - (portRef CLK (instanceRef CLK_000_P_SYNC_4)) - (portRef CLK (instanceRef CLK_000_P_SYNC_5)) - (portRef CLK (instanceRef CLK_000_P_SYNC_6)) - (portRef CLK (instanceRef CLK_000_P_SYNC_7)) - (portRef CLK (instanceRef CLK_000_P_SYNC_8)) - (portRef CLK (instanceRef CLK_000_P_SYNC_9)) - (portRef CLK (instanceRef CLK_000_P_SYNC_10)) (portRef CLK (instanceRef CLK_030_H)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE_50)) @@ -3094,7 +2897,7 @@ (net FPU_SENSE_c (joined (portRef O (instanceRef FPU_SENSE)) (portRef I0 (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un22_berr_0_a2_1)) + (portRef I1 (instanceRef un22_berr_0_a2_0_a3_1_0)) )) (net FPU_SENSE (joined (portRef FPU_SENSE) @@ -3130,7 +2933,7 @@ (net (rename IPL_c_0 "IPL_c[0]") (joined (portRef O (instanceRef IPL_0)) (portRef I0 (instanceRef IPL_030_0_0__m)) - (portRef I1 (instanceRef G_134)) + (portRef I1 (instanceRef G_116)) (portRef I0 (instanceRef IPL_c_i_0)) )) (net (rename IPL_0 "IPL[0]") (joined @@ -3139,8 +2942,8 @@ )) (net (rename IPL_c_1 "IPL_c[1]") (joined (portRef O (instanceRef IPL_1)) + (portRef I1 (instanceRef G_117)) (portRef I0 (instanceRef IPL_030_0_1__m)) - (portRef I1 (instanceRef G_135)) (portRef I0 (instanceRef IPL_c_i_1)) )) (net (rename IPL_1 "IPL[1]") (joined @@ -3150,7 +2953,7 @@ (net (rename IPL_c_2 "IPL_c[2]") (joined (portRef O (instanceRef IPL_2)) (portRef I0 (instanceRef IPL_030_0_2__m)) - (portRef I1 (instanceRef G_136)) + (portRef I1 (instanceRef G_118)) (portRef I0 (instanceRef IPL_c_i_2)) )) (net (rename IPL_2 "IPL[2]") (joined @@ -3191,51 +2994,47 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) + (portRef I1 (instanceRef IPL_030_1_0)) + (portRef I1 (instanceRef IPL_D0_0_0)) (portRef I1 (instanceRef DS_000_DMA_1)) (portRef I1 (instanceRef AS_000_DMA_1)) - (portRef I1 (instanceRef RW_000_DMA_2)) - (portRef I1 (instanceRef A0_DMA_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i)) - (portRef I1 (instanceRef AS_030_D0_0_i_a2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) - (portRef I1 (instanceRef BGACK_030_INT_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_0_o3)) + (portRef I1 (instanceRef RESET_OUT_2_0_0_a3)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + (portRef I1 (instanceRef VMA_INT_1)) (portRef I1 (instanceRef DTACK_D0_0)) + (portRef I1 (instanceRef BGACK_030_INT_1)) (portRef I0 (instanceRef VPA_D_0)) + (portRef I1 (instanceRef DSACK1_INT_1)) (portRef I1 (instanceRef AS_000_INT_1)) (portRef I1 (instanceRef AS_030_000_SYNC_1)) - (portRef I1 (instanceRef RW_000_INT_2)) - (portRef I1 (instanceRef DS_000_ENABLE_1)) - (portRef I1 (instanceRef VMA_INT_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_o2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) - (portRef I1 (instanceRef RESET_OUT_2_0_i)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2)) - (portRef I1 (instanceRef IPL_030_1_0)) - (portRef I1 (instanceRef IPL_030_1_1)) - (portRef I1 (instanceRef IPL_030_1_2)) + (portRef I1 (instanceRef RW_000_INT_1)) + (portRef I1 (instanceRef A0_DMA_1)) (portRef I1 (instanceRef BG_000_1)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef AS_030_D0_0_i_a2_i)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_o2)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_126_0)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) (portRef I1 (instanceRef UDS_000_INT_1)) + (portRef I1 (instanceRef RW_000_DMA_2)) (portRef I1 (instanceRef LDS_000_INT_1)) - (portRef I1 (instanceRef DSACK1_INT_1)) - (portRef I1 (instanceRef IPL_D0_0_0)) (portRef I1 (instanceRef IPL_D0_0_1)) (portRef I1 (instanceRef IPL_D0_0_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2_3)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_1)) + (portRef I1 (instanceRef IPL_030_1_1)) + (portRef I1 (instanceRef IPL_030_1_2)) (portRef I1 (instanceRef RST_DLY_e2_i_0_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2_2)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a2_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_2_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1)) - (portRef I1 (instanceRef RST_DLY_e0_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5)) - (portRef I1 (instanceRef CLK_030_H_2_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_1_2)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_2)) + (portRef I1 (instanceRef CLK_030_H_2_i_0_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_2_0)) + (portRef I1 (instanceRef RST_DLY_e0_i)) )) (net RST (joined (portRef RST) @@ -3247,7 +3046,7 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I0 (instanceRef I_253)) + (portRef I0 (instanceRef RW_c_i)) )) (net RW (joined (portRef IO (instanceRef RW)) @@ -3255,7 +3054,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -3263,7 +3062,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_1)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -3274,7 +3073,7 @@ (portRef AMIGA_ADDR_ENABLE) )) (net AMIGA_BUS_DATA_DIR_c (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) (net AMIGA_BUS_DATA_DIR (joined @@ -3293,34 +3092,38 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net BG_030_c_i (joined - (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef pos_clk_un9_bg_030)) + (net N_25_i (joined + (portRef O (instanceRef N_25_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) )) - (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_i)) - (portRef I1 (instanceRef pos_clk_un9_bg_030)) + (net N_34_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) )) - (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined - (portRef O (instanceRef pos_clk_un9_bg_030)) - (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) + (net N_24_i (joined + (portRef O (instanceRef N_24_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) )) - (net N_26_i (joined - (portRef O (instanceRef N_26_i)) - (portRef I0 (instanceRef BG_000_1)) + (net N_35_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) )) - (net N_33_0 (joined - (portRef O (instanceRef BG_000_1)) - (portRef I0 (instanceRef BG_000_1_i)) - )) - (net N_21_i (joined - (portRef O (instanceRef N_21_i)) + (net N_23_i (joined + (portRef O (instanceRef N_23_i)) (portRef I0 (instanceRef UDS_000_INT_1)) )) - (net N_38_0 (joined + (net N_36_0 (joined (portRef O (instanceRef UDS_000_INT_1)) (portRef I0 (instanceRef UDS_000_INT_1_i)) )) + (net N_19_i (joined + (portRef O (instanceRef N_19_i)) + (portRef I0 (instanceRef RW_000_DMA_2)) + )) + (net N_40_0 (joined + (portRef O (instanceRef RW_000_DMA_2)) + (portRef I0 (instanceRef RW_000_DMA_2_i)) + )) (net N_17_i (joined (portRef O (instanceRef N_17_i)) (portRef I0 (instanceRef LDS_000_INT_1)) @@ -3329,22 +3132,6 @@ (portRef O (instanceRef LDS_000_INT_1)) (portRef I0 (instanceRef LDS_000_INT_1_i)) )) - (net N_4_i (joined - (portRef O (instanceRef N_4_i)) - (portRef I0 (instanceRef DSACK1_INT_1)) - )) - (net N_48_0 (joined - (portRef O (instanceRef DSACK1_INT_1)) - (portRef I0 (instanceRef DSACK1_INT_1_i)) - )) - (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined - (portRef O (instanceRef IPL_c_i_0)) - (portRef I0 (instanceRef IPL_D0_0_0)) - )) - (net N_51_0 (joined - (portRef O (instanceRef IPL_D0_0_0)) - (portRef I0 (instanceRef IPL_D0_0_i_0)) - )) (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined (portRef O (instanceRef IPL_c_i_1)) (portRef I0 (instanceRef IPL_D0_0_1)) @@ -3361,14 +3148,6 @@ (portRef O (instanceRef IPL_D0_0_2)) (portRef I0 (instanceRef IPL_D0_0_i_2)) )) - (net N_27_i (joined - (portRef O (instanceRef N_27_i)) - (portRef I0 (instanceRef IPL_030_1_0)) - )) - (net N_30_0 (joined - (portRef O (instanceRef IPL_030_1_0)) - (portRef I0 (instanceRef IPL_030_1_i_0)) - )) (net N_28_i (joined (portRef O (instanceRef N_28_i)) (portRef I0 (instanceRef IPL_030_1_1)) @@ -3397,353 +3176,267 @@ (portRef O (instanceRef pos_clk_un10_sm_amiga)) (portRef I0 (instanceRef LDS_000_INT_0_m)) )) - (net N_258_0 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) + (net N_332_i (joined + (portRef O (instanceRef N_332_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_6)) + )) + (net N_240_i (joined + (portRef O (instanceRef N_240_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_6)) + )) + (net N_315_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_6)) + )) + (net N_281_0 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0_0)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_0_i)) + )) + (net N_270_i (joined + (portRef O (instanceRef N_270_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0)) + )) + (net N_282_i (joined + (portRef O (instanceRef N_282_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_i)) + )) + (net RW_c_i (joined + (portRef O (instanceRef RW_c_i)) + (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_0)) + )) + (net N_140_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_0_i)) + )) + (net N_353_i (joined + (portRef O (instanceRef N_353_i)) + (portRef I1 (instanceRef un1_SM_AMIGA_1_i_a2_3_o2)) + )) + (net N_143_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_o2)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_o2_i)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_o2_0_0)) + )) + (net N_320_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_o2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_o2_0_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_3_0)) )) (net N_357_i (joined (portRef O (instanceRef N_357_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_2)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) )) - (net N_254_i (joined - (portRef O (instanceRef N_254_i)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_2)) + (net N_356_i (joined + (portRef O (instanceRef N_356_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) )) - (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2)) + (net N_156_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i)) )) - (net N_315_i (joined - (portRef O (instanceRef N_315_i)) - (portRef I1 (instanceRef cpu_est_2_i_0_i_3)) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_o2_2_0)) )) - (net N_291_0 (joined - (portRef O (instanceRef cpu_est_2_i_0_i_3)) - (portRef I0 (instanceRef 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(joined - (portRef O (instanceRef N_285_i)) - (portRef I1 (instanceRef un5_e_i_i)) - )) - (net N_292_0 (joined - (portRef O (instanceRef un5_e_i_i)) - (portRef I0 (instanceRef un5_e_i_i_i)) - )) - (net N_280_i (joined - (portRef O (instanceRef N_280_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_2)) - )) - (net N_277_i (joined - (portRef O (instanceRef N_277_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_2)) - )) - (net N_257_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_i_2)) - )) - (net N_235_i (joined - (portRef O (instanceRef N_235_i)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_1)) - )) - (net N_236_i (joined - (portRef O (instanceRef N_236_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_1)) - )) - (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1)) - )) - (net N_231_i (joined - (portRef O (instanceRef N_231_i)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0)) - )) - (net N_230_i (joined - (portRef O (instanceRef N_230_i)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0)) - )) - (net (rename pos_clk_un4_clk_000_pe_0 "pos_clk.un4_clk_000_pe_0") (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_i)) - )) - (net N_22_i (joined - (portRef O (instanceRef N_22_i)) - (portRef I0 (instanceRef VMA_INT_1)) - )) - (net N_37_0 (joined - (portRef O (instanceRef VMA_INT_1)) - (portRef I0 (instanceRef VMA_INT_1_i)) - )) - (net N_142_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_6)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net N_334_i (joined - (portRef O (instanceRef N_334_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_6)) - )) - (net N_335_i (joined - (portRef O (instanceRef N_335_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_2_6)) - )) - (net N_194_0 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_o2)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_o2_i)) - )) - (net N_191_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_5)) - )) - (net un1_SM_AMIGA_5_i (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2)) - (portRef I0 (instanceRef DS_000_ENABLE_0_n)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_i)) - )) - (net N_346_i (joined - (portRef O (instanceRef N_346_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_2)) - )) - (net N_163_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_1)) - )) - (net N_345_i (joined - (portRef O (instanceRef N_345_i)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) - )) - (net N_344_i (joined - (portRef O (instanceRef N_344_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) - )) - (net N_153_0 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i)) - )) - (net (rename pos_clk_un3_as_030_d0_i "pos_clk.un3_as_030_d0_i") (joined - (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a2)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_0)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a2_i)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) - (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2_i)) - )) - (net N_293_0 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a2_i_i)) - )) - (net N_233_i (joined - (portRef O (instanceRef N_233_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i)) - )) - (net N_232_i (joined - (portRef O (instanceRef N_232_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i)) - )) - (net N_290_0 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_i)) - )) - (net VPA_c_i (joined - (portRef O (instanceRef VPA_c_i)) - (portRef I1 (instanceRef VPA_D_0)) - )) - (net N_54_0 (joined - (portRef O (instanceRef VPA_D_0)) - (portRef I0 (instanceRef VPA_D_0_i)) + (net N_48_0 (joined + (portRef O (instanceRef DSACK1_INT_1)) + (portRef I0 (instanceRef DSACK1_INT_1_i)) )) (net N_5_i (joined (portRef O (instanceRef N_5_i)) @@ -3763,11 +3456,39 @@ )) (net N_18_i (joined (portRef O (instanceRef N_18_i)) - (portRef I0 (instanceRef RW_000_INT_2)) + (portRef I0 (instanceRef RW_000_INT_1)) )) (net N_41_0 (joined - (portRef O (instanceRef RW_000_INT_2)) - (portRef I0 (instanceRef RW_000_INT_2_i)) + (portRef O (instanceRef RW_000_INT_1)) + (portRef I0 (instanceRef RW_000_INT_1_i)) + )) + (net N_22_i (joined + (portRef O (instanceRef N_22_i)) + (portRef I0 (instanceRef A0_DMA_1)) + )) + (net N_37_0 (joined + (portRef O (instanceRef A0_DMA_1)) + (portRef I0 (instanceRef A0_DMA_1_i)) + )) + (net N_26_i (joined + (portRef O (instanceRef N_26_i)) + (portRef I0 (instanceRef BG_000_1)) + )) + (net N_33_0 (joined + (portRef O (instanceRef BG_000_1)) + (portRef I0 (instanceRef BG_000_1_i)) + )) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef pos_clk_un9_bg_030)) + )) + (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i)) + (portRef I1 (instanceRef pos_clk_un9_bg_030)) + )) + (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined + (portRef O (instanceRef pos_clk_un9_bg_030)) + (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) )) (net N_10_i (joined (portRef O (instanceRef N_10_i)) @@ -3777,6 +3498,73 @@ (portRef O (instanceRef BGACK_030_INT_1)) (portRef I0 (instanceRef BGACK_030_INT_1_i)) )) + (net VPA_c_i (joined + (portRef O (instanceRef VPA_c_i)) + (portRef I1 (instanceRef VPA_D_0)) + )) + (net N_54_0 (joined + (portRef O (instanceRef VPA_D_0)) + (portRef I0 (instanceRef VPA_D_0_i)) + )) + (net un3_as_030_i (joined + (portRef O (instanceRef un3_as_030_0)) + (portRef OE (instanceRef AHIGH_24)) + (portRef OE (instanceRef AHIGH_25)) + (portRef OE (instanceRef AHIGH_26)) + (portRef OE (instanceRef AHIGH_27)) + (portRef OE (instanceRef AHIGH_28)) + (portRef OE (instanceRef AHIGH_29)) + (portRef OE (instanceRef AHIGH_30)) + (portRef OE (instanceRef AHIGH_31)) + (portRef OE (instanceRef AS_030)) + (portRef OE (instanceRef A_0)) + (portRef OE (instanceRef DS_030)) + )) + (net N_370_i (joined + (portRef O (instanceRef N_370_i)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0)) + )) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_i)) + )) + (net N_283_i (joined + (portRef O (instanceRef N_283_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) + )) + (net N_345_i (joined + (portRef O (instanceRef N_345_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + )) + (net UDS_000_c_i (joined + (portRef O (instanceRef UDS_000_c_i)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) + )) + (net LDS_000_c_i (joined + (portRef O (instanceRef LDS_000_c_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) + )) + (net N_171_i (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) + )) + (net N_21_i (joined + (portRef O (instanceRef N_21_i)) + (portRef I0 (instanceRef VMA_INT_1)) + )) + (net N_38_0 (joined + (portRef O (instanceRef VMA_INT_1)) + (portRef I0 (instanceRef VMA_INT_1_i)) + )) (net DTACK_c_i (joined (portRef O (instanceRef DTACK_c_i)) (portRef I0 (instanceRef DTACK_D0_0)) @@ -3785,246 +3573,326 @@ (portRef O (instanceRef DTACK_D0_0)) (portRef I0 (instanceRef DTACK_D0_0_i)) )) - (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_i)) + (net N_249_i (joined + (portRef O (instanceRef N_249_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0)) )) - (net N_137_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) + (net N_248_i (joined + (portRef O (instanceRef N_248_i)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0)) )) - (net N_184_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_2)) + (net (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) )) - (net N_349_i (joined - (portRef O (instanceRef N_349_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) + (net N_250_i (joined + (portRef O (instanceRef N_250_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_1)) )) - (net N_185_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + (net N_251_i (joined + (portRef O (instanceRef N_251_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_1)) )) - (net N_187_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) + (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1)) )) - (net N_203_i (joined - (portRef O (instanceRef pos_clk_un4_bgack_000_i_o2)) - (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_o2_i)) + (net N_253_i (joined + (portRef O (instanceRef N_253_i)) + (portRef I0 (instanceRef cpu_est_2_i_i_i_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_2)) )) - (net N_324_i (joined - (portRef O (instanceRef N_324_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) + (net N_369_i (joined + (portRef O (instanceRef N_369_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_2)) )) - (net N_130_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0)) - (portRef D (instanceRef SM_AMIGA_0)) + (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2)) )) - (net N_199_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) + (net N_254_i (joined + (portRef O (instanceRef N_254_i)) + (portRef I1 (instanceRef cpu_est_2_i_i_i_3)) )) - (net N_197_0 (joined - (portRef O (instanceRef CLK_030_H_2_i_o2)) - (portRef I0 (instanceRef CLK_030_H_2_i_o2_i)) + (net N_316_i (joined + (portRef O (instanceRef cpu_est_2_i_i_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__n)) )) - (net N_196_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) + (net N_256_i (joined + (portRef O (instanceRef N_256_i)) + (portRef I1 (instanceRef un5_e_0_i)) )) - (net LDS_000_c_i (joined - (portRef O (instanceRef LDS_000_c_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + (net N_255_i (joined + (portRef O (instanceRef N_255_i)) + (portRef I0 (instanceRef un5_e_0_i)) )) - (net UDS_000_c_i (joined - (portRef O (instanceRef UDS_000_c_i)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + (net N_317_i (joined + (portRef O (instanceRef un5_e_0_i)) + (portRef I0 (instanceRef E)) )) - (net N_181_i (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) + (net N_267_i (joined + (portRef O (instanceRef N_267_i)) + (portRef I1 (instanceRef RESET_OUT_2_0_0)) )) - (net N_347_i (joined - (portRef O (instanceRef N_347_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + (net N_266_i (joined + (portRef O (instanceRef N_266_i)) + (portRef I0 (instanceRef RESET_OUT_2_0_0)) )) - (net N_348_i (joined - (portRef O (instanceRef N_348_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + (net N_57_0 (joined + (portRef O (instanceRef RESET_OUT_2_0_0)) + (portRef I0 (instanceRef RESET_OUT_2_0_0_i)) )) - (net N_178_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) + (net N_151_0 (joined + (portRef O (instanceRef un5_e_0_i_o2)) + (portRef I0 (instanceRef un5_e_0_i_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a2_1_2)) + )) + (net N_321_i (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) + )) + (net N_158_i (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_1_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) )) (net VMA_INT_i (joined (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a2_2_2)) )) - (net (rename pos_clk_un5_bgack_030_int_d_i "pos_clk.un5_bgack_030_int_d_i") (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_o2_1)) + (net N_361_i (joined + (portRef O (instanceRef N_361_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_o2_2)) )) - (net (rename pos_clk_un23_bgack_030_int_i_1_0 "pos_clk.un23_bgack_030_int_i_1_0") (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_i)) - (portRef I1 (instanceRef CLK_030_H_2_i)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i)) + (net N_362_i (joined + (portRef O (instanceRef N_362_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_o2_2)) + )) + (net N_169_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_o2_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_o2_i_2)) + )) + (net N_186_0 (joined + (portRef O (instanceRef un5_e_0_i_o2_0)) + (portRef I0 (instanceRef un5_e_0_i_o2_0_i)) + )) + (net N_195_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_o2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_o2_i_3)) + )) + (net N_196_0 (joined + (portRef O (instanceRef cpu_est_2_i_i_i_o2_3)) + (portRef I0 (instanceRef cpu_est_2_i_i_i_o2_i_3)) + )) + (net N_60_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + (portRef D (instanceRef CYCLE_DMA_0)) + )) + (net N_263_i (joined + (portRef O (instanceRef N_263_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + )) + (net N_262_i (joined + (portRef O (instanceRef N_262_i)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + )) + (net N_323_0 (joined + (portRef O (instanceRef CLK_030_H_2_i_0_o2)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_o2_i)) + )) + (net N_101_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_0_o3)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_0_o3_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) + )) + (net N_366_i (joined + (portRef O (instanceRef N_366_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o3)) + )) + (net N_182_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o3)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + )) + (net (rename pos_clk_un23_bgack_030_int_i_0_0 "pos_clk.un23_bgack_030_int_i_0_0") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_0)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_0)) + )) + (net N_310_i (joined + (portRef O (instanceRef N_310_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_o2_0)) + )) + (net N_359_i (joined + (portRef O (instanceRef N_359_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_o2_0)) + )) + (net N_144_0 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_o2_i_0)) )) (net CLK_OUT_PRE_D_i (joined (portRef O (instanceRef CLK_OUT_PRE_D_i)) (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0)) )) - (net N_148_0 (joined + (net N_142_0 (joined (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0)) (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0_i)) )) + (net N_311_i (joined + (portRef O (instanceRef N_311_i)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_2)) + )) + (net N_319_i (joined + (portRef O (instanceRef N_88_i_0_o2)) + (portRef I1 (instanceRef G_111)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_a2)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_a3)) + (portRef I1 (instanceRef un1_SM_AMIGA_1_i_a2_3_a2)) + (portRef I0 (instanceRef N_88_i_0_o2_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) + )) + (net N_93_i (joined + (portRef O (instanceRef un1_rw_i_a2_i)) + (portRef OE (instanceRef RW)) + )) + (net N_272_0 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0_i)) + )) + (net N_290_i (joined + (portRef O (instanceRef N_290_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + )) + (net N_273_0 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0_i)) + )) + (net N_346_i (joined + (portRef O (instanceRef N_346_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0)) + )) + (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_0)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_0_i)) + )) + (net N_268_i (joined + (portRef O (instanceRef N_268_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_0_4)) + )) + (net N_269_i (joined + (portRef O (instanceRef N_269_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_0_4)) + )) + (net (rename SM_AMIGA_nss_0_3 "SM_AMIGA_nss_0[3]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_0_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_0_i_4)) + )) (net N_341_i (joined (portRef O (instanceRef N_341_i)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2)) + (portRef I0 (instanceRef CLK_030_H_2_i_0_1)) )) - (net N_338_i (joined - (portRef O (instanceRef N_338_i)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_1)) + (net N_276_i (joined + (portRef O (instanceRef CLK_030_H_2_i_0)) + (portRef D (instanceRef CLK_030_H)) )) - (net N_339_i (joined - (portRef O (instanceRef N_339_i)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_1)) + (net N_277_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) + (portRef D (instanceRef CYCLE_DMA_1)) + )) + (net N_238_i (joined + (portRef O (instanceRef N_238_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_5)) )) (net N_239_i (joined - (portRef O (instanceRef RST_DLY_e0_i_0)) - (portRef D (instanceRef RST_DLY_0)) + (portRef O (instanceRef N_239_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_5)) )) - (net N_336_i (joined - (portRef O (instanceRef N_336_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_1)) + (net (rename SM_AMIGA_nss_0_2 "SM_AMIGA_nss_0[2]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_i_5)) )) - (net N_122_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_3_i_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_i)) + (net N_235_i (joined + (portRef O (instanceRef N_235_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_3)) )) - (net N_211_i (joined - (portRef O (instanceRef N_211_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (net N_236_i (joined + (portRef O (instanceRef N_236_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_3)) )) - (net N_332_i (joined - (portRef O (instanceRef N_332_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (net (rename SM_AMIGA_nss_0_4 "SM_AMIGA_nss_0[4]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_i_3)) )) - (net N_132_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) - (portRef D (instanceRef SM_AMIGA_1)) + (net N_234_i (joined + (portRef O (instanceRef N_234_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_2)) + )) + (net (rename SM_AMIGA_nss_0_5 "SM_AMIGA_nss_0[5]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_i_2)) + )) + (net N_231_i (joined + (portRef O (instanceRef N_231_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_1)) + )) + (net N_232_i (joined + (portRef O (instanceRef N_232_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_1)) + )) + (net (rename SM_AMIGA_nss_0_6 "SM_AMIGA_nss_0[6]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_i_1)) + )) + (net N_230_i (joined + (portRef O (instanceRef N_230_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_0)) + )) + (net (rename SM_AMIGA_nss_0_7 "SM_AMIGA_nss_0[7]") (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_i_0)) + )) + (net N_226_i (joined + (portRef O (instanceRef N_226_i)) + (portRef I0 (instanceRef RST_DLY_e0_i_1)) )) (net N_331_i (joined (portRef O (instanceRef N_331_i)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + (portRef I1 (instanceRef RST_DLY_e0_i_1)) )) - (net N_120_0 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + (net N_314_i (joined + (portRef O (instanceRef RST_DLY_e0_i)) + (portRef D (instanceRef RST_DLY_0)) )) - (net N_330_i (joined - (portRef O (instanceRef N_330_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (net un1_as_000_i (joined + (portRef O (instanceRef un1_as_000_0)) + (portRef OE (instanceRef AS_000)) + (portRef OE (instanceRef LDS_000)) + (portRef OE (instanceRef RW_000)) + (portRef OE (instanceRef UDS_000)) )) - (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + (net N_27_i (joined + (portRef O (instanceRef N_27_i)) + (portRef I0 (instanceRef IPL_030_1_0)) )) - (net N_329_i (joined - (portRef O (instanceRef N_329_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (net N_30_0 (joined + (portRef O (instanceRef IPL_030_1_0)) + (portRef I0 (instanceRef IPL_030_1_i_0)) )) - (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined + (portRef O (instanceRef IPL_c_i_0)) + (portRef I0 (instanceRef IPL_D0_0_0)) )) - (net N_328_i (joined - (portRef O (instanceRef N_328_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - )) - (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) - )) - (net N_325_i (joined - (portRef O (instanceRef N_325_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) - )) - (net N_327_i (joined - (portRef O (instanceRef N_327_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) - )) - (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) - )) - (net N_320_i (joined - (portRef O (instanceRef N_320_i)) - (portRef I0 (instanceRef CLK_030_H_2_i_1)) - )) - (net N_106_i (joined - (portRef O (instanceRef CLK_030_H_2_i)) - (portRef D (instanceRef CLK_030_H)) - )) - (net N_103_i (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) - (portRef D (instanceRef CYCLE_DMA_1)) - )) - (net N_92_i (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i)) - (portRef D (instanceRef CYCLE_DMA_0)) - )) - (net N_298_0 (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i)) - )) - (net N_295_0 (joined - (portRef O (instanceRef un14_amiga_bus_data_dir_i_0)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_i)) - )) - (net N_294_0 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i)) - )) - (net N_319_i (joined - (portRef O (instanceRef N_319_i)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0[0]") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0)) - )) - (net N_206_i (joined - (portRef O (instanceRef N_206_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) - )) - (net N_283_i (joined - (portRef O (instanceRef N_283_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) - )) - (net N_140_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5)) - (portRef D (instanceRef SM_AMIGA_5)) - )) - (net N_281_i (joined - (portRef O (instanceRef N_281_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - )) - (net N_282_i (joined - (portRef O (instanceRef N_282_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - )) - (net N_138_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef D (instanceRef SM_AMIGA_4)) + (net N_51_0 (joined + (portRef O (instanceRef IPL_D0_0_0)) + (portRef I0 (instanceRef IPL_D0_0_i_0)) )) (net N_3_i (joined (portRef O (instanceRef N_3_i)) @@ -4042,345 +3910,269 @@ (portRef O (instanceRef AS_000_DMA_1)) (portRef I0 (instanceRef AS_000_DMA_1_i)) )) - (net N_19_i (joined - (portRef O (instanceRef N_19_i)) - (portRef I0 (instanceRef RW_000_DMA_2)) + (net (rename SM_AMIGA_nss_i_0_1_0 "SM_AMIGA_nss_i_0_1[0]") (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_4_0)) )) - (net N_40_0 (joined - (portRef O (instanceRef RW_000_DMA_2)) - (portRef I0 (instanceRef RW_000_DMA_2_i)) + (net (rename SM_AMIGA_nss_i_0_2_0 "SM_AMIGA_nss_i_0_2[0]") (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_4_0)) )) - (net N_20_i (joined - (portRef O (instanceRef N_20_i)) - (portRef I0 (instanceRef A0_DMA_1)) + (net (rename SM_AMIGA_nss_i_0_3_0 "SM_AMIGA_nss_i_0_3[0]") (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_5_0)) )) - (net N_39_0 (joined - (portRef O (instanceRef A0_DMA_1)) - (portRef I0 (instanceRef A0_DMA_1_i)) + (net (rename SM_AMIGA_nss_i_0_4_0 "SM_AMIGA_nss_i_0_4[0]") (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_4_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_0)) )) - (net N_24_i (joined - (portRef O (instanceRef N_24_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - )) - (net N_35_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) - )) - (net N_25_i (joined - (portRef O (instanceRef N_25_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - )) - (net N_34_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) - )) - (net N_194_0_1 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_o2)) - )) - (net N_237_i_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e2_i_0)) - )) - (net N_237_i_2 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0)) - )) - (net N_238_i_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0)) - )) - (net N_238_i_2 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e1_i_0)) - )) - (net N_144_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_3_0)) - )) - (net N_144_i_2 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_3_0)) - )) - (net N_144_i_3 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - )) - (net N_136_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - )) - (net N_136_i_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - )) - (net N_176_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) - )) - (net N_146_0_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) + (net (rename SM_AMIGA_nss_i_0_5_0 "SM_AMIGA_nss_i_0_5[0]") (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_5_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_0)) )) (net (rename pos_clk_un10_sm_amiga_i_1 "pos_clk.un10_sm_amiga_i_1") (joined (portRef O (instanceRef pos_clk_un10_sm_amiga_1)) (portRef I0 (instanceRef pos_clk_un10_sm_amiga)) )) (net un10_ciin_1 (joined - (portRef O (instanceRef un10_ciin_0_a2_1)) - (portRef I0 (instanceRef un10_ciin_0_a2_7)) + (portRef O (instanceRef un10_ciin_0_a3_1)) + (portRef I0 (instanceRef un10_ciin_0_a3_7)) )) (net un10_ciin_2 (joined - (portRef O (instanceRef un10_ciin_0_a2_2)) - (portRef I1 (instanceRef un10_ciin_0_a2_7)) + (portRef O (instanceRef un10_ciin_0_a3_2)) + (portRef I1 (instanceRef un10_ciin_0_a3_7)) )) (net un10_ciin_3 (joined - (portRef O (instanceRef un10_ciin_0_a2_3)) - (portRef I0 (instanceRef un10_ciin_0_a2_8)) + (portRef O (instanceRef un10_ciin_0_a3_3)) + (portRef I0 (instanceRef un10_ciin_0_a3_8)) )) (net un10_ciin_4 (joined - (portRef O (instanceRef un10_ciin_0_a2_4)) - (portRef I1 (instanceRef un10_ciin_0_a2_8)) + (portRef O (instanceRef un10_ciin_0_a3_4)) + (portRef I1 (instanceRef un10_ciin_0_a3_8)) )) (net un10_ciin_5 (joined - (portRef O (instanceRef un10_ciin_0_a2_5)) - (portRef I0 (instanceRef un10_ciin_0_a2_9)) + (portRef O (instanceRef un10_ciin_0_a3_5)) + (portRef I0 (instanceRef un10_ciin_0_a3_9)) )) (net un10_ciin_6 (joined - (portRef O (instanceRef un10_ciin_0_a2_6)) - (portRef I1 (instanceRef un10_ciin_0_a2_9)) + (portRef O (instanceRef un10_ciin_0_a3_6)) + (portRef I1 (instanceRef un10_ciin_0_a3_9)) )) (net un10_ciin_7 (joined - (portRef O (instanceRef un10_ciin_0_a2_7)) - (portRef I0 (instanceRef un10_ciin_0_a2_10)) + (portRef O (instanceRef un10_ciin_0_a3_7)) + (portRef I0 (instanceRef un10_ciin_0_a3_10)) )) (net un10_ciin_8 (joined - (portRef O (instanceRef un10_ciin_0_a2_8)) - (portRef I1 (instanceRef un10_ciin_0_a2_10)) + (portRef O (instanceRef un10_ciin_0_a3_8)) + (portRef I1 (instanceRef un10_ciin_0_a3_10)) )) (net un10_ciin_9 (joined - (portRef O (instanceRef un10_ciin_0_a2_9)) - (portRef I0 (instanceRef un10_ciin_0_a2_11)) + (portRef O (instanceRef un10_ciin_0_a3_9)) + (portRef I0 (instanceRef un10_ciin_0_a3_11)) )) (net un10_ciin_10 (joined - (portRef O (instanceRef un10_ciin_0_a2_10)) - (portRef I0 (instanceRef un10_ciin_0_a2)) + (portRef O (instanceRef un10_ciin_0_a3_10)) + (portRef I0 (instanceRef un10_ciin_0_a3)) )) (net un10_ciin_11 (joined - (portRef O (instanceRef un10_ciin_0_a2_11)) - (portRef I1 (instanceRef un10_ciin_0_a2)) + (portRef O (instanceRef un10_ciin_0_a3_11)) + (portRef I1 (instanceRef un10_ciin_0_a3)) )) - (net N_347_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (net (rename pos_clk_un23_bgack_030_int_i_0_0_1 "pos_clk.un23_bgack_030_int_i_0_0_1") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_1)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3)) )) - (net N_347_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (net (rename pos_clk_un23_bgack_030_int_i_0_0_2 "pos_clk.un23_bgack_030_int_i_0_0_2") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3_2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2_o3)) )) - (net (rename pos_clk_un23_bgack_030_int_i_1_0_1 "pos_clk.un23_bgack_030_int_i_1_0_1") (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_1)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2)) + (net N_60_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) )) - (net (rename pos_clk_un23_bgack_030_int_i_1_0_2 "pos_clk.un23_bgack_030_int_i_1_0_2") (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2)) + (net N_60_i_2 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0)) + )) + (net N_248_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) + )) + (net N_248_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3)) + )) + (net N_249_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) + )) + (net N_249_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a3_0)) + )) + (net N_361_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a2_2)) + )) + (net N_361_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a2_2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_0_0_a2_2)) + )) + (net N_157_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + )) + (net N_157_2 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + )) + (net N_157_3 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + )) + (net N_157_4 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + )) + (net N_260_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_a3_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_a3)) + )) + (net N_260_2 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_a3_2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i_a3)) )) (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_1_0)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2)) + (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3)) )) (net un22_berr_1_0 (joined - (portRef O (instanceRef un22_berr_0_a2_1)) - (portRef I0 (instanceRef un22_berr_0_a2)) + (portRef O (instanceRef un22_berr_0_a2_0_a3_1_0)) + (portRef I0 (instanceRef un22_berr_0_a2_0_a3)) )) - (net N_366_1 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_1)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_4)) + (net N_275_i_1 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_0)) )) - (net N_366_2 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_2)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_4)) + (net N_275_i_2 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_2)) + (portRef I1 (instanceRef RST_DLY_e1_i_0)) )) - (net N_366_3 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_3)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1)) + (net N_274_i_1 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_1)) + (portRef I0 (instanceRef RST_DLY_e2_i_0)) )) - (net N_366_4 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_4)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1)) + (net N_274_i_2 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0)) )) - (net un1_SM_AMIGA_5_i_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2)) + (net N_115_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_a3_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_1_i_a2_3_a3)) )) - (net un1_SM_AMIGA_5_i_2 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_2)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2)) + (net N_115_2 (joined + (portRef O (instanceRef un1_SM_AMIGA_1_i_a2_3_a3_2)) + (portRef I1 (instanceRef un1_SM_AMIGA_1_i_a2_3_a3)) )) - (net N_142_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_6)) + (net N_332_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_0_6)) )) - (net N_142_i_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_2_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_6)) + (net N_246_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_4_0)) )) - (net N_339_1 (joined - (portRef O (instanceRef RST_DLY_e0_i_0_a2_0_1)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a2_0)) + (net N_246_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_4_0)) )) - (net N_280_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2)) + (net N_246_3 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_3_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_0)) )) - (net N_280_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2)) + (net N_246_4 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_4_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_0)) )) - (net N_231_1 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_1)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0)) + (net N_332_4_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_0)) )) - (net N_231_2 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0)) + (net N_332_4_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_0_0_a3_2_5_0)) )) - (net N_230_1 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_3)) + (net N_273_0_1 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_0_1)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_0)) )) - (net N_230_2 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_2)) - (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_3)) + (net N_276_i_1 (joined + (portRef O (instanceRef CLK_030_H_2_i_0_1)) + (portRef I0 (instanceRef CLK_030_H_2_i_0)) )) - (net N_230_3 (joined - (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_3)) - (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2)) + (net N_277_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0)) )) - (net N_226_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_3_0)) + (net N_314_i_1 (joined + (portRef O (instanceRef RST_DLY_e0_i_1)) + (portRef I0 (instanceRef RST_DLY_e0_i)) )) - (net N_226_2 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_3_0)) + (net N_356_1 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) )) - (net N_226_3 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_0)) + (net N_282_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0)) )) - (net N_239_i_1 (joined - (portRef O (instanceRef RST_DLY_e0_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e0_i_0)) - )) - (net N_122_0_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_3_i_0_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0)) - )) - (net N_132_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) - )) - (net N_120_0_1 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i)) - )) - (net N_106_i_1 (joined - (portRef O (instanceRef CLK_030_H_2_i_1)) - (portRef I0 (instanceRef CLK_030_H_2_i)) - )) - (net N_103_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) - )) - (net N_92_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) - )) - (net N_140_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5)) - )) - (net N_138_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4)) - )) - (net N_344_1 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0_1)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) + (net N_251_1 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_1_1_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_1_1)) )) (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3)) )) - (net N_327_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + (net N_240_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_6)) )) - (net N_319_1 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0)) + (net N_238_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a3_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a3_5)) )) - (net N_285_1 (joined - (portRef O (instanceRef un5_e_i_i_a2_0_1)) - (portRef I0 (instanceRef un5_e_i_i_a2_0)) + (net N_233_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a3_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a3_2)) )) - (net N_277_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_2)) - )) - (net N_236_1 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_1_1_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_1_1)) - )) - (net N_228_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) - )) - (net N_225_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_0)) + (net N_231_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_0_0_a3_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_0_0_a3_1)) )) (net N_224_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) + (portRef O (instanceRef RST_DLY_e1_i_0_a3_1_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_1)) )) - (net N_222_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a2_1_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_1)) - )) - (net N_215_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a2_1)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2)) + (net N_218_1 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a3_1_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a3)) )) (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined - (portRef O (instanceRef G_137_1)) - (portRef I0 (instanceRef G_137)) + (portRef O (instanceRef G_119_1)) + (portRef I0 (instanceRef G_119)) )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) - )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) )) (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined (portRef O (instanceRef LDS_000_INT_0_r)) @@ -4394,17 +4186,53 @@ (portRef O (instanceRef LDS_000_INT_0_n)) (portRef I1 (instanceRef LDS_000_INT_0_p)) )) - (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined - (portRef O (instanceRef DSACK1_INT_0_r)) - (portRef I1 (instanceRef DSACK1_INT_0_n)) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) )) - (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined - (portRef O (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_p)) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) )) - (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined - (portRef O (instanceRef DSACK1_INT_0_n)) - (portRef I1 (instanceRef DSACK1_INT_0_p)) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) )) (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined (portRef O (instanceRef IPL_030_0_2__r)) @@ -4418,125 +4246,17 @@ (portRef O (instanceRef IPL_030_0_2__n)) (portRef I1 (instanceRef IPL_030_0_2__p)) )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un3") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un1") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) - )) - (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined - (portRef O (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_3__n)) - )) - (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined - (portRef O (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined - (portRef O (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un3 "SM_AMIGA_srsts_i_0_m2_1_.un3") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un1 "SM_AMIGA_srsts_i_0_m2_1_.un1") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un0 "SM_AMIGA_srsts_i_0_m2_1_.un0") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) - )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) - )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) - )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) - )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_0_m2_5__un3 "SM_AMIGA_srsts_i_0_0_m2_5_.un3") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__n)) - )) - (net (rename SM_AMIGA_srsts_i_0_0_m2_5__un1 "SM_AMIGA_srsts_i_0_0_m2_5_.un1") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_0_m2_5__un0 "SM_AMIGA_srsts_i_0_0_m2_5_.un0") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__n)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__p)) - )) - (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined - (portRef O (instanceRef RW_000_INT_0_r)) - (portRef I1 (instanceRef RW_000_INT_0_n)) - )) - (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined - (portRef O (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_p)) - )) - (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined - (portRef O (instanceRef RW_000_INT_0_n)) - (portRef I1 (instanceRef RW_000_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) - )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un0") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) )) (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined (portRef O (instanceRef AS_000_INT_0_r)) @@ -4574,41 +4294,53 @@ (portRef O (instanceRef AS_030_000_SYNC_0_n)) (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un3") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un1") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un0") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined + (portRef O (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_n)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined + (portRef O (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined + (portRef O (instanceRef A0_DMA_0_n)) + (portRef I1 (instanceRef A0_DMA_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + )) + (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_1__n)) + (portRef I1 (instanceRef SIZE_DMA_0_1__p)) )) (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined (portRef O (instanceRef SIZE_DMA_0_0__r)) @@ -4622,17 +4354,89 @@ (portRef O (instanceRef SIZE_DMA_0_0__n)) (portRef I1 (instanceRef SIZE_DMA_0_0__p)) )) - (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_1__r)) - (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) )) - (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) )) - (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_1__n)) - (portRef I1 (instanceRef SIZE_DMA_0_1__p)) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined + (portRef O (instanceRef DSACK1_INT_0_r)) + (portRef I1 (instanceRef DSACK1_INT_0_n)) + )) + (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined + (portRef O (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined + (portRef O (instanceRef DSACK1_INT_0_n)) + (portRef I1 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined + (portRef O (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) + )) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) + )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) + )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) )) (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined (portRef O (instanceRef DS_000_DMA_0_r)) @@ -4658,30 +4462,6 @@ (portRef O (instanceRef AS_000_DMA_0_n)) (portRef I1 (instanceRef AS_000_DMA_0_p)) )) - (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined - (portRef O (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_n)) - )) - (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined - (portRef O (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_p)) - )) - (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined - (portRef O (instanceRef RW_000_DMA_0_n)) - (portRef I1 (instanceRef RW_000_DMA_0_p)) - )) - (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined - (portRef O (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef A0_DMA_0_n)) - )) - (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined - (portRef O (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_p)) - )) - (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined - (portRef O (instanceRef A0_DMA_0_n)) - (portRef I1 (instanceRef A0_DMA_0_p)) - )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index b871b07..d7c403b 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {7139371391} onehot +fsm_encoding {7130381301} onehot -fsm_state_encoding {7139371391} idle_p {00000000} +fsm_state_encoding {7130381301} idle_p {00000000} -fsm_state_encoding {7139371391} idle_n {00000011} +fsm_state_encoding {7130381301} idle_n {00000011} -fsm_state_encoding {7139371391} as_set_p {00000101} +fsm_state_encoding {7130381301} as_set_p {00000101} -fsm_state_encoding {7139371391} as_set_n {00001001} +fsm_state_encoding {7130381301} as_set_n {00001001} -fsm_state_encoding {7139371391} sample_dtack_p {00010001} +fsm_state_encoding {7130381301} sample_dtack_p {00010001} -fsm_state_encoding {7139371391} data_fetch_n {00100001} +fsm_state_encoding {7130381301} data_fetch_n {00100001} -fsm_state_encoding {7139371391} data_fetch_p {01000001} +fsm_state_encoding {7130381301} data_fetch_p {01000001} -fsm_state_encoding {7139371391} end_cycle_n {10000001} +fsm_state_encoding {7130381301} end_cycle_n {10000001} -fsm_registers {7139371391} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} +fsm_registers {7130381301} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index e3c6872..2c7c9c7 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Fri Aug 19 00:20:27 2016 +#-- Written on Fri Aug 19 00:39:21 2016 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index fca5b83..7238bae 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -187,7 +187,7 @@ NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\F\8OCklM\0#\0oHE\kL\jnUd j0\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj +POR3DMCNk#b_0.Cb_l0HC3RjjUcn(;6j RNP3CODNbMk_C#0b04_HRlCj43j66n.jN; POR3F0M#N_M0sRCo"qAtBji_dQj_hua_)4 R"N; P#R30Dl0H0#0HRlCjj3jjjjj;P @@ -202,8 +202,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#(RU( -.;N3PR#_$MD HMC8sHRc"{gggjU-A.dBBc-6cA6j-g(7 -.qnqn.Bcn} ("N; +RNP3M#$_lMkOsEN#dRUc +j;N3PR#_$MD HMC8sHRd"{BB nn-cwq4g(-.c4A4-gqU6-g4( 7.Ajj}UU"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -354,51 +354,43 @@ F@:@(64U:::6UcQ:BQBhRQ;Qh RNH3Ds0_HFsolMNCBR"Q"Qh;L oR4qr9N; LLR3HF0bsH08s;R4 -RoMk_M4qtvQqz_A1h_ q Ap_q7v_t]Q]9rj;M +RoMk_M4NolHNk_L#M_CNCLD_IDF;M NRN3#PMC_CV0_D#No46R.no; -MMRk4l_NH_oNL_k#CLMNDDC_F -I;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_MnNj#_d -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_Md#CHx;M +MMRkn#_N_jjd;M NRN3#PMC_CV0_D#No46R.no; -MMRkcH_#x +MMRkdH_#x C;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_Mck_8#j;jj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRckM_#D8_jjj;M +RoMk_Mc#CHx;M NRN3#PMC_CV0_D#No46R.no; -MMRkc#_N_jjj;M -NRN3#PMC_CV0_D#No46R.no; -MMRk4Oj_H;HM -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.kM4b_Vk#_O;M -NRN3#PMC_CV0_D#No46R.no; -MMRk.L._C;ss -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRnkM__8#j;dj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_;M -NRN3#PMC_CV0_D#No46R.no; -M_RhUN; +MMRkc8_k#j_jjN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;44 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_.N; +n;okMRMDc_8j#_j +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMk_McNj#_j +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMkjM4_HOHMN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4c -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_6N; +n;okMRM_.4V_bkO +#;N3MR#CNP_0MC_NVDoR#4.;6n +RoMk.M._sLCsN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4n -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_gN; +n;okMRM8n_#d_jjN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.j +n;ohMR_ +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_U RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_cN; +oR4h_4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.6 +n;ohMR_;4. +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_cN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;46 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_nN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.( RNM3P#NCC_M0D_VN4o#Rn.6;M oRdh_jN; M#R3N_PCM_C0VoDN#.4R6 @@ -412,11 +404,11 @@ oRdh_cN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;d6 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_(N; +oRdh_nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;dU +n;ohMR_;d( RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_gN; +oRdh_UN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;cj RNM3P#NCC_M0D_VN4o#Rn.6;M @@ -446,95 +438,69 @@ n;ohMR_;6c RNM3P#NCC_M0D_VN4o#Rn.6;M oR6h_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;6U +n;ohMR_;6( RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_jN; +oR6h_UN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(4 +n;ohMR_;(j RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_.N; +oR(h_4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(d +n;ohMR_;(. RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_cN; +oR(h_dN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(6 +n;ohMR_;(c RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_nN; +oR(h_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(( +n;ohMR_;(n RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_. -.;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_..N; +oR(h_(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_d.4;M +n;ohMR_4.c;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;4c +M_Rh.;c. RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_6 -(;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhg_..N; +oR.h_c +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh(_..N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_c.g;M +n;ohMR_d.(;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;g6 +M_Rhd;4d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_g -n;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhg_.UN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_Ud4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rhd;4g -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_. -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._d4N; +oRdh_4 +6;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh4_dgN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_.d.;M NRN3#PMC_CV0_D#No46R.no; M_Rhd;.d RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_. -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._d(N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_Ud.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rhd;.g -RNM3P#NCC_M0D_VN4o#Rn.6;M oRdh_d -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_d4N; +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhc_d4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_.dd;M +n;ohMR_ndc;M NRN3#PMC_CV0_D#No46R.no; -M_Rhd;dn +M_Rhd;66 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_d -U;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_dgN; +oRdh_6 +n;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh6_dgN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_4dc;M +n;ohMR_jdn;M NRN3#PMC_CV0_D#No46R.no; -M_Rhd;cc +M_Rhd;n6 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_c -(;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_dUN; -M#R3N_PCM_C0VoDN#.4R6 -n;oAMRtj_jj3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_Atj_jjjM3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oAMRtj_jj3_jk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR1z7_jjj_aQh_kj3M -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMz_71j_jjQ_hajM3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;ozMR7j1_jQj_hja_3jkM;M +oRdh_n +n;N3MR#CNP_0MC_NVDoR#4.;6n +RoM)jW_j7j_vjq_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MWR)_jjj_q7v_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoM)jW_j7j_vjq_3jkM;M NRN3#PMC_CV0_D#No46R.no; M7Rp1j_jjh_Qa3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M @@ -542,11 +508,29 @@ oR1p7_jjj_aQh_kj3M 4;N3MR#CNP_0MC_NVDoR#4.;6n RoMp_71j_jjQ_hajM3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;o7MR1iqB4h_Qa3_jk;Md +n;oQMRujp_djj__34_k;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRq71B_i4Q_hajM3k4N; +oRpQu_jjd_4j__M3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;o7MR1iqB4h_Qa3_jk;Mj +n;oQMRujp_djj__34_k;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRQqvtAq_z 1_hpqA v_7qQ_]tj]_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqp7 _v]q_Q_t]jM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMRvqQt_1Az_q hA_p 7_vq]]Qt_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqtvQqz_A1h_ q Ap_q7v_Wpm_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqtvQqz_A1h_ q Ap_q7v_Wpm_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqtvQqz_A1h_ q Ap_q7v_Wpm_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMz_71j_jjQ_hajM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;ozMR7j1_jQj_hja_34kM;M +NRN3#PMC_CV0_D#No46R.no; +M7Rz1j_jjh_Qa3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oRpQu_jjd_.j__M3kdN; M#R3N_PCM_C0VoDN#.4R6 @@ -554,17 +538,71 @@ n;oQMRujp_djj__3._k;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M oRpQu_jjd_.j__M3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__34_k;Md +n;okMRMq4_vqQt_1Az_q hA_p 7_vq]]Qt_lH_.__j3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MMRk4v_qQ_tqA_z1 Ahqp7 _v]q_Q_t]H._l_3j_k;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_4j__M3k4N; +oR4kM_QqvtAq_z 1_hpqA v_7qQ_]tH]___l.jk_3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqj1_jQj_hja_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +M1Rq_jjj_aQh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMqj1_jQj_hja_3jkM;M +NRN3#PMC_CV0_D#No46R.no; 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+R:fjjNRlOqERhR7.blsHR_q1j_jj7_vqj +3lSqm=1j_jjv_7q3_jk +M4S=Qjb_F#O\D 3.kMdo_LN_O j_djH_M0H +_jS=Q4h(_..s; +R:fjjNRlOqERhR7.blsHR_q1j_jj7_vqj +3MSqm=1j_jjv_7q3_jk +MjS=Qjqj1_j7j_vSq +Qq4=1j_jjv_7q3_jk;Md +fsRjR:jlENOR.m)RHbsl1Rq_jjj_q7v_bj3 +=Smh +_US=Qjqj1_j7j_vjq_34kM +4SQ=_q1j_jj7_vqjM3kjs; +R:fjjNRlOqERhR7.blsHR_q1j_jj7_vq4m +S=ch_6 +_jS=Qjh__UHQ +S41=)a;_O +fsRjR:jlENOR7qh.sRbH7lR1j_jjv_7q +_4Shm=__cgjQ +Sj_=hd +_HS=Q4)_1aOs; +R:fjjNRlOqERhR7.blsHRpQu__7jj9rj +=Smh4_6_Sj +QQj=uOp__jHr9Q +S41=)a;_O +fsRjR:jlENOR7qh.sRbHQlRujp_d4j_r +j9Shm=__djjQ +Sj_=h.H(_ +4SQ=a)1_ +O; @ diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 3869487..70cd89e 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Fri Aug 19 00:20:34 2016 +#Fri Aug 19 00:39:28 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -18,17 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000 -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000 +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2 -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2 +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -39,14 +39,14 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:34 2016 +# Fri Aug 19 00:39:28 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -56,7 +56,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:35 2016 +# Fri Aug 19 00:39:29 2016 ###########################################################] Map & Optimize Report @@ -65,7 +65,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -80,15 +80,15 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 88 uses +DFF 63 uses BI_DIR 18 uses BUFTH 4 uses IBUF 38 uses OBUF 15 uses -AND2 301 uses -INV 262 uses -OR2 27 uses -XOR2 7 uses +AND2 295 uses +INV 265 uses +OR2 25 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -98,6 +98,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:36 2016 +# Fri Aug 19 00:39:30 2016 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 31f997deaa5782daff22c29af71ab688b730478a..de3b191083b0806310125a3d22c8e3ebb17fd00c 100644 GIT binary patch delta 12973 zcmV;eGE&WyYNlwA8GnN9xM}UDbs>Yo){ds#lfcNbk{p#KBb~`S^2hh&wS({X$#K67msk;A0aIuNy>FmW(8zPy5ZOR z!FC1}(g5}iXwbfBzks?&LlOQ>4v<|(M80Ck)^&r&RW9|60%5q#A!N@nxr3q-2Vw%Hs!1tpw`d_ zrbFgX%K1iGrQwWp8U;!FHjMJh*#@Il0CxcSr$HQF+rZY2Uh8P+H~1fQxHSeGGx{jE z0I%6?)2m3h0DtG9;of!mOlh% zU+JHETBdoDW?7!Dvp23Sb8!qGglHxGV(9xc_~yv*`zTt7%}ugS=tT(Qj;Kc3v-5oZ z{JbA)m2z#jiWXVnI=#9oip|aB)9$mr0nq_}?Qh!3v+(EgS0G&Jg3?+bR)&}_4W`sR zicMGvdRiq~1#e5bq)rS;dv31o|NhLZz3a8Hf&A`yS|zd9_P)-}`^tp{4K5GSy zmTY4dPP~9^R@SQP**@#u3y=0=5iLf4ZAXs5n@z%1uwkCnU3Cfb>AfdNUpP)|XZ@Z9 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zXK)eZo@F{+z)`0|ULPf8((n$soD7n76!GoSKAEC4})tT#6bXA?Zu8mXGz1-QKq=M%beA>l-bIJAi*@I`6 z!*wNZ$6OM1Ib7krww@dAAH-zfaASV4gE&Ui157(i&hQO`)Mt4p&O!PxtKZS+aSp3o zhaVt5JIE92)_esPj?`e`NCg(IOqXkTLe-f;1)flwKt;BT6xml`)0gy}(iwr?QH*$jfJ`g=GMyP z=*VRApo*sH&m}!*8(jC5EJs-&+SmI~*6%c#^Mh87qQmGPmpLnSdr-rw-Y-%w(Bms` zzsR;Ic?V=%DbMx#S-U1diN{y!I{%Q49gMNi&a8e0IqME%JO4ib00960;&M>n0ssI2 P|NjF3d+C{@ceellnEgEv diff --git a/Logic/automake.err b/Logic/automake.err index f964a6e..e69de29 100644 --- a/Logic/automake.err +++ b/Logic/automake.err @@ -1 +0,0 @@ -Need not generate svf file according to the constraints, exit diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index 989fdb8..455dd42 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -54,614 +54,506 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 3 1 End Section Cross Reference File -Design 'BUS68030' created Fri Aug 19 00:20:41 2016 +Design 'BUS68030' created Fri Aug 19 00:39:35 2016 Type New Name Original Name // ---------------------------------------------------------------------- - Inst i_z4848 AS_030 - Inst i_z4949 AS_000 - Inst i_z4A4A RW_000 - Inst i_z4B4B DS_030 - Inst i_z4C4C UDS_000 - Inst i_z4D4D LDS_000 - Inst i_z5H5H BERR - Inst i_z6363 DSACK1 - Inst i_z6A6A RESET - Inst i_z6B6B RW - Inst i_z6I6I CIIN - Inst pos_clk_un9_bg_030 pos_clk.un9_bg_030 - Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_p AMIGA_BUS_ENABLE_DMA_HIGH_0.p - Inst CLK_000_N_SYNC_i_12_ CLK_000_N_SYNC_i[12] - Inst SM_AMIGA_srsts_i_0_1_1_ SM_AMIGA_srsts_i_0_1[1] - Inst RST_DLY_i_2_ RST_DLY_i[2] - Inst SM_AMIGA_srsts_i_0_1_ SM_AMIGA_srsts_i_0[1] - Inst pos_clk_un37_as_030_d0_0_i_a2_1 pos_clk.un37_as_030_d0_0_i_a2_1 - Inst SIZE_DMA_0_0__r SIZE_DMA_0_0_.r - Inst SIZE_DMA_0_0__m SIZE_DMA_0_0_.m - Inst SIZE_DMA_0_0__n SIZE_DMA_0_0_.n - Inst IPL_030_0_2__r IPL_030_0_2_.r - Inst SIZE_DMA_0_0__p SIZE_DMA_0_0_.p - Inst SM_AMIGA_srsts_i_0_1_6_ SM_AMIGA_srsts_i_0_1[6] - Inst IPL_030_0_2__m IPL_030_0_2_.m - Inst SIZE_DMA_0_1__r SIZE_DMA_0_1_.r - Inst SM_AMIGA_srsts_i_0_2_6_ SM_AMIGA_srsts_i_0_2[6] - Inst IPL_030_0_2__n IPL_030_0_2_.n - Inst SIZE_DMA_0_1__m SIZE_DMA_0_1_.m - Inst SM_AMIGA_srsts_i_0_6_ SM_AMIGA_srsts_i_0[6] - Inst IPL_030_0_2__p IPL_030_0_2_.p - Inst SIZE_DMA_0_1__n SIZE_DMA_0_1_.n - Inst IPL_030_0_1__r IPL_030_0_1_.r - Inst SIZE_DMA_0_1__p SIZE_DMA_0_1_.p - Inst IPL_030_0_1__m IPL_030_0_1_.m - Inst SM_AMIGA_srsts_i_i_0_a2_0_1_2_ SM_AMIGA_srsts_i_i_0_a2_0_1[2] - Inst IPL_030_0_1__n IPL_030_0_1_.n - Inst SM_AMIGA_srsts_i_i_0_a2_0_2_2_ SM_AMIGA_srsts_i_i_0_a2_0_2[2] - Inst IPL_030_0_1__p IPL_030_0_1_.p - Inst SM_AMIGA_srsts_i_i_0_a2_0_2_ SM_AMIGA_srsts_i_i_0_a2_0[2] - Inst IPL_030_0_0__r IPL_030_0_0_.r - Inst pos_clk_un4_clk_000_pe_0_0_a2_0_1 pos_clk.un4_clk_000_pe_0_0_a2_0_1 - Inst IPL_030_0_0__m IPL_030_0_0_.m - Inst pos_clk_un4_clk_000_pe_0_0_a2_0_2 pos_clk.un4_clk_000_pe_0_0_a2_0_2 - Inst IPL_030_0_0__n IPL_030_0_0_.n - Inst pos_clk_un4_clk_000_pe_0_0_a2_0 pos_clk.un4_clk_000_pe_0_0_a2_0 - Inst IPL_030_0_0__p IPL_030_0_0_.p - Inst cpu_est_0_3__r cpu_est_0_3_.r - Inst SM_AMIGA_srsts_i_0_0_a2_2_1_3_ SM_AMIGA_srsts_i_0_0_a2_2_1[3] - Inst cpu_est_0_3__m cpu_est_0_3_.m - Inst SM_AMIGA_srsts_i_0_0_a2_2_2_3_ SM_AMIGA_srsts_i_0_0_a2_2_2[3] - Inst cpu_est_0_3__n cpu_est_0_3_.n - Inst DS_000_DMA_0_r DS_000_DMA_0.r - Inst SM_AMIGA_srsts_i_0_0_a2_2_3_ SM_AMIGA_srsts_i_0_0_a2_2[3] - Inst cpu_est_0_3__p cpu_est_0_3_.p - Inst DS_000_DMA_0_m DS_000_DMA_0.m - Inst pos_clk_un23_bgack_030_int_i_0_o2_1 pos_clk.un23_bgack_030_int_i_0_o2_1 - Inst cpu_est_0_2__r cpu_est_0_2_.r - Inst DS_000_DMA_0_n DS_000_DMA_0.n - Inst pos_clk_un23_bgack_030_int_i_0_o2_2 pos_clk.un23_bgack_030_int_i_0_o2_2 - Inst cpu_est_0_2__m cpu_est_0_2_.m - Inst DS_000_DMA_0_p DS_000_DMA_0.p - Inst pos_clk_un23_bgack_030_int_i_0_o2 pos_clk.un23_bgack_030_int_i_0_o2 - Inst cpu_est_0_2__n cpu_est_0_2_.n + Inst i_z3F3F AS_030 + Inst i_z3G3G AS_000 + Inst i_z3H3H RW_000 + Inst i_z3I3I DS_030 + Inst i_z3J3J UDS_000 + Inst i_z3K3K LDS_000 + Inst i_z4O4O BERR + Inst i_z5A5A DSACK1 + Inst i_z5H5H RESET + Inst i_z5I5I RW + Inst i_z5P5P CIIN + Inst pos_clk_un37_as_030_d0_i_a2_1 pos_clk.un37_as_030_d0_i_a2_1 Inst AS_000_DMA_0_r AS_000_DMA_0.r - Inst cpu_est_0_2__p cpu_est_0_2_.p Inst AS_000_DMA_0_m AS_000_DMA_0.m - Inst IPL_030_1_2_ IPL_030_1[2] + Inst IPL_030_0_2__r IPL_030_0_2_.r Inst AS_000_DMA_0_n AS_000_DMA_0.n - Inst IPL_030_1_1_ IPL_030_1[1] + Inst IPL_030_0_2__m IPL_030_0_2_.m Inst AS_000_DMA_0_p AS_000_DMA_0.p + Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst IPL_030_0_2__p IPL_030_0_2_.p + Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] + Inst IPL_D0_0_0_ IPL_D0_0[0] Inst IPL_030_1_0_ IPL_030_1[0] - Inst RW_000_DMA_0_r RW_000_DMA_0.r - Inst pos_clk_un37_as_030_d0_0_i_a2_1_1 pos_clk.un37_as_030_d0_0_i_a2_1_1 - Inst RW_000_DMA_0_m RW_000_DMA_0.m - Inst pos_clk_un37_as_030_d0_0_i_a2_1_2 pos_clk.un37_as_030_d0_0_i_a2_1_2 - Inst cpu_est_2_i_0_i_3_ cpu_est_2_i_0_i[3] - Inst RW_000_DMA_0_n RW_000_DMA_0.n - Inst pos_clk_un37_as_030_d0_0_i_a2_1_3 pos_clk.un37_as_030_d0_0_i_a2_1_3 - Inst cpu_est_2_0_0_0_2_ cpu_est_2_0_0_0[2] - Inst RW_000_DMA_0_p RW_000_DMA_0.p - Inst pos_clk_un37_as_030_d0_0_i_a2_1_4 pos_clk.un37_as_030_d0_0_i_a2_1_4 - Inst A0_DMA_0_r A0_DMA_0.r - Inst SM_AMIGA_nss_i_i_0_0_o2_0_1_0_ SM_AMIGA_nss_i_i_0_0_o2_0_1[0] - Inst cpu_est_i_2_ cpu_est_i[2] - Inst A0_DMA_0_m A0_DMA_0.m - Inst SM_AMIGA_nss_i_i_0_0_o2_0_0_ SM_AMIGA_nss_i_i_0_0_o2_0[0] - Inst cpu_est_2_0_0_a2_0_2_ cpu_est_2_0_0_a2_0[2] - Inst A0_DMA_0_n A0_DMA_0.n + Inst CLK_000_D_i_1_ CLK_000_D_i[1] + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m + Inst pos_clk_un23_bgack_030_int_i_0_o2_2_o3_1 pos_clk.un23_bgack_030_int_i_0_o2_2_o3_1 + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n + Inst pos_clk_un23_bgack_030_int_i_0_o2_2_o3_2 pos_clk.un23_bgack_030_int_i_0_o2_2_o3_2 + Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p + Inst pos_clk_un23_bgack_030_int_i_0_o2_2_o3 pos_clk.un23_bgack_030_int_i_0_o2_2_o3 + Inst SM_AMIGA_nss_i_0_0_o2_1_0_ SM_AMIGA_nss_i_0_0_o2_1[0] + Inst pos_clk_CYCLE_DMA_5_0_i_0_1 pos_clk.CYCLE_DMA_5_0_i_0_1 + Inst SM_AMIGA_nss_i_0_0_o2_2_0_ SM_AMIGA_nss_i_0_0_o2_2[0] + Inst pos_clk_CYCLE_DMA_5_0_i_0_2 pos_clk.CYCLE_DMA_5_0_i_0_2 + Inst IPL_D0_0_i_0_ IPL_D0_0_i[0] + Inst SM_AMIGA_nss_i_0_0_o2_0_0_ SM_AMIGA_nss_i_0_0_o2_0[0] + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst SM_AMIGA_nss_i_0_0_1_0_ SM_AMIGA_nss_i_0_0_1[0] + Inst SM_AMIGA_nss_i_0_0_2_0_ SM_AMIGA_nss_i_0_0_2[0] + Inst SM_AMIGA_srsts_i_i_6_ SM_AMIGA_srsts_i_i[6] + Inst SM_AMIGA_nss_i_0_0_3_0_ SM_AMIGA_nss_i_0_0_3[0] + Inst CLK_000_D_i_11_ CLK_000_D_i[11] + Inst SM_AMIGA_nss_i_0_0_4_0_ SM_AMIGA_nss_i_0_0_4[0] + Inst SM_AMIGA_nss_i_0_0_5_0_ SM_AMIGA_nss_i_0_0_5[0] + Inst SM_AMIGA_nss_i_0_0_0_ SM_AMIGA_nss_i_0_0[0] + Inst SM_AMIGA_srsts_0_0_a2_0_ SM_AMIGA_srsts_0_0_a2[0] Inst pos_clk_un10_sm_amiga_1 pos_clk.un10_sm_amiga_1 - Inst A0_DMA_0_p A0_DMA_0.p Inst pos_clk_un10_sm_amiga pos_clk.un10_sm_amiga - Inst SM_AMIGA_srsts_i_0_0_a2_1_3_ SM_AMIGA_srsts_i_0_0_a2_1[3] - Inst cpu_est_2_i_0_i_a2_3_ cpu_est_2_i_0_i_a2[3] - Inst cpu_est_2_0_0_0_a2_2_ cpu_est_2_0_0_0_a2[2] - Inst SM_AMIGA_nss_i_i_0_0_a2_0_ SM_AMIGA_nss_i_i_0_0_a2[0] + Inst cpu_est_0_i_i_0_ cpu_est_0_i_i[0] + Inst SM_AMIGA_srsts_0_0_i_3_ SM_AMIGA_srsts_0_0_i[3] + Inst RST_DLY_i_0_ RST_DLY_i[0] Inst RST_DLY_i_1_ RST_DLY_i[1] + Inst SM_AMIGA_srsts_0_0_i_2_ SM_AMIGA_srsts_0_0_i[2] + Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] + Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7] + Inst SM_AMIGA_srsts_0_0_i_1_ SM_AMIGA_srsts_0_0_i[1] + Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst SM_AMIGA_srsts_0_0_i_0_ SM_AMIGA_srsts_0_0_i[0] + Inst IPL_030_1_i_0_ IPL_030_1_i[0] + Inst IPL_c_i_0_ IPL_c_i[0] + Inst RST_DLY_i_2_ RST_DLY_i[2] Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] Inst SM_AMIGA_6_ SM_AMIGA[6] - Inst cpu_est_0_0_x2_0_x2_0_ cpu_est_0_0_x2_0_x2[0] Inst SM_AMIGA_5_ SM_AMIGA[5] - Inst cpu_est_i_3_ cpu_est_i[3] Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst cpu_est_i_0_ cpu_est_i[0] Inst SM_AMIGA_3_ SM_AMIGA[3] - Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] + Inst cpu_est_0_i_i_a3_0_ cpu_est_0_i_i_a3[0] Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst pos_clk_DS_000_DMA_4_f0_0_0_i pos_clk.DS_000_DMA_4_f0_0_0_i + Inst cpu_est_0_i_i_a3_0_0_ cpu_est_0_i_i_a3_0[0] Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst SM_AMIGA_nss_i_i_0_0_o2_3_0_ SM_AMIGA_nss_i_i_0_0_o2_3[0] + Inst A_DECODE_i_19_ A_DECODE_i[19] Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst A_DECODE_i_16_ A_DECODE_i[16] Inst cpu_est_2_ cpu_est[2] - Inst SM_AMIGA_nss_i_i_0_0_o2_1_0_ SM_AMIGA_nss_i_i_0_0_o2_1[0] + Inst SM_AMIGA_srsts_0_0_0_i_4_ SM_AMIGA_srsts_0_0_0_i[4] Inst cpu_est_3_ cpu_est[3] Inst IPL_030DFF_0_ IPL_030DFF[0] - Inst SM_AMIGA_nss_i_i_0_0_1_0_ SM_AMIGA_nss_i_i_0_0_1[0] - Inst cpu_est_i_1_ cpu_est_i[1] + Inst pos_clk_A0_DMA_3_0_a2_0_a3 pos_clk.A0_DMA_3_0_a2_0_a3 Inst IPL_030DFF_1_ IPL_030DFF[1] - Inst SM_AMIGA_nss_i_i_0_0_2_0_ SM_AMIGA_nss_i_i_0_0_2[0] - Inst cpu_est_i_0_ cpu_est_i[0] Inst IPL_030DFF_2_ IPL_030DFF[2] - Inst SM_AMIGA_nss_i_i_0_0_3_0_ SM_AMIGA_nss_i_i_0_0_3[0] - Inst cpu_est_2_0_0_0_o2_2_ cpu_est_2_0_0_0_o2[2] + Inst SM_AMIGA_srsts_0_0_i_5_ SM_AMIGA_srsts_0_0_i[5] Inst IPL_D0_0_ IPL_D0[0] - Inst SM_AMIGA_nss_i_i_0_0_0_ SM_AMIGA_nss_i_i_0_0[0] - Inst RST_DLY_i_0_ RST_DLY_i[0] Inst IPL_D0_1_ IPL_D0[1] - Inst SM_AMIGA_srsts_i_0_0_1_3_ SM_AMIGA_srsts_i_0_0_1[3] + Inst SM_AMIGA_srsts_0_0_o2_i_2_ SM_AMIGA_srsts_0_0_o2_i[2] + Inst pos_clk_RW_000_INT_5_0 pos_clk.RW_000_INT_5_0 Inst IPL_D0_2_ IPL_D0[2] - Inst SM_AMIGA_srsts_i_0_0_2_3_ SM_AMIGA_srsts_i_0_0_2[3] - Inst SM_AMIGA_srsts_i_i_0_2_ SM_AMIGA_srsts_i_i_0[2] - Inst CLK_000_N_SYNC_6_ CLK_000_N_SYNC[6] - Inst SM_AMIGA_srsts_i_0_0_3_ SM_AMIGA_srsts_i_0_0[3] - Inst CLK_000_N_SYNC_7_ CLK_000_N_SYNC[7] - Inst SM_AMIGA_nss_i_i_0_0_o2_2_1_0_ SM_AMIGA_nss_i_i_0_0_o2_2_1[0] - Inst CLK_000_N_SYNC_8_ CLK_000_N_SYNC[8] - Inst SM_AMIGA_nss_i_i_0_0_o2_2_0_ SM_AMIGA_nss_i_i_0_0_o2_2[0] - Inst CLK_000_N_SYNC_9_ CLK_000_N_SYNC[9] - Inst CLK_000_N_SYNC_10_ CLK_000_N_SYNC[10] - Inst CLK_000_N_SYNC_11_ CLK_000_N_SYNC[11] - Inst CLK_000_N_SYNC_12_ CLK_000_N_SYNC[12] - Inst CYCLE_DMA_0_ CYCLE_DMA[0] - Inst CYCLE_DMA_1_ CYCLE_DMA[1] - Inst SIZE_DMA_0_ SIZE_DMA[0] - Inst SIZE_DMA_1_ SIZE_DMA[1] - Inst cpu_est_2_i_0_i_o2_3_ cpu_est_2_i_0_i_o2[3] - Inst cpu_est_0_ cpu_est[0] - Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] - Inst cpu_est_1_ cpu_est[1] - Inst SM_AMIGA_srsts_i_0_o2_1_ SM_AMIGA_srsts_i_0_o2[1] - Inst CLK_000_P_SYNC_2_ CLK_000_P_SYNC[2] - Inst CLK_000_P_SYNC_3_ CLK_000_P_SYNC[3] - Inst SM_AMIGA_srsts_i_0_m2_1__r SM_AMIGA_srsts_i_0_m2_1_.r - Inst CLK_000_P_SYNC_4_ CLK_000_P_SYNC[4] - Inst SM_AMIGA_srsts_i_0_m2_1__m SM_AMIGA_srsts_i_0_m2_1_.m - Inst CLK_000_P_SYNC_5_ CLK_000_P_SYNC[5] - Inst pos_clk_un37_as_030_d0_0_i_o2_1 pos_clk.un37_as_030_d0_0_i_o2_1 - Inst SM_AMIGA_srsts_i_0_m2_1__n SM_AMIGA_srsts_i_0_m2_1_.n - Inst CLK_000_P_SYNC_6_ CLK_000_P_SYNC[6] - Inst pos_clk_un37_as_030_d0_0_i_o2 pos_clk.un37_as_030_d0_0_i_o2 - Inst SM_AMIGA_srsts_i_0_m2_1__p SM_AMIGA_srsts_i_0_m2_1_.p - Inst CLK_000_P_SYNC_7_ CLK_000_P_SYNC[7] - Inst pos_clk_SIZE_DMA_6_0_0_i_1_ pos_clk.SIZE_DMA_6_0_0_i[1] - Inst VMA_INT_0_r VMA_INT_0.r - Inst CLK_000_P_SYNC_8_ CLK_000_P_SYNC[8] - Inst VMA_INT_0_m VMA_INT_0.m - Inst CLK_000_P_SYNC_9_ CLK_000_P_SYNC[9] - Inst pos_clk_SIZE_DMA_6_0_0_i_0_ pos_clk.SIZE_DMA_6_0_0_i[0] - Inst VMA_INT_0_n VMA_INT_0.n - Inst CLK_000_P_SYNC_10_ CLK_000_P_SYNC[10] - Inst VMA_INT_0_p VMA_INT_0.p - Inst CLK_000_N_SYNC_0_ CLK_000_N_SYNC[0] - Inst CLK_000_N_SYNC_1_ CLK_000_N_SYNC[1] - Inst cpu_est_0_1__r cpu_est_0_1_.r - Inst CLK_000_N_SYNC_2_ CLK_000_N_SYNC[2] - Inst cpu_est_0_1__m cpu_est_0_1_.m - Inst CLK_000_N_SYNC_3_ CLK_000_N_SYNC[3] - Inst cpu_est_0_1__n cpu_est_0_1_.n - Inst CLK_000_N_SYNC_4_ CLK_000_N_SYNC[4] - Inst cpu_est_0_1__p cpu_est_0_1_.p - Inst CLK_000_N_SYNC_5_ CLK_000_N_SYNC[5] - Inst cpu_est_2_0_0_0_a2_1_ cpu_est_2_0_0_0_a2[1] - Inst CLK_000_D_0_ CLK_000_D[0] - Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] - Inst CLK_000_D_1_ CLK_000_D[1] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0_ un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i[0] - Inst SM_AMIGA_srsts_i_0_0_a2_0_4_ SM_AMIGA_srsts_i_0_0_a2_0[4] - Inst CLK_000_D_2_ CLK_000_D[2] - Inst CLK_000_D_3_ CLK_000_D[3] - Inst CLK_000_D_4_ CLK_000_D[4] - Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] - Inst CLK_000_D_5_ CLK_000_D[5] - Inst pos_clk_un23_bgack_030_int_i_0_o2_i pos_clk.un23_bgack_030_int_i_0_o2_i - Inst SM_AMIGA_srsts_i_0_a2_1_ SM_AMIGA_srsts_i_0_a2[1] + Inst pos_clk_un37_as_030_d0_i_i pos_clk.un37_as_030_d0_i_i Inst CLK_000_D_6_ CLK_000_D[6] + Inst SM_AMIGA_srsts_0_0_o2_i_3_ SM_AMIGA_srsts_0_0_o2_i[3] Inst CLK_000_D_7_ CLK_000_D[7] + Inst cpu_est_2_i_i_i_o2_i_3_ cpu_est_2_i_i_i_o2_i[3] Inst CLK_000_D_8_ CLK_000_D[8] - Inst pos_clk_un4_clk_000_pe_0_0 pos_clk.un4_clk_000_pe_0_0 Inst CLK_000_D_9_ CLK_000_D[9] - Inst cpu_est_2_0_0_0_1_ cpu_est_2_0_0_0[1] Inst CLK_000_D_10_ CLK_000_D[10] - Inst SM_AMIGA_srsts_i_0_a2_6_ SM_AMIGA_srsts_i_0_a2[6] + Inst pos_clk_un3_as_030_d0_0_o2_0_o3 pos_clk.un3_as_030_d0_0_o2_0_o3 Inst CLK_000_D_11_ CLK_000_D[11] + Inst pos_clk_CYCLE_DMA_5_1_i_o2_0_o3_i pos_clk.CYCLE_DMA_5_1_i_o2_0_o3_i Inst CLK_000_D_12_ CLK_000_D[12] - Inst CLK_000_D_i_11_ CLK_000_D_i[11] - Inst CLK_000_P_SYNC_0_ CLK_000_P_SYNC[0] - Inst CLK_000_P_SYNC_1_ CLK_000_P_SYNC[1] - Inst RST_DLY_0_ RST_DLY[0] - Inst pos_clk_un37_as_030_d0_0_i pos_clk.un37_as_030_d0_0_i + Inst AS_000_INT_0_r AS_000_INT_0.r + Inst CYCLE_DMA_0_ CYCLE_DMA[0] + Inst pos_clk_un23_bgack_030_int_i_0_o2_2_o3_i pos_clk.un23_bgack_030_int_i_0_o2_2_o3_i + Inst AS_000_INT_0_m AS_000_INT_0.m + Inst CYCLE_DMA_1_ CYCLE_DMA[1] + Inst AS_000_INT_0_n AS_000_INT_0.n + Inst SIZE_DMA_0_ SIZE_DMA[0] + Inst AS_000_INT_0_p AS_000_INT_0.p + Inst SIZE_DMA_1_ SIZE_DMA[1] + Inst SM_AMIGA_nss_i_0_0_o2_i_0_ SM_AMIGA_nss_i_0_0_o2_i[0] + Inst DS_000_ENABLE_0_r DS_000_ENABLE_0.r + Inst cpu_est_0_ cpu_est[0] + Inst DS_000_ENABLE_0_m DS_000_ENABLE_0.m + Inst cpu_est_1_ cpu_est[1] + Inst DS_000_ENABLE_0_n DS_000_ENABLE_0.n Inst RST_DLY_1_ RST_DLY[1] + Inst cpu_est_2_0_0_0_i_1_ cpu_est_2_0_0_0_i[1] + Inst DS_000_ENABLE_0_p DS_000_ENABLE_0.p Inst RST_DLY_2_ RST_DLY[2] - Inst pos_clk_un3_as_030_d0_0_o2_0_o2 pos_clk.un3_as_030_d0_0_o2_0_o2 - Inst pos_clk_DS_000_DMA_4_f0_0_i pos_clk.DS_000_DMA_4_f0_0_i - Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7] - Inst SM_AMIGA_srsts_i_0_o2_0_6_ SM_AMIGA_srsts_i_0_o2_0[6] - Inst SM_AMIGA_srsts_i_0_0_o2_i_4_ SM_AMIGA_srsts_i_0_0_o2_i[4] - Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] - Inst pos_clk_un4_bgack_000_i_o2_i pos_clk.un4_bgack_000_i_o2_i - Inst SM_AMIGA_srsts_i_0_0_o2_5_ SM_AMIGA_srsts_i_0_0_o2[5] - Inst SM_AMIGA_srsts_i_0_0_m2_5__r SM_AMIGA_srsts_i_0_0_m2_5_.r - Inst SM_AMIGA_srsts_i_0_o2_i_0_ SM_AMIGA_srsts_i_0_o2_i[0] - Inst SM_AMIGA_srsts_i_0_0_m2_5__m SM_AMIGA_srsts_i_0_0_m2_5_.m - Inst SM_AMIGA_srsts_i_0_0_m2_5__n SM_AMIGA_srsts_i_0_0_m2_5_.n - Inst SM_AMIGA_srsts_i_0_0_o2_i_3_ SM_AMIGA_srsts_i_0_0_o2_i[3] - Inst SM_AMIGA_srsts_i_0_0_m2_5__p SM_AMIGA_srsts_i_0_0_m2_5_.p - Inst CLK_000_P_SYNC_i_10_ CLK_000_P_SYNC_i[10] - Inst pos_clk_SIZE_DMA_6_0_0_o2_i_0_ pos_clk.SIZE_DMA_6_0_0_o2_i[0] + Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst CLK_000_D_0_ CLK_000_D[0] + Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst CLK_000_D_1_ CLK_000_D[1] + Inst cpu_est_2_0_0_0_i_2_ cpu_est_2_0_0_0_i[2] + Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst CLK_000_D_2_ CLK_000_D[2] + Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p + Inst CLK_000_D_3_ CLK_000_D[3] Inst RW_000_INT_0_r RW_000_INT_0.r + Inst CLK_000_D_4_ CLK_000_D[4] Inst RW_000_INT_0_m RW_000_INT_0.m + Inst CLK_000_D_5_ CLK_000_D[5] Inst RW_000_INT_0_n RW_000_INT_0.n - Inst SM_AMIGA_srsts_i_0_0_o2_0_i_3_ SM_AMIGA_srsts_i_0_0_o2_0_i[3] + Inst RST_DLY_0_ RST_DLY[0] Inst RW_000_INT_0_p RW_000_INT_0.p - Inst pos_clk_un37_as_030_d0_0_i_a2 pos_clk.un37_as_030_d0_0_i_a2 - Inst pos_clk_un37_as_030_d0_0_i_a2_0 pos_clk.un37_as_030_d0_0_i_a2_0 - Inst SM_AMIGA_srsts_i_0_0_a2_5_ SM_AMIGA_srsts_i_0_0_a2[5] - Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst A0_DMA_0_r A0_DMA_0.r + Inst A0_DMA_0_m A0_DMA_0.m + Inst cpu_est_2_0_0_0_o2_i_2_ cpu_est_2_0_0_0_o2_i[2] + Inst A0_DMA_0_n A0_DMA_0.n + Inst A0_DMA_0_p A0_DMA_0.p + Inst BG_000_0_r BG_000_0.r + Inst BG_000_0_m BG_000_0.m + Inst pos_clk_SIZE_DMA_6_0_0_0_i_0_ pos_clk.SIZE_DMA_6_0_0_0_i[0] + Inst BG_000_0_n BG_000_0.n + Inst BG_000_0_p BG_000_0.p + Inst pos_clk_SIZE_DMA_6_0_0_0_i_1_ pos_clk.SIZE_DMA_6_0_0_0_i[1] + Inst pos_clk_SIZE_DMA_6_0_0_0_o2_i_0_ pos_clk.SIZE_DMA_6_0_0_0_o2_i[0] Inst A_DECODE_i_18_ A_DECODE_i[18] - Inst pos_clk_un6_bgack_000_0_i pos_clk.un6_bgack_000_0_i - Inst SM_AMIGA_srsts_i_0_o2_i_6_ SM_AMIGA_srsts_i_0_o2_i[6] - Inst SM_AMIGA_srsts_i_i_0_o2_i_2_ SM_AMIGA_srsts_i_i_0_o2_i[2] + Inst pos_clk_SIZE_DMA_6_0_0_0_a3_0_ pos_clk.SIZE_DMA_6_0_0_0_a3[0] + Inst SIZE_DMA_i_0_ SIZE_DMA_i[0] + Inst pos_clk_un9_clk_000_pe_0_0_i pos_clk.un9_clk_000_pe_0_0_i + Inst SIZE_DMA_i_1_ SIZE_DMA_i[1] + Inst SIZE_DMA_0_1__r SIZE_DMA_0_1_.r + Inst SIZE_DMA_0_1__m SIZE_DMA_0_1_.m + Inst SIZE_DMA_0_1__n SIZE_DMA_0_1_.n + Inst SIZE_DMA_0_1__p SIZE_DMA_0_1_.p + Inst SIZE_DMA_0_0__r SIZE_DMA_0_0_.r + Inst SIZE_DMA_0_0__m SIZE_DMA_0_0_.m + Inst pos_clk_un6_bg_030_i pos_clk.un6_bg_030_i + Inst SIZE_DMA_0_0__n SIZE_DMA_0_0_.n + Inst pos_clk_un9_bg_030_i pos_clk.un9_bg_030_i + Inst SIZE_DMA_0_0__p SIZE_DMA_0_0_.p Inst SIZE_0_ SIZE[0] Inst BGACK_030_INT_0_r BGACK_030_INT_0.r Inst SIZE_1_ SIZE[1] Inst BGACK_030_INT_0_m BGACK_030_INT_0.m Inst AHIGH_24_ AHIGH[24] - Inst pos_clk_un37_as_030_d0_0_i_o2_i pos_clk.un37_as_030_d0_0_i_o2_i Inst BGACK_030_INT_0_n BGACK_030_INT_0.n Inst AHIGH_25_ AHIGH[25] - Inst SM_AMIGA_srsts_i_0_0_o2_i_5_ SM_AMIGA_srsts_i_0_0_o2_i[5] + Inst pos_clk_un6_bgack_000_0_i pos_clk.un6_bgack_000_0_i Inst BGACK_030_INT_0_p BGACK_030_INT_0.p Inst AHIGH_26_ AHIGH[26] + Inst pos_clk_un9_bg_030 pos_clk.un9_bg_030 Inst AHIGH_27_ AHIGH[27] Inst AHIGH_28_ AHIGH[28] - Inst SM_AMIGA_srsts_i_0_o2_0_i_6_ SM_AMIGA_srsts_i_0_o2_0_i[6] Inst AHIGH_29_ AHIGH[29] Inst AHIGH_30_ AHIGH[30] + Inst pos_clk_un37_as_030_d0_i_i_i pos_clk.un37_as_030_d0_i_i_i + Inst DSACK1_INT_0_r DSACK1_INT_0.r Inst AHIGH_31_ AHIGH[31] - Inst pos_clk_un3_as_030_d0_0_o2_0_o2_i pos_clk.un3_as_030_d0_0_o2_0_o2_i - Inst AS_000_INT_0_r AS_000_INT_0.r - Inst AS_000_INT_0_m AS_000_INT_0.m - Inst AS_000_INT_0_n AS_000_INT_0.n - Inst pos_clk_un37_as_030_d0_0_i_i pos_clk.un37_as_030_d0_0_i_i - Inst AS_000_INT_0_p AS_000_INT_0.p - Inst DS_000_ENABLE_0_r DS_000_ENABLE_0.r - Inst DS_000_ENABLE_0_m DS_000_ENABLE_0.m - Inst DS_000_ENABLE_0_n DS_000_ENABLE_0.n - Inst DS_000_ENABLE_0_p DS_000_ENABLE_0.p - Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r - Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m - Inst SM_AMIGA_srsts_i_i_0_i_2_ SM_AMIGA_srsts_i_i_0_i[2] - Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n - Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk.CYCLE_DMA_5_1_i_x2 + Inst pos_clk_RW_000_INT_5_0_i pos_clk.RW_000_INT_5_0_i + Inst DSACK1_INT_0_m DSACK1_INT_0.m + Inst DSACK1_INT_0_n DSACK1_INT_0.n + Inst DSACK1_INT_0_p DSACK1_INT_0.p + Inst cpu_est_0_3__r cpu_est_0_3_.r + Inst cpu_est_0_3__m cpu_est_0_3_.m + Inst cpu_est_0_3__n cpu_est_0_3_.n + Inst cpu_est_0_3__p cpu_est_0_3_.p + Inst cpu_est_0_2__r cpu_est_0_2_.r + Inst cpu_est_0_2__m cpu_est_0_2_.m + Inst cpu_est_0_2__n cpu_est_0_2_.n + Inst cpu_est_0_2__p cpu_est_0_2_.p + Inst cpu_est_0_1__r cpu_est_0_1_.r + Inst cpu_est_0_1__m cpu_est_0_1_.m + Inst cpu_est_0_1__n cpu_est_0_1_.n + Inst cpu_est_0_1__p cpu_est_0_1_.p Inst A_DECODE_16_ A_DECODE[16] - Inst cpu_est_2_0_0_0_i_1_ cpu_est_2_0_0_0_i[1] - Inst pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk.CYCLE_DMA_5_0_i_x2 Inst A_DECODE_17_ A_DECODE[17] Inst A_DECODE_18_ A_DECODE[18] - Inst pos_clk_un4_bgack_000_i_o2 pos_clk.un4_bgack_000_i_o2 + Inst cpu_est_i_1_ cpu_est_i[1] Inst A_DECODE_19_ A_DECODE[19] - Inst pos_clk_un4_clk_000_pe_0_0_i pos_clk.un4_clk_000_pe_0_0_i - Inst SM_AMIGA_srsts_i_0_0_o2_4_ SM_AMIGA_srsts_i_0_0_o2[4] + Inst VMA_INT_0_r VMA_INT_0.r Inst A_DECODE_20_ A_DECODE[20] - Inst SM_AMIGA_nss_i_i_0_0_o2_0_ SM_AMIGA_nss_i_i_0_0_o2[0] + Inst VMA_INT_0_m VMA_INT_0.m Inst A_DECODE_21_ A_DECODE[21] - Inst SM_AMIGA_srsts_i_i_0_o2_2_ SM_AMIGA_srsts_i_i_0_o2[2] + Inst VMA_INT_0_n VMA_INT_0.n Inst A_DECODE_22_ A_DECODE[22] - Inst SM_AMIGA_srsts_i_0_o2_6_ SM_AMIGA_srsts_i_0_o2[6] + Inst VMA_INT_0_p VMA_INT_0.p Inst A_DECODE_23_ A_DECODE[23] - Inst pos_clk_un6_bgack_000_0 pos_clk.un6_bgack_000_0 + Inst pos_clk_un3_as_030_d0_0_o2_0_o3_i pos_clk.un3_as_030_d0_0_o2_0_o3_i + Inst pos_clk_SIZE_DMA_6_0_0_0_o2_0_ pos_clk.SIZE_DMA_6_0_0_0_o2[0] Inst A_0_ A[0] - Inst A_DECODE_i_16_ A_DECODE_i[16] + Inst pos_clk_SIZE_DMA_6_0_0_0_1_ pos_clk.SIZE_DMA_6_0_0_0[1] Inst A_1_ A[1] - Inst SM_AMIGA_nss_i_i_0_0_a2_3_0_ SM_AMIGA_nss_i_i_0_0_a2_3[0] - Inst SM_AMIGA_srsts_i_0_a2_0_6_ SM_AMIGA_srsts_i_0_a2_0[6] - Inst SM_AMIGA_srsts_i_0_0_a2_4_ SM_AMIGA_srsts_i_0_0_a2[4] - Inst A_DECODE_i_19_ A_DECODE_i[19] - Inst pos_clk_un23_bgack_030_int_i_0_x2 pos_clk.un23_bgack_030_int_i_0_x2 - Inst SM_AMIGA_srsts_i_0_o2_i_1_ SM_AMIGA_srsts_i_0_o2_i[1] - Inst cpu_est_2_i_0_i_o2_i_3_ cpu_est_2_i_0_i_o2_i[3] - Inst SM_AMIGA_srsts_i_0_0_o2_0_3_ SM_AMIGA_srsts_i_0_0_o2_0[3] - Inst pos_clk_SIZE_DMA_6_0_0_o2_0_ pos_clk.SIZE_DMA_6_0_0_o2[0] - Inst SM_AMIGA_srsts_i_0_0_o2_3_ SM_AMIGA_srsts_i_0_0_o2[3] - Inst cpu_est_2_i_0_i_i_3_ cpu_est_2_i_0_i_i[3] + Inst pos_clk_SIZE_DMA_6_0_0_0_0_ pos_clk.SIZE_DMA_6_0_0_0[0] + Inst pos_clk_un6_bgack_000_0 pos_clk.un6_bgack_000_0 + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] + Inst SM_AMIGA_nss_i_0_0_o2_2_i_0_ SM_AMIGA_nss_i_0_0_o2_2_i[0] + Inst pos_clk_un6_bgack_000_0_a2 pos_clk.un6_bgack_000_0_a2 + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst pos_clk_SIZE_DMA_6_0_0_0_a3_1_ pos_clk.SIZE_DMA_6_0_0_0_a3[1] + Inst SM_AMIGA_nss_i_0_0_o2_1_i_0_ SM_AMIGA_nss_i_0_0_o2_1_i[0] + Inst cpu_est_2_0_0_0_2_ cpu_est_2_0_0_0[2] + Inst cpu_est_2_0_0_0_1_ cpu_est_2_0_0_0[1] + Inst pos_clk_un9_clk_000_pe_0_0 pos_clk.un9_clk_000_pe_0_0 + Inst cpu_est_2_0_0_0_a2_2_ cpu_est_2_0_0_0_a2[2] + Inst SM_AMIGA_srsts_0_0_a2_0_2_ SM_AMIGA_srsts_0_0_a2_0[2] Inst IPL_030_0_ IPL_030[0] - Inst SM_AMIGA_nss_i_i_0_0_o2_0_i_0_ SM_AMIGA_nss_i_i_0_0_o2_0_i[0] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.r + Inst SM_AMIGA_nss_i_0_0_i_0_ SM_AMIGA_nss_i_0_0_i[0] Inst IPL_030_1_ IPL_030[1] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.m Inst IPL_030_2_ IPL_030[2] - Inst cpu_est_2_0_0_0_o2_i_2_ cpu_est_2_0_0_0_o2_i[2] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.n + Inst SIZE_c_i_1_ SIZE_c_i[1] Inst IPL_0_ IPL[0] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.p + Inst cpu_est_i_2_ cpu_est_i[2] Inst IPL_1_ IPL[1] - Inst SM_AMIGA_nss_i_i_0_0_o2_1_i_0_ SM_AMIGA_nss_i_i_0_0_o2_1_i[0] - Inst SM_AMIGA_srsts_i_0_o2_0_ SM_AMIGA_srsts_i_0_o2[0] + Inst cpu_est_2_i_i_i_a3_3_ cpu_est_2_i_i_i_a3[3] Inst IPL_2_ IPL[2] - Inst SM_AMIGA_nss_i_i_0_0_o2_2_i_0_ SM_AMIGA_nss_i_i_0_0_o2_2_i[0] - Inst SM_AMIGA_srsts_i_0_0_ SM_AMIGA_srsts_i_0[0] - Inst SM_AMIGA_srsts_i_0_a2_0_ SM_AMIGA_srsts_i_0_a2[0] - Inst SM_AMIGA_nss_i_i_0_0_o2_3_i_0_ SM_AMIGA_nss_i_i_0_0_o2_3_i[0] - Inst pos_clk_DS_000_DMA_4_f0_0_a2 pos_clk.DS_000_DMA_4_f0_0_a2 - Inst pos_clk_un23_bgack_030_int_i_0_a2 pos_clk.un23_bgack_030_int_i_0_a2 - Inst IPL_c_i_2_ IPL_c_i[2] - Inst CLK_000_D_i_10_ CLK_000_D_i[10] - Inst IPL_D0_0_i_2_ IPL_D0_0_i[2] + Inst SM_AMIGA_srsts_i_i_i_6_ SM_AMIGA_srsts_i_i_i[6] + Inst cpu_est_2_0_0_0_a3_2_ cpu_est_2_0_0_0_a3[2] + Inst cpu_est_2_0_0_0_a3_1_ cpu_est_2_0_0_0_a3[1] + Inst pos_clk_CYCLE_DMA_5_1_i_o2_0_o3 pos_clk.CYCLE_DMA_5_1_i_o2_0_o3 + Inst pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk.CYCLE_DMA_5_1_i_0_x2 + Inst cpu_est_2_i_i_i_o2_3_ cpu_est_2_i_i_i_o2[3] + Inst SM_AMIGA_srsts_0_0_o2_3_ SM_AMIGA_srsts_0_0_o2[3] + Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] + Inst SM_AMIGA_srsts_0_0_o2_2_ SM_AMIGA_srsts_0_0_o2[2] Inst FC_0_ FC[0] - Inst SM_AMIGA_srsts_i_0_0_a2_3_3_ SM_AMIGA_srsts_i_0_0_a2_3[3] + Inst SM_AMIGA_nss_i_0_0_o2_0_i_0_ SM_AMIGA_nss_i_0_0_o2_0_i[0] + Inst pos_clk_un9_clk_000_pe_0_0_o2 pos_clk.un9_clk_000_pe_0_0_o2 Inst FC_1_ FC[1] - Inst IPL_030_1_i_0_ IPL_030_1_i[0] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0_ un1_AMIGA_BUS_ENABLE_DMA_HIGH_0[0] + Inst cpu_est_2_0_0_0_o2_2_ cpu_est_2_0_0_0_o2[2] + Inst cpu_est_i_3_ cpu_est_i[3] + Inst cpu_est_2_i_i_i_3_ cpu_est_2_i_i_i[3] + Inst SM_AMIGA_srsts_0_0_a3_5_ SM_AMIGA_srsts_0_0_a3[5] + Inst SM_AMIGA_srsts_0_0_0_ SM_AMIGA_srsts_0_0[0] + Inst SM_AMIGA_srsts_0_0_a3_1_2_ SM_AMIGA_srsts_0_0_a3_1[2] + Inst IPL_c_i_1_ IPL_c_i[1] + Inst SM_AMIGA_srsts_0_0_1_ SM_AMIGA_srsts_0_0[1] + Inst SM_AMIGA_srsts_0_0_a3_2_ SM_AMIGA_srsts_0_0_a3[2] + Inst IPL_D0_0_i_1_ IPL_D0_0_i[1] + Inst SM_AMIGA_srsts_0_0_2_ SM_AMIGA_srsts_0_0[2] + Inst SM_AMIGA_srsts_0_0_a3_1_1_ SM_AMIGA_srsts_0_0_a3_1[1] + Inst IPL_c_i_2_ IPL_c_i[2] + Inst SM_AMIGA_srsts_0_0_3_ SM_AMIGA_srsts_0_0[3] + Inst SM_AMIGA_srsts_0_0_a3_1_ SM_AMIGA_srsts_0_0_a3[1] + Inst IPL_D0_0_i_2_ IPL_D0_0_i[2] + Inst SM_AMIGA_srsts_0_0_5_ SM_AMIGA_srsts_0_0[5] + Inst SM_AMIGA_srsts_0_0_0_4_ SM_AMIGA_srsts_0_0_0[4] Inst IPL_030_1_i_1_ IPL_030_1_i[1] + Inst pos_clk_DS_000_DMA_4_f0_0_0 pos_clk.DS_000_DMA_4_f0_0_0 Inst IPL_030_1_i_2_ IPL_030_1_i[2] Inst A_c_i_0_ A_c_i[0] - Inst pos_clk_SIZE_DMA_6_0_0_0_ pos_clk.SIZE_DMA_6_0_0[0] - Inst SM_AMIGA_nss_i_i_0_0_a2_0_0_ SM_AMIGA_nss_i_i_0_0_a2_0[0] - Inst SIZE_c_i_1_ SIZE_c_i[1] - Inst pos_clk_SIZE_DMA_6_0_0_1_ pos_clk.SIZE_DMA_6_0_0[1] - Inst pos_clk_DS_000_DMA_4_f0_0 pos_clk.DS_000_DMA_4_f0_0 - Inst CLK_000_D_i_1_ CLK_000_D_i[1] - Inst pos_clk_CLK_000_P_SYNC_2_0_a2_0_ pos_clk.CLK_000_P_SYNC_2_0_a2[0] - Inst cpu_est_2_0_0_0_i_2_ cpu_est_2_0_0_0_i[2] Inst CLK_000_D_i_0_ CLK_000_D_i[0] - Inst pos_clk_CLK_000_N_SYNC_2_0_a2_0_ pos_clk.CLK_000_N_SYNC_2_0_a2[0] - Inst pos_clk_un6_bg_030_i pos_clk.un6_bg_030_i - Inst pos_clk_un9_bg_030_i pos_clk.un9_bg_030_i - Inst pos_clk_A0_DMA_3_0_a2 pos_clk.A0_DMA_3_0_a2 - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0_ un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1[0] - Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0_ un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2[0] - Inst A_i_1_ A_i[1] - Inst pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 - Inst SM_AMIGA_srsts_i_i_0_a2_1_2_ SM_AMIGA_srsts_i_i_0_a2_1[2] - Inst pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 - Inst SM_AMIGA_srsts_i_i_0_a2_2_ SM_AMIGA_srsts_i_i_0_a2[2] - Inst cpu_est_2_0_0_a2_1_1_1_ cpu_est_2_0_0_a2_1_1[1] - Inst pos_clk_SIZE_DMA_6_0_0_a2_0_ pos_clk.SIZE_DMA_6_0_0_a2[0] - Inst cpu_est_2_0_0_a2_1_1_ cpu_est_2_0_0_a2_1[1] - Inst pos_clk_SIZE_DMA_6_0_0_a2_1_ pos_clk.SIZE_DMA_6_0_0_a2[1] - Inst SM_AMIGA_srsts_i_0_0_a2_0_1_3_ SM_AMIGA_srsts_i_0_0_a2_0_1[3] - Inst IPL_c_i_0_ IPL_c_i[0] - Inst SM_AMIGA_srsts_i_0_0_a2_0_3_ SM_AMIGA_srsts_i_0_0_a2_0[3] - Inst IPL_D0_0_i_0_ IPL_D0_0_i[0] - Inst SM_AMIGA_nss_i_i_0_0_a2_1_1_0_ SM_AMIGA_nss_i_i_0_0_a2_1_1[0] - Inst IPL_c_i_1_ IPL_c_i[1] - Inst SM_AMIGA_nss_i_i_0_0_a2_1_0_ SM_AMIGA_nss_i_i_0_0_a2_1[0] - Inst IPL_D0_0_i_1_ IPL_D0_0_i[1] - Inst SM_AMIGA_nss_i_i_0_0_a2_0_1_0_ SM_AMIGA_nss_i_i_0_0_a2_0_1[0] + Inst pos_clk_CYCLE_DMA_5_1_i_0_1 pos_clk.CYCLE_DMA_5_1_i_0_1 + Inst pos_clk_un23_bgack_030_int_i_0_o2_2_x2 pos_clk.un23_bgack_030_int_i_0_o2_2_x2 + Inst pos_clk_CYCLE_DMA_5_1_i_0 pos_clk.CYCLE_DMA_5_1_i_0 + Inst RW_000_DMA_0_r RW_000_DMA_0.r + Inst SM_AMIGA_nss_i_0_0_o2_0_ SM_AMIGA_nss_i_0_0_o2[0] + Inst RW_000_DMA_0_m RW_000_DMA_0.m + Inst RW_000_DMA_0_n RW_000_DMA_0.n + Inst SM_AMIGA_srsts_0_0_0_a3_4_ SM_AMIGA_srsts_0_0_0_a3[4] + Inst RW_000_DMA_0_p RW_000_DMA_0.p + Inst SM_AMIGA_srsts_0_0_0_a3_0_4_ SM_AMIGA_srsts_0_0_0_a3_0[4] + Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst pos_clk_DS_000_DMA_4_f0_0_0_a3 pos_clk.DS_000_DMA_4_f0_0_0_a3 + Inst cpu_est_2_0_0_a3_1_1_1_ cpu_est_2_0_0_a3_1_1[1] + Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst cpu_est_2_0_0_a3_1_1_ cpu_est_2_0_0_a3_1[1] + Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst pos_clk_un6_bg_030_0_a3_1 pos_clk.un6_bg_030_0_a3_1 + Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst pos_clk_un6_bg_030_0_a3 pos_clk.un6_bg_030_0_a3 + Inst SM_AMIGA_srsts_i_i_a3_1_6_ SM_AMIGA_srsts_i_i_a3_1[6] + Inst pos_clk_un23_bgack_030_int_i_0_o2_2_a2 pos_clk.un23_bgack_030_int_i_0_o2_2_a2 + Inst SM_AMIGA_srsts_i_i_a3_6_ SM_AMIGA_srsts_i_i_a3[6] + Inst SM_AMIGA_nss_i_0_0_a2_0_ SM_AMIGA_nss_i_0_0_a2[0] + Inst SM_AMIGA_srsts_0_0_a3_1_5_ SM_AMIGA_srsts_0_0_a3_1[5] + Inst CLK_000_D_i_10_ CLK_000_D_i[10] + Inst SM_AMIGA_srsts_0_0_a2_0_1_ SM_AMIGA_srsts_0_0_a2_0[1] + Inst SM_AMIGA_srsts_i_i_a3_0_1_6_ SM_AMIGA_srsts_i_i_a3_0_1[6] + Inst SM_AMIGA_srsts_0_0_a2_0_0_ SM_AMIGA_srsts_0_0_a2_0[0] + Inst SM_AMIGA_srsts_i_i_a3_0_6_ SM_AMIGA_srsts_i_i_a3_0[6] + Inst SM_AMIGA_nss_i_0_0_a3_2_1_0_ SM_AMIGA_nss_i_0_0_a3_2_1[0] + Inst SM_AMIGA_nss_i_0_0_a3_2_2_0_ SM_AMIGA_nss_i_0_0_a3_2_2[0] + Inst SM_AMIGA_nss_i_0_0_a3_2_3_0_ SM_AMIGA_nss_i_0_0_a3_2_3[0] + Inst IPL_030_0_1__r IPL_030_0_1_.r + Inst SM_AMIGA_nss_i_0_0_a3_2_4_0_ SM_AMIGA_nss_i_0_0_a3_2_4[0] + Inst IPL_030_0_1__m IPL_030_0_1_.m + Inst SM_AMIGA_nss_i_0_0_a3_2_0_ SM_AMIGA_nss_i_0_0_a3_2[0] + Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst SM_AMIGA_nss_i_0_0_a3_2_5_1_0_ SM_AMIGA_nss_i_0_0_a3_2_5_1[0] + Inst IPL_030_0_1__p IPL_030_0_1_.p + Inst SM_AMIGA_nss_i_0_0_a3_2_5_2_0_ SM_AMIGA_nss_i_0_0_a3_2_5_2[0] + Inst IPL_030_1_2_ IPL_030_1[2] + Inst SM_AMIGA_srsts_0_0_a3_0_ SM_AMIGA_srsts_0_0_a3[0] + Inst SM_AMIGA_nss_i_0_0_a3_2_5_0_ SM_AMIGA_nss_i_0_0_a3_2_5[0] + Inst IPL_030_1_1_ IPL_030_1[1] + Inst SM_AMIGA_srsts_0_0_a3_0_0_ SM_AMIGA_srsts_0_0_a3_0[0] Inst IPL_D0_0_2_ IPL_D0_0[2] + Inst SM_AMIGA_srsts_0_0_a3_0_1_ SM_AMIGA_srsts_0_0_a3_0[1] Inst IPL_D0_0_1_ IPL_D0_0[1] - Inst IPL_D0_0_0_ IPL_D0_0[0] - Inst pos_clk_CYCLE_DMA_5_1_i_1 pos_clk.CYCLE_DMA_5_1_i_1 - Inst pos_clk_CYCLE_DMA_5_1_i pos_clk.CYCLE_DMA_5_1_i - Inst SIZE_DMA_i_1_ SIZE_DMA_i[1] - Inst pos_clk_CYCLE_DMA_5_0_i_1 pos_clk.CYCLE_DMA_5_0_i_1 - Inst pos_clk_CYCLE_DMA_5_0_i pos_clk.CYCLE_DMA_5_0_i - Inst BG_000_0_r BG_000_0.r - Inst SIZE_DMA_i_0_ SIZE_DMA_i[0] - Inst SM_AMIGA_srsts_i_0_0_1_5_ SM_AMIGA_srsts_i_0_0_1[5] - Inst BG_000_0_m BG_000_0.m - Inst SM_AMIGA_srsts_i_0_0_5_ SM_AMIGA_srsts_i_0_0[5] - Inst BG_000_0_n BG_000_0.n - Inst SM_AMIGA_srsts_i_0_0_1_4_ SM_AMIGA_srsts_i_0_0_1[4] - Inst BG_000_0_p BG_000_0.p - Inst SM_AMIGA_srsts_i_0_0_a2_3_ SM_AMIGA_srsts_i_0_0_a2[3] - Inst SM_AMIGA_srsts_i_0_0_4_ SM_AMIGA_srsts_i_0_0[4] + Inst SM_AMIGA_srsts_0_0_a3_0_2_ SM_AMIGA_srsts_0_0_a3_0[2] + Inst SM_AMIGA_srsts_0_0_a3_3_ SM_AMIGA_srsts_0_0_a3[3] + Inst SM_AMIGA_srsts_0_0_a3_0_3_ SM_AMIGA_srsts_0_0_a3_0[3] + Inst pos_clk_un37_as_030_d0_i_i_a3_1 pos_clk.un37_as_030_d0_i_i_a3_1 + Inst SM_AMIGA_srsts_0_0_a3_0_5_ SM_AMIGA_srsts_0_0_a3_0[5] + Inst pos_clk_un37_as_030_d0_i_i_a3_2 pos_clk.un37_as_030_d0_i_i_a3_2 + Inst CYCLE_DMA_i_0_ CYCLE_DMA_i[0] + Inst pos_clk_un37_as_030_d0_i_i_a3 pos_clk.un37_as_030_d0_i_i_a3 + Inst pos_clk_CYCLE_DMA_5_0_i_0_a3 pos_clk.CYCLE_DMA_5_0_i_0_a3 + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_r AMIGA_BUS_ENABLE_DMA_HIGH_0.r + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_m AMIGA_BUS_ENABLE_DMA_HIGH_0.m + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.n + Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_p AMIGA_BUS_ENABLE_DMA_HIGH_0.p + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_r AMIGA_BUS_ENABLE_DMA_LOW_0.r + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_m AMIGA_BUS_ENABLE_DMA_LOW_0.m + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_n AMIGA_BUS_ENABLE_DMA_LOW_0.n + Inst AMIGA_BUS_ENABLE_DMA_LOW_0_p AMIGA_BUS_ENABLE_DMA_LOW_0.p Inst UDS_000_INT_0_r UDS_000_INT_0.r Inst UDS_000_INT_0_m UDS_000_INT_0.m + Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst pos_clk_CYCLE_DMA_5_0_i_0 pos_clk.CYCLE_DMA_5_0_i_0 Inst UDS_000_INT_0_n UDS_000_INT_0.n - Inst pos_clk_un6_bg_030_0_a2_1 pos_clk.un6_bg_030_0_a2_1 + Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst pos_clk_un9_clk_000_pe_0_0_a3_1 pos_clk.un9_clk_000_pe_0_0_a3_1 Inst UDS_000_INT_0_p UDS_000_INT_0.p - Inst pos_clk_un6_bg_030_0_a2 pos_clk.un6_bg_030_0_a2 - Inst LDS_000_INT_0_r LDS_000_INT_0.r - Inst pos_clk_un4_clk_000_pe_0_0_a2_1 pos_clk.un4_clk_000_pe_0_0_a2_1 - Inst LDS_000_INT_0_m LDS_000_INT_0.m - Inst AMIGA_BUS_ENABLE_DMA_LOW_0_r AMIGA_BUS_ENABLE_DMA_LOW_0.r - Inst pos_clk_un4_clk_000_pe_0_0_a2_2 pos_clk.un4_clk_000_pe_0_0_a2_2 - Inst LDS_000_INT_0_n LDS_000_INT_0.n - Inst AMIGA_BUS_ENABLE_DMA_LOW_0_m AMIGA_BUS_ENABLE_DMA_LOW_0.m - Inst pos_clk_un4_clk_000_pe_0_0_a2_3 pos_clk.un4_clk_000_pe_0_0_a2_3 - Inst LDS_000_INT_0_p LDS_000_INT_0.p - Inst AMIGA_BUS_ENABLE_DMA_LOW_0_n AMIGA_BUS_ENABLE_DMA_LOW_0.n - Inst pos_clk_un4_clk_000_pe_0_0_a2 pos_clk.un4_clk_000_pe_0_0_a2 - Inst AMIGA_BUS_ENABLE_DMA_LOW_0_p AMIGA_BUS_ENABLE_DMA_LOW_0.p - Inst SM_AMIGA_nss_i_i_0_0_a2_2_1_0_ SM_AMIGA_nss_i_i_0_0_a2_2_1[0] - Inst DSACK1_INT_0_r DSACK1_INT_0.r - Inst SM_AMIGA_nss_i_i_0_0_a2_2_2_0_ SM_AMIGA_nss_i_i_0_0_a2_2_2[0] - Inst DSACK1_INT_0_m DSACK1_INT_0.m - Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_r AMIGA_BUS_ENABLE_DMA_HIGH_0.r - Inst SM_AMIGA_nss_i_i_0_0_a2_2_3_0_ SM_AMIGA_nss_i_i_0_0_a2_2_3[0] - Inst DSACK1_INT_0_n DSACK1_INT_0.n - Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_m AMIGA_BUS_ENABLE_DMA_HIGH_0.m - Inst SM_AMIGA_nss_i_i_0_0_a2_2_0_ SM_AMIGA_nss_i_i_0_0_a2_2[0] - Inst DSACK1_INT_0_p DSACK1_INT_0.p - Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.n - Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 - Net a_c_i_0__n A_c_i[0] - Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 - Net size_c_i_1__n SIZE_c_i[1] - Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 - Net pos_clk_un10_sm_amiga_i_n pos_clk.un10_sm_amiga_i - Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 - Net sm_amiga_srsts_i_0_m2_1__un3_n SM_AMIGA_srsts_i_0_m2_1_.un3 - Net sm_amiga_srsts_i_0_m2_1__un1_n SM_AMIGA_srsts_i_0_m2_1_.un1 - Net sm_amiga_srsts_i_0_m2_1__un0_n SM_AMIGA_srsts_i_0_m2_1_.un0 - Net cpu_est_2_0_2__n cpu_est_2_0[2] - Net vma_int_0_un3_n VMA_INT_0.un3 - Net vma_int_0_un1_n VMA_INT_0.un1 - Net vcc_n_n VCC - Net vma_int_0_un0_n VMA_INT_0.un0 - Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 - Net gnd_n_n GND - Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 - Net un1_amiga_bus_enable_dma_high_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH[0] - Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 - Net sm_amiga_srsts_i_0_0_m2_5__un3_n SM_AMIGA_srsts_i_0_0_m2_5_.un3 - Net cpu_est_2_2__n cpu_est_2[2] - Net sm_amiga_srsts_i_0_0_m2_5__un1_n SM_AMIGA_srsts_i_0_0_m2_5_.un1 - Net sm_amiga_srsts_i_0_0_m2_5__un0_n SM_AMIGA_srsts_i_0_0_m2_5_.un0 - Net rw_000_int_0_un3_n RW_000_INT_0.un3 - Net rw_000_int_0_un1_n RW_000_INT_0.un1 - Net rw_000_int_0_un0_n RW_000_INT_0.un0 - Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst pos_clk_un9_clk_000_pe_0_0_a3_2 pos_clk.un9_clk_000_pe_0_0_a3_2 + Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst pos_clk_un9_clk_000_pe_0_0_a3 pos_clk.un9_clk_000_pe_0_0_a3 + Inst pos_clk_un9_clk_000_pe_0_0_a3_0_1 pos_clk.un9_clk_000_pe_0_0_a3_0_1 + Inst SM_AMIGA_srsts_0_0_a2_1_ SM_AMIGA_srsts_0_0_a2[1] + Inst pos_clk_un9_clk_000_pe_0_0_a3_0_2 pos_clk.un9_clk_000_pe_0_0_a3_0_2 + Inst pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3 pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3 + Inst pos_clk_un9_clk_000_pe_0_0_a3_0 pos_clk.un9_clk_000_pe_0_0_a3_0 + Inst A_i_1_ A_i[1] + Inst SM_AMIGA_srsts_0_0_a2_1_2_ SM_AMIGA_srsts_0_0_a2_1[2] + Inst pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3 pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3 + Inst SM_AMIGA_srsts_0_0_a2_2_2_ SM_AMIGA_srsts_0_0_a2_2[2] + Inst SM_AMIGA_srsts_0_0_a2_2_ SM_AMIGA_srsts_0_0_a2[2] + Inst pos_clk_un37_as_030_d0_i_a2_1_1 pos_clk.un37_as_030_d0_i_a2_1_1 + Inst DS_000_DMA_0_r DS_000_DMA_0.r + Inst pos_clk_un37_as_030_d0_i_a2_1_2 pos_clk.un37_as_030_d0_i_a2_1_2 + Inst SM_AMIGA_nss_i_0_0_a3_1_0_ SM_AMIGA_nss_i_0_0_a3_1[0] + Inst DS_000_DMA_0_m DS_000_DMA_0.m + Inst pos_clk_un37_as_030_d0_i_a2_1_3 pos_clk.un37_as_030_d0_i_a2_1_3 + Inst SM_AMIGA_nss_i_0_0_a3_0_0_ SM_AMIGA_nss_i_0_0_a3_0[0] + Inst DS_000_DMA_0_n DS_000_DMA_0.n + Inst pos_clk_un37_as_030_d0_i_a2_1_4 pos_clk.un37_as_030_d0_i_a2_1_4 + Inst SM_AMIGA_nss_i_0_0_a3_0_ SM_AMIGA_nss_i_0_0_a3[0] + Inst DS_000_DMA_0_p DS_000_DMA_0.p Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net sm_amiga_nss_i_0_0__n SM_AMIGA_nss_i_0[0] Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 - Net as_000_int_0_un3_n AS_000_INT_0.un3 - Net as_000_int_0_un1_n AS_000_INT_0.un1 - Net cpu_est_2__n cpu_est[2] - Net pos_clk_un9_bg_030_n pos_clk.un9_bg_030 - Net as_000_int_0_un0_n AS_000_INT_0.un0 - Net cpu_est_3__n cpu_est[3] - Net ds_000_enable_0_un3_n DS_000_ENABLE_0.un3 - Net cpu_est_0__n cpu_est[0] - Net ds_000_enable_0_un1_n DS_000_ENABLE_0.un1 - Net cpu_est_1__n cpu_est[1] - Net ds_000_enable_0_un0_n DS_000_ENABLE_0.un0 - Net clk_000_n_sync_i_12__n CLK_000_N_SYNC_i[12] - Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 - Net rst_dly_i_2__n RST_DLY_i[2] - Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 - Net rst_dly_i_1__n RST_DLY_i[1] - Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 - Net un1_amiga_bus_enable_dma_high_0_m2_0__un3_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un3 - Net cpu_est_i_2__n cpu_est_i[2] - Net un1_amiga_bus_enable_dma_high_0_m2_0__un1_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un1 - Net un1_amiga_bus_enable_dma_high_0_m2_0__un0_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un0 - Net rst_dly_i_0__n RST_DLY_i[0] - Net amiga_bus_enable_dma_low_0_un3_n AMIGA_BUS_ENABLE_DMA_LOW_0.un3 - Net cycle_dma_0__n CYCLE_DMA[0] - Net cpu_est_i_1__n cpu_est_i[1] - Net amiga_bus_enable_dma_low_0_un1_n AMIGA_BUS_ENABLE_DMA_LOW_0.un1 - Net cycle_dma_1__n CYCLE_DMA[1] - Net cpu_est_i_0__n cpu_est_i[0] - Net amiga_bus_enable_dma_low_0_un0_n AMIGA_BUS_ENABLE_DMA_LOW_0.un0 - Net size_dma_0__n SIZE_DMA[0] - Net amiga_bus_enable_dma_high_0_un3_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un3 - Net size_dma_1__n SIZE_DMA[1] - Net sm_amiga_i_3__n SM_AMIGA_i[3] - Net amiga_bus_enable_dma_high_0_un1_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un1 + Net dsack1_int_0_un3_n DSACK1_INT_0.un3 + Net dsack1_int_0_un1_n DSACK1_INT_0.un1 + Net dsack1_int_0_un0_n DSACK1_INT_0.un0 + Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 + Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 + Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 + Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 + Net vcc_n_n VCC + Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 + Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 + Net gnd_n_n GND + Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 + Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 + Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 + Net vma_int_0_un3_n VMA_INT_0.un3 + Net a_i_1__n A_i[1] + Net vma_int_0_un1_n VMA_INT_0.un1 + Net clk_000_d_i_11__n CLK_000_D_i[11] + Net vma_int_0_un0_n VMA_INT_0.un0 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 + Net clk_000_d_i_1__n CLK_000_D_i[1] + Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 + Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 Net sm_amiga_i_0__n SM_AMIGA_i[0] - Net amiga_bus_enable_dma_high_0_un0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un0 - Net cpu_est_i_3__n cpu_est_i[3] - Net size_dma_0_0__un3_n SIZE_DMA_0_0_.un3 - Net sm_amiga_i_1__n SM_AMIGA_i[1] - Net size_dma_0_0__un1_n SIZE_DMA_0_0_.un1 - Net size_dma_0_0__un0_n SIZE_DMA_0_0_.un0 - Net clk_000_d_10__n CLK_000_D[10] - Net size_dma_0_1__un3_n SIZE_DMA_0_1_.un3 - Net clk_000_d_11__n CLK_000_D[11] - Net sm_amiga_i_2__n SM_AMIGA_i[2] - Net size_dma_0_1__un1_n SIZE_DMA_0_1_.un1 - Net sm_amiga_i_4__n SM_AMIGA_i[4] - Net size_dma_0_1__un0_n SIZE_DMA_0_1_.un0 - Net clk_000_p_sync_i_10__n CLK_000_P_SYNC_i[10] + Net pos_clk_un3_as_030_d0_0_n pos_clk.un3_as_030_d0_0 Net ds_000_dma_0_un3_n DS_000_DMA_0.un3 - Net sm_amiga_i_5__n SM_AMIGA_i[5] + Net sm_amiga_i_3__n SM_AMIGA_i[3] Net ds_000_dma_0_un1_n DS_000_DMA_0.un1 - Net clk_000_d_1__n CLK_000_D[1] Net sm_amiga_i_i_7__n SM_AMIGA_i_i[7] Net ds_000_dma_0_un0_n DS_000_DMA_0.un0 - Net clk_000_d_0__n CLK_000_D[0] - Net clk_000_d_i_11__n CLK_000_D_i[11] + Net cpu_est_3__n cpu_est[3] + Net sm_amiga_i_5__n SM_AMIGA_i[5] Net as_000_dma_0_un3_n AS_000_DMA_0.un3 - Net clk_000_p_sync_10__n CLK_000_P_SYNC[10] - Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net cpu_est_0__n cpu_est[0] + Net rst_dly_i_0__n RST_DLY_i[0] Net as_000_dma_0_un1_n AS_000_DMA_0.un1 - Net sm_amiga_5__n SM_AMIGA[5] + Net cpu_est_1__n cpu_est[1] + Net rst_dly_i_1__n RST_DLY_i[1] Net as_000_dma_0_un0_n AS_000_DMA_0.un0 - Net ipl_d0_0__n IPL_D0[0] - Net rw_000_dma_0_un3_n RW_000_DMA_0.un3 - Net ipl_d0_1__n IPL_D0[1] - Net rw_000_dma_0_un1_n RW_000_DMA_0.un1 - Net ipl_d0_2__n IPL_D0[2] - Net rw_000_dma_0_un0_n RW_000_DMA_0.un0 - Net clk_000_d_2__n CLK_000_D[2] - Net a0_dma_0_un3_n A0_DMA_0.un3 - Net clk_000_d_3__n CLK_000_D[3] - Net a0_dma_0_un1_n A0_DMA_0.un1 - Net clk_000_d_4__n CLK_000_D[4] - Net a_decode_i_19__n A_DECODE_i[19] - Net a0_dma_0_un0_n A0_DMA_0.un0 - Net clk_000_d_5__n CLK_000_D[5] - Net a_decode_i_18__n A_DECODE_i[18] - Net cpu_est_2_0_1__n cpu_est_2_0[1] + Net cpu_est_2__n cpu_est[2] Net a_decode_15__n A_DECODE[15] - Net clk_000_d_6__n CLK_000_D[6] - Net a_decode_i_16__n A_DECODE_i[16] - Net clk_000_d_7__n CLK_000_D[7] + Net cpu_est_i_0__n cpu_est_i[0] + Net rst_dly_i_2__n RST_DLY_i[2] + Net pos_clk_rw_000_int_5_0_n pos_clk.RW_000_INT_5_0 Net a_decode_14__n A_DECODE[14] - Net clk_000_d_8__n CLK_000_D[8] - Net pos_clk_un4_clk_000_pe_0_n pos_clk.un4_clk_000_pe_0 - Net clk_000_d_9__n CLK_000_D[9] Net a_decode_13__n A_DECODE[13] - Net clk_000_d_12__n CLK_000_D[12] - Net pos_clk_un6_bg_030_n pos_clk.un6_bg_030 + Net a_decode_i_16__n A_DECODE_i[16] Net a_decode_12__n A_DECODE[12] - Net sm_amiga_0__n SM_AMIGA[0] - Net clk_000_d_i_10__n CLK_000_D_i[10] + Net a_decode_i_18__n A_DECODE_i[18] + Net cycle_dma_0__n CYCLE_DMA[0] + Net a_decode_i_19__n A_DECODE_i[19] Net a_decode_11__n A_DECODE[11] - Net pos_clk_clk_000_p_sync_2_0__n pos_clk.CLK_000_P_SYNC_2[0] - Net a_i_1__n A_i[1] - Net pos_clk_clk_000_n_sync_2_0__n pos_clk.CLK_000_N_SYNC_2[0] + Net cycle_dma_1__n CYCLE_DMA[1] + Net size_dma_0__n SIZE_DMA[0] Net a_decode_10__n A_DECODE[10] - Net pos_clk_ipl_n pos_clk.ipl - Net clk_000_n_sync_0__n CLK_000_N_SYNC[0] - Net clk_000_d_i_0__n CLK_000_D_i[0] - Net a_decode_9__n A_DECODE[9] - Net sm_amiga_4__n SM_AMIGA[4] - Net clk_000_d_i_1__n CLK_000_D_i[1] - Net a_decode_8__n A_DECODE[8] - Net clk_000_n_sync_12__n CLK_000_N_SYNC[12] - Net size_dma_i_0__n SIZE_DMA_i[0] - Net rst_dly_0__n RST_DLY[0] + Net size_dma_1__n SIZE_DMA[1] Net size_dma_i_1__n SIZE_DMA_i[1] + Net a_decode_9__n A_DECODE[9] + Net size_dma_i_0__n SIZE_DMA_i[0] + Net a_decode_8__n A_DECODE[8] + Net cpu_est_i_1__n cpu_est_i[1] + Net clk_000_d_1__n CLK_000_D[1] + Net cpu_est_i_2__n cpu_est_i[2] Net a_decode_7__n A_DECODE[7] - Net rst_dly_1__n RST_DLY[1] - Net ahigh_i_30__n AHIGH_i[30] - Net pos_clk_un3_as_030_d0_i_n pos_clk.un3_as_030_d0_i - Net rst_dly_2__n RST_DLY[2] - Net ahigh_i_31__n AHIGH_i[31] + Net clk_000_d_10__n CLK_000_D[10] + Net clk_000_d_11__n CLK_000_D[11] Net a_decode_6__n A_DECODE[6] - Net clk_000_p_sync_0__n CLK_000_P_SYNC[0] - Net ahigh_i_28__n AHIGH_i[28] - Net clk_000_p_sync_1__n CLK_000_P_SYNC[1] - Net ahigh_i_29__n AHIGH_i[29] + Net cpu_est_i_3__n cpu_est_i[3] + Net pos_clk_un6_bg_030_i_n pos_clk.un6_bg_030_i + Net pos_clk_un9_bg_030_0_n pos_clk.un9_bg_030_0 Net a_decode_5__n A_DECODE[5] - Net clk_000_p_sync_2__n CLK_000_P_SYNC[2] - Net ahigh_i_26__n AHIGH_i[26] - Net clk_000_p_sync_3__n CLK_000_P_SYNC[3] - Net ahigh_i_27__n AHIGH_i[27] + Net clk_000_d_0__n CLK_000_D[0] + Net clk_000_d_i_0__n CLK_000_D_i[0] + Net clk_000_d_i_10__n CLK_000_D_i[10] Net a_decode_4__n A_DECODE[4] - Net clk_000_p_sync_4__n CLK_000_P_SYNC[4] - Net ahigh_i_24__n AHIGH_i[24] - Net clk_000_p_sync_5__n CLK_000_P_SYNC[5] - Net ahigh_i_25__n AHIGH_i[25] + Net ipl_d0_0__n IPL_D0[0] + Net ipl_d0_1__n IPL_D0[1] Net a_decode_3__n A_DECODE[3] - Net clk_000_p_sync_6__n CLK_000_P_SYNC[6] - Net clk_000_p_sync_7__n CLK_000_P_SYNC[7] + Net ipl_d0_2__n IPL_D0[2] + Net clk_000_d_2__n CLK_000_D[2] + Net cycle_dma_i_0__n CYCLE_DMA_i[0] Net a_decode_2__n A_DECODE[2] - Net clk_000_p_sync_8__n CLK_000_P_SYNC[8] - Net clk_000_p_sync_9__n CLK_000_P_SYNC[9] - Net clk_000_n_sync_1__n CLK_000_N_SYNC[1] - Net clk_000_n_sync_2__n CLK_000_N_SYNC[2] - Net clk_000_n_sync_3__n CLK_000_N_SYNC[3] - Net clk_000_n_sync_4__n CLK_000_N_SYNC[4] - Net clk_000_n_sync_5__n CLK_000_N_SYNC[5] - Net clk_000_n_sync_6__n CLK_000_N_SYNC[6] + Net clk_000_d_3__n CLK_000_D[3] Net pos_clk_un6_bgack_000_0_n pos_clk.un6_bgack_000_0 - Net clk_000_n_sync_7__n CLK_000_N_SYNC[7] - Net clk_000_n_sync_8__n CLK_000_N_SYNC[8] - Net clk_000_n_sync_9__n CLK_000_N_SYNC[9] - Net clk_000_n_sync_10__n CLK_000_N_SYNC[10] - Net clk_000_n_sync_11__n CLK_000_N_SYNC[11] - Net pos_clk_un5_bgack_030_int_d_n pos_clk.un5_bgack_030_int_d - Net pos_clk_a0_dma_3_n pos_clk.A0_DMA_3 + Net clk_000_d_4__n CLK_000_D[4] + Net ahigh_i_30__n AHIGH_i[30] + Net clk_000_d_5__n CLK_000_D[5] + Net ahigh_i_31__n AHIGH_i[31] + Net pos_clk_size_dma_6_0_0__n pos_clk.SIZE_DMA_6_0[0] + Net clk_000_d_6__n CLK_000_D[6] + Net ahigh_i_28__n AHIGH_i[28] + Net clk_000_d_7__n CLK_000_D[7] + Net ahigh_i_29__n AHIGH_i[29] + Net pos_clk_size_dma_6_0_1__n pos_clk.SIZE_DMA_6_0[1] + Net clk_000_d_8__n CLK_000_D[8] + Net ahigh_i_26__n AHIGH_i[26] + Net clk_000_d_9__n CLK_000_D[9] + Net ahigh_i_27__n AHIGH_i[27] + Net clk_000_d_12__n CLK_000_D[12] + Net ahigh_i_24__n AHIGH_i[24] + Net pos_clk_un6_bg_030_n pos_clk.un6_bg_030 + Net ahigh_i_25__n AHIGH_i[25] + Net pos_clk_ipl_n pos_clk.ipl Net sm_amiga_6__n SM_AMIGA[6] + Net sm_amiga_0__n SM_AMIGA[0] + Net pos_clk_un9_clk_000_pe_0_n pos_clk.un9_clk_000_pe_0 + Net sm_amiga_4__n SM_AMIGA[4] + Net cpu_est_2_0_1__n cpu_est_2_0[1] + Net rst_dly_0__n RST_DLY[0] + Net rst_dly_1__n RST_DLY[1] + Net rst_dly_2__n RST_DLY[2] + Net cpu_est_2_0_2__n cpu_est_2_0[2] Net sm_amiga_1__n SM_AMIGA[1] + Net sm_amiga_5__n SM_AMIGA[5] Net sm_amiga_3__n SM_AMIGA[3] - Net size_c_0__n SIZE_c[0] Net sm_amiga_2__n SM_AMIGA[2] - Net size_0__n SIZE[0] Net pos_clk_ds_000_dma_4_n pos_clk.DS_000_DMA_4 + Net size_c_0__n SIZE_c[0] + Net size_0__n SIZE[0] Net size_c_1__n SIZE_c[1] - Net pos_clk_un5_bgack_030_int_d_i_n pos_clk.un5_bgack_030_int_d_i Net ahigh_c_24__n AHIGH_c[24] - Net pos_clk_un23_bgack_030_int_i_1_0_n pos_clk.un23_bgack_030_int_i_1_0 Net ahigh_24__n AHIGH[24] Net ahigh_c_25__n AHIGH_c[25] Net ahigh_25__n AHIGH[25] @@ -674,17 +566,26 @@ Design 'BUS68030' created Fri Aug 19 00:20:41 2016 Net ahigh_c_29__n AHIGH_c[29] Net ahigh_29__n AHIGH[29] Net ahigh_c_30__n AHIGH_c[30] + Net pos_clk_un23_bgack_030_int_i_0_0_n pos_clk.un23_bgack_030_int_i_0_0 Net ahigh_30__n AHIGH[30] Net ahigh_c_31__n AHIGH_c[31] Net pos_clk_ds_000_dma_4_0_n pos_clk.DS_000_DMA_4_0 - Net pos_clk_size_dma_6_0_1__n pos_clk.SIZE_DMA_6_0[1] - Net pos_clk_size_dma_6_0_0__n pos_clk.SIZE_DMA_6_0[0] - Net un1_amiga_bus_enable_dma_high_0_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0[0] + Net sm_amiga_nss_i_0__n SM_AMIGA_nss_i[0] Net sm_amiga_i_7__n SM_AMIGA_i[7] - Net pos_clk_size_dma_6_0__n pos_clk.SIZE_DMA_6[0] - Net pos_clk_size_dma_6_1__n pos_clk.SIZE_DMA_6[1] - Net pos_clk_un23_bgack_030_int_i_1_n pos_clk.un23_bgack_030_int_i_1 + Net sm_amiga_nss_0_3__n SM_AMIGA_nss_0[3] + Net sm_amiga_nss_2__n SM_AMIGA_nss[2] + Net sm_amiga_nss_3__n SM_AMIGA_nss[3] + Net sm_amiga_nss_4__n SM_AMIGA_nss[4] + Net sm_amiga_nss_5__n SM_AMIGA_nss[5] + Net sm_amiga_nss_6__n SM_AMIGA_nss[6] + Net sm_amiga_nss_7__n SM_AMIGA_nss[7] + Net sm_amiga_nss_0_2__n SM_AMIGA_nss_0[2] + Net sm_amiga_nss_0_4__n SM_AMIGA_nss_0[4] + Net pos_clk_un23_bgack_030_int_i_0_n pos_clk.un23_bgack_030_int_i_0 + Net sm_amiga_nss_0_5__n SM_AMIGA_nss_0[5] + Net sm_amiga_nss_0_6__n SM_AMIGA_nss_0[6] Net a_decode_c_16__n A_DECODE_c[16] + Net sm_amiga_nss_0_7__n SM_AMIGA_nss_0[7] Net a_decode_16__n A_DECODE[16] Net a_decode_c_17__n A_DECODE_c[17] Net a_decode_17__n A_DECODE[17] @@ -692,19 +593,25 @@ Design 'BUS68030' created Fri Aug 19 00:20:41 2016 Net a_decode_18__n A_DECODE[18] Net a_decode_c_19__n A_DECODE_c[19] Net a_decode_19__n A_DECODE[19] + Net ipl_c_i_0__n IPL_c_i[0] Net a_decode_c_20__n A_DECODE_c[20] Net a_decode_20__n A_DECODE[20] Net a_decode_c_21__n A_DECODE_c[21] Net a_decode_21__n A_DECODE[21] Net a_decode_c_22__n A_DECODE_c[22] Net a_decode_22__n A_DECODE[22] + Net sm_amiga_nss_i_0_1_0__n SM_AMIGA_nss_i_0_1[0] Net a_decode_c_23__n A_DECODE_c[23] + Net sm_amiga_nss_i_0_2_0__n SM_AMIGA_nss_i_0_2[0] + Net sm_amiga_nss_i_0_3_0__n SM_AMIGA_nss_i_0_3[0] Net a_c_0__n A_c[0] + Net sm_amiga_nss_i_0_4_0__n SM_AMIGA_nss_i_0_4[0] Net a_0__n A[0] + Net sm_amiga_nss_i_0_5_0__n SM_AMIGA_nss_i_0_5[0] Net a_c_1__n A_c[1] Net pos_clk_un10_sm_amiga_i_1_n pos_clk.un10_sm_amiga_i_1 - Net pos_clk_un23_bgack_030_int_i_1_0_1_n pos_clk.un23_bgack_030_int_i_1_0_1 - Net pos_clk_un23_bgack_030_int_i_1_0_2_n pos_clk.un23_bgack_030_int_i_1_0_2 + Net pos_clk_un23_bgack_030_int_i_0_0_1_n pos_clk.un23_bgack_030_int_i_0_0_1 + Net pos_clk_un23_bgack_030_int_i_0_0_2_n pos_clk.un23_bgack_030_int_i_0_0_2 Net ipl_030_c_0__n IPL_030_c[0] Net ipl_030_0__n IPL_030[0] Net ipl_030_c_1__n IPL_030_c[1] @@ -715,43 +622,78 @@ Design 'BUS68030' created Fri Aug 19 00:20:41 2016 Net ipl_c_1__n IPL_c[1] Net ipl_1__n IPL[1] Net ipl_c_2__n IPL_c[2] - Net pos_clk_un6_bgack_000_n pos_clk.un6_bgack_000 - Net pos_clk_un6_bg_030_1_n pos_clk.un6_bg_030_1 + Net cpu_est_2_2__n cpu_est_2[2] + Net cpu_est_2_1__n cpu_est_2[1] + Net pos_clk_un9_clk_000_pe_n pos_clk.un9_clk_000_pe + Net pos_clk_size_dma_6_1__n pos_clk.SIZE_DMA_6[1] + Net pos_clk_size_dma_6_0__n pos_clk.SIZE_DMA_6[0] Net fc_c_0__n FC_c[0] + Net pos_clk_un6_bg_030_1_n pos_clk.un6_bg_030_1 Net fc_0__n FC[0] + Net pos_clk_un6_bgack_000_n pos_clk.un6_bgack_000 Net fc_c_1__n FC_c[1] - Net pos_clk_un3_as_030_d0_n pos_clk.un3_as_030_d0 + Net pos_clk_un9_bg_030_n pos_clk.un9_bg_030 Net pos_clk_ipl_1_n pos_clk.ipl_1 - Net bg_000_0_un3_n BG_000_0.un3 - Net bg_000_0_un1_n BG_000_0.un1 - Net pos_clk_un6_bg_030_i_n pos_clk.un6_bg_030_i - Net bg_000_0_un0_n BG_000_0.un0 - Net pos_clk_un9_bg_030_0_n pos_clk.un9_bg_030_0 - Net uds_000_int_0_un3_n UDS_000_INT_0.un3 - Net uds_000_int_0_un1_n UDS_000_INT_0.un1 - Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net rw_000_dma_0_un3_n RW_000_DMA_0.un3 + Net rw_000_dma_0_un1_n RW_000_DMA_0.un1 + Net rw_000_dma_0_un0_n RW_000_DMA_0.un0 Net lds_000_int_0_un3_n LDS_000_INT_0.un3 Net lds_000_int_0_un1_n LDS_000_INT_0.un1 Net lds_000_int_0_un0_n LDS_000_INT_0.un0 - Net dsack1_int_0_un3_n DSACK1_INT_0.un3 - Net dsack1_int_0_un1_n DSACK1_INT_0.un1 - Net dsack1_int_0_un0_n DSACK1_INT_0.un0 - Net pos_clk_un4_clk_000_pe_n pos_clk.un4_clk_000_pe - Net ipl_c_i_0__n IPL_c_i[0] - Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 - Net cpu_est_2_1__n cpu_est_2[1] - Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 - Net ipl_c_i_1__n IPL_c_i[1] - Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 - Net ipl_c_i_2__n IPL_c_i[2] Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 - Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 - Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 - Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 - Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 - Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 + Net pos_clk_un3_as_030_d0_n pos_clk.un3_as_030_d0 + Net amiga_bus_enable_dma_high_0_un3_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un3 + Net amiga_bus_enable_dma_high_0_un1_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un1 + Net amiga_bus_enable_dma_high_0_un0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un0 + Net pos_clk_rw_000_int_5_n pos_clk.RW_000_INT_5 + Net ipl_c_i_1__n IPL_c_i[1] + Net amiga_bus_enable_dma_low_0_un3_n AMIGA_BUS_ENABLE_DMA_LOW_0.un3 + Net amiga_bus_enable_dma_low_0_un1_n AMIGA_BUS_ENABLE_DMA_LOW_0.un1 + Net ipl_c_i_2__n IPL_c_i[2] + Net amiga_bus_enable_dma_low_0_un0_n AMIGA_BUS_ENABLE_DMA_LOW_0.un0 + Net pos_clk_a0_dma_3_n pos_clk.A0_DMA_3 + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 + Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 + Net a_c_i_0__n A_c_i[0] + Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 + Net size_c_i_1__n SIZE_c_i[1] + Net un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un3 + Net pos_clk_un10_sm_amiga_i_n pos_clk.un10_sm_amiga_i + Net un1_amiga_bus_enable_dma_high_i_m2_0__un1_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un1 + Net un1_amiga_bus_enable_dma_high_i_m2_0__un0_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un0 + Net as_000_int_0_un3_n AS_000_INT_0.un3 + Net as_000_int_0_un1_n AS_000_INT_0.un1 + Net as_000_int_0_un0_n AS_000_INT_0.un0 + Net ds_000_enable_0_un3_n DS_000_ENABLE_0.un3 + Net ds_000_enable_0_un1_n DS_000_ENABLE_0.un1 + Net ds_000_enable_0_un0_n DS_000_ENABLE_0.un0 + Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 + Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 + Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net rw_000_int_0_un3_n RW_000_INT_0.un3 + Net sm_amiga_i_1__n SM_AMIGA_i[1] + Net rw_000_int_0_un1_n RW_000_INT_0.un1 + Net rw_000_int_0_un0_n RW_000_INT_0.un0 + Net a0_dma_0_un3_n A0_DMA_0.un3 + Net a0_dma_0_un1_n A0_DMA_0.un1 + Net a0_dma_0_un0_n A0_DMA_0.un0 + Net sm_amiga_i_4__n SM_AMIGA_i[4] + Net bg_000_0_un3_n BG_000_0.un3 + Net bg_000_0_un1_n BG_000_0.un1 + Net sm_amiga_i_2__n SM_AMIGA_i[2] + Net bg_000_0_un0_n BG_000_0.un0 + Net size_dma_0_1__un3_n SIZE_DMA_0_1_.un3 + Net size_dma_0_1__un1_n SIZE_DMA_0_1_.un1 + Net size_dma_0_1__un0_n SIZE_DMA_0_1_.un0 + Net size_dma_0_0__un3_n SIZE_DMA_0_0_.un3 + Net size_dma_0_0__un1_n SIZE_DMA_0_0_.un1 + Net size_dma_0_0__un0_n SIZE_DMA_0_0_.un0 + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 End Section Type Name // ---------------------------------------------------------------------- diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 3869487..70cd89e 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Fri Aug 19 00:20:34 2016 +#Fri Aug 19 00:39:28 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -18,17 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000 -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000 +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2 -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2 +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -39,14 +39,14 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:34 2016 +# Fri Aug 19 00:39:28 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -56,7 +56,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:35 2016 +# Fri Aug 19 00:39:29 2016 ###########################################################] Map & Optimize Report @@ -65,7 +65,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -80,15 +80,15 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 88 uses +DFF 63 uses BI_DIR 18 uses BUFTH 4 uses IBUF 38 uses OBUF 15 uses -AND2 301 uses -INV 262 uses -OR2 27 uses -XOR2 7 uses +AND2 295 uses +INV 265 uses +OR2 25 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -98,6 +98,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:36 2016 +# Fri Aug 19 00:39:30 2016 ###########################################################] diff --git a/Logic/dm/BUS68030_comp.xdm b/Logic/dm/BUS68030_comp.xdm index 826a9bc..5b7157f 100644 --- a/Logic/dm/BUS68030_comp.xdm +++ b/Logic/dm/BUS68030_comp.xdm @@ -25,7 +25,7 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S> SRSqS SRSqSSqSSqSSqS"/ diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 2808a7b..1382bf1 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version I-2014.03LC #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Fri Aug 19 00:20:34 2016 +#-- Written on Fri Aug 19 00:39:28 2016 #project files diff --git a/Logic/synlog/BUS68030_multi_srs_gen.srr b/Logic/synlog/BUS68030_multi_srs_gen.srr index 2d21907..f0b5fa1 100644 --- a/Logic/synlog/BUS68030_multi_srs_gen.srr +++ b/Logic/synlog/BUS68030_multi_srs_gen.srr @@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:35 2016 +# Fri Aug 19 00:39:29 2016 ###########################################################] diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index f1af172..3722633 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -17,15 +17,15 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 88 uses +DFF 63 uses BI_DIR 18 uses BUFTH 4 uses IBUF 38 uses OBUF 15 uses -AND2 301 uses -INV 262 uses -OR2 27 uses -XOR2 7 uses +AND2 295 uses +INV 265 uses +OR2 25 uses +XOR2 5 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -35,6 +35,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Fri Aug 19 00:20:36 2016 +# Fri Aug 19 00:39:30 2016 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index 1020aa7..2c21aac 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,8 +2,8 @@ @N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000 +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 90baef6..4991a74 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1471558834 + 1471559968 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index af8fe07..5ca3237 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,9 +1,9 @@ -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2 -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2 +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ... @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index b060c55..a2f4a80 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the 105MB -1471558836 +1471559970 diff --git a/Logic/syntmp/BUS68030_srr.htm b/Logic/syntmp/BUS68030_srr.htm index 3760611..8593217 100644 --- a/Logic/syntmp/BUS68030_srr.htm +++ b/Logic/syntmp/BUS68030_srr.htm @@ -1,5 +1,5 @@ 
-
+
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: E:\ispLEVER_Classic2_0\synpbase
 #OS: Windows 7 6.2
@@ -8,29 +8,29 @@
 #Implementation: logic
 
 $ Start of Compile
-#Fri Aug 19 00:20:34 2016
+#Fri Aug 19 00:39:28 2016
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
-@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
-@N:CD233 : 68030-68000-bus.vhd(71) | Using sequential encoding for type sm_e
-@N:CD233 : 68030-68000-bus.vhd(88) | Using sequential encoding for type sm_68000
-@W:CD638 : 68030-68000-bus.vhd(129) | Signal clk_out_pre is undriven 
+@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
+@N:CD233 : 68030-68000-bus.vhd(69) | Using sequential encoding for type sm_e
+@N:CD233 : 68030-68000-bus.vhd(86) | Using sequential encoding for type sm_68000
+@W:CD638 : 68030-68000-bus.vhd(127) | Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register DS_030_D0_3  
-@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register nEXP_SPACE_D0_3  
-@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_OUT_EXP_INT_1  
-@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_PRE_25_3  
-@W:CL169 : 68030-68000-bus.vhd(163) | Pruning register CLK_030_D0_2  
-@W:CL189 : 68030-68000-bus.vhd(139) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register SM_AMIGA
+@W:CL169 : 68030-68000-bus.vhd(130) | Pruning register DS_030_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(130) | Pruning register nEXP_SPACE_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(129) | Pruning register CLK_OUT_EXP_INT_1  
+@W:CL169 : 68030-68000-bus.vhd(125) | Pruning register CLK_OUT_PRE_25_3  
+@W:CL169 : 68030-68000-bus.vhd(153) | Pruning register CLK_030_D0_2  
+@W:CL189 : 68030-68000-bus.vhd(130) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N:CL201 : 68030-68000-bus.vhd(130) | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -41,24 +41,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register cpu_est
-@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
+@N:CL201 : 68030-68000-bus.vhd(130) | Trying to extract state machine for register cpu_est
+@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
 @END
 
 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Aug 19 00:20:34 2016
+# Fri Aug 19 00:39:28 2016
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Aug 19 00:20:35 2016
+# Fri Aug 19 00:39:29 2016
 
 ###########################################################]
 Map & Optimize Report
@@ -66,8 +66,8 @@ Map & Optimize Report
 Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:MF248 :  | Running in 64-bit mode. 
-@N: : 68030-68000-bus.vhd(139) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+@N:MF248 :  | Running in 64-bit mode. 
+@N: : 68030-68000-bus.vhd(130) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -82,25 +82,25 @@ original code -> new code
 Resource Usage Report
 
 Simple gate primitives:
-DFF             88 uses
+DFF             63 uses
 BI_DIR          18 uses
 BUFTH           4 uses
 IBUF            38 uses
 OBUF            15 uses
-AND2            301 uses
-INV             262 uses
-OR2             27 uses
-XOR2            7 uses
+AND2            295 uses
+INV             265 uses
+OR2             25 uses
+XOR2            5 uses
 
 
-@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Aug 19 00:20:36 2016
+# Fri Aug 19 00:39:30 2016
 
 ###########################################################]
 
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index 78fcf6d..b82dad5 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
 
  • Mapper Report  
 
    • 
-
  • Session Log (00:20 19-Aug)  
+
  • Session Log (00:39 19-Aug)  
 
      •          
         
    
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 6fb15cf..a685b02 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Fri Aug 19 00:20:34 2016
+  Written on Fri Aug 19 00:39:28 2016
 
 
 --> 
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index 346c0e2..42efa7f 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -38,7 +38,7 @@
 -
 0m:00s
 -
-19.08.2016
      00:20:34
+19.08.2016
      00:39:28
  
 
  
@@ -49,12 +49,12 @@
 0m:00s
 0m:00s
 105MB
-19.08.2016
      00:20:36
+19.08.2016
      00:39:30
  
 
 
   Multi-srs Generator
-  Complete0m:00s19.08.2016
      00:20:35 		
+  Complete0m:00s19.08.2016
      00:39:29 		
      
   
  
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index a9765cb..820b344 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -9,7 +9,7 @@
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471558823
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471559957
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index 3dd5757..c306393 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -9,7 +9,7 @@
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471558823
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471559957
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
index 63737dc57464882844302bdb2e9ef361310df514..b5053169d5856acd80f2f753a30ea6fbfaf44626 100644
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diff --git a/Logic/synwork/BUS68030_comp.tlg b/Logic/synwork/BUS68030_comp.tlg
index fcf2754..9e82db4 100644
--- a/Logic/synwork/BUS68030_comp.tlg
+++ b/Logic/synwork/BUS68030_comp.tlg
@@ -1,15 +1,15 @@
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
-@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e
-@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000
-@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven 
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":69:10:69:11|Using sequential encoding for type sm_e
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:14:86:15|Using sequential encoding for type sm_68000
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:17|Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2  
-@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register DS_030_D0_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Pruning register nEXP_SPACE_D0_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_OUT_EXP_INT_1  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:36:125:38|Pruning register CLK_OUT_PRE_25_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":153:2:153:3|Pruning register CLK_030_D0_2  
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -20,5 +20,5 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:38:130:40|Trying to extract state machine for register cpu_est
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
diff --git a/Logic/synwork/BUS68030_mult.srs b/Logic/synwork/BUS68030_mult.srs
index 31f997deaa5782daff22c29af71ab688b730478a..de3b191083b0806310125a3d22c8e3ebb17fd00c 100644
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diff --git a/Logic/synwork/BUS68030_mult_srs/skeleton.srs b/Logic/synwork/BUS68030_mult_srs/skeleton.srs
index 53a8c9a98145372bca8a3d8fe9b309bf76b9035b..868d915127926931eccecb27d29cd1f474b3f13e 100644
GIT binary patch
delta 1154
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diff --git a/Logic/synwork/BUS68030_s.srs b/Logic/synwork/BUS68030_s.srs
index 63737dc57464882844302bdb2e9ef361310df514..b5053169d5856acd80f2f753a30ea6fbfaf44626 100644
GIT binary patch
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