diff --git a/Layout and PCB/68030-TK-V09c.b#1 b/Layout and PCB/68030-TK-V09c.b#1
index 45cfeac..883e4fd 100644
--- a/Layout and PCB/68030-TK-V09c.b#1
+++ b/Layout and PCB/68030-TK-V09c.b#1
@@ -2720,9 +2720,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -4632,6 +4706,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -4654,6 +4730,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -4681,6 +4759,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -4706,6 +4786,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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diff --git a/Layout and PCB/68030-TK-V09c.b#2 b/Layout and PCB/68030-TK-V09c.b#2
index 22573e0..86235c4 100644
--- a/Layout and PCB/68030-TK-V09c.b#2
+++ b/Layout and PCB/68030-TK-V09c.b#2
@@ -2862,6 +2862,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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diff --git a/Layout and PCB/68030-TK-V09c.b#3 b/Layout and PCB/68030-TK-V09c.b#3
new file mode 100644
index 0000000..45cfeac
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09c.b#3
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+TOP
+Bot
+a1k.org 68030-TK v0.9b
+(c) 2013 Matthias
+Heinrichs
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
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+>NAME
+>VALUE
+
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+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09c.b#4 b/Layout and PCB/68030-TK-V09c.b#4
new file mode 100644
index 0000000..22573e0
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09c.b#4
@@ -0,0 +1,8104 @@
+
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+
+
+TOP
+Bot
+a1k.org 68030-TK v0.9b
+(c) 2013 Matthias
+Heinrichs
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
+
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+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
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diff --git a/Layout and PCB/68030-TK-V09c.brd b/Layout and PCB/68030-TK-V09c.brd
index 86235c4..ba49c0c 100644
--- a/Layout and PCB/68030-TK-V09c.brd
+++ b/Layout and PCB/68030-TK-V09c.brd
@@ -2720,9 +2720,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -4108,6 +4138,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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diff --git a/Layout and PCB/68030-TK-V09c.s#1 b/Layout and PCB/68030-TK-V09c.s#1
index a7a04df..60381f9 100644
--- a/Layout and PCB/68030-TK-V09c.s#1
+++ b/Layout and PCB/68030-TK-V09c.s#1
@@ -10071,7 +10071,6 @@ Source: RS Component / Phycomp
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diff --git a/Layout and PCB/68030-TK-V09c.s#2 b/Layout and PCB/68030-TK-V09c.s#2
new file mode 100644
index 0000000..6dbe79e
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09c.s#2
@@ -0,0 +1,14414 @@
+
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+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
+
+
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+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+
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+
+
+>NAME
+>VALUE
+
+
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+
+
+
+
+
+
+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
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+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
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+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
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+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
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+<b>RESISTOR</b>
+
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+>NAME
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+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
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+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
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+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
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+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
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+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
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+
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+
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+
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+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH SERIES</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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diff --git a/Layout and PCB/68030-TK-V09c.s#3 b/Layout and PCB/68030-TK-V09c.s#3
new file mode 100644
index 0000000..a7a04df
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09c.s#3
@@ -0,0 +1,14401 @@
+
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+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
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+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+>NAME
+>VALUE
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+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
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+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
+
+
+
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+
+
+
+
+
+<b>AMD MACH SERIES</b>
+
+
+
+
+
+
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diff --git a/Layout and PCB/68030-TK-V09c.sch b/Layout and PCB/68030-TK-V09c.sch
index 6dbe79e..d105635 100644
--- a/Layout and PCB/68030-TK-V09c.sch
+++ b/Layout and PCB/68030-TK-V09c.sch
@@ -10071,7 +10071,6 @@ Source: RS Component / Phycomp
-
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-
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+
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@@ -10137,7 +10141,6 @@ Source: RS Component / Phycomp
-
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+
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@@ -13712,103 +13663,201 @@ Source: RS Component / Phycomp
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diff --git a/Layout and PCB/68030-TK-V09d.b#1 b/Layout and PCB/68030-TK-V09d.b#1
new file mode 100644
index 0000000..4d3c63e
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#1
@@ -0,0 +1,8260 @@
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
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+
+
+
+
+
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+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
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+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
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+
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+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#2 b/Layout and PCB/68030-TK-V09d.b#2
new file mode 100644
index 0000000..76c1ac4
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#2
@@ -0,0 +1,8278 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#3 b/Layout and PCB/68030-TK-V09d.b#3
new file mode 100644
index 0000000..f1fc0b5
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#3
@@ -0,0 +1,8010 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#4 b/Layout and PCB/68030-TK-V09d.b#4
new file mode 100644
index 0000000..5be233b
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#4
@@ -0,0 +1,8014 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#5 b/Layout and PCB/68030-TK-V09d.b#5
new file mode 100644
index 0000000..4388ab8
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#5
@@ -0,0 +1,8003 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
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+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#6 b/Layout and PCB/68030-TK-V09d.b#6
new file mode 100644
index 0000000..89bf9c4
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#6
@@ -0,0 +1,8250 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#7 b/Layout and PCB/68030-TK-V09d.b#7
new file mode 100644
index 0000000..f46350a
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#7
@@ -0,0 +1,8294 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
+
+
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+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
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+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#8 b/Layout and PCB/68030-TK-V09d.b#8
new file mode 100644
index 0000000..b2000dc
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#8
@@ -0,0 +1,8050 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
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+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
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+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
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+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.b#9 b/Layout and PCB/68030-TK-V09d.b#9
new file mode 100644
index 0000000..9179c88
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.b#9
@@ -0,0 +1,8277 @@
+
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+
+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
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+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
+
+
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+
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+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
+
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+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
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+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
+
+
diff --git a/Layout and PCB/68030-TK-V09d.brd b/Layout and PCB/68030-TK-V09d.brd
new file mode 100644
index 0000000..d619944
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.brd
@@ -0,0 +1,8012 @@
+
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+TOP
+Bot
+a1k.org 68030-TK v0.9d
+(c) 2013 Matthias Heinrichs
+thx Buko Charly
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+
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+
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+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
+
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+
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+
+
+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
+
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+
+
+>NAME
+>VALUE
+
+
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+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
+
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+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+
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+
diff --git a/Layout and PCB/68030-TK-V09d.s#1 b/Layout and PCB/68030-TK-V09d.s#1
new file mode 100644
index 0000000..4ca4fdd
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.s#1
@@ -0,0 +1,14634 @@
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+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+>NAME
+>VALUE
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+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH SERIES</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/Layout and PCB/68030-TK-V09d.s#2 b/Layout and PCB/68030-TK-V09d.s#2
new file mode 100644
index 0000000..eefc953
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.s#2
@@ -0,0 +1,14641 @@
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+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+>NAME
+>VALUE
+
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+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH SERIES</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/Layout and PCB/68030-TK-V09d.s#3 b/Layout and PCB/68030-TK-V09d.s#3
new file mode 100644
index 0000000..cc6c0cf
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.s#3
@@ -0,0 +1,14641 @@
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+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+>NAME
+>VALUE
+
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+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH SERIES</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/Layout and PCB/68030-TK-V09d.sch b/Layout and PCB/68030-TK-V09d.sch
new file mode 100644
index 0000000..d921919
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09d.sch
@@ -0,0 +1,14637 @@
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+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+
+
+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+>NAME
+>VALUE
+
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+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
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+
+
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+
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+
+
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+
+
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+
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+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
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+
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+
+
+
+
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+
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+
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+
+
+
+
+
+
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+
+
+
+
+
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+
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+
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+
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+
+
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+
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+
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+
+
+
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+
+
+
+
+
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+
+
+
+
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+
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+
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+
+
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+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
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+
+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
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+
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+
+
+
+
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+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>AMD MACH SERIES</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd
index 544218b..ad31bea 100644
--- a/Logic/68030-68000-bus.vhd
+++ b/Logic/68030-68000-bus.vhd
@@ -15,6 +15,7 @@ entity BUS68030 is
port(
AS_030: inout std_logic ;
AS_000: inout std_logic ;
+ RW_000: inout std_logic ;
DS_030: inout std_logic ;
UDS_000: inout std_logic;
LDS_000: inout std_logic;
@@ -35,7 +36,7 @@ port(
FPU_CS: out std_logic ;
IPL_030: out std_logic_vector ( 2 downto 0 );
IPL: in std_logic_vector ( 2 downto 0 );
- DSACK: inout std_logic_vector ( 1 downto 0 );
+ DSACK1: inout std_logic;
DTACK: inout std_logic ;
AVEC: out std_logic ;
AVEC_EXP: inout std_logic ; --this is a "free pin"
@@ -44,7 +45,7 @@ port(
VMA: out std_logic ;
RST: in std_logic ;
RESET: out std_logic ;
- RW: in std_logic ;
+ RW: inout std_logic ;
-- D: inout std_logic_vector ( 31 downto 28 );
FC: in std_logic_vector ( 1 downto 0 );
AMIGA_BUS_ENABLE: out std_logic ;
@@ -94,6 +95,8 @@ signal SM_AMIGA : AMIGA_STATE;
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal AS_000_INT:STD_LOGIC := '1';
+signal RW_000_INT:STD_LOGIC := '1';
+signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
signal AS_030_000_SYNC:STD_LOGIC := '1';
signal BGACK_030_INT:STD_LOGIC := '1';
signal BGACK_030_INT_D:STD_LOGIC := '1';
@@ -140,8 +143,8 @@ begin
end if;
end if;
end process neg_clk;
- --the clocks
- clk: process(RST, CLK_OSZI)
+ --the state machine
+ state_machine: process(RST, CLK_OSZI)
begin
if(RST = '0' ) then
CLK_CNT_P <= "00";
@@ -161,6 +164,25 @@ begin
CLK_000_D6 <= '1';
VPA_D <= '1';
DTACK_D0 <= '1';
+ SM_AMIGA <= IDLE_P;
+ AS_000_INT <= '1';
+ RW_000_INT <= '1';
+ AS_030_000_SYNC <= '1';
+ UDS_000_INT <= '1';
+ LDS_000_INT <= '1';
+ CLK_REF <= "00";
+ VMA_INT <= '1';
+ FPU_CS_INT <= '1';
+ BG_000 <= '1';
+ BGACK_030_INT <= '1';
+ BGACK_030_INT_D <= '1';
+ DSACK1_INT <= '1';
+ IPL_030 <= "111";
+ AS_000_DMA <= '1';
+ DS_000_DMA <= '1';
+ SIZE_DMA <= "11";
+ A0_DMA <= '1';
+ AMIGA_BUS_ENABLE_INT <= '1';
elsif(rising_edge(CLK_OSZI)) then
--reset buffer
RESET <= '1';
@@ -187,7 +209,7 @@ begin
-- the external clock to the processor is generated here
CLK_OUT_INT <= CLK_OUT_PRE_25; --this way we know the clock of the next state: Its like looking in the future, cool!
- --delayed Clocks for edge detection
+ --delayed Clocks and signals for edge detection
CLK_000_D0 <= CLK_000;
CLK_000_D1 <= CLK_000_D0;
CLK_000_D2 <= CLK_000_D1;
@@ -198,7 +220,8 @@ begin
DTACK_D0 <= DTACK;
VPA_D <= VPA;
-
+ --now: 68000 state machine and signals
+
-- e-clock
if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then
case (cpu_est) is
@@ -223,35 +246,8 @@ begin
null;
end case;
end if;
- end if;
- end process clk;
- --the state process
- state_machine: process(RST, CLK_OSZI)
- begin
- if(RST = '0' ) then
- SM_AMIGA <= IDLE_P;
- AS_000_INT <= '1';
- AS_030_000_SYNC <= '1';
- UDS_000_INT <= '1';
- LDS_000_INT <= '1';
- CLK_REF <= "00";
- VMA_INT <= '1';
- FPU_CS_INT <= '1';
- BG_000 <= '1';
- BGACK_030_INT <= '1';
- BGACK_030_INT_D <= '1';
- DSACK1_INT <= '1';
- IPL_030 <= "111";
- AMIGA_BUS_ENABLE <= '1' ;
- AS_000_DMA <= '1';
- DS_000_DMA <= '1';
- SIZE_DMA <= "11";
- A0_DMA <= '1';
-
- elsif(rising_edge(CLK_OSZI)) then
-
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
@@ -313,24 +309,27 @@ begin
--Amiga statemachine
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
- --VMA_INT <= '1';
+ AMIGA_BUS_ENABLE_INT <= '1';
+
+
if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then
- SM_AMIGA<=IDLE_N; --go to s1
+
+ if(nEXP_SPACE ='1')then
+ AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
+ SM_AMIGA<=IDLE_N; --go to s1
+ else -- if this a delayed expansion space detection, aboard this cycle!
+ AS_030_000_SYNC <= '1';
+ end if;
end if;
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
- if(nEXP_SPACE ='1')then
- AMIGA_BUS_ENABLE <= CLK_000_D4 ;--for now: allways on for amiga
- else -- if this a delayed expansion space detection, aboard this cycle!
- AS_030_000_SYNC <= '1';
- SM_AMIGA <= IDLE_P; --aboard
- end if;
-
if(CLK_000_D0='1')then --go to s2
SM_AMIGA <= AS_SET_P; --as for amiga set!
+ RW_000_INT <= RW;
end if;
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
- if(CLK_000_D4='1')then
- AS_000_INT <= '0';
+ if(CLK_000_D2='1')then
+ AS_000_INT <= '0';
+
if (RW='1' and DS_030 = '0') then --read: set udl/lds
if(A0='0') then
UDS_000_INT <= '0';
@@ -374,33 +373,28 @@ begin
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
if(CLK_000_D0='1')then --go to s6
SM_AMIGA<=DATA_FETCH_P;
+ DSACK1_INT <='0';
+ AS_030_000_SYNC <= '1'; --cycle end
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
- if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
- DSACK1_INT <='0';
- AS_030_000_SYNC <= '1'; --cycle end
- elsif( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
- --DSACK1_INT<='0';
+ --if( CLK_000_D2 ='1' AND CLK_000_D3 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+
+ --els
+ if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
SM_AMIGA<=END_CYCLE_N;
- --AS_030_000_SYNC <= '1'; --cycle end
- end if;
- if(AS_030 = '1' )then
- AMIGA_BUS_ENABLE <= '1';
end if;
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
- if(AS_030 = '1' )then
- AMIGA_BUS_ENABLE <= '1';
- end if;
- if(CLK_000_D0='1' and AS_000_INT = '1' )then --go to s0
+ if(CLK_000_D0='1')then --go to s0
+ RW_000_INT <= '1';
SM_AMIGA<=IDLE_P;
end if;
end case;
if(BGACK_030_INT='0')then
--switch amiga bus on for DMA-Cycles
- AMIGA_BUS_ENABLE <= '0' ;
+ AMIGA_BUS_ENABLE_INT <= '0' ;
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
- AMIGA_BUS_ENABLE <= '1' ;
+ AMIGA_BUS_ENABLE_INT <= '1' ;
end if;
--dma stuff
@@ -409,14 +403,15 @@ begin
--set AS_000
if( CLK_030='0') then
- AS_000_DMA <= '0';
+ AS_000_DMA <= '0';
+ RW_000_INT <= RW_000;
elsif(AS_000_DMA = '0' and CLK_030='1')then
CLK_030_H <= '1';
end if;
- if(RW='1') then
+ if(RW_000='1') then
DS_000_DMA <=AS_000_DMA;
- elsif(RW='0' and CLK_030_H = '1' and CLK_030='0')then
+ elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='0')then
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
end if;
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
@@ -447,11 +442,11 @@ begin
--output clock assignment
CLK_DIV_OUT <= CLK_OUT_INT;
CLK_EXP <= CLK_OUT_INT;
- AVEC_EXP <= 'Z' when FPU_CS_INT ='1' else '0';
-
+ AVEC_EXP <= AMIGA_BUS_ENABLE_INT;
+ AMIGA_BUS_ENABLE <= AMIGA_BUS_ENABLE_INT;
--dma stuff
DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
- DSACK(1);
+ DSACK1;
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
AS_000_DMA;
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
@@ -494,7 +489,8 @@ begin
--as and uds/lds
AS_000 <= 'Z' when BGACK_030_INT ='0' else
AS_000_INT;
-
+ RW_000 <= 'Z' when BGACK_030_INT ='0' else
+ RW_000_INT;
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
UDS_000_INT;
@@ -502,9 +498,11 @@ begin
LDS_000_INT;
--dsack
- DSACK(1) <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
- DSACK1_INT;
- DSACK(0) <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
- '1';
+ DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle
+ DSACK1_INT;
+ --rw
+ RW <= 'Z' when BGACK_030_INT ='1' else
+ RW_000_INT;
+
BGACK_030 <= BGACK_030_INT;
-end Behavioral;
+end Behavioral;
\ No newline at end of file
diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY
index b246b0a..87516c2 100644
--- a/Logic/68030_TK.STY
+++ b/Logic/68030_TK.STY
@@ -1,4 +1,6 @@
-[STRATEGY-LIST]
-Normal=True, 1385910337
[synthesis-type]
tool=Synplify
+[STRATEGY-LIST]
+Normal=True, 1385910337
+[TOUCHED-REPORT]
+Design.tt4File=1401573640
diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi
index ad1fedc..f537a6f 100644
--- a/Logic/68030_TK.cmi
+++ b/Logic/68030_TK.cmi
@@ -9,7 +9,7 @@ Remember_Setting=1
Open_PV_Opt=2
Open_PV=0
PV_IS_ACTIVE=0
-ACTIVE_SHEET=Global Constraints
+ACTIVE_SHEET=Pin Attributes
Show_Def_Opt=2
Show_Def_Val=1
Expand_All_Column=0
@@ -18,7 +18,7 @@ Sort_Type=0
Sort_Direction=0
Skip_Next_Pin=0
[Pin Attributes]
-sort_column_1=Signal/Group Name
+sort_column_-1=Type
Type=42,no
Signal/Group Name=209,no
Group Members=111,no
diff --git a/Logic/68030_TK.lci b/Logic/68030_TK.lci
index 4342065..b48508e 100644
--- a/Logic/68030_TK.lci
+++ b/Logic/68030_TK.lci
@@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
-DATE = 05/25/2014;
-TIME = 21:04:55;
+DATE = 06/01/2014;
+TIME = 00:00:40;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@@ -36,7 +36,6 @@ Balanced_partitioning = No;
[Location Assignments]
layer = OFF;
AS_030 = Pin, 82, -, H, -;
-A_0_ = Pin, 69, -, G, -;
A_16_ = Pin, 96, -, A, -;
A_17_ = Pin, 59, -, F, -;
A_18_ = Pin, 95, -, A, -;
@@ -46,7 +45,6 @@ BG_030 = Pin, 21, -, C, -;
CLK_000 = Pin, 11, -, -, -;
CLK_030 = Pin, 64, -, -, -;
CLK_OSZI = Pin, 61, -, -, -;
-CPU_SPACE = Pin, 14, -, -, -;
FC_0_ = Pin, 57, -, F, -;
FC_1_ = Pin, 58, -, F, -;
IPL_0_ = Pin, 67, -, G, -;
@@ -62,7 +60,6 @@ BGACK_030 = Pin, 83, -, H, -;
BG_000 = Pin, 29, -, D, -;
CLK_DIV_OUT = Pin, 65, -, G, -;
CLK_EXP = Pin, 10, -, B, -;
-DSACK_0_ = Pin, 80, -, H, -;
E = Pin, 66, -, G, -;
FPU_CS = Pin, 78, -, H, -;
IPL_030_0_ = Pin, 8, -, B, -;
@@ -72,7 +69,6 @@ LDS_000 = Pin, 31, -, D, -;
UDS_000 = Pin, 32, -, D, -;
VMA = Pin, 35, -, D, -;
AS_000 = Pin, 33, -, D, -;
-DSACK_1_ = Pin, 81, -, H, -;
DTACK = Pin, 30, -, D, -;
RESET = Pin, 3, -, B, -;
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
@@ -96,6 +92,8 @@ AVEC_EXP = Pin, 22, -, C, -;
BERR = Pin, 41, -, E, -;
nEXP_SPACE = Pin, 14, -, -, -;
A0 = Pin, 69, -, G, -;
+DSACK1 = Pin, 81, -, H, -;
+RW_000 = Pin, 80, -, H, -;
[Group Assignments]
layer = OFF;
@@ -106,7 +104,7 @@ layer = OFF;
[Fitter Report Format]
[Power]
-Default = Low;
+Default = High;
[Source Constraint Option]
@@ -126,7 +124,7 @@ layer = OFF;
Default = UP;
[Slewrate]
-Default = SLOW;
+Default = Slow;
[Region]
diff --git a/Logic/68030_TK.lct b/Logic/68030_TK.lct
index 4342065..b48508e 100644
--- a/Logic/68030_TK.lct
+++ b/Logic/68030_TK.lct
@@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
-DATE = 05/25/2014;
-TIME = 21:04:55;
+DATE = 06/01/2014;
+TIME = 00:00:40;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@@ -36,7 +36,6 @@ Balanced_partitioning = No;
[Location Assignments]
layer = OFF;
AS_030 = Pin, 82, -, H, -;
-A_0_ = Pin, 69, -, G, -;
A_16_ = Pin, 96, -, A, -;
A_17_ = Pin, 59, -, F, -;
A_18_ = Pin, 95, -, A, -;
@@ -46,7 +45,6 @@ BG_030 = Pin, 21, -, C, -;
CLK_000 = Pin, 11, -, -, -;
CLK_030 = Pin, 64, -, -, -;
CLK_OSZI = Pin, 61, -, -, -;
-CPU_SPACE = Pin, 14, -, -, -;
FC_0_ = Pin, 57, -, F, -;
FC_1_ = Pin, 58, -, F, -;
IPL_0_ = Pin, 67, -, G, -;
@@ -62,7 +60,6 @@ BGACK_030 = Pin, 83, -, H, -;
BG_000 = Pin, 29, -, D, -;
CLK_DIV_OUT = Pin, 65, -, G, -;
CLK_EXP = Pin, 10, -, B, -;
-DSACK_0_ = Pin, 80, -, H, -;
E = Pin, 66, -, G, -;
FPU_CS = Pin, 78, -, H, -;
IPL_030_0_ = Pin, 8, -, B, -;
@@ -72,7 +69,6 @@ LDS_000 = Pin, 31, -, D, -;
UDS_000 = Pin, 32, -, D, -;
VMA = Pin, 35, -, D, -;
AS_000 = Pin, 33, -, D, -;
-DSACK_1_ = Pin, 81, -, H, -;
DTACK = Pin, 30, -, D, -;
RESET = Pin, 3, -, B, -;
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
@@ -96,6 +92,8 @@ AVEC_EXP = Pin, 22, -, C, -;
BERR = Pin, 41, -, E, -;
nEXP_SPACE = Pin, 14, -, -, -;
A0 = Pin, 69, -, G, -;
+DSACK1 = Pin, 81, -, H, -;
+RW_000 = Pin, 80, -, H, -;
[Group Assignments]
layer = OFF;
@@ -106,7 +104,7 @@ layer = OFF;
[Fitter Report Format]
[Power]
-Default = Low;
+Default = High;
[Source Constraint Option]
@@ -126,7 +124,7 @@ layer = OFF;
Default = UP;
[Slewrate]
-Default = SLOW;
+Default = Slow;
[Region]
diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl
index c1a8af5..aac282c 100644
--- a/Logic/68030_TK.tcl
+++ b/Logic/68030_TK.tcl
@@ -176803,3 +176803,9285 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
########## Tcl recorder end at 05/29/14 22:04:20 ###########
+
+########## Tcl recorder starts at 05/30/14 20:59:21 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 20:59:21 ###########
+
+
+########## Tcl recorder starts at 05/30/14 20:59:22 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 20:59:22 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:04:48 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:04:48 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:04:48 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:04:48 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:06:10 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:06:10 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:06:10 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:06:10 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:08:51 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:08:51 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:08:52 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:08:52 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:11:10 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:11:10 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:11:10 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:11:10 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:12:08 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:12:08 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:12:08 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:12:08 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:13:21 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:13:21 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:13:21 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:13:21 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:14:43 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:14:43 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:14:43 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:14:43 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:15:29 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:15:29 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:15:30 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:15:30 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:16:46 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:16:46 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:16:46 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:16:46 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:17:55 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:17:55 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:17:55 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:17:55 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:18:50 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:18:50 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:18:51 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:18:51 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:19:29 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:19:29 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:19:29 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:19:29 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:21:49 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:21:49 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:21:49 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:21:49 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:24:49 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:24:49 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:24:49 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:24:49 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:27:29 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:27:29 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:27:29 ##########
+
+# Commands to make the Process:
+# Post-Fit Pinouts
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+# Application to view the Process:
+# Post-Fit Pinouts
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+ puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+ puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -postfit -lci 68030_tk.lco
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:27:29 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:28:35 ##########
+
+# Commands to make the Process:
+# Constraint Editor
+# - none -
+# Application to view the Process:
+# Constraint Editor
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+ puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+ puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:28:35 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:28:59 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:28:59 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:29:31 ##########
+
+# Commands to make the Process:
+# Constraint Editor
+# - none -
+# Application to view the Process:
+# Constraint Editor
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+ puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+ puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:29:31 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:29:44 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:29:44 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:31:33 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:31:33 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:31:34 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:31:34 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:33:50 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:33:50 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:33:51 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:33:51 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:37:13 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:37:13 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:37:13 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:37:13 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:39:27 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:39:27 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:39:27 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:39:27 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:41:02 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:41:02 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:41:02 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:41:02 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:44:52 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:44:52 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:44:52 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:44:52 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:45:08 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:45:08 ###########
+
+
+########## Tcl recorder starts at 05/30/14 21:45:08 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/30/14 21:45:08 ###########
+
+
+########## Tcl recorder starts at 05/31/14 10:54:44 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 10:54:44 ###########
+
+
+########## Tcl recorder starts at 05/31/14 10:54:44 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 10:54:44 ###########
+
+
+########## Tcl recorder starts at 05/31/14 10:55:59 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 10:55:59 ###########
+
+
+########## Tcl recorder starts at 05/31/14 10:56:00 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 10:56:00 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:30:31 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:30:31 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:30:31 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:30:31 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:33:47 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:33:47 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:33:47 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:33:47 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:39:30 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:39:30 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:39:30 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:39:30 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:47:46 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:47:46 ###########
+
+
+########## Tcl recorder starts at 05/31/14 20:47:46 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 20:47:46 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:18:37 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:18:37 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:18:37 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:18:37 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:19:31 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:19:31 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:19:31 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:19:31 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:20:19 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:20:19 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:20:19 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:20:19 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:20:46 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:20:46 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:20:46 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:20:46 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:21:07 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:21:07 ###########
+
+
+########## Tcl recorder starts at 05/31/14 21:21:07 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 21:21:07 ###########
+
+
+########## Tcl recorder starts at 05/31/14 23:57:54 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 23:57:54 ###########
+
+
+########## Tcl recorder starts at 05/31/14 23:57:54 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 23:57:54 ###########
+
+
+########## Tcl recorder starts at 05/31/14 23:59:00 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 23:59:00 ###########
+
+
+########## Tcl recorder starts at 05/31/14 23:59:00 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 23:59:00 ###########
+
+
+########## Tcl recorder starts at 05/31/14 23:59:15 ##########
+
+# Commands to make the Process:
+# Constraint Editor
+# - none -
+# Application to view the Process:
+# Constraint Editor
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+ puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+ puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/31/14 23:59:15 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:00:44 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:00:44 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:06:22 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:06:22 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:06:22 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:06:22 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:06:37 ##########
+
+# Commands to make the Process:
+# Constraint Editor
+# - none -
+# Application to view the Process:
+# Constraint Editor
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+ puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+ puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:06:37 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:11:31 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:11:31 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:11:32 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:11:32 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:19:48 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:19:48 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:19:48 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:19:48 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:21:50 ##########
+
+# Commands to make the Process:
+# Constraint Editor
+# - none -
+# Application to view the Process:
+# Constraint Editor
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+ puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+ puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:21:50 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:30:48 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:30:48 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:30:48 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:30:48 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:32:36 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:32:36 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:32:36 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:32:36 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:34:43 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:34:43 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:34:43 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:34:43 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:40:33 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:40:33 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:40:33 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:40:33 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:44:45 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:44:45 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:44:46 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:44:46 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:48:59 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:48:59 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:48:59 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:48:59 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:54:24 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:54:24 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:54:24 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:54:24 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:59:20 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:59:20 ###########
+
+
+########## Tcl recorder starts at 06/01/14 00:59:20 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 00:59:20 ###########
+
+
+########## Tcl recorder starts at 06/01/14 01:02:48 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 01:02:48 ###########
+
+
+########## Tcl recorder starts at 06/01/14 01:02:48 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 01:02:48 ###########
+
+
+########## Tcl recorder starts at 06/01/14 01:03:17 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 01:03:17 ###########
+
+
+########## Tcl recorder starts at 06/01/14 01:03:17 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 06/01/14 01:03:18 ###########
+
diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2
index 441a058..bdff8d8 100644
--- a/Logic/68030_tk.bl2
+++ b/Logic/68030_tk.bl2
@@ -1,175 +1,176 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ \
-# IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 \
-# UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
-# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \
-# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
-# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 405 CLK_030_c CLK_000_c CLK_OSZI_c inst_BGACK_030_INTreg CLK_OUT_INTreg \
-# inst_FPU_CS_INTreg inst_VMA_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg \
-# inst_BGACK_030_INT_D inst_AS_000_DMA IPL_030DFFSH_1_reg inst_VPA_D \
-# inst_CLK_OUT_PRE_50_D IPL_030DFFSH_2_reg inst_CLK_000_D0 inst_CLK_000_D1 \
-# ipl_c_0__n inst_CLK_000_D2 inst_CLK_000_D4 ipl_c_1__n inst_DTACK_D0 \
-# inst_CLK_OUT_PRE_50 ipl_c_2__n inst_CLK_OUT_PRE_25 vcc_n_n gnd_n_n dsack_c_1__n \
-# state_machine_un13_clk_000_d0_n inst_AS_000_INT SM_AMIGA_1_ SM_AMIGA_0_ \
-# SM_AMIGA_6_ SM_AMIGA_5_ inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \
-# clk_un3_clk_out_pre_50_n RST_c inst_CLK_000_D3 inst_CLK_030_H RESETDFFRHreg \
-# state_machine_un6_bgack_000_n state_machine_un15_clk_000_d0_n RW_c \
-# inst_DS_000_DMA SIZE_DMA_0_ fc_c_0__n SIZE_DMA_1_ inst_A0_DMA fc_c_1__n SM_AMIGA_7_ \
-# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 AMIGA_BUS_ENABLEDFFSHreg SM_AMIGA_4_ \
-# AMIGA_BUS_DATA_DIR_c state_machine_ds_000_dma_3_n SM_AMIGA_3_ SM_AMIGA_2_ \
-# cpu_est_ns_0_1__n state_machine_un10_bg_030_n N_134_i \
-# state_machine_lds_000_int_7_n N_169_i state_machine_uds_000_int_7_n N_133_i \
-# N_167_i N_51_0 N_140_i N_202_0 N_86_0 N_171_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 \
-# N_82_i sm_amiga_i_1__n N_78_i N_170_i N_77_0 CLK_000_D1_i CLK_OUT_PRE_25_0 N_76_i \
-# N_74_i N_72_0 AS_030_000_SYNC_i CLK_000_D2_i \
-# state_machine_un8_bgack_030_int_i_0_0_n cpu_est_0_ N_69_i cpu_est_1_ AS_030_c_i \
-# cpu_est_2_ N_65_i cpu_est_3_reg N_64_i N_62_i N_152_i N_153_i cpu_est_ns_1__n N_61_0 \
-# cpu_est_ns_2__n N_150_i state_machine_un8_bgack_030_int_i_0_n N_148_i N_197 N_149_i \
-# N_198 N_199 N_123_i N_200 N_145_i N_201 N_146_i sm_amiga_ns_0_0__n N_51 N_142_i N_53 \
-# N_143_i N_61 N_144_i N_62 cpu_est_ns_0_2__n N_64 N_141_i N_65 N_53_0 N_66 N_139_i N_69 \
-# state_machine_amiga_bus_enable_4_iv_i_n N_72 N_138_i N_74 N_48_i N_76 N_136_i N_77 \
-# N_137_i N_78 AMIGA_BUS_DATA_DIR_c_0 N_82 N_135_i N_86 N_168_i N_202 N_151_i N_203 \
-# N_132_i N_205 N_164_i N_206 N_115 N_130_i N_116 N_131_i N_117 N_41_0 N_118 N_128_i N_120 \
-# N_129_i N_121 sm_amiga_ns_0_5__n N_122 N_126_i N_123 N_127_i N_124 N_125 N_125_i N_126 \
-# N_127 N_124_i N_128 N_129 N_122_i N_130 N_131 N_172_i N_132 \
-# state_machine_size_dma_4_0_1__n N_133 state_machine_ds_000_dma_3_0_n N_134 N_66_i \
-# N_135 N_120_i N_136 state_machine_lds_000_int_7_0_n N_137 \
-# state_machine_uds_000_int_7_0_n N_138 N_118_i N_139 N_201_0 N_140 N_117_i N_141 \
-# N_200_0 N_142 N_115_i N_143 N_116_i N_144 N_199_0 N_145 BG_030_c_i N_146 N_206_i N_147 \
-# state_machine_un10_bg_030_0_n N_148 N_198_0 N_149 N_197_0 N_150 N_203_i N_152 \
-# state_machine_un13_clk_000_d0_i_n N_153 state_machine_un15_clk_000_d0_0_n N_164 \
-# state_machine_un6_bgack_000_0_n N_167 N_225_1 N_168 N_225_2 N_169 N_225_3 N_170 \
-# N_225_4 N_171 N_225_5 N_172 N_225_6 N_173 N_228_1 N_225 N_228_2 N_228 N_69_i_1 \
-# CLK_000_D0_i N_69_i_2 BGACK_030_INT_i N_69_i_3 CLK_030_i N_69_i_4 cpu_est_i_3__n \
-# N_69_i_5 sm_amiga_i_6__n state_machine_un8_bgack_030_int_i_0_0_1_n nEXP_SPACE_i \
-# N_72_0_1 CLK_000_D4_i N_51_0_1 sm_amiga_i_5__n N_51_0_2 sm_amiga_i_4__n \
-# cpu_est_ns_0_1_1__n AS_000_i cpu_est_ns_0_2_1__n LDS_000_i N_128_1 UDS_000_i N_128_2 \
-# cpu_est_i_1__n N_118_1 cpu_est_i_0__n N_118_2 DTACK_D0_i N_118_3 VMA_INT_i N_206_1 \
-# VPA_D_i N_206_2 AS_000_DMA_i sm_amiga_ns_0_1_0__n CLK_030_H_i cpu_est_ns_0_1_2__n \
-# RW_i N_53_0_1 cpu_est_i_2__n N_43_i_1 sm_amiga_i_0__n \
-# state_machine_lds_000_int_7_0_1_n sm_amiga_i_3__n \
-# state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_199_0_1 A0_i N_152_1 \
-# size_i_1__n N_147_1 DS_030_i N_139_1 a_i_19__n N_137_1 a_i_16__n N_127_1 a_i_18__n \
-# N_120_1 a_i_30__n state_machine_a0_dma_2_1_n a_i_31__n N_116_1 a_i_28__n N_115_1 \
-# a_i_29__n state_machine_un13_clk_000_d0_1_n a_i_26__n N_203_1 a_i_27__n \
-# state_machine_uds_000_int_7_0_m3_un3_n a_i_24__n \
-# state_machine_uds_000_int_7_0_m3_un1_n a_i_25__n \
-# state_machine_uds_000_int_7_0_m3_un0_n RST_i dsack1_int_0_un3_n \
-# dsack1_int_0_un1_n dsack1_int_0_un0_n N_205_i vma_int_0_un3_n FPU_CS_INT_i \
-# vma_int_0_un1_n CLK_OUT_PRE_50_D_i vma_int_0_un0_n AS_030_c bgack_030_int_0_un3_n \
-# bgack_030_int_0_un1_n AS_000_c bgack_030_int_0_un0_n ipl_030_0_0__un3_n DS_030_c \
+#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ \
+# IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 \
+# IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 \
+# CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET \
+# RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
+# A_28_ A_27_
+#$ NODES 410 BG_030_c BG_000DFFSHreg inst_BGACK_030_INTreg BGACK_000_c \
+# inst_FPU_CS_INTreg inst_avec_expreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC \
+# CLK_000_c inst_BGACK_030_INT_D inst_AS_000_DMA CLK_OSZI_c inst_VPA_D \
+# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 \
+# inst_CLK_000_D2 inst_DTACK_D0 IPL_030DFFSH_0_reg inst_CLK_OUT_PRE_50 \
+# inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ vcc_n_n IPL_030DFFSH_2_reg \
+# gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n inst_AS_000_INT SM_AMIGA_6_ \
+# ipl_c_1__n SM_AMIGA_0_ SM_AMIGA_5_ ipl_c_2__n SM_AMIGA_2_ inst_RW_000_INT DSACK1_c \
+# inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \
+# state_machine_un3_clk_out_pre_50_n inst_CLK_000_D3 inst_CLK_030_H \
+# state_machine_un12_clk_000_d0_n inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ RST_c \
+# inst_A0_DMA AMIGA_BUS_ENABLE_INT_2_sqmuxa RESETDFFRHreg SM_AMIGA_4_ SM_AMIGA_3_ \
+# RW_c SM_AMIGA_1_ un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n \
+# state_machine_un10_bg_030_n state_machine_lds_000_int_7_n \
+# state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c \
+# state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i N_197_0 \
+# state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n N_130_i \
+# N_131_i CLK_OUT_PRE_25_0 N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \
+# cpu_est_0_ N_140_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_141_i \
+# cpu_est_3_reg N_52_i N_143_i N_142_i state_machine_rw_000_int_7_iv_i_n \
+# cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i \
+# N_30 N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n \
+# N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i \
+# N_79 N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i N_115 \
+# un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 N_71_i \
+# N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 N_145_i N_132 N_146_i \
+# N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 N_142 N_138_i N_144 \
+# N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 \
+# N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 \
+# state_machine_uds_000_int_7_0_n N_168 N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 \
+# N_220 N_117_i N_230 N_118_i N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i \
+# N_201 N_115_i N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \
+# state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n N_134 \
+# N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 state_machine_ds_000_dma_3_n \
+# N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n \
+# N_230_1 N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 \
+# sm_amiga_i_4__n N_230_6 sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n \
+# cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n \
+# N_122_3 RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \
+# DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \
+# N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \
+# sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \
+# state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 \
+# cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 VPA_D_i N_132_1 \
+# AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 \
+# A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i \
+# AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n bgack_030_int_0_un3_n \
+# a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n \
+# as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n \
+# a_i_25__n ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n \
+# clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n \
+# CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n \
+# rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n \
+# state_machine_uds_000_int_7_0_m3_un1_n RW_000_c \
+# state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \
# ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \
# ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \
# ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \
# cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \
# cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n \
-# a_c_19__n cpu_estse_2_un0_n amiga_bus_enable_0_un3_n a_c_20__n \
-# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_21__n \
-# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_22__n as_030_000_sync_0_un0_n \
-# clk_030_h_0_un3_n a_c_23__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_24__n \
-# uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_25__n uds_000_int_0_un0_n \
-# lds_000_int_0_un3_n a_c_26__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_27__n \
-# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_28__n fpu_cs_int_0_un0_n bg_000_0_un3_n \
-# a_c_29__n bg_000_0_un1_n bg_000_0_un0_n a_c_30__n ds_000_dma_0_un3_n \
-# ds_000_dma_0_un1_n a_c_31__n ds_000_dma_0_un0_n as_000_dma_0_un3_n A0_c \
-# as_000_dma_0_un1_n as_000_dma_0_un0_n nEXP_SPACE_c as_000_int_0_un3_n \
-# as_000_int_0_un1_n as_000_int_0_un0_n BG_030_c BG_000DFFSHreg BGACK_000_c
+# a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_20__n \
+# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n \
+# uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_23__n \
+# lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n \
+# fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n \
+# avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n \
+# bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \
+# a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n \
+# vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
-RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
-A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \
-A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF \
-DSACK_1_.BLIF AS_030.BLIF AS_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF \
-A0.BLIF DTACK.BLIF SIZE_0_.BLIF DSACK_0_.BLIF CLK_030_c.BLIF CLK_000_c.BLIF \
-CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.BLIF CLK_OUT_INTreg.BLIF \
-inst_FPU_CS_INTreg.BLIF inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
-IPL_030DFFSH_0_reg.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \
-IPL_030DFFSH_1_reg.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF \
-IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
-ipl_c_0__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D4.BLIF ipl_c_1__n.BLIF \
-inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF ipl_c_2__n.BLIF \
-inst_CLK_OUT_PRE_25.BLIF vcc_n_n.BLIF gnd_n_n.BLIF dsack_c_1__n.BLIF \
-state_machine_un13_clk_000_d0_n.BLIF inst_AS_000_INT.BLIF SM_AMIGA_1_.BLIF \
-SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF inst_UDS_000_INT.BLIF \
-inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF clk_un3_clk_out_pre_50_n.BLIF \
-RST_c.BLIF inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF RESETDFFRHreg.BLIF \
-state_machine_un6_bgack_000_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \
-RW_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF fc_c_0__n.BLIF \
-SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF fc_c_1__n.BLIF SM_AMIGA_7_.BLIF \
-un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF \
-SM_AMIGA_4_.BLIF AMIGA_BUS_DATA_DIR_c.BLIF state_machine_ds_000_dma_3_n.BLIF \
-SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF cpu_est_ns_0_1__n.BLIF \
-state_machine_un10_bg_030_n.BLIF N_134_i.BLIF \
-state_machine_lds_000_int_7_n.BLIF N_169_i.BLIF \
-state_machine_uds_000_int_7_n.BLIF N_133_i.BLIF N_167_i.BLIF N_51_0.BLIF \
-N_140_i.BLIF N_202_0.BLIF N_86_0.BLIF N_171_i.BLIF \
-un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_82_i.BLIF sm_amiga_i_1__n.BLIF \
-N_78_i.BLIF N_170_i.BLIF N_77_0.BLIF CLK_000_D1_i.BLIF CLK_OUT_PRE_25_0.BLIF \
-N_76_i.BLIF N_74_i.BLIF N_72_0.BLIF AS_030_000_SYNC_i.BLIF CLK_000_D2_i.BLIF \
-state_machine_un8_bgack_030_int_i_0_0_n.BLIF cpu_est_0_.BLIF N_69_i.BLIF \
-cpu_est_1_.BLIF AS_030_c_i.BLIF cpu_est_2_.BLIF N_65_i.BLIF cpu_est_3_reg.BLIF \
-N_64_i.BLIF N_62_i.BLIF N_152_i.BLIF N_153_i.BLIF cpu_est_ns_1__n.BLIF \
-N_61_0.BLIF cpu_est_ns_2__n.BLIF N_150_i.BLIF \
-state_machine_un8_bgack_030_int_i_0_n.BLIF N_148_i.BLIF N_197.BLIF \
-N_149_i.BLIF N_198.BLIF N_199.BLIF N_123_i.BLIF N_200.BLIF N_145_i.BLIF \
-N_201.BLIF N_146_i.BLIF sm_amiga_ns_0_0__n.BLIF N_51.BLIF N_142_i.BLIF \
-N_53.BLIF N_143_i.BLIF N_61.BLIF N_144_i.BLIF N_62.BLIF cpu_est_ns_0_2__n.BLIF \
-N_64.BLIF N_141_i.BLIF N_65.BLIF N_53_0.BLIF N_66.BLIF N_139_i.BLIF N_69.BLIF \
-state_machine_amiga_bus_enable_4_iv_i_n.BLIF N_72.BLIF N_138_i.BLIF N_74.BLIF \
-N_48_i.BLIF N_76.BLIF N_136_i.BLIF N_77.BLIF N_137_i.BLIF N_78.BLIF \
-AMIGA_BUS_DATA_DIR_c_0.BLIF N_82.BLIF N_135_i.BLIF N_86.BLIF N_168_i.BLIF \
-N_202.BLIF N_151_i.BLIF N_203.BLIF N_132_i.BLIF N_205.BLIF N_164_i.BLIF \
-N_206.BLIF N_115.BLIF N_130_i.BLIF N_116.BLIF N_131_i.BLIF N_117.BLIF \
-N_41_0.BLIF N_118.BLIF N_128_i.BLIF N_120.BLIF N_129_i.BLIF N_121.BLIF \
-sm_amiga_ns_0_5__n.BLIF N_122.BLIF N_126_i.BLIF N_123.BLIF N_127_i.BLIF \
-N_124.BLIF N_125.BLIF N_125_i.BLIF N_126.BLIF N_127.BLIF N_124_i.BLIF \
-N_128.BLIF N_129.BLIF N_122_i.BLIF N_130.BLIF N_131.BLIF N_172_i.BLIF \
-N_132.BLIF state_machine_size_dma_4_0_1__n.BLIF N_133.BLIF \
-state_machine_ds_000_dma_3_0_n.BLIF N_134.BLIF N_66_i.BLIF N_135.BLIF \
-N_120_i.BLIF N_136.BLIF state_machine_lds_000_int_7_0_n.BLIF N_137.BLIF \
-state_machine_uds_000_int_7_0_n.BLIF N_138.BLIF N_118_i.BLIF N_139.BLIF \
-N_201_0.BLIF N_140.BLIF N_117_i.BLIF N_141.BLIF N_200_0.BLIF N_142.BLIF \
-N_115_i.BLIF N_143.BLIF N_116_i.BLIF N_144.BLIF N_199_0.BLIF N_145.BLIF \
-BG_030_c_i.BLIF N_146.BLIF N_206_i.BLIF N_147.BLIF \
-state_machine_un10_bg_030_0_n.BLIF N_148.BLIF N_198_0.BLIF N_149.BLIF \
-N_197_0.BLIF N_150.BLIF N_203_i.BLIF N_152.BLIF \
-state_machine_un13_clk_000_d0_i_n.BLIF N_153.BLIF \
-state_machine_un15_clk_000_d0_0_n.BLIF N_164.BLIF \
-state_machine_un6_bgack_000_0_n.BLIF N_167.BLIF N_225_1.BLIF N_168.BLIF \
-N_225_2.BLIF N_169.BLIF N_225_3.BLIF N_170.BLIF N_225_4.BLIF N_171.BLIF \
-N_225_5.BLIF N_172.BLIF N_225_6.BLIF N_173.BLIF N_228_1.BLIF N_225.BLIF \
-N_228_2.BLIF N_228.BLIF N_69_i_1.BLIF CLK_000_D0_i.BLIF N_69_i_2.BLIF \
-BGACK_030_INT_i.BLIF N_69_i_3.BLIF CLK_030_i.BLIF N_69_i_4.BLIF \
-cpu_est_i_3__n.BLIF N_69_i_5.BLIF sm_amiga_i_6__n.BLIF \
-state_machine_un8_bgack_030_int_i_0_0_1_n.BLIF nEXP_SPACE_i.BLIF N_72_0_1.BLIF \
-CLK_000_D4_i.BLIF N_51_0_1.BLIF sm_amiga_i_5__n.BLIF N_51_0_2.BLIF \
-sm_amiga_i_4__n.BLIF cpu_est_ns_0_1_1__n.BLIF AS_000_i.BLIF \
-cpu_est_ns_0_2_1__n.BLIF LDS_000_i.BLIF N_128_1.BLIF UDS_000_i.BLIF \
-N_128_2.BLIF cpu_est_i_1__n.BLIF N_118_1.BLIF cpu_est_i_0__n.BLIF N_118_2.BLIF \
-DTACK_D0_i.BLIF N_118_3.BLIF VMA_INT_i.BLIF N_206_1.BLIF VPA_D_i.BLIF \
-N_206_2.BLIF AS_000_DMA_i.BLIF sm_amiga_ns_0_1_0__n.BLIF CLK_030_H_i.BLIF \
-cpu_est_ns_0_1_2__n.BLIF RW_i.BLIF N_53_0_1.BLIF cpu_est_i_2__n.BLIF \
-N_43_i_1.BLIF sm_amiga_i_0__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF \
-sm_amiga_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF \
-sm_amiga_i_7__n.BLIF N_199_0_1.BLIF A0_i.BLIF N_152_1.BLIF size_i_1__n.BLIF \
-N_147_1.BLIF DS_030_i.BLIF N_139_1.BLIF a_i_19__n.BLIF N_137_1.BLIF \
-a_i_16__n.BLIF N_127_1.BLIF a_i_18__n.BLIF N_120_1.BLIF a_i_30__n.BLIF \
-state_machine_a0_dma_2_1_n.BLIF a_i_31__n.BLIF N_116_1.BLIF a_i_28__n.BLIF \
-N_115_1.BLIF a_i_29__n.BLIF state_machine_un13_clk_000_d0_1_n.BLIF \
-a_i_26__n.BLIF N_203_1.BLIF a_i_27__n.BLIF \
-state_machine_uds_000_int_7_0_m3_un3_n.BLIF a_i_24__n.BLIF \
-state_machine_uds_000_int_7_0_m3_un1_n.BLIF a_i_25__n.BLIF \
-state_machine_uds_000_int_7_0_m3_un0_n.BLIF RST_i.BLIF dsack1_int_0_un3_n.BLIF \
-dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_205_i.BLIF \
-vma_int_0_un3_n.BLIF FPU_CS_INT_i.BLIF vma_int_0_un1_n.BLIF \
-CLK_OUT_PRE_50_D_i.BLIF vma_int_0_un0_n.BLIF AS_030_c.BLIF \
-bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF AS_000_c.BLIF \
-bgack_030_int_0_un0_n.BLIF ipl_030_0_0__un3_n.BLIF DS_030_c.BLIF \
-ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF \
+A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
+A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
+A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \
+AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \
+DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \
+inst_BGACK_030_INTreg.BLIF BGACK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \
+inst_avec_expreg.BLIF CLK_030_c.BLIF inst_VMA_INTreg.BLIF \
+inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_AS_000_DMA.BLIF CLK_OSZI_c.BLIF inst_VPA_D.BLIF \
+inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF \
+inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF \
+IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF \
+IPL_030DFFSH_1_reg.BLIF SM_AMIGA_7_.BLIF vcc_n_n.BLIF IPL_030DFFSH_2_reg.BLIF \
+gnd_n_n.BLIF state_machine_un10_clk_000_d0_n.BLIF ipl_c_0__n.BLIF \
+inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF ipl_c_1__n.BLIF SM_AMIGA_0_.BLIF \
+SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF \
+DSACK1_c.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \
+state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D3.BLIF \
+inst_CLK_030_H.BLIF state_machine_un12_clk_000_d0_n.BLIF inst_DS_000_DMA.BLIF \
+SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF RST_c.BLIF inst_A0_DMA.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF \
+SM_AMIGA_3_.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF un1_DSACK1_INT_0_sqmuxa_3.BLIF \
+fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un10_bg_030_n.BLIF \
+state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \
+AMIGA_BUS_DATA_DIR_c.BLIF state_machine_un6_bgack_000_0_n.BLIF N_194_0.BLIF \
+N_119_i.BLIF N_120_i.BLIF N_197_0.BLIF state_machine_ds_000_dma_3_0_n.BLIF \
+N_171_i.BLIF state_machine_size_dma_4_0_1__n.BLIF N_130_i.BLIF N_131_i.BLIF \
+CLK_OUT_PRE_25_0.BLIF N_132_i.BLIF N_133_i.BLIF N_134_i.BLIF \
+sm_amiga_ns_0_5__n.BLIF N_135_i.BLIF N_139_i.BLIF cpu_est_0_.BLIF N_140_i.BLIF \
+cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_141_i.BLIF \
+cpu_est_3_reg.BLIF N_52_i.BLIF N_143_i.BLIF N_142_i.BLIF \
+state_machine_rw_000_int_7_iv_i_n.BLIF cpu_est_ns_1__n.BLIF N_62_0.BLIF \
+cpu_est_ns_2__n.BLIF N_161_i.BLIF N_193.BLIF N_155_i.BLIF N_196.BLIF \
+N_63_0.BLIF N_28.BLIF N_66_i.BLIF N_30.BLIF N_76_i.BLIF N_55.BLIF \
+CLK_000_D1_i.BLIF N_62.BLIF N_77_i.BLIF N_63.BLIF N_79_0.BLIF N_66.BLIF \
+N_199_0.BLIF N_67.BLIF sm_amiga_i_2__n.BLIF N_69.BLIF N_201_0.BLIF N_70.BLIF \
+N_203_0.BLIF N_71.BLIF cpu_est_ns_0_1__n.BLIF N_75.BLIF N_167_i.BLIF N_76.BLIF \
+N_170_i.BLIF N_77.BLIF N_136_i.BLIF N_79.BLIF N_137_i.BLIF N_90.BLIF \
+N_202_0.BLIF N_200.BLIF N_200_0.BLIF N_202.BLIF N_169_i.BLIF N_204.BLIF \
+N_198_0.BLIF N_114.BLIF N_168_i.BLIF N_115.BLIF \
+un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_116.BLIF N_90_i.BLIF N_117.BLIF \
+AS_030_c_i.BLIF N_118.BLIF N_75_i.BLIF N_120.BLIF N_71_i.BLIF N_121.BLIF \
+N_69_i.BLIF N_122.BLIF N_67_i.BLIF N_124.BLIF N_150_i.BLIF N_125.BLIF \
+N_151_i.BLIF N_128.BLIF N_129.BLIF N_145_i.BLIF N_132.BLIF N_146_i.BLIF \
+N_136.BLIF N_147_i.BLIF N_137.BLIF cpu_est_ns_0_2__n.BLIF N_138.BLIF \
+N_144_i.BLIF N_140.BLIF N_55_0.BLIF N_142.BLIF N_138_i.BLIF N_144.BLIF \
+N_172_i.BLIF N_145.BLIF N_149_i.BLIF N_146.BLIF N_129_i.BLIF N_147.BLIF \
+N_148.BLIF N_128_i.BLIF N_150.BLIF sm_amiga_ns_0_0__n.BLIF N_151.BLIF \
+N_70_i.BLIF N_155.BLIF N_124_i.BLIF N_166.BLIF \
+state_machine_lds_000_int_7_0_n.BLIF N_167.BLIF \
+state_machine_uds_000_int_7_0_n.BLIF N_168.BLIF N_122_i.BLIF N_169.BLIF \
+N_30_0.BLIF N_170.BLIF N_121_i.BLIF N_172.BLIF N_28_0.BLIF N_220.BLIF \
+N_117_i.BLIF N_230.BLIF N_118_i.BLIF N_133.BLIF N_196_0.BLIF N_143.BLIF \
+N_116_i.BLIF N_143_2.BLIF N_195_i.BLIF N_203.BLIF BG_030_c_i.BLIF N_201.BLIF \
+N_115_i.BLIF N_199.BLIF state_machine_un10_bg_030_0_n.BLIF N_161.BLIF \
+N_193_0.BLIF N_141.BLIF N_204_i.BLIF N_139.BLIF \
+state_machine_un10_clk_000_d0_i_n.BLIF N_135.BLIF \
+state_machine_un12_clk_000_d0_0_n.BLIF N_134.BLIF N_69_i_1.BLIF N_131.BLIF \
+N_76_i_1.BLIF N_130.BLIF N_76_i_2.BLIF N_171.BLIF N_76_i_3.BLIF \
+state_machine_ds_000_dma_3_n.BLIF N_76_i_4.BLIF N_197.BLIF N_76_i_5.BLIF \
+N_119.BLIF N_220_1.BLIF N_194.BLIF N_220_2.BLIF \
+state_machine_un6_bgack_000_n.BLIF N_230_1.BLIF N_143_2_i.BLIF N_230_2.BLIF \
+a_i_18__n.BLIF N_230_3.BLIF a_i_16__n.BLIF N_230_4.BLIF a_i_19__n.BLIF \
+N_230_5.BLIF sm_amiga_i_4__n.BLIF N_230_6.BLIF sm_amiga_i_5__n.BLIF \
+cpu_est_ns_0_1_1__n.BLIF sm_amiga_i_3__n.BLIF cpu_est_ns_0_2_1__n.BLIF \
+CLK_000_D0_i.BLIF N_122_1.BLIF sm_amiga_i_0__n.BLIF N_122_2.BLIF \
+sm_amiga_i_1__n.BLIF N_122_3.BLIF RW_i.BLIF N_115_1.BLIF CLK_030_H_i.BLIF \
+N_115_2.BLIF CLK_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF \
+DTACK_D0_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \
+N_133_1.BLIF AS_000_i.BLIF N_133_2.BLIF UDS_000_i.BLIF N_143_1.BLIF \
+LDS_000_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_000_i.BLIF N_55_0_1.BLIF \
+sm_amiga_i_6__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF \
+cpu_est_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF \
+sm_amiga_i_7__n.BLIF N_196_0_1.BLIF CLK_000_D2_i.BLIF N_155_1.BLIF \
+cpu_est_i_1__n.BLIF N_148_1.BLIF cpu_est_i_0__n.BLIF N_142_1.BLIF \
+VMA_INT_i.BLIF N_140_1.BLIF VPA_D_i.BLIF N_132_1.BLIF AS_000_DMA_i.BLIF \
+N_124_1.BLIF nEXP_SPACE_i.BLIF state_machine_a0_dma_2_1_n.BLIF \
+cpu_est_i_2__n.BLIF N_120_1.BLIF A0_i.BLIF N_118_1.BLIF size_i_1__n.BLIF \
+N_117_1.BLIF DS_030_i.BLIF N_116_1.BLIF AS_030_000_SYNC_i.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF a_i_30__n.BLIF N_204_1.BLIF \
+a_i_31__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_28__n.BLIF \
+bgack_030_int_0_un1_n.BLIF a_i_29__n.BLIF bgack_030_int_0_un0_n.BLIF \
+a_i_26__n.BLIF as_000_dma_0_un3_n.BLIF a_i_27__n.BLIF as_000_dma_0_un1_n.BLIF \
+a_i_24__n.BLIF as_000_dma_0_un0_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un3_n.BLIF \
+RST_i.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \
+clk_030_h_0_un3_n.BLIF N_114_i.BLIF clk_030_h_0_un1_n.BLIF FPU_CS_INT_i.BLIF \
+clk_030_h_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_int_0_un3_n.BLIF \
+AS_030_c.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF AS_000_c.BLIF \
+state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
+state_machine_uds_000_int_7_0_m3_un1_n.BLIF RW_000_c.BLIF \
+state_machine_uds_000_int_7_0_m3_un0_n.BLIF ipl_030_0_0__un3_n.BLIF \
+DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF \
ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF LDS_000_c.BLIF \
ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF \
ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF \
@@ -177,24 +178,22 @@ cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_16__n.BLIF \
cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF \
cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF \
cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_19__n.BLIF \
-cpu_estse_2_un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF a_c_20__n.BLIF \
-amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF a_c_21__n.BLIF \
-as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF a_c_22__n.BLIF \
-as_030_000_sync_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_23__n.BLIF \
-clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_24__n.BLIF \
-uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_25__n.BLIF \
-uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_26__n.BLIF \
-lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_27__n.BLIF \
-fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_28__n.BLIF \
-fpu_cs_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF a_c_29__n.BLIF bg_000_0_un1_n.BLIF \
-bg_000_0_un0_n.BLIF a_c_30__n.BLIF ds_000_dma_0_un3_n.BLIF \
-ds_000_dma_0_un1_n.BLIF a_c_31__n.BLIF ds_000_dma_0_un0_n.BLIF \
-as_000_dma_0_un3_n.BLIF A0_c.BLIF as_000_dma_0_un1_n.BLIF \
-as_000_dma_0_un0_n.BLIF nEXP_SPACE_c.BLIF as_000_int_0_un3_n.BLIF \
-as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF BG_030_c.BLIF \
-BG_000DFFSHreg.BLIF BGACK_000_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
-DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
-SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
+cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF a_c_20__n.BLIF \
+as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF a_c_21__n.BLIF \
+uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_22__n.BLIF \
+uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_23__n.BLIF \
+lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_24__n.BLIF \
+fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_25__n.BLIF \
+fpu_cs_int_0_un0_n.BLIF avec_exp_0_un3_n.BLIF a_c_26__n.BLIF \
+avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF a_c_27__n.BLIF bg_000_0_un3_n.BLIF \
+bg_000_0_un1_n.BLIF a_c_28__n.BLIF bg_000_0_un0_n.BLIF as_000_int_0_un3_n.BLIF \
+a_c_29__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF a_c_30__n.BLIF \
+dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF a_c_31__n.BLIF \
+dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF A0_c.BLIF vma_int_0_un1_n.BLIF \
+vma_int_0_un0_n.BLIF nEXP_SPACE_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
+RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
+SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \
+RW.PIN.BLIF
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \
@@ -212,93 +211,91 @@ inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D \
inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D \
inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \
-SIZE_DMA_0_.AP inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \
-inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \
-inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
-BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \
-inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \
-inst_AS_000_INT.C inst_AS_000_INT.AP AMIGA_BUS_ENABLEDFFSHreg.D \
-AMIGA_BUS_ENABLEDFFSHreg.C AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_030_000_SYNC.D \
+SIZE_DMA_0_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \
+inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \
+inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \
+BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \
+inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
+inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D \
+inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D \
inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D \
-inst_CLK_030_H.C inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_000_D4.D \
-inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_DTACK_D0.D inst_DTACK_D0.C \
-inst_DTACK_D0.AP inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP \
-inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D \
-CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \
+inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \
+inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C \
+inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \
+CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D \
+inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C \
inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C \
inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \
inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \
-RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ DSACK_1_ AS_030 \
-AS_000 DS_030 UDS_000 LDS_000 A0 DTACK SIZE_0_ DSACK_0_ CLK_030_c CLK_000_c \
-CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n \
-state_machine_un13_clk_000_d0_n clk_un3_clk_out_pre_50_n RST_c \
-state_machine_un6_bgack_000_n state_machine_un15_clk_000_d0_n RW_c fc_c_0__n \
-fc_c_1__n un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 AMIGA_BUS_DATA_DIR_c \
-state_machine_ds_000_dma_3_n cpu_est_ns_0_1__n state_machine_un10_bg_030_n \
-N_134_i state_machine_lds_000_int_7_n N_169_i state_machine_uds_000_int_7_n \
-N_133_i N_167_i N_51_0 N_140_i N_202_0 N_86_0 N_171_i \
-un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 N_82_i sm_amiga_i_1__n N_78_i N_170_i N_77_0 \
-CLK_000_D1_i N_76_i N_74_i N_72_0 AS_030_000_SYNC_i CLK_000_D2_i \
-state_machine_un8_bgack_030_int_i_0_0_n N_69_i AS_030_c_i N_65_i N_64_i N_62_i \
-N_152_i N_153_i cpu_est_ns_1__n N_61_0 cpu_est_ns_2__n N_150_i \
-state_machine_un8_bgack_030_int_i_0_n N_148_i N_197 N_149_i N_198 N_199 \
-N_123_i N_200 N_145_i N_201 N_146_i sm_amiga_ns_0_0__n N_51 N_142_i N_53 \
-N_143_i N_61 N_144_i N_62 cpu_est_ns_0_2__n N_64 N_141_i N_65 N_53_0 N_66 \
-N_139_i N_69 state_machine_amiga_bus_enable_4_iv_i_n N_72 N_138_i N_74 N_48_i \
-N_76 N_136_i N_77 N_137_i N_78 AMIGA_BUS_DATA_DIR_c_0 N_82 N_135_i N_86 \
-N_168_i N_202 N_151_i N_203 N_132_i N_205 N_164_i N_206 N_115 N_130_i N_116 \
-N_131_i N_117 N_41_0 N_118 N_128_i N_120 N_129_i N_121 sm_amiga_ns_0_5__n \
-N_122 N_126_i N_123 N_127_i N_124 N_125 N_125_i N_126 N_127 N_124_i N_128 \
-N_129 N_122_i N_130 N_131 N_172_i N_132 state_machine_size_dma_4_0_1__n N_133 \
-state_machine_ds_000_dma_3_0_n N_134 N_66_i N_135 N_120_i N_136 \
-state_machine_lds_000_int_7_0_n N_137 state_machine_uds_000_int_7_0_n N_138 \
-N_118_i N_139 N_201_0 N_140 N_117_i N_141 N_200_0 N_142 N_115_i N_143 N_116_i \
-N_144 N_199_0 N_145 BG_030_c_i N_146 N_206_i N_147 \
-state_machine_un10_bg_030_0_n N_148 N_198_0 N_149 N_197_0 N_150 N_203_i N_152 \
-state_machine_un13_clk_000_d0_i_n N_153 state_machine_un15_clk_000_d0_0_n \
-N_164 state_machine_un6_bgack_000_0_n N_167 N_225_1 N_168 N_225_2 N_169 \
-N_225_3 N_170 N_225_4 N_171 N_225_5 N_172 N_225_6 N_173 N_228_1 N_225 N_228_2 \
-N_228 N_69_i_1 CLK_000_D0_i N_69_i_2 BGACK_030_INT_i N_69_i_3 CLK_030_i \
-N_69_i_4 cpu_est_i_3__n N_69_i_5 sm_amiga_i_6__n \
-state_machine_un8_bgack_030_int_i_0_0_1_n nEXP_SPACE_i N_72_0_1 CLK_000_D4_i \
-N_51_0_1 sm_amiga_i_5__n N_51_0_2 sm_amiga_i_4__n cpu_est_ns_0_1_1__n AS_000_i \
-cpu_est_ns_0_2_1__n LDS_000_i N_128_1 UDS_000_i N_128_2 cpu_est_i_1__n N_118_1 \
-cpu_est_i_0__n N_118_2 DTACK_D0_i N_118_3 VMA_INT_i N_206_1 VPA_D_i N_206_2 \
-AS_000_DMA_i sm_amiga_ns_0_1_0__n CLK_030_H_i cpu_est_ns_0_1_2__n RW_i \
-N_53_0_1 cpu_est_i_2__n N_43_i_1 sm_amiga_i_0__n \
-state_machine_lds_000_int_7_0_1_n sm_amiga_i_3__n \
-state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_199_0_1 A0_i N_152_1 \
-size_i_1__n N_147_1 DS_030_i N_139_1 a_i_19__n N_137_1 a_i_16__n N_127_1 \
-a_i_18__n N_120_1 a_i_30__n state_machine_a0_dma_2_1_n a_i_31__n N_116_1 \
-a_i_28__n N_115_1 a_i_29__n state_machine_un13_clk_000_d0_1_n a_i_26__n \
-N_203_1 a_i_27__n state_machine_uds_000_int_7_0_m3_un3_n a_i_24__n \
-state_machine_uds_000_int_7_0_m3_un1_n a_i_25__n \
-state_machine_uds_000_int_7_0_m3_un0_n RST_i dsack1_int_0_un3_n \
-dsack1_int_0_un1_n dsack1_int_0_un0_n N_205_i vma_int_0_un3_n FPU_CS_INT_i \
-vma_int_0_un1_n CLK_OUT_PRE_50_D_i vma_int_0_un0_n AS_030_c \
-bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_000_c bgack_030_int_0_un0_n \
-ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c \
-ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n \
-ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \
-size_c_1__n cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n \
-cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n \
-cpu_estse_2_un3_n cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n \
-amiga_bus_enable_0_un3_n a_c_20__n amiga_bus_enable_0_un1_n \
-amiga_bus_enable_0_un0_n a_c_21__n as_030_000_sync_0_un3_n \
-as_030_000_sync_0_un1_n a_c_22__n as_030_000_sync_0_un0_n clk_030_h_0_un3_n \
-a_c_23__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_24__n uds_000_int_0_un3_n \
-uds_000_int_0_un1_n a_c_25__n uds_000_int_0_un0_n lds_000_int_0_un3_n \
-a_c_26__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_27__n fpu_cs_int_0_un3_n \
-fpu_cs_int_0_un1_n a_c_28__n fpu_cs_int_0_un0_n bg_000_0_un3_n a_c_29__n \
-bg_000_0_un1_n bg_000_0_un0_n a_c_30__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n \
-a_c_31__n ds_000_dma_0_un0_n as_000_dma_0_un3_n A0_c as_000_dma_0_un1_n \
-as_000_dma_0_un0_n nEXP_SPACE_c as_000_int_0_un3_n as_000_int_0_un1_n \
-as_000_int_0_un0_n BG_030_c BGACK_000_c AS_030.OE AS_000.OE DS_030.OE \
-UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE \
-DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
-.names N_148_i.BLIF N_149_i.BLIF cpu_est_0_.D
+RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \
+DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ BG_030_c BGACK_000_c \
+CLK_030_c CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n state_machine_un10_clk_000_d0_n \
+ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c state_machine_un3_clk_out_pre_50_n \
+state_machine_un12_clk_000_d0_n RST_c AMIGA_BUS_ENABLE_INT_2_sqmuxa RW_c \
+un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n \
+state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n \
+AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i \
+N_197_0 state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n \
+N_130_i N_131_i N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \
+N_140_i AMIGA_BUS_DATA_DIR_c_0 N_141_i N_52_i N_143_i N_142_i \
+state_machine_rw_000_int_7_iv_i_n cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n \
+N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i N_30 N_76_i N_55 CLK_000_D1_i \
+N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n N_69 N_201_0 N_70 \
+N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i N_79 \
+N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i \
+N_115 un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i \
+N_120 N_71_i N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 \
+N_145_i N_132 N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i \
+N_140 N_55_0 N_142 N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 \
+N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 \
+state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n N_168 \
+N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i N_230 N_118_i \
+N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i N_201 N_115_i \
+N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \
+state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n \
+N_134 N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 \
+state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 \
+N_220_2 state_machine_un6_bgack_000_n N_230_1 N_143_2_i N_230_2 a_i_18__n \
+N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 \
+sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n \
+CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n N_122_3 RW_i \
+N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \
+DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \
+N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \
+sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \
+state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i \
+N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 \
+VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n \
+cpu_est_i_2__n N_120_1 A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 \
+AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n \
+bgack_030_int_0_un3_n a_i_28__n bgack_030_int_0_un1_n a_i_29__n \
+bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n \
+as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n a_i_25__n ds_000_dma_0_un3_n \
+RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i \
+clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i \
+rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c \
+state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n \
+RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \
+ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \
+ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \
+ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \
+cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \
+cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n \
+cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n \
+a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n \
+uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n \
+lds_000_int_0_un3_n a_c_23__n lds_000_int_0_un1_n lds_000_int_0_un0_n \
+a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n \
+avec_exp_0_un3_n a_c_26__n avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n \
+bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n \
+a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n a_c_30__n dsack1_int_0_un3_n \
+dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c \
+vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c AS_030.OE AS_000.OE RW_000.OE \
+DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE \
+RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0
+.names N_150_i.BLIF N_151_i.BLIF cpu_est_0_.D
11 1
.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
1- 1
@@ -309,7 +306,7 @@ DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
1- 1
-1 1
-.names N_43_i_1.BLIF N_164_i.BLIF SM_AMIGA_0_.D
+.names CLK_000_D0_i.BLIF N_135_i.BLIF SM_AMIGA_0_.D
11 1
.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
0 1
@@ -324,18 +321,18 @@ DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
-1 1
.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
0 1
-.names N_122_i.BLIF N_123_i.BLIF SM_AMIGA_6_.D
+.names N_129_i.BLIF N_198_0.BLIF SM_AMIGA_6_.D
11 1
-.names inst_CLK_000_D0.BLIF N_124_i.BLIF SM_AMIGA_5_.D
+.names inst_CLK_000_D0.BLIF N_200.BLIF SM_AMIGA_5_.D
11 1
-.names CLK_000_D0_i.BLIF N_125_i.BLIF SM_AMIGA_4_.D
+.names CLK_000_D0_i.BLIF N_130_i.BLIF SM_AMIGA_4_.D
11 1
-.names N_126_i.BLIF N_127_i.BLIF SM_AMIGA_3_.D
+.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_3_.D
11 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
-.names N_41_0.BLIF SM_AMIGA_1_.D
-0 1
+.names inst_CLK_000_D0.BLIF N_201.BLIF SM_AMIGA_1_.D
+11 1
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
1- 1
-1 1
@@ -346,17 +343,17 @@ DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
inst_BGACK_030_INTreg.D
1- 1
-1 1
-.names N_121.BLIF SIZE_DMA_0_.D
+.names N_125.BLIF SIZE_DMA_0_.D
0 1
-.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
-1- 1
--1 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D
1- 1
-1 1
+.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D
+1- 1
+-1 1
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
@@ -369,8 +366,7 @@ inst_BGACK_030_INTreg.D
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
-.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \
-AMIGA_BUS_ENABLEDFFSHreg.D
+.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
1- 1
-1 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \
@@ -380,674 +376,682 @@ inst_AS_030_000_SYNC.D
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
-.names state_machine_a0_dma_2_1_n.BLIF N_173.BLIF inst_A0_DMA.D
+.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
+1- 1
+-1 1
+.names state_machine_a0_dma_2_1_n.BLIF N_166.BLIF inst_A0_DMA.D
11 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
.names vcc_n_n
1
.names gnd_n_n
-.names state_machine_un13_clk_000_d0_1_n.BLIF N_168.BLIF \
-state_machine_un13_clk_000_d0_n
+.names state_machine_un10_clk_000_d0_1_n.BLIF \
+state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n
11 1
.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \
-clk_un3_clk_out_pre_50_n
+state_machine_un3_clk_out_pre_50_n
11 1
-.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
-.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n
-0 1
-.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2
-0 1
-.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
-0 1
-.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
-0 1
-.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
+.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa
11 1
+.names un1_DSACK1_INT_0_sqmuxa_3_0.BLIF un1_DSACK1_INT_0_sqmuxa_3
+0 1
.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
-.names N_134.BLIF N_134_i
-0 1
.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n
0 1
-.names N_169.BLIF N_169_i
-0 1
.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n
0 1
-.names N_133.BLIF N_133_i
+.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
0 1
-.names N_167.BLIF N_167_i
-0 1
-.names N_51_0_1.BLIF N_51_0_2.BLIF N_51_0
+.names BGACK_000_c.BLIF N_77.BLIF state_machine_un6_bgack_000_0_n
11 1
-.names N_140.BLIF N_140_i
-0 1
-.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_202_0
+.names CLK_030_c.BLIF N_143_2.BLIF N_194_0
11 1
-.names CLK_000_D0_i.BLIF N_74_i.BLIF N_86_0
+.names N_119.BLIF N_119_i
+0 1
+.names N_120.BLIF N_120_i
+0 1
+.names N_119_i.BLIF N_120_i.BLIF N_197_0
+11 1
+.names AS_000_DMA_i.BLIF N_143_2.BLIF state_machine_ds_000_dma_3_0_n
11 1
.names N_171.BLIF N_171_i
0 1
-.names N_65_i.BLIF N_171_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0
-11 1
-.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_82_i
-11 1
-.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
-0 1
-.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_78_i
-11 1
-.names N_170.BLIF N_170_i
-0 1
-.names CLK_000_D0_i.BLIF N_170_i.BLIF N_77_0
-11 1
-.names inst_CLK_000_D1.BLIF CLK_000_D1_i
-0 1
-.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_76_i
-11 1
-.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_74_i
-11 1
-.names N_72_0_1.BLIF CLK_000_D2_i.BLIF N_72_0
-11 1
-.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
-0 1
-.names inst_CLK_000_D2.BLIF CLK_000_D2_i
-0 1
-.names state_machine_un8_bgack_030_int_i_0_0_1_n.BLIF BGACK_030_INT_i.BLIF \
-state_machine_un8_bgack_030_int_i_0_0_n
-11 1
-.names N_69_i_4.BLIF N_69_i_5.BLIF N_69_i
-11 1
-.names AS_030_c.BLIF AS_030_c_i
-0 1
-.names AS_030_c_i.BLIF N_205_i.BLIF N_65_i
-11 1
-.names inst_CLK_000_D4.BLIF SM_AMIGA_5_.BLIF N_64_i
-11 1
-.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_62_i
-11 1
-.names N_152.BLIF N_152_i
-0 1
-.names N_153.BLIF N_153_i
-0 1
-.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
-0 1
-.names N_152_i.BLIF N_153_i.BLIF N_61_0
-11 1
-.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
-0 1
-.names N_150.BLIF N_150_i
-0 1
-.names state_machine_un8_bgack_030_int_i_0_0_n.BLIF \
-state_machine_un8_bgack_030_int_i_0_n
-0 1
-.names N_148.BLIF N_148_i
-0 1
-.names N_197_0.BLIF N_197
-0 1
-.names N_149.BLIF N_149_i
-0 1
-.names N_198_0.BLIF N_198
-0 1
-.names N_199_0.BLIF N_199
-0 1
-.names N_123.BLIF N_123_i
-0 1
-.names N_200_0.BLIF N_200
-0 1
-.names N_145.BLIF N_145_i
-0 1
-.names N_201_0.BLIF N_201
-0 1
-.names N_146.BLIF N_146_i
-0 1
-.names sm_amiga_ns_0_1_0__n.BLIF N_145_i.BLIF sm_amiga_ns_0_0__n
-11 1
-.names N_51_0.BLIF N_51
-0 1
-.names N_142.BLIF N_142_i
-0 1
-.names N_53_0.BLIF N_53
-0 1
-.names N_143.BLIF N_143_i
-0 1
-.names N_61_0.BLIF N_61
-0 1
-.names N_144.BLIF N_144_i
-0 1
-.names N_62_i.BLIF N_62
-0 1
-.names cpu_est_ns_0_1_2__n.BLIF N_143_i.BLIF cpu_est_ns_0_2__n
-11 1
-.names N_64_i.BLIF N_64
-0 1
-.names N_141.BLIF N_141_i
-0 1
-.names N_65_i.BLIF N_65
-0 1
-.names N_53_0_1.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_53_0
-11 1
-.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF \
-state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_66
-1- 1
--1 1
-.names N_139.BLIF N_139_i
-0 1
-.names N_69_i.BLIF N_69
-0 1
-.names inst_BGACK_030_INTreg.BLIF N_139_i.BLIF \
-state_machine_amiga_bus_enable_4_iv_i_n
-11 1
-.names N_72_0.BLIF N_72
-0 1
-.names N_138.BLIF N_138_i
-0 1
-.names N_74_i.BLIF N_74
-0 1
-.names N_138_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_48_i
-11 1
-.names N_76_i.BLIF N_76
-0 1
-.names N_136.BLIF N_136_i
-0 1
-.names N_77_0.BLIF N_77
-0 1
-.names N_137.BLIF N_137_i
-0 1
-.names N_78_i.BLIF N_78
-0 1
-.names N_136_i.BLIF N_137_i.BLIF AMIGA_BUS_DATA_DIR_c_0
-11 1
-.names N_82_i.BLIF N_82
-0 1
-.names N_135.BLIF N_135_i
-0 1
-.names N_86_0.BLIF N_86
-0 1
-.names N_168.BLIF N_168_i
-0 1
-.names N_202_0.BLIF N_202
-0 1
-.names N_135_i.BLIF N_168_i.BLIF N_151_i
-11 1
-.names N_203_1.BLIF VPA_D_i.BLIF N_203
-11 1
-.names N_132.BLIF N_132_i
-0 1
-.names N_170.BLIF SM_AMIGA_1_.BLIF N_205
-11 1
-.names N_164.BLIF N_164_i
-0 1
-.names N_206_1.BLIF N_206_2.BLIF N_206
-11 1
-.names N_115_1.BLIF RW_c.BLIF N_115
+.names N_143_2.BLIF N_171_i.BLIF state_machine_size_dma_4_0_1__n
11 1
.names N_130.BLIF N_130_i
0 1
-.names N_116_1.BLIF RW_i.BLIF N_116
-11 1
.names N_131.BLIF N_131_i
0 1
-.names CLK_030_c.BLIF N_69_i.BLIF N_117
-11 1
-.names N_130_i.BLIF N_131_i.BLIF N_41_0
-11 1
-.names N_118_3.BLIF nEXP_SPACE_c.BLIF N_118
-11 1
-.names N_128.BLIF N_128_i
+.names N_132.BLIF N_132_i
0 1
-.names N_120_1.BLIF size_i_1__n.BLIF N_120
-11 1
-.names N_129.BLIF N_129_i
+.names N_133.BLIF N_133_i
0 1
-.names N_172.BLIF N_173.BLIF N_121
-11 1
-.names N_128_i.BLIF N_129_i.BLIF sm_amiga_ns_0_5__n
-11 1
-.names N_86.BLIF sm_amiga_i_7__n.BLIF N_122
-11 1
-.names N_126.BLIF N_126_i
+.names N_134.BLIF N_134_i
0 1
-.names N_72.BLIF SM_AMIGA_7_.BLIF N_123
+.names N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n
11 1
-.names N_127.BLIF N_127_i
+.names N_135.BLIF N_135_i
0 1
-.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_124
-11 1
-.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_125
-11 1
-.names N_125.BLIF N_125_i
+.names N_139.BLIF N_139_i
0 1
-.names N_62.BLIF sm_amiga_i_3__n.BLIF N_126
-11 1
-.names N_127_1.BLIF inst_CLK_000_D1.BLIF N_127
-11 1
-.names N_124.BLIF N_124_i
+.names N_140.BLIF N_140_i
0 1
-.names N_128_1.BLIF N_128_2.BLIF N_128
+.names N_139_i.BLIF N_140_i.BLIF AMIGA_BUS_DATA_DIR_c_0
11 1
-.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_129
-11 1
-.names N_122.BLIF N_122_i
+.names N_141.BLIF N_141_i
0 1
-.names N_77.BLIF SM_AMIGA_1_.BLIF N_130
+.names N_141_i.BLIF N_143_2.BLIF N_52_i
11 1
-.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_131
+.names N_143.BLIF N_143_i
+0 1
+.names N_142.BLIF N_142_i
+0 1
+.names N_142_i.BLIF N_143_i.BLIF state_machine_rw_000_int_7_iv_i_n
+11 1
+.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
+0 1
+.names LDS_000_c.BLIF UDS_000_c.BLIF N_62_0
+11 1
+.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
+0 1
+.names N_161.BLIF N_161_i
+0 1
+.names N_193_0.BLIF N_193
+0 1
+.names N_155.BLIF N_155_i
+0 1
+.names N_196_0.BLIF N_196
+0 1
+.names N_155_i.BLIF N_161_i.BLIF N_63_0
+11 1
+.names N_28_0.BLIF N_28
+0 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_66_i
+11 1
+.names N_30_0.BLIF N_30
+0 1
+.names N_76_i_4.BLIF N_76_i_5.BLIF N_76_i
+11 1
+.names N_55_0.BLIF N_55
+0 1
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
+0 1
+.names N_62_0.BLIF N_62
+0 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_77_i
+11 1
+.names N_63_0.BLIF N_63
+0 1
+.names CLK_030_i.BLIF N_143_2.BLIF N_79_0
+11 1
+.names N_66_i.BLIF N_66
+0 1
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_199_0
+11 1
+.names N_67_i.BLIF N_67
+0 1
+.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+0 1
+.names N_69_i.BLIF N_69
+0 1
+.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_201_0
+11 1
+.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF \
+state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_70
+1- 1
+-1 1
+.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_203_0
+11 1
+.names N_71_i.BLIF N_71
+0 1
+.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
+11 1
+.names N_75_i.BLIF N_75
+0 1
+.names N_167.BLIF N_167_i
+0 1
+.names N_76_i.BLIF N_76
+0 1
+.names N_170.BLIF N_170_i
+0 1
+.names N_77_i.BLIF N_77
+0 1
+.names N_136.BLIF N_136_i
+0 1
+.names N_79_0.BLIF N_79
+0 1
+.names N_137.BLIF N_137_i
+0 1
+.names N_90_i.BLIF N_90
+0 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_202_0
+11 1
+.names N_200_0.BLIF N_200
+0 1
+.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_200_0
+11 1
+.names N_202_0.BLIF N_202
+0 1
+.names N_169.BLIF N_169_i
+0 1
+.names N_204_1.BLIF VPA_D_i.BLIF N_204
+11 1
+.names N_71.BLIF N_169_i.BLIF N_198_0
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114
+11 1
+.names N_168.BLIF N_168_i
+0 1
+.names N_115_1.BLIF N_115_2.BLIF N_115
+11 1
+.names N_75_i.BLIF N_168_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0
+11 1
+.names N_116_1.BLIF N_69_i.BLIF N_116
+11 1
+.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_90_i
+11 1
+.names N_117_1.BLIF RW_c.BLIF N_117
+11 1
+.names AS_030_c.BLIF AS_030_c_i
+0 1
+.names N_118_1.BLIF RW_i.BLIF N_118
+11 1
+.names AS_030_c_i.BLIF N_114_i.BLIF N_75_i
+11 1
+.names N_120_1.BLIF N_166.BLIF N_120
+11 1
+.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_71_i
+11 1
+.names CLK_030_c.BLIF N_76_i.BLIF N_121
+11 1
+.names N_69_i_1.BLIF inst_CLK_000_D3.BLIF N_69_i
+11 1
+.names N_122_3.BLIF nEXP_SPACE_c.BLIF N_122
+11 1
+.names inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF N_67_i
+11 1
+.names N_124_1.BLIF size_i_1__n.BLIF N_124
+11 1
+.names N_150.BLIF N_150_i
+0 1
+.names N_166.BLIF N_171.BLIF N_125
+11 1
+.names N_151.BLIF N_151_i
+0 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_128
+11 1
+.names N_202.BLIF sm_amiga_i_7__n.BLIF N_129
+11 1
+.names N_145.BLIF N_145_i
+0 1
+.names N_132_1.BLIF inst_CLK_000_D1.BLIF N_132
+11 1
+.names N_146.BLIF N_146_i
+0 1
+.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_136
+11 1
+.names N_147.BLIF N_147_i
+0 1
+.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_137
+11 1
+.names cpu_est_ns_0_1_2__n.BLIF N_146_i.BLIF cpu_est_ns_0_2__n
+11 1
+.names N_90.BLIF cpu_est_2_.BLIF N_138
+11 1
+.names N_144.BLIF N_144_i
+0 1
+.names N_140_1.BLIF nEXP_SPACE_i.BLIF N_140
+11 1
+.names N_55_0_1.BLIF RW_000_i.BLIF N_55_0
+11 1
+.names N_142_1.BLIF SM_AMIGA_6_.BLIF N_142
+11 1
+.names N_138.BLIF N_138_i
+0 1
+.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_144
11 1
.names N_172.BLIF N_172_i
0 1
-.names N_77.BLIF sm_amiga_i_0__n.BLIF N_132
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_145
11 1
-.names N_172_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF \
-state_machine_size_dma_4_0_1__n
+.names N_138_i.BLIF N_172_i.BLIF N_149_i
11 1
-.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_133
+.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_146
11 1
-.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF \
-state_machine_ds_000_dma_3_0_n
-11 1
-.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_134
-11 1
-.names N_66.BLIF N_66_i
+.names N_129.BLIF N_129_i
0 1
-.names N_82.BLIF cpu_est_2_.BLIF N_135
+.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_147
11 1
-.names N_120.BLIF N_120_i
+.names N_148_1.BLIF nEXP_SPACE_i.BLIF N_148
+11 1
+.names N_128.BLIF N_128_i
0 1
-.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_136
+.names N_77.BLIF cpu_est_i_0__n.BLIF N_150
11 1
-.names state_machine_lds_000_int_7_0_1_n.BLIF N_66_i.BLIF \
+.names N_128_i.BLIF N_198_0.BLIF sm_amiga_ns_0_0__n
+11 1
+.names N_77_i.BLIF cpu_est_0_.BLIF N_151
+11 1
+.names N_70.BLIF N_70_i
+0 1
+.names N_155_1.BLIF VPA_D_i.BLIF N_155
+11 1
+.names N_124.BLIF N_124_i
+0 1
+.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_166
+11 1
+.names state_machine_lds_000_int_7_0_1_n.BLIF N_70_i.BLIF \
state_machine_lds_000_int_7_0_n
11 1
-.names N_137_1.BLIF nEXP_SPACE_i.BLIF N_137
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167
11 1
.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF \
state_machine_uds_000_int_7_0_n
11 1
-.names CLK_030_H_i.BLIF N_202.BLIF N_138
+.names N_69_i.BLIF N_71_i.BLIF N_168
11 1
-.names N_118.BLIF N_118_i
+.names N_122.BLIF N_122_i
0 1
-.names N_139_1.BLIF CLK_000_D4_i.BLIF N_139
+.names N_69.BLIF SM_AMIGA_7_.BLIF N_169
11 1
-.names N_118_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_201_0
+.names N_122_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_30_0
11 1
-.names AS_030_c.BLIF N_78.BLIF N_140
+.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_170
+11 1
+.names N_121.BLIF N_121_i
+0 1
+.names N_167.BLIF cpu_est_i_3__n.BLIF N_172
+11 1
+.names AS_030_c_i.BLIF N_121_i.BLIF N_28_0
+11 1
+.names N_220_1.BLIF N_220_2.BLIF N_220
11 1
.names N_117.BLIF N_117_i
0 1
-.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_141
+.names N_230_5.BLIF N_230_6.BLIF N_230
11 1
-.names AS_030_c_i.BLIF N_117_i.BLIF N_200_0
-11 1
-.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_142
-11 1
-.names N_115.BLIF N_115_i
+.names N_118.BLIF N_118_i
0 1
-.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_143
+.names N_133_1.BLIF N_133_2.BLIF N_133
+11 1
+.names N_196_0_1.BLIF N_117_i.BLIF N_196_0
+11 1
+.names N_143_1.BLIF RW_000_i.BLIF N_143
11 1
.names N_116.BLIF N_116_i
0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_144
+.names N_62.BLIF N_166.BLIF N_143_2
11 1
-.names N_199_0_1.BLIF N_115_i.BLIF N_199_0
-11 1
-.names CLK_000_D0_i.BLIF N_171.BLIF N_145
+.names inst_BGACK_030_INTreg.BLIF N_116_i.BLIF N_195_i
11 1
+.names N_203_0.BLIF N_203
+0 1
.names BG_030_c.BLIF BG_030_c_i
0 1
-.names N_164.BLIF SM_AMIGA_0_.BLIF N_146
-11 1
-.names N_206.BLIF N_206_i
+.names N_201_0.BLIF N_201
0 1
-.names N_147_1.BLIF nEXP_SPACE_i.BLIF N_147
-11 1
-.names BG_030_c_i.BLIF N_206_i.BLIF state_machine_un10_bg_030_0_n
-11 1
-.names N_76.BLIF cpu_est_i_0__n.BLIF N_148
-11 1
-.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_198_0
-11 1
-.names N_76_i.BLIF cpu_est_0_.BLIF N_149
-11 1
-.names AS_030_c_i.BLIF N_64.BLIF N_197_0
-11 1
-.names LDS_000_c.BLIF UDS_000_c.BLIF N_150
-11 1
-.names N_203.BLIF N_203_i
+.names N_115.BLIF N_115_i
0 1
-.names N_152_1.BLIF VPA_D_i.BLIF N_152
-11 1
-.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n
+.names N_199_0.BLIF N_199
0 1
-.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_153
+.names BG_030_c_i.BLIF N_115_i.BLIF state_machine_un10_bg_030_0_n
11 1
-.names N_203_i.BLIF state_machine_un13_clk_000_d0_i_n.BLIF \
-state_machine_un15_clk_000_d0_0_n
+.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_161
11 1
-.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF N_164
+.names AS_030_c_i.BLIF N_67.BLIF N_193_0
11 1
-.names BGACK_000_c.BLIF N_76.BLIF state_machine_un6_bgack_000_0_n
+.names CLK_030_H_i.BLIF N_203.BLIF N_141
11 1
-.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167
-11 1
-.names a_i_24__n.BLIF a_i_25__n.BLIF N_225_1
-11 1
-.names N_167.BLIF cpu_est_i_3__n.BLIF N_168
-11 1
-.names a_i_26__n.BLIF a_i_27__n.BLIF N_225_2
-11 1
-.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_169
-11 1
-.names a_i_28__n.BLIF a_i_29__n.BLIF N_225_3
-11 1
-.names inst_CLK_000_D3.BLIF CLK_000_D4_i.BLIF N_170
-11 1
-.names a_i_30__n.BLIF a_i_31__n.BLIF N_225_4
-11 1
-.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_171
-11 1
-.names N_225_1.BLIF N_225_2.BLIF N_225_5
-11 1
-.names LDS_000_i.BLIF UDS_000_i.BLIF N_172
-11 1
-.names N_225_3.BLIF N_225_4.BLIF N_225_6
-11 1
-.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_173
-11 1
-.names a_c_20__n.BLIF a_c_21__n.BLIF N_228_1
-11 1
-.names N_225_5.BLIF N_225_6.BLIF N_225
-11 1
-.names a_c_22__n.BLIF a_c_23__n.BLIF N_228_2
-11 1
-.names N_228_1.BLIF N_228_2.BLIF N_228
-11 1
-.names a_c_17__n.BLIF BGACK_000_c.BLIF N_69_i_1
-11 1
-.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+.names N_204.BLIF N_204_i
0 1
-.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_69_i_2
+.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_139
11 1
-.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
-.names a_i_19__n.BLIF a_i_16__n.BLIF N_69_i_3
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_135
11 1
-.names CLK_030_c.BLIF CLK_030_i
-0 1
-.names N_69_i_1.BLIF N_69_i_2.BLIF N_69_i_4
+.names N_204_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF \
+state_machine_un12_clk_000_d0_0_n
11 1
-.names cpu_est_3_reg.BLIF cpu_est_i_3__n
-0 1
-.names N_69_i_3.BLIF a_i_18__n.BLIF N_69_i_5
+.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_134
11 1
-.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
-0 1
-.names N_150_i.BLIF AS_000_i.BLIF state_machine_un8_bgack_030_int_i_0_0_1_n
+.names CLK_000_D2_i.BLIF AS_030_000_SYNC_i.BLIF N_69_i_1
11 1
-.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
-0 1
-.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF N_72_0_1
+.names N_66.BLIF sm_amiga_i_3__n.BLIF N_131
11 1
-.names inst_CLK_000_D4.BLIF CLK_000_D4_i
-0 1
-.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_51_0_1
+.names BGACK_000_c.BLIF a_i_19__n.BLIF N_76_i_1
11 1
-.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
-0 1
-.names N_74.BLIF N_140_i.BLIF N_51_0_2
+.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_130
11 1
-.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
-0 1
-.names N_133_i.BLIF N_134_i.BLIF cpu_est_ns_0_1_1__n
+.names a_i_16__n.BLIF a_i_18__n.BLIF N_76_i_2
11 1
-.names AS_000_c.BLIF AS_000_i
-0 1
-.names N_167_i.BLIF N_169_i.BLIF cpu_est_ns_0_2_1__n
+.names LDS_000_i.BLIF UDS_000_i.BLIF N_171
11 1
-.names LDS_000_c.BLIF LDS_000_i
-0 1
-.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_128_1
+.names a_c_17__n.BLIF fc_c_0__n.BLIF N_76_i_3
11 1
-.names UDS_000_c.BLIF UDS_000_i
+.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
0 1
-.names N_61.BLIF SM_AMIGA_3_.BLIF N_128_2
+.names N_76_i_1.BLIF N_76_i_2.BLIF N_76_i_4
11 1
-.names cpu_est_1_.BLIF cpu_est_i_1__n
+.names N_197_0.BLIF N_197
0 1
-.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_118_1
+.names N_76_i_3.BLIF fc_c_1__n.BLIF N_76_i_5
11 1
-.names cpu_est_0_.BLIF cpu_est_i_0__n
-0 1
-.names N_69.BLIF SM_AMIGA_7_.BLIF N_118_2
+.names inst_CLK_000_D0.BLIF N_199.BLIF N_119
11 1
-.names inst_DTACK_D0.BLIF DTACK_D0_i
-0 1
-.names N_118_1.BLIF N_118_2.BLIF N_118_3
+.names a_c_20__n.BLIF a_c_21__n.BLIF N_220_1
11 1
-.names inst_VMA_INTreg.BLIF VMA_INT_i
+.names N_194_0.BLIF N_194
0 1
-.names AS_030_c.BLIF CLK_000_c.BLIF N_206_1
+.names a_c_22__n.BLIF a_c_23__n.BLIF N_220_2
11 1
-.names inst_VPA_D.BLIF VPA_D_i
+.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
0 1
-.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_206_2
+.names a_i_24__n.BLIF a_i_25__n.BLIF N_230_1
11 1
-.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+.names N_143_2.BLIF N_143_2_i
0 1
-.names N_146_i.BLIF N_123_i.BLIF sm_amiga_ns_0_1_0__n
-11 1
-.names inst_CLK_030_H.BLIF CLK_030_H_i
-0 1
-.names N_144_i.BLIF N_142_i.BLIF cpu_est_ns_0_1_2__n
-11 1
-.names RW_c.BLIF RW_i
-0 1
-.names N_141_i.BLIF RW_i.BLIF N_53_0_1
-11 1
-.names cpu_est_2_.BLIF cpu_est_i_2__n
-0 1
-.names N_78.BLIF N_132_i.BLIF N_43_i_1
-11 1
-.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
-0 1
-.names N_120_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n
-11 1
-.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
-0 1
-.names N_66_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n
-11 1
-.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
-0 1
-.names N_116_i.BLIF AS_030_c_i.BLIF N_199_0_1
-11 1
-.names A0_c.BLIF A0_i
-0 1
-.names N_82_i.BLIF VMA_INT_i.BLIF N_152_1
-11 1
-.names size_c_1__n.BLIF size_i_1__n
-0 1
-.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_147_1
-11 1
-.names DS_030_c.BLIF DS_030_i
-0 1
-.names N_74_i.BLIF inst_BGACK_030_INT_D.BLIF N_139_1
-11 1
-.names a_c_19__n.BLIF a_i_19__n
-0 1
-.names N_173.BLIF RW_c.BLIF N_137_1
-11 1
-.names a_c_16__n.BLIF a_i_16__n
-0 1
-.names N_61.BLIF CLK_000_D0_i.BLIF N_127_1
+.names a_i_26__n.BLIF a_i_27__n.BLIF N_230_2
11 1
.names a_c_18__n.BLIF a_i_18__n
0 1
-.names A0_i.BLIF size_c_0__n.BLIF N_120_1
+.names a_i_28__n.BLIF a_i_29__n.BLIF N_230_3
11 1
-.names a_c_30__n.BLIF a_i_30__n
+.names a_c_16__n.BLIF a_i_16__n
+0 1
+.names a_i_30__n.BLIF a_i_31__n.BLIF N_230_4
+11 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names N_230_1.BLIF N_230_2.BLIF N_230_5
+11 1
+.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names N_230_3.BLIF N_230_4.BLIF N_230_6
+11 1
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names N_136_i.BLIF N_137_i.BLIF cpu_est_ns_0_1_1__n
+11 1
+.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
+0 1
+.names N_167_i.BLIF N_170_i.BLIF cpu_est_ns_0_2_1__n
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
+.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_122_1
+11 1
+.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
+0 1
+.names N_76.BLIF SM_AMIGA_7_.BLIF N_122_2
+11 1
+.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+0 1
+.names N_122_1.BLIF N_122_2.BLIF N_122_3
+11 1
+.names RW_c.BLIF RW_i
+0 1
+.names AS_030_c.BLIF CLK_000_c.BLIF N_115_1
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_H_i
+0 1
+.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_115_2
+11 1
+.names CLK_030_c.BLIF CLK_030_i
+0 1
+.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF \
+state_machine_un10_clk_000_d0_1_n
+11 1
+.names inst_DTACK_D0.BLIF DTACK_D0_i
+0 1
+.names N_172.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
+11 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_133_1
+11 1
+.names AS_000_c.BLIF AS_000_i
+0 1
+.names N_63.BLIF SM_AMIGA_3_.BLIF N_133_2
+11 1
+.names UDS_000_c.BLIF UDS_000_i
+0 1
+.names CLK_030_i.BLIF N_143_2.BLIF N_143_1
+11 1
+.names LDS_000_c.BLIF LDS_000_i
+0 1
+.names N_147_i.BLIF N_145_i.BLIF cpu_est_ns_0_1_2__n
+11 1
+.names RW_000_c.BLIF RW_000_i
+0 1
+.names N_143_2.BLIF N_144_i.BLIF N_55_0_1
+11 1
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names N_124_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n
+11 1
+.names cpu_est_3_reg.BLIF cpu_est_i_3__n
+0 1
+.names N_70_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n
+11 1
+.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+0 1
+.names N_118_i.BLIF AS_030_c_i.BLIF N_196_0_1
+11 1
+.names inst_CLK_000_D2.BLIF CLK_000_D2_i
+0 1
+.names N_90_i.BLIF VMA_INT_i.BLIF N_155_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_148_1
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
+.names N_79.BLIF RW_i.BLIF N_142_1
+11 1
+.names inst_VMA_INTreg.BLIF VMA_INT_i
+0 1
+.names N_166.BLIF RW_c.BLIF N_140_1
+11 1
+.names inst_VPA_D.BLIF VPA_D_i
+0 1
+.names N_63.BLIF CLK_000_D0_i.BLIF N_132_1
+11 1
+.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+0 1
+.names A0_i.BLIF size_c_0__n.BLIF N_124_1
+11 1
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n
11 1
+.names cpu_est_2_.BLIF cpu_est_i_2__n
+0 1
+.names CLK_030_i.BLIF N_62.BLIF N_120_1
+11 1
+.names A0_c.BLIF A0_i
+0 1
+.names DS_030_i.BLIF N_66_i.BLIF N_118_1
+11 1
+.names size_c_1__n.BLIF size_i_1__n
+0 1
+.names DS_030_i.BLIF N_67_i.BLIF N_117_1
+11 1
+.names DS_030_c.BLIF DS_030_i
+0 1
+.names N_71.BLIF inst_BGACK_030_INT_D.BLIF N_116_1
+11 1
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
+11 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names CLK_000_D0_i.BLIF N_170.BLIF N_204_1
+11 1
.names a_c_31__n.BLIF a_i_31__n
0 1
-.names DS_030_i.BLIF N_62_i.BLIF N_116_1
-11 1
-.names a_c_28__n.BLIF a_i_28__n
-0 1
-.names DS_030_i.BLIF N_64_i.BLIF N_115_1
-11 1
-.names a_c_29__n.BLIF a_i_29__n
-0 1
-.names cpu_est_2_.BLIF N_164.BLIF state_machine_un13_clk_000_d0_1_n
-11 1
-.names a_c_26__n.BLIF a_i_26__n
-0 1
-.names CLK_000_D0_i.BLIF N_169.BLIF N_203_1
-11 1
-.names a_c_27__n.BLIF a_i_27__n
-0 1
-.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n
-0 1
-.names a_c_24__n.BLIF a_i_24__n
-0 1
-.names N_64.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n
-11 1
-.names a_c_25__n.BLIF a_i_25__n
-0 1
-.names N_62.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
-state_machine_uds_000_int_7_0_m3_un0_n
-11 1
-.names RST_c.BLIF RST_i
-0 1
-.names N_65.BLIF dsack1_int_0_un3_n
-0 1
-.names N_205_i.BLIF N_65.BLIF dsack1_int_0_un1_n
-11 1
-.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
-11 1
-.names N_205.BLIF N_205_i
-0 1
-.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n
-0 1
-.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
-0 1
-.names state_machine_un13_clk_000_d0_n.BLIF \
-state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n
-11 1
-.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
-0 1
-.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
-11 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
11 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
-.names N_76.BLIF ipl_030_0_0__un3_n
+.names a_c_26__n.BLIF a_i_26__n
0 1
-.names IPL_030DFFSH_0_reg.BLIF N_76.BLIF ipl_030_0_0__un1_n
+.names N_194.BLIF as_000_dma_0_un3_n
+0 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names N_143_2_i.BLIF N_194.BLIF as_000_dma_0_un1_n
+11 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
+.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
+11 1
+.names a_c_25__n.BLIF a_i_25__n
+0 1
+.names N_55.BLIF ds_000_dma_0_un3_n
+0 1
+.names RST_c.BLIF RST_i
+0 1
+.names state_machine_ds_000_dma_3_n.BLIF N_55.BLIF ds_000_dma_0_un1_n
+11 1
+.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+11 1
+.names RST_c.BLIF clk_030_h_0_un3_n
+0 1
+.names N_114.BLIF N_114_i
+0 1
+.names N_52_i.BLIF RST_c.BLIF clk_030_h_0_un1_n
+11 1
+.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
+0 1
+.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
+11 1
+.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
+0 1
+.names N_197.BLIF rw_000_int_0_un3_n
+0 1
+.names state_machine_rw_000_int_7_iv_i_n.BLIF N_197.BLIF rw_000_int_0_un1_n
+11 1
+.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
+11 1
+.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n
+0 1
+.names N_67.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n
+11 1
+.names N_66.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
+state_machine_uds_000_int_7_0_m3_un0_n
+11 1
+.names N_77.BLIF ipl_030_0_0__un3_n
+0 1
+.names IPL_030DFFSH_0_reg.BLIF N_77.BLIF ipl_030_0_0__un1_n
11 1
.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
-.names N_76.BLIF ipl_030_0_1__un3_n
+.names N_77.BLIF ipl_030_0_1__un3_n
0 1
-.names IPL_030DFFSH_1_reg.BLIF N_76.BLIF ipl_030_0_1__un1_n
+.names IPL_030DFFSH_1_reg.BLIF N_77.BLIF ipl_030_0_1__un1_n
11 1
.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
11 1
-.names N_76.BLIF ipl_030_0_2__un3_n
+.names N_77.BLIF ipl_030_0_2__un3_n
0 1
-.names IPL_030DFFSH_2_reg.BLIF N_76.BLIF ipl_030_0_2__un1_n
+.names IPL_030DFFSH_2_reg.BLIF N_77.BLIF ipl_030_0_2__un1_n
11 1
.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
11 1
-.names N_76.BLIF cpu_estse_0_un3_n
+.names N_77.BLIF cpu_estse_0_un3_n
0 1
-.names cpu_est_1_.BLIF N_76.BLIF cpu_estse_0_un1_n
+.names cpu_est_1_.BLIF N_77.BLIF cpu_estse_0_un1_n
11 1
.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
11 1
-.names N_76.BLIF cpu_estse_1_un3_n
+.names N_77.BLIF cpu_estse_1_un3_n
0 1
-.names cpu_est_2_.BLIF N_76.BLIF cpu_estse_1_un1_n
+.names cpu_est_2_.BLIF N_77.BLIF cpu_estse_1_un1_n
11 1
.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
11 1
-.names N_76.BLIF cpu_estse_2_un3_n
+.names N_77.BLIF cpu_estse_2_un3_n
0 1
-.names cpu_est_3_reg.BLIF N_76.BLIF cpu_estse_2_un1_n
+.names cpu_est_3_reg.BLIF N_77.BLIF cpu_estse_2_un1_n
11 1
-.names N_151_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
+.names N_149_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
11 1
-.names N_51.BLIF amiga_bus_enable_0_un3_n
+.names N_30.BLIF as_030_000_sync_0_un3_n
0 1
-.names state_machine_amiga_bus_enable_4_iv_i_n.BLIF N_51.BLIF \
-amiga_bus_enable_0_un1_n
-11 1
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF amiga_bus_enable_0_un3_n.BLIF \
-amiga_bus_enable_0_un0_n
-11 1
-.names N_201.BLIF as_030_000_sync_0_un3_n
-0 1
-.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_201.BLIF as_030_000_sync_0_un1_n
+.names un1_DSACK1_INT_0_sqmuxa_3.BLIF N_30.BLIF as_030_000_sync_0_un1_n
11 1
.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \
as_030_000_sync_0_un0_n
11 1
-.names RST_c.BLIF clk_030_h_0_un3_n
+.names N_196.BLIF uds_000_int_0_un3_n
0 1
-.names N_48_i.BLIF RST_c.BLIF clk_030_h_0_un1_n
-11 1
-.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
-11 1
-.names N_199.BLIF uds_000_int_0_un3_n
-0 1
-.names state_machine_uds_000_int_7_n.BLIF N_199.BLIF uds_000_int_0_un1_n
+.names state_machine_uds_000_int_7_n.BLIF N_196.BLIF uds_000_int_0_un1_n
11 1
.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
11 1
-.names N_199.BLIF lds_000_int_0_un3_n
+.names N_196.BLIF lds_000_int_0_un3_n
0 1
-.names state_machine_lds_000_int_7_n.BLIF N_199.BLIF lds_000_int_0_un1_n
+.names state_machine_lds_000_int_7_n.BLIF N_196.BLIF lds_000_int_0_un1_n
11 1
.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
11 1
-.names N_200.BLIF fpu_cs_int_0_un3_n
+.names N_28.BLIF fpu_cs_int_0_un3_n
0 1
-.names AS_030_c.BLIF N_200.BLIF fpu_cs_int_0_un1_n
+.names AS_030_c.BLIF N_28.BLIF fpu_cs_int_0_un1_n
11 1
.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
+.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n
+0 1
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \
+avec_exp_0_un1_n
+11 1
+.names N_195_i.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n
+11 1
.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
-.names N_53.BLIF ds_000_dma_0_un3_n
+.names N_193.BLIF as_000_int_0_un3_n
0 1
-.names state_machine_ds_000_dma_3_n.BLIF N_53.BLIF ds_000_dma_0_un1_n
-11 1
-.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
-11 1
-.names N_198.BLIF as_000_dma_0_un3_n
-0 1
-.names state_machine_un8_bgack_030_int_i_0_n.BLIF N_198.BLIF \
-as_000_dma_0_un1_n
-11 1
-.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
-11 1
-.names N_197.BLIF as_000_int_0_un3_n
-0 1
-.names N_64.BLIF N_197.BLIF as_000_int_0_un1_n
+.names N_67.BLIF N_193.BLIF as_000_int_0_un1_n
11 1
.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
-.names inst_CLK_OUT_PRE_25.BLIF clk_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0
+.names N_75.BLIF dsack1_int_0_un3_n
+0 1
+.names N_114_i.BLIF N_75.BLIF dsack1_int_0_un1_n
+11 1
+.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
+11 1
+.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
+0 1
+.names state_machine_un10_clk_000_d0_n.BLIF \
+state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
+11 1
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+11 1
+.names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
+CLK_OUT_PRE_25_0
01 1
10 1
11 0
@@ -1076,7 +1080,7 @@ as_000_dma_0_un1_n
.names vcc_n_n.BLIF AVEC
1 1
0 0
-.names gnd_n_n.BLIF AVEC_EXP
+.names inst_avec_expreg.BLIF AVEC_EXP
1 1
0 0
.names cpu_est_3_reg.BLIF E
@@ -1088,7 +1092,7 @@ as_000_dma_0_un1_n
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
@@ -1097,7 +1101,7 @@ as_000_dma_0_un1_n
.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
-.names N_228.BLIF CIIN
+.names N_220.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
@@ -1235,12 +1239,6 @@ as_000_dma_0_un1_n
.names RST_i.BLIF SIZE_DMA_0_.AP
1 1
0 0
-.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
-1 1
-0 0
-.names RST_i.BLIF inst_UDS_000_INT.AP
-1 1
-0 0
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
1 1
0 0
@@ -1253,6 +1251,12 @@ as_000_dma_0_un1_n
.names RST_i.BLIF inst_FPU_CS_INTreg.AP
1 1
0 0
+.names CLK_OSZI_c.BLIF inst_avec_expreg.C
+1 1
+0 0
+.names RST_i.BLIF inst_avec_expreg.AP
+1 1
+0 0
.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
1 1
0 0
@@ -1277,10 +1281,10 @@ as_000_dma_0_un1_n
.names RST_i.BLIF inst_AS_000_INT.AP
1 1
0 0
-.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFSHreg.C
+.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
1 1
0 0
-.names RST_i.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP
+.names RST_i.BLIF inst_RW_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
@@ -1292,21 +1296,18 @@ as_000_dma_0_un1_n
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
1 1
0 0
+.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
+1 1
+0 0
+.names RST_i.BLIF inst_UDS_000_INT.AP
+1 1
+0 0
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
1 1
0 0
.names RST_i.BLIF inst_A0_DMA.AP
1 1
0 0
-.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
-1 1
-0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C
-1 1
-0 0
-.names RST_i.BLIF inst_CLK_000_D4.AP
-1 1
-0 0
.names DTACK.PIN.BLIF inst_DTACK_D0.D
1 1
0 0
@@ -1316,15 +1317,6 @@ as_000_dma_0_un1_n
.names RST_i.BLIF inst_DTACK_D0.AP
1 1
0 0
-.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
-1 1
-0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
-1 1
-0 0
-.names RST_i.BLIF inst_CLK_000_D3.AP
-1 1
-0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
@@ -1343,6 +1335,15 @@ as_000_dma_0_un1_n
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
0 0
+.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
+1 1
+0 0
+.names RST_i.BLIF inst_CLK_000_D3.AP
+1 1
+0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
@@ -1406,15 +1407,15 @@ as_000_dma_0_un1_n
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
-.names inst_DSACK1_INT.BLIF DSACK_1_
-1 1
-0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
@@ -1427,13 +1428,22 @@ as_000_dma_0_un1_n
.names inst_A0_DMA.BLIF A0
1 1
0 0
-.names dsack_c_1__n.BLIF DTACK
+.names inst_DSACK1_INT.BLIF DSACK1
+1 1
+0 0
+.names DSACK1_c.BLIF DTACK
+1 1
+0 0
+.names inst_RW_000_INT.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
-.names vcc_n_n.BLIF DSACK_0_
+.names BG_030.BLIF BG_030_c
+1 1
+0 0
+.names BGACK_000.BLIF BGACK_000_c
1 1
0 0
.names CLK_030.BLIF CLK_030_c
@@ -1454,13 +1464,13 @@ as_000_dma_0_un1_n
.names IPL_2_.BLIF ipl_c_2__n
1 1
0 0
-.names DSACK_1_.PIN.BLIF dsack_c_1__n
+.names DSACK1.PIN.BLIF DSACK1_c
1 1
0 0
.names RST.BLIF RST_c
1 1
0 0
-.names RW.BLIF RW_c
+.names RW.PIN.BLIF RW_c
1 1
0 0
.names FC_0_.BLIF fc_c_0__n
@@ -1475,6 +1485,9 @@ as_000_dma_0_un1_n
.names AS_000.PIN.BLIF AS_000_c
1 1
0 0
+.names RW_000.PIN.BLIF RW_000_c
+1 1
+0 0
.names DS_030.PIN.BLIF DS_030_c
1 1
0 0
@@ -1544,19 +1557,16 @@ as_000_dma_0_un1_n
.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
-.names BG_030.BLIF BG_030_c
-1 1
-0 0
-.names BGACK_000.BLIF BGACK_000_c
-1 1
-0 0
-.names N_147.BLIF AS_030.OE
+.names N_148.BLIF AS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
-.names N_147.BLIF DS_030.OE
+.names inst_BGACK_030_INTreg.BLIF RW_000.OE
+1 1
+0 0
+.names N_148.BLIF DS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
@@ -1565,31 +1575,28 @@ as_000_dma_0_un1_n
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
-.names N_147.BLIF SIZE_0_.OE
+.names N_148.BLIF SIZE_0_.OE
1 1
0 0
-.names N_147.BLIF SIZE_1_.OE
+.names N_148.BLIF SIZE_1_.OE
1 1
0 0
-.names N_147.BLIF A0.OE
+.names N_148.BLIF A0.OE
1 1
0 0
-.names nEXP_SPACE_c.BLIF DSACK_1_.OE
+.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
0 0
-.names N_147.BLIF DTACK.OE
+.names N_148.BLIF DTACK.OE
+1 1
+0 0
+.names BGACK_030_INT_i.BLIF RW.OE
1 1
0 0
.names FPU_CS_INT_i.BLIF BERR.OE
1 1
0 0
-.names nEXP_SPACE_c.BLIF DSACK_0_.OE
-1 1
-0 0
-.names FPU_CS_INT_i.BLIF AVEC_EXP.OE
-1 1
-0 0
-.names N_225.BLIF CIIN.OE
+.names N_230.BLIF CIIN.OE
1 1
0 0
.end
diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3
index c4088f7..87a1d7b 100644
--- a/Logic/68030_tk.bl3
+++ b/Logic/68030_tk.bl3
@@ -1,44 +1,43 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ \
-# IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 \
-# UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
-# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \
-# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
-# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 44 inst_BGACK_030_INTreg CLK_OUT_INTreg inst_FPU_CS_INTreg \
-# inst_VMA_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_BGACK_030_INT_D \
-# inst_AS_000_DMA IPL_030DFFSH_1_reg inst_VPA_D inst_CLK_OUT_PRE_50_D \
-# IPL_030DFFSH_2_reg inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D4 \
-# inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_AS_000_INT SM_AMIGA_1_ \
-# SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_UDS_000_INT inst_LDS_000_INT \
-# inst_DSACK1_INT inst_CLK_000_D3 inst_CLK_030_H RESETDFFRHreg inst_DS_000_DMA \
-# SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA SM_AMIGA_7_ AMIGA_BUS_ENABLEDFFSHreg \
-# SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_reg \
-# BG_000DFFSHreg
+#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ \
+# IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 \
+# IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 \
+# CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET \
+# RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
+# A_28_ A_27_
+#$ NODES 44 BG_000DFFSHreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg \
+# inst_avec_expreg inst_VMA_INTreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \
+# inst_AS_000_DMA inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg \
+# inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 IPL_030DFFSH_0_reg \
+# inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ \
+# IPL_030DFFSH_2_reg inst_AS_000_INT SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ \
+# inst_RW_000_INT inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT inst_CLK_000_D3 \
+# inst_CLK_030_H inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA RESETDFFRHreg \
+# SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_reg
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
-RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
-A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \
-A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
-inst_BGACK_030_INTreg.BLIF CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \
-inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \
-inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF IPL_030DFFSH_1_reg.BLIF \
-inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF IPL_030DFFSH_2_reg.BLIF \
-inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \
-inst_CLK_000_D4.BLIF inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF \
-inst_CLK_OUT_PRE_25.BLIF inst_AS_000_INT.BLIF SM_AMIGA_1_.BLIF \
-SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF inst_UDS_000_INT.BLIF \
-inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF inst_CLK_000_D3.BLIF \
-inst_CLK_030_H.BLIF RESETDFFRHreg.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF \
-SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF SM_AMIGA_7_.BLIF \
-AMIGA_BUS_ENABLEDFFSHreg.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
-SM_AMIGA_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
-cpu_est_3_reg.BLIF BG_000DFFSHreg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
-DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
-SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
+A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
+A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
+A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF BG_000DFFSHreg.BLIF \
+inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF \
+inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_AS_000_DMA.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF \
+inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF inst_CLK_000_D1.BLIF \
+inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF IPL_030DFFSH_0_reg.BLIF \
+inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF IPL_030DFFSH_1_reg.BLIF \
+SM_AMIGA_7_.BLIF IPL_030DFFSH_2_reg.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \
+SM_AMIGA_0_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF \
+inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \
+inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF \
+SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF \
+SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
+cpu_est_2_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
+RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
+SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \
+RW.PIN.BLIF
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \
@@ -55,30 +54,29 @@ SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR inst_DSACK1_INT.D \
inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP \
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \
inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR \
-SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP inst_UDS_000_INT.D \
-inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_LDS_000_INT.D inst_LDS_000_INT.C \
-inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \
-inst_FPU_CS_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \
-inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D \
-inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D inst_AS_000_INT.C \
-inst_AS_000_INT.AP AMIGA_BUS_ENABLEDFFSHreg.D AMIGA_BUS_ENABLEDFFSHreg.C \
-AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
-inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_A0_DMA.D \
-inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_000_D4.D inst_CLK_000_D4.C \
-inst_CLK_000_D4.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP \
-inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D2.D \
-inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
-CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \
+SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP inst_LDS_000_INT.D \
+inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \
+inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \
+inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
+BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \
+inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \
+inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C \
+inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
+inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D \
+inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \
+inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP \
+inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D \
+CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D inst_CLK_000_D3.C \
+inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \
inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \
inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \
inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
inst_CLK_OUT_PRE_50.AR RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR \
-SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 DTACK SIZE_0_ \
-DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
-SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \
-inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 \
-cpu_est_3_reg.D.X2
+SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ \
+AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
+SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE inst_VMA_INTreg.D.X1 \
+inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D
100 1
-11 1
@@ -112,16 +110,11 @@ cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D
--010- 0
-1--0- 0
0---0- 0
-.names inst_CLK_000_D0.BLIF inst_CLK_000_D4.BLIF inst_AS_000_INT.BLIF \
-SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_0_.D
-01-1-- 1
---0-1- 1
-0--1-0 1
-0---1- 1
-1-1--- 0
----00- 0
--0--01 0
-1---0- 0
+.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.D
+01- 1
+0-1 1
+-00 0
+1-- 0
.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF SIZE_DMA_1_.D
--00 1
@@ -130,57 +123,53 @@ LDS_000.PIN.BLIF SIZE_DMA_1_.D
1--- 1
0010 0
0001 0
-.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \
-inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D
-1-10 1
--10- 1
--1-1 1
-0-10 0
--00- 0
--0-1 0
-.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \
-inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D
-1-10 1
--10- 1
--1-1 1
-0-10 0
--00- 0
--0-1 0
-.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF \
-inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D
-1-10 1
--10- 1
--1-1 1
-0-10 0
--00- 0
--0-1 0
+.names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D
+110- 1
+--11 1
+-0-1 1
+010- 0
+--10 0
+-0-0 0
+.names IPL_1_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_1_reg.D
+110- 1
+--11 1
+-0-1 1
+010- 0
+--10 0
+-0-0 0
+.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D
+110- 1
+--11 1
+-0-1 1
+010- 0
+--10 0
+-0-0 0
.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \
-inst_CLK_000_D2.BLIF inst_AS_000_INT.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \
-inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_7_.D
-0-0---1-- 1
---1-11--- 1
--------01 1
----1----1 1
--1------1 1
--000--01- 0
--010-0-1- 0
--0100--1- 0
-1000---1- 0
---0---0-0 0
---1--0--0 0
---1-0---0 0
-1-0-----0 0
+inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF inst_CLK_000_D3.BLIF \
+SM_AMIGA_7_.D
+--1--1- 1
+---11-- 1
+-1--1-- 1
+0---1-- 1
+----1-0 1
+10-0-01 0
+1000--1 0
+----00- 0
+--0-0-- 0
.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \
-inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF \
+inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF \
SM_AMIGA_6_.D
-1-0-1-0 1
--0-0-11 1
-----0-0 0
---1---0 0
-0-----0 0
------01 0
----1--1 0
--1----1 0
+10-01-1 1
+--0-01- 1
+----00- 0
+--1-0-- 0
+---11-- 0
+-1--1-- 0
+0---1-- 0
+----1-0 0
.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
11- 1
1-1 1
@@ -206,37 +195,31 @@ cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_3_.D
-----00-- 0
--0---0-- 0
.names inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \
-inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
+inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_3_.BLIF \
cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_2_.D
-0001-1-01 1
--10101--- 1
---0---1-- 1
--1--1-0-- 0
--0----01- 0
-10----0-- 0
+0001--101 1
+-1010-1-- 1
+--0--1--- 1
+-1--10--- 0
+-0---0-1- 0
+10---0--- 0
-----00-- 0
----0--0-- 0
--0----0-0 0
+---0-0--- 0
+-0---0--0 0
--1------ 0
-.names inst_CLK_000_D0.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF \
-inst_CLK_000_D3.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
--011- 1
-1-1-- 1
-1---1 1
-0--0- 0
-01--- 0
-0-0-- 0
---0-0 0
-.names inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF inst_DSACK1_INT.BLIF \
-inst_CLK_000_D3.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D
---10- 1
--01-- 1
-1-1-- 1
----01 1
--0--1 1
-1---1 1
-01-1- 0
---0-0 0
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_1_.D
+11- 1
+1-1 1
+-00 0
+0-- 0
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF inst_DSACK1_INT.BLIF \
+AS_030.PIN.BLIF inst_DSACK1_INT.D
+-01- 1
+0-1- 1
+-0-1 1
+0--1 1
+11-- 0
+--00 0
.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D
1-10 1
@@ -251,54 +234,32 @@ LDS_000.PIN.BLIF SIZE_DMA_0_.D
1--- 1
---1 1
0000 0
-.names RW.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_5_.BLIF \
-inst_UDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF \
-A0.PIN.BLIF inst_UDS_000_INT.D
-01---1-01 1
-1-11---01 1
-0---10--- 1
-1--01---- 1
-1-0-1---- 1
-00--1---- 1
-0----01-- 1
-1--0--1-- 1
-1-0---1-- 1
-00----1-- 1
-----1--1- 1
-------11- 1
-01---1-00 0
-1-11---00 0
-0---000-- 0
-1--00-0-- 0
-1-0-0-0-- 0
-00--0-0-- 0
-----0-01- 0
-.names RW.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_5_.BLIF \
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF \
inst_LDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF \
-SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
-01---1-0100 1
-1-11---0100 1
-0---10----- 1
-1--01------ 1
-1-0-1------ 1
-00--1------ 1
-----1--1--- 1
-0----01---- 1
-1--0--1---- 1
-1-0---1---- 1
-00----1---- 1
-------11--- 1
-01---1-0-1- 0
-1-11---0-1- 0
-01---1-00-- 0
-1-11---00-- 0
-01---1-0--1 0
-1-11---0--1 0
-0---000---- 0
-1--00-0---- 0
-1-0-0-0---- 0
-00--0-0---- 0
-----0-01--- 0
+SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF RW.PIN.BLIF inst_LDS_000_INT.D
+1---1-01000 1
+-11---01001 1
+---10-----0 1
+0--1------0 1
+--01------1 1
+-0-1------1 1
+---1--1---- 1
+----01----0 1
+0----1----0 1
+--0--1----1 1
+-0---1----1 1
+-----11---- 1
+1---1-0--10 0
+1---1-0-1-0 0
+1---1-00--0 0
+-11---0--11 0
+-11---0-1-1 0
+-11---00--1 0
+---000----0 0
+0--0-0----0 0
+--00-0----1 0
+-0-0-0----1 0
+---0-01---- 0
.names FC_1_.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF AS_030.PIN.BLIF \
inst_FPU_CS_INTreg.D
@@ -313,33 +274,45 @@ inst_FPU_CS_INTreg.D
---------1 1
11100101-0 0
--------00 0
-.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF SM_AMIGA_7_.BLIF \
-BG_000DFFSHreg.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D
----01- 1
---0-1- 1
-0---1- 1
-----10 1
+.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_avec_expreg.BLIF \
+inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_CLK_000_D2.BLIF \
+SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF inst_avec_expreg.D
+-11---0- 1
+-1---11- 1
+-1-1--1- 1
+01----1- 1
+-1--0--- 1
+-1----10 1
+1--01011 0
+--0-1-0- 0
+-0------ 0
+.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF BG_000DFFSHreg.BLIF \
+SM_AMIGA_7_.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D
+---10- 1
+--01-- 1
+0--1-- 1
+---1-0 1
-1---- 1
-1011-1 0
--0--0- 0
-.names CLK_030.BLIF RW.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
-inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
-LDS_000.PIN.BLIF inst_DS_000_DMA.D
-0--11---- 1
--0--01--- 1
-10---1--- 1
--1-1----- 1
-------1-- 1
---1------ 1
+101-11 0
+-0-0-- 0
+.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
+inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
+UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_DS_000_DMA.D
+0-11----- 1
+---01-0-- 1
+1---1-0-- 1
+--1---1-- 1
+-----1--- 1
+-1------- 1
-------11 1
-0-001-00- 0
--00-0000- 0
-100--000- 0
-0-001-0-0 0
--00-000-0 0
-100--00-0 0
--100--00- 0
--100--0-0 0
+0001-0-0- 0
+-0-00000- 0
+10--0000- 0
+0001-0--0 0
+-0-0000-0 0
+10--000-0 0
+-00--010- 0
+-00--01-0 0
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AS_000_DMA.D
1-1--- 1
@@ -350,7 +323,7 @@ AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AS_000_DMA.D
00-00- 0
-000-0 0
00-0-0 0
-.names inst_CLK_000_D4.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF \
+.names inst_CLK_000_D2.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF \
AS_030.PIN.BLIF inst_AS_000_INT.D
-10- 1
01-- 1
@@ -358,63 +331,77 @@ AS_030.PIN.BLIF inst_AS_000_INT.D
0--1 1
1-1- 0
-0-0 0
-.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
-inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \
-AMIGA_BUS_ENABLEDFFSHreg.BLIF AS_030.PIN.BLIF AMIGA_BUS_ENABLEDFFSHreg.D
--1----01- 1
-01-----1- 1
-11-1--1-- 1
--1---10-1 1
--1--1-0-1 1
-01---1--1 1
-01--1---1 1
--10------ 1
---1-0000- 0
-0-1-00-0- 0
-1-10--1-- 0
---1---000 0
-0-1----00 0
--0------- 0
+.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
+SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF AS_000.PIN.BLIF \
+RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF RW.PIN.BLIF \
+inst_RW_000_INT.D
+00----01-0- 1
+00----010-- 1
+---0-1--11- 1
+--101---11- 1
+--0--1--11- 1
+--11----111 1
+---0-11---- 1
+-1-0-1----- 1
+1--0-1----- 1
+--101-1---- 1
+-1101------ 1
+1-101------ 1
+--0--11---- 1
+-10--1----- 1
+1-0--1----- 1
+--11--1---1 1
+-111------1 1
+1-11------1 1
+00----00-0- 0
+00----000-- 0
+---000--11- 0
+--11----110 0
+--0--0--11- 0
+---0001---- 0
+-1-000----- 0
+1--000----- 0
+--11--1---0 0
+-111------0 0
+1-11------0 0
+--0--01---- 0
+-10--0----- 0
+1-0--0----- 0
.names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \
A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
-inst_AS_030_000_SYNC.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF \
-SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF AS_030.PIN.BLIF \
+inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF \
+SM_AMIGA_7_.BLIF SM_AMIGA_2_.BLIF inst_CLK_000_D3.BLIF AS_030.PIN.BLIF \
inst_AS_030_000_SYNC.D
1-1-00101-1------ 1
------------01-1-- 1
--0-----------1--- 1
-----------1----0- 1
+-0----------01-1- 1
+-----------1--1-- 1
+----------1--0--- 1
---------01------ 1
---0------1------ 1
-0--------1------ 1
----------------1 1
--1-1----01----010 0
--1-1---1-1----010 0
--1-1--0--1----010 0
--1-1-1---1----010 0
--1-11----1----010 0
--101-----1----010 0
-01-1-----1----010 0
--1-1----01--0--10 0
--1-1---1-1--0--10 0
--1-1--0--1--0--10 0
--1-1-1---1--0--10 0
--1-11----1--0--10 0
--101-----1--0--10 0
-01-1-----1--0--10 0
--1-1----01-1---10 0
--1-1---1-1-1---10 0
--1-1--0--1-1---10 0
--1-1-1---1-1---10 0
--1-11----1-1---10 0
--101-----1-1---10 0
-01-1-----1-1---10 0
+-1-1----01---10-0 0
+-1-1---1-1---10-0 0
+-1-1--0--1---10-0 0
+-1-1-1---1---10-0 0
+-1-11----1---10-0 0
+-101-----1---10-0 0
+01-1-----1---10-0 0
+-1-1----01-0-1--0 0
+-1-1---1-1-0-1--0 0
+-1-1--0--1-0-1--0 0
+-1-1-1---1-0-1--0 0
+-1-11----1-0-1--0 0
+-101-----1-0-1--0 0
+01-1-----1-0-1--0 0
+----------0---000 0
+----------00---00 0
----------0--00-0 0
-----------0-00--0 0
-----------01-0--0 0
+----------0-1-0-0 0
+----------00-0--0 0
+----------001---0 0
-1--------0---0-0 0
--1--------0-0---0 0
--1--------01----0 0
+-1--------00----0 0
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
inst_CLK_030_H.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
inst_CLK_030_H.D
@@ -429,6 +416,28 @@ inst_CLK_030_H.D
---10--- 0
-0--0--- 0
0---0--- 0
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF \
+inst_UDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF \
+A0.PIN.BLIF RW.PIN.BLIF inst_UDS_000_INT.D
+1---1-010 1
+-11---011 1
+---10---0 1
+0--1----0 1
+--01----1 1
+-0-1----1 1
+---1--1-- 1
+----01--0 1
+0----1--0 1
+--0--1--1 1
+-0---1--1 1
+-----11-- 1
+1---1-000 0
+-11---001 0
+---000--0 0
+0--0-0--0 0
+--00-0--1 0
+-0-0-0--1 0
+---0-01-- 0
.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
LDS_000.PIN.BLIF inst_A0_DMA.D
0010 1
@@ -461,8 +470,9 @@ LDS_000.PIN.BLIF inst_A0_DMA.D
0 0
.names AVEC
1
-.names AVEC_EXP
- 0
+.names inst_avec_expreg.BLIF AVEC_EXP
+1 1
+0 0
.names cpu_est_3_reg.BLIF E
1 1
0 0
@@ -472,17 +482,17 @@ LDS_000.PIN.BLIF inst_A0_DMA.D
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
-.names nEXP_SPACE.BLIF RW.BLIF inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF \
+.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF RW.PIN.BLIF \
AMIGA_BUS_DATA_DIR
-0100 1
--01- 1
-1-0- 0
---01 0
--00- 0
--11- 0
+0001 1
+-1-0 1
+1--1 0
+--11 0
+-0-0 0
+-1-1 0
.names AMIGA_BUS_ENABLE_LOW
1
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
@@ -631,12 +641,6 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names RST.BLIF SIZE_DMA_0_.AP
0 1
1 0
-.names CLK_OSZI.BLIF inst_UDS_000_INT.C
-1 1
-0 0
-.names RST.BLIF inst_UDS_000_INT.AP
-0 1
-1 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
@@ -649,6 +653,12 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names RST.BLIF inst_FPU_CS_INTreg.AP
0 1
1 0
+.names CLK_OSZI.BLIF inst_avec_expreg.C
+1 1
+0 0
+.names RST.BLIF inst_avec_expreg.AP
+0 1
+1 0
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
1 1
0 0
@@ -673,10 +683,10 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names RST.BLIF inst_AS_000_INT.AP
0 1
1 0
-.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFSHreg.C
+.names CLK_OSZI.BLIF inst_RW_000_INT.C
1 1
0 0
-.names RST.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP
+.names RST.BLIF inst_RW_000_INT.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
@@ -688,21 +698,18 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names CLK_OSZI.BLIF inst_CLK_030_H.C
1 1
0 0
+.names CLK_OSZI.BLIF inst_UDS_000_INT.C
+1 1
+0 0
+.names RST.BLIF inst_UDS_000_INT.AP
+0 1
+1 0
.names CLK_OSZI.BLIF inst_A0_DMA.C
1 1
0 0
.names RST.BLIF inst_A0_DMA.AP
0 1
1 0
-.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
-1 1
-0 0
-.names CLK_OSZI.BLIF inst_CLK_000_D4.C
-1 1
-0 0
-.names RST.BLIF inst_CLK_000_D4.AP
-0 1
-1 0
.names DTACK.PIN.BLIF inst_DTACK_D0.D
1 1
0 0
@@ -712,15 +719,6 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names RST.BLIF inst_DTACK_D0.AP
0 1
1 0
-.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
-1 1
-0 0
-.names CLK_OSZI.BLIF inst_CLK_000_D3.C
-1 1
-0 0
-.names RST.BLIF inst_CLK_000_D3.AP
-0 1
-1 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
@@ -739,6 +737,15 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names RST.BLIF CLK_OUT_INTreg.AR
0 1
1 0
+.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_000_D3.C
+1 1
+0 0
+.names RST.BLIF inst_CLK_000_D3.AP
+0 1
+1 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
@@ -801,15 +808,15 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
-.names inst_DSACK1_INT.BLIF DSACK_1_
-1 1
-0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
@@ -822,14 +829,18 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
.names inst_A0_DMA.BLIF A0
1 1
0 0
-.names DSACK_1_.PIN.BLIF DTACK
+.names inst_DSACK1_INT.BLIF DSACK1
+1 1
+0 0
+.names DSACK1.PIN.BLIF DTACK
+1 1
+0 0
+.names inst_RW_000_INT.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
-.names DSACK_0_
- 1
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
AS_030.OE
000 1
@@ -839,6 +850,9 @@ AS_030.OE
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
+.names inst_BGACK_030_INTreg.BLIF RW_000.OE
+1 1
+0 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
DS_030.OE
000 1
@@ -868,7 +882,7 @@ SIZE_1_.OE
-1- 0
1-- 0
--1 0
-.names nEXP_SPACE.BLIF DSACK_1_.OE
+.names nEXP_SPACE.BLIF DSACK1.OE
1 1
0 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
@@ -877,13 +891,10 @@ DTACK.OE
-1- 0
1-- 0
--1 0
-.names inst_FPU_CS_INTreg.BLIF BERR.OE
+.names inst_BGACK_030_INTreg.BLIF RW.OE
0 1
1 0
-.names nEXP_SPACE.BLIF DSACK_0_.OE
-1 1
-0 0
-.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
+.names inst_FPU_CS_INTreg.BLIF BERR.OE
0 1
1 0
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf
index 8777495..c8e7089 100644
--- a/Logic/68030_tk.crf
+++ b/Logic/68030_tk.crf
@@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
-// Design '68030_tk' created Thu May 29 22:04:27 2014
+// Design '68030_tk' created Sun Jun 01 01:03:24 2014
// LEGEND: '>' Functional Block Port Separator
diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3
index fd1eea7..9a0f404 100644
--- a/Logic/68030_tk.eq3
+++ b/Logic/68030_tk.eq3
@@ -2,13 +2,13 @@
Copyright(C), 1992-2013, Lattice Semiconductor Corp.
All Rights Reserved.
-Design bus68030 created Thu May 29 22:04:27 2014
+Design bus68030 created Sun Jun 01 01:03:24 2014
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
- 1 0 1 Pin DSACK_0_
- 1 1 1 Pin DSACK_0_.OE
+ 1 1 1 Pin RW_000
+ 1 1 1 Pin RW_000.OE
0 0 1 Pin BERR
1 1 1 Pin BERR.OE
1 1 1 Pin CLK_DIV_OUT.AR
@@ -17,8 +17,12 @@ Design bus68030 created Thu May 29 22:04:27 2014
1 1 1 Pin DTACK
1 3 1 Pin DTACK.OE
1 0 1 Pin AVEC
- 0 0 1 Pin AVEC_EXP
- 1 1 1 Pin AVEC_EXP.OE
+ 3 8 1 Pin AVEC_EXP.D-
+ 1 1 1 Pin AVEC_EXP.AP
+ 1 1 1 Pin AVEC_EXP.C
+ 1 1 1 Pin RW
+ 1 1 1 Pin RW.OE
+ 1 1 1 Pin AMIGA_BUS_ENABLE
2 4 1 Pin AMIGA_BUS_DATA_DIR
1 0 1 Pin AMIGA_BUS_ENABLE_LOW
1 4 1 Pin CIIN
@@ -30,24 +34,20 @@ Design bus68030 created Thu May 29 22:04:27 2014
3 4 1 Pin IPL_030_2_.D
1 1 1 Pin IPL_030_2_.AP
1 1 1 Pin IPL_030_2_.C
- 3 4 1 Pin IPL_030_1_.D
- 1 1 1 Pin IPL_030_1_.AP
- 1 1 1 Pin IPL_030_1_.C
- 3 4 1 Pin IPL_030_0_.D
- 1 1 1 Pin IPL_030_0_.AP
- 1 1 1 Pin IPL_030_0_.C
- 1 1 1 Pin DSACK_1_.OE
- 2 5 1 Pin DSACK_1_.D-
- 1 1 1 Pin DSACK_1_.AP
- 1 1 1 Pin DSACK_1_.C
1 3 1 Pin AS_030.OE
4 6 1 Pin AS_030.D
1 1 1 Pin AS_030.AP
1 1 1 Pin AS_030.C
+ 3 4 1 Pin IPL_030_1_.D
+ 1 1 1 Pin IPL_030_1_.AP
+ 1 1 1 Pin IPL_030_1_.C
1 1 1 Pin AS_000.OE
2 4 1 Pin AS_000.D-
1 1 1 Pin AS_000.AP
1 1 1 Pin AS_000.C
+ 3 4 1 Pin IPL_030_0_.D
+ 1 1 1 Pin IPL_030_0_.AP
+ 1 1 1 Pin IPL_030_0_.C
1 3 1 Pin DS_030.OE
7 9 1 Pin DS_030.D
1 1 1 Pin DS_030.AP
@@ -76,6 +76,10 @@ Design bus68030 created Thu May 29 22:04:27 2014
2 10 1 Pin FPU_CS.D-
1 1 1 Pin FPU_CS.AP
1 1 1 Pin FPU_CS.C
+ 1 1 1 Pin DSACK1.OE
+ 2 4 1 Pin DSACK1.D-
+ 1 1 1 Pin DSACK1.AP
+ 1 1 1 Pin DSACK1.C
3 6 1 PinX1 E.D.X1
1 1 1 PinX2 E.D.X2
1 1 1 Pin E.AR
@@ -87,9 +91,6 @@ Design bus68030 created Thu May 29 22:04:27 2014
1 1 1 Pin RESET.AR
1 0 1 Pin RESET.D
1 1 1 Pin RESET.C
- 6 9 1 Pin AMIGA_BUS_ENABLE.D-
- 1 1 1 Pin AMIGA_BUS_ENABLE.AP
- 1 1 1 Pin AMIGA_BUS_ENABLE.C
1 3 1 Pin SIZE_0_.OE
1 4 1 Pin SIZE_0_.D-
1 1 1 Pin SIZE_0_.AP
@@ -115,9 +116,6 @@ Design bus68030 created Thu May 29 22:04:27 2014
1 1 1 Node inst_CLK_000_D2.D
1 1 1 Node inst_CLK_000_D2.AP
1 1 1 Node inst_CLK_000_D2.C
- 1 1 1 Node inst_CLK_000_D4.D
- 1 1 1 Node inst_CLK_000_D4.AP
- 1 1 1 Node inst_CLK_000_D4.C
1 1 1 Node inst_DTACK_D0.D
1 1 1 Node inst_DTACK_D0.AP
1 1 1 Node inst_DTACK_D0.C
@@ -127,35 +125,38 @@ Design bus68030 created Thu May 29 22:04:27 2014
1 1 1 Node inst_CLK_OUT_PRE_25.AR
3 3 1 Node inst_CLK_OUT_PRE_25.D
1 1 1 Node inst_CLK_OUT_PRE_25.C
- 1 1 1 Node SM_AMIGA_1_.AR
- 3 5 1 Node SM_AMIGA_1_.D
- 1 1 1 Node SM_AMIGA_1_.C
- 1 1 1 Node SM_AMIGA_0_.AR
- 4 6 1 Node SM_AMIGA_0_.D
- 1 1 1 Node SM_AMIGA_0_.C
+ 4 7 1 Node SM_AMIGA_7_.D-
+ 1 1 1 Node SM_AMIGA_7_.AP
+ 1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node SM_AMIGA_6_.AR
2 7 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
+ 1 1 1 Node SM_AMIGA_0_.AR
+ 2 3 1 Node SM_AMIGA_0_.D
+ 1 1 1 Node SM_AMIGA_0_.C
1 1 1 Node SM_AMIGA_5_.AR
2 3 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
+ 1 1 1 Node SM_AMIGA_2_.AR
+ 3 9 1 Node SM_AMIGA_2_.D
+ 1 1 1 Node SM_AMIGA_2_.C
+ 14 11 1 Node inst_RW_000_INT.D-
+ 1 1 1 Node inst_RW_000_INT.AP
+ 1 1 1 Node inst_RW_000_INT.C
1 1 1 Node inst_CLK_000_D3.D
1 1 1 Node inst_CLK_000_D3.AP
1 1 1 Node inst_CLK_000_D3.C
5 8 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
- 5 9 1 Node SM_AMIGA_7_.D
- 1 1 1 Node SM_AMIGA_7_.AP
- 1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node SM_AMIGA_4_.AR
2 3 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
1 1 1 Node SM_AMIGA_3_.AR
4 9 1 Node SM_AMIGA_3_.D-
1 1 1 Node SM_AMIGA_3_.C
- 1 1 1 Node SM_AMIGA_2_.AR
- 3 9 1 Node SM_AMIGA_2_.D
- 1 1 1 Node SM_AMIGA_2_.C
+ 1 1 1 Node SM_AMIGA_1_.AR
+ 2 3 1 Node SM_AMIGA_1_.D
+ 1 1 1 Node SM_AMIGA_1_.C
1 1 1 Node cpu_est_0_.AR
3 3 1 Node cpu_est_0_.D
1 1 1 Node cpu_est_0_.C
@@ -167,7 +168,7 @@ Design bus68030 created Thu May 29 22:04:27 2014
1 1 1 Node cpu_est_2_.AR
1 1 1 Node cpu_est_2_.C
=========
- 240 P-Term Total: 240
+ 248 P-Term Total: 248
Total Pins: 59
Total Nodes: 24
Average P-Term/Output: 2
@@ -175,9 +176,9 @@ Design bus68030 created Thu May 29 22:04:27 2014
Equations:
-DSACK_0_ = (1);
+RW_000 = (inst_RW_000_INT.Q);
-DSACK_0_.OE = (nEXP_SPACE);
+RW_000.OE = (BGACK_030.Q);
BERR = (0);
@@ -189,18 +190,28 @@ CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
-DTACK = (DSACK_1_.PIN);
+DTACK = (DSACK1.PIN);
DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
AVEC = (1);
-AVEC_EXP = (0);
+!AVEC_EXP.D = (!BGACK_030.Q
+ # inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !AVEC_EXP
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
-AVEC_EXP.OE = (!FPU_CS.Q);
+AVEC_EXP.AP = (!RST);
-AMIGA_BUS_DATA_DIR = (!RW & BGACK_030.Q
- # !nEXP_SPACE & RW & !BGACK_030.Q & !AS_000.PIN);
+AVEC_EXP.C = (CLK_OSZI);
+
+RW = (inst_RW_000_INT.Q);
+
+RW.OE = (!BGACK_030.Q);
+
+AMIGA_BUS_ENABLE = (AVEC_EXP);
+
+AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
+ # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);
AMIGA_BUS_ENABLE_LOW = (1);
@@ -217,39 +228,14 @@ SIZE_1_.AP = (!RST);
SIZE_1_.C = (CLK_OSZI);
-IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q
- # IPL_030_2_.Q & inst_CLK_000_D1.Q
+IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
+ # inst_CLK_000_D1.Q & IPL_030_2_.Q
# IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
IPL_030_2_.AP = (!RST);
IPL_030_2_.C = (CLK_OSZI);
-IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D0.Q
- # IPL_030_1_.Q & inst_CLK_000_D1.Q
- # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
-
-IPL_030_1_.AP = (!RST);
-
-IPL_030_1_.C = (CLK_OSZI);
-
-IPL_030_0_.D = (IPL_030_0_.Q & !inst_CLK_000_D0.Q
- # IPL_030_0_.Q & inst_CLK_000_D1.Q
- # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
-
-IPL_030_0_.AP = (!RST);
-
-IPL_030_0_.C = (CLK_OSZI);
-
-DSACK_1_.OE = (nEXP_SPACE);
-
-!DSACK_1_.D = (!DSACK_1_.Q & !AS_030.PIN
- # !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q & inst_CLK_000_D3.Q);
-
-DSACK_1_.AP = (!RST);
-
-DSACK_1_.C = (CLK_OSZI);
-
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
AS_030.D = (BGACK_030.Q
@@ -261,24 +247,40 @@ AS_030.AP = (!RST);
AS_030.C = (CLK_OSZI);
+IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
+ # inst_CLK_000_D1.Q & IPL_030_1_.Q
+ # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_1_.AP = (!RST);
+
+IPL_030_1_.C = (CLK_OSZI);
+
AS_000.OE = (BGACK_030.Q);
-!AS_000.D = (inst_CLK_000_D4.Q & SM_AMIGA_5_.Q
+!AS_000.D = (inst_CLK_000_D2.Q & SM_AMIGA_5_.Q
# !AS_000.Q & !AS_030.PIN);
AS_000.AP = (!RST);
AS_000.C = (CLK_OSZI);
+IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
+ # inst_CLK_000_D1.Q & IPL_030_0_.Q
+ # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_0_.AP = (!RST);
+
+IPL_030_0_.C = (CLK_OSZI);
+
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DS_030.D = (BGACK_030.Q
# AS_000.PIN
- # RW & AS_030.Q
+ # AS_030.Q & RW_000.PIN
# UDS_000.PIN & LDS_000.PIN
# !CLK_030 & AS_030.Q & inst_CLK_030_H.Q
- # CLK_030 & !RW & DS_030.Q
- # !RW & !inst_CLK_030_H.Q & DS_030.Q);
+ # CLK_030 & DS_030.Q & !RW_000.PIN
+ # !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
DS_030.AP = (!RST);
@@ -287,12 +289,12 @@ DS_030.C = (CLK_OSZI);
UDS_000.OE = (BGACK_030.Q);
!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN
- # !RW & !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN
- # RW & !inst_CLK_000_D4.Q & !UDS_000.Q & !AS_030.PIN
- # RW & !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN
- # !RW & !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN);
+ # !inst_CLK_000_D2.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
+ # !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
+ # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN
+ # !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN);
UDS_000.AP = (!RST);
@@ -301,16 +303,16 @@ UDS_000.C = (CLK_OSZI);
LDS_000.OE = (BGACK_030.Q);
!LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN
- # !RW & !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN
- # RW & !inst_CLK_000_D4.Q & !LDS_000.Q & !AS_030.PIN
- # RW & !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN
- # !RW & !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN);
+ # !inst_CLK_000_D2.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
+ # !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
+ # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN
+ # !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN & !RW.PIN);
LDS_000.AP = (!RST);
@@ -351,6 +353,15 @@ FPU_CS.AP = (!RST);
FPU_CS.C = (CLK_OSZI);
+DSACK1.OE = (nEXP_SPACE);
+
+!DSACK1.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # !DSACK1.Q & !AS_030.PIN);
+
+DSACK1.AP = (!RST);
+
+DSACK1.C = (CLK_OSZI);
+
E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);
@@ -376,17 +387,6 @@ RESET.D = (1);
RESET.C = (CLK_OSZI);
-!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q
- # nEXP_SPACE & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D4.Q & SM_AMIGA_6_.Q
- # !nEXP_SPACE & inst_BGACK_030_INT_D.Q & !AMIGA_BUS_ENABLE.Q & !AS_030.PIN
- # inst_BGACK_030_INT_D.Q & !SM_AMIGA_6_.Q & !AMIGA_BUS_ENABLE.Q & !AS_030.PIN
- # !nEXP_SPACE & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !AMIGA_BUS_ENABLE.Q
- # inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !AMIGA_BUS_ENABLE.Q);
-
-AMIGA_BUS_ENABLE.AP = (!RST);
-
-AMIGA_BUS_ENABLE.C = (CLK_OSZI);
-
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
@@ -399,9 +399,9 @@ inst_AS_030_000_SYNC.D = (AS_030.PIN
# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
# !CLK_030 & inst_AS_030_000_SYNC.Q
# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
- # !nEXP_SPACE & SM_AMIGA_6_.Q
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
- # !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q & inst_CLK_000_D3.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # !nEXP_SPACE & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q
# FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
inst_AS_030_000_SYNC.AP = (!RST);
@@ -444,12 +444,6 @@ inst_CLK_000_D2.AP = (!RST);
inst_CLK_000_D2.C = (CLK_OSZI);
-inst_CLK_000_D4.D = (inst_CLK_000_D3.Q);
-
-inst_CLK_000_D4.AP = (!RST);
-
-inst_CLK_000_D4.C = (CLK_OSZI);
-
inst_DTACK_D0.D = (DTACK.PIN);
inst_DTACK_D0.AP = (!RST);
@@ -470,30 +464,29 @@ inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
-SM_AMIGA_1_.AR = (!RST);
+!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q
+ # !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D3.Q);
-SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q
- # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
- # !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q & inst_CLK_000_D3.Q);
+SM_AMIGA_7_.AP = (!RST);
-SM_AMIGA_1_.C = (CLK_OSZI);
+SM_AMIGA_7_.C = (CLK_OSZI);
+
+SM_AMIGA_6_.AR = (!RST);
+
+SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
+
+SM_AMIGA_6_.C = (CLK_OSZI);
SM_AMIGA_0_.AR = (!RST);
SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
- # !AS_000.Q & SM_AMIGA_0_.Q
- # !inst_CLK_000_D0.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q
- # !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q & !inst_CLK_000_D3.Q);
+ # !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
SM_AMIGA_0_.C = (CLK_OSZI);
-SM_AMIGA_6_.AR = (!RST);
-
-SM_AMIGA_6_.D = (!inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q & SM_AMIGA_7_.Q
- # nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q);
-
-SM_AMIGA_6_.C = (CLK_OSZI);
-
SM_AMIGA_5_.AR = (!RST);
SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
@@ -501,6 +494,33 @@ SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
SM_AMIGA_5_.C = (CLK_OSZI);
+SM_AMIGA_2_.AR = (!RST);
+
+SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q
+ # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
+
+SM_AMIGA_2_.C = (CLK_OSZI);
+
+!inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
+ # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
+ # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN
+ # CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
+ # BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
+ # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN
+ # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
+ # CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
+ # BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN
+ # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
+ # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
+ # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN);
+
+inst_RW_000_INT.AP = (!RST);
+
+inst_RW_000_INT.C = (CLK_OSZI);
+
inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);
inst_CLK_000_D3.AP = (!RST);
@@ -515,16 +535,6 @@ inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
inst_CLK_030_H.C = (CLK_OSZI);
-SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q
- # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q
- # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q
- # inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q
- # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q);
-
-SM_AMIGA_7_.AP = (!RST);
-
-SM_AMIGA_7_.C = (CLK_OSZI);
-
SM_AMIGA_4_.AR = (!RST);
SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
@@ -541,13 +551,12 @@ SM_AMIGA_3_.AR = (!RST);
SM_AMIGA_3_.C = (CLK_OSZI);
-SM_AMIGA_2_.AR = (!RST);
+SM_AMIGA_1_.AR = (!RST);
-SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
- # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q
- # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
+SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
-SM_AMIGA_2_.C = (CLK_OSZI);
+SM_AMIGA_1_.C = (CLK_OSZI);
cpu_est_0_.AR = (!RST);
diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti
index 55610c5..0b0c368 100644
--- a/Logic/68030_tk.fti
+++ b/Logic/68030_tk.fti
@@ -1,16 +1,16 @@
#PLAFILE 68030_tk.tt4
-#DATE 05/25/2014
+#DATE 06/01/2014
#DESIGN
#DEVICE mach447a
DATA LOCATION A0:G_8_69 // IO
DATA LOCATION AMIGA_BUS_DATA_DIR:E_0_48 // OUT
-DATA LOCATION AMIGA_BUS_ENABLE:D_7_34 // IO {RN_AMIGA_BUS_ENABLE}
+DATA LOCATION AMIGA_BUS_ENABLE:D_3_34 // OUT
DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT
-DATA LOCATION AS_000:D_5_33 // IO {RN_AS_000}
+DATA LOCATION AS_000:D_4_33 // IO {RN_AS_000}
DATA LOCATION AS_030:H_6_82 // IO {RN_AS_030}
DATA LOCATION AVEC:A_2_92 // OUT
-DATA LOCATION AVEC_EXP:C_0_22 // OUT
+DATA LOCATION AVEC_EXP:C_0_22 // IO {RN_AVEC_EXP}
DATA LOCATION A_16_:A_*_96 // INP
DATA LOCATION A_17_:F_*_59 // INP
DATA LOCATION A_18_:A_*_95 // INP
@@ -29,77 +29,77 @@ DATA LOCATION A_30_:B_*_5 // INP
DATA LOCATION A_31_:B_*_4 // INP
DATA LOCATION BERR:E_2_41 // OUT
DATA LOCATION BGACK_000:D_*_28 // INP
-DATA LOCATION BGACK_030:H_5_83 // IO {RN_BGACK_030}
-DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
+DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
+DATA LOCATION BG_000:D_2_29 // IO {RN_BG_000}
DATA LOCATION BG_030:C_*_21 // INP
DATA LOCATION CIIN:E_1_47 // OUT
DATA LOCATION CLK_000:*_*_11 // INP
DATA LOCATION CLK_030:*_*_64 // INP
-DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT
+DATA LOCATION CLK_DIV_OUT:G_3_65 // OUT
DATA LOCATION CLK_EXP:B_0_10 // OUT
DATA LOCATION CLK_OSZI:*_*_61 // Cin
-DATA LOCATION DSACK_0_:H_10_80 // OUT
-DATA LOCATION DSACK_1_:H_11_81 // IO {RN_DSACK_1_}
-DATA LOCATION DS_030:A_5_98 // IO {RN_DS_030}
+DATA LOCATION DSACK1:H_8_81 // IO {RN_DSACK1}
+DATA LOCATION DS_030:A_0_98 // IO {RN_DS_030}
DATA LOCATION DTACK:D_0_30 // IO
DATA LOCATION E:G_2_66 // IO {RN_E}
DATA LOCATION FC_0_:F_*_57 // INP
DATA LOCATION FC_1_:F_*_58 // INP
-DATA LOCATION FPU_CS:H_1_78 // IO {RN_FPU_CS}
+DATA LOCATION FPU_CS:H_2_78 // IO {RN_FPU_CS}
DATA LOCATION IPL_030_0_:B_4_8 // IO {RN_IPL_030_0_}
DATA LOCATION IPL_030_1_:B_6_7 // IO {RN_IPL_030_1_}
DATA LOCATION IPL_030_2_:B_2_9 // IO {RN_IPL_030_2_}
DATA LOCATION IPL_0_:G_*_67 // INP
DATA LOCATION IPL_1_:F_*_56 // INP
DATA LOCATION IPL_2_:G_*_68 // INP
-DATA LOCATION LDS_000:D_9_31 // IO {RN_LDS_000}
+DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000}
DATA LOCATION RESET:B_1_3 // OUT
-DATA LOCATION RN_AMIGA_BUS_ENABLE:D_7 // NOD {AMIGA_BUS_ENABLE}
-DATA LOCATION RN_AS_000:D_5 // NOD {AS_000}
+DATA LOCATION RN_AS_000:D_4 // NOD {AS_000}
DATA LOCATION RN_AS_030:H_6 // NOD {AS_030}
-DATA LOCATION RN_BGACK_030:H_5 // NOD {BGACK_030}
-DATA LOCATION RN_BG_000:D_1 // NOD {BG_000}
-DATA LOCATION RN_DSACK_1_:H_11 // NOD {DSACK_1_}
-DATA LOCATION RN_DS_030:A_5 // NOD {DS_030}
+DATA LOCATION RN_AVEC_EXP:C_0 // NOD {AVEC_EXP}
+DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030}
+DATA LOCATION RN_BG_000:D_2 // NOD {BG_000}
+DATA LOCATION RN_DSACK1:H_8 // NOD {DSACK1}
+DATA LOCATION RN_DS_030:A_0 // NOD {DS_030}
DATA LOCATION RN_E:G_2 // NOD {E}
-DATA LOCATION RN_FPU_CS:H_1 // NOD {FPU_CS}
+DATA LOCATION RN_FPU_CS:H_2 // NOD {FPU_CS}
DATA LOCATION RN_IPL_030_0_:B_4 // NOD {IPL_030_0_}
DATA LOCATION RN_IPL_030_1_:B_6 // NOD {IPL_030_1_}
DATA LOCATION RN_IPL_030_2_:B_2 // NOD {IPL_030_2_}
-DATA LOCATION RN_LDS_000:D_9 // NOD {LDS_000}
+DATA LOCATION RN_LDS_000:D_8 // NOD {LDS_000}
DATA LOCATION RN_UDS_000:D_6 // NOD {UDS_000}
-DATA LOCATION RN_VMA:D_3 // NOD {VMA}
+DATA LOCATION RN_VMA:D_1 // NOD {VMA}
DATA LOCATION RST:*_*_86 // INP
-DATA LOCATION RW:G_*_71 // INP
-DATA LOCATION SIZE_0_:G_14_70 // IO
+DATA LOCATION RW:G_0_71 // IO
+DATA LOCATION RW_000:H_1_80 // IO
+DATA LOCATION SIZE_0_:G_1_70 // IO
DATA LOCATION SIZE_1_:H_0_79 // IO
-DATA LOCATION SM_AMIGA_0_:B_5 // NOD
-DATA LOCATION SM_AMIGA_1_:B_10 // NOD
-DATA LOCATION SM_AMIGA_2_:G_6 // NOD
-DATA LOCATION SM_AMIGA_3_:G_7 // NOD
-DATA LOCATION SM_AMIGA_4_:B_7 // NOD
-DATA LOCATION SM_AMIGA_5_:D_2 // NOD
-DATA LOCATION SM_AMIGA_6_:H_7 // NOD
-DATA LOCATION SM_AMIGA_7_:A_11 // NOD
+DATA LOCATION SM_AMIGA_0_:A_1 // NOD
+DATA LOCATION SM_AMIGA_1_:H_7 // NOD
+DATA LOCATION SM_AMIGA_2_:G_5 // NOD
+DATA LOCATION SM_AMIGA_3_:G_6 // NOD
+DATA LOCATION SM_AMIGA_4_:D_9 // NOD
+DATA LOCATION SM_AMIGA_5_:B_8 // NOD
+DATA LOCATION SM_AMIGA_6_:B_9 // NOD
+DATA LOCATION SM_AMIGA_7_:B_5 // NOD
DATA LOCATION UDS_000:D_6_32 // IO {RN_UDS_000}
-DATA LOCATION VMA:D_3_35 // IO {RN_VMA}
+DATA LOCATION VMA:D_1_35 // IO {RN_VMA}
DATA LOCATION VPA:*_*_36 // INP
-DATA LOCATION cpu_est_0_:B_8 // NOD
-DATA LOCATION cpu_est_1_:G_4 // NOD
-DATA LOCATION cpu_est_2_:G_5 // NOD
-DATA LOCATION inst_AS_030_000_SYNC:H_9 // NOD
+DATA LOCATION cpu_est_0_:C_2 // NOD
+DATA LOCATION cpu_est_1_:B_3 // NOD
+DATA LOCATION cpu_est_2_:G_4 // NOD
+DATA LOCATION inst_AS_030_000_SYNC:C_3 // NOD
DATA LOCATION inst_BGACK_030_INT_D:D_10 // NOD
-DATA LOCATION inst_CLK_000_D0:D_12 // NOD
-DATA LOCATION inst_CLK_000_D1:H_3 // NOD
-DATA LOCATION inst_CLK_000_D2:H_12 // NOD
-DATA LOCATION inst_CLK_000_D3:H_2 // NOD
-DATA LOCATION inst_CLK_000_D4:H_8 // NOD
-DATA LOCATION inst_CLK_030_H:A_0 // NOD
-DATA LOCATION inst_CLK_OUT_PRE_25:B_9 // NOD
-DATA LOCATION inst_CLK_OUT_PRE_50:G_1 // NOD
-DATA LOCATION inst_CLK_OUT_PRE_50_D:A_3 // NOD
-DATA LOCATION inst_DTACK_D0:A_1 // NOD
-DATA LOCATION inst_VPA_D:H_14 // NOD
+DATA LOCATION inst_CLK_000_D0:D_5 // NOD
+DATA LOCATION inst_CLK_000_D1:D_7 // NOD
+DATA LOCATION inst_CLK_000_D2:H_3 // NOD
+DATA LOCATION inst_CLK_000_D3:C_4 // NOD
+DATA LOCATION inst_CLK_030_H:H_5 // NOD
+DATA LOCATION inst_CLK_OUT_PRE_25:B_7 // NOD
+DATA LOCATION inst_CLK_OUT_PRE_50:H_9 // NOD
+DATA LOCATION inst_CLK_OUT_PRE_50_D:H_12 // NOD
+DATA LOCATION inst_DTACK_D0:H_11 // NOD
+DATA LOCATION inst_RW_000_INT:A_3 // NOD
+DATA LOCATION inst_VPA_D:H_10 // NOD
DATA LOCATION nEXP_SPACE:*_*_14 // INP
DATA IO_DIR A0:BI
DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT
@@ -136,8 +136,7 @@ DATA IO_DIR CLK_030:IN
DATA IO_DIR CLK_DIV_OUT:OUT
DATA IO_DIR CLK_EXP:OUT
DATA IO_DIR CLK_OSZI:IN
-DATA IO_DIR DSACK_0_:OUT
-DATA IO_DIR DSACK_1_:BI
+DATA IO_DIR DSACK1:BI
DATA IO_DIR DS_030:BI
DATA IO_DIR DTACK:BI
DATA IO_DIR E:OUT
@@ -153,7 +152,8 @@ DATA IO_DIR IPL_2_:IN
DATA IO_DIR LDS_000:BI
DATA IO_DIR RESET:OUT
DATA IO_DIR RST:IN
-DATA IO_DIR RW:IN
+DATA IO_DIR RW:BI
+DATA IO_DIR RW_000:BI
DATA IO_DIR SIZE_0_:BI
DATA IO_DIR SIZE_1_:BI
DATA IO_DIR UDS_000:BI
@@ -161,179 +161,179 @@ DATA IO_DIR VMA:OUT
DATA IO_DIR VPA:IN
DATA IO_DIR nEXP_SPACE:IN
DATA GLB_CLOCK CLK_OSZI
-DATA PW_LEVEL A_21_:1
-DATA SLEW A_21_:1
-DATA PW_LEVEL A_20_:1
-DATA SLEW A_20_:1
-DATA PW_LEVEL A_19_:1
-DATA SLEW A_19_:1
-DATA PW_LEVEL A_18_:1
-DATA SLEW A_18_:1
-DATA PW_LEVEL A_31_:1
+DATA PW_LEVEL A_26_:0
+DATA SLEW A_26_:1
+DATA PW_LEVEL A_25_:0
+DATA SLEW A_25_:1
+DATA PW_LEVEL A_24_:0
+DATA SLEW A_24_:1
+DATA PW_LEVEL A_23_:0
+DATA SLEW A_23_:1
+DATA PW_LEVEL A_31_:0
DATA SLEW A_31_:1
-DATA PW_LEVEL A_17_:1
-DATA SLEW A_17_:1
-DATA PW_LEVEL A_16_:1
-DATA SLEW A_16_:1
-DATA PW_LEVEL IPL_2_:1
+DATA PW_LEVEL A_22_:0
+DATA SLEW A_22_:1
+DATA PW_LEVEL A_21_:0
+DATA SLEW A_21_:1
+DATA PW_LEVEL A_20_:0
+DATA SLEW A_20_:1
+DATA PW_LEVEL A_19_:0
+DATA SLEW A_19_:1
+DATA PW_LEVEL IPL_2_:0
DATA SLEW IPL_2_:1
-DATA PW_LEVEL IPL_1_:1
-DATA SLEW IPL_1_:1
-DATA PW_LEVEL IPL_0_:1
-DATA SLEW IPL_0_:1
-DATA PW_LEVEL DSACK_0_:1
-DATA SLEW DSACK_0_:1
-DATA PW_LEVEL FC_0_:1
-DATA SLEW FC_0_:1
-DATA PW_LEVEL FC_1_:1
+DATA PW_LEVEL A_18_:0
+DATA SLEW A_18_:1
+DATA PW_LEVEL A_17_:0
+DATA SLEW A_17_:1
+DATA PW_LEVEL FC_1_:0
DATA SLEW FC_1_:1
+DATA PW_LEVEL A_16_:0
+DATA SLEW A_16_:1
+DATA PW_LEVEL RW_000:0
+DATA SLEW RW_000:1
+DATA PW_LEVEL IPL_1_:0
+DATA SLEW IPL_1_:1
+DATA PW_LEVEL IPL_0_:0
+DATA SLEW IPL_0_:1
+DATA PW_LEVEL FC_0_:0
+DATA SLEW FC_0_:1
DATA SLEW nEXP_SPACE:1
-DATA PW_LEVEL BERR:1
+DATA PW_LEVEL BERR:0
DATA SLEW BERR:1
-DATA PW_LEVEL BG_030:1
+DATA PW_LEVEL BG_030:0
DATA SLEW BG_030:1
-DATA PW_LEVEL BGACK_000:1
+DATA PW_LEVEL BGACK_000:0
DATA SLEW BGACK_000:1
DATA SLEW CLK_030:1
DATA SLEW CLK_000:1
DATA SLEW CLK_OSZI:1
-DATA PW_LEVEL CLK_DIV_OUT:1
+DATA PW_LEVEL CLK_DIV_OUT:0
DATA SLEW CLK_DIV_OUT:1
-DATA PW_LEVEL DTACK:1
+DATA PW_LEVEL DTACK:0
DATA SLEW DTACK:1
-DATA PW_LEVEL AVEC:1
+DATA PW_LEVEL AVEC:0
DATA SLEW AVEC:1
-DATA PW_LEVEL AVEC_EXP:1
+DATA PW_LEVEL AVEC_EXP:0
DATA SLEW AVEC_EXP:1
DATA SLEW VPA:1
DATA SLEW RST:1
-DATA PW_LEVEL RW:1
+DATA PW_LEVEL RW:0
DATA SLEW RW:1
-DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
-DATA SLEW AMIGA_BUS_DATA_DIR:1
-DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1
-DATA SLEW AMIGA_BUS_ENABLE_LOW:1
-DATA PW_LEVEL CIIN:1
-DATA SLEW CIIN:1
-DATA PW_LEVEL A_30_:1
-DATA SLEW A_30_:1
-DATA PW_LEVEL A_29_:1
-DATA SLEW A_29_:1
-DATA PW_LEVEL A_28_:1
-DATA SLEW A_28_:1
-DATA PW_LEVEL A_27_:1
-DATA SLEW A_27_:1
-DATA PW_LEVEL A_26_:1
-DATA SLEW A_26_:1
-DATA PW_LEVEL A_25_:1
-DATA SLEW A_25_:1
-DATA PW_LEVEL A_24_:1
-DATA SLEW A_24_:1
-DATA PW_LEVEL A_23_:1
-DATA SLEW A_23_:1
-DATA PW_LEVEL A_22_:1
-DATA SLEW A_22_:1
-DATA PW_LEVEL SIZE_1_:1
-DATA SLEW SIZE_1_:1
-DATA PW_LEVEL IPL_030_2_:1
-DATA SLEW IPL_030_2_:1
-DATA PW_LEVEL IPL_030_1_:1
-DATA SLEW IPL_030_1_:1
-DATA PW_LEVEL IPL_030_0_:1
-DATA SLEW IPL_030_0_:1
-DATA PW_LEVEL DSACK_1_:1
-DATA SLEW DSACK_1_:1
-DATA PW_LEVEL AS_030:1
-DATA SLEW AS_030:1
-DATA PW_LEVEL AS_000:1
-DATA SLEW AS_000:1
-DATA PW_LEVEL DS_030:1
-DATA SLEW DS_030:1
-DATA PW_LEVEL UDS_000:1
-DATA SLEW UDS_000:1
-DATA PW_LEVEL LDS_000:1
-DATA SLEW LDS_000:1
-DATA PW_LEVEL A0:1
-DATA SLEW A0:1
-DATA PW_LEVEL BG_000:1
-DATA SLEW BG_000:1
-DATA PW_LEVEL BGACK_030:1
-DATA SLEW BGACK_030:1
-DATA PW_LEVEL CLK_EXP:1
-DATA SLEW CLK_EXP:1
-DATA PW_LEVEL FPU_CS:1
-DATA SLEW FPU_CS:1
-DATA PW_LEVEL E:1
-DATA SLEW E:1
-DATA PW_LEVEL VMA:1
-DATA SLEW VMA:1
-DATA PW_LEVEL RESET:1
-DATA SLEW RESET:1
-DATA PW_LEVEL AMIGA_BUS_ENABLE:1
+DATA PW_LEVEL AMIGA_BUS_ENABLE:0
DATA SLEW AMIGA_BUS_ENABLE:1
-DATA PW_LEVEL SIZE_0_:1
+DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0
+DATA SLEW AMIGA_BUS_DATA_DIR:1
+DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0
+DATA SLEW AMIGA_BUS_ENABLE_LOW:1
+DATA PW_LEVEL CIIN:0
+DATA SLEW CIIN:1
+DATA PW_LEVEL A_30_:0
+DATA SLEW A_30_:1
+DATA PW_LEVEL A_29_:0
+DATA SLEW A_29_:1
+DATA PW_LEVEL A_28_:0
+DATA SLEW A_28_:1
+DATA PW_LEVEL A_27_:0
+DATA SLEW A_27_:1
+DATA PW_LEVEL SIZE_1_:0
+DATA SLEW SIZE_1_:1
+DATA PW_LEVEL IPL_030_2_:0
+DATA SLEW IPL_030_2_:1
+DATA PW_LEVEL AS_030:0
+DATA SLEW AS_030:1
+DATA PW_LEVEL IPL_030_1_:0
+DATA SLEW IPL_030_1_:1
+DATA PW_LEVEL AS_000:0
+DATA SLEW AS_000:1
+DATA PW_LEVEL IPL_030_0_:0
+DATA SLEW IPL_030_0_:1
+DATA PW_LEVEL DS_030:0
+DATA SLEW DS_030:1
+DATA PW_LEVEL UDS_000:0
+DATA SLEW UDS_000:1
+DATA PW_LEVEL LDS_000:0
+DATA SLEW LDS_000:1
+DATA PW_LEVEL A0:0
+DATA SLEW A0:1
+DATA PW_LEVEL BG_000:0
+DATA SLEW BG_000:1
+DATA PW_LEVEL BGACK_030:0
+DATA SLEW BGACK_030:1
+DATA PW_LEVEL CLK_EXP:0
+DATA SLEW CLK_EXP:1
+DATA PW_LEVEL FPU_CS:0
+DATA SLEW FPU_CS:1
+DATA PW_LEVEL DSACK1:0
+DATA SLEW DSACK1:1
+DATA PW_LEVEL E:0
+DATA SLEW E:1
+DATA PW_LEVEL VMA:0
+DATA SLEW VMA:1
+DATA PW_LEVEL RESET:0
+DATA SLEW RESET:1
+DATA PW_LEVEL SIZE_0_:0
DATA SLEW SIZE_0_:1
-DATA PW_LEVEL inst_AS_030_000_SYNC:1
+DATA PW_LEVEL inst_AS_030_000_SYNC:0
DATA SLEW inst_AS_030_000_SYNC:1
-DATA PW_LEVEL inst_BGACK_030_INT_D:1
+DATA PW_LEVEL inst_BGACK_030_INT_D:0
DATA SLEW inst_BGACK_030_INT_D:1
-DATA PW_LEVEL inst_VPA_D:1
+DATA PW_LEVEL inst_VPA_D:0
DATA SLEW inst_VPA_D:1
-DATA PW_LEVEL inst_CLK_OUT_PRE_50_D:1
+DATA PW_LEVEL inst_CLK_OUT_PRE_50_D:0
DATA SLEW inst_CLK_OUT_PRE_50_D:1
-DATA PW_LEVEL inst_CLK_000_D0:1
+DATA PW_LEVEL inst_CLK_000_D0:0
DATA SLEW inst_CLK_000_D0:1
-DATA PW_LEVEL inst_CLK_000_D1:1
+DATA PW_LEVEL inst_CLK_000_D1:0
DATA SLEW inst_CLK_000_D1:1
-DATA PW_LEVEL inst_CLK_000_D2:1
+DATA PW_LEVEL inst_CLK_000_D2:0
DATA SLEW inst_CLK_000_D2:1
-DATA PW_LEVEL inst_CLK_000_D4:1
-DATA SLEW inst_CLK_000_D4:1
-DATA PW_LEVEL inst_DTACK_D0:1
+DATA PW_LEVEL inst_DTACK_D0:0
DATA SLEW inst_DTACK_D0:1
-DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
+DATA PW_LEVEL inst_CLK_OUT_PRE_50:0
DATA SLEW inst_CLK_OUT_PRE_50:1
-DATA PW_LEVEL inst_CLK_OUT_PRE_25:1
+DATA PW_LEVEL inst_CLK_OUT_PRE_25:0
DATA SLEW inst_CLK_OUT_PRE_25:1
-DATA PW_LEVEL SM_AMIGA_1_:1
-DATA SLEW SM_AMIGA_1_:1
-DATA PW_LEVEL SM_AMIGA_0_:1
-DATA SLEW SM_AMIGA_0_:1
-DATA PW_LEVEL SM_AMIGA_6_:1
-DATA SLEW SM_AMIGA_6_:1
-DATA PW_LEVEL SM_AMIGA_5_:1
-DATA SLEW SM_AMIGA_5_:1
-DATA PW_LEVEL inst_CLK_000_D3:1
-DATA SLEW inst_CLK_000_D3:1
-DATA PW_LEVEL inst_CLK_030_H:1
-DATA SLEW inst_CLK_030_H:1
-DATA PW_LEVEL SM_AMIGA_7_:1
+DATA PW_LEVEL SM_AMIGA_7_:0
DATA SLEW SM_AMIGA_7_:1
-DATA PW_LEVEL SM_AMIGA_4_:1
-DATA SLEW SM_AMIGA_4_:1
-DATA PW_LEVEL SM_AMIGA_3_:1
-DATA SLEW SM_AMIGA_3_:1
-DATA PW_LEVEL SM_AMIGA_2_:1
+DATA PW_LEVEL SM_AMIGA_6_:0
+DATA SLEW SM_AMIGA_6_:1
+DATA PW_LEVEL SM_AMIGA_0_:0
+DATA SLEW SM_AMIGA_0_:1
+DATA PW_LEVEL SM_AMIGA_5_:0
+DATA SLEW SM_AMIGA_5_:1
+DATA PW_LEVEL SM_AMIGA_2_:0
DATA SLEW SM_AMIGA_2_:1
-DATA PW_LEVEL cpu_est_0_:1
+DATA PW_LEVEL inst_RW_000_INT:0
+DATA SLEW inst_RW_000_INT:1
+DATA PW_LEVEL inst_CLK_000_D3:0
+DATA SLEW inst_CLK_000_D3:1
+DATA PW_LEVEL inst_CLK_030_H:0
+DATA SLEW inst_CLK_030_H:1
+DATA PW_LEVEL SM_AMIGA_4_:0
+DATA SLEW SM_AMIGA_4_:1
+DATA PW_LEVEL SM_AMIGA_3_:0
+DATA SLEW SM_AMIGA_3_:1
+DATA PW_LEVEL SM_AMIGA_1_:0
+DATA SLEW SM_AMIGA_1_:1
+DATA PW_LEVEL cpu_est_0_:0
DATA SLEW cpu_est_0_:1
-DATA PW_LEVEL cpu_est_1_:1
+DATA PW_LEVEL cpu_est_1_:0
DATA SLEW cpu_est_1_:1
-DATA PW_LEVEL cpu_est_2_:1
+DATA PW_LEVEL cpu_est_2_:0
DATA SLEW cpu_est_2_:1
-DATA PW_LEVEL RN_IPL_030_2_:1
-DATA PW_LEVEL RN_IPL_030_1_:1
-DATA PW_LEVEL RN_IPL_030_0_:1
-DATA PW_LEVEL RN_DSACK_1_:1
-DATA PW_LEVEL RN_AS_030:1
-DATA PW_LEVEL RN_AS_000:1
-DATA PW_LEVEL RN_DS_030:1
-DATA PW_LEVEL RN_UDS_000:1
-DATA PW_LEVEL RN_LDS_000:1
-DATA PW_LEVEL RN_BG_000:1
-DATA PW_LEVEL RN_BGACK_030:1
-DATA PW_LEVEL RN_FPU_CS:1
-DATA PW_LEVEL RN_E:1
-DATA PW_LEVEL RN_VMA:1
-DATA PW_LEVEL RN_AMIGA_BUS_ENABLE:1
+DATA PW_LEVEL RN_IPL_030_2_:0
+DATA PW_LEVEL RN_AS_030:0
+DATA PW_LEVEL RN_IPL_030_1_:0
+DATA PW_LEVEL RN_AS_000:0
+DATA PW_LEVEL RN_IPL_030_0_:0
+DATA PW_LEVEL RN_DS_030:0
+DATA PW_LEVEL RN_UDS_000:0
+DATA PW_LEVEL RN_LDS_000:0
+DATA PW_LEVEL RN_BG_000:0
+DATA PW_LEVEL RN_BGACK_030:0
+DATA PW_LEVEL RN_FPU_CS:0
+DATA PW_LEVEL RN_DSACK1:0
+DATA PW_LEVEL RN_E:0
+DATA PW_LEVEL RN_VMA:0
+DATA PW_LEVEL RN_AVEC_EXP:0
END
diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp
index 91c939d..8af8540 100644
--- a/Logic/68030_tk.grp
+++ b/Logic/68030_tk.grp
@@ -1,17 +1,16 @@
-GROUP MACH_SEG_A DS_030 RN_DS_030 SM_AMIGA_7_ inst_DTACK_D0 inst_CLK_OUT_PRE_50_D
- AVEC inst_CLK_030_H
+GROUP MACH_SEG_A DS_030 RN_DS_030 inst_RW_000_INT SM_AMIGA_0_ AVEC
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
- RN_IPL_030_2_ CLK_EXP RESET SM_AMIGA_0_ SM_AMIGA_1_ inst_CLK_OUT_PRE_25
- SM_AMIGA_4_ cpu_est_0_
-GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW
-GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 AMIGA_BUS_ENABLE
- RN_AMIGA_BUS_ENABLE VMA RN_VMA BG_000 RN_BG_000 AS_000 RN_AS_000
- SM_AMIGA_5_ inst_CLK_000_D0 inst_BGACK_030_INT_D DTACK
+ RN_IPL_030_2_ CLK_EXP RESET SM_AMIGA_7_ SM_AMIGA_6_ cpu_est_1_ inst_CLK_OUT_PRE_25
+ SM_AMIGA_5_
+GROUP MACH_SEG_C AVEC_EXP RN_AVEC_EXP inst_AS_030_000_SYNC cpu_est_0_ inst_CLK_000_D3
+ AMIGA_BUS_ENABLE_LOW
+GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000
+ RN_BG_000 AS_000 RN_AS_000 SM_AMIGA_4_ inst_CLK_000_D0 inst_BGACK_030_INT_D
+ inst_CLK_000_D1 DTACK AMIGA_BUS_ENABLE
GROUP MACH_SEG_E CIIN AMIGA_BUS_DATA_DIR BERR
GROUP MACH_SEG_G E RN_E A0 SIZE_0_ CLK_DIV_OUT SM_AMIGA_2_ SM_AMIGA_3_
- cpu_est_1_ cpu_est_2_ inst_CLK_OUT_PRE_50
-GROUP MACH_SEG_H FPU_CS RN_FPU_CS AS_030 RN_AS_030 DSACK_1_ RN_DSACK_1_
- SIZE_1_ BGACK_030 RN_BGACK_030 inst_AS_030_000_SYNC SM_AMIGA_6_ inst_VPA_D
- inst_CLK_000_D3 inst_CLK_000_D4 inst_CLK_000_D2 inst_CLK_000_D1 DSACK_0_
-
\ No newline at end of file
+ cpu_est_2_ RW
+GROUP MACH_SEG_H FPU_CS RN_FPU_CS AS_030 RN_AS_030 SIZE_1_ DSACK1 RN_DSACK1
+ BGACK_030 RN_BGACK_030 SM_AMIGA_1_ inst_VPA_D inst_DTACK_D0 inst_CLK_OUT_PRE_50_D
+ inst_CLK_OUT_PRE_50 inst_CLK_000_D2 RW_000 inst_CLK_030_H
\ No newline at end of file
diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr
index e79fc9e..361b712 100644
--- a/Logic/68030_tk.ipr
+++ b/Logic/68030_tk.ipr
@@ -1 +1 @@
-77:0=67 (zS'4<
\ No newline at end of file
+4164307ðsl5{jgj
\ No newline at end of file
diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed
index 77b7556..dfc04e9 100644
--- a/Logic/68030_tk.jed
+++ b/Logic/68030_tk.jed
@@ -10,7 +10,7 @@ AUTHOR:
PATTERN:
COMPANY:
REVISION:
-DATE: Thu May 29 22:04:32 2014
+DATE: Sun Jun 01 01:03:29 2014
ABEL mach447a
*
@@ -31,80 +31,81 @@ NOTE Spread Placement? N *
NOTE Run Time Upper Bound in 15 minutes 0 *
NOTE Zero Hold Time For Input Registers? Y *
NOTE Table of pin names and numbers*
-NOTE PINS A_21_:94 A_20_:93 A_19_:97 A_18_:95 A_31_:4 A_17_:59*
-NOTE PINS A_16_:96 IPL_2_:68 IPL_1_:56 IPL_0_:67 DSACK_0_:80*
-NOTE PINS FC_0_:57 FC_1_:58 nEXP_SPACE:14 BERR:41 BG_030:21*
-NOTE PINS BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61*
-NOTE PINS CLK_DIV_OUT:65 DTACK:30 AVEC:92 AVEC_EXP:22 VPA:36*
-NOTE PINS RST:86 RW:71 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20*
-NOTE PINS CIIN:47 A_30_:5 A_29_:6 A_28_:15 A_27_:16 A_26_:17*
-NOTE PINS A_25_:18 A_24_:19 A_23_:84 A_22_:85 SIZE_1_:79*
-NOTE PINS IPL_030_2_:9 IPL_030_1_:7 IPL_030_0_:8 DSACK_1_:81*
-NOTE PINS AS_030:82 AS_000:33 DS_030:98 UDS_000:32 LDS_000:31*
-NOTE PINS A0:69 BG_000:29 BGACK_030:83 CLK_EXP:10 FPU_CS:78*
-NOTE PINS E:66 VMA:35 RESET:3 AMIGA_BUS_ENABLE:34 SIZE_0_:70*
+NOTE PINS A_26_:17 A_25_:18 A_24_:19 A_23_:84 A_31_:4 A_22_:85*
+NOTE PINS A_21_:94 A_20_:93 A_19_:97 IPL_2_:68 A_18_:95 A_17_:59*
+NOTE PINS FC_1_:58 A_16_:96 RW_000:80 IPL_1_:56 IPL_0_:67*
+NOTE PINS FC_0_:57 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28*
+NOTE PINS CLK_030:64 CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65*
+NOTE PINS DTACK:30 AVEC:92 AVEC_EXP:22 VPA:36 RST:86 RW:71*
+NOTE PINS AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20*
+NOTE PINS CIIN:47 A_30_:5 A_29_:6 A_28_:15 A_27_:16 SIZE_1_:79*
+NOTE PINS IPL_030_2_:9 AS_030:82 IPL_030_1_:7 AS_000:33 IPL_030_0_:8*
+NOTE PINS DS_030:98 UDS_000:32 LDS_000:31 A0:69 BG_000:29*
+NOTE PINS BGACK_030:83 CLK_EXP:10 FPU_CS:78 DSACK1:81 E:66*
+NOTE PINS VMA:35 RESET:3 SIZE_0_:70 *
NOTE Table of node names and numbers*
-NOTE NODES RN_DTACK:173 RN_SIZE_1_:269 RN_IPL_030_2_:128 *
-NOTE NODES RN_IPL_030_1_:134 RN_IPL_030_0_:131 RN_DSACK_1_:286 *
-NOTE NODES RN_AS_030:278 RN_AS_000:181 RN_DS_030:109 RN_UDS_000:182 *
-NOTE NODES RN_LDS_000:187 RN_A0:257 RN_BG_000:175 RN_BGACK_030:277 *
-NOTE NODES RN_FPU_CS:271 RN_E:248 RN_VMA:178 RN_AMIGA_BUS_ENABLE:184 *
-NOTE NODES RN_SIZE_0_:266 inst_AS_030_000_SYNC:283 inst_BGACK_030_INT_D:188 *
-NOTE NODES inst_VPA_D:290 inst_CLK_OUT_PRE_50_D:106 inst_CLK_000_D0:191 *
-NOTE NODES inst_CLK_000_D1:274 inst_CLK_000_D2:287 inst_CLK_000_D4:281 *
-NOTE NODES inst_DTACK_D0:103 inst_CLK_OUT_PRE_50:247 inst_CLK_OUT_PRE_25:139 *
-NOTE NODES SM_AMIGA_1_:140 SM_AMIGA_0_:133 SM_AMIGA_6_:280 *
-NOTE NODES SM_AMIGA_5_:176 inst_CLK_000_D3:272 inst_CLK_030_H:101 *
-NOTE NODES SM_AMIGA_7_:118 SM_AMIGA_4_:136 SM_AMIGA_3_:256 *
-NOTE NODES SM_AMIGA_2_:254 cpu_est_0_:137 cpu_est_1_:251 *
-NOTE NODES cpu_est_2_:253 *
+NOTE NODES RN_RW_000:271 RN_DTACK:173 RN_AVEC_EXP:149 RN_RW:245 *
+NOTE NODES RN_SIZE_1_:269 RN_IPL_030_2_:128 RN_AS_030:278 *
+NOTE NODES RN_IPL_030_1_:134 RN_AS_000:179 RN_IPL_030_0_:131 *
+NOTE NODES RN_DS_030:101 RN_UDS_000:182 RN_LDS_000:185 RN_A0:257 *
+NOTE NODES RN_BG_000:176 RN_BGACK_030:275 RN_FPU_CS:272 *
+NOTE NODES RN_DSACK1:281 RN_E:248 RN_VMA:175 RN_SIZE_0_:247 *
+NOTE NODES inst_AS_030_000_SYNC:154 inst_BGACK_030_INT_D:188 *
+NOTE NODES inst_VPA_D:284 inst_CLK_OUT_PRE_50_D:287 inst_CLK_000_D0:181 *
+NOTE NODES inst_CLK_000_D1:184 inst_CLK_000_D2:274 inst_DTACK_D0:286 *
+NOTE NODES inst_CLK_OUT_PRE_50:283 inst_CLK_OUT_PRE_25:136 *
+NOTE NODES SM_AMIGA_7_:133 SM_AMIGA_6_:139 SM_AMIGA_0_:103 *
+NOTE NODES SM_AMIGA_5_:137 SM_AMIGA_2_:253 inst_RW_000_INT:106 *
+NOTE NODES inst_CLK_000_D3:155 inst_CLK_030_H:277 SM_AMIGA_4_:187 *
+NOTE NODES SM_AMIGA_3_:254 SM_AMIGA_1_:280 cpu_est_0_:152 *
+NOTE NODES cpu_est_1_:130 cpu_est_2_:251 *
NOTE BLOCK 0 *
L000000
- 111111111111111111111111111111111111111110111111111111111111111111
- 111111111111111111111111111111011111111111111111111011111111111111
- 111111111111111111111111111111111111111111111111111111110111111111
+ 111111111011111111111111111111111111111111111111111111111111111111
+ 111111111101011110111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111101111111111111111
- 111111111111111110111111110111111101111111111111111111111111111111
- 011111111110111111011111111111111111111111111111111111111110111111
- 111101111111111011111101011111111111111111111101111111101111111111
- 111111110111111111111111111110111111111111101111111111111111111111*
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111111111011111111111111111111111111111111011111111011111111
+ 111111111111111111111101011011111111111110101101110111111111111111
+ 101111111111111111011111111111011111111111111111111111111111111111*
L000594
000000000000000000000000000000000000000000000000000000000000000000*
-L000660 111111110111111111111111111111111111111111101111111111111111111111*
-L000726 111111111111111011111111101111111111111101011110111111101111111111*
-L000792 111111110111111111111111101111111111111111111110111111101111111111*
-L000858 101111111111111011111111111111111111111101011110111111101111111111*
-L000924 101111110111111111111111111111111111111111111110111111101111111111*
-L000990 111111111111111111011111111111111111111111111111111111111111111111*
-L001056 000000000000000000000000000000000000000000000000000000000000000000*
+L000660 111111111111111111111111111111111111111101111111111111111111111111*
+L000726 111111111111111111111111111111111111111111111101111111111111111111*
+L000792 111111111111111111111111011111111111111111111111011111111111111111*
+L000858 111111111011111111111111110111111111111111011111111111111111111111*
+L000924 111111111111111111111111111111111111111111011111111111110111111111*
+L000990 111111111111111111011110111111111111111111111111111111111111111111*
+L001056 111111111111110111111110111111111111111111111111111111111111111111*
L001122 000000000000000000000000000000000000000000000000000000000000000000*
L001188 000000000000000000000000000000000000000000000000000000000000000000*
L001254 000000000000000000000000000000000000000000000000000000000000000000*
L001320
111111111111111111111111111111111111111111111111111111111111111111*
L001386 111111111111111111111111111111111111111111111111111111111111111111*
-L001452 000000000000000000000000000000000000000000000000000000000000000000*
-L001518 000000000000000000000000000000000000000000000000000000000000000000*
+L001452 111111110111111111111111111111011111111111111111111111111011111111*
+L001518 111111111111111111111111111011011111111111111111111111111011111111*
L001584 000000000000000000000000000000000000000000000000000000000000000000*
L001650 000000000000000000000000000000000000000000000000000000000000000000*
-L001716 111111111111111111111111111111111111111111111111011111111111111111*
-L001782 111111111111111111111111111111111111111111111111111111111111111111*
-L001848 111111111111111111111111111111111111111111111111111111111111111111*
-L001914 111111111111111111111111111111111111111111111111111111111111111111*
-L001980 111111111111111111111111111111111111111111111111111111111111111111*
+L001716 111111110111111111111110111111111111111111111111111011111111111111*
+L001782 111111111111111111111110111111111111111101111111111011111111111111*
+L001848 111111110111101111101111111111111111111111111111111011111111111111*
+L001914 111111111111101111101111111111111111111101111111111011111111111111*
+L001980 111111111111111111111110111111111111111111111101111011111111111111*
L002046
000000000000000000000000000000000000000000000000000000000000000000*
-L002112 111111111111111111111111111111111111111111111111111111111111111111*
-L002178 111111111111111111111111111111111111111111111111111111111111111111*
-L002244 111111111111111111111111111111111111111111111111111111111111111111*
-L002310 111111111111111111111111111111111111111111111111111111111111111111*
-L002376 111111111111111111111111111111111111111111111111111111111111111111*
-L002442 111111111111111111111111111111111111111111111111111111011111111111*
-L002508 111111111111111111111111111111111111111111111101111111111111111111*
-L002574 011111111111111111111111011111111111111111111111111111111111111111*
-L002640 111111111111110111111111111111111111111111111111110111111111111111*
-L002706 111111110111110111111111111111111111111110111111111111111111111111*
+L002112 111111111111101111101111111111111111111111111101111011111111111111*
+L002178 111111111011111111111111101111111111111110111110111111111011111111*
+L002244 111111111111111111111110011111111111111111111111011011111111111111*
+L002310 111111111111101111101111011111111111111111111111011011111111111111*
+L002376 111111111011111111111111111111111111111110111110101111111011111111*
+L002442 111111110111011110111101111111111111111111111111111111111111111111*
+L002508 111111111111011110111101111111111111111101111111111111111111111111*
+L002574 111111111111011110111101111111111111111111111101111111111111111111*
+L002640 111111111111011110111101011111111111111111111111011111111111111111*
+L002706 000000000000000000000000000000000000000000000000000000000000000000*
L002772
000000000000000000000000000000000000000000000000000000000000000000*
L002838 111111111111111111111111111111111111111111111111111111111111111111*
@@ -112,11 +113,11 @@ L002904 111111111111111111111111111111111111111111111111111111111111111111*
L002970 111111111111111111111111111111111111111111111111111111111111111111*
L003036 111111111111111111111111111111111111111111111111111111111111111111*
L003102 111111111111111111111111111111111111111111111111111111111111111111*
-L003168 111101111111111111111111111111111111111101111111111011111111111111*
-L003234 111101111011111111111111111111111111111111111111111011111111111111*
-L003300 000000000000000000000000000000000000000000000000000000000000000000*
-L003366 000000000000000000000000000000000000000000000000000000000000000000*
-L003432 000000000000000000000000000000000000000000000000000000000000000000*
+L003168 111111111111111111111111111111111111111111111111111111111111111111*
+L003234 111111111111111111111111111111111111111111111111111111111111111111*
+L003300 111111111111111111111111111111111111111111111111111111111111111111*
+L003366 111111111111111111111111111111111111111111111111111111111111111111*
+L003432 111111111111111111111111111111111111111111111111111111111111111111*
L003498
000000000000000000000000000000000000000000000000000000000000000000*
L003564 111111111111111111111111111111111111111111111111111111111111111111*
@@ -136,11 +137,11 @@ L004356 111111111111111111111111111111111111111111111111111111111111111111*
L004422 111111111111111111111111111111111111111111111111111111111111111111*
L004488 111111111111111111111111111111111111111111111111111111111111111111*
L004554 111111111111111111111111111111111111111111111111111111111111111111*
-L004620 111111111111111111111101111111111101111111111111111111110111111111*
-L004686 111111111111111111111111111111101110111111111111111111111101111111*
-L004752 111111111101111111111111110111111111111111111111111111111111111111*
-L004818 111111111111111101111111110111111111111111111111111111111111111111*
-L004884 111111111111111111111111110110111111111111111111111111111111111111*
+L004620 111111111111111111111111111111111111111111111111111111111111111111*
+L004686 111111111111111111111111111111111111111111111111111111111111111111*
+L004752 111111111111111111111111111111111111111111111111111111111111111111*
+L004818 111111111111111111111111111111111111111111111111111111111111111111*
+L004884 111111111111111111111111111111111111111111111111111111111111111111*
L004950
000000000000000000000000000000000000000000000000000000000000000000*
L005016 111111111111111111111111111111111111111111111111111111111111111111*
@@ -154,7 +155,7 @@ L005478 111111111111111111111111111111111111111111111111111111111111111111*
L005544 111111111111111111111111111111111111111111111111111111111111111111*
L005610 111111111111111111111111111111111111111111111111111111111111111111*
L005676
- 111111111111111011111111111111101111111111111111111111101111111111*
+ 111111111110111111111111111111111111111110101111111111111111111111*
L005742 111111111111111111111111111111111111111111111111111111111111111111*
L005808 111111111111111111111111111111111111111111111111111111111111111111*
L005874 111111111111111111111111111111111111111111111111111111111111111111*
@@ -167,38 +168,38 @@ L006270 111111111111111111111111111111111111111111111111111111111111111111*
L006336 111111111111111111111111111111111111111111111111111111111111111111*
L006402
000000000000000000000000000000000000000000000000000000000000000000
- 111111111111111111111111111111111111111111101111111111111111111111*
+ 101111111111111111111111111111111111111111111111111111111111111111*
L006534 0010*
-L006538 10100110010000*
-L006552 00100110011110*
-L006566 00101111110000*
-L006580 00010100011111*
-L006594 11101111110000*
-L006608 10100110010010*
-L006622 11001111110000*
-L006636 11001011110011*
+L006538 10100110011000*
+L006552 10100100011110*
+L006566 00001111110000*
+L006580 11100110011111*
+L006594 11111111110000*
+L006608 11001011110010*
+L006622 11110011110000*
+L006636 11110111110011*
L006650 11110011110000*
L006664 11111011110010*
-L006678 11111111110000*
-L006692 10100110010011*
-L006706 11000011110000*
-L006720 11111011110010*
-L006734 11110111111111*
+L006678 11110111110001*
+L006692 11111111110011*
+L006706 11110011110000*
+L006720 11111011110011*
+L006734 11110111110101*
L006748 11111111110011*
NOTE BLOCK 1 *
L006762
111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111011111111111111111111111111111111111110111
- 110101101010111101111111111111111111111111111111111111110111111111
- 101111111111111111110111111111111111111111111111111111011111111111
- 111111111111111111111111111111111111111111111111101111111111111111
- 111111111111111111111111111111111101111111111111111111111111111111
- 111111111111111111111111111011111111111111111111111111111111111111
- 111111111111010111111110111111111111111111111111111111111111111111
- 111111111111111111111111111110110111111111101111111111111111111111*
+ 111111111101011111111111111111111111111111111111111111111111111111
+ 110101101011111111111111111111111101111111111111111111110111111111
+ 111111111111111111110111010101111011111111100110111111011111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111111101111111111111111111111111111111111
+ 111111111111111101111110111111111111111111111111111111111111111111
+ 111111111111110111111111111111111111101111111111111111111111111111
+ 101111111111111111011111111111111111111111111111111111111111111111*
L007356
111111111111111111111111111111111111111111111111111111111111111111*
-L007422 111111111111111111111111111111111111111111111111111111111111110111*
+L007422 110111111111111111111111111111111111111111111111111111111111111111*
L007488 000000000000000000000000000000000000000000000000000000000000000000*
L007554 000000000000000000000000000000000000000000000000000000000000000000*
L007620 000000000000000000000000000000000000000000000000000000000000000000*
@@ -210,59 +211,59 @@ L007950 000000000000000000000000000000000000000000000000000000000000000000*
L008016 000000000000000000000000000000000000000000000000000000000000000000*
L008082
111111111111111111111111111111111111111111111111111111111111111111*
-L008148 111111111111111111110111111111111110111111111111111111111111111111*
-L008214 111111111111111111110101111111111111111111111111111111111111111111*
-L008280 111111110111111111111110111111111101111111111111111111111111111111*
+L008148 111111110111110110111111111111111111111111111111111111111111111111*
+L008214 111111111111111011110111111111111111111111111111111111111111111111*
+L008280 111111111111111101110111111111111111111111111111111111111111111111*
L008346 000000000000000000000000000000000000000000000000000000000000000000*
L008412 000000000000000000000000000000000000000000000000000000000000000000*
-L008478 111111111111111111111111111111111111111111111111111111111111111111*
-L008544 111111111111111111111111111111111111111111111111111111111111111111*
-L008610 111111111111111111111111111111111111111111111111111111111111111111*
-L008676 111111111111111111111111111111111111111111111111111111111111111111*
-L008742 111111111111111111111111111111111111111111111111111111111111111111*
+L008478 111111111111110110111111111011111111111111101110111111111111111111*
+L008544 111111111111110110111111111011111111111111011101111111111111111111*
+L008610 111111111111110110111111111111111111111111100101111111111111111111*
+L008676 111111111111110110111111111111111111111111010110111111111111111111*
+L008742 000000000000000000000000000000000000000000000000000000000000000000*
L008808
111111111111111111111111111111111111111111111111111111111111111111*
-L008874 111111111111111111111111111111111110111111111111111111011111111111*
-L008940 111111111111111111111101111111111111111111111111111111011111111111*
-L009006 011111111111111111111110111111111101111111111111111111111111111111*
+L008874 111111111111110110111111111111110111111111111111111111111111111111*
+L008940 111111111111111011111111111111111111111111111111111111011111111111*
+L009006 111111111111111101111111111111111111111111111111111111011111111111*
L009072 000000000000000000000000000000000000000000000000000000000000000000*
L009138 000000000000000000000000000000000000000000000000000000000000000000*
-L009204 111111111111111111111111010111111110111111111111111111111111111111*
-L009270 111111111111111111111111111111111110111111111111111111110111111111*
-L009336 111111111111111011111111111111111111111111111111111111110111111111*
-L009402 111111111111111111111111011110111110111111111111111111111111111111*
+L009204 111111111111111011111111111111111111111111111111111111111011111111*
+L009270 111111111111111111101111111111111111111111111111111111111011111111*
+L009336 111111111101111011111111101101111111101111111111111111111111111111*
+L009402 111111111101111111101111101101111111101111111111111111111111111111*
L009468 000000000000000000000000000000000000000000000000000000000000000000*
L009534
111111111111111111111111111111111111111111111111111111111111111111*
-L009600 111101111111111111111111111111111110111111111111111111111111111111*
-L009666 111101111111111111111101111111111111111111111111111111111111111111*
-L009732 111111011111111111111110111111111101111111111111111111111111111111*
+L009600 111111011111110110111111111111111111111111111111111111111111111111*
+L009666 111101111111111011111111111111111111111111111111111111111111111111*
+L009732 111101111111111101111111111111111111111111111111111111111111111111*
L009798 000000000000000000000000000000000000000000000000000000000000000000*
L009864 000000000000000000000000000000000000000000000000000000000000000000*
-L009930 111111111111111111111111111111110110111111111111111111111111111111*
-L009996 110111111111111111111111111111111110111111111111111111111111111111*
-L010062 000000000000000000000000000000000000000000000000000000000000000000*
+L009930 110111111111111111111111111111011111111111111111111111111111111111*
+L009996 110111111111111111111110111111111111111111111111111111111111111111*
+L010062 111011111111111111111101111111101111111111111111111111111111111111*
L010128 000000000000000000000000000000000000000000000000000000000000000000*
L010194 000000000000000000000000000000000000000000000000000000000000000000*
L010260
000000000000000000000000000000000000000000000000000000000000000000*
-L010326 111111111111111101111111111111111110111111111111111111111111111111*
-L010392 111111111111111101111101111111111111111111111111111111111111111111*
-L010458 111111111111111110111110111111111101111111111111111111111111111111*
+L010326 111111111111010111111111111111111111111111111111111111111111111111*
+L010392 111111111111110111111111111111111101111111111111111111111111111111*
+L010458 000000000000000000000000000000000000000000000000000000000000000000*
L010524 000000000000000000000000000000000000000000000000000000000000000000*
L010590 000000000000000000000000000000000000000000000000000000000000000000*
-L010656 111111111111011111111111111111111111111111111111111111111111110111*
-L010722 111111111111111111111111111111111111111111111111101111111111110111*
-L010788 111111111111101111111111111111111111111111111111011111111111111011*
+L010656 111111111111011011111111111111111111111111111111111111111011111111*
+L010722 111111111101111111111111101101111111101111111111111111110111111111*
+L010788 000000000000000000000000000000000000000000000000000000000000000000*
L010854 000000000000000000000000000000000000000000000000000000000000000000*
L010920 000000000000000000000000000000000000000000000000000000000000000000*
L010986
000000000000000000000000000000000000000000000000000000000000000000*
-L011052 111111111111111111111111011001111111111111111111111111111111111111*
-L011118 111111111111111111111111011111111101111111111111111111111111111111*
-L011184 111111111101111111111111111111111101111111111111111111111111111111*
-L011250 000000000000000000000000000000000000000000000000000000000000000000*
-L011316 000000000000000000000000000000000000000000000000000000000000000000*
+L011052 111111111111111111111111111111111111111111111111111111111111111111*
+L011118 111111111111111111111111111111111111111111111111111111111111111111*
+L011184 111111111111111111111111111111111111111111111111111111111111111111*
+L011250 111111111111111111111111111111111111111111111111111111111111111111*
+L011316 111111111111111111111111111111111111111111111111111111111111111111*
L011382 111111111111111111111111111111111111111111111111111111111111111111*
L011448 111111111111111111111111111111111111111111111111111111111111111111*
L011514 111111111111111111111111111111111111111111111111111111111111111111*
@@ -294,66 +295,66 @@ L013032 111111111111111111111111111111111111111111111111111111111111111111*
L013098 111111111111111111111111111111111111111111111111111111111111111111*
L013164
000000000000000000000000000000000000000000000000000000000000000000
- 111111111111111111111111111111111111111111101111111111111111111111*
+ 101111111111111111111111111111111111111111111111111111111111111111*
L013296 0010*
L013300 00100100010000*
L013314 00100100011110*
L013328 10100110010000*
-L013342 11100011111111*
+L013342 10100101011111*
L013356 10100110010001*
-L013370 10100100011111*
+L013370 11100110011111*
L013384 10100110010000*
-L013398 10100100011111*
-L013412 10100100010001*
+L013398 10100100011110*
+L013412 10100100010000*
L013426 10100100010011*
-L013440 10100100010000*
-L013454 11010011110010*
+L013440 11011111110001*
+L013454 11110011110011*
L013468 11111011110000*
-L013482 11111111110011*
-L013496 11110011111101*
+L013482 11111111110010*
+L013496 11110011111100*
L013510 11111011111111*
NOTE BLOCK 2 *
L013524
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111011111111111111111111111111111111111111111111*
+ 111111111111111111111111111111111111111110111111111111111111111111
+ 111111111101111111111111111111111111111111111111111111111111111111
+ 111111111111101111111111111111111111111111111111111111110111111111
+ 111011100111111110111111111101111111111111110111111111111111111111
+ 111111111111111111011111111111111111111111111111111111111111111111
+ 111101111111111111111111011111111111011111111111111111111111111111
+ 111111111111111111111101110111111101111111111111111111111111111111
+ 111111111111110111111011111111111111111011111110111111111111111111
+ 101111111111111111111111111111111111111111111111111111111111111111*
L014118
000000000000000000000000000000000000000000000000000000000000000000*
-L014184 000000000000000000000000000000000000000000000000000000000000000000*
-L014250 000000000000000000000000000000000000000000000000000000000000000000*
-L014316 000000000000000000000000000000000000000000000000000000000000000000*
+L014184 111111111111111111111111111111111111111111111110111111111111111111*
+L014250 111101111111111111101111111111111111111111111111111111111011111111*
+L014316 111101111001111111111011111101111111111111111111111111110111111111*
L014382 000000000000000000000000000000000000000000000000000000000000000000*
L014448 000000000000000000000000000000000000000000000000000000000000000000*
L014514 111111111111111111111111111111111111111111111111111111111111111111*
-L014580 111111111111111111111111111111111111111111111111111111111111111111*
-L014646 111111111111111111111111111111111111111111111111111111111111111111*
-L014712 111111111111111111111111111111111111111111111111111111111111111111*
-L014778 111111111111111111111111111111111111111111111111111111111111111111*
+L014580 000000000000000000000000000000000000000000000000000000000000000000*
+L014646 000000000000000000000000000000000000000000000000000000000000000000*
+L014712 000000000000000000000000000000000000000000000000000000000000000000*
+L014778 000000000000000000000000000000000000000000000000000000000000000000*
L014844
000000000000000000000000000000000000000000000000000000000000000000*
-L014910 111111111111111111111111111111111111111111111111111111111111111111*
-L014976 111111111111111111111111111111111111111111111111111111111111111111*
-L015042 111111111111111111111111111111111111111111111111111111111111111111*
-L015108 111111111111111111111111111111111111111111111111111111111111111111*
-L015174 111111111111111111111111111111111111111111111111111111111111111111*
-L015240 111111111111111111111111111111111111111111111111111111111111111111*
-L015306 111111111111111111111111111111111111111111111111111111111111111111*
-L015372 111111111111111111111111111111111111111111111111111111111111111111*
-L015438 111111111111111111111111111111111111111111111111111111111111111111*
-L015504 111111111111111111111111111111111111111111111111111111111111111111*
+L014910 111111111111111011111111111111111111111111110111111111111111111111*
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L015570
000000000000000000000000000000000000000000000000000000000000000000*
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L015966 111111111111111111111111111111111111111111111111111111111111111111*
L016032 111111111111111111111111111111111111111111111111111111111111111111*
L016098 111111111111111111111111111111111111111111111111111111111111111111*
@@ -408,7 +409,7 @@ L019002 111111111111111111111111111111111111111111111111111111111111111111*
L019068 111111111111111111111111111111111111111111111111111111111111111111*
L019134 111111111111111111111111111111111111111111111111111111111111111111*
L019200
- 111111111111111111111011111111111111111111111111111111111111111111*
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L019266 111111111111111111111111111111111111111111111111111111111111111111*
L019332 111111111111111111111111111111111111111111111111111111111111111111*
L019398 111111111111111111111111111111111111111111111111111111111111111111*
@@ -421,110 +422,110 @@ L019794 111111111111111111111111111111111111111111111111111111111111111111*
L019860 111111111111111111111111111111111111111111111111111111111111111111*
L019926
000000000000000000000000000000000000000000000000000000000000000000
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+ 101111111111111111111111111111111111111111111111111111111111111111*
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L020188 11111011110011*
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L020216 11111111111111*
L020230 11110011110000*
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L020258 11110111110101*
L020272 11111111111111*
NOTE BLOCK 3 *
L020286
111111011111111111111111111111111111111111111111111111111111111111
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111111111111111111111111111111111101111111101111111111110111111111*
L020880
111111111111111111111111111111111111111111111111111111111111111111*
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L021012 000000000000000000000000000000000000000000000000000000000000000000*
L021078 000000000000000000000000000000000000000000000000000000000000000000*
L021144 000000000000000000000000000000000000000000000000000000000000000000*
L021210 000000000000000000000000000000000000000000000000000000000000000000*
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L021474 000000000000000000000000000000000000000000000000000000000000000000*
L021540 000000000000000000000000000000000000000000000000000000000000000000*
L021606
111111111111111111111111111111111111111111111111111111111111111111*
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L021804 000000000000000000000000000000000000000000000000000000000000000000*
L021870 000000000000000000000000000000000000000000000000000000000000000000*
L021936 000000000000000000000000000000000000000000000000000000000000000000*
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L022200 000000000000000000000000000000000000000000000000000000000000000000*
L022266 000000000000000000000000000000000000000000000000000000000000000000*
L022332
- 111111111111111111111111111111111111111111111111111111011111111111*
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L022530 000000000000000000000000000000000000000000000000000000000000000000*
L022596 000000000000000000000000000000000000000000000000000000000000000000*
L022662 000000000000000000000000000000000000000000000000000000000000000000*
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L023058
- 111111111111111111111111111111111111111111111111111111011111111111*
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L023322 000000000000000000000000000000000000000000000000000000000000000000*
L023388 000000000000000000000000000000000000000000000000000000000000000000*
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L023784
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L024510
- 111111111111111111111111111111101111111111111111111111101111101111*
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L025236
111111111111111111111111111111111111111111111111111111111111111111*
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L025368 111111111111111111111111111111111111111111111111111111111111111111*
L025434 111111111111111111111111111111111111111111111111111111111111111111*
L025500 111111111111111111111111111111111111111111111111111111111111111111*
@@ -550,20 +551,20 @@ L026688
000000000000000000000000000000000000000000000000000000000000000000
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L026820 0010*
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L027020 11111011110000*
L027034 11111111110010*
NOTE BLOCK 4 *
@@ -575,12 +576,12 @@ L027048
111111111111110111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
- 011111111111111111111111111011011111111111111111111111111101111111
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L027642
- 111111111111111111111011111111111111111111111111111111111111111111*
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-L027774 101111111111111111111111111011111111111111101111110111111111111111*
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L027840 000000000000000000000000000000000000000000000000000000000000000000*
L027906 000000000000000000000000000000000000000000000000000000000000000000*
L027972 000000000000000000000000000000000000000000000000000000000000000000*
@@ -823,14 +824,14 @@ L040558 11111111111111*
NOTE BLOCK 6 *
L040572
111111111111111111111111111111111111111111111111111111111111111111
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- 011111111111111111111111111111111111111111111111111111111111111111
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- 111111111111111111011111111111111111111111101111111111111111111111*
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+ 101101111111111111111111111111111111111111111111111111111111111111*
L041166
111111111111111111111111111111111111111111111111111111111111111111*
L041232 111111111111011111111111111111111111111111111111111111111111111111*
@@ -838,7 +839,7 @@ L041298 000000000000000000000000000000000000000000000000000000000000000000*
L041364 000000000000000000000000000000000000000000000000000000000000000000*
L041430 000000000000000000000000000000000000000000000000000000000000000000*
L041496 000000000000000000000000000000000000000000000000000000000000000000*
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L041628 000000000000000000000000000000000000000000000000000000000000000000*
L041694 000000000000000000000000000000000000000000000000000000000000000000*
L041760 000000000000000000000000000000000000000000000000000000000000000000*
@@ -846,42 +847,42 @@ L041826 000000000000000000000000000000000000000000000000000000000000000000*
L041892
111111111111111111111111111111111111111111111111111111111111111111*
L041958 111111110111111111111111111111111111111111111111111111111111111111*
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L042222 000000000000000000000000000000000000000000000000000000000000000000*
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L042618
000000000000000000000000000000000000000000000000000000000000000000*
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L042948 000000000000000000000000000000000000000000000000000000000000000000*
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L043344
000000000000000000000000000000000000000000000000000000000000000000*
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L043674 000000000000000000000000000000000000000000000000000000000000000000*
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L044070
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L044202 111111111111111111111111111111111111111111111111111111111111111111*
L044268 111111111111111111111111111111111111111111111111111111111111111111*
L044334 111111111111111111111111111111111111111111111111111111111111111111*
@@ -892,7 +893,7 @@ L044598 111111111111111111111111111111111111111111111111111111111111111111*
L044664 111111111111111111111111111111111111111111111111111111111111111111*
L044730 111111111111111111111111111111111111111111111111111111111111111111*
L044796
- 111111111111111011111111111111101111111111111111111111101111111111*
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L044862 111111111111111111111111111111111111111111111111111111111111111111*
L044928 111111111111111111111111111111111111111111111111111111111111111111*
L044994 111111111111111111111111111111111111111111111111111111111111111111*
@@ -904,7 +905,7 @@ L045324 111111111111111111111111111111111111111111111111111111111111111111*
L045390 111111111111111111111111111111111111111111111111111111111111111111*
L045456 111111111111111111111111111111111111111111111111111111111111111111*
L045522
- 000000000000000000000000000000000000000000000000000000000000000000*
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L045588 111111111111111111111111111111111111111111111111111111111111111111*
L045654 111111111111111111111111111111111111111111111111111111111111111111*
L045720 111111111111111111111111111111111111111111111111111111111111111111*
@@ -917,7 +918,7 @@ L046116 111111111111111111111111111111111111111111111111111111111111111111*
L046182 111111111111111111111111111111111111111111111111111111111111111111*
L046248
000000000000000000000000000000000000000000000000000000000000000000*
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L046380 111111111111111111111111111111111111111111111111111111111111111111*
L046446 111111111111111111111111111111111111111111111111111111111111111111*
L046512 111111111111111111111111111111111111111111111111111111111111111111*
@@ -928,111 +929,111 @@ L046776 111111111111111111111111111111111111111111111111111111111111111111*
L046842 111111111111111111111111111111111111111111111111111111111111111111*
L046908 111111111111111111111111111111111111111111111111111111111111111111*
L046974
- 111111111111111111111111111111111111111111101111111111111111111111
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L047106 0010*
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NOTE BLOCK 7 *
L047334
- 111111111011111111111111111111111111111111111111111111111111111111
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L047928
000000000000000000000000000000000000000000000000000000000000000000*
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L048126 000000000000000000000000000000000000000000000000000000000000000000*
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L048654
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L049380
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L050106
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L050436 000000000000000000000000000000000000000000000000000000000000000000*
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L050634 000000000000000000000000000000000000000000000000000000000000000000*
L050700 000000000000000000000000000000000000000000000000000000000000000000*
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L050832
111111111111111111111111111111011111111111111111111111111111111111*
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L051030 000000000000000000000000000000000000000000000000000000000000000000*
L051096 000000000000000000000000000000000000000000000000000000000000000000*
L051162 000000000000000000000000000000000000000000000000000000000000000000*
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-L051426 110111111101101111111111100111111101111111111111111111111111111001*
-L051492 111111111101111111111111111111111111111111111111111111101111111111*
+L051228 111111111110111111111111111111111111111111111111111111111111111111*
+L051294 000000000000000000000000000000000000000000000000000000000000000000*
+L051360 000000000000000000000000000000000000000000000000000000000000000000*
+L051426 000000000000000000000000000000000000000000000000000000000000000000*
+L051492 000000000000000000000000000000000000000000000000000000000000000000*
L051558
- 111111111111111111111111111111011111111111111111111111111111111111*
-L051624 111111111111111111111111111111111111111111111111111111111111111111*
-L051690 111111111111111111111111111111101111111101111111111111111111111111*
-L051756 111111111101111011111111111111111111111111111111111111111111111111*
-L051822 111111111111111111011111111111111111111111111111111111111111111111*
+ 111111111111111111111111111111111111111111111101111111111111111111*
+L051624 111111111111111111110111111111111111111111111111111111111111111111*
+L051690 000000000000000000000000000000000000000000000000000000000000000000*
+L051756 000000000000000000000000000000000000000000000000000000000000000000*
+L051822 000000000000000000000000000000000000000000000000000000000000000000*
L051888 000000000000000000000000000000000000000000000000000000000000000000*
-L051954 111101101111111111111111111111111111111111111111111111110111111111*
-L052020 111111111111111111101111111110111111111111111111111111111111111111*
+L051954 111111111111111111011111111111111111111111111111111111111111111111*
+L052020 000000000000000000000000000000000000000000000000000000000000000000*
L052086 000000000000000000000000000000000000000000000000000000000000000000*
L052152 000000000000000000000000000000000000000000000000000000000000000000*
L052218 000000000000000000000000000000000000000000000000000000000000000000*
L052284
- 111111111111111111111111111111101111111111101111111111101111111111*
-L052350 111111111111111111111111111111111111011111111111111111111111111111*
+ 111111111111111111111111111111101111111111111110111111111111101111*
+L052350 111111111101111111111111111111111111111111111111111111111111111111*
L052416 111111111111111111111111111111111111111111111111111111111111111111*
L052482 111111111111111111111111111111111111111111111111111111111111111111*
L052548 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1044,7 +1045,7 @@ L052878 111111111111111111111111111111111111111111111111111111111111111111*
L052944 111111111111111111111111111111111111111111111111111111111111111111*
L053010
111111111111111111111111111111111111111111111111111111111111111111*
-L053076 111111111111111111110111111111111111111111111111111111111111111111*
+L053076 111111111111111111111111111111111111111111111111111111111111111111*
L053142 111111111111111111111111111111111111111111111111111111111111111111*
L053208 111111111111111111111111111111111111111111111111111111111111111111*
L053274 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1056,43 +1057,43 @@ L053604 111111111111111111111111111111111111111111111111111111111111111111*
L053670 111111111111111111111111111111111111111111111111111111111111111111*
L053736
000000000000000000000000000000000000000000000000000000000000000000
- 101111111111111111111111111111111111111111111111111111111111111111*
+ 111111111111111111111111111111111111111111101111111111111111111111*
L053868 0010*
-L053872 11100110011100*
-L053886 11100110010010*
-L053900 00100110010000*
-L053914 00010110010011*
-L053928 11101011111001*
-L053942 10100110011111*
+L053872 11100110011010*
+L053886 00101011110010*
+L053900 11100110011001*
+L053914 00100110010011*
+L053928 10100110010000*
+L053942 10100110011110*
L053956 10100110010000*
-L053970 10100100010010*
-L053984 00100110011101*
-L053998 10100110010011*
-L054012 00110011110000*
-L054026 11100110011110*
-L054040 00010110010010*
-L054054 11101011110011*
-L054068 00110110011101*
-L054082 11001111111111*
+L053970 10100100010011*
+L053984 11100110010001*
+L053998 00100100010011*
+L054012 00100110011110*
+L054026 00100110010010*
+L054040 00010100010010*
+L054054 11010011110011*
+L054068 11111011110011*
+L054082 11111111111111*
E1
-1
+0
11111100
-1
-00110011
-1
+0
+01110011
+0
00000000
-1
+0
11000001
-1
+0
01111111
-1
+0
10100000
-1
+0
10001111
-1
+0
10000010
1
*
-CA8F5*
+C527D*
U00000000000000000000000000000000*
-DF40
+E1E7
diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco
index 1fe2204..2b7a354 100644
--- a/Logic/68030_tk.lco
+++ b/Logic/68030_tk.lco
@@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
-DATE = 5/29/14;
-TIME = 22:04:32;
+DATE = 6/1/14;
+TIME = 01:03:29;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@@ -76,19 +76,24 @@ Usercode_Format = Hex;
[LOCATION ASSIGNMENTS]
Layer = OFF;
+A_26_ = pin,17,-,C,-;
+A_25_ = pin,18,-,C,-;
+A_24_ = pin,19,-,C,-;
+A_23_ = pin,84,-,H,-;
+A_31_ = pin,4,-,B,-;
+A_22_ = pin,85,-,H,-;
A_21_ = pin,94,-,A,-;
A_20_ = pin,93,-,A,-;
A_19_ = pin,97,-,A,-;
-A_18_ = pin,95,-,A,-;
-A_31_ = pin,4,-,B,-;
-A_17_ = pin,59,-,F,-;
-A_16_ = pin,96,-,A,-;
IPL_2_ = pin,68,-,G,-;
+A_18_ = pin,95,-,A,-;
+A_17_ = pin,59,-,F,-;
+FC_1_ = pin,58,-,F,-;
+A_16_ = pin,96,-,A,-;
+RW_000 = pin,80,-,H,-;
IPL_1_ = pin,56,-,F,-;
IPL_0_ = pin,67,-,G,-;
-DSACK_0_ = pin,80,-,H,-;
FC_0_ = pin,57,-,F,-;
-FC_1_ = pin,58,-,F,-;
nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
@@ -103,6 +108,7 @@ AVEC_EXP = pin,22,-,C,-;
VPA = pin,36,-,-,-;
RST = pin,86,-,-,-;
RW = pin,71,-,G,-;
+AMIGA_BUS_ENABLE = pin,34,-,D,-;
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
CIIN = pin,47,-,E,-;
@@ -110,18 +116,12 @@ A_30_ = pin,5,-,B,-;
A_29_ = pin,6,-,B,-;
A_28_ = pin,15,-,C,-;
A_27_ = pin,16,-,C,-;
-A_26_ = pin,17,-,C,-;
-A_25_ = pin,18,-,C,-;
-A_24_ = pin,19,-,C,-;
-A_23_ = pin,84,-,H,-;
-A_22_ = pin,85,-,H,-;
SIZE_1_ = pin,79,-,H,-;
IPL_030_2_ = pin,9,-,B,-;
-IPL_030_1_ = pin,7,-,B,-;
-IPL_030_0_ = pin,8,-,B,-;
-DSACK_1_ = pin,81,-,H,-;
AS_030 = pin,82,-,H,-;
+IPL_030_1_ = pin,7,-,B,-;
AS_000 = pin,33,-,D,-;
+IPL_030_0_ = pin,8,-,B,-;
DS_030 = pin,98,-,A,-;
UDS_000 = pin,32,-,D,-;
LDS_000 = pin,31,-,D,-;
@@ -130,35 +130,35 @@ BG_000 = pin,29,-,D,-;
BGACK_030 = pin,83,-,H,-;
CLK_EXP = pin,10,-,B,-;
FPU_CS = pin,78,-,H,-;
+DSACK1 = pin,81,-,H,-;
E = pin,66,-,G,-;
VMA = pin,35,-,D,-;
RESET = pin,3,-,B,-;
-AMIGA_BUS_ENABLE = pin,34,-,D,-;
SIZE_0_ = pin,70,-,G,-;
-inst_AS_030_000_SYNC = node,-,-,H,9;
+inst_AS_030_000_SYNC = node,-,-,C,3;
inst_BGACK_030_INT_D = node,-,-,D,10;
-inst_VPA_D = node,-,-,H,14;
-inst_CLK_OUT_PRE_50_D = node,-,-,A,3;
-inst_CLK_000_D0 = node,-,-,D,12;
-inst_CLK_000_D1 = node,-,-,H,3;
-inst_CLK_000_D2 = node,-,-,H,12;
-inst_CLK_000_D4 = node,-,-,H,8;
-inst_DTACK_D0 = node,-,-,A,1;
-inst_CLK_OUT_PRE_50 = node,-,-,G,1;
-inst_CLK_OUT_PRE_25 = node,-,-,B,9;
-SM_AMIGA_1_ = node,-,-,B,10;
-SM_AMIGA_0_ = node,-,-,B,5;
-SM_AMIGA_6_ = node,-,-,H,7;
-SM_AMIGA_5_ = node,-,-,D,2;
-inst_CLK_000_D3 = node,-,-,H,2;
-inst_CLK_030_H = node,-,-,A,0;
-SM_AMIGA_7_ = node,-,-,A,11;
-SM_AMIGA_4_ = node,-,-,B,7;
-SM_AMIGA_3_ = node,-,-,G,7;
-SM_AMIGA_2_ = node,-,-,G,6;
-cpu_est_0_ = node,-,-,B,8;
-cpu_est_1_ = node,-,-,G,4;
-cpu_est_2_ = node,-,-,G,5;
+inst_VPA_D = node,-,-,H,10;
+inst_CLK_OUT_PRE_50_D = node,-,-,H,12;
+inst_CLK_000_D0 = node,-,-,D,5;
+inst_CLK_000_D1 = node,-,-,D,7;
+inst_CLK_000_D2 = node,-,-,H,3;
+inst_DTACK_D0 = node,-,-,H,11;
+inst_CLK_OUT_PRE_50 = node,-,-,H,9;
+inst_CLK_OUT_PRE_25 = node,-,-,B,7;
+SM_AMIGA_7_ = node,-,-,B,5;
+SM_AMIGA_6_ = node,-,-,B,9;
+SM_AMIGA_0_ = node,-,-,A,1;
+SM_AMIGA_5_ = node,-,-,B,8;
+SM_AMIGA_2_ = node,-,-,G,5;
+inst_RW_000_INT = node,-,-,A,3;
+inst_CLK_000_D3 = node,-,-,C,4;
+inst_CLK_030_H = node,-,-,H,5;
+SM_AMIGA_4_ = node,-,-,D,9;
+SM_AMIGA_3_ = node,-,-,G,6;
+SM_AMIGA_1_ = node,-,-,H,7;
+cpu_est_0_ = node,-,-,C,2;
+cpu_est_1_ = node,-,-,B,3;
+cpu_est_2_ = node,-,-,G,4;
[GROUP ASSIGNMENTS]
Layer = OFF;
@@ -195,7 +195,7 @@ Page_Break = Yes;
[POWER]
Powerlevel = Low,High;
-Default = Low;
+Default = High;
Type = GLB;
[SOURCE CONSTRAINT OPTION]
diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out
index 73f3348..9a58f18 100644
--- a/Logic/68030_tk.out
+++ b/Logic/68030_tk.out
@@ -78512,6 +78512,5207 @@
16 A_26_ 1 -1 -1 1 4 16 -1
15 A_27_ 1 -1 -1 1 4 15 -1
14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D4 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 308 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 314 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 309 SM_AMIGA_4_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 303 SM_AMIGA_5_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 305 inst_CLK_000_D3 3 -1 1 3 0 6 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 310 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 322 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 306 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 313 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 311 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 312 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 307 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21
+ 299 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+96 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 318 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 321 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 320 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 317 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 319 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 65 E 5 325 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 323 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 324 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 326 3 0 34 -1 2 1 21
+ 28 BG_000 5 322 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 323 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21
+ 317 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 297 inst_CLK_000_D4 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 306 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 313 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 325 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 312 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 318 RN_AS_000 3 32 3 3 0 3 6 32 -1 2 0 21
+ 300 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 303 inst_CLK_000_D3 3 -1 1 3 0 6 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 308 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 304 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21
+ 311 SM_AMIGA_0_ 3 -1 6 2 0 6 -1 -1 4 0 21
+ 314 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 310 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21
+ 326 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 307 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 301 SM_AMIGA_5_ 3 -1 0 2 0 3 -1 -1 2 0 21
+ 299 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 6 2 1 3 -1 -1 1 0 21
+ 321 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 320 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 309 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 305 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 10 CLK_000 1 -1 -1 2 1 3 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 317 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 3 1 3 6 -1 -1 3 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 300 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 297 inst_CLK_000_D4 3 -1 7 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 0 2 1 6 -1 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 301 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 21
+ 303 inst_CLK_000_D3 3 -1 1 2 0 7 -1 -1 1 0 21
+ 299 CLK_CNT_N_0_ 3 -1 1 2 0 1 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 8 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 304 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 0 1 0 -1 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 0 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 1 1 1 -1 -1 1 0 21
+ 305 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 1 3 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 317 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 3 1 3 6 -1 -1 3 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 300 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 297 inst_CLK_000_D4 3 -1 7 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 0 2 1 6 -1 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 301 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 21
+ 303 inst_CLK_000_D3 3 -1 1 2 0 7 -1 -1 1 0 21
+ 299 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 8 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 304 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 307 CLK_CNT_N_0_ 3 -1 0 1 0 -1 -1 2 0 21
+ 308 CLK_CNT_N_1_ 3 -1 0 1 0 -1 -1 1 0 21
+ 306 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 305 CLK_CNT_P_1_ 3 -1 1 1 1 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 1 3 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 320 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 301 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 304 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 3 0 21
+ 303 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 308 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 307 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 302 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 305 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 306 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 300 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 299 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+100 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 324 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 327 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 326 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 323 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 325 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 322 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 331 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 333 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 321 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 332 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 323 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 299 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 312 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 317 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 inst_CLK_OUT_PRE_33 3 -1 1 2 1 6 -1 -1 4 0 21
+ 331 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 318 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 316 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 332 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 324 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 7 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 327 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 326 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 325 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 333 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 0 1 1 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 7 1 1 -1 -1 1 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 323 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 326 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 325 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 322 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 324 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 4 0 21
+ 9 CLK_EXP 0 1 0 9 -1 4 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 328 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 329 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 327 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 328 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 322 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 316 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 331 RN_VMA 3 34 3 3 1 3 6 34 -1 2 1 21
+ 329 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 7 3 1 3 7 -1 -1 2 0 21
+ 299 SM_AMIGA_6_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 0 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 3 1 3 6 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 4 0 21
+ 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 315 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 323 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 3 2 3 7 -1 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 1 2 1 6 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 2 1 6 -1 -1 1 0 21
+ 326 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 325 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 0 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 323 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 326 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 325 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 322 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 324 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 4 0 21
+ 9 CLK_EXP 0 1 0 9 -1 4 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 328 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 329 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 327 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 328 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 322 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 316 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 331 RN_VMA 3 34 3 3 1 3 6 34 -1 2 1 21
+ 329 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 7 3 1 3 7 -1 -1 2 0 21
+ 299 SM_AMIGA_6_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 0 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 3 1 3 6 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 4 0 21
+ 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 315 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 323 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 3 2 3 7 -1 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 1 2 1 6 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 2 1 6 -1 -1 1 0 21
+ 326 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 325 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 0 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 323 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 326 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 325 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 322 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 324 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 4 0 21
+ 9 CLK_EXP 0 1 0 9 -1 4 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 328 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 329 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 327 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 328 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 322 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 316 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 331 RN_VMA 3 34 3 3 1 3 6 34 -1 2 1 21
+ 329 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 7 3 1 3 7 -1 -1 2 0 21
+ 299 SM_AMIGA_6_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 0 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 3 1 3 6 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 4 0 21
+ 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 315 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 323 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 3 2 3 7 -1 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 1 2 1 6 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 2 1 6 -1 -1 1 0 21
+ 326 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 325 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 0 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 323 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 326 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 325 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 322 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 324 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 4 0 21
+ 9 CLK_EXP 0 1 0 9 -1 4 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 328 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 329 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 327 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 328 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 322 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 316 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 331 RN_VMA 3 34 3 3 1 3 6 34 -1 2 1 21
+ 329 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 7 3 1 3 7 -1 -1 2 0 21
+ 299 SM_AMIGA_6_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 0 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 3 1 3 6 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 4 0 21
+ 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 315 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 323 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 3 2 3 7 -1 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 1 2 1 6 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 2 1 6 -1 -1 1 0 21
+ 326 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 325 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 0 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 323 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 326 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 325 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 322 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 324 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 4 0 21
+ 9 CLK_EXP 0 1 0 9 -1 4 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 328 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 329 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 327 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 328 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 322 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 316 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 331 RN_VMA 3 34 3 3 1 3 6 34 -1 2 1 21
+ 329 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 7 3 1 3 7 -1 -1 2 0 21
+ 299 SM_AMIGA_6_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 inst_CLK_000_D3 3 -1 0 3 0 1 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D4 3 -1 1 3 0 3 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 3 1 3 6 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 2 1 6 -1 -1 4 0 21
+ 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 315 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 301 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 323 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 307 CLK_CNT_P_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 305 CLK_CNT_N_0_ 3 -1 1 2 1 6 -1 -1 2 0 21
+ 300 SM_AMIGA_5_ 3 -1 3 2 3 7 -1 -1 2 0 21
+ 308 CLK_CNT_P_1_ 3 -1 1 2 1 6 -1 -1 1 0 21
+ 306 CLK_CNT_N_1_ 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 1 2 1 6 -1 -1 1 0 21
+ 326 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 325 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 303 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 4 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 304 inst_CLK_000_D2 3 -1 7 1 0 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D4 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 308 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 314 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 309 SM_AMIGA_4_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 303 SM_AMIGA_5_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 305 inst_CLK_000_D3 3 -1 1 3 0 6 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 310 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 322 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 306 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 313 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 311 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 312 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 307 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21
+ 299 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+96 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 318 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 321 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 320 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 317 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 319 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 65 E 5 325 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 323 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 324 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 326 3 0 34 -1 2 1 21
+ 28 BG_000 5 322 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 323 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21
+ 317 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 297 inst_CLK_000_D4 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 306 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 313 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 325 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 312 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 318 RN_AS_000 3 32 3 3 0 3 6 32 -1 2 0 21
+ 300 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 303 inst_CLK_000_D3 3 -1 1 3 0 6 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 308 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 304 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21
+ 311 SM_AMIGA_0_ 3 -1 6 2 0 6 -1 -1 4 0 21
+ 314 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 310 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21
+ 326 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 307 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 301 SM_AMIGA_5_ 3 -1 0 2 0 3 -1 -1 2 0 21
+ 299 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 6 2 1 3 -1 -1 1 0 21
+ 321 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 320 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 309 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 305 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 10 CLK_000 1 -1 -1 2 1 3 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+95 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 317 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 320 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 319 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 316 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 318 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 315 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 65 E 5 324 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 314 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 322 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 323 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 325 3 0 34 -1 2 1 21
+ 28 BG_000 5 321 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 322 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 316 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 300 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 302 inst_CLK_000_D2 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 305 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 312 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 324 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 311 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 303 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 3 0 21
+ 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 297 inst_CLK_000_D3 3 -1 3 3 0 6 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 307 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 304 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21
+ 313 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 309 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21
+ 325 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 317 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 306 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 301 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 299 inst_CLK_OUT_PRE_50 3 -1 6 2 1 6 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21
+ 320 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 319 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 318 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 310 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 308 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 314 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 321 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 315 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 298 inst_DTACK_D0 3 -1 6 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+96 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 318 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 321 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 320 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 317 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 319 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 65 E 5 325 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 323 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 324 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 326 3 0 34 -1 2 1 21
+ 28 BG_000 5 322 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 323 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 295 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 21
+ 317 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 297 inst_CLK_000_D4 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 306 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 313 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 325 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 312 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 318 RN_AS_000 3 32 3 3 0 3 6 32 -1 2 0 21
+ 300 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 303 inst_CLK_000_D3 3 -1 1 3 0 6 7 -1 -1 1 0 21
+ 296 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 308 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 304 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21
+ 311 SM_AMIGA_0_ 3 -1 6 2 0 6 -1 -1 4 0 21
+ 314 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 310 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21
+ 326 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 307 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 301 SM_AMIGA_5_ 3 -1 0 2 0 3 -1 -1 2 0 21
+ 299 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 6 2 1 3 -1 -1 1 0 21
+ 321 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 320 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 309 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 305 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 298 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 10 CLK_000 1 -1 -1 2 1 3 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D4 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 308 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 314 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 309 SM_AMIGA_4_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 303 SM_AMIGA_5_ 3 -1 0 3 0 3 7 -1 -1 2 0 21
+ 302 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 305 inst_CLK_000_D3 3 -1 1 3 0 6 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 310 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 322 RN_AS_000 3 32 3 2 0 3 32 -1 2 0 21
+ 294 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 306 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 313 SM_AMIGA_0_ 3 -1 0 1 0 -1 -1 4 0 21
+ 311 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 312 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 307 inst_CLK_000_D2 3 -1 7 1 1 -1 -1 1 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21
+ 299 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+76 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 304 7 1 3 80 -1 4 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 31 UDS_000 5 306 3 0 31 -1 10 0 21
+ 30 LDS_000 5 307 3 0 30 -1 7 1 21
+ 65 E 5 309 6 0 65 -1 4 0 21
+ 64 CLK_DIV_OUT 5 311 6 0 64 -1 3 0 21
+ 32 AS_000 5 305 3 0 32 -1 3 0 21
+ 46 CIIN 0 4 0 46 -1 2 0 21
+ 34 VMA 5 310 3 0 34 -1 2 1 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 82 BGACK_030 5 308 7 0 82 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 77 FPU_CS 0 7 0 77 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 28 BG_000 0 3 0 28 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 8 IPL_030_2_ 0 1 0 8 -1 1 0 21
+ 7 IPL_030_0_ 0 1 0 7 -1 1 0 21
+ 6 IPL_030_1_ 0 1 0 6 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 302 SM_AMIGA_0_ 3 -1 6 3 3 6 7 -1 -1 4 0 21
+ 303 SM_AMIGA_1_ 3 -1 6 3 3 6 7 -1 -1 3 0 21
+ 309 RN_E 3 65 6 2 3 6 65 -1 4 0 21
+ 294 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 311 RN_CLK_DIV_OUT 3 64 6 2 1 6 64 -1 3 0 21
+ 305 RN_AS_000 3 32 3 2 3 6 32 -1 3 0 21
+ 300 inst_AS_AMIGA_ENABLE 3 -1 7 2 3 7 -1 -1 3 0 21
+ 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 0 21
+ 310 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 293 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 1 0 21
+ 306 RN_UDS_000 3 31 3 1 3 31 -1 10 0 21
+ 307 RN_LDS_000 3 30 3 1 3 30 -1 7 1 21
+ 304 RN_DSACK_1_ 3 80 7 1 7 80 -1 4 0 21
+ 299 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21
+ 308 RN_BGACK_030 3 82 7 1 3 82 -1 1 0 21
+ 301 SM_AMIGA_LAST_1_ 3 -1 3 1 7 -1 -1 1 0 21
+ 298 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21
+ 297 inst_VPA_SYNC 3 -1 7 1 6 -1 -1 1 0 21
+ 296 SM_AMIGA_LAST_0_ 3 -1 7 1 7 -1 -1 1 0 21
+ 10 CLK_000 9 -1 1 3 10 -1
+ 63 CLK_030 9 -1 0 63 -1
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 35 VPA 1 -1 -1 3 3 6 7 35 -1
+ 96 A_19_ 1 -1 -1 2 4 7 96 -1
+ 95 A_16_ 1 -1 -1 2 4 7 95 -1
+ 94 A_18_ 1 -1 -1 2 4 7 94 -1
+ 85 RST 1 -1 -1 2 1 6 85 -1
+ 81 AS_030 1 -1 -1 2 3 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 58 A_17_ 1 -1 -1 2 4 7 58 -1
+ 13 CPU_SPACE 1 -1 -1 2 3 7 13 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 310 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 305 SM_AMIGA_0_ 3 -1 1 3 0 1 3 -1 -1 4 0 21
+ 314 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 322 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 302 inst_CLK_OUT_PRE_50 3 -1 6 3 0 1 6 -1 -1 1 0 21
+ 300 inst_CLK_000_D4 3 -1 7 3 1 3 7 -1 -1 1 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 303 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 307 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 2 0 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 301 inst_DTACK_D0 3 -1 0 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 0 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+96 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 321 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 6 0 21
+ 65 E 5 327 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 316 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 315 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 325 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 326 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 328 3 0 34 -1 2 1 21
+ 28 BG_000 5 324 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21
+ 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 313 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 327 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 312 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 3 0 21
+ 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 304 SM_AMIGA_6_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 299 inst_CLK_000_D4 3 -1 7 3 0 3 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 308 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21
+ 303 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 4 0 21
+ 314 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 311 SM_AMIGA_2_ 3 -1 1 2 0 1 -1 -1 3 0 21
+ 328 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 320 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 309 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 21
+ 306 inst_CLK_000_D3 3 -1 7 2 0 7 -1 -1 1 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 6 2 1 3 -1 -1 1 0 21
+ 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 8 0 21
+ 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 307 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 310 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 316 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 315 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 300 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 298 inst_CLK_000_D2 3 -1 7 1 7 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 6 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 310 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 305 SM_AMIGA_0_ 3 -1 1 3 0 1 3 -1 -1 4 0 21
+ 314 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 322 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 302 inst_CLK_OUT_PRE_50 3 -1 6 3 0 1 6 -1 -1 1 0 21
+ 300 inst_CLK_000_D4 3 -1 7 3 1 3 7 -1 -1 1 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 303 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 307 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 2 0 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 301 inst_DTACK_D0 3 -1 0 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 0 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 10 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 6 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 310 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 305 SM_AMIGA_0_ 3 -1 1 3 0 1 3 -1 -1 4 0 21
+ 314 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 322 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 302 inst_CLK_OUT_PRE_50 3 -1 6 3 0 1 6 -1 -1 1 0 21
+ 300 inst_CLK_000_D4 3 -1 7 3 1 3 7 -1 -1 1 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 303 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 307 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 2 0 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21
+ 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 301 inst_DTACK_D0 3 -1 0 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 0 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 310 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 305 SM_AMIGA_0_ 3 -1 1 3 0 1 3 -1 -1 4 0 21
+ 314 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 322 RN_AS_000 3 32 3 3 0 1 3 32 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 7 3 0 1 7 -1 -1 1 0 21
+ 302 inst_CLK_OUT_PRE_50 3 -1 6 3 0 1 6 -1 -1 1 0 21
+ 300 inst_CLK_000_D4 3 -1 7 3 1 3 7 -1 -1 1 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 303 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 307 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 2 0 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 301 inst_DTACK_D0 3 -1 0 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 0 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21
+ 65 E 0 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 0 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 0 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 0 1 0 6 -1 3 0 21
+ 82 BGACK_030 0 7 0 82 -1 2 0 21
+ 80 DSACK_1_ 5 320 7 0 80 -1 2 0 21
+ 77 FPU_CS 0 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 0 3 0 34 -1 2 1 21
+ 28 BG_000 0 3 0 28 -1 2 0 21
+ 91 AVEC 0 -1 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 -1 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 -1 0 40 -1 1 0 21
+ 29 DTACK 0 -1 0 29 -1 1 0 21
+ 21 AVEC_EXP 0 -1 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D1 3 -1 -1 3 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21
+ 303 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21
+ 299 inst_CLK_000_D2 3 -1 -1 2 3 7 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 310 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 5 0 21
+ 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21
+ 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 330 RN_VMA 3 34 3 1 3 34 -1 2 1 21
+ 328 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 309 inst_CLK_000_D4 3 -1 -1 1 3 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21
+ 307 inst_CLK_000_D3 3 -1 -1 0 -1 -1 1 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 35 VPA 1 -1 -1 0 35 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21
+ 65 E 0 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 0 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 0 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 0 1 0 6 -1 3 0 21
+ 82 BGACK_030 0 7 0 82 -1 2 0 21
+ 80 DSACK_1_ 5 320 7 0 80 -1 2 0 21
+ 77 FPU_CS 0 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 0 3 0 34 -1 2 1 21
+ 28 BG_000 0 3 0 28 -1 2 0 21
+ 91 AVEC 0 -1 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 -1 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 -1 0 40 -1 1 0 21
+ 29 DTACK 0 -1 0 29 -1 1 0 21
+ 21 AVEC_EXP 0 -1 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21
+ 297 inst_CLK_000_D1 3 -1 -1 3 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21
+ 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 3 0 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21
+ 306 inst_CLK_000_D2 3 -1 -1 2 3 7 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 309 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 5 0 21
+ 307 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21
+ 303 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 330 RN_VMA 3 34 3 1 3 34 -1 2 1 21
+ 328 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 304 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 308 inst_CLK_000_D4 3 -1 -1 1 3 -1 -1 1 0 21
+ 298 inst_CLK_000_D3 3 -1 -1 1 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
+ 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 35 VPA 1 -1 -1 0 35 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21
+ 65 E 0 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 0 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 0 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 0 1 0 6 -1 3 0 21
+ 82 BGACK_030 0 7 0 82 -1 2 0 21
+ 80 DSACK_1_ 5 320 7 0 80 -1 2 0 21
+ 77 FPU_CS 0 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 0 3 0 34 -1 2 1 21
+ 28 BG_000 0 3 0 28 -1 2 0 21
+ 91 AVEC 0 -1 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 -1 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 -1 0 40 -1 1 0 21
+ 29 DTACK 0 -1 0 29 -1 1 0 21
+ 21 AVEC_EXP 0 -1 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D1 3 -1 -1 3 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21
+ 304 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 3 0 21
+ 303 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21
+ 300 inst_CLK_000_D4 3 -1 -1 2 3 7 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 310 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 5 0 21
+ 309 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21
+ 305 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 330 RN_VMA 3 34 3 1 3 34 -1 2 1 21
+ 328 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 307 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 306 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 -1 1 7 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
+ 301 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 35 VPA 1 -1 -1 0 35 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21
+ 65 E 0 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 0 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 0 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 0 1 0 6 -1 3 0 21
+ 82 BGACK_030 0 7 0 82 -1 2 0 21
+ 80 DSACK_1_ 5 320 7 0 80 -1 2 0 21
+ 77 FPU_CS 0 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 0 3 0 34 -1 2 1 21
+ 28 BG_000 0 3 0 28 -1 2 0 21
+ 91 AVEC 0 -1 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 -1 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 -1 0 40 -1 1 0 21
+ 29 DTACK 0 -1 0 29 -1 1 0 21
+ 21 AVEC_EXP 0 -1 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D1 3 -1 -1 3 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21
+ 303 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 310 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 5 0 21
+ 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21
+ 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 330 RN_VMA 3 34 3 1 3 34 -1 2 1 21
+ 328 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21
+ 309 inst_CLK_000_D4 3 -1 -1 1 3 -1 -1 1 0 21
+ 307 inst_CLK_000_D3 3 -1 -1 1 3 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 -1 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 8 0 21
+ 312 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21
+ 313 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 35 VPA 1 -1 -1 0 35 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK_1_ 5 320 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D1 3 -1 3 4 0 1 6 7 -1 -1 1 0 21
+ 303 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21
+ 310 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 304 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 322 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 1 2 0 1 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 1 2 0 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 0 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 8 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21
+ 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 21
+ 307 inst_CLK_000_D4 3 -1 7 1 3 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 0 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 70 RW 1 -1 -1 3 0 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 10 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 6 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 294 DSACK1 5 331 7 1 3 -1 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 293 RW_000 5 -1 6 1 0 -1 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 334 3 0 33 -1 5 0 21
+ 65 E 5 332 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 326 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 329 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 330 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 333 3 0 34 -1 2 1 21
+ 28 BG_000 5 328 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 329 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 299 inst_CLK_000_D0 3 -1 0 5 0 1 3 6 7 -1 -1 1 0 21
+ 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 317 cpu_est_0_ 3 -1 7 4 1 3 6 7 -1 -1 3 0 21
+ 301 inst_CLK_000_D2 3 -1 7 4 0 1 6 7 -1 -1 1 0 21
+ 307 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 318 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 332 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 319 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 3 1 21
+ 312 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 3 0 21
+ 330 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 300 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 309 inst_RW_000_INT 3 -1 0 2 0 6 -1 -1 14 0 21
+ 295 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 316 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 306 SM_AMIGA_0_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 304 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 333 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 314 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 305 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 2 0 21
+ 310 inst_CLK_000_D3 3 -1 7 2 0 7 -1 -1 1 0 21
+ 297 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21
+ 334 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 5 0 21
+ 311 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 315 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 331 RN_DSACK1 3 294 7 1 7 -1 -1 2 0 21
+ 328 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 313 inst_CLK_000_D4 3 -1 7 1 3 -1 -1 1 0 21
+ 303 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21
+ 302 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 298 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 296 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 0 3 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 323 3 3 0 6 7 30 -1 10 0 21
+ 31 UDS_000 5 322 3 3 0 6 7 31 -1 6 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 321 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 329 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 5 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 325 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 324 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21
+ 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D1 3 -1 3 4 0 1 6 7 -1 -1 1 0 21
+ 307 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 315 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 312 SM_AMIGA_4_ 3 -1 0 3 0 3 6 -1 -1 2 0 21
+ 305 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21
+ 316 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 310 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21
+ 304 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 331 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 306 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 303 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 8 0 21
+ 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 5 0 21
+ 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 313 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 325 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 324 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 329 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 311 inst_CLK_000_D4 3 -1 7 1 3 -1 -1 1 0 21
+ 308 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 6 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 319 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21
+ 81 AS_030 5 318 7 3 0 3 7 81 -1 4 0 21
+ 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21
+ 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 320 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 298 inst_CLK_000_D1 3 -1 7 4 0 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 310 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 303 SM_AMIGA_6_ 3 -1 0 3 0 3 6 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 3 0 6 7 -1 -1 1 0 21
+ 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21
+ 309 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21
+ 305 SM_AMIGA_7_ 3 -1 0 2 0 3 -1 -1 5 0 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 313 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21
+ 304 SM_AMIGA_0_ 3 -1 6 2 0 6 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 311 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 1 3 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 0 1 0 -1 -1 8 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 0 1 0 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 1 1 1 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 96 A_19_ 1 -1 -1 2 0 7 96 -1
+ 95 A_16_ 1 -1 -1 2 0 7 95 -1
+ 94 A_18_ 1 -1 -1 2 0 7 94 -1
+ 58 A_17_ 1 -1 -1 2 0 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 0 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 0 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 0 7 27 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 319 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 318 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 4 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 320 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 304 SM_AMIGA_6_ 3 -1 1 4 0 1 3 7 -1 -1 2 0 21
+ 306 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 310 SM_AMIGA_7_ 3 -1 1 3 1 3 7 -1 -1 5 0 21
+ 303 SM_AMIGA_0_ 3 -1 1 3 0 1 3 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 2 1 7 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 309 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 0 7 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 0 2 3 6 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21
+ 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 4 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 305 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21
+ 307 inst_CLK_000_D3 3 -1 7 1 1 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 0 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 13 nEXP_SPACE 1 -1 -1 6 0 1 3 4 6 7 13 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 319 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 318 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 321 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 4 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 322 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 320 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 315 cpu_est_1_ 3 -1 6 4 0 1 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 4 0 1 3 6 65 -1 3 1 21
+ 303 SM_AMIGA_6_ 3 -1 7 4 0 1 3 7 -1 -1 2 0 21
+ 297 inst_CLK_000_D1 3 -1 3 4 0 1 6 7 -1 -1 1 0 21
+ 305 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 316 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21
+ 302 SM_AMIGA_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 6 3 1 3 6 -1 -1 2 0 21
+ 304 SM_AMIGA_5_ 3 -1 1 3 1 3 6 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 5 0 21
+ 313 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21
+ 306 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 307 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21
+ 298 inst_CLK_000_D3 3 -1 7 2 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 7 2 1 3 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 1 7 -1 -1 8 0 21
+ 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21
+ 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 4 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 322 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 299 inst_DTACK_D0 3 -1 1 1 1 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 6 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 319 7 3 0 3 7 81 -1 4 0 21
+ 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21
+ 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 4 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 303 SM_AMIGA_6_ 3 -1 7 4 0 3 6 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 315 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 302 SM_AMIGA_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 305 inst_CLK_000_D2 3 -1 7 3 0 3 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 306 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 0 2 0 7 -1 -1 8 0 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 1 2 0 1 -1 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_CLK_000_D3 3 -1 7 2 0 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 4 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 304 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21
+ 299 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 96 A_19_ 1 -1 -1 2 0 7 96 -1
+ 95 A_16_ 1 -1 -1 2 0 7 95 -1
+ 94 A_18_ 1 -1 -1 2 0 7 94 -1
+ 58 A_17_ 1 -1 -1 2 0 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 0 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 0 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 0 7 27 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+99 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 325 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 324 3 3 0 6 7 31 -1 7 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 320 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 323 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 329 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 332 3 0 33 -1 4 0 21
+ 65 E 5 330 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 327 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 328 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 331 3 0 34 -1 2 1 21
+ 28 BG_000 5 326 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 327 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 302 SM_AMIGA_6_ 3 -1 6 5 0 1 3 6 7 -1 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 0 5 0 1 3 6 7 -1 -1 1 0 21
+ 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 297 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 21
+ 305 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 10 0 21
+ 309 SM_AMIGA_7_ 3 -1 6 3 3 6 7 -1 -1 5 0 21
+ 315 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21
+ 330 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 306 SM_AMIGA_1_ 3 -1 6 3 0 6 7 -1 -1 3 0 21
+ 304 SM_AMIGA_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21
+ 328 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 307 inst_CLK_000_D2 3 -1 7 3 0 6 7 -1 -1 1 0 21
+ 298 inst_CLK_000_D3 3 -1 7 3 0 6 7 -1 -1 1 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 8 0 21
+ 316 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21
+ 331 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 310 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 303 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 7 2 6 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21
+ 325 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 324 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 332 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 4 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 329 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 317 state_machine_un8_bgack_030_int_n 3 -1 7 1 0 -1 -1 2 0 21
+ 299 inst_DTACK_D0 3 -1 1 1 1 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 7 1 6 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 10 CLK_000 1 -1 -1 4 0 1 3 6 10 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 0 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 319 7 3 0 3 7 81 -1 4 0 21
+ 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21
+ 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 4 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 296 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 303 SM_AMIGA_6_ 3 -1 7 4 0 3 6 7 -1 -1 2 0 21
+ 309 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 5 0 21
+ 315 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 302 SM_AMIGA_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 305 inst_CLK_000_D2 3 -1 7 3 0 3 7 -1 -1 1 0 21
+ 297 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 306 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21
+ 311 inst_AS_030_000_SYNC 3 -1 0 2 0 7 -1 -1 8 0 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 1 2 0 1 -1 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
+ 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 310 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 300 inst_CLK_OUT_PRE_50 3 -1 6 2 1 6 -1 -1 1 0 21
+ 298 inst_CLK_000_D3 3 -1 7 2 0 7 -1 -1 1 0 21
+ 294 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 4 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 304 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21
+ 299 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 295 inst_CLK_OUT_PRE_50_D 3 -1 1 1 1 -1 -1 1 0 21
+ 293 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 96 A_19_ 1 -1 -1 2 0 7 96 -1
+ 95 A_16_ 1 -1 -1 2 0 7 95 -1
+ 94 A_18_ 1 -1 -1 2 0 7 94 -1
+ 58 A_17_ 1 -1 -1 2 0 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 0 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 0 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 0 7 27 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 320 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 4 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21
+ 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 304 SM_AMIGA_6_ 3 -1 0 4 0 3 6 7 -1 -1 2 0 21
+ 307 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 310 SM_AMIGA_7_ 3 -1 0 3 0 3 7 -1 -1 5 0 21
+ 315 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 305 SM_AMIGA_0_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 299 inst_CLK_000_D2 3 -1 7 3 0 3 6 -1 -1 1 0 21
+ 298 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 2 0 7 -1 -1 8 0 21
+ 309 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 313 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 21
+ 303 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 4 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 308 inst_CLK_000_D3 3 -1 6 1 0 -1 -1 1 0 21
+ 300 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 320 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 5 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 4 0 3 6 7 -1 -1 8 0 21
+ 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 304 SM_AMIGA_7_ 3 -1 6 4 0 3 6 7 -1 -1 4 0 21
+ 309 inst_CLK_000_D3 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 308 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 306 SM_AMIGA_0_ 3 -1 0 3 0 3 6 -1 -1 2 0 21
+ 303 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 2 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_6_ 3 -1 0 2 0 1 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 5 0 21
+ 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 300 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 81 AS_030 5 320 7 2 3 7 81 -1 4 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 1 29 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 5 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 7 4 0 3 6 7 -1 -1 8 0 21
+ 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 304 SM_AMIGA_7_ 3 -1 6 4 0 3 6 7 -1 -1 4 0 21
+ 309 inst_CLK_000_D3 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 7 4 0 3 6 7 -1 -1 1 0 21
+ 308 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 306 SM_AMIGA_0_ 3 -1 0 3 0 3 6 -1 -1 2 0 21
+ 303 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 2 0 21
+ 298 inst_CLK_000_D1 3 -1 7 3 1 6 7 -1 -1 1 0 21
+ 315 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 2 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_6_ 3 -1 0 2 0 1 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 5 0 21
+ 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 300 inst_DTACK_D0 3 -1 1 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 2 0 7 63 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 320 7 3 0 3 7 81 -1 4 0 21
+ 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21
+ 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 3 0 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21
+ 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 0 3 0 3 6 -1 -1 8 0 21
+ 315 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21
+ 303 SM_AMIGA_7_ 3 -1 6 3 0 3 6 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 3 1 21
+ 314 cpu_est_0_ 3 -1 6 3 1 3 6 -1 -1 3 0 21
+ 307 SM_AMIGA_2_ 3 -1 1 3 0 1 7 -1 -1 3 0 21
+ 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 309 inst_CLK_000_D3 3 -1 0 3 0 3 6 -1 -1 1 0 21
+ 299 inst_CLK_000_D2 3 -1 7 3 0 3 6 -1 -1 1 0 21
+ 298 inst_CLK_000_D1 3 -1 3 3 1 6 7 -1 -1 1 0 21
+ 308 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 305 SM_AMIGA_0_ 3 -1 7 2 6 7 -1 -1 2 0 21
+ 304 SM_AMIGA_6_ 3 -1 6 2 6 7 -1 -1 2 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21
+ 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21
+ 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 313 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 2 0 21
+ 300 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1
+ 63 CLK_030 1 -1 -1 3 0 6 7 63 -1
+ 96 A_19_ 1 -1 -1 2 0 7 96 -1
+ 95 A_16_ 1 -1 -1 2 0 7 95 -1
+ 94 A_18_ 1 -1 -1 2 0 7 94 -1
+ 58 A_17_ 1 -1 -1 2 0 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 0 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 0 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 0 7 27 -1
+ 10 CLK_000 1 -1 -1 2 3 7 10 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 1 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 318 7 3 2 3 7 81 -1 4 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 7 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21
+ 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 314 cpu_est_0_ 3 -1 2 4 1 2 3 6 -1 -1 3 0 21
+ 298 inst_CLK_000_D1 3 -1 3 4 1 2 6 7 -1 -1 1 0 21
+ 308 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 315 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21
+ 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 3 1 3 6 -1 -1 3 1 21
+ 307 SM_AMIGA_2_ 3 -1 6 3 2 6 7 -1 -1 3 0 21
+ 299 inst_CLK_000_D2 3 -1 7 3 1 2 3 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21
+ 310 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21
+ 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21
+ 313 SM_AMIGA_1_ 3 -1 7 2 0 7 -1 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_0_ 3 -1 0 2 0 1 -1 -1 2 0 21
+ 304 SM_AMIGA_6_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 309 inst_CLK_000_D3 3 -1 2 2 1 2 -1 -1 1 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 300 inst_DTACK_D0 3 -1 7 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
+ 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1
+ 63 CLK_030 1 -1 -1 3 0 2 7 63 -1
+ 96 A_19_ 1 -1 -1 2 2 7 96 -1
+ 95 A_16_ 1 -1 -1 2 2 7 95 -1
+ 94 A_18_ 1 -1 -1 2 2 7 94 -1
+ 58 A_17_ 1 -1 -1 2 2 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 2 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 2 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 2 7 27 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 3 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+98 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21
+ 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21
+ 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21
+ 81 AS_030 5 318 7 3 2 3 7 81 -1 4 0 21
+ 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21
+ 97 DS_030 5 322 0 1 3 97 -1 7 0 21
+ 80 DSACK1 5 328 7 1 3 80 -1 2 0 21
+ 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21
+ 79 RW_000 5 -1 7 1 0 79 -1 1 0 21
+ 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21
+ 68 A0 5 -1 6 1 3 68 -1 1 0 21
+ 29 DTACK 5 -1 3 1 7 29 -1 1 0 21
+ 65 E 5 329 6 0 65 -1 3 1 21
+ 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 326 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 327 7 0 77 -1 2 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
+ 34 VMA 5 330 3 0 34 -1 2 1 21
+ 28 BG_000 5 325 3 0 28 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 21
+ 2 RESET 0 1 0 2 -1 1 0 21
+ 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21
+ 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21
+ 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21
+ 314 cpu_est_0_ 3 -1 2 4 1 2 3 6 -1 -1 3 0 21
+ 298 inst_CLK_000_D1 3 -1 3 4 1 2 6 7 -1 -1 1 0 21
+ 308 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21
+ 315 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21
+ 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21
+ 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21
+ 316 cpu_est_2_ 3 -1 6 3 1 3 6 -1 -1 3 1 21
+ 307 SM_AMIGA_2_ 3 -1 6 3 2 6 7 -1 -1 3 0 21
+ 299 inst_CLK_000_D2 3 -1 7 3 1 2 3 -1 -1 1 0 21
+ 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21
+ 310 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21
+ 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21
+ 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21
+ 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21
+ 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21
+ 313 SM_AMIGA_1_ 3 -1 7 2 0 7 -1 -1 2 0 21
+ 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21
+ 305 SM_AMIGA_0_ 3 -1 0 2 0 1 -1 -1 2 0 21
+ 304 SM_AMIGA_6_ 3 -1 1 2 0 1 -1 -1 2 0 21
+ 309 inst_CLK_000_D3 3 -1 2 2 1 2 -1 -1 1 0 21
+ 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21
+ 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21
+ 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21
+ 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21
+ 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21
+ 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21
+ 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
+ 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21
+ 300 inst_DTACK_D0 3 -1 7 1 6 -1 -1 1 0 21
+ 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21
+ 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 0 60 -1
+ 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
+ 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1
+ 63 CLK_030 1 -1 -1 3 0 2 7 63 -1
+ 96 A_19_ 1 -1 -1 2 2 7 96 -1
+ 95 A_16_ 1 -1 -1 2 2 7 95 -1
+ 94 A_18_ 1 -1 -1 2 2 7 94 -1
+ 58 A_17_ 1 -1 -1 2 2 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 2 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 2 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 2 7 27 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
10 CLK_000 1 -1 -1 1 3 10 -1
5 A_29_ 1 -1 -1 1 4 5 -1
4 A_30_ 1 -1 -1 1 4 4 -1
diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc
index 01e7d8a..8051e4f 100644
--- a/Logic/68030_tk.plc
+++ b/Logic/68030_tk.plc
@@ -8,22 +8,27 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
-; DATE Thu May 29 22:04:32 2014
+; DATE Sun Jun 01 01:03:29 2014
+Pin 17 A_26_
+Pin 18 A_25_
+Pin 19 A_24_
+Pin 84 A_23_
+Pin 4 A_31_
+Pin 85 A_22_
Pin 94 A_21_
Pin 93 A_20_
Pin 97 A_19_
-Pin 95 A_18_
-Pin 4 A_31_
-Pin 59 A_17_
-Pin 96 A_16_
Pin 68 IPL_2_
+Pin 95 A_18_
+Pin 59 A_17_
+Pin 58 FC_1_
+Pin 96 A_16_
+Pin 80 RW_000 Comb ; S6=1 S9=1 Pair 271
Pin 56 IPL_1_
Pin 67 IPL_0_
-Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 284
Pin 57 FC_0_
-Pin 58 FC_1_
Pin 14 nEXP_SPACE
Pin 41 BERR Comb ; S6=1 S9=1 Pair 200
Pin 21 BG_030
@@ -31,13 +36,14 @@ Pin 28 BGACK_000
Pin 64 CLK_030
Pin 11 CLK_000
Pin 61 CLK_OSZI
-Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245
+Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 250
Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 104
-Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149
+Pin 22 AVEC_EXP Reg ; S6=1 S9=1 Pair 149
Pin 36 VPA
Pin 86 RST
-Pin 71 RW
+Pin 71 RW Comb ; S6=1 S9=1 Pair 245
+Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 178
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 199
@@ -45,73 +51,69 @@ Pin 5 A_30_
Pin 6 A_29_
Pin 15 A_28_
Pin 16 A_27_
-Pin 17 A_26_
-Pin 18 A_25_
-Pin 19 A_24_
-Pin 84 A_23_
-Pin 85 A_22_
Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 269
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 128
-Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 134
-Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 131
-Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 286
Pin 82 AS_030 Reg ; S6=1 S9=1 Pair 278
-Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 181
-Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 109
+Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 134
+Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 179
+Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 131
+Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101
Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 182
-Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 187
+Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185
Pin 69 A0 Reg ; S6=0 S9=1 Pair 257
-Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
-Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 277
+Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 176
+Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 10 CLK_EXP Reg ; S6=0 S9=1 Pair 125
-Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 271
+Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 272
+Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 281
Pin 66 E Reg ; S6=1 S9=1 Pair 248
-Pin 35 VMA Reg ; S6=1 S9=1 Pair 178
+Pin 35 VMA Reg ; S6=1 S9=1 Pair 175
Pin 3 RESET Reg ; S6=0 S9=1 Pair 127
-Pin 34 AMIGA_BUS_ENABLE Reg ; S6=1 S9=1 Pair 184
-Pin 70 SIZE_0_ Reg ; S6=0 S9=1 Pair 266
+Pin 70 SIZE_0_ Reg ; S6=0 S9=1 Pair 247
+Node 271 RN_RW_000 Comb ; S6=1 S9=1
Node 173 RN_DTACK Comb ; S6=1 S9=1
+Node 149 RN_AVEC_EXP Reg ; S6=1 S9=1
+Node 245 RN_RW Comb ; S6=1 S9=1
Node 269 RN_SIZE_1_ Reg ; S6=1 S9=1
Node 128 RN_IPL_030_2_ Reg ; S6=1 S9=1
-Node 134 RN_IPL_030_1_ Reg ; S6=1 S9=1
-Node 131 RN_IPL_030_0_ Reg ; S6=1 S9=1
-Node 286 RN_DSACK_1_ Reg ; S6=1 S9=1
Node 278 RN_AS_030 Reg ; S6=1 S9=1
-Node 181 RN_AS_000 Reg ; S6=1 S9=1
-Node 109 RN_DS_030 Reg ; S6=1 S9=1
+Node 134 RN_IPL_030_1_ Reg ; S6=1 S9=1
+Node 179 RN_AS_000 Reg ; S6=1 S9=1
+Node 131 RN_IPL_030_0_ Reg ; S6=1 S9=1
+Node 101 RN_DS_030 Reg ; S6=1 S9=1
Node 182 RN_UDS_000 Reg ; S6=1 S9=1
-Node 187 RN_LDS_000 Reg ; S6=1 S9=1
+Node 185 RN_LDS_000 Reg ; S6=1 S9=1
Node 257 RN_A0 Reg ; S6=0 S9=1
-Node 175 RN_BG_000 Reg ; S6=1 S9=1
-Node 277 RN_BGACK_030 Reg ; S6=1 S9=1
-Node 271 RN_FPU_CS Reg ; S6=1 S9=1
+Node 176 RN_BG_000 Reg ; S6=1 S9=1
+Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
+Node 272 RN_FPU_CS Reg ; S6=1 S9=1
+Node 281 RN_DSACK1 Reg ; S6=1 S9=1
Node 248 RN_E Reg ; S6=1 S9=1
-Node 178 RN_VMA Reg ; S6=1 S9=1
-Node 184 RN_AMIGA_BUS_ENABLE Reg ; S6=1 S9=1
-Node 266 RN_SIZE_0_ Reg ; S6=0 S9=1
-Node 283 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
+Node 175 RN_VMA Reg ; S6=1 S9=1
+Node 247 RN_SIZE_0_ Reg ; S6=0 S9=1
+Node 154 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 188 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
-Node 290 inst_VPA_D Reg ; S6=1 S9=1
-Node 106 inst_CLK_OUT_PRE_50_D Reg ; S6=0 S9=1
-Node 191 inst_CLK_000_D0 Reg ; S6=1 S9=1
-Node 274 inst_CLK_000_D1 Reg ; S6=1 S9=1
-Node 287 inst_CLK_000_D2 Reg ; S6=1 S9=1
-Node 281 inst_CLK_000_D4 Reg ; S6=1 S9=1
-Node 103 inst_DTACK_D0 Reg ; S6=1 S9=1
-Node 247 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
-Node 139 inst_CLK_OUT_PRE_25 Reg ; S6=0 S9=1
-Node 140 SM_AMIGA_1_ Reg ; S6=0 S9=1
-Node 133 SM_AMIGA_0_ Reg ; S6=0 S9=1
-Node 280 SM_AMIGA_6_ Reg ; S6=0 S9=1
-Node 176 SM_AMIGA_5_ Reg ; S6=0 S9=1
-Node 272 inst_CLK_000_D3 Reg ; S6=1 S9=1
-Node 101 inst_CLK_030_H Reg ; S6=1 S9=1
-Node 118 SM_AMIGA_7_ Reg ; S6=1 S9=1
-Node 136 SM_AMIGA_4_ Reg ; S6=0 S9=1
-Node 256 SM_AMIGA_3_ Reg ; S6=1 S9=1
-Node 254 SM_AMIGA_2_ Reg ; S6=1 S9=1
-Node 137 cpu_est_0_ Reg ; S6=0 S9=1
-Node 251 cpu_est_1_ Reg ; S6=1 S9=1
-Node 253 cpu_est_2_ Reg ; S6=1 S9=1
+Node 284 inst_VPA_D Reg ; S6=1 S9=1
+Node 287 inst_CLK_OUT_PRE_50_D Reg ; S6=0 S9=1
+Node 181 inst_CLK_000_D0 Reg ; S6=1 S9=1
+Node 184 inst_CLK_000_D1 Reg ; S6=1 S9=1
+Node 274 inst_CLK_000_D2 Reg ; S6=1 S9=1
+Node 286 inst_DTACK_D0 Reg ; S6=1 S9=1
+Node 283 inst_CLK_OUT_PRE_50 Reg ; S6=0 S9=1
+Node 136 inst_CLK_OUT_PRE_25 Reg ; S6=0 S9=1
+Node 133 SM_AMIGA_7_ Reg ; S6=1 S9=1
+Node 139 SM_AMIGA_6_ Reg ; S6=0 S9=1
+Node 103 SM_AMIGA_0_ Reg ; S6=0 S9=1
+Node 137 SM_AMIGA_5_ Reg ; S6=0 S9=1
+Node 253 SM_AMIGA_2_ Reg ; S6=1 S9=1
+Node 106 inst_RW_000_INT Reg ; S6=1 S9=1
+Node 155 inst_CLK_000_D3 Reg ; S6=1 S9=1
+Node 277 inst_CLK_030_H Reg ; S6=1 S9=1
+Node 187 SM_AMIGA_4_ Reg ; S6=0 S9=1
+Node 254 SM_AMIGA_3_ Reg ; S6=1 S9=1
+Node 280 SM_AMIGA_1_ Reg ; S6=0 S9=1
+Node 152 cpu_est_0_ Reg ; S6=0 S9=1
+Node 130 cpu_est_1_ Reg ; S6=0 S9=1
+Node 251 cpu_est_2_ Reg ; S6=1 S9=1
; Unused Pins & Nodes
; -> None Found.
diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd
index b35846b..eb507f2 100644
--- a/Logic/68030_tk.prd
+++ b/Logic/68030_tk.prd
@@ -5,8 +5,8 @@
|--------------------------------------------|
-Start: Thu May 29 22:04:32 2014
-End : Thu May 29 22:04:32 2014 $$$ Elapsed time: 00:00:00
+Start: Sun Jun 01 01:03:29 2014
+End : Sun Jun 01 01:03:29 2014 $$$ Elapsed time: 00:00:00
===========================================================================
Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
@@ -21,18 +21,18 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030
| | +- Signals to Place | | +----- Logic Array Inputs
| | | +- Placed | | | +- Array Inputs Used
_|____|____|____|_______________|____|_____________|___|________________
- 0 | 16 | 6 | 6 => 100% | 8 | 7 => 87% | 33 | 21 => 63%
- 1 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 21 => 63%
- 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3%
- 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 33 => 100%
+ 0 | 16 | 4 | 4 => 100% | 8 | 7 => 87% | 33 | 17 => 51%
+ 1 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 24 => 72%
+ 2 | 16 | 5 | 5 => 100% | 8 | 8 => 100% | 33 | 22 => 66%
+ 3 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 29 => 87%
4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 17 => 51%
5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0%
- 6 | 16 | 9 | 9 => 100% | 8 | 7 => 87% | 33 | 21 => 63%
- 7 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 28 => 84%
+ 6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 21 => 63%
+ 7 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 27 => 81%
---|----|----|------------|-------|------------|-----|------------------
- | Avg number of array inputs in used blocks : 20.29 => 61%
+ | Avg number of array inputs in used blocks : 22.43 => 67%
-* Input/Clock Signal count: 30 -> placed: 30 = 100%
+* Input/Clock Signal count: 29 -> placed: 29 = 100%
Resources Available Used
-----------------------------------------------------------------
@@ -41,13 +41,13 @@ _|____|____|____|_______________|____|_____________|___|________________
Clock Only Pins : 0 0 => 0%
Clock/Input Pins : 4 4 => 100%
Logic Blocks : 8 7 => 87%
- Macrocells : 128 53 => 41%
- PT Clusters : 128 37 => 28%
+ Macrocells : 128 54 => 42%
+ PT Clusters : 128 39 => 30%
- Single PT Clusters : 128 22 => 17%
Input Registers : 0
* Routing Completion: 100%
-* Attempts: Place [ 7682] Route [ 0]
+* Attempts: Place [ 98] Route [ 0]
===========================================================================
Signal Fanout Table
===========================================================================
@@ -59,19 +59,19 @@ _|____|____|____|_______________|____|_____________|___|________________
___|__|__|____|____________________________________________________________
1| 6| IO| 69|=> ...3|....| A0
2| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR
- 3| 3| IO| 34|=> ....|....| AMIGA_BUS_ENABLE
- |=> Paired w/: RN_AMIGA_BUS_ENABLE
+ 3| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE
4| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW
5| 3| IO| 33|=> 0...|4.67| AS_000
|=> Paired w/: RN_AS_000
- 6| 7| IO| 82|=> ...3|...7| AS_030
+ 6| 7| IO| 82|=> ..23|...7| AS_030
|=> Paired w/: RN_AS_030
7| 0|OUT| 92|=> ....|....| AVEC
- 8| 2|OUT| 22|=> ....|....| AVEC_EXP
- 9| 0|INP| 96|=> ....|...7| A_16_
- 10| 5|INP| 59|=> ....|...7| A_17_
- 11| 0|INP| 95|=> ....|...7| A_18_
- 12| 0|INP| 97|=> ....|...7| A_19_
+ 8| 2| IO| 22|=> ....|....| AVEC_EXP
+ |=> Paired w/: RN_AVEC_EXP
+ 9| 0|INP| 96|=> ..2.|...7| A_16_
+ 10| 5|INP| 59|=> ..2.|...7| A_17_
+ 11| 0|INP| 95|=> ..2.|...7| A_18_
+ 12| 0|INP| 97|=> ..2.|...7| A_19_
13| 0|INP| 93|=> ....|4...| A_20_
14| 0|INP| 94|=> ....|4...| A_21_
15| 7|INP| 85|=> ....|4...| A_22_
@@ -85,7 +85,7 @@ ___|__|__|____|____________________________________________________________
23| 1|INP| 5|=> ....|4...| A_30_
24| 1|INP| 4|=> ....|4...| A_31_
25| 4|OUT| 41|=> ....|....| BERR
- 26| 3|INP| 28|=> ....|...7| BGACK_000
+ 26| 3|INP| 28|=> ..2.|...7| BGACK_000
27| 7| IO| 83|=> ....|....| BGACK_030
|=> Paired w/: RN_BGACK_030
28| 3| IO| 29|=> ....|....| BG_000
@@ -93,98 +93,98 @@ ___|__|__|____|____________________________________________________________
29| 2|INP| 21|=> ...3|....| BG_030
30| 4|OUT| 47|=> ....|....| CIIN
31| +|INP| 11|=> ...3|....| CLK_000
- 32| +|INP| 64|=> 0...|...7| CLK_030
+ 32| +|INP| 64|=> 0.2.|...7| CLK_030
33| 6|OUT| 65|=> ....|....| CLK_DIV_OUT
34| 1|OUT| 10|=> ....|....| CLK_EXP
35| +|Cin| 61|=> ....|....| CLK_OSZI
- 36| 7|OUT| 80|=> ....|....| DSACK_0_
- 37| 7| IO| 81|=> ...3|....| DSACK_1_
- |=> Paired w/: RN_DSACK_1_
- 38| 0| IO| 98|=> ...3|....| DS_030
+ 36| 7| IO| 81|=> ...3|....| DSACK1
+ |=> Paired w/: RN_DSACK1
+ 37| 0| IO| 98|=> ...3|....| DS_030
|=> Paired w/: RN_DS_030
- 39| 3| IO| 30|=> 0...|....| DTACK
- 40| 6| IO| 66|=> ....|....| E
+ 38| 3| IO| 30|=> ....|...7| DTACK
+ 39| 6| IO| 66|=> ....|....| E
|=> Paired w/: RN_E
- 41| 5|INP| 57|=> ....|...7| FC_0_
- 42| 5|INP| 58|=> ....|...7| FC_1_
- 43| 7| IO| 78|=> ....|....| FPU_CS
+ 40| 5|INP| 57|=> ..2.|...7| FC_0_
+ 41| 5|INP| 58|=> ..2.|...7| FC_1_
+ 42| 7| IO| 78|=> ....|....| FPU_CS
|=> Paired w/: RN_FPU_CS
- 44| 1| IO| 8|=> ....|....| IPL_030_0_
+ 43| 1| IO| 8|=> ....|....| IPL_030_0_
|=> Paired w/: RN_IPL_030_0_
- 45| 1| IO| 7|=> ....|....| IPL_030_1_
+ 44| 1| IO| 7|=> ....|....| IPL_030_1_
|=> Paired w/: RN_IPL_030_1_
- 46| 1| IO| 9|=> ....|....| IPL_030_2_
+ 45| 1| IO| 9|=> ....|....| IPL_030_2_
|=> Paired w/: RN_IPL_030_2_
- 47| 6|INP| 67|=> .1..|....| IPL_0_
- 48| 5|INP| 56|=> .1..|....| IPL_1_
- 49| 6|INP| 68|=> .1..|....| IPL_2_
- 50| 3| IO| 31|=> 0...|..67| LDS_000
+ 46| 6|INP| 67|=> .1..|....| IPL_0_
+ 47| 5|INP| 56|=> .1..|....| IPL_1_
+ 48| 6|INP| 68|=> .1..|....| IPL_2_
+ 49| 3| IO| 31|=> 0...|..67| LDS_000
|=> Paired w/: RN_LDS_000
- 51| 1|OUT| 3|=> ....|....| RESET
- 52| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE
- |=> Paired w/: AMIGA_BUS_ENABLE
- 53| 3|NOD| . |=> 01.3|....| RN_AS_000
+ 50| 1|OUT| 3|=> ....|....| RESET
+ 51| 3|NOD| . |=> ...3|....| RN_AS_000
|=> Paired w/: AS_000
- 54| 7|NOD| . |=> 0..3|..67| RN_AS_030
+ 52| 7|NOD| . |=> 0..3|..67| RN_AS_030
|=> Paired w/: AS_030
- 55| 7|NOD| . |=> 0..3|4.67| RN_BGACK_030
+ 53| 2|NOD| . |=> ..23|....| RN_AVEC_EXP
+ |=> Paired w/: AVEC_EXP
+ 54| 7|NOD| . |=> 0.23|4.67| RN_BGACK_030
|=> Paired w/: BGACK_030
- 56| 3|NOD| . |=> ...3|....| RN_BG_000
+ 55| 3|NOD| . |=> ...3|....| RN_BG_000
|=> Paired w/: BG_000
- 57| 7|NOD| . |=> ....|...7| RN_DSACK_1_
- |=> Paired w/: DSACK_1_
- 58| 0|NOD| . |=> 0...|....| RN_DS_030
+ 56| 7|NOD| . |=> ....|...7| RN_DSACK1
+ |=> Paired w/: DSACK1
+ 57| 0|NOD| . |=> 0...|....| RN_DS_030
|=> Paired w/: DS_030
- 59| 6|NOD| . |=> ...3|..6.| RN_E
+ 58| 6|NOD| . |=> .1.3|..6.| RN_E
|=> Paired w/: E
- 60| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS
+ 59| 7|NOD| . |=> ....|4..7| RN_FPU_CS
|=> Paired w/: FPU_CS
- 61| 1|NOD| . |=> .1..|....| RN_IPL_030_0_
+ 60| 1|NOD| . |=> .1..|....| RN_IPL_030_0_
|=> Paired w/: IPL_030_0_
- 62| 1|NOD| . |=> .1..|....| RN_IPL_030_1_
+ 61| 1|NOD| . |=> .1..|....| RN_IPL_030_1_
|=> Paired w/: IPL_030_1_
- 63| 1|NOD| . |=> .1..|....| RN_IPL_030_2_
+ 62| 1|NOD| . |=> .1..|....| RN_IPL_030_2_
|=> Paired w/: IPL_030_2_
- 64| 3|NOD| . |=> ...3|....| RN_LDS_000
+ 63| 3|NOD| . |=> ...3|....| RN_LDS_000
|=> Paired w/: LDS_000
- 65| 3|NOD| . |=> ...3|....| RN_UDS_000
+ 64| 3|NOD| . |=> ...3|....| RN_UDS_000
|=> Paired w/: UDS_000
- 66| 3|NOD| . |=> ...3|..6.| RN_VMA
+ 65| 3|NOD| . |=> ...3|..6.| RN_VMA
|=> Paired w/: VMA
- 67| +|INP| 86|=> 01.3|..67| RST
- 68| 6|INP| 71|=> 0..3|4...| RW
+ 66| +|INP| 86|=> 0123|..67| RST
+ 67| 6| IO| 71|=> 0..3|4...| RW
+ 68| 7| IO| 80|=> 0...|....| RW_000
69| 6| IO| 70|=> ...3|....| SIZE_0_
70| 7| IO| 79|=> ...3|....| SIZE_1_
- 71| 1|NOD| . |=> 01.3|....| SM_AMIGA_0_
- 72| 1|NOD| . |=> .1.3|...7| SM_AMIGA_1_
- 73| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_
+ 71| 0|NOD| . |=> 01..|....| SM_AMIGA_0_
+ 72| 7|NOD| . |=> 0...|...7| SM_AMIGA_1_
+ 73| 6|NOD| . |=> ..2.|..67| SM_AMIGA_2_
74| 6|NOD| . |=> ....|..6.| SM_AMIGA_3_
- 75| 1|NOD| . |=> .1.3|..6.| SM_AMIGA_4_
- 76| 3|NOD| . |=> .1.3|....| SM_AMIGA_5_
- 77| 7|NOD| . |=> 0..3|...7| SM_AMIGA_6_
- 78| 0|NOD| . |=> 0..3|...7| SM_AMIGA_7_
+ 75| 3|NOD| . |=> ...3|..6.| SM_AMIGA_4_
+ 76| 1|NOD| . |=> .1.3|....| SM_AMIGA_5_
+ 77| 1|NOD| . |=> 01..|....| SM_AMIGA_6_
+ 78| 1|NOD| . |=> .123|....| SM_AMIGA_7_
79| 3| IO| 32|=> 0...|..67| UDS_000
|=> Paired w/: RN_UDS_000
80| 3| IO| 35|=> ....|....| VMA
|=> Paired w/: RN_VMA
81| +|INP| 36|=> ....|...7| VPA
- 82| 1|NOD| . |=> .1.3|..6.| cpu_est_0_
- 83| 6|NOD| . |=> ...3|..6.| cpu_est_1_
- 84| 6|NOD| . |=> ...3|..6.| cpu_est_2_
- 85| 7|NOD| . |=> 0...|...7| inst_AS_030_000_SYNC
- 86| 3|NOD| . |=> ...3|....| inst_BGACK_030_INT_D
- 87| 3|NOD| . |=> 01.3|..67| inst_CLK_000_D0
- 88| 7|NOD| . |=> .1..|..67| inst_CLK_000_D1
- 89| 7|NOD| . |=> 0...|...7| inst_CLK_000_D2
- 90| 7|NOD| . |=> 01..|...7| inst_CLK_000_D3
- 91| 7|NOD| . |=> .1.3|...7| inst_CLK_000_D4
- 92| 0|NOD| . |=> 0...|....| inst_CLK_030_H
- 93| 1|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_25
- 94| 6|NOD| . |=> 01..|..6.| inst_CLK_OUT_PRE_50
- 95| 0|NOD| . |=> .1..|....| inst_CLK_OUT_PRE_50_D
- 96| 0|NOD| . |=> ....|..6.| inst_DTACK_D0
+ 82| 2|NOD| . |=> .123|..6.| cpu_est_0_
+ 83| 1|NOD| . |=> .1.3|..6.| cpu_est_1_
+ 84| 6|NOD| . |=> .1.3|..6.| cpu_est_2_
+ 85| 2|NOD| . |=> .12.|....| inst_AS_030_000_SYNC
+ 86| 3|NOD| . |=> ..2.|....| inst_BGACK_030_INT_D
+ 87| 3|NOD| . |=> 0123|..67| inst_CLK_000_D0
+ 88| 3|NOD| . |=> .12.|..67| inst_CLK_000_D1
+ 89| 7|NOD| . |=> .123|....| inst_CLK_000_D2
+ 90| 2|NOD| . |=> .12.|....| inst_CLK_000_D3
+ 91| 7|NOD| . |=> 0...|...7| inst_CLK_030_H
+ 92| 1|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_25
+ 93| 7|NOD| . |=> .1..|...7| inst_CLK_OUT_PRE_50
+ 94| 7|NOD| . |=> .1..|....| inst_CLK_OUT_PRE_50_D
+ 95| 7|NOD| . |=> ....|..6.| inst_DTACK_D0
+ 96| 0|NOD| . |=> 0...|..67| inst_RW_000_INT
97| 7|NOD| . |=> ...3|..6.| inst_VPA_D
- 98| +|INP| 14|=> 0..3|4.67| nEXP_SPACE
+ 98| +|INP| 14|=> 0123|4.67| nEXP_SPACE
---------------------------------------------------------------------------
===========================================================================
< C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments >
@@ -272,8 +272,8 @@ ____|_____|_________|______________________________________________________
77 | GND | | | (pwr/test)
78 | I_O | 7_07|*| FPU_CS
79 | I_O | 7_06|*| SIZE_1_
- 80 | I_O | 7_05|*| DSACK_0_
- 81 | I_O | 7_04|*| DSACK_1_
+ 80 | I_O | 7_05|*| RW_000
+ 81 | I_O | 7_04|*| DSACK1
82 | I_O | 7_03|*| AS_030
83 | I_O | 7_02|*| BGACK_030
84 | I_O | 7_01|*| A_23_
@@ -304,18 +304,18 @@ ____|_____|_________|______________________________________________________
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
- 0|inst_CLK_030_H|NOD| | S | 5 | 4 to [ 0]| 1 XOR to [ 0] as logic PT
- 1| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
- 2| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig
- 3|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig
- 4| | ? | | S | | 4 free | 1 XOR free
- 5| DS_030| IO| | S | 7 | 4 to [ 5]| 1 XOR to [ 5] as logic PT
+ 0| DS_030| IO| | S | 7 | 4 to [ 0]| 1 XOR to [ 0] as logic PT
+ 1| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 1]| 1 XOR free
+ 2| AVEC|OUT| | S | 1 | 4 to [ 0]| 1 XOR to [ 2] for 1 PT sig
+ 3|inst_RW_000_INT|NOD| | S |14 | 4 to [ 3]| 1 XOR to [ 3] as logic PT
+ 4| | ? | | S | | 4 to [ 3]| 1 XOR to [ 3] as logic PT
+ 5| | ? | | S | | 4 to [ 3]| 1 XOR free
6| | ? | | S | | 4 free | 1 XOR free
- 7| | ? | | S | | 4 to [ 5]| 1 XOR free
+ 7| | ? | | S | | 4 free | 1 XOR free
8| | ? | | S | | 4 free | 1 XOR free
9| | ? | | S | | 4 free | 1 XOR free
10| | ? | | S | | 4 free | 1 XOR free
-11| SM_AMIGA_7_|NOD| | S | 5 | 4 to [11]| 1 XOR to [11] as logic PT
+11| | ? | | S | | 4 free | 1 XOR free
12| | ? | | S | | 4 free | 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
@@ -331,19 +331,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
- 0|inst_CLK_030_H|NOD| | S | 5 |=> can support up to [ 13] logic PT(s)
- 1| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 13] logic PT(s)
- 2| AVEC|OUT| | S | 1 |=> can support up to [ 18] logic PT(s)
- 3|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s)
- 4| | ? | | S | |=> can support up to [ 14] logic PT(s)
- 5| DS_030| IO| | S | 7 |=> can support up to [ 20] logic PT(s)
- 6| | ? | | S | |=> can support up to [ 10] logic PT(s)
- 7| | ? | | S | |=> can support up to [ 16] logic PT(s)
- 8| | ? | | S | |=> can support up to [ 15] logic PT(s)
- 9| | ? | | S | |=> can support up to [ 15] logic PT(s)
-10| | ? | | S | |=> can support up to [ 15] logic PT(s)
-11| SM_AMIGA_7_|NOD| | S | 5 |=> can support up to [ 20] logic PT(s)
-12| | ? | | S | |=> can support up to [ 15] logic PT(s)
+ 0| DS_030| IO| | S | 7 |=> can support up to [ 9] logic PT(s)
+ 1| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s)
+ 2| AVEC|OUT| | S | 1 |=> can support up to [ 1] logic PT(s)
+ 3|inst_RW_000_INT|NOD| | S |14 |=> can support up to [ 15] logic PT(s)
+ 4| | ? | | S | |=> can support up to [ 5] logic PT(s)
+ 5| | ? | | S | |=> can support up to [ 11] logic PT(s)
+ 6| | ? | | S | |=> can support up to [ 15] logic PT(s)
+ 7| | ? | | S | |=> can support up to [ 20] logic PT(s)
+ 8| | ? | | S | |=> can support up to [ 20] logic PT(s)
+ 9| | ? | | S | |=> can support up to [ 20] logic PT(s)
+10| | ? | | S | |=> can support up to [ 20] logic PT(s)
+11| | ? | | S | |=> can support up to [ 20] logic PT(s)
+12| | ? | | S | |=> can support up to [ 20] logic PT(s)
13| | ? | | S | |=> can support up to [ 20] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
@@ -356,18 +356,18 @@ _|_________________|__|__|___|_____|_______________________________________
| Sig Type---+ | to | Block [ 0] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
- 0|inst_CLK_030_H|NOD| | => | 5 6 7 0 | 96 97 98 91
- 1| inst_DTACK_D0|NOD| | => | 5 6 7 0 | 96 97 98 91
+ 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91
+ 1| SM_AMIGA_0_|NOD| | => | 5 6 7 0 | 96 97 98 91
2| AVEC|OUT| | => | 6 7 0 ( 1)| 97 98 91 ( 92)
- 3|inst_CLK_OUT_PRE_50_D|NOD| | => | 6 7 0 1 | 97 98 91 92
+ 3|inst_RW_000_INT|NOD| | => | 6 7 0 1 | 97 98 91 92
4| | | | => | 7 0 1 2 | 98 91 92 93
- 5| DS_030| IO| | => |( 7) 0 1 2 |( 98) 91 92 93
+ 5| | | | => | 7 0 1 2 | 98 91 92 93
6| | | | => | 0 1 2 3 | 91 92 93 94
7| | | | => | 0 1 2 3 | 91 92 93 94
8| | | | => | 1 2 3 4 | 92 93 94 95
9| | | | => | 1 2 3 4 | 92 93 94 95
10| | | | => | 2 3 4 5 | 93 94 95 96
-11| SM_AMIGA_7_|NOD| | => | 2 3 4 5 | 93 94 95 96
+11| | | | => | 2 3 4 5 | 93 94 95 96
12| | | | => | 3 4 5 6 | 94 95 96 97
13| | | | => | 3 4 5 6 | 94 95 96 97
14| | | | => | 4 5 6 7 | 95 96 97 98
@@ -389,7 +389,7 @@ _|_________________|__|___|_____|___________________________________________
4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15
5| A_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1
6| A_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3
- 7| DS_030| IO|*| 98| => | 14 15 0 1 2 3 4 ( 5)
+ 7| DS_030| IO|*| 98| => | 14 15 ( 0) 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table
@@ -421,18 +421,18 @@ IMX No. | +---- Block IO Pin or Macrocell Number
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 91| -| | ]
[RegIn 0 |102| -| | ]
- [MCell 0 |101|NOD inst_CLK_030_H| |*]
- [MCell 1 |103|NOD inst_DTACK_D0| |*]
+ [MCell 0 |101|NOD RN_DS_030| |*] paired w/[ DS_030]
+ [MCell 1 |103|NOD SM_AMIGA_0_| |*]
1 [IOpin 1 | 92|OUT AVEC|*| ]
[RegIn 1 |105| -| | ]
[MCell 2 |104|OUT AVEC| | ]
- [MCell 3 |106|NOD inst_CLK_OUT_PRE_50_D| |*]
+ [MCell 3 |106|NOD inst_RW_000_INT| |*]
2 [IOpin 2 | 93|INP A_20_|*|*]
[RegIn 2 |108| -| | ]
[MCell 4 |107| -| | ]
- [MCell 5 |109|NOD RN_DS_030| |*] paired w/[ DS_030]
+ [MCell 5 |109| -| | ]
3 [IOpin 3 | 94|INP A_21_|*|*]
[RegIn 3 |111| -| | ]
@@ -447,7 +447,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
5 [IOpin 5 | 96|INP A_16_|*|*]
[RegIn 5 |117| -| | ]
[MCell 10 |116| -| | ]
- [MCell 11 |118|NOD SM_AMIGA_7_| |*]
+ [MCell 11 |118| -| | ]
6 [IOpin 6 | 97|INP A_19_|*|*]
[RegIn 6 |120| -| | ]
@@ -465,36 +465,36 @@ IMX No. | +---- Block IO Pin or Macrocell Number
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
-Mux00| IOPin 3 4 ( 31)| LDS_000
+Mux00| Input Pin ( 86)| RST
Mux01| ... | ...
-Mux02| Mcel 0 5 ( 109)| RN_DS_030
+Mux02| ... | ...
Mux03| ... | ...
-Mux04| Mcel 0 0 ( 101)| inst_CLK_030_H
-Mux05| Mcel 7 9 ( 283)| inst_AS_030_000_SYNC
-Mux06| ... | ...
-Mux07| Mcel 7 6 ( 278)| RN_AS_030
-Mux08| Mcel 7 12 ( 287)| inst_CLK_000_D2
-Mux09| IOPin 3 5 ( 30)| DTACK
+Mux04| Input Pin ( 64)| CLK_030
+Mux05| Input Pin ( 14)| nEXP_SPACE
+Mux06| Mcel 1 9 ( 139)| SM_AMIGA_6_
+Mux07| Mcel 7 7 ( 280)| SM_AMIGA_1_
+Mux08| IOPin 6 6 ( 71)| RW
+Mux09| Mcel 0 1 ( 103)| SM_AMIGA_0_
Mux10| ... | ...
-Mux11| Mcel 3 5 ( 181)| RN_AS_000
+Mux11| Mcel 3 5 ( 181)| inst_CLK_000_D0
Mux12| IOPin 3 3 ( 32)| UDS_000
-Mux13| Mcel 0 11 ( 118)| SM_AMIGA_7_
-Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D3
-Mux15| Input Pin ( 14)| nEXP_SPACE
+Mux13| Mcel 7 5 ( 277)| inst_CLK_030_H
+Mux14| ... | ...
+Mux15| Mcel 0 0 ( 101)| RN_DS_030
Mux16| ... | ...
-Mux17| Mcel 3 12 ( 191)| inst_CLK_000_D0
+Mux17| ... | ...
Mux18| ... | ...
Mux19| ... | ...
-Mux20| Input Pin ( 64)| CLK_030
-Mux21| Input Pin ( 86)| RST
+Mux20| Mcel 7 4 ( 275)| RN_BGACK_030
+Mux21| Mcel 7 6 ( 278)| RN_AS_030
Mux22| ... | ...
Mux23| IOPin 3 2 ( 33)| AS_000
-Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE_50
-Mux25| IOPin 6 6 ( 71)| RW
+Mux24| IOPin 3 4 ( 31)| LDS_000
+Mux25| Mcel 0 3 ( 106)| inst_RW_000_INT
Mux26| ... | ...
-Mux27| Mcel 7 5 ( 277)| RN_BGACK_030
-Mux28| Mcel 1 5 ( 133)| SM_AMIGA_0_
-Mux29| Mcel 7 7 ( 280)| SM_AMIGA_6_
+Mux27| ... | ...
+Mux28| IOPin 7 5 ( 80)| RW_000
+Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
Mux32| ... | ...
@@ -512,14 +512,14 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
0| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
1| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
2| IPL_030_2_| IO| | S | 3 | 4 to [ 2]| 1 XOR free
- 3| | ? | | S | | 4 free | 1 XOR free
+ 3| cpu_est_1_|NOD| | S | 4 | 4 to [ 3]| 1 XOR free
4| IPL_030_0_| IO| | S | 3 | 4 to [ 4]| 1 XOR free
- 5| SM_AMIGA_0_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free
+ 5| SM_AMIGA_7_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free
6| IPL_030_1_| IO| | S | 3 | 4 to [ 6]| 1 XOR free
- 7| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 7]| 1 XOR free
- 8| cpu_est_0_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free
- 9|inst_CLK_OUT_PRE_25|NOD| | S | 3 | 4 to [ 9]| 1 XOR free
-10| SM_AMIGA_1_|NOD| | S | 3 | 4 to [10]| 1 XOR free
+ 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 | 4 to [ 7]| 1 XOR free
+ 8| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 8]| 1 XOR free
+ 9| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free
+10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| | ? | | S | | 4 free | 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
@@ -537,17 +537,17 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s)
- 1| RESET|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
- 2| IPL_030_2_| IO| | S | 3 |=> can support up to [ 14] logic PT(s)
- 3| | ? | | S | |=> can support up to [ 5] logic PT(s)
- 4| IPL_030_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s)
- 5| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s)
+ 1| RESET|OUT| | S | 1 |=> can support up to [ 9] logic PT(s)
+ 2| IPL_030_2_| IO| | S | 3 |=> can support up to [ 9] logic PT(s)
+ 3| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s)
+ 4| IPL_030_0_| IO| | S | 3 |=> can support up to [ 5] logic PT(s)
+ 5| SM_AMIGA_7_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s)
6| IPL_030_1_| IO| | S | 3 |=> can support up to [ 5] logic PT(s)
- 7| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s)
- 8| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s)
- 9|inst_CLK_OUT_PRE_25|NOD| | S | 3 |=> can support up to [ 10] logic PT(s)
-10| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s)
-11| | ? | | S | |=> can support up to [ 15] logic PT(s)
+ 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 |=> can support up to [ 5] logic PT(s)
+ 8| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s)
+ 9| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s)
+10| | ? | | S | |=> can support up to [ 15] logic PT(s)
+11| | ? | | S | |=> can support up to [ 20] logic PT(s)
12| | ? | | S | |=> can support up to [ 20] logic PT(s)
13| | ? | | S | |=> can support up to [ 20] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
@@ -564,14 +564,14 @@ _|_________________|__|_____|____________________|________________________
0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10)
1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10
2| IPL_030_2_| IO| | => | 6 7 0 ( 1)| 4 3 10 ( 9)
- 3| | | | => | 6 7 0 1 | 4 3 10 9
+ 3| cpu_est_1_|NOD| | => | 6 7 0 1 | 4 3 10 9
4| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8)
- 5| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 3 10 9 8
+ 5| SM_AMIGA_7_|NOD| | => | 7 0 1 2 | 3 10 9 8
6| IPL_030_1_| IO| | => | 0 1 2 ( 3)| 10 9 8 ( 7)
- 7| SM_AMIGA_4_|NOD| | => | 0 1 2 3 | 10 9 8 7
- 8| cpu_est_0_|NOD| | => | 1 2 3 4 | 9 8 7 6
- 9|inst_CLK_OUT_PRE_25|NOD| | => | 1 2 3 4 | 9 8 7 6
-10| SM_AMIGA_1_|NOD| | => | 2 3 4 5 | 8 7 6 5
+ 7|inst_CLK_OUT_PRE_25|NOD| | => | 0 1 2 3 | 10 9 8 7
+ 8| SM_AMIGA_5_|NOD| | => | 1 2 3 4 | 9 8 7 6
+ 9| SM_AMIGA_6_|NOD| | => | 1 2 3 4 | 9 8 7 6
+10| | | | => | 2 3 4 5 | 8 7 6 5
11| | | | => | 2 3 4 5 | 8 7 6 5
12| | | | => | 3 4 5 6 | 7 6 5 4
13| | | | => | 3 4 5 6 | 7 6 5 4
@@ -634,26 +634,26 @@ IMX No. | +---- Block IO Pin or Macrocell Number
1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_]
[RegIn 1 |129| -| | ]
[MCell 2 |128|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_]
- [MCell 3 |130| -| | ]
+ [MCell 3 |130|NOD cpu_est_1_| |*]
2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_]
[RegIn 2 |132| -| | ]
[MCell 4 |131|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_]
- [MCell 5 |133|NOD SM_AMIGA_0_| |*]
+ [MCell 5 |133|NOD SM_AMIGA_7_| |*]
3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_]
[RegIn 3 |135| -| | ]
[MCell 6 |134|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_]
- [MCell 7 |136|NOD SM_AMIGA_4_| |*]
+ [MCell 7 |136|NOD inst_CLK_OUT_PRE_25| |*]
4 [IOpin 4 | 6|INP A_29_|*|*]
[RegIn 4 |138| -| | ]
- [MCell 8 |137|NOD cpu_est_0_| |*]
- [MCell 9 |139|NOD inst_CLK_OUT_PRE_25| |*]
+ [MCell 8 |137|NOD SM_AMIGA_5_| |*]
+ [MCell 9 |139|NOD SM_AMIGA_6_| |*]
5 [IOpin 5 | 5|INP A_30_|*|*]
[RegIn 5 |141| -| | ]
- [MCell 10 |140|NOD SM_AMIGA_1_| |*]
+ [MCell 10 |140| -| | ]
[MCell 11 |142| -| | ]
6 [IOpin 6 | 4|INP A_31_|*|*]
@@ -672,38 +672,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
-Mux00| IOPin 6 2 ( 67)| IPL_0_
-Mux01| Mcel 1 7 ( 136)| SM_AMIGA_4_
+Mux00| Input Pin ( 86)| RST
+Mux01| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25
Mux02| Mcel 1 6 ( 134)| RN_IPL_030_1_
Mux03| IOPin 5 4 ( 56)| IPL_1_
Mux04| IOPin 6 3 ( 68)| IPL_2_
-Mux05| Mcel 6 6 ( 254)| SM_AMIGA_2_
-Mux06| Mcel 0 3 ( 106)| inst_CLK_OUT_PRE_50_D
-Mux07| Mcel 3 5 ( 181)| RN_AS_000
-Mux08| Mcel 1 8 ( 137)| cpu_est_0_
-Mux09| ... | ...
+Mux05| Input Pin ( 14)| nEXP_SPACE
+Mux06| Mcel 1 9 ( 139)| SM_AMIGA_6_
+Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D0
+Mux08| Mcel 3 7 ( 184)| inst_CLK_000_D1
+Mux09| Mcel 0 1 ( 103)| SM_AMIGA_0_
Mux10| Mcel 1 2 ( 128)| RN_IPL_030_2_
-Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D1
-Mux12| Mcel 1 10 ( 140)| SM_AMIGA_1_
-Mux13| Mcel 7 8 ( 281)| inst_CLK_000_D4
-Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D3
-Mux15| ... | ...
-Mux16| Mcel 3 2 ( 176)| SM_AMIGA_5_
-Mux17| Mcel 3 12 ( 191)| inst_CLK_000_D0
-Mux18| ... | ...
+Mux11| Mcel 7 9 ( 283)| inst_CLK_OUT_PRE_50
+Mux12| Mcel 2 3 ( 154)| inst_AS_030_000_SYNC
+Mux13| Mcel 1 3 ( 130)| cpu_est_1_
+Mux14| Mcel 2 4 ( 155)| inst_CLK_000_D3
+Mux15| Mcel 7 12 ( 287)| inst_CLK_OUT_PRE_50_D
+Mux16| IOPin 6 2 ( 67)| IPL_0_
+Mux17| Mcel 1 8 ( 137)| SM_AMIGA_5_
+Mux18| Mcel 7 3 ( 274)| inst_CLK_000_D2
Mux19| ... | ...
Mux20| ... | ...
-Mux21| Input Pin ( 86)| RST
-Mux22| ... | ...
-Mux23| ... | ...
-Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE_50
+Mux21| Mcel 6 4 ( 251)| cpu_est_2_
+Mux22| Mcel 2 2 ( 152)| cpu_est_0_
+Mux23| Mcel 6 2 ( 248)| RN_E
+Mux24| ... | ...
Mux25| ... | ...
Mux26| ... | ...
Mux27| Mcel 1 4 ( 131)| RN_IPL_030_0_
-Mux28| Mcel 1 5 ( 133)| SM_AMIGA_0_
+Mux28| Mcel 1 5 ( 133)| SM_AMIGA_7_
Mux29| ... | ...
Mux30| ... | ...
-Mux31| Mcel 1 9 ( 139)| inst_CLK_OUT_PRE_25
+Mux31| ... | ...
Mux32| ... | ...
---------------------------------------------------------------------------
===========================================================================
@@ -716,11 +716,11 @@ Mux32| ... | ...
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
- 0| AVEC_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
+ 0| AVEC_EXP| IO| | S | 3 | 4 to [ 0]| 1 XOR free
1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
- 2| | ? | | S | | 4 free | 1 XOR free
- 3| | ? | | S | | 4 free | 1 XOR free
- 4| | ? | | S | | 4 free | 1 XOR free
+ 2| cpu_est_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free
+ 3|inst_AS_030_000_SYNC|NOD| | S | 8 | 4 to [ 3]| 1 XOR to [ 3] as logic PT
+ 4|inst_CLK_000_D3|NOD| | S | 1 | 4 to [ 3]| 1 XOR to [ 4] for 1 PT sig
5| | ? | | S | | 4 free | 1 XOR free
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
@@ -743,12 +743,12 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
- 0| AVEC_EXP|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
- 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 19] logic PT(s)
- 2| | ? | | S | |=> can support up to [ 19] logic PT(s)
- 3| | ? | | S | |=> can support up to [ 20] logic PT(s)
- 4| | ? | | S | |=> can support up to [ 20] logic PT(s)
- 5| | ? | | S | |=> can support up to [ 20] logic PT(s)
+ 0| AVEC_EXP| IO| | S | 3 |=> can support up to [ 9] logic PT(s)
+ 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 5] logic PT(s)
+ 2| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s)
+ 3|inst_AS_030_000_SYNC|NOD| | S | 8 |=> can support up to [ 14] logic PT(s)
+ 4|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 11] logic PT(s)
+ 5| | ? | | S | |=> can support up to [ 15] logic PT(s)
6| | ? | | S | |=> can support up to [ 20] logic PT(s)
7| | ? | | S | |=> can support up to [ 20] logic PT(s)
8| | ? | | S | |=> can support up to [ 20] logic PT(s)
@@ -768,11 +768,11 @@ _|_________________|__|__|___|_____|_______________________________________
| Sig Type---+ | to | Block [ 2] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
- 0| AVEC_EXP|OUT| | => | 5 6 ( 7) 0 | 20 21 ( 22) 15
+ 0| AVEC_EXP| IO| | => | 5 6 ( 7) 0 | 20 21 ( 22) 15
1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15
- 2| | | | => | 6 7 0 1 | 21 22 15 16
- 3| | | | => | 6 7 0 1 | 21 22 15 16
- 4| | | | => | 7 0 1 2 | 22 15 16 17
+ 2| cpu_est_0_|NOD| | => | 6 7 0 1 | 21 22 15 16
+ 3|inst_AS_030_000_SYNC|NOD| | => | 6 7 0 1 | 21 22 15 16
+ 4|inst_CLK_000_D3|NOD| | => | 7 0 1 2 | 22 15 16 17
5| | | | => | 7 0 1 2 | 22 15 16 17
6| | | | => | 0 1 2 3 | 15 16 17 18
7| | | | => | 0 1 2 3 | 15 16 17 18
@@ -801,7 +801,7 @@ _|_________________|__|___|_____|___________________________________________
4| A_24_|INP|*| 19| => | 8 9 10 11 12 13 14 15
5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 0 ( 1)
6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3
- 7| AVEC_EXP|OUT|*| 22| => | 14 15 ( 0) 1 2 3 4 5
+ 7| AVEC_EXP| IO|*| 22| => | 14 15 ( 0) 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table
@@ -819,7 +819,8 @@ _|_________________|__|___|_____|__________________________________________
4| A_24_|INP|*| 19| => | Input macrocell [ -]
5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -]
6| BG_030|INP|*| 21| => | Input macrocell [ -]
- 7| AVEC_EXP|OUT|*| 22| => | Input macrocell [ -]
+ 7| AVEC_EXP| IO|*| 22| => | Input macrocell [ -]
+ | | | | | | IO paired w/ node [ RN_AVEC_EXP]
---------------------------------------------------------------------------
===========================================================================
< Block [ 2] > Input Multiplexer (IMX) Assignments
@@ -832,17 +833,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 15|INP A_28_|*|*]
[RegIn 0 |150| -| | ]
- [MCell 0 |149|OUT AVEC_EXP| | ]
+ [MCell 0 |149|NOD RN_AVEC_EXP| |*] paired w/[ AVEC_EXP]
[MCell 1 |151|OUT AMIGA_BUS_ENABLE_LOW| | ]
1 [IOpin 1 | 16|INP A_27_|*|*]
[RegIn 1 |153| -| | ]
- [MCell 2 |152| -| | ]
- [MCell 3 |154| -| | ]
+ [MCell 2 |152|NOD cpu_est_0_| |*]
+ [MCell 3 |154|NOD inst_AS_030_000_SYNC| |*]
2 [IOpin 2 | 17|INP A_26_|*|*]
[RegIn 2 |156| -| | ]
- [MCell 4 |155| -| | ]
+ [MCell 4 |155|NOD inst_CLK_000_D3| |*]
[MCell 5 |157| -| | ]
3 [IOpin 3 | 18|INP A_25_|*|*]
@@ -865,7 +866,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
[MCell 12 |167| -| | ]
[MCell 13 |169| -| | ]
- 7 [IOpin 7 | 22|OUT AVEC_EXP|*| ]
+ 7 [IOpin 7 | 22| IO AVEC_EXP|*| ] paired w/[ RN_AVEC_EXP]
[RegIn 7 |171| -| | ]
[MCell 14 |170| -| | ]
[MCell 15 |172| -| | ]
@@ -876,35 +877,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
-Mux00| ... | ...
-Mux01| ... | ...
-Mux02| ... | ...
-Mux03| ... | ...
-Mux04| ... | ...
-Mux05| ... | ...
-Mux06| ... | ...
-Mux07| ... | ...
-Mux08| ... | ...
-Mux09| ... | ...
-Mux10| Mcel 7 1 ( 271)| RN_FPU_CS
-Mux11| ... | ...
-Mux12| ... | ...
-Mux13| ... | ...
-Mux14| ... | ...
+Mux00| Input Pin ( 86)| RST
+Mux01| IOPin 5 2 ( 58)| FC_1_
+Mux02| Mcel 3 10 ( 188)| inst_BGACK_030_INT_D
+Mux03| Mcel 6 5 ( 253)| SM_AMIGA_2_
+Mux04| Mcel 2 3 ( 154)| inst_AS_030_000_SYNC
+Mux05| Input Pin ( 14)| nEXP_SPACE
+Mux06| IOPin 5 3 ( 57)| FC_0_
+Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D0
+Mux08| IOPin 5 1 ( 59)| A_17_
+Mux09| Mcel 2 0 ( 149)| RN_AVEC_EXP
+Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D2
+Mux11| IOPin 0 5 ( 96)| A_16_
+Mux12| IOPin 0 6 ( 97)| A_19_
+Mux13| Mcel 3 7 ( 184)| inst_CLK_000_D1
+Mux14| Mcel 2 4 ( 155)| inst_CLK_000_D3
Mux15| ... | ...
Mux16| ... | ...
-Mux17| ... | ...
-Mux18| ... | ...
-Mux19| ... | ...
-Mux20| ... | ...
+Mux17| IOPin 0 4 ( 95)| A_18_
+Mux18| IOPin 3 7 ( 28)| BGACK_000
+Mux19| IOPin 7 3 ( 82)| AS_030
+Mux20| Input Pin ( 64)| CLK_030
Mux21| ... | ...
-Mux22| ... | ...
-Mux23| ... | ...
+Mux22| Mcel 2 2 ( 152)| cpu_est_0_
+Mux23| Mcel 7 4 ( 275)| RN_BGACK_030
Mux24| ... | ...
Mux25| ... | ...
Mux26| ... | ...
Mux27| ... | ...
-Mux28| ... | ...
+Mux28| Mcel 1 5 ( 133)| SM_AMIGA_7_
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
@@ -921,18 +922,18 @@ Mux32| ... | ...
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
- 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free
- 2| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free
- 3| VMA| IO| | S | 2 :+: 1| 4 to [ 3]| 1 XOR to [ 3]
- 4| | ? | | S | | 4 to [ 5]| 1 XOR free
- 5| AS_000| IO| | S | 2 | 4 to [ 6]| 1 XOR free
+ 1| VMA| IO| | S | 2 :+: 1| 4 to [ 1]| 1 XOR to [ 1]
+ 2| BG_000| IO| | S | 2 | 4 to [ 2]| 1 XOR free
+ 3|AMIGA_BUS_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig
+ 4| AS_000| IO| | S | 2 | 4 to [ 4]| 1 XOR free
+ 5|inst_CLK_000_D0|NOD| | S | 1 | 4 to [ 6]| 1 XOR to [ 5] for 1 PT sig
6| UDS_000| IO| | S | 7 | 4 to [ 6]| 1 XOR to [ 6] as logic PT
- 7|AMIGA_BUS_ENABLE| IO| | S | 6 | 4 to [ 7]| 1 XOR to [ 7] as logic PT
- 8| | ? | | S | | 4 to [ 7]| 1 XOR free
- 9| LDS_000| IO| | S |11 | 4 to [ 9]| 1 XOR to [ 9] as logic PT
-10|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig
-11| | ? | | S | | 4 to [ 9]| 1 XOR free
-12|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
+ 7|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 7] for 1 PT sig
+ 8| LDS_000| IO| | S |11 | 4 to [ 8]| 1 XOR to [ 8] as logic PT
+ 9| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free
+10|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [10] for 1 PT sig
+11| | ? | | S | | 4 free | 1 XOR free
+12| | ? | | S | | 4 free | 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
@@ -948,19 +949,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s)
- 1| BG_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s)
- 2| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s)
- 3| VMA| IO| | S | 2 :+: 1|=> can support up to [ 4] logic PT(s)
- 4| | ? | | S | |=> can support up to [ 1] logic PT(s)
- 5| AS_000| IO| | S | 2 |=> can support up to [ 5] logic PT(s)
- 6| UDS_000| IO| | S | 7 |=> can support up to [ 10] logic PT(s)
- 7|AMIGA_BUS_ENABLE| IO| | S | 6 |=> can support up to [ 10] logic PT(s)
- 8| | ? | | S | |=> can support up to [ 1] logic PT(s)
- 9| LDS_000| IO| | S |11 |=> can support up to [ 14] logic PT(s)
-10|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
-11| | ? | | S | |=> can support up to [ 10] logic PT(s)
-12|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s)
-13| | ? | | S | |=> can support up to [ 19] logic PT(s)
+ 1| VMA| IO| | S | 2 :+: 1|=> can support up to [ 12] logic PT(s)
+ 2| BG_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s)
+ 3|AMIGA_BUS_ENABLE|OUT| | S | 1 |=> can support up to [ 5] logic PT(s)
+ 4| AS_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s)
+ 5|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 1] logic PT(s)
+ 6| UDS_000| IO| | S | 7 |=> can support up to [ 9] logic PT(s)
+ 7|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 1] logic PT(s)
+ 8| LDS_000| IO| | S |11 |=> can support up to [ 13] logic PT(s)
+ 9| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s)
+10|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 11] logic PT(s)
+11| | ? | | S | |=> can support up to [ 15] logic PT(s)
+12| | ? | | S | |=> can support up to [ 20] logic PT(s)
+13| | ? | | S | |=> can support up to [ 20] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
@@ -973,18 +974,18 @@ _|_________________|__|__|___|_____|_______________________________________
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35
- 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35
- 2| SM_AMIGA_5_|NOD| | => | 6 7 0 1 | 29 28 35 34
- 3| VMA| IO| | => | 6 7 ( 0) 1 | 29 28 ( 35) 34
- 4| | | | => | 7 0 1 2 | 28 35 34 33
- 5| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33)
+ 1| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35)
+ 2| BG_000| IO| | => |( 6) 7 0 1 |( 29) 28 35 34
+ 3|AMIGA_BUS_ENABLE|OUT| | => | 6 7 0 ( 1)| 29 28 35 ( 34)
+ 4| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33)
+ 5|inst_CLK_000_D0|NOD| | => | 7 0 1 2 | 28 35 34 33
6| UDS_000| IO| | => | 0 1 2 ( 3)| 35 34 33 ( 32)
- 7|AMIGA_BUS_ENABLE| IO| | => | 0 ( 1) 2 3 | 35 ( 34) 33 32
- 8| | | | => | 1 2 3 4 | 34 33 32 31
- 9| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31)
+ 7|inst_CLK_000_D1|NOD| | => | 0 1 2 3 | 35 34 33 32
+ 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31)
+ 9| SM_AMIGA_4_|NOD| | => | 1 2 3 4 | 34 33 32 31
10|inst_BGACK_030_INT_D|NOD| | => | 2 3 4 5 | 33 32 31 30
11| | | | => | 2 3 4 5 | 33 32 31 30
-12|inst_CLK_000_D0|NOD| | => | 3 4 5 6 | 32 31 30 29
+12| | | | => | 3 4 5 6 | 32 31 30 29
13| | | | => | 3 4 5 6 | 32 31 30 29
14| | | | => | 4 5 6 7 | 31 30 29 28
15| | | | => | 4 5 6 7 | 31 30 29 28
@@ -998,13 +999,13 @@ _|_________________|__|_____|____________________|________________________
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
- 0| VMA| IO|*| 35| => | 0 1 2 ( 3) 4 5 6 7
- 1|AMIGA_BUS_ENABLE| IO|*| 34| => | 2 3 4 5 6 ( 7) 8 9
- 2| AS_000| IO|*| 33| => | 4 ( 5) 6 7 8 9 10 11
+ 0| VMA| IO|*| 35| => | 0 ( 1) 2 3 4 5 6 7
+ 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | 2 ( 3) 4 5 6 7 8 9
+ 2| AS_000| IO|*| 33| => | ( 4) 5 6 7 8 9 10 11
3| UDS_000| IO|*| 32| => | ( 6) 7 8 9 10 11 12 13
- 4| LDS_000| IO|*| 31| => | 8 ( 9) 10 11 12 13 14 15
+ 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15
5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1
- 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3
+ 6| BG_000| IO|*| 29| => | 12 13 14 15 0 1 ( 2) 3
7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
@@ -1018,8 +1019,7 @@ _|_________________|__|___|_____|___________________________________________
_|_________________|__|___|_____|__________________________________________
0| VMA| IO|*| 35| => | Input macrocell [ -]
| | | | | | IO paired w/ node [ RN_VMA]
- 1|AMIGA_BUS_ENABLE| IO|*| 34| => | Input macrocell [ -]
- | | | | | | IO paired w/ node [RN_AMIGA_BUS_ENABLE]
+ 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | Input macrocell [ -]
2| AS_000| IO|*| 33| => | Input macrocell [ -]
| | | | | | IO paired w/ node [ RN_AS_000]
3| UDS_000| IO|*| 32| => | Input macrocell [ -]
@@ -1043,27 +1043,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number
0 [IOpin 0 | 35| IO VMA|*| ] paired w/[ RN_VMA]
[RegIn 0 |174| -| | ]
[MCell 0 |173| IO DTACK| | ]
- [MCell 1 |175|NOD RN_BG_000| |*] paired w/[ BG_000]
+ [MCell 1 |175|NOD RN_VMA| |*] paired w/[ VMA]
- 1 [IOpin 1 | 34| IO AMIGA_BUS_ENABLE|*| ] paired w/[RN_AMIGA_BUS_ENABLE]
+ 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE|*| ]
[RegIn 1 |177| -| | ]
- [MCell 2 |176|NOD SM_AMIGA_5_| |*]
- [MCell 3 |178|NOD RN_VMA| |*] paired w/[ VMA]
+ [MCell 2 |176|NOD RN_BG_000| |*] paired w/[ BG_000]
+ [MCell 3 |178|OUT AMIGA_BUS_ENABLE| | ]
2 [IOpin 2 | 33| IO AS_000|*|*] paired w/[ RN_AS_000]
[RegIn 2 |180| -| | ]
- [MCell 4 |179| -| | ]
- [MCell 5 |181|NOD RN_AS_000| |*] paired w/[ AS_000]
+ [MCell 4 |179|NOD RN_AS_000| |*] paired w/[ AS_000]
+ [MCell 5 |181|NOD inst_CLK_000_D0| |*]
3 [IOpin 3 | 32| IO UDS_000|*|*] paired w/[ RN_UDS_000]
[RegIn 3 |183| -| | ]
[MCell 6 |182|NOD RN_UDS_000| |*] paired w/[ UDS_000]
- [MCell 7 |184|NOD RN_AMIGA_BUS_ENABLE| |*] paired w/[AMIGA_BUS_ENABLE]
+ [MCell 7 |184|NOD inst_CLK_000_D1| |*]
4 [IOpin 4 | 31| IO LDS_000|*|*] paired w/[ RN_LDS_000]
[RegIn 4 |186| -| | ]
- [MCell 8 |185| -| | ]
- [MCell 9 |187|NOD RN_LDS_000| |*] paired w/[ LDS_000]
+ [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000]
+ [MCell 9 |187|NOD SM_AMIGA_4_| |*]
5 [IOpin 5 | 30| IO DTACK|*|*]
[RegIn 5 |189| -| | ]
@@ -1072,7 +1072,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000]
[RegIn 6 |192| -| | ]
- [MCell 12 |191|NOD inst_CLK_000_D0| |*]
+ [MCell 12 |191| -| | ]
[MCell 13 |193| -| | ]
7 [IOpin 7 | 28|INP BGACK_000|*|*]
@@ -1087,38 +1087,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| IOPin 6 4 ( 69)| A0
-Mux01| Mcel 1 7 ( 136)| SM_AMIGA_4_
-Mux02| Mcel 6 4 ( 251)| cpu_est_1_
+Mux01| ... | ...
+Mux02| Mcel 6 4 ( 251)| cpu_est_2_
Mux03| Input Pin ( 11)| CLK_000
Mux04| IOPin 2 6 ( 21)| BG_030
-Mux05| Mcel 3 12 ( 191)| inst_CLK_000_D0
+Mux05| IOPin 0 7 ( 98)| DS_030
Mux06| IOPin 7 6 ( 79)| SIZE_1_
-Mux07| Mcel 3 9 ( 187)| RN_LDS_000
-Mux08| Mcel 1 8 ( 137)| cpu_est_0_
-Mux09| Mcel 3 3 ( 178)| RN_VMA
-Mux10| IOPin 7 4 ( 81)| DSACK_1_
-Mux11| IOPin 6 6 ( 71)| RW
-Mux12| Mcel 1 10 ( 140)| SM_AMIGA_1_
-Mux13| Mcel 3 7 ( 184)| RN_AMIGA_BUS_ENABLE
+Mux07| Mcel 7 6 ( 278)| RN_AS_030
+Mux08| Mcel 1 8 ( 137)| SM_AMIGA_5_
+Mux09| Mcel 2 0 ( 149)| RN_AVEC_EXP
+Mux10| Mcel 3 4 ( 179)| RN_AS_000
+Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D2
+Mux12| Mcel 3 9 ( 187)| SM_AMIGA_4_
+Mux13| Mcel 1 3 ( 130)| cpu_est_1_
Mux14| IOPin 6 5 ( 70)| SIZE_0_
Mux15| Input Pin ( 14)| nEXP_SPACE
-Mux16| Mcel 3 6 ( 182)| RN_UDS_000
-Mux17| Mcel 3 1 ( 175)| RN_BG_000
-Mux18| IOPin 0 7 ( 98)| DS_030
+Mux16| Mcel 3 8 ( 185)| RN_LDS_000
+Mux17| Mcel 3 1 ( 175)| RN_VMA
+Mux18| Mcel 7 10 ( 284)| inst_VPA_D
Mux19| IOPin 7 3 ( 82)| AS_030
-Mux20| Mcel 3 10 ( 188)| inst_BGACK_030_INT_D
+Mux20| Mcel 7 4 ( 275)| RN_BGACK_030
Mux21| Input Pin ( 86)| RST
-Mux22| Mcel 7 14 ( 290)| inst_VPA_D
+Mux22| Mcel 2 2 ( 152)| cpu_est_0_
Mux23| Mcel 6 2 ( 248)| RN_E
-Mux24| Mcel 3 5 ( 181)| RN_AS_000
-Mux25| Mcel 7 8 ( 281)| inst_CLK_000_D4
-Mux26| Mcel 0 11 ( 118)| SM_AMIGA_7_
-Mux27| Mcel 7 5 ( 277)| RN_BGACK_030
-Mux28| Mcel 3 2 ( 176)| SM_AMIGA_5_
-Mux29| Mcel 7 7 ( 280)| SM_AMIGA_6_
-Mux30| Mcel 7 6 ( 278)| RN_AS_030
-Mux31| Mcel 1 5 ( 133)| SM_AMIGA_0_
-Mux32| Mcel 6 5 ( 253)| cpu_est_2_
+Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D0
+Mux25| IOPin 6 6 ( 71)| RW
+Mux26| ... | ...
+Mux27| ... | ...
+Mux28| Mcel 3 2 ( 176)| RN_BG_000
+Mux29| ... | ...
+Mux30| Mcel 3 6 ( 182)| RN_UDS_000
+Mux31| Mcel 1 5 ( 133)| SM_AMIGA_7_
+Mux32| IOPin 7 4 ( 81)| DSACK1
---------------------------------------------------------------------------
===========================================================================
< Block [ 4] > Macrocell (MCell) Cluster Assignments
@@ -1290,7 +1290,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
-Mux00| IOPin 3 2 ( 33)| AS_000
+Mux00| Mcel 7 4 ( 275)| RN_BGACK_030
Mux01| IOPin 1 6 ( 4)| A_31_
Mux02| ... | ...
Mux03| IOPin 2 1 ( 16)| A_27_
@@ -1300,11 +1300,11 @@ Mux06| ... | ...
Mux07| IOPin 2 0 ( 15)| A_28_
Mux08| IOPin 7 0 ( 85)| A_22_
Mux09| IOPin 1 5 ( 5)| A_30_
-Mux10| Mcel 7 1 ( 271)| RN_FPU_CS
+Mux10| ... | ...
Mux11| IOPin 7 1 ( 84)| A_23_
Mux12| IOPin 2 3 ( 18)| A_25_
-Mux13| Mcel 7 5 ( 277)| RN_BGACK_030
-Mux14| ... | ...
+Mux13| ... | ...
+Mux14| Mcel 7 2 ( 272)| RN_FPU_CS
Mux15| IOPin 0 3 ( 94)| A_21_
Mux16| ... | ...
Mux17| IOPin 2 2 ( 17)| A_26_
@@ -1313,7 +1313,7 @@ Mux19| ... | ...
Mux20| ... | ...
Mux21| Input Pin ( 14)| nEXP_SPACE
Mux22| ... | ...
-Mux23| ... | ...
+Mux23| IOPin 3 2 ( 33)| AS_000
Mux24| ... | ...
Mux25| IOPin 6 6 ( 71)| RW
Mux26| ... | ...
@@ -1419,21 +1419,21 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
- 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
- 1|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
+ 0| RW| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
+ 1| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
2| E| IO| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2]
- 3| | ? | | S | | 4 free | 1 XOR free
- 4| cpu_est_1_|NOD| | S | 4 | 4 to [ 4]| 1 XOR free
- 5| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 5]| 1 XOR to [ 5]
- 6| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free
- 7| SM_AMIGA_3_|NOD| | S | 4 | 4 to [ 7]| 1 XOR free
+ 3| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig
+ 4| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4]
+ 5| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free
+ 6| SM_AMIGA_3_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free
+ 7| | ? | | S | | 4 free | 1 XOR free
8| A0| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
9| | ? | | S | | 4 free | 1 XOR free
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| | ? | | S | | 4 free | 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
-14| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig
+14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
@@ -1446,22 +1446,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
- 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s)
- 1|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 14] logic PT(s)
- 2| E| IO| | S | 3 :+: 1|=> can support up to [ 13] logic PT(s)
- 3| | ? | | S | |=> can support up to [ 5] logic PT(s)
- 4| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s)
- 5| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 4] logic PT(s)
- 6| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s)
- 7| SM_AMIGA_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s)
- 8| A0| IO| | S | 1 |=> can support up to [ 15] logic PT(s)
+ 0| RW| IO| | S | 1 |=> can support up to [ 9] logic PT(s)
+ 1| SIZE_0_| IO| | S | 1 |=> can support up to [ 13] logic PT(s)
+ 2| E| IO| | S | 3 :+: 1|=> can support up to [ 12] logic PT(s)
+ 3| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 5] logic PT(s)
+ 4| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s)
+ 5| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s)
+ 6| SM_AMIGA_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s)
+ 7| | ? | | S | |=> can support up to [ 14] logic PT(s)
+ 8| A0| IO| | S | 1 |=> can support up to [ 20] logic PT(s)
9| | ? | | S | |=> can support up to [ 19] logic PT(s)
10| | ? | | S | |=> can support up to [ 20] logic PT(s)
11| | ? | | S | |=> can support up to [ 20] logic PT(s)
-12| | ? | | S | |=> can support up to [ 19] logic PT(s)
-13| | ? | | S | |=> can support up to [ 19] logic PT(s)
-14| SIZE_0_| IO| | S | 1 |=> can support up to [ 15] logic PT(s)
-15| | ? | | S | |=> can support up to [ 9] logic PT(s)
+12| | ? | | S | |=> can support up to [ 20] logic PT(s)
+13| | ? | | S | |=> can support up to [ 20] logic PT(s)
+14| | ? | | S | |=> can support up to [ 15] logic PT(s)
+15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 6] > Node-Pin Assignments
@@ -1471,21 +1471,21 @@ _|_________________|__|__|___|_____|_______________________________________
| Sig Type---+ | to | Block [ 6] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
- 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65)
- 1|inst_CLK_OUT_PRE_50|NOD| | => | 5 6 7 0 | 70 71 72 65
+ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65
+ 1| SIZE_0_| IO| | => |( 5) 6 7 0 |( 70) 71 72 65
2| E| IO| | => | 6 7 0 ( 1)| 71 72 65 ( 66)
- 3| | | | => | 6 7 0 1 | 71 72 65 66
- 4| cpu_est_1_|NOD| | => | 7 0 1 2 | 72 65 66 67
- 5| cpu_est_2_|NOD| | => | 7 0 1 2 | 72 65 66 67
- 6| SM_AMIGA_2_|NOD| | => | 0 1 2 3 | 65 66 67 68
- 7| SM_AMIGA_3_|NOD| | => | 0 1 2 3 | 65 66 67 68
+ 3| CLK_DIV_OUT|OUT| | => | 6 7 ( 0) 1 | 71 72 ( 65) 66
+ 4| cpu_est_2_|NOD| | => | 7 0 1 2 | 72 65 66 67
+ 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 72 65 66 67
+ 6| SM_AMIGA_3_|NOD| | => | 0 1 2 3 | 65 66 67 68
+ 7| | | | => | 0 1 2 3 | 65 66 67 68
8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69)
9| | | | => | 1 2 3 4 | 66 67 68 69
10| | | | => | 2 3 4 5 | 67 68 69 70
11| | | | => | 2 3 4 5 | 67 68 69 70
12| | | | => | 3 4 5 6 | 68 69 70 71
13| | | | => | 3 4 5 6 | 68 69 70 71
-14| SIZE_0_| IO| | => | 4 ( 5) 6 7 | 69 ( 70) 71 72
+14| | | | => | 4 5 6 7 | 69 70 71 72
15| | | | => | 4 5 6 7 | 69 70 71 72
---------------------------------------------------------------------------
===========================================================================
@@ -1497,13 +1497,13 @@ _|_________________|__|_____|____________________|________________________
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
- 0| CLK_DIV_OUT|OUT|*| 65| => | ( 0) 1 2 3 4 5 6 7
+ 0| CLK_DIV_OUT|OUT|*| 65| => | 0 1 2 ( 3) 4 5 6 7
1| E| IO|*| 66| => | ( 2) 3 4 5 6 7 8 9
2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11
3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13
4| A0| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15
- 5| SIZE_0_| IO|*| 70| => | 10 11 12 13 (14) 15 0 1
- 6| RW|INP|*| 71| => | 12 13 14 15 0 1 2 3
+ 5| SIZE_0_| IO|*| 70| => | 10 11 12 13 14 15 0 ( 1)
+ 6| RW| IO|*| 71| => | 12 13 14 15 ( 0) 1 2 3
7| | | | 72| => | 14 15 0 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
@@ -1522,7 +1522,7 @@ _|_________________|__|___|_____|__________________________________________
3| IPL_2_|INP|*| 68| => | Input macrocell [ -]
4| A0| IO|*| 69| => | Input macrocell [ -]
5| SIZE_0_| IO|*| 70| => | Input macrocell [ -]
- 6| RW|INP|*| 71| => | Input macrocell [ -]
+ 6| RW| IO|*| 71| => | Input macrocell [ -]
7| | | | 72| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
@@ -1536,23 +1536,23 @@ IMX No. | +---- Block IO Pin or Macrocell Number
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ]
[RegIn 0 |246| -| | ]
- [MCell 0 |245|OUT CLK_DIV_OUT| | ]
- [MCell 1 |247|NOD inst_CLK_OUT_PRE_50| |*]
+ [MCell 0 |245| IO RW| | ]
+ [MCell 1 |247| IO SIZE_0_| | ]
1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E]
[RegIn 1 |249| -| | ]
[MCell 2 |248|NOD RN_E| |*] paired w/[ E]
- [MCell 3 |250| -| | ]
+ [MCell 3 |250|OUT CLK_DIV_OUT| | ]
2 [IOpin 2 | 67|INP IPL_0_|*|*]
[RegIn 2 |252| -| | ]
- [MCell 4 |251|NOD cpu_est_1_| |*]
- [MCell 5 |253|NOD cpu_est_2_| |*]
+ [MCell 4 |251|NOD cpu_est_2_| |*]
+ [MCell 5 |253|NOD SM_AMIGA_2_| |*]
3 [IOpin 3 | 68|INP IPL_2_|*|*]
[RegIn 3 |255| -| | ]
- [MCell 6 |254|NOD SM_AMIGA_2_| |*]
- [MCell 7 |256|NOD SM_AMIGA_3_| |*]
+ [MCell 6 |254|NOD SM_AMIGA_3_| |*]
+ [MCell 7 |256| -| | ]
4 [IOpin 4 | 69| IO A0|*|*]
[RegIn 4 |258| -| | ]
@@ -1564,14 +1564,14 @@ IMX No. | +---- Block IO Pin or Macrocell Number
[MCell 10 |260| -| | ]
[MCell 11 |262| -| | ]
- 6 [IOpin 6 | 71|INP RW|*|*]
+ 6 [IOpin 6 | 71| IO RW|*|*]
[RegIn 6 |264| -| | ]
[MCell 12 |263| -| | ]
[MCell 13 |265| -| | ]
7 [IOpin 7 | 72| -| | ]
[RegIn 7 |267| -| | ]
- [MCell 14 |266| IO SIZE_0_| | ]
+ [MCell 14 |266| -| | ]
[MCell 15 |268| -| | ]
---------------------------------------------------------------------------
===========================================================================
@@ -1580,34 +1580,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
-Mux00| IOPin 3 4 ( 31)| LDS_000
-Mux01| Mcel 1 7 ( 136)| SM_AMIGA_4_
-Mux02| Mcel 7 14 ( 290)| inst_VPA_D
-Mux03| Mcel 6 5 ( 253)| cpu_est_2_
+Mux00| Input Pin ( 86)| RST
+Mux01| Mcel 7 11 ( 286)| inst_DTACK_D0
+Mux02| Mcel 3 1 ( 175)| RN_VMA
+Mux03| Mcel 6 5 ( 253)| SM_AMIGA_2_
Mux04| Mcel 6 2 ( 248)| RN_E
-Mux05| Mcel 3 12 ( 191)| inst_CLK_000_D0
-Mux06| Mcel 1 9 ( 139)| inst_CLK_OUT_PRE_25
-Mux07| Mcel 7 6 ( 278)| RN_AS_030
-Mux08| Mcel 6 7 ( 256)| SM_AMIGA_3_
-Mux09| Mcel 0 1 ( 103)| inst_DTACK_D0
-Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D1
-Mux11| Mcel 6 4 ( 251)| cpu_est_1_
-Mux12| IOPin 3 3 ( 32)| UDS_000
-Mux13| Mcel 3 3 ( 178)| RN_VMA
+Mux05| Mcel 1 3 ( 130)| cpu_est_1_
+Mux06| Mcel 0 3 ( 106)| inst_RW_000_INT
+Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D0
+Mux08| IOPin 3 3 ( 32)| UDS_000
+Mux09| ... | ...
+Mux10| ... | ...
+Mux11| Mcel 6 4 ( 251)| cpu_est_2_
+Mux12| Mcel 3 9 ( 187)| SM_AMIGA_4_
+Mux13| Mcel 3 7 ( 184)| inst_CLK_000_D1
Mux14| ... | ...
Mux15| Input Pin ( 14)| nEXP_SPACE
Mux16| ... | ...
-Mux17| Mcel 1 8 ( 137)| cpu_est_0_
-Mux18| ... | ...
+Mux17| ... | ...
+Mux18| Mcel 7 10 ( 284)| inst_VPA_D
Mux19| ... | ...
-Mux20| ... | ...
-Mux21| Input Pin ( 86)| RST
-Mux22| ... | ...
-Mux23| Mcel 6 6 ( 254)| SM_AMIGA_2_
-Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE_50
+Mux20| Mcel 7 4 ( 275)| RN_BGACK_030
+Mux21| Mcel 7 6 ( 278)| RN_AS_030
+Mux22| Mcel 2 2 ( 152)| cpu_est_0_
+Mux23| Mcel 6 6 ( 254)| SM_AMIGA_3_
+Mux24| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25
Mux25| ... | ...
Mux26| IOPin 3 2 ( 33)| AS_000
-Mux27| Mcel 7 5 ( 277)| RN_BGACK_030
+Mux27| IOPin 3 4 ( 31)| LDS_000
Mux28| ... | ...
Mux29| ... | ...
Mux30| ... | ...
@@ -1625,20 +1625,20 @@ Mux32| ... | ...
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| SIZE_1_| IO| | S | 2 | 4 to [ 0]| 1 XOR free
- 1| FPU_CS| IO| | S | 2 | 4 to [ 1]| 1 XOR free
- 2|inst_CLK_000_D3|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig
- 3|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig
- 4| | ? | | S | | 4 free | 1 XOR free
- 5| BGACK_030| IO| | S | 2 | 4 to [ 5]| 1 XOR free
+ 1| RW_000| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
+ 2| FPU_CS| IO| | S | 2 | 4 to [ 2]| 1 XOR free
+ 3|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig
+ 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free
+ 5|inst_CLK_030_H|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT
6| AS_030| IO| | S | 4 | 4 to [ 6]| 1 XOR free
- 7| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 7]| 1 XOR free
- 8|inst_CLK_000_D4|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
- 9|inst_AS_030_000_SYNC|NOD| | S | 8 | 4 to [ 9]| 1 XOR to [ 9] as logic PT
-10| DSACK_0_|OUT| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig
-11| DSACK_1_| IO| | S | 2 | 4 to [11]| 1 XOR free
-12|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
+ 7| SM_AMIGA_1_|NOD| | S | 2 | 4 to [ 7]| 1 XOR free
+ 8| DSACK1| IO| | S | 2 | 4 to [ 8]| 1 XOR free
+ 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig
+10| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig
+11| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig
+12|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
13| | ? | | S | | 4 free | 1 XOR free
-14| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig
+14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
@@ -1652,21 +1652,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| SIZE_1_| IO| | S | 2 |=> can support up to [ 9] logic PT(s)
- 1| FPU_CS| IO| | S | 2 |=> can support up to [ 13] logic PT(s)
- 2|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 14] logic PT(s)
- 3|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 14] logic PT(s)
- 4| | ? | | S | |=> can support up to [ 9] logic PT(s)
- 5| BGACK_030| IO| | S | 2 |=> can support up to [ 10] logic PT(s)
- 6| AS_030| IO| | S | 4 |=> can support up to [ 9] logic PT(s)
- 7| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s)
- 8|inst_CLK_000_D4|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
- 9|inst_AS_030_000_SYNC|NOD| | S | 8 |=> can support up to [ 13] logic PT(s)
-10| DSACK_0_|OUT| | S | 1 |=> can support up to [ 5] logic PT(s)
-11| DSACK_1_| IO| | S | 2 |=> can support up to [ 14] logic PT(s)
-12|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 14] logic PT(s)
-13| | ? | | S | |=> can support up to [ 18] logic PT(s)
-14| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s)
-15| | ? | | S | |=> can support up to [ 9] logic PT(s)
+ 1| RW_000| IO| | S | 1 |=> can support up to [ 9] logic PT(s)
+ 2| FPU_CS| IO| | S | 2 |=> can support up to [ 13] logic PT(s)
+ 3|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 5] logic PT(s)
+ 4| BGACK_030| IO| | S | 2 |=> can support up to [ 9] logic PT(s)
+ 5|inst_CLK_030_H|NOD| | S | 5 |=> can support up to [ 5] logic PT(s)
+ 6| AS_030| IO| | S | 4 |=> can support up to [ 5] logic PT(s)
+ 7| SM_AMIGA_1_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s)
+ 8| DSACK1| IO| | S | 2 |=> can support up to [ 13] logic PT(s)
+ 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 13] logic PT(s)
+10| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 17] logic PT(s)
+11| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s)
+12|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s)
+13| | ? | | S | |=> can support up to [ 19] logic PT(s)
+14| | ? | | S | |=> can support up to [ 15] logic PT(s)
+15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 7] > Node-Pin Assignments
@@ -1677,20 +1677,20 @@ _|_________________|__|__|___|_____|_______________________________________
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| SIZE_1_| IO| | => | 5 ( 6) 7 0 | 80 ( 79) 78 85
- 1| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85
- 2|inst_CLK_000_D3|NOD| | => | 6 7 0 1 | 79 78 85 84
- 3|inst_CLK_000_D1|NOD| | => | 6 7 0 1 | 79 78 85 84
- 4| | | | => | 7 0 1 2 | 78 85 84 83
- 5| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83)
+ 1| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85
+ 2| FPU_CS| IO| | => | 6 ( 7) 0 1 | 79 ( 78) 85 84
+ 3|inst_CLK_000_D2|NOD| | => | 6 7 0 1 | 79 78 85 84
+ 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83)
+ 5|inst_CLK_030_H|NOD| | => | 7 0 1 2 | 78 85 84 83
6| AS_030| IO| | => | 0 1 2 ( 3)| 85 84 83 ( 82)
- 7| SM_AMIGA_6_|NOD| | => | 0 1 2 3 | 85 84 83 82
- 8|inst_CLK_000_D4|NOD| | => | 1 2 3 4 | 84 83 82 81
- 9|inst_AS_030_000_SYNC|NOD| | => | 1 2 3 4 | 84 83 82 81
-10| DSACK_0_|OUT| | => | 2 3 4 ( 5)| 83 82 81 ( 80)
-11| DSACK_1_| IO| | => | 2 3 ( 4) 5 | 83 82 ( 81) 80
-12|inst_CLK_000_D2|NOD| | => | 3 4 5 6 | 82 81 80 79
+ 7| SM_AMIGA_1_|NOD| | => | 0 1 2 3 | 85 84 83 82
+ 8| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81)
+ 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 84 83 82 81
+10| inst_VPA_D|NOD| | => | 2 3 4 5 | 83 82 81 80
+11| inst_DTACK_D0|NOD| | => | 2 3 4 5 | 83 82 81 80
+12|inst_CLK_OUT_PRE_50_D|NOD| | => | 3 4 5 6 | 82 81 80 79
13| | | | => | 3 4 5 6 | 82 81 80 79
-14| inst_VPA_D|NOD| | => | 4 5 6 7 | 81 80 79 78
+14| | | | => | 4 5 6 7 | 81 80 79 78
15| | | | => | 4 5 6 7 | 81 80 79 78
---------------------------------------------------------------------------
===========================================================================
@@ -1704,12 +1704,12 @@ _|_________________|__|_____|____________________|________________________
_|_________________|__|___|_____|___________________________________________
0| A_22_|INP|*| 85| => | 0 1 2 3 4 5 6 7
1| A_23_|INP|*| 84| => | 2 3 4 5 6 7 8 9
- 2| BGACK_030| IO|*| 83| => | 4 ( 5) 6 7 8 9 10 11
+ 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11
3| AS_030| IO|*| 82| => | ( 6) 7 8 9 10 11 12 13
- 4| DSACK_1_| IO|*| 81| => | 8 9 10 (11) 12 13 14 15
- 5| DSACK_0_|OUT|*| 80| => | (10) 11 12 13 14 15 0 1
+ 4| DSACK1| IO|*| 81| => | ( 8) 9 10 11 12 13 14 15
+ 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 0 ( 1)
6| SIZE_1_| IO|*| 79| => | 12 13 14 15 ( 0) 1 2 3
- 7| FPU_CS| IO|*| 78| => | 14 15 0 ( 1) 2 3 4 5
+ 7| FPU_CS| IO|*| 78| => | 14 15 0 1 ( 2) 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table
@@ -1726,9 +1726,9 @@ _|_________________|__|___|_____|__________________________________________
| | | | | | IO paired w/ node [ RN_BGACK_030]
3| AS_030| IO|*| 82| => | Input macrocell [ -]
| | | | | | IO paired w/ node [ RN_AS_030]
- 4| DSACK_1_| IO|*| 81| => | Input macrocell [ -]
- | | | | | | IO paired w/ node [ RN_DSACK_1_]
- 5| DSACK_0_|OUT|*| 80| => | Input macrocell [ -]
+ 4| DSACK1| IO|*| 81| => | Input macrocell [ -]
+ | | | | | | IO paired w/ node [ RN_DSACK1]
+ 5| RW_000| IO|*| 80| => | Input macrocell [ -]
6| SIZE_1_| IO|*| 79| => | Input macrocell [ -]
7| FPU_CS| IO|*| 78| => | Input macrocell [ -]
| | | | | | IO paired w/ node [ RN_FPU_CS]
@@ -1745,41 +1745,41 @@ IMX No. | +---- Block IO Pin or Macrocell Number
0 [IOpin 0 | 85|INP A_22_|*|*]
[RegIn 0 |270| -| | ]
[MCell 0 |269| IO SIZE_1_| | ]
- [MCell 1 |271|NOD RN_FPU_CS| |*] paired w/[ FPU_CS]
+ [MCell 1 |271| IO RW_000| | ]
1 [IOpin 1 | 84|INP A_23_|*|*]
[RegIn 1 |273| -| | ]
- [MCell 2 |272|NOD inst_CLK_000_D3| |*]
- [MCell 3 |274|NOD inst_CLK_000_D1| |*]
+ [MCell 2 |272|NOD RN_FPU_CS| |*] paired w/[ FPU_CS]
+ [MCell 3 |274|NOD inst_CLK_000_D2| |*]
2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030]
[RegIn 2 |276| -| | ]
- [MCell 4 |275| -| | ]
- [MCell 5 |277|NOD RN_BGACK_030| |*] paired w/[ BGACK_030]
+ [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030]
+ [MCell 5 |277|NOD inst_CLK_030_H| |*]
3 [IOpin 3 | 82| IO AS_030|*|*] paired w/[ RN_AS_030]
[RegIn 3 |279| -| | ]
[MCell 6 |278|NOD RN_AS_030| |*] paired w/[ AS_030]
- [MCell 7 |280|NOD SM_AMIGA_6_| |*]
+ [MCell 7 |280|NOD SM_AMIGA_1_| |*]
- 4 [IOpin 4 | 81| IO DSACK_1_|*|*] paired w/[ RN_DSACK_1_]
+ 4 [IOpin 4 | 81| IO DSACK1|*|*] paired w/[ RN_DSACK1]
[RegIn 4 |282| -| | ]
- [MCell 8 |281|NOD inst_CLK_000_D4| |*]
- [MCell 9 |283|NOD inst_AS_030_000_SYNC| |*]
+ [MCell 8 |281|NOD RN_DSACK1| |*] paired w/[ DSACK1]
+ [MCell 9 |283|NOD inst_CLK_OUT_PRE_50| |*]
- 5 [IOpin 5 | 80|OUT DSACK_0_|*| ]
+ 5 [IOpin 5 | 80| IO RW_000|*|*]
[RegIn 5 |285| -| | ]
- [MCell 10 |284|OUT DSACK_0_| | ]
- [MCell 11 |286|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_]
+ [MCell 10 |284|NOD inst_VPA_D| |*]
+ [MCell 11 |286|NOD inst_DTACK_D0| |*]
6 [IOpin 6 | 79| IO SIZE_1_|*|*]
[RegIn 6 |288| -| | ]
- [MCell 12 |287|NOD inst_CLK_000_D2| |*]
+ [MCell 12 |287|NOD inst_CLK_OUT_PRE_50_D| |*]
[MCell 13 |289| -| | ]
7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS]
[RegIn 7 |291| -| | ]
- [MCell 14 |290|NOD inst_VPA_D| |*]
+ [MCell 14 |290| -| | ]
[MCell 15 |292| -| | ]
---------------------------------------------------------------------------
===========================================================================
@@ -1788,37 +1788,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
-Mux00| Input Pin ( 86)| RST
+Mux00| IOPin 3 4 ( 31)| LDS_000
Mux01| IOPin 5 2 ( 58)| FC_1_
-Mux02| Mcel 1 10 ( 140)| SM_AMIGA_1_
-Mux03| Mcel 7 8 ( 281)| inst_CLK_000_D4
-Mux04| Input Pin ( 64)| CLK_030
-Mux05| Mcel 7 9 ( 283)| inst_AS_030_000_SYNC
-Mux06| IOPin 0 5 ( 96)| A_16_
-Mux07| Mcel 0 11 ( 118)| SM_AMIGA_7_
-Mux08| IOPin 3 3 ( 32)| UDS_000
-Mux09| IOPin 7 3 ( 82)| AS_030
+Mux02| ... | ...
+Mux03| Mcel 7 8 ( 281)| RN_DSACK1
+Mux04| IOPin 0 4 ( 95)| A_18_
+Mux05| Mcel 7 9 ( 283)| inst_CLK_OUT_PRE_50
+Mux06| IOPin 0 6 ( 97)| A_19_
+Mux07| Mcel 7 7 ( 280)| SM_AMIGA_1_
+Mux08| Mcel 3 7 ( 184)| inst_CLK_000_D1
+Mux09| IOPin 3 5 ( 30)| DTACK
Mux10| Input Pin ( 36)| VPA
-Mux11| Mcel 3 12 ( 191)| inst_CLK_000_D0
-Mux12| IOPin 0 6 ( 97)| A_19_
-Mux13| IOPin 5 1 ( 59)| A_17_
-Mux14| Mcel 7 11 ( 286)| RN_DSACK_1_
+Mux11| IOPin 0 5 ( 96)| A_16_
+Mux12| IOPin 3 3 ( 32)| UDS_000
+Mux13| Mcel 7 5 ( 277)| inst_CLK_030_H
+Mux14| Mcel 7 2 ( 272)| RN_FPU_CS
Mux15| Input Pin ( 14)| nEXP_SPACE
Mux16| ... | ...
Mux17| IOPin 5 3 ( 57)| FC_0_
-Mux18| Mcel 7 3 ( 274)| inst_CLK_000_D1
-Mux19| Mcel 7 1 ( 271)| RN_FPU_CS
-Mux20| Mcel 7 7 ( 280)| SM_AMIGA_6_
-Mux21| Mcel 7 6 ( 278)| RN_AS_030
-Mux22| ... | ...
-Mux23| IOPin 3 2 ( 33)| AS_000
-Mux24| IOPin 3 4 ( 31)| LDS_000
-Mux25| ... | ...
-Mux26| ... | ...
-Mux27| Mcel 7 5 ( 277)| RN_BGACK_030
-Mux28| Mcel 7 2 ( 272)| inst_CLK_000_D3
-Mux29| Mcel 7 12 ( 287)| inst_CLK_000_D2
-Mux30| ... | ...
-Mux31| IOPin 0 4 ( 95)| A_18_
-Mux32| IOPin 3 7 ( 28)| BGACK_000
+Mux18| IOPin 3 7 ( 28)| BGACK_000
+Mux19| IOPin 7 3 ( 82)| AS_030
+Mux20| Input Pin ( 64)| CLK_030
+Mux21| Input Pin ( 86)| RST
+Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_
+Mux23| Mcel 7 4 ( 275)| RN_BGACK_030
+Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D0
+Mux25| Mcel 0 3 ( 106)| inst_RW_000_INT
+Mux26| IOPin 3 2 ( 33)| AS_000
+Mux27| IOPin 5 1 ( 59)| A_17_
+Mux28| ... | ...
+Mux29| ... | ...
+Mux30| Mcel 7 6 ( 278)| RN_AS_030
+Mux31| ... | ...
+Mux32| ... | ...
---------------------------------------------------------------------------
\ No newline at end of file
diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt
index e776f1a..21bf7b8 100644
--- a/Logic/68030_tk.rpt
+++ b/Logic/68030_tk.rpt
@@ -12,7 +12,7 @@ Project_Summary
Project Name : 68030_tk
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
-Project Fitted on : Thu May 29 22:04:32 2014
+Project Fitted on : Sun Jun 01 01:03:29 2014
Device : M4A5-128/64
Package : 100TQFP
@@ -37,11 +37,11 @@ Fitter 00:00:00
Design_Summary
~~~~~~~~~~~~~~
- Total Input Pins : 30
- Total Output Pins : 19
- Total Bidir I/O Pins : 10
+ Total Input Pins : 29
+ Total Output Pins : 18
+ Total Bidir I/O Pins : 12
Total Flip-Flops : 45
- Total Product Terms : 136
+ Total Product Terms : 143
Total Reserved Pins : 0
Total Reserved Blocks : 0
@@ -54,13 +54,13 @@ Dedicated Pins
Input-Only Pins 2 2 0 --> 100%
Clock/Input Pins 4 4 0 --> 100%
I/O Pins 64 53 11 --> 82%
-Logic Macrocells 128 53 75 --> 41%
+Logic Macrocells 128 54 74 --> 42%
Input Registers 64 0 64 --> 0%
Unusable Macrocells .. 0 ..
-CSM Outputs/Total Block Inputs 264 142 122 --> 53%
-Logical Product Terms 640 139 501 --> 21%
-Product Term Clusters 128 37 91 --> 28%
+CSM Outputs/Total Block Inputs 264 157 107 --> 59%
+Logical Product Terms 640 146 494 --> 22%
+Product Term Clusters 128 39 89 --> 30%
Blocks_Resource_Summary
@@ -71,14 +71,14 @@ Blocks_Resource_Summary
---------------------------------------------------------------------------------
Maximum 33 8 8 -- -- 16 80 16 -
---------------------------------------------------------------------------------
-Block A 21 7 0 6 0 10 20 12 Lo
-Block B 21 8 0 10 0 6 26 8 Lo
-Block C 1 8 0 2 0 14 2 16 Lo
-Block D 33 8 0 10 0 6 36 5 Lo
-Block E 17 3 0 3 0 13 4 15 Lo
-Block F 0 4 0 0 0 16 0 16 Lo
-Block G 21 7 0 9 0 7 23 11 Lo
-Block H 28 8 0 13 0 3 28 8 Lo
+Block A 17 7 0 4 0 12 24 10 Hi
+Block B 24 8 0 10 0 6 26 8 Hi
+Block C 22 8 0 5 0 11 16 12 Hi
+Block D 29 8 0 11 0 5 32 7 Hi
+Block E 17 3 0 3 0 13 4 15 Hi
+Block F 0 4 0 0 0 16 0 16 Hi
+Block G 21 7 0 8 0 8 19 12 Hi
+Block H 27 8 0 13 0 3 25 9 Hi
---------------------------------------------------------------------------------
Four rightmost columns above reflect last status of the placement process.
@@ -150,7 +150,7 @@ Block Reservation : No
@Output_Slew_Rate Default = Slow(2)
-@Power Default = Low (2)
+@Power Default = High(2)
Device Options:
@@ -246,8 +246,8 @@ Pin No| Type |Pad |Pin | Signal name
77 | GND | | |
78 | I_O | H7 | * |FPU_CS
79 | I_O | H6 | * |SIZE_1_
-80 | I_O | H5 | * |DSACK_0_
-81 | I_O | H4 | * |DSACK_1_
+80 | I_O | H5 | * |RW_000
+81 | I_O | H4 | * |DSACK1
82 | I_O | H3 | * |AS_030
83 | I_O | H2 | * |BGACK_030
84 | I_O | H1 | * |A_23_
@@ -287,36 +287,35 @@ Input_Signal_List
Pin r e O Input
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
- 96 A . I/O -------H Low Slow A_16_
- 59 F . I/O -------H Low Slow A_17_
- 95 A . I/O -------H Low Slow A_18_
- 97 A . I/O -------H Low Slow A_19_
- 93 A . I/O ----E--- Low Slow A_20_
- 94 A . I/O ----E--- Low Slow A_21_
- 85 H . I/O ----E--- Low Slow A_22_
- 84 H . I/O ----E--- Low Slow A_23_
- 19 C . I/O ----E--- Low Slow A_24_
- 18 C . I/O ----E--- Low Slow A_25_
- 17 C . I/O ----E--- Low Slow A_26_
- 16 C . I/O ----E--- Low Slow A_27_
- 15 C . I/O ----E--- Low Slow A_28_
- 6 B . I/O ----E--- Low Slow A_29_
- 5 B . I/O ----E--- Low Slow A_30_
- 4 B . I/O ----E--- Low Slow A_31_
- 28 D . I/O -------H Low Slow BGACK_000
- 21 C . I/O ---D---- Low Slow BG_030
- 57 F . I/O -------H Low Slow FC_0_
- 58 F . I/O -------H Low Slow FC_1_
- 67 G . I/O -B------ Low Slow IPL_0_
- 56 F . I/O -B------ Low Slow IPL_1_
- 68 G . I/O -B------ Low Slow IPL_2_
- 71 G . I/O A--DE--- Low Slow RW
+ 96 A . I/O --C----H Hi Slow A_16_
+ 59 F . I/O --C----H Hi Slow A_17_
+ 95 A . I/O --C----H Hi Slow A_18_
+ 97 A . I/O --C----H Hi Slow A_19_
+ 93 A . I/O ----E--- Hi Slow A_20_
+ 94 A . I/O ----E--- Hi Slow A_21_
+ 85 H . I/O ----E--- Hi Slow A_22_
+ 84 H . I/O ----E--- Hi Slow A_23_
+ 19 C . I/O ----E--- Hi Slow A_24_
+ 18 C . I/O ----E--- Hi Slow A_25_
+ 17 C . I/O ----E--- Hi Slow A_26_
+ 16 C . I/O ----E--- Hi Slow A_27_
+ 15 C . I/O ----E--- Hi Slow A_28_
+ 6 B . I/O ----E--- Hi Slow A_29_
+ 5 B . I/O ----E--- Hi Slow A_30_
+ 4 B . I/O ----E--- Hi Slow A_31_
+ 28 D . I/O --C----H Hi Slow BGACK_000
+ 21 C . I/O ---D---- Hi Slow BG_030
+ 57 F . I/O --C----H Hi Slow FC_0_
+ 58 F . I/O --C----H Hi Slow FC_1_
+ 67 G . I/O -B------ Hi Slow IPL_0_
+ 56 F . I/O -B------ Hi Slow IPL_1_
+ 68 G . I/O -B------ Hi Slow IPL_2_
11 . . Ck/I ---D---- - Slow CLK_000
- 14 . . Ck/I A--DE-GH - Slow nEXP_SPACE
+ 14 . . Ck/I ABCDE-GH - Slow nEXP_SPACE
36 . . Ded -------H - Slow VPA
- 61 . . Ck/I AB-D--GH - Slow CLK_OSZI
- 64 . . Ck/I A------H - Slow CLK_030
- 86 . . Ded AB-D--GH - Slow RST
+ 61 . . Ck/I ABCD--GH - Slow CLK_OSZI
+ 64 . . Ck/I A-C----H - Slow CLK_030
+ 86 . . Ded ABCD--GH - Slow RST
----------------------------------------------------------------------
Power : Hi = High
@@ -332,25 +331,24 @@ Output_Signal_List
Pin r e O Output
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
- 48 E 2 COM -------- Low Slow AMIGA_BUS_DATA_DIR
- 34 D 6 DFF * -------- Low Slow AMIGA_BUS_ENABLE
- 20 C 1 COM -------- Low Slow AMIGA_BUS_ENABLE_LOW
- 92 A 1 COM -------- Low Slow AVEC
- 22 C 1 COM -------- Low Slow AVEC_EXP
- 41 E 1 COM -------- Low Slow BERR
- 83 H 2 DFF * -------- Low Slow BGACK_030
- 29 D 2 DFF * -------- Low Slow BG_000
- 47 E 1 COM -------- Low Slow CIIN
- 65 G 1 DFF * -------- Low Slow CLK_DIV_OUT
- 10 B 1 DFF * -------- Low Slow CLK_EXP
- 80 H 1 COM -------- Low Slow DSACK_0_
- 66 G 3 DFF * -------- Low Slow E
- 78 H 2 DFF * -------- Low Slow FPU_CS
- 8 B 3 DFF * -------- Low Slow IPL_030_0_
- 7 B 3 DFF * -------- Low Slow IPL_030_1_
- 9 B 3 DFF * -------- Low Slow IPL_030_2_
- 3 B 1 DFF * -------- Low Slow RESET
- 35 D 2 DFF * -------- Low Slow VMA
+ 48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR
+ 34 D 1 COM -------- Hi Slow AMIGA_BUS_ENABLE
+ 20 C 1 COM -------- Hi Slow AMIGA_BUS_ENABLE_LOW
+ 92 A 1 COM -------- Hi Slow AVEC
+ 22 C 3 DFF * -------- Hi Slow AVEC_EXP
+ 41 E 1 COM -------- Hi Slow BERR
+ 83 H 2 DFF * -------- Hi Slow BGACK_030
+ 29 D 2 DFF * -------- Hi Slow BG_000
+ 47 E 1 COM -------- Hi Slow CIIN
+ 65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT
+ 10 B 1 DFF * -------- Hi Slow CLK_EXP
+ 66 G 3 DFF * -------- Hi Slow E
+ 78 H 2 DFF * -------- Hi Slow FPU_CS
+ 8 B 3 DFF * -------- Hi Slow IPL_030_0_
+ 7 B 3 DFF * -------- Hi Slow IPL_030_1_
+ 9 B 3 DFF * -------- Hi Slow IPL_030_2_
+ 3 B 1 DFF * -------- Hi Slow RESET
+ 35 D 2 DFF * -------- Hi Slow VMA
----------------------------------------------------------------------
Power : Hi = High
@@ -366,16 +364,18 @@ Bidir_Signal_List
Pin r e O Bidir
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
- 69 G 1 DFF * ---D---- Low Slow A0
- 33 D 2 DFF * A---E-GH Low Slow AS_000
- 82 H 4 DFF * ---D---H Low Slow AS_030
- 81 H 2 DFF * ---D---- Low Slow DSACK_1_
- 98 A 7 DFF * ---D---- Low Slow DS_030
- 30 D 1 COM A------- Low Slow DTACK
- 31 D 11 DFF * A-----GH Low Slow LDS_000
- 70 G 1 DFF * ---D---- Low Slow SIZE_0_
- 79 H 2 DFF * ---D---- Low Slow SIZE_1_
- 32 D 7 DFF * A-----GH Low Slow UDS_000
+ 69 G 1 DFF * ---D---- Hi Slow A0
+ 33 D 2 DFF * A---E-GH Hi Slow AS_000
+ 82 H 4 DFF * --CD---H Hi Slow AS_030
+ 81 H 2 DFF * ---D---- Hi Slow DSACK1
+ 98 A 7 DFF * ---D---- Hi Slow DS_030
+ 30 D 1 COM -------H Hi Slow DTACK
+ 31 D 11 DFF * A-----GH Hi Slow LDS_000
+ 71 G 1 COM A--DE--- Hi Slow RW
+ 80 H 1 COM A------- Hi Slow RW_000
+ 70 G 1 DFF * ---D---- Hi Slow SIZE_0_
+ 79 H 2 DFF * ---D---- Hi Slow SIZE_1_
+ 32 D 7 DFF * A-----GH Hi Slow UDS_000
----------------------------------------------------------------------
Power : Hi = High
@@ -391,45 +391,45 @@ Buried_Signal_List
Pin r e O Node
#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
- D7 D 6 DFF * ---D---- Low - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE
- D5 D 2 DFF * AB-D---- Low - RN_AS_000 --> AS_000
- H6 H 4 DFF * A--D--GH Low - RN_AS_030 --> AS_030
- H5 H 2 DFF * A--DE-GH Low - RN_BGACK_030 --> BGACK_030
- D1 D 2 DFF * ---D---- Low - RN_BG_000 --> BG_000
- H11 H 2 DFF * -------H Low - RN_DSACK_1_ --> DSACK_1_
- A5 A 7 DFF * A------- Low - RN_DS_030 --> DS_030
- G2 G 3 DFF * ---D--G- Low - RN_E --> E
- H1 H 2 DFF * --C-E--H Low - RN_FPU_CS --> FPU_CS
- B4 B 3 DFF * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_
- B6 B 3 DFF * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_
- B2 B 3 DFF * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_
- D9 D 11 DFF * ---D---- Low - RN_LDS_000 --> LDS_000
- D6 D 7 DFF * ---D---- Low - RN_UDS_000 --> UDS_000
- D3 D 2 DFF * ---D--G- Low - RN_VMA --> VMA
- B5 B 4 DFF * AB-D---- Low Slow SM_AMIGA_0_
- B10 B 3 DFF * -B-D---H Low Slow SM_AMIGA_1_
- G6 G 3 DFF * -B----G- Low Slow SM_AMIGA_2_
- G7 G 4 DFF * ------G- Low Slow SM_AMIGA_3_
- B7 B 2 DFF * -B-D--G- Low Slow SM_AMIGA_4_
- D2 D 2 DFF * -B-D---- Low Slow SM_AMIGA_5_
- H7 H 2 DFF * A--D---H Low Slow SM_AMIGA_6_
- A11 A 5 DFF * A--D---H Low Slow SM_AMIGA_7_
- B8 B 3 DFF * -B-D--G- Low Slow cpu_est_0_
- G4 G 4 TFF * ---D--G- Low Slow cpu_est_1_
- G5 G 3 DFF * ---D--G- Low Slow cpu_est_2_
- H9 H 8 DFF * A------H Low Slow inst_AS_030_000_SYNC
- D10 D 1 DFF * ---D---- Low Slow inst_BGACK_030_INT_D
- D12 D 1 DFF * AB-D--GH Low Slow inst_CLK_000_D0
- H3 H 1 DFF * -B----GH Low Slow inst_CLK_000_D1
- H12 H 1 DFF * A------H Low Slow inst_CLK_000_D2
- H2 H 1 DFF * AB-----H Low Slow inst_CLK_000_D3
- H8 H 1 DFF * -B-D---H Low Slow inst_CLK_000_D4
- A0 A 5 DFF A------- Low Slow inst_CLK_030_H
- B9 B 3 DFF * -B----G- Low Slow inst_CLK_OUT_PRE_25
- G1 G 1 DFF * AB----G- Low Slow inst_CLK_OUT_PRE_50
- A3 A 1 DFF * -B------ Low Slow inst_CLK_OUT_PRE_50_D
- A1 A 1 DFF * ------G- Low Slow inst_DTACK_D0
- H14 H 1 DFF * ---D--G- Low Slow inst_VPA_D
+ D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000
+ H6 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030
+ C0 C 3 DFF * --CD---- Hi - RN_AVEC_EXP --> AVEC_EXP
+ H4 H 2 DFF * A-CDE-GH Hi - RN_BGACK_030 --> BGACK_030
+ D2 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000
+ H8 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1
+ A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030
+ G2 G 3 DFF * -B-D--G- Hi - RN_E --> E
+ H2 H 2 DFF * ----E--H Hi - RN_FPU_CS --> FPU_CS
+ B4 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_
+ B6 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_
+ B2 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_
+ D8 D 11 DFF * ---D---- Hi - RN_LDS_000 --> LDS_000
+ D6 D 7 DFF * ---D---- Hi - RN_UDS_000 --> UDS_000
+ D1 D 2 DFF * ---D--G- Hi - RN_VMA --> VMA
+ A1 A 2 DFF * AB------ Hi Slow SM_AMIGA_0_
+ H7 H 2 DFF * A------H Hi Slow SM_AMIGA_1_
+ G5 G 3 DFF * --C---GH Hi Slow SM_AMIGA_2_
+ G6 G 4 DFF * ------G- Hi Slow SM_AMIGA_3_
+ D9 D 2 DFF * ---D--G- Hi Slow SM_AMIGA_4_
+ B8 B 2 DFF * -B-D---- Hi Slow SM_AMIGA_5_
+ B9 B 2 DFF * AB------ Hi Slow SM_AMIGA_6_
+ B5 B 4 DFF * -BCD---- Hi Slow SM_AMIGA_7_
+ C2 C 3 DFF * -BCD--G- Hi Slow cpu_est_0_
+ B3 B 4 TFF * -B-D--G- Hi Slow cpu_est_1_
+ G4 G 3 DFF * -B-D--G- Hi Slow cpu_est_2_
+ C3 C 8 DFF * -BC----- Hi Slow inst_AS_030_000_SYNC
+ D10 D 1 DFF * --C----- Hi Slow inst_BGACK_030_INT_D
+ D5 D 1 DFF * ABCD--GH Hi Slow inst_CLK_000_D0
+ D7 D 1 DFF * -BC---GH Hi Slow inst_CLK_000_D1
+ H3 H 1 DFF * -BCD---- Hi Slow inst_CLK_000_D2
+ C4 C 1 DFF * -BC----- Hi Slow inst_CLK_000_D3
+ H5 H 5 DFF A------H Hi Slow inst_CLK_030_H
+ B7 B 3 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_25
+ H9 H 1 DFF * -B-----H Hi Slow inst_CLK_OUT_PRE_50
+ H12 H 1 DFF * -B------ Hi Slow inst_CLK_OUT_PRE_50_D
+ H11 H 1 DFF * ------G- Hi Slow inst_DTACK_D0
+ A3 A 14 DFF * A-----GH Hi Slow inst_RW_000_INT
+ H10 H 1 DFF * ---D--G- Hi Slow inst_VPA_D
----------------------------------------------------------------------
Power : Hi = High
@@ -444,138 +444,141 @@ Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source : Fanout List
-----------------------------------------------------------------------------
- A_21_{ B}: CIIN{ E}
- A_20_{ B}: CIIN{ E}
- A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- A_31_{ C}: CIIN{ E}
- A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- IPL_2_{ H}: IPL_030_2_{ B}
- IPL_1_{ G}: IPL_030_1_{ B}
- IPL_0_{ H}: IPL_030_0_{ B}
- FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- nEXP_SPACE{. }: DSACK_0_{ H} DTACK{ D}AMIGA_BUS_DATA_DIR{ E}
- : SIZE_1_{ H} DSACK_1_{ H} AS_030{ H}
- : DS_030{ A} A0{ G} BG_000{ D}
- :AMIGA_BUS_ENABLE{ D} SIZE_0_{ G}inst_AS_030_000_SYNC{ H}
- : SM_AMIGA_6_{ H} SM_AMIGA_7_{ A}
- BG_030{ D}: BG_000{ D}
- BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
- CLK_030{. }: AS_030{ H} DS_030{ A} FPU_CS{ H}
- :inst_AS_030_000_SYNC{ H} inst_CLK_030_H{ A}
- CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ D}
- DTACK{ E}: inst_DTACK_D0{ A}
- VPA{. }: inst_VPA_D{ H}
- RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B}
- : IPL_030_1_{ B} IPL_030_0_{ B} DSACK_1_{ H}
- : AS_030{ H} AS_000{ D} DS_030{ A}
- : UDS_000{ D} LDS_000{ D} A0{ G}
- : BG_000{ D} BGACK_030{ H} CLK_EXP{ B}
- : FPU_CS{ H} E{ G} VMA{ D}
- : RESET{ B}AMIGA_BUS_ENABLE{ D} SIZE_0_{ G}
- :inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ D} inst_VPA_D{ H}
- :inst_CLK_OUT_PRE_50_D{ A}inst_CLK_000_D0{ D}inst_CLK_000_D1{ H}
- :inst_CLK_000_D2{ H}inst_CLK_000_D4{ H} inst_DTACK_D0{ A}
- :inst_CLK_OUT_PRE_50{ G}inst_CLK_OUT_PRE_25{ B} SM_AMIGA_1_{ B}
- : SM_AMIGA_0_{ B} SM_AMIGA_6_{ H} SM_AMIGA_5_{ D}
- :inst_CLK_000_D3{ H} inst_CLK_030_H{ A} SM_AMIGA_7_{ A}
- : SM_AMIGA_4_{ B} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
- : cpu_est_0_{ B} cpu_est_1_{ G} cpu_est_2_{ G}
- RW{ H}:AMIGA_BUS_DATA_DIR{ E} DS_030{ A} UDS_000{ D}
- : LDS_000{ D}
- A_30_{ C}: CIIN{ E}
- A_29_{ C}: CIIN{ E}
- A_28_{ D}: CIIN{ E}
- A_27_{ D}: CIIN{ E}
A_26_{ D}: CIIN{ E}
A_25_{ D}: CIIN{ E}
A_24_{ D}: CIIN{ E}
A_23_{ I}: CIIN{ E}
+ A_31_{ C}: CIIN{ E}
A_22_{ I}: CIIN{ E}
+ A_21_{ B}: CIIN{ E}
+ A_20_{ B}: CIIN{ E}
+ A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ IPL_2_{ H}: IPL_030_2_{ B}
+ A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ RW_000{ I}: DS_030{ A}inst_RW_000_INT{ A}
+ IPL_1_{ G}: IPL_030_1_{ B}
+ IPL_0_{ H}: IPL_030_0_{ B}
+ FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ nEXP_SPACE{. }: DTACK{ D} AVEC_EXP{ C}AMIGA_BUS_DATA_DIR{ E}
+ : SIZE_1_{ H} AS_030{ H} DS_030{ A}
+ : A0{ G} BG_000{ D} DSACK1{ H}
+ : SIZE_0_{ G}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
+ : SM_AMIGA_6_{ B}
+ BG_030{ D}: BG_000{ D}
+ BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+ CLK_030{. }: AS_030{ H} DS_030{ A} FPU_CS{ H}
+ :inst_AS_030_000_SYNC{ C}inst_RW_000_INT{ A} inst_CLK_030_H{ H}
+ CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ D}
+ DTACK{ E}: inst_DTACK_D0{ H}
+RN_AVEC_EXP{ D}: AVEC_EXP{ C}AMIGA_BUS_ENABLE{ D}
+ VPA{. }: inst_VPA_D{ H}
+ RST{. }: CLK_DIV_OUT{ G} AVEC_EXP{ C} SIZE_1_{ H}
+ : IPL_030_2_{ B} AS_030{ H} IPL_030_1_{ B}
+ : AS_000{ D} IPL_030_0_{ B} DS_030{ A}
+ : UDS_000{ D} LDS_000{ D} A0{ G}
+ : BG_000{ D} BGACK_030{ H} CLK_EXP{ B}
+ : FPU_CS{ H} DSACK1{ H} E{ G}
+ : VMA{ D} RESET{ B} SIZE_0_{ G}
+ :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ D} inst_VPA_D{ H}
+ :inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ D}inst_CLK_000_D1{ D}
+ :inst_CLK_000_D2{ H} inst_DTACK_D0{ H}inst_CLK_OUT_PRE_50{ H}
+ :inst_CLK_OUT_PRE_25{ B} SM_AMIGA_7_{ B} SM_AMIGA_6_{ B}
+ : SM_AMIGA_0_{ A} SM_AMIGA_5_{ B} SM_AMIGA_2_{ G}
+ :inst_RW_000_INT{ A}inst_CLK_000_D3{ C} inst_CLK_030_H{ H}
+ : SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} SM_AMIGA_1_{ H}
+ : cpu_est_0_{ C} cpu_est_1_{ B} cpu_est_2_{ G}
+ RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D}
+ :inst_RW_000_INT{ A}
+ A_30_{ C}: CIIN{ E}
+ A_29_{ C}: CIIN{ E}
+ A_28_{ D}: CIIN{ E}
+ A_27_{ D}: CIIN{ E}
SIZE_1_{ I}: LDS_000{ D}
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
-RN_IPL_030_1_{ C}: IPL_030_1_{ B}
-RN_IPL_030_0_{ C}: IPL_030_0_{ B}
- DSACK_1_{ I}: DTACK{ D}
-RN_DSACK_1_{ I}: DSACK_1_{ H}
- AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D}
- : LDS_000{ D} BG_000{ D} FPU_CS{ H}
- :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}
+ AS_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D}
+ : BG_000{ D} FPU_CS{ H} DSACK1{ H}
+ :inst_AS_030_000_SYNC{ C}
RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H}
: DS_030{ A} A0{ G} SIZE_0_{ G}
- : inst_CLK_030_H{ A}
+ : inst_CLK_030_H{ H}
+RN_IPL_030_1_{ C}: IPL_030_1_{ B}
AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H}
: DS_030{ A} A0{ G} SIZE_0_{ G}
- : inst_CLK_030_H{ A}
- RN_AS_000{ E}: AS_000{ D} VMA{ D} SM_AMIGA_0_{ B}
- : SM_AMIGA_7_{ A}
+ :inst_RW_000_INT{ A} inst_CLK_030_H{ H}
+ RN_AS_000{ E}: AS_000{ D} VMA{ D}
+RN_IPL_030_0_{ C}: IPL_030_0_{ B}
DS_030{ B}: UDS_000{ D} LDS_000{ D}
RN_DS_030{ B}: DS_030{ A}
UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
- : A0{ G} SIZE_0_{ G} inst_CLK_030_H{ A}
+ : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ A}
+ : inst_CLK_030_H{ H}
RN_UDS_000{ E}: UDS_000{ D}
LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
- : A0{ G} SIZE_0_{ G} inst_CLK_030_H{ A}
+ : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ A}
+ : inst_CLK_030_H{ H}
RN_LDS_000{ E}: LDS_000{ D}
A0{ H}: UDS_000{ D} LDS_000{ D}
RN_BG_000{ E}: BG_000{ D}
-RN_BGACK_030{ I}: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H}
+RN_BGACK_030{ I}: RW_000{ H} DTACK{ D} AVEC_EXP{ C}
+ : RW{ G}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H}
: AS_030{ H} AS_000{ D} DS_030{ A}
: UDS_000{ D} LDS_000{ D} A0{ G}
- : BGACK_030{ H}AMIGA_BUS_ENABLE{ D} SIZE_0_{ G}
- :inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ D} inst_CLK_030_H{ A}
- RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H}
- RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ G}
- : SM_AMIGA_2_{ G} cpu_est_1_{ G} cpu_est_2_{ G}
- RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
-RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D}
+ : BGACK_030{ H} SIZE_0_{ G}inst_AS_030_000_SYNC{ C}
+ :inst_BGACK_030_INT_D{ D}inst_RW_000_INT{ A} inst_CLK_030_H{ H}
+ RN_FPU_CS{ I}: BERR{ E} FPU_CS{ H}
+ DSACK1{ I}: DTACK{ D}
+ RN_DSACK1{ I}: DSACK1{ H}
+ RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_2_{ G}
+ : SM_AMIGA_3_{ G} cpu_est_1_{ B} cpu_est_2_{ G}
+ RN_VMA{ E}: VMA{ D} SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
SIZE_0_{ H}: LDS_000{ D}
-inst_AS_030_000_SYNC{ I}:inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} SM_AMIGA_7_{ A}
-inst_BGACK_030_INT_D{ E}:AMIGA_BUS_ENABLE{ D}
- inst_VPA_D{ I}: VMA{ D} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
-inst_CLK_OUT_PRE_50_D{ B}:inst_CLK_OUT_PRE_25{ B}
+inst_AS_030_000_SYNC{ D}: AVEC_EXP{ C}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
+ : SM_AMIGA_6_{ B}
+inst_BGACK_030_INT_D{ E}: AVEC_EXP{ C}
+ inst_VPA_D{ I}: VMA{ D} SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
+inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ B}
inst_CLK_000_D0{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
: UDS_000{ D} LDS_000{ D} BGACK_030{ H}
- : E{ G} VMA{ D}inst_CLK_000_D1{ H}
- : SM_AMIGA_1_{ B} SM_AMIGA_0_{ B} SM_AMIGA_6_{ H}
- : SM_AMIGA_5_{ D} SM_AMIGA_7_{ A} SM_AMIGA_4_{ B}
- : SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} cpu_est_0_{ B}
- : cpu_est_1_{ G} cpu_est_2_{ G}
-inst_CLK_000_D1{ I}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
+ : DSACK1{ H} E{ G} VMA{ D}
+ :inst_AS_030_000_SYNC{ C}inst_CLK_000_D1{ D} SM_AMIGA_7_{ B}
+ : SM_AMIGA_6_{ B} SM_AMIGA_0_{ A} SM_AMIGA_5_{ B}
+ : SM_AMIGA_2_{ G}inst_RW_000_INT{ A} SM_AMIGA_4_{ D}
+ : SM_AMIGA_3_{ G} SM_AMIGA_1_{ H} cpu_est_0_{ C}
+ : cpu_est_1_{ B} cpu_est_2_{ G}
+inst_CLK_000_D1{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
: BGACK_030{ H} E{ G}inst_CLK_000_D2{ H}
- : SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} cpu_est_0_{ B}
- : cpu_est_1_{ G} cpu_est_2_{ G}
-inst_CLK_000_D2{ I}: SM_AMIGA_6_{ H}inst_CLK_000_D3{ H} SM_AMIGA_7_{ A}
-inst_CLK_000_D4{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D}
- : LDS_000{ D}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}
- : SM_AMIGA_1_{ B} SM_AMIGA_0_{ B}
-inst_DTACK_D0{ B}: SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
-inst_CLK_OUT_PRE_50{ H}:inst_CLK_OUT_PRE_50_D{ A}inst_CLK_OUT_PRE_50{ G}inst_CLK_OUT_PRE_25{ B}
+ : SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} cpu_est_0_{ C}
+ : cpu_est_1_{ B} cpu_est_2_{ G}
+inst_CLK_000_D2{ I}: AVEC_EXP{ C} AS_000{ D} UDS_000{ D}
+ : LDS_000{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
+ : SM_AMIGA_6_{ B}inst_CLK_000_D3{ C}
+inst_DTACK_D0{ I}: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
+inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B}
inst_CLK_OUT_PRE_25{ C}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE_25{ B}
-SM_AMIGA_1_{ C}: DSACK_1_{ H}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}
- : SM_AMIGA_1_{ B} SM_AMIGA_0_{ B}
-SM_AMIGA_0_{ C}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_0_{ B} SM_AMIGA_7_{ A}
-SM_AMIGA_6_{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H}
- : SM_AMIGA_5_{ D} SM_AMIGA_7_{ A}
-SM_AMIGA_5_{ E}: AS_000{ D} UDS_000{ D} LDS_000{ D}
- : SM_AMIGA_5_{ D} SM_AMIGA_4_{ B}
-inst_CLK_000_D3{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H}inst_CLK_000_D4{ H}
- : SM_AMIGA_1_{ B} SM_AMIGA_0_{ B} SM_AMIGA_6_{ H}
- : SM_AMIGA_7_{ A}
-inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A}
-SM_AMIGA_7_{ B}: BG_000{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H}
- : SM_AMIGA_7_{ A}
-SM_AMIGA_4_{ C}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ B}
+SM_AMIGA_7_{ C}: AVEC_EXP{ C} BG_000{ D}inst_AS_030_000_SYNC{ C}
+ : SM_AMIGA_7_{ B} SM_AMIGA_6_{ B}
+SM_AMIGA_6_{ C}: SM_AMIGA_6_{ B} SM_AMIGA_5_{ B}inst_RW_000_INT{ A}
+SM_AMIGA_0_{ B}: SM_AMIGA_7_{ B} SM_AMIGA_0_{ A}inst_RW_000_INT{ A}
+SM_AMIGA_5_{ C}: AS_000{ D} UDS_000{ D} LDS_000{ D}
+ : SM_AMIGA_5_{ B} SM_AMIGA_4_{ D}
+SM_AMIGA_2_{ H}: DSACK1{ H}inst_AS_030_000_SYNC{ C} SM_AMIGA_2_{ G}
+ : SM_AMIGA_1_{ H}
+inst_RW_000_INT{ B}: RW_000{ H} RW{ G}inst_RW_000_INT{ A}
+inst_CLK_000_D3{ D}: AVEC_EXP{ C}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B}
+ : SM_AMIGA_6_{ B}
+inst_CLK_030_H{ I}: DS_030{ A} inst_CLK_030_H{ H}
+SM_AMIGA_4_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ D}
: SM_AMIGA_3_{ G}
-SM_AMIGA_3_{ H}: SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
-SM_AMIGA_2_{ H}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ G}
- cpu_est_0_{ C}: E{ G} VMA{ D} cpu_est_0_{ B}
- : cpu_est_1_{ G} cpu_est_2_{ G}
- cpu_est_1_{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ G}
- : SM_AMIGA_2_{ G} cpu_est_1_{ G} cpu_est_2_{ G}
- cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G}
+SM_AMIGA_3_{ H}: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G}
+SM_AMIGA_1_{ I}: SM_AMIGA_0_{ A} SM_AMIGA_1_{ H}
+ cpu_est_0_{ D}: E{ G} VMA{ D} cpu_est_0_{ C}
+ : cpu_est_1_{ B} cpu_est_2_{ G}
+ cpu_est_1_{ C}: E{ G} VMA{ D} SM_AMIGA_2_{ G}
+ : SM_AMIGA_3_{ G} cpu_est_1_{ B} cpu_est_2_{ G}
+ cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ B}
: cpu_est_2_{ G}
-----------------------------------------------------------------------------
@@ -594,11 +597,9 @@ Equations :
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | DS_030
| | | | | AVEC
-| * | S | BS | BR | SM_AMIGA_7_
+| * | S | BS | BR | inst_RW_000_INT
+| * | S | BR | BS | SM_AMIGA_0_
| * | S | BS | BR | RN_DS_030
-| * | S | BR | BR | inst_CLK_030_H
-| * | S | BS | BR | inst_DTACK_D0
-| * | S | BR | BS | inst_CLK_OUT_PRE_50_D
| | | | | A_19_
| | | | | A_16_
| | | | | A_18_
@@ -618,11 +619,11 @@ Equations :
| * | S | BS | BR | IPL_030_1_
| * | S | BR | BS | CLK_EXP
| * | S | BR | BS | RESET
-| * | S | BR | BS | SM_AMIGA_0_
-| * | S | BR | BS | cpu_est_0_
-| * | S | BR | BS | SM_AMIGA_1_
-| * | S | BR | BS | SM_AMIGA_4_
+| * | S | BR | BS | cpu_est_1_
+| * | S | BS | BR | SM_AMIGA_7_
| * | S | BR | BS | inst_CLK_OUT_PRE_25
+| * | S | BR | BS | SM_AMIGA_5_
+| * | S | BR | BS | SM_AMIGA_6_
| * | S | BS | BR | RN_IPL_030_0_
| * | S | BS | BR | RN_IPL_030_1_
| * | S | BS | BR | RN_IPL_030_2_
@@ -632,14 +633,18 @@ Equations :
Block C
-block level set pt :
+block level set pt : !RST
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
-| | | | | AVEC_EXP
+| * | S | BS | BR | AVEC_EXP
| | | | | AMIGA_BUS_ENABLE_LOW
+| * | S | BR | BS | cpu_est_0_
+| * | S | BS | BR | inst_AS_030_000_SYNC
+| * | S | BS | BR | RN_AVEC_EXP
+| * | S | BS | BR | inst_CLK_000_D3
| | | | | BG_030
| | | | | A_24_
| | | | | A_25_
@@ -659,17 +664,17 @@ Equations :
| * | S | BS | BR | LDS_000
| * | S | BS | BR | UDS_000
| | | | | DTACK
-| * | S | BS | BR | AMIGA_BUS_ENABLE
| * | S | BS | BR | VMA
| * | S | BS | BR | BG_000
+| | | | | AMIGA_BUS_ENABLE
| * | S | BS | BR | inst_CLK_000_D0
-| * | S | BS | BR | RN_AS_000
+| * | S | BS | BR | inst_CLK_000_D1
| * | S | BS | BR | RN_VMA
-| * | S | BR | BS | SM_AMIGA_5_
+| * | S | BR | BS | SM_AMIGA_4_
| * | S | BS | BR | RN_LDS_000
| * | S | BS | BR | RN_UDS_000
-| * | S | BS | BR | RN_AMIGA_BUS_ENABLE
| * | S | BS | BR | RN_BG_000
+| * | S | BS | BR | RN_AS_000
| * | S | BS | BR | inst_BGACK_030_INT_D
| | | | | BGACK_000
@@ -706,17 +711,15 @@ Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
+| | | | | RW
| * | S | BR | BS | SIZE_0_
| * | S | BR | BS | A0
| * | S | BS | BR | E
| * | S | BS | BR | CLK_DIV_OUT
-| * | S | BS | BR | inst_CLK_OUT_PRE_50
-| * | S | BS | BR | cpu_est_1_
| * | S | BS | BR | RN_E
| * | S | BS | BR | cpu_est_2_
| * | S | BS | BR | SM_AMIGA_2_
| * | S | BS | BR | SM_AMIGA_3_
-| | | | | RW
| | | | | IPL_2_
| | | | | IPL_0_
@@ -729,22 +732,22 @@ Equations :
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | AS_030
-| * | S | BS | BR | DSACK_1_
+| * | S | BS | BR | DSACK1
| * | S | BS | BR | SIZE_1_
+| | | | | RW_000
| * | S | BS | BR | BGACK_030
| * | S | BS | BR | FPU_CS
-| | | | | DSACK_0_
| * | S | BS | BR | RN_BGACK_030
| * | S | BS | BR | RN_AS_030
-| * | S | BS | BR | RN_FPU_CS
-| * | S | BR | BS | SM_AMIGA_6_
-| * | S | BS | BR | inst_CLK_000_D3
-| * | S | BS | BR | inst_CLK_000_D4
-| * | S | BS | BR | inst_CLK_000_D1
-| * | S | BS | BR | inst_AS_030_000_SYNC
| * | S | BS | BR | inst_CLK_000_D2
+| * | S | BR | BR | inst_CLK_030_H
+| * | S | BS | BR | RN_FPU_CS
+| * | S | BR | BS | SM_AMIGA_1_
+| * | S | BR | BS | inst_CLK_OUT_PRE_50
| * | S | BS | BR | inst_VPA_D
-| * | S | BS | BR | RN_DSACK_1_
+| * | S | BS | BR | RN_DSACK1
+| * | S | BS | BR | inst_DTACK_D0
+| * | S | BR | BS | inst_CLK_OUT_PRE_50_D
| | | | | A_22_
| | | | | A_23_
@@ -763,22 +766,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx A0 LDS_000 pin 31 mx A17 inst_CLK_000_D0 mcell D12
+mx A0 RST pin 86 mx A17 ... ...
mx A1 ... ... mx A18 ... ...
-mx A2 RN_DS_030 mcell A5 mx A19 ... ...
-mx A3 ... ... mx A20 CLK_030 pin 64
-mx A4 inst_CLK_030_H mcell A0 mx A21 RST pin 86
-mx A5inst_AS_030_000_SYNC mcell H9 mx A22 ... ...
-mx A6 ... ... mx A23 AS_000 pin 33
-mx A7 RN_AS_030 mcell H6 mx A24inst_CLK_OUT_PRE_50 mcell G1
-mx A8 inst_CLK_000_D2 mcell H12 mx A25 RW pin 71
-mx A9 DTACK pin 30 mx A26 ... ...
-mx A10 ... ... mx A27 RN_BGACK_030 mcell H5
-mx A11 RN_AS_000 mcell D5 mx A28 SM_AMIGA_0_ mcell B5
-mx A12 UDS_000 pin 32 mx A29 SM_AMIGA_6_ mcell H7
-mx A13 SM_AMIGA_7_ mcell A11 mx A30 ... ...
-mx A14 inst_CLK_000_D3 mcell H2 mx A31 ... ...
-mx A15 nEXP_SPACE pin 14 mx A32 ... ...
+mx A2 ... ... mx A19 ... ...
+mx A3 ... ... mx A20 RN_BGACK_030 mcell H4
+mx A4 CLK_030 pin 64 mx A21 RN_AS_030 mcell H6
+mx A5 nEXP_SPACE pin 14 mx A22 ... ...
+mx A6 SM_AMIGA_6_ mcell B9 mx A23 AS_000 pin 33
+mx A7 SM_AMIGA_1_ mcell H7 mx A24 LDS_000 pin 31
+mx A8 RW pin 71 mx A25 inst_RW_000_INT mcell A3
+mx A9 SM_AMIGA_0_ mcell A1 mx A26 ... ...
+mx A10 ... ... mx A27 ... ...
+mx A11 inst_CLK_000_D0 mcell D5 mx A28 RW_000 pin 80
+mx A12 UDS_000 pin 32 mx A29 ... ...
+mx A13 inst_CLK_030_H mcell H5 mx A30 ... ...
+mx A14 ... ... mx A31 ... ...
+mx A15 RN_DS_030 mcell A0 mx A32 ... ...
mx A16 ... ...
----------------------------------------------------------------------------
@@ -787,23 +790,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx B0 IPL_0_ pin 67 mx B17 inst_CLK_000_D0 mcell D12
-mx B1 SM_AMIGA_4_ mcell B7 mx B18 ... ...
+mx B0 RST pin 86 mx B17 SM_AMIGA_5_ mcell B8
+mx B1inst_CLK_OUT_PRE_25 mcell B7 mx B18 inst_CLK_000_D2 mcell H3
mx B2 RN_IPL_030_1_ mcell B6 mx B19 ... ...
mx B3 IPL_1_ pin 56 mx B20 ... ...
-mx B4 IPL_2_ pin 68 mx B21 RST pin 86
-mx B5 SM_AMIGA_2_ mcell G6 mx B22 ... ...
-mx B6inst_CLK_OUT_PRE_50_D mcell A3 mx B23 ... ...
-mx B7 RN_AS_000 mcell D5 mx B24inst_CLK_OUT_PRE_50 mcell G1
-mx B8 cpu_est_0_ mcell B8 mx B25 ... ...
-mx B9 ... ... mx B26 ... ...
+mx B4 IPL_2_ pin 68 mx B21 cpu_est_2_ mcell G4
+mx B5 nEXP_SPACE pin 14 mx B22 cpu_est_0_ mcell C2
+mx B6 SM_AMIGA_6_ mcell B9 mx B23 RN_E mcell G2
+mx B7 inst_CLK_000_D0 mcell D5 mx B24 ... ...
+mx B8 inst_CLK_000_D1 mcell D7 mx B25 ... ...
+mx B9 SM_AMIGA_0_ mcell A1 mx B26 ... ...
mx B10 RN_IPL_030_2_ mcell B2 mx B27 RN_IPL_030_0_ mcell B4
-mx B11 inst_CLK_000_D1 mcell H3 mx B28 SM_AMIGA_0_ mcell B5
-mx B12 SM_AMIGA_1_ mcell B10 mx B29 ... ...
-mx B13 inst_CLK_000_D4 mcell H8 mx B30 ... ...
-mx B14 inst_CLK_000_D3 mcell H2 mx B31inst_CLK_OUT_PRE_25 mcell B9
-mx B15 ... ... mx B32 ... ...
-mx B16 SM_AMIGA_5_ mcell D2
+mx B11inst_CLK_OUT_PRE_50 mcell H9 mx B28 SM_AMIGA_7_ mcell B5
+mx B12inst_AS_030_000_SYNC mcell C3 mx B29 ... ...
+mx B13 cpu_est_1_ mcell B3 mx B30 ... ...
+mx B14 inst_CLK_000_D3 mcell C4 mx B31 ... ...
+mx B15inst_CLK_OUT_PRE_50_D mcell H12 mx B32 ... ...
+mx B16 IPL_0_ pin 67
----------------------------------------------------------------------------
@@ -811,21 +814,21 @@ BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx C0 ... ... mx C17 ... ...
-mx C1 ... ... mx C18 ... ...
-mx C2 ... ... mx C19 ... ...
-mx C3 ... ... mx C20 ... ...
-mx C4 ... ... mx C21 ... ...
-mx C5 ... ... mx C22 ... ...
-mx C6 ... ... mx C23 ... ...
-mx C7 ... ... mx C24 ... ...
-mx C8 ... ... mx C25 ... ...
-mx C9 ... ... mx C26 ... ...
-mx C10 RN_FPU_CS mcell H1 mx C27 ... ...
-mx C11 ... ... mx C28 ... ...
-mx C12 ... ... mx C29 ... ...
-mx C13 ... ... mx C30 ... ...
-mx C14 ... ... mx C31 ... ...
+mx C0 RST pin 86 mx C17 A_18_ pin 95
+mx C1 FC_1_ pin 58 mx C18 BGACK_000 pin 28
+mx C2inst_BGACK_030_INT_D mcell D10 mx C19 AS_030 pin 82
+mx C3 SM_AMIGA_2_ mcell G5 mx C20 CLK_030 pin 64
+mx C4inst_AS_030_000_SYNC mcell C3 mx C21 ... ...
+mx C5 nEXP_SPACE pin 14 mx C22 cpu_est_0_ mcell C2
+mx C6 FC_0_ pin 57 mx C23 RN_BGACK_030 mcell H4
+mx C7 inst_CLK_000_D0 mcell D5 mx C24 ... ...
+mx C8 A_17_ pin 59 mx C25 ... ...
+mx C9 RN_AVEC_EXP mcell C0 mx C26 ... ...
+mx C10 inst_CLK_000_D2 mcell H3 mx C27 ... ...
+mx C11 A_16_ pin 96 mx C28 SM_AMIGA_7_ mcell B5
+mx C12 A_19_ pin 97 mx C29 ... ...
+mx C13 inst_CLK_000_D1 mcell D7 mx C30 ... ...
+mx C14 inst_CLK_000_D3 mcell C4 mx C31 ... ...
mx C15 ... ... mx C32 ... ...
mx C16 ... ...
----------------------------------------------------------------------------
@@ -835,23 +838,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx D0 A0 pin 69 mx D17 RN_BG_000 mcell D1
-mx D1 SM_AMIGA_4_ mcell B7 mx D18 DS_030 pin 98
-mx D2 cpu_est_1_ mcell G4 mx D19 AS_030 pin 82
-mx D3 CLK_000 pin 11 mx D20inst_BGACK_030_INT_D mcell D10
+mx D0 A0 pin 69 mx D17 RN_VMA mcell D1
+mx D1 ... ... mx D18 inst_VPA_D mcell H10
+mx D2 cpu_est_2_ mcell G4 mx D19 AS_030 pin 82
+mx D3 CLK_000 pin 11 mx D20 RN_BGACK_030 mcell H4
mx D4 BG_030 pin 21 mx D21 RST pin 86
-mx D5 inst_CLK_000_D0 mcell D12 mx D22 inst_VPA_D mcell H14
+mx D5 DS_030 pin 98 mx D22 cpu_est_0_ mcell C2
mx D6 SIZE_1_ pin 79 mx D23 RN_E mcell G2
-mx D7 RN_LDS_000 mcell D9 mx D24 RN_AS_000 mcell D5
-mx D8 cpu_est_0_ mcell B8 mx D25 inst_CLK_000_D4 mcell H8
-mx D9 RN_VMA mcell D3 mx D26 SM_AMIGA_7_ mcell A11
-mx D10 DSACK_1_ pin 81 mx D27 RN_BGACK_030 mcell H5
-mx D11 RW pin 71 mx D28 SM_AMIGA_5_ mcell D2
-mx D12 SM_AMIGA_1_ mcell B10 mx D29 SM_AMIGA_6_ mcell H7
-mx D13RN_AMIGA_BUS_ENABLE mcell D7 mx D30 RN_AS_030 mcell H6
-mx D14 SIZE_0_ pin 70 mx D31 SM_AMIGA_0_ mcell B5
-mx D15 nEXP_SPACE pin 14 mx D32 cpu_est_2_ mcell G5
-mx D16 RN_UDS_000 mcell D6
+mx D7 RN_AS_030 mcell H6 mx D24 inst_CLK_000_D0 mcell D5
+mx D8 SM_AMIGA_5_ mcell B8 mx D25 RW pin 71
+mx D9 RN_AVEC_EXP mcell C0 mx D26 ... ...
+mx D10 RN_AS_000 mcell D4 mx D27 ... ...
+mx D11 inst_CLK_000_D2 mcell H3 mx D28 RN_BG_000 mcell D2
+mx D12 SM_AMIGA_4_ mcell D9 mx D29 ... ...
+mx D13 cpu_est_1_ mcell B3 mx D30 RN_UDS_000 mcell D6
+mx D14 SIZE_0_ pin 70 mx D31 SM_AMIGA_7_ mcell B5
+mx D15 nEXP_SPACE pin 14 mx D32 DSACK1 pin 81
+mx D16 RN_LDS_000 mcell D8
----------------------------------------------------------------------------
@@ -859,21 +862,21 @@ BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx E0 AS_000 pin 33 mx E17 A_26_ pin 17
+mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17
mx E1 A_31_ pin 4 mx E18 ... ...
mx E2 ... ... mx E19 ... ...
mx E3 A_27_ pin 16 mx E20 ... ...
mx E4 A_29_ pin 6 mx E21 nEXP_SPACE pin 14
mx E5 A_24_ pin 19 mx E22 ... ...
-mx E6 ... ... mx E23 ... ...
+mx E6 ... ... mx E23 AS_000 pin 33
mx E7 A_28_ pin 15 mx E24 ... ...
mx E8 A_22_ pin 85 mx E25 RW pin 71
mx E9 A_30_ pin 5 mx E26 ... ...
-mx E10 RN_FPU_CS mcell H1 mx E27 ... ...
+mx E10 ... ... mx E27 ... ...
mx E11 A_23_ pin 84 mx E28 ... ...
mx E12 A_25_ pin 18 mx E29 A_20_ pin 93
-mx E13 RN_BGACK_030 mcell H5 mx E30 ... ...
-mx E14 ... ... mx E31 ... ...
+mx E13 ... ... mx E30 ... ...
+mx E14 RN_FPU_CS mcell H2 mx E31 ... ...
mx E15 A_21_ pin 94 mx E32 ... ...
mx E16 ... ...
----------------------------------------------------------------------------
@@ -883,20 +886,20 @@ BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx G0 LDS_000 pin 31 mx G17 cpu_est_0_ mcell B8
-mx G1 SM_AMIGA_4_ mcell B7 mx G18 ... ...
-mx G2 inst_VPA_D mcell H14 mx G19 ... ...
-mx G3 cpu_est_2_ mcell G5 mx G20 ... ...
-mx G4 RN_E mcell G2 mx G21 RST pin 86
-mx G5 inst_CLK_000_D0 mcell D12 mx G22 ... ...
-mx G6inst_CLK_OUT_PRE_25 mcell B9 mx G23 SM_AMIGA_2_ mcell G6
-mx G7 RN_AS_030 mcell H6 mx G24inst_CLK_OUT_PRE_50 mcell G1
-mx G8 SM_AMIGA_3_ mcell G7 mx G25 ... ...
-mx G9 inst_DTACK_D0 mcell A1 mx G26 AS_000 pin 33
-mx G10 inst_CLK_000_D1 mcell H3 mx G27 RN_BGACK_030 mcell H5
-mx G11 cpu_est_1_ mcell G4 mx G28 ... ...
-mx G12 UDS_000 pin 32 mx G29 ... ...
-mx G13 RN_VMA mcell D3 mx G30 ... ...
+mx G0 RST pin 86 mx G17 ... ...
+mx G1 inst_DTACK_D0 mcell H11 mx G18 inst_VPA_D mcell H10
+mx G2 RN_VMA mcell D1 mx G19 ... ...
+mx G3 SM_AMIGA_2_ mcell G5 mx G20 RN_BGACK_030 mcell H4
+mx G4 RN_E mcell G2 mx G21 RN_AS_030 mcell H6
+mx G5 cpu_est_1_ mcell B3 mx G22 cpu_est_0_ mcell C2
+mx G6 inst_RW_000_INT mcell A3 mx G23 SM_AMIGA_3_ mcell G6
+mx G7 inst_CLK_000_D0 mcell D5 mx G24inst_CLK_OUT_PRE_25 mcell B7
+mx G8 UDS_000 pin 32 mx G25 ... ...
+mx G9 ... ... mx G26 AS_000 pin 33
+mx G10 ... ... mx G27 LDS_000 pin 31
+mx G11 cpu_est_2_ mcell G4 mx G28 ... ...
+mx G12 SM_AMIGA_4_ mcell D9 mx G29 ... ...
+mx G13 inst_CLK_000_D1 mcell D7 mx G30 ... ...
mx G14 ... ... mx G31 ... ...
mx G15 nEXP_SPACE pin 14 mx G32 ... ...
mx G16 ... ...
@@ -907,22 +910,22 @@ BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx H0 RST pin 86 mx H17 FC_0_ pin 57
-mx H1 FC_1_ pin 58 mx H18 inst_CLK_000_D1 mcell H3
-mx H2 SM_AMIGA_1_ mcell B10 mx H19 RN_FPU_CS mcell H1
-mx H3 inst_CLK_000_D4 mcell H8 mx H20 SM_AMIGA_6_ mcell H7
-mx H4 CLK_030 pin 64 mx H21 RN_AS_030 mcell H6
-mx H5inst_AS_030_000_SYNC mcell H9 mx H22 ... ...
-mx H6 A_16_ pin 96 mx H23 AS_000 pin 33
-mx H7 SM_AMIGA_7_ mcell A11 mx H24 LDS_000 pin 31
-mx H8 UDS_000 pin 32 mx H25 ... ...
-mx H9 AS_030 pin 82 mx H26 ... ...
-mx H10 VPA pin 36 mx H27 RN_BGACK_030 mcell H5
-mx H11 inst_CLK_000_D0 mcell D12 mx H28 inst_CLK_000_D3 mcell H2
-mx H12 A_19_ pin 97 mx H29 inst_CLK_000_D2 mcell H12
-mx H13 A_17_ pin 59 mx H30 ... ...
-mx H14 RN_DSACK_1_ mcell H11 mx H31 A_18_ pin 95
-mx H15 nEXP_SPACE pin 14 mx H32 BGACK_000 pin 28
+mx H0 LDS_000 pin 31 mx H17 FC_0_ pin 57
+mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28
+mx H2 ... ... mx H19 AS_030 pin 82
+mx H3 RN_DSACK1 mcell H8 mx H20 CLK_030 pin 64
+mx H4 A_18_ pin 95 mx H21 RST pin 86
+mx H5inst_CLK_OUT_PRE_50 mcell H9 mx H22 SM_AMIGA_2_ mcell G5
+mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4
+mx H7 SM_AMIGA_1_ mcell H7 mx H24 inst_CLK_000_D0 mcell D5
+mx H8 inst_CLK_000_D1 mcell D7 mx H25 inst_RW_000_INT mcell A3
+mx H9 DTACK pin 30 mx H26 AS_000 pin 33
+mx H10 VPA pin 36 mx H27 A_17_ pin 59
+mx H11 A_16_ pin 96 mx H28 ... ...
+mx H12 UDS_000 pin 32 mx H29 ... ...
+mx H13 inst_CLK_030_H mcell H5 mx H30 RN_AS_030 mcell H6
+mx H14 RN_FPU_CS mcell H2 mx H31 ... ...
+mx H15 nEXP_SPACE pin 14 mx H32 ... ...
mx H16 ... ...
----------------------------------------------------------------------------
@@ -938,8 +941,8 @@ PostFit_Equations
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
- 1 0 1 Pin DSACK_0_
- 1 1 1 Pin DSACK_0_.OE
+ 1 1 1 Pin RW_000
+ 1 1 1 Pin RW_000.OE
0 0 1 Pin BERR
1 1 1 Pin BERR.OE
1 1 1 Pin CLK_DIV_OUT.AR
@@ -948,8 +951,12 @@ PostFit_Equations
1 1 1 Pin DTACK
1 3 1 Pin DTACK.OE
1 0 1 Pin AVEC
- 0 0 1 Pin AVEC_EXP
- 1 1 1 Pin AVEC_EXP.OE
+ 3 8 1 Pin AVEC_EXP.D-
+ 1 1 1 Pin AVEC_EXP.AP
+ 1 1 1 Pin AVEC_EXP.C
+ 1 1 1 Pin RW
+ 1 1 1 Pin RW.OE
+ 1 1 1 Pin AMIGA_BUS_ENABLE
2 4 1 Pin AMIGA_BUS_DATA_DIR
1 0 1 Pin AMIGA_BUS_ENABLE_LOW
1 4 1 Pin CIIN
@@ -961,24 +968,20 @@ PostFit_Equations
3 4 1 Pin IPL_030_2_.D
1 1 1 Pin IPL_030_2_.AP
1 1 1 Pin IPL_030_2_.C
- 3 4 1 Pin IPL_030_1_.D
- 1 1 1 Pin IPL_030_1_.AP
- 1 1 1 Pin IPL_030_1_.C
- 3 4 1 Pin IPL_030_0_.D
- 1 1 1 Pin IPL_030_0_.AP
- 1 1 1 Pin IPL_030_0_.C
- 1 1 1 Pin DSACK_1_.OE
- 2 5 1 Pin DSACK_1_.D-
- 1 1 1 Pin DSACK_1_.AP
- 1 1 1 Pin DSACK_1_.C
1 3 1 Pin AS_030.OE
4 6 1 Pin AS_030.D
1 1 1 Pin AS_030.AP
1 1 1 Pin AS_030.C
+ 3 4 1 Pin IPL_030_1_.D
+ 1 1 1 Pin IPL_030_1_.AP
+ 1 1 1 Pin IPL_030_1_.C
1 1 1 Pin AS_000.OE
2 4 1 Pin AS_000.D-
1 1 1 Pin AS_000.AP
1 1 1 Pin AS_000.C
+ 3 4 1 Pin IPL_030_0_.D
+ 1 1 1 Pin IPL_030_0_.AP
+ 1 1 1 Pin IPL_030_0_.C
1 3 1 Pin DS_030.OE
7 9 1 Pin DS_030.D
1 1 1 Pin DS_030.AP
@@ -1007,6 +1010,10 @@ PostFit_Equations
2 10 1 Pin FPU_CS.D-
1 1 1 Pin FPU_CS.AP
1 1 1 Pin FPU_CS.C
+ 1 1 1 Pin DSACK1.OE
+ 2 4 1 Pin DSACK1.D-
+ 1 1 1 Pin DSACK1.AP
+ 1 1 1 Pin DSACK1.C
3 6 1 PinX1 E.D.X1
1 1 1 PinX2 E.D.X2
1 1 1 Pin E.AR
@@ -1018,9 +1025,6 @@ PostFit_Equations
1 1 1 Pin RESET.AR
1 0 1 Pin RESET.D
1 1 1 Pin RESET.C
- 6 9 1 Pin AMIGA_BUS_ENABLE.D-
- 1 1 1 Pin AMIGA_BUS_ENABLE.AP
- 1 1 1 Pin AMIGA_BUS_ENABLE.C
1 3 1 Pin SIZE_0_.OE
1 4 1 Pin SIZE_0_.D-
1 1 1 Pin SIZE_0_.AP
@@ -1046,9 +1050,6 @@ PostFit_Equations
1 1 1 Node inst_CLK_000_D2.D
1 1 1 Node inst_CLK_000_D2.AP
1 1 1 Node inst_CLK_000_D2.C
- 1 1 1 Node inst_CLK_000_D4.D
- 1 1 1 Node inst_CLK_000_D4.AP
- 1 1 1 Node inst_CLK_000_D4.C
1 1 1 Node inst_DTACK_D0.D
1 1 1 Node inst_DTACK_D0.AP
1 1 1 Node inst_DTACK_D0.C
@@ -1058,35 +1059,38 @@ PostFit_Equations
1 1 1 Node inst_CLK_OUT_PRE_25.AR
3 3 1 Node inst_CLK_OUT_PRE_25.D
1 1 1 Node inst_CLK_OUT_PRE_25.C
- 1 1 1 Node SM_AMIGA_1_.AR
- 3 5 1 Node SM_AMIGA_1_.D
- 1 1 1 Node SM_AMIGA_1_.C
- 1 1 1 Node SM_AMIGA_0_.AR
- 4 6 1 Node SM_AMIGA_0_.D
- 1 1 1 Node SM_AMIGA_0_.C
+ 4 7 1 Node SM_AMIGA_7_.D-
+ 1 1 1 Node SM_AMIGA_7_.AP
+ 1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node SM_AMIGA_6_.AR
2 7 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
+ 1 1 1 Node SM_AMIGA_0_.AR
+ 2 3 1 Node SM_AMIGA_0_.D
+ 1 1 1 Node SM_AMIGA_0_.C
1 1 1 Node SM_AMIGA_5_.AR
2 3 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
+ 1 1 1 Node SM_AMIGA_2_.AR
+ 3 9 1 Node SM_AMIGA_2_.D
+ 1 1 1 Node SM_AMIGA_2_.C
+ 14 11 1 Node inst_RW_000_INT.D-
+ 1 1 1 Node inst_RW_000_INT.AP
+ 1 1 1 Node inst_RW_000_INT.C
1 1 1 Node inst_CLK_000_D3.D
1 1 1 Node inst_CLK_000_D3.AP
1 1 1 Node inst_CLK_000_D3.C
5 8 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
- 5 9 1 Node SM_AMIGA_7_.D
- 1 1 1 Node SM_AMIGA_7_.AP
- 1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node SM_AMIGA_4_.AR
2 3 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
1 1 1 Node SM_AMIGA_3_.AR
4 9 1 Node SM_AMIGA_3_.D-
1 1 1 Node SM_AMIGA_3_.C
- 1 1 1 Node SM_AMIGA_2_.AR
- 3 9 1 Node SM_AMIGA_2_.D
- 1 1 1 Node SM_AMIGA_2_.C
+ 1 1 1 Node SM_AMIGA_1_.AR
+ 2 3 1 Node SM_AMIGA_1_.D
+ 1 1 1 Node SM_AMIGA_1_.C
1 1 1 Node cpu_est_0_.AR
3 3 1 Node cpu_est_0_.D
1 1 1 Node cpu_est_0_.C
@@ -1098,7 +1102,7 @@ PostFit_Equations
1 1 1 Node cpu_est_2_.AR
1 1 1 Node cpu_est_2_.C
=========
- 240 P-Term Total: 240
+ 248 P-Term Total: 248
Total Pins: 59
Total Nodes: 24
Average P-Term/Output: 2
@@ -1106,9 +1110,9 @@ PostFit_Equations
Equations:
-DSACK_0_ = (1);
+RW_000 = (inst_RW_000_INT.Q);
-DSACK_0_.OE = (nEXP_SPACE);
+RW_000.OE = (BGACK_030.Q);
BERR = (0);
@@ -1120,18 +1124,28 @@ CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q);
CLK_DIV_OUT.C = (CLK_OSZI);
-DTACK = (DSACK_1_.PIN);
+DTACK = (DSACK1.PIN);
DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
AVEC = (1);
-AVEC_EXP = (0);
+!AVEC_EXP.D = (!BGACK_030.Q
+ # inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !AVEC_EXP
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
-AVEC_EXP.OE = (!FPU_CS.Q);
+AVEC_EXP.AP = (!RST);
-AMIGA_BUS_DATA_DIR = (!RW & BGACK_030.Q
- # !nEXP_SPACE & RW & !BGACK_030.Q & !AS_000.PIN);
+AVEC_EXP.C = (CLK_OSZI);
+
+RW = (inst_RW_000_INT.Q);
+
+RW.OE = (!BGACK_030.Q);
+
+AMIGA_BUS_ENABLE = (AVEC_EXP);
+
+AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
+ # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);
AMIGA_BUS_ENABLE_LOW = (1);
@@ -1148,39 +1162,14 @@ SIZE_1_.AP = (!RST);
SIZE_1_.C = (CLK_OSZI);
-IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q
- # IPL_030_2_.Q & inst_CLK_000_D1.Q
+IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
+ # inst_CLK_000_D1.Q & IPL_030_2_.Q
# IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
IPL_030_2_.AP = (!RST);
IPL_030_2_.C = (CLK_OSZI);
-IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D0.Q
- # IPL_030_1_.Q & inst_CLK_000_D1.Q
- # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
-
-IPL_030_1_.AP = (!RST);
-
-IPL_030_1_.C = (CLK_OSZI);
-
-IPL_030_0_.D = (IPL_030_0_.Q & !inst_CLK_000_D0.Q
- # IPL_030_0_.Q & inst_CLK_000_D1.Q
- # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
-
-IPL_030_0_.AP = (!RST);
-
-IPL_030_0_.C = (CLK_OSZI);
-
-DSACK_1_.OE = (nEXP_SPACE);
-
-!DSACK_1_.D = (!DSACK_1_.Q & !AS_030.PIN
- # !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q & inst_CLK_000_D3.Q);
-
-DSACK_1_.AP = (!RST);
-
-DSACK_1_.C = (CLK_OSZI);
-
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
AS_030.D = (BGACK_030.Q
@@ -1192,24 +1181,40 @@ AS_030.AP = (!RST);
AS_030.C = (CLK_OSZI);
+IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
+ # inst_CLK_000_D1.Q & IPL_030_1_.Q
+ # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_1_.AP = (!RST);
+
+IPL_030_1_.C = (CLK_OSZI);
+
AS_000.OE = (BGACK_030.Q);
-!AS_000.D = (inst_CLK_000_D4.Q & SM_AMIGA_5_.Q
+!AS_000.D = (inst_CLK_000_D2.Q & SM_AMIGA_5_.Q
# !AS_000.Q & !AS_030.PIN);
AS_000.AP = (!RST);
AS_000.C = (CLK_OSZI);
+IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
+ # inst_CLK_000_D1.Q & IPL_030_0_.Q
+ # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_0_.AP = (!RST);
+
+IPL_030_0_.C = (CLK_OSZI);
+
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
DS_030.D = (BGACK_030.Q
# AS_000.PIN
- # RW & AS_030.Q
+ # AS_030.Q & RW_000.PIN
# UDS_000.PIN & LDS_000.PIN
# !CLK_030 & AS_030.Q & inst_CLK_030_H.Q
- # CLK_030 & !RW & DS_030.Q
- # !RW & !inst_CLK_030_H.Q & DS_030.Q);
+ # CLK_030 & DS_030.Q & !RW_000.PIN
+ # !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
DS_030.AP = (!RST);
@@ -1218,12 +1223,12 @@ DS_030.C = (CLK_OSZI);
UDS_000.OE = (BGACK_030.Q);
!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN
- # !RW & !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN
- # RW & !inst_CLK_000_D4.Q & !UDS_000.Q & !AS_030.PIN
- # RW & !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN
- # !RW & !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN);
+ # !inst_CLK_000_D2.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
+ # !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN
+ # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN
+ # !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN);
UDS_000.AP = (!RST);
@@ -1232,16 +1237,16 @@ UDS_000.C = (CLK_OSZI);
LDS_000.OE = (BGACK_030.Q);
!LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN
- # !RW & !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN
- # RW & !inst_CLK_000_D4.Q & !LDS_000.Q & !AS_030.PIN
- # RW & !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN
- # !RW & !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN
- # RW & inst_CLK_000_D4.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN
- # !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN);
+ # !inst_CLK_000_D2.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
+ # !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN
+ # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN
+ # !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN
+ # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN & !RW.PIN);
LDS_000.AP = (!RST);
@@ -1282,6 +1287,15 @@ FPU_CS.AP = (!RST);
FPU_CS.C = (CLK_OSZI);
+DSACK1.OE = (nEXP_SPACE);
+
+!DSACK1.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # !DSACK1.Q & !AS_030.PIN);
+
+DSACK1.AP = (!RST);
+
+DSACK1.C = (CLK_OSZI);
+
E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q
# inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q);
@@ -1307,17 +1321,6 @@ RESET.D = (1);
RESET.C = (CLK_OSZI);
-!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q
- # nEXP_SPACE & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D4.Q & SM_AMIGA_6_.Q
- # !nEXP_SPACE & inst_BGACK_030_INT_D.Q & !AMIGA_BUS_ENABLE.Q & !AS_030.PIN
- # inst_BGACK_030_INT_D.Q & !SM_AMIGA_6_.Q & !AMIGA_BUS_ENABLE.Q & !AS_030.PIN
- # !nEXP_SPACE & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !AMIGA_BUS_ENABLE.Q
- # inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !AMIGA_BUS_ENABLE.Q);
-
-AMIGA_BUS_ENABLE.AP = (!RST);
-
-AMIGA_BUS_ENABLE.C = (CLK_OSZI);
-
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
@@ -1330,9 +1333,9 @@ inst_AS_030_000_SYNC.D = (AS_030.PIN
# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
# !CLK_030 & inst_AS_030_000_SYNC.Q
# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
- # !nEXP_SPACE & SM_AMIGA_6_.Q
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
- # !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q & inst_CLK_000_D3.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # !nEXP_SPACE & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q
# FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
inst_AS_030_000_SYNC.AP = (!RST);
@@ -1375,12 +1378,6 @@ inst_CLK_000_D2.AP = (!RST);
inst_CLK_000_D2.C = (CLK_OSZI);
-inst_CLK_000_D4.D = (inst_CLK_000_D3.Q);
-
-inst_CLK_000_D4.AP = (!RST);
-
-inst_CLK_000_D4.C = (CLK_OSZI);
-
inst_DTACK_D0.D = (DTACK.PIN);
inst_DTACK_D0.AP = (!RST);
@@ -1401,30 +1398,29 @@ inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
-SM_AMIGA_1_.AR = (!RST);
+!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q
+ # !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D3.Q);
-SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q
- # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
- # !inst_CLK_000_D4.Q & SM_AMIGA_1_.Q & inst_CLK_000_D3.Q);
+SM_AMIGA_7_.AP = (!RST);
-SM_AMIGA_1_.C = (CLK_OSZI);
+SM_AMIGA_7_.C = (CLK_OSZI);
+
+SM_AMIGA_6_.AR = (!RST);
+
+SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q
+ # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q);
+
+SM_AMIGA_6_.C = (CLK_OSZI);
SM_AMIGA_0_.AR = (!RST);
SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
- # !AS_000.Q & SM_AMIGA_0_.Q
- # !inst_CLK_000_D0.Q & inst_CLK_000_D4.Q & SM_AMIGA_1_.Q
- # !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q & !inst_CLK_000_D3.Q);
+ # !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
SM_AMIGA_0_.C = (CLK_OSZI);
-SM_AMIGA_6_.AR = (!RST);
-
-SM_AMIGA_6_.D = (!inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q & SM_AMIGA_7_.Q
- # nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q);
-
-SM_AMIGA_6_.C = (CLK_OSZI);
-
SM_AMIGA_5_.AR = (!RST);
SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
@@ -1432,6 +1428,33 @@ SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q
SM_AMIGA_5_.C = (CLK_OSZI);
+SM_AMIGA_2_.AR = (!RST);
+
+SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q
+ # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
+
+SM_AMIGA_2_.C = (CLK_OSZI);
+
+!inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
+ # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q
+ # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN
+ # CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
+ # BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q
+ # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN
+ # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
+ # CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
+ # BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN
+ # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
+ # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN
+ # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN
+ # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN);
+
+inst_RW_000_INT.AP = (!RST);
+
+inst_RW_000_INT.C = (CLK_OSZI);
+
inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);
inst_CLK_000_D3.AP = (!RST);
@@ -1446,16 +1469,6 @@ inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
inst_CLK_030_H.C = (CLK_OSZI);
-SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q
- # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q
- # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q
- # inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q
- # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q);
-
-SM_AMIGA_7_.AP = (!RST);
-
-SM_AMIGA_7_.C = (CLK_OSZI);
-
SM_AMIGA_4_.AR = (!RST);
SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
@@ -1472,13 +1485,12 @@ SM_AMIGA_3_.AR = (!RST);
SM_AMIGA_3_.C = (CLK_OSZI);
-SM_AMIGA_2_.AR = (!RST);
+SM_AMIGA_1_.AR = (!RST);
-SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
- # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q
- # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
+SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_1_.Q);
-SM_AMIGA_2_.C = (CLK_OSZI);
+SM_AMIGA_1_.C = (CLK_OSZI);
cpu_est_0_.AR = (!RST);
diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal
index 481277e..1f36523 100644
--- a/Logic/68030_tk.tal
+++ b/Logic/68030_tk.tal
@@ -33,22 +33,23 @@ TCR, Clocked Output-to-Register Time,
#passes #passes #passes #passes
SIGNAL NAME min max min max min max min max
inst_DTACK_D0 1 2 .. .. .. .. 1 1
+ inst_RW_000_INT 1 1 1 2 .. .. 2 2
DTACK .. .. .. .. 1 1 .. ..
+ AVEC_EXP 1 1 0 1 .. .. 1 1
+ RN_AVEC_EXP 1 1 0 1 .. .. 1 1
AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
CIIN .. .. .. .. 1 1 .. ..
SIZE_1_ 1 1 0 0 .. .. .. ..
IPL_030_2_ 1 1 0 0 .. .. 1 1
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
- IPL_030_1_ 1 1 0 0 .. .. 1 1
- RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
- IPL_030_0_ 1 1 0 0 .. .. 1 1
- RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
- DSACK_1_ 1 1 0 0 .. .. 1 1
- RN_DSACK_1_ 1 1 0 0 .. .. 1 1
AS_030 1 1 0 0 .. .. 1 1
RN_AS_030 1 1 0 0 .. .. 1 1
+ IPL_030_1_ 1 1 0 0 .. .. 1 1
+ RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
AS_000 1 1 0 0 .. .. 1 1
RN_AS_000 1 1 0 0 .. .. 1 1
+ IPL_030_0_ 1 1 0 0 .. .. 1 1
+ RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
DS_030 1 1 0 0 .. .. 1 1
RN_DS_030 1 1 0 0 .. .. 1 1
UDS_000 1 1 0 0 .. .. 1 1
@@ -62,12 +63,12 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
RN_BGACK_030 1 1 0 1 .. .. 1 1
FPU_CS 1 1 0 0 .. .. 1 1
RN_FPU_CS 1 1 0 0 .. .. 1 1
+ DSACK1 1 1 0 0 .. .. 1 1
+ RN_DSACK1 1 1 0 0 .. .. 1 1
E .. .. 0 0 .. .. 1 1
RN_E .. .. 0 0 .. .. 1 1
VMA .. .. 0 0 .. .. 1 1
RN_VMA .. .. 0 0 .. .. 1 1
-AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1
-RN_AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1
SIZE_0_ 1 1 0 0 .. .. .. ..
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1
inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1
@@ -76,19 +77,18 @@ inst_CLK_OUT_PRE_50_D .. .. .. .. .. .. 1 1
inst_CLK_000_D0 1 1 .. .. .. .. 1 1
inst_CLK_000_D1 .. .. .. .. .. .. 1 1
inst_CLK_000_D2 .. .. .. .. .. .. 1 1
- inst_CLK_000_D4 .. .. .. .. .. .. 1 1
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1
- SM_AMIGA_1_ .. .. .. .. .. .. 1 1
- SM_AMIGA_0_ .. .. .. .. .. .. 1 1
+ SM_AMIGA_7_ 1 1 .. .. .. .. 1 1
SM_AMIGA_6_ 1 1 .. .. .. .. 1 1
+ SM_AMIGA_0_ .. .. .. .. .. .. 1 1
SM_AMIGA_5_ .. .. .. .. .. .. 1 1
+ SM_AMIGA_2_ .. .. .. .. .. .. 1 1
inst_CLK_000_D3 .. .. .. .. .. .. 1 1
inst_CLK_030_H 1 1 .. .. .. .. 1 1
- SM_AMIGA_7_ 1 1 .. .. .. .. 1 1
SM_AMIGA_4_ .. .. .. .. .. .. 1 1
SM_AMIGA_3_ .. .. .. .. .. .. 1 1
- SM_AMIGA_2_ .. .. .. .. .. .. 1 1
+ SM_AMIGA_1_ .. .. .. .. .. .. 1 1
cpu_est_0_ .. .. .. .. .. .. 1 1
cpu_est_1_ .. .. .. .. .. .. 1 1
cpu_est_2_ .. .. .. .. .. .. 1 1
\ No newline at end of file
diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2
index a9c6eba..3587338 100644
--- a/Logic/68030_tk.tt2
+++ b/Logic/68030_tk.tt2
@@ -1,365 +1,375 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
-#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D4 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_
+#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_ A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_
+#$ NODES 25 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ cpu_est_2_
.type fr
-.i 79
-.o 156
-.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q VMA.Q inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_BGACK_030_INT_D.Q AS_030.Q IPL_030_1_.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q IPL_030_2_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D4.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q AS_000.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SM_AMIGA_6_.Q SM_AMIGA_5_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_7_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN
-.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C A0.C A0.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR DTACK DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D CLK_EXP.D FPU_CS.D VMA.D inst_AS_030_000_SYNC.D IPL_030_0_.D inst_BGACK_030_INT_D.D AS_030.D IPL_030_1_.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D IPL_030_2_.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D4.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D AS_000.D SM_AMIGA_1_.D SM_AMIGA_0_.D SM_AMIGA_6_.D SM_AMIGA_5_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D inst_CLK_030_H.D RESET.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D SM_AMIGA_7_.D AMIGA_BUS_ENABLE.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_2_.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D BG_000.D
-.p 353
-------------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
--------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------1---------------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------0-------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-0-----------0000000------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------1111-------------------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~
------1------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------0------------------1------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---0----------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------0-------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------0------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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----0-----------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------0--------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---1--1-----------------0010--1---1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0--1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------1----0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------1-----------------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------1------------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
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----0-------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
----1--------------------------1-------------1------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
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------------------------------------------0----------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
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------------0-----------------------------0-----------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------1--------------------------------0--------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------1----------------------------------------01------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------0-----------------------------0------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
------------1--------------------------------0---------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
------------1----------------------------------------0-1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
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---------------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------0----1------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
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--------------------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
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-------0-----------------------------1--------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
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----------------------------------1-------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
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----------------------------------0---------0------------1--1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
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----------------------------------1-------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-------------------------------------0---------1-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
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-------------------------------1--------------------0--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
------------------------------------------1-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
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------------0-----------------------------------------1-------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------0------------------------------------------1------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
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------------------------------------------1--------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
-------------------------------------------0-------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
---------------------------------------1------1----------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
---------------------------------------1--01--0----------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
------------------------------------------1---------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0---------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
------------------------------------------0----------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
-------------------------------------------1---------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
---------------------------------1-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10---------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
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------------------------------------------10---------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------0------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-------------------------------------------1-----------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------------------------------11------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------10---------------------1-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------10----------------------00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------0-------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
-------------------------------------------1------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------10---------------------1--1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------------------------------0-1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
---------------------------------0-----0--01-------------------1--0-1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
------------------------------------------10----------------------011----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
-------------------------------------------------------------------01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------10---------------------1-01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
---------------------------------------0-----------------------1----0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
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------------------------------------------1------1---------------0110----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10----------------------000----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
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--------0------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
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----------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------0-----------------------------0---------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~
---------------------------------------------1------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
---------------------------------------------0------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
------------1--------------------------------0------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~
----0--------------------------1------------------1-------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
--------------------------------------------------0-------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----0--------------------------1-------------------1------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------------------------------1------------------1-0-----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------------------------------1-------------------10-----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-----------------------------------------------------0----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
------------1----------------------------------------0----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~
---------------------------------------------------------0------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
------------0-------------------------------------------------0-------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~
---------------------------------------------------------------------10--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
-----------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~
----0-------1------------------0---------------------------------------0-------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------------1-----------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------1----------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
----------------------------------------------------------------------1-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
-------1---1-------------------0-----0---------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
-------------------------------0--------------------------1------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
--------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
-------------------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~
-------1---1-------------------0-----0---------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
-------------------------------0--------------------------1------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
-------------------------------0---------------------------------------0-10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
-------------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
------------1--------------------------------1-------1------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0--100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0--100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-1------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----0--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------0------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------0---------------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------1-------------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------0----------------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------0---------------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------0--------------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------0-------------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-----------1-------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
------------1------------------1------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~00~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
----1--------------------------0------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------0------------------0------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~
------------------------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~0~~~~~~~~~~~~~~~~0~~~
-------------------------------0----------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------0--------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------0------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0---0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------00------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-------------------------------0-----------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------0-------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0----1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------0-1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--0---------------------------------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------0-------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------0------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
------------------------------------------0--1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------1--01--0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
-----------------------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0------11------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
---------------------------------0---------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0-------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1--------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------------00---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
----1-------------------------------1--------0------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
---------------------------------------------1-------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
----1-----------------------------0-------0-0------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
----------------------------------0-------1-0----0-------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
---------------------------------------------0----1------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
----------------------------------0-------1-0------0-----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
---------------------------------------------0-----0-----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
----------------------------------0-------0-0-------0----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
---------------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0--------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
-------0--------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-----------0----------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-------------------------------------1--------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
----------------------------------1-------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1---------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------------0--1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
----0-------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1-----------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
----1-------------------------------------0-----------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
------------------------------------------1------0----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
------------------------------------------1--------0--------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
----------------------------------------------------0-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0---------0-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
----0-------------------------------1-------------00---------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
------------------------------------1-------------000--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
-----------------------------------------------------0--------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
------------------------------------------0--------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
--------------------------------------------------------------00---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
---------------------------------1-----0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
-------------------------------------------0--------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
---------------------------------------1------1-----------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
--------------------------------------------------0-------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------------------00--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
---------------------------------0-------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10---------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
------------------------------------------0----------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
-------------------------------------------1---------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
---------------------------------------0------------------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
---------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------0--0----------------------10------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10----------------------11------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
---------------------------------0---------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
-------------------------------------------1-----------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
-----------------------------------------------------------------010------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
---------------------------------0----------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------0-----0--01----------------------0-1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
------------------------------------------------------------------111----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-----------------------------------------------------------------0-01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
------------------------------------------0-------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
-------------------------------------------1------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
---------------------------------------0------------------------0---0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
-----------------------------------------------------------------01-0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
------------------------------------------10---------------------10-0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
-------------------------------------------------------------------10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
-----------------------------------------------------------------0-10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-----------------------------------------------------------------1-00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
------------------------------------------------------------------100----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-----0---------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
----10--1---------------------------------------------------1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
---1--11----------------0010--1---------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------0-------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-----------------------------0----------1------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------0--------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
----1-----------------------------0---------------0-------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------0----------1------0-----------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------0---------------0-0-----------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------0-----------------------------0-----------0---------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------1--------------------------------0--------0---------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------1----------------------------------------00---------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------0-----------------------------0------------0--------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------0---------0--------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1----------------------------------------0-0--------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
--------------------------------------------------------0-------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
----1-----------------------------0----------------------0------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------0-----------------0----0------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---01--1-----------------------1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-01-----------------------1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------1------1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-----------------1-----1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1------------------0----1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-------------------1---1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------------01-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---01--1-----------------------1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-01-----------------------1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------1------1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-----------------1-----1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1------------------0----1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-------------------1---1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------------01------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---01--1-----------------------1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-01-----------------------1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------1------1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-----------------1-----1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1------------------0----1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-------------------1---1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------------01-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----0-------------------------------1------------------------0--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
------------------------------------1---------------0--------0--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
------------0-----------------------------------------0-------0-------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------0------------------------------------------0------0-------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
-----------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-----------1-----------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-------------------------------0---------------------------------------1-------- ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------------0---------------0-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------0--------------0-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-------0-----------------------0---------------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0-----0---------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------1------------------0-----0---------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------0-----------------------0-----0--------------------1------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------1----0------------------0---------------------------0-----------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
------------0------------------0--------------------------00-----------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
--------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-----------1-------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-------------------------------0---------------------------------------0-01----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-------0-----------------------0---------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0-----0---------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------1------------------0-----0---------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------0-----------------------0-----0--------------------1------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------1----0------------------0---------------------------0-----------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
------------0------------------0--------------------------00-----------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------------------------------0---------------------------------------0-10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-------------------------------0---------------------------------------0-00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.i 80
+.o 158
+.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_DTACK_D0.Q IPL_030_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_030_1_.Q SM_AMIGA_7_.Q IPL_030_2_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN
+.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR DSACK1.C DSACK1.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D CLK_EXP.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_DTACK_D0.D IPL_030_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D IPL_030_1_.D SM_AMIGA_7_.D IPL_030_2_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_5_.D SM_AMIGA_2_.D inst_RW_000_INT.D UDS_000.D LDS_000.D DSACK1.D inst_CLK_000_D3.D inst_CLK_030_H.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D RESET.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_1_.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D
+.p 363
+-------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
+---1---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------1----------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------0--------------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+0----------0000000-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------1111---------------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---0-------------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------0---------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~
+-----1------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--0----------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----0-------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------1--------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------1-------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------0------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------1-----1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------0--1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------0------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------1----------------------------------------------- ~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---0------------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0---------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--1--1----------------0010--1-----1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------0---1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------1----0-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------1-----------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---0--------------------------0-----0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------1---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------1-----1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-1-------------------------------------10--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
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.end
diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3
index be80d6d..c9a069d 100644
--- a/Logic/68030_tk.tt3
+++ b/Logic/68030_tk.tt3
@@ -1,365 +1,375 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
-#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D4 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_
+#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_ A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_
+#$ NODES 25 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ cpu_est_2_
.type fr
-.i 79
-.o 156
-.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q VMA.Q inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_BGACK_030_INT_D.Q AS_030.Q IPL_030_1_.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q IPL_030_2_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D4.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q AS_000.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SM_AMIGA_6_.Q SM_AMIGA_5_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_7_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN
-.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C A0.C A0.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR DTACK DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D CLK_EXP.D FPU_CS.D VMA.D inst_AS_030_000_SYNC.D IPL_030_0_.D inst_BGACK_030_INT_D.D AS_030.D IPL_030_1_.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D IPL_030_2_.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D4.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D AS_000.D SM_AMIGA_1_.D SM_AMIGA_0_.D SM_AMIGA_6_.D SM_AMIGA_5_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D inst_CLK_030_H.D RESET.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D SM_AMIGA_7_.D AMIGA_BUS_ENABLE.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_2_.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D BG_000.D
-.p 353
-------------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
--------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------1---------------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------0-------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-0-----------0000000------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------1111-------------------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~
------1------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------0------------------1------------------------------------------------ ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---0----------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------0-------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------0------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------1-------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------1------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------0-----1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------1----1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------0-1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------0----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----0-----------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------0--------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---1--1-----------------0010--1---1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0--1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------1----0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------1-----------------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------1------------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
----0--------------------------0-----0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------1-----1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------1--------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------1------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------1---0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------10------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------1-------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------1----1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------1-1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--1---------------------------------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------1-----------------------------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------1-------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------1------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
-----------------------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------0---1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
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------------------------------------------0--1----1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0--------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------1-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-------------------------------------------------0-1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
----0-----------------------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
----0-------------------------------------0---------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
----1--------------------------1-------------1------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
------------------------------------------1----------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
------------------------------------------0----------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
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------------0-----------------------------0-----------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------1--------------------------------0--------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------1----------------------------------------01------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------0-----------------------------0------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
------------1--------------------------------0---------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
------------1----------------------------------------0-1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
---------------------------------------------1----------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
--------------------------------------------------0-----1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
---------------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------0----1------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0-------1------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
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-----------0----------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
-------0-----------------------------1--------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
-------1----0----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
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----------------------------------1-------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
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----------------------------------0---------0------------1--1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------------0--1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
----------------------------------1-------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-------------------------------------0---------1-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
----0--------------------------1-----------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------------------------------1--------------------0--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
------------------------------------------1-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
------------------------------------------0-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
------------0-----------------------------------------1-------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
------------0------------------------------------------1------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
---------------------------------1-----0-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
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-------------------------------------------0-------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
---------------------------------------1------1----------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
---------------------------------------1--01--0----------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
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------------------------------------------0---------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
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---------------------------------1-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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------------------------------------------10---------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------0------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-------------------------------------------1-----------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------------------------------11------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------------------------------------------10---------------------1-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------10----------------------00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------0-------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
-------------------------------------------1------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
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------------------------------------------------------------------0-1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
---------------------------------0-----0--01-------------------1--0-1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
------------------------------------------10----------------------011----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
-------------------------------------------------------------------01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
------------------------------------------10---------------------1-01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
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------------------------------------------1------1---------------0110----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10----------------------000----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
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--------0------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
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---------------------------------------------1------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
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----0--------------------------1-------------------1------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------------------------------1------------------1-0-----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-------------------------------1-------------------10-----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-----------------------------------------------------0----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
------------1----------------------------------------0----------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~
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---------------------------------------------------------------------10--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
-----------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~
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-------------------------------------------------------1----------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
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-------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
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-------------------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~
-------1---1-------------------0-----0---------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
-------------------------------0--------------------------1------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
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-------------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
------------1--------------------------------1-------1------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
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------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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--------0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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----------------------0--------------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-----------1-------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
------------1------------------1------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~00~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
----1--------------------------0------------------------------------------------ ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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--------------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~
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--------------------------------------0---0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------00------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-------------------------------0-----------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------0-------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0----1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------0-1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--0---------------------------------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------0-------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------0------------10------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
------------------------------------------0--1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------1--01--0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
-----------------------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0------11------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
---------------------------------0---------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0-------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1--------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------------00---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
----1-------------------------------1--------0------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
---------------------------------------------1-------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------------00-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
----1-----------------------------0-------0-0------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
----------------------------------0-------1-0----0-------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
---------------------------------------------0----1------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
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----------------------------------0-------0-0-------0----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
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------------------------------------------0--------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
-------0--------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-----------0----------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-------------------------------------1--------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
----------------------------------1-------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
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----------------------------------------------------0-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0---------0-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
----0-------------------------------1-------------00---------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
------------------------------------1-------------000--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
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---------------------------------1-----0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
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---------------------------------0-------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10---------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
------------------------------------------0----------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
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---------------------------------------0------------------------0-1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
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---------------------------------------0--0----------------------10------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10----------------------11------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
---------------------------------0---------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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---------------------------------0----------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-------------------------------------------------------------------10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
-----------------------------------------------------------------0-10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-----------------------------------------------------------------1-00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
------------------------------------------------------------------100----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-----0---------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
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---1--11----------------0010--1---------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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------------0-----------------------------0-----------0---------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------1--------------------------------0--------0---------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
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------------0-----------------------------0------------0--------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
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---01--1-----------------------1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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----1--1-------------------1---1-------------1--------------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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---01--1-----------------------1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-01-----------------------1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------1------1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-----------------1-----1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1------------------0----1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-------------------1---1------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------------01------------------0---------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---01--1-----------------------1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1-01-----------------------1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1----------------1------1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-----------------1-----1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1------------------0----1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1--1-------------------1---1-------------------------0--1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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----0-------------------------------1------------------------0--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
------------------------------------1---------------0--------0--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
------------0-----------------------------------------0-------0-------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------0------------------------------------------0------0-------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
-----------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-----------1-----------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-------------------------------0---------------------------------------1-------- ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------------0---------------0-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------0--------------0-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
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-------0-----------------------0---------------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0-----0---------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------1------------------0-----0---------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------0-----------------------0-----0--------------------1------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------1----0------------------0---------------------------0-----------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
------------0------------------0--------------------------00-----------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
--------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-----------1-------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
-------------------------------0---------------------------------------0-01----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-------0-----------------------0---------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------0-----0---------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------1------------------0-----0---------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------0-----------------------0-----0--------------------1------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------1----0------------------0---------------------------0-----------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
------------0------------------0--------------------------00-----------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
-------------------------------0---------------------------------------0-10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-------------------------------0---------------------------------------0-00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
------------1--------------------------------1-------1------------------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------0-----------------------------1-------------------1---------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.i 80
+.o 158
+.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_DTACK_D0.Q IPL_030_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_030_1_.Q SM_AMIGA_7_.Q IPL_030_2_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN
+.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR DSACK1.C DSACK1.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D CLK_EXP.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_DTACK_D0.D IPL_030_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D IPL_030_1_.D SM_AMIGA_7_.D IPL_030_2_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_5_.D SM_AMIGA_2_.D inst_RW_000_INT.D UDS_000.D LDS_000.D DSACK1.D inst_CLK_000_D3.D inst_CLK_030_H.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D RESET.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_1_.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D
+.p 363
+-------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
+---1---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------1----------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------0--------------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+0----------0000000-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+---------------------------------------10-----------------------1-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
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+------------------------------------------------------------------01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
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+-------------------------------------0------------------------1----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
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+---------------------------------------1---------1--------------0110------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------10------------------------000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
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+---------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~
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+--------------------------------------------------------------------1--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~
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+------------------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~
+---------------------------------------1----------01--------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+---------------------------------------0--------------1-----------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+--------------------------------------------------0---1-----------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+------1---1-------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
+------------------------------0----------------------------1---------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
+------0-----------------------0--------------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+------------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
+------------------------------------------------------------------------00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
+-----------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------1--------------------------------1----------1----------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+------------------------------1--------1----------1----------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+-----------------------------------------0-------------1-----------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+----------------------------------------------------0--1-----------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+-----------------------------------------0--------------1----------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+----------------------------------------------------0---1----------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+-----------------------------------------0--------------------------1----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~
+----------------------------------------------------0---------------1----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~
+---------------------------------------1----------1------------------1---------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+---0--------------------------0--------------------------------------0---------1 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------1----------1---------------------11-----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
+-----------------------------------------1----------1------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+-----------------------------------------1----------1------------------0--100--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+------------------------------1------------------------------------------------0 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0---------------1-----------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+---------------------------------------0----------------1----------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+-------------------------------------------------------1-----0-----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+--------------------------------------------------------1----0-----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+---------------------------------------0----------------------------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~
+-------------------------------------------------------------0------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~
+---------------------------------------1---------------------1---------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+---------------------------------------1---------------------1---------0--100--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+-------------------------------------------------------------------------------- 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+1------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---0---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----0-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------0------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------0----------------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------1--------------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------0------------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------0------------------------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------0----------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------0---------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0------------------------0-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+----------1-------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+------------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~00~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------0----------------------------------------------- ~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~0~~~~~~
+---------------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~0~~~~~~~~~~~~~~0~0~~
+------------------------------0--------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------0-----0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
+------------------------------0---------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-0-------------------------------------10--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------0------------10--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------0-----------10--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-------------------------------------1-01-0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+---------------------------------------0---0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1--0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------0-----11---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------1------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------------00---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1-----0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
+---0-------------------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
+----------------------------------1------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1-----1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
+--------------------------------0--1-----------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------1-------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0-------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0--------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1-------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------0---------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------0--0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------0---0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1----------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------------------0-0--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
+---------------------------------------1-------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+---------------------------------1---0---------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+----------------------------------------0------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+-------------------------------------1----1----------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+------------------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------1--------------------------------0--------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------------------------------1--------0--------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------1-------------------------------------------00--0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------------------------------1-------------------00--0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+---1------------------------------0----0-0----------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
+---1------------------------------01-----0-----1----------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1------------------------------0------0---------0------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------1----------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
+------0----------------------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+----------0------------------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+------------------------------------1----------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+----------------------------------------------------0--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
+---------------------------------------0----------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+-----------------------------------------------------0--------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+-------------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+---------------------------------------------------0-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------------------0---------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
+---------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------10-----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
+---------------------------------------0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
+----------------------------------------1-----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
+-------------------------------------0---------------0-----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+---------------------------------0-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------0-0------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------10------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+---------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+----------------------------------------1-------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
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+---------------------------------0---------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------0---0-01------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
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+----------------------------------------1--------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+-------------------------------------0---------------0-------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+----------------------------------------------------------------01-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+---------------------------------------10-----------------------10-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
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+----------------------------------------------------------------0-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
+----------------------------------------------------------------1-00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
+-----------------------------------------------------------------100------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
+---10--1---------------------------------------1--------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--1--11---------------0010--1---------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------0------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1------------------------------0----0----------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------0----0-1--------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--01--1-----------------------1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+---1--1----------------1------1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1--1-----------------0-----1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1--1------------------1----1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1--1---------------------0-1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------0----0-------0--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------------0------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
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+----------------------------------0------1-----------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+---1--1------------------1----1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+----------------------------------0----0------------------0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------0------------------0----0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+----------1----------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+---------------------------------------0--------------0--------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
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+-------------------------------------------------------0------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+--------------------------------------------------------0-----------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+------------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+------0-----------------------0--------------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0-----------------------0-----0----------------------1---------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------------------------------0-----0--------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------0-----------------------0--------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------1-----------------------0-----------------------------0--------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------------------------------0----------------------------00--------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+-------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+----------1-------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+---------------------------------------0--------------0-----------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+--------------------------------------------------00--0-----------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------------------------------0--------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
+------0-----------------------0--------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0-----------------------0-----0----------------------1---------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------------------------------0-----0--------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------0-----------------------0--------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------1-----------------------0-----------------------------0--------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------------------------------0----------------------------00--------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
+------------------------------0--------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
+-----------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1---------------------------------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------0-------------0------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+----------------------------------------------------0--0------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+-----------------------------------------0--------------0-----------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+----------------------------------------------------0---0-----------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+---------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1----------1------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+-----------------------------------------1----------1------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+-----------------------------------------1----------1------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+-----------------------------------------1----------1------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+------------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------1--------------------------------1----------1----------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------------------------------1--------1----------1----------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+---------------------------------------0---------------0------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+---------------------------------------0----------------0-----------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+-------------------------------------------------------0-----0------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+--------------------------------------------------------0----0------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+---------------------------------------1----------1------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+---------------------------------------1----------1---------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+---------------------------------------1---------------------1---------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+---------------------------------------1---------------------1---------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+---------------------------------------1---------------------1---------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+---------------------------------------1---------------------1---------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
.end
diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4
index 1b40a9a..f7e3a05 100644
--- a/Logic/68030_tk.tt4
+++ b/Logic/68030_tk.tt4
@@ -1,191 +1,200 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE BUS68030
-#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_
- DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
- CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR
- AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
- SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000
- LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
+#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_
+ A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000
+ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW
+ AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_
+ A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000
+ LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_
#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D
inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2
- inst_CLK_000_D4 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25
- SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_CLK_000_D3 inst_CLK_030_H
- SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_
+ inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_
+ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3
+ inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_
+ cpu_est_2_
.type f
-.i 79
-.o 159
+.i 80
+.o 160
.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA
- RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_
- A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q VMA.Q
- inst_AS_030_000_SYNC.Q IPL_030_0_.Q inst_BGACK_030_INT_D.Q AS_030.Q IPL_030_1_.Q
- inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q IPL_030_2_.Q inst_CLK_000_D0.Q
- inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D4.Q inst_DTACK_D0.Q
- inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q AS_000.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q
- SM_AMIGA_6_.Q SM_AMIGA_5_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q
- inst_CLK_030_H.Q DS_030.Q SM_AMIGA_7_.Q AMIGA_BUS_ENABLE.Q SM_AMIGA_4_.Q
- SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q
- AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
- A0.PIN DSACK_1_.PIN DTACK.PIN
-.ob DSACK_0_ DSACK_0_.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR
- DTACK DTACK.OE AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW
- CIIN CIIN.OE SIZE_1_.D% SIZE_1_.C SIZE_1_.AP SIZE_1_.OE IPL_030_2_.D
- IPL_030_2_.C IPL_030_2_.AP IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D
- IPL_030_0_.C IPL_030_0_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP DSACK_1_.OE
- AS_030.D AS_030.C AS_030.AP AS_030.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE
- DS_030.D DS_030.C DS_030.AP DS_030.OE UDS_000.D% UDS_000.C UDS_000.AP UDS_000.OE
- LDS_000.D% LDS_000.C LDS_000.AP LDS_000.OE A0.D A0.C A0.AP A0.OE BG_000.D%
- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C
- CLK_EXP.AR FPU_CS.D% FPU_CS.C FPU_CS.AP E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2
- VMA.C VMA.AP RESET.D RESET.C RESET.AR AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C
- AMIGA_BUS_ENABLE.AP SIZE_0_.D% SIZE_0_.C SIZE_0_.AP SIZE_0_.OE
- inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP
- inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP
- inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50_D.D
- inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D
- inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C
- inst_CLK_000_D1.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP
- inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_DTACK_D0.D
- inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
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diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte
index 61ff6cb..6228616 100644
--- a/Logic/68030_tk.tte
+++ b/Logic/68030_tk.tte
@@ -1,191 +1,200 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE BUS68030
-#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_
- DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
- CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR
- AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
- SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000
- LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
+#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_
+ A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000
+ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW
+ AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_
+ A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000
+ LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_
#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D
inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2
- inst_CLK_000_D4 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25
- SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_CLK_000_D3 inst_CLK_030_H
- SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_
+ inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_
+ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3
+ inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_
+ cpu_est_2_
.type f
-.i 79
-.o 159
+.i 80
+.o 160
.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA
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+--------------------------------------10-----------------------000-------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
+--------------------------------------10-----------------------1010------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
+-----------------------------------------------------------------1-------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
.end
diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl
index 14173f1..24cfb13 100644
--- a/Logic/68030_tk.vcl
+++ b/Logic/68030_tk.vcl
@@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
-DATE = 5/29/14;
-TIME = 22:04:32;
+DATE = 6/1/14;
+TIME = 01:03:29;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@@ -116,7 +116,7 @@ Conf_Unused_IOs = OUT_LOW;
[POWER]
Powerlevel = Low, High;
-Default = Low;
+Default = High;
Type = GLB;
[HARDWARE DEVICE OPTIONS]
@@ -138,14 +138,16 @@ AS_000 = BIDIR,33,3,-;
LDS_000 = BIDIR,31,3,-;
UDS_000 = BIDIR,32,3,-;
AS_030 = BIDIR,82,7,-;
+RW = OUTPUT,71,6,-;
DS_030 = BIDIR,98,0,-;
-DSACK_1_ = BIDIR,81,7,-;
+DSACK1 = BIDIR,81,7,-;
SIZE_1_ = OUTPUT,79,7,-;
+RW_000 = OUTPUT,80,7,-;
SIZE_0_ = OUTPUT,70,6,-;
A0 = OUTPUT,69,6,-;
DTACK = OUTPUT,30,3,-;
-AMIGA_BUS_ENABLE = OUTPUT,34,3,-;
E = OUTPUT,66,6,-;
+AVEC_EXP = OUTPUT,22,2,-;
IPL_030_2_ = OUTPUT,9,1,-;
IPL_030_0_ = OUTPUT,8,1,-;
IPL_030_1_ = OUTPUT,7,1,-;
@@ -155,51 +157,50 @@ AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
VMA = OUTPUT,35,3,-;
BG_000 = OUTPUT,29,3,-;
AVEC = OUTPUT,92,0,-;
-DSACK_0_ = OUTPUT,80,7,-;
CLK_DIV_OUT = OUTPUT,65,6,-;
CIIN = OUTPUT,47,4,-;
BERR = OUTPUT,41,4,-;
-AVEC_EXP = OUTPUT,22,2,-;
+AMIGA_BUS_ENABLE = OUTPUT,34,3,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
CLK_EXP = OUTPUT,10,1,-;
RESET = OUTPUT,3,1,-;
RN_BGACK_030 = NODE,-1,7,-;
inst_CLK_000_D0 = NODE,*,3,-;
RN_AS_030 = NODE,-1,7,-;
-SM_AMIGA_7_ = NODE,*,0,-;
-SM_AMIGA_0_ = NODE,*,1,-;
-cpu_est_0_ = NODE,*,1,-;
-SM_AMIGA_1_ = NODE,*,1,-;
-RN_FPU_CS = NODE,-1,7,-;
-RN_AS_000 = NODE,-1,3,-;
-SM_AMIGA_4_ = NODE,*,1,-;
-SM_AMIGA_6_ = NODE,*,7,-;
-inst_CLK_000_D3 = NODE,*,7,-;
-inst_CLK_OUT_PRE_50 = NODE,*,6,-;
-inst_CLK_000_D4 = NODE,*,7,-;
-inst_CLK_000_D1 = NODE,*,7,-;
-inst_AS_030_000_SYNC = NODE,*,7,-;
-cpu_est_1_ = NODE,*,6,-;
+cpu_est_0_ = NODE,*,2,-;
+inst_CLK_000_D1 = NODE,*,3,-;
+inst_RW_000_INT = NODE,*,0,-;
+cpu_est_1_ = NODE,*,1,-;
+SM_AMIGA_7_ = NODE,*,1,-;
RN_E = NODE,-1,6,-;
cpu_est_2_ = NODE,*,6,-;
SM_AMIGA_2_ = NODE,*,6,-;
+inst_CLK_000_D2 = NODE,*,7,-;
+inst_AS_030_000_SYNC = NODE,*,2,-;
+inst_CLK_030_H = NODE,*,7,-;
+RN_AVEC_EXP = NODE,-1,2,-;
inst_CLK_OUT_PRE_25 = NODE,*,1,-;
RN_VMA = NODE,-1,3,-;
-SM_AMIGA_5_ = NODE,*,3,-;
-inst_CLK_000_D2 = NODE,*,7,-;
+RN_FPU_CS = NODE,-1,7,-;
+SM_AMIGA_1_ = NODE,*,7,-;
+SM_AMIGA_4_ = NODE,*,3,-;
+SM_AMIGA_5_ = NODE,*,1,-;
+SM_AMIGA_0_ = NODE,*,0,-;
+SM_AMIGA_6_ = NODE,*,1,-;
+inst_CLK_000_D3 = NODE,*,2,-;
+inst_CLK_OUT_PRE_50 = NODE,*,7,-;
inst_VPA_D = NODE,*,7,-;
RN_LDS_000 = NODE,-1,3,-;
RN_UDS_000 = NODE,-1,3,-;
RN_DS_030 = NODE,-1,0,-;
-RN_AMIGA_BUS_ENABLE = NODE,-1,3,-;
-inst_CLK_030_H = NODE,*,0,-;
SM_AMIGA_3_ = NODE,*,6,-;
RN_IPL_030_0_ = NODE,-1,1,-;
RN_IPL_030_1_ = NODE,-1,1,-;
RN_IPL_030_2_ = NODE,-1,1,-;
+RN_DSACK1 = NODE,-1,7,-;
RN_BG_000 = NODE,-1,3,-;
-RN_DSACK_1_ = NODE,-1,7,-;
-inst_DTACK_D0 = NODE,*,0,-;
-inst_CLK_OUT_PRE_50_D = NODE,*,0,-;
+RN_AS_000 = NODE,-1,3,-;
+inst_DTACK_D0 = NODE,*,7,-;
+inst_CLK_OUT_PRE_50_D = NODE,*,7,-;
inst_BGACK_030_INT_D = NODE,*,3,-;
CLK_OSZI = INPUT,61,-,-;
diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco
index 9fb3f10..f4e3003 100644
--- a/Logic/68030_tk.vco
+++ b/Logic/68030_tk.vco
@@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
-DATE = 5/29/14;
-TIME = 22:04:32;
+DATE = 6/1/14;
+TIME = 01:03:29;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@@ -116,7 +116,7 @@ Conf_Unused_IOs = OUT_LOW;
[POWER]
Powerlevel = Low, High;
-Default = Low;
+Default = High;
Type = GLB;
[HARDWARE DEVICE OPTIONS]
@@ -134,19 +134,24 @@ layer = OFF;
[LOCATION ASSIGNMENT]
Layer = OFF;
+A_26_ = INPUT,17, C,-;
+A_25_ = INPUT,18, C,-;
+A_24_ = INPUT,19, C,-;
+A_23_ = INPUT,84, H,-;
+A_31_ = INPUT,4, B,-;
+A_22_ = INPUT,85, H,-;
A_21_ = INPUT,94, A,-;
A_20_ = INPUT,93, A,-;
A_19_ = INPUT,97, A,-;
-A_18_ = INPUT,95, A,-;
-A_31_ = INPUT,4, B,-;
-A_17_ = INPUT,59, F,-;
-A_16_ = INPUT,96, A,-;
IPL_2_ = INPUT,68, G,-;
+A_18_ = INPUT,95, A,-;
+A_17_ = INPUT,59, F,-;
+FC_1_ = INPUT,58, F,-;
+A_16_ = INPUT,96, A,-;
+RW_000 = BIDIR,80, H,-;
IPL_1_ = INPUT,56, F,-;
IPL_0_ = INPUT,67, G,-;
-DSACK_0_ = OUTPUT,80, H,-;
FC_0_ = INPUT,57, F,-;
-FC_1_ = INPUT,58, F,-;
nEXP_SPACE = INPUT,14,-,-;
BERR = OUTPUT,41, E,-;
BG_030 = INPUT,21, C,-;
@@ -160,7 +165,8 @@ AVEC = OUTPUT,92, A,-;
AVEC_EXP = OUTPUT,22, C,-;
VPA = INPUT,36,-,-;
RST = INPUT,86,-,-;
-RW = INPUT,71, G,-;
+RW = BIDIR,71, G,-;
+AMIGA_BUS_ENABLE = OUTPUT,34, D,-;
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
CIIN = OUTPUT,47, E,-;
@@ -168,18 +174,12 @@ A_30_ = INPUT,5, B,-;
A_29_ = INPUT,6, B,-;
A_28_ = INPUT,15, C,-;
A_27_ = INPUT,16, C,-;
-A_26_ = INPUT,17, C,-;
-A_25_ = INPUT,18, C,-;
-A_24_ = INPUT,19, C,-;
-A_23_ = INPUT,84, H,-;
-A_22_ = INPUT,85, H,-;
SIZE_1_ = BIDIR,79, H,-;
IPL_030_2_ = OUTPUT,9, B,-;
-IPL_030_1_ = OUTPUT,7, B,-;
-IPL_030_0_ = OUTPUT,8, B,-;
-DSACK_1_ = BIDIR,81, H,-;
AS_030 = BIDIR,82, H,-;
+IPL_030_1_ = OUTPUT,7, B,-;
AS_000 = BIDIR,33, D,-;
+IPL_030_0_ = OUTPUT,8, B,-;
DS_030 = BIDIR,98, A,-;
UDS_000 = BIDIR,32, D,-;
LDS_000 = BIDIR,31, D,-;
@@ -188,32 +188,32 @@ BG_000 = OUTPUT,29, D,-;
BGACK_030 = OUTPUT,83, H,-;
CLK_EXP = OUTPUT,10, B,-;
FPU_CS = OUTPUT,78, H,-;
+DSACK1 = BIDIR,81, H,-;
E = OUTPUT,66, G,-;
VMA = OUTPUT,35, D,-;
RESET = OUTPUT,3, B,-;
-AMIGA_BUS_ENABLE = OUTPUT,34, D,-;
SIZE_0_ = BIDIR,70, G,-;
-inst_AS_030_000_SYNC = NODE,9, H,-;
+inst_AS_030_000_SYNC = NODE,3, C,-;
inst_BGACK_030_INT_D = NODE,10, D,-;
-inst_VPA_D = NODE,14, H,-;
-inst_CLK_OUT_PRE_50_D = NODE,3, A,-;
-inst_CLK_000_D0 = NODE,12, D,-;
-inst_CLK_000_D1 = NODE,3, H,-;
-inst_CLK_000_D2 = NODE,12, H,-;
-inst_CLK_000_D4 = NODE,8, H,-;
-inst_DTACK_D0 = NODE,1, A,-;
-inst_CLK_OUT_PRE_50 = NODE,1, G,-;
-inst_CLK_OUT_PRE_25 = NODE,9, B,-;
-SM_AMIGA_1_ = NODE,10, B,-;
-SM_AMIGA_0_ = NODE,5, B,-;
-SM_AMIGA_6_ = NODE,7, H,-;
-SM_AMIGA_5_ = NODE,2, D,-;
-inst_CLK_000_D3 = NODE,2, H,-;
-inst_CLK_030_H = NODE,0, A,-;
-SM_AMIGA_7_ = NODE,11, A,-;
-SM_AMIGA_4_ = NODE,7, B,-;
-SM_AMIGA_3_ = NODE,7, G,-;
-SM_AMIGA_2_ = NODE,6, G,-;
-cpu_est_0_ = NODE,8, B,-;
-cpu_est_1_ = NODE,4, G,-;
-cpu_est_2_ = NODE,5, G,-;
+inst_VPA_D = NODE,10, H,-;
+inst_CLK_OUT_PRE_50_D = NODE,12, H,-;
+inst_CLK_000_D0 = NODE,5, D,-;
+inst_CLK_000_D1 = NODE,7, D,-;
+inst_CLK_000_D2 = NODE,3, H,-;
+inst_DTACK_D0 = NODE,11, H,-;
+inst_CLK_OUT_PRE_50 = NODE,9, H,-;
+inst_CLK_OUT_PRE_25 = NODE,7, B,-;
+SM_AMIGA_7_ = NODE,5, B,-;
+SM_AMIGA_6_ = NODE,9, B,-;
+SM_AMIGA_0_ = NODE,1, A,-;
+SM_AMIGA_5_ = NODE,8, B,-;
+SM_AMIGA_2_ = NODE,5, G,-;
+inst_RW_000_INT = NODE,3, A,-;
+inst_CLK_000_D3 = NODE,4, C,-;
+inst_CLK_030_H = NODE,5, H,-;
+SM_AMIGA_4_ = NODE,9, D,-;
+SM_AMIGA_3_ = NODE,6, G,-;
+SM_AMIGA_1_ = NODE,7, H,-;
+cpu_est_0_ = NODE,2, C,-;
+cpu_est_1_ = NODE,3, B,-;
+cpu_est_2_ = NODE,4, G,-;
diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct
index a043344..5cb097f 100644
--- a/Logic/68030_tk.vct
+++ b/Logic/68030_tk.vct
@@ -15,8 +15,8 @@ Voltage = 5.0;
RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
-DATE = 05/25/2014;
-TIME = 21:04:55;
+DATE = 06/01/2014;
+TIME = 00:00:40;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@@ -115,7 +115,6 @@ Layer = OFF;
[LOCATION ASSIGNMENT]
Layer = OFF;
AS_030 = input,82,H,-;
-A_0_ = input,69,G,-;
A_16_ = input,96,A,-;
A_17_ = input,59,F,-;
A_18_ = input,95,A,-;
@@ -125,7 +124,6 @@ BG_030 = input,21,C,-;
CLK_000 = input,11,-,-;
CLK_030 = input,64,-,-;
CLK_OSZI = input,61,-,-;
-CPU_SPACE = input,14,-,-;
FC_0_ = input,57,F,-;
FC_1_ = input,58,F,-;
IPL_0_ = input,67,G,-;
@@ -141,7 +139,6 @@ BGACK_030 = input,83,H,-;
BG_000 = input,29,D,-;
CLK_DIV_OUT = input,65,G,-;
CLK_EXP = input,10,B,-;
-DSACK_0_ = input,80,H,-;
E = input,66,G,-;
FPU_CS = input,78,H,-;
IPL_030_0_ = input,8,B,-;
@@ -151,7 +148,6 @@ LDS_000 = input,31,D,-;
UDS_000 = input,32,D,-;
VMA = input,35,D,-;
AS_000 = input,33,D,-;
-DSACK_1_ = input,81,H,-;
DTACK = input,30,D,-;
RESET = input,3,B,-;
AMIGA_BUS_DATA_DIR = input,48,E,-;
@@ -175,6 +171,8 @@ AVEC_EXP = input,22,C,-;
BERR = input,41,E,-;
nEXP_SPACE = input,14,-,-;
A0 = input,69,G,-;
+DSACK1 = input,81,H,-;
+RW_000 = input,80,H,-;
[GROUP ASSIGNMENT]
Layer = OFF;
@@ -203,7 +201,7 @@ Page_Break = Yes;
[POWER]
Powerlevel = Low,High;
-Default = Low;
+Default = High;
Type = GLB;
[SOURCE CONSTRAINT OPTION]
diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf
index e4a680b..9eaf7f8 100644
--- a/Logic/68030_tk.xrf
+++ b/Logic/68030_tk.xrf
@@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 1.7.00.05.28.13
-Design '68030_tk' created Thu May 29 22:04:27 2014
+Design '68030_tk' created Sun Jun 01 01:03:24 2014
LEGEND: '>' Functional Block Port Separator
diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0
index 757af5c..dc88bac 100644
--- a/Logic/BUS68030.bl0
+++ b/Logic/BUS68030.bl0
@@ -1,99 +1,101 @@
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ TOOL EDIF2BLIF version IspLever 1.0
#$ MODULE bus68030
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 405 CLK_030_c CLK_000_c CLK_OSZI_c inst_BGACK_030_INTreg CLK_OUT_INTreg inst_FPU_CS_INTreg inst_VMA_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_BGACK_030_INT_D \
-# inst_AS_000_DMA IPL_030DFFSH_1_reg inst_VPA_D inst_CLK_OUT_PRE_50_D IPL_030DFFSH_2_reg inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_0__n inst_CLK_000_D2 inst_CLK_000_D4 \
-# ipl_c_1__n inst_DTACK_D0 inst_CLK_OUT_PRE_50 ipl_c_2__n inst_CLK_OUT_PRE_25 vcc_n_n gnd_n_n dsack_c_1__n state_machine_un13_clk_000_d0_n inst_AS_000_INT \
-# SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT clk_un3_clk_out_pre_50_n RST_c inst_CLK_000_D3 \
-# inst_CLK_030_H RESETDFFRHreg state_machine_un6_bgack_000_n state_machine_un15_clk_000_d0_n RW_c inst_DS_000_DMA SIZE_DMA_0_ fc_c_0__n SIZE_DMA_1_ inst_A0_DMA \
-# fc_c_1__n SM_AMIGA_7_ un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 AMIGA_BUS_ENABLEDFFSHreg SM_AMIGA_4_ AMIGA_BUS_DATA_DIR_c state_machine_ds_000_dma_3_n SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_ns_0_1__n \
-# state_machine_un10_bg_030_n N_134_i state_machine_lds_000_int_7_n N_169_i state_machine_uds_000_int_7_n N_133_i N_167_i N_51_0 N_140_i N_202_0 \
-# N_86_0 N_171_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 N_82_i sm_amiga_i_1__n N_78_i N_170_i N_77_0 CLK_000_D1_i CLK_OUT_PRE_25_0 \
-# N_76_i N_74_i N_72_0 AS_030_000_SYNC_i CLK_000_D2_i state_machine_un8_bgack_030_int_i_0_0_n cpu_est_0_ N_69_i cpu_est_1_ AS_030_c_i \
-# cpu_est_2_ N_65_i cpu_est_3_reg N_64_i N_62_i N_152_i N_153_i cpu_est_ns_1__n N_61_0 cpu_est_ns_2__n \
-# N_150_i state_machine_un8_bgack_030_int_i_0_n N_148_i N_197 N_149_i N_198 N_199 N_123_i N_200 N_145_i \
-# N_201 N_146_i sm_amiga_ns_0_0__n N_51 N_142_i N_53 N_143_i N_61 N_144_i N_62 \
-# cpu_est_ns_0_2__n N_64 N_141_i N_65 N_53_0 N_66 N_139_i N_69 state_machine_amiga_bus_enable_4_iv_i_n N_72 \
-# N_138_i N_74 N_48_i N_76 N_136_i N_77 N_137_i N_78 AMIGA_BUS_DATA_DIR_c_0 N_82 \
-# N_135_i N_86 N_168_i N_202 N_151_i N_203 N_132_i N_205 N_164_i N_206 \
-# N_115 N_130_i N_116 N_131_i N_117 N_41_0 N_118 N_128_i N_120 N_129_i \
-# N_121 sm_amiga_ns_0_5__n N_122 N_126_i N_123 N_127_i N_124 N_125 N_125_i N_126 \
-# N_127 N_124_i N_128 N_129 N_122_i N_130 N_131 N_172_i N_132 state_machine_size_dma_4_0_1__n \
-# N_133 state_machine_ds_000_dma_3_0_n N_134 N_66_i N_135 N_120_i N_136 state_machine_lds_000_int_7_0_n N_137 state_machine_uds_000_int_7_0_n \
-# N_138 N_118_i N_139 N_201_0 N_140 N_117_i N_141 N_200_0 N_142 N_115_i \
-# N_143 N_116_i N_144 N_199_0 N_145 BG_030_c_i N_146 N_206_i N_147 state_machine_un10_bg_030_0_n \
-# N_148 N_198_0 N_149 N_197_0 N_150 N_203_i N_152 state_machine_un13_clk_000_d0_i_n N_153 state_machine_un15_clk_000_d0_0_n \
-# N_164 state_machine_un6_bgack_000_0_n N_167 N_225_1 N_168 N_225_2 N_169 N_225_3 N_170 N_225_4 \
-# N_171 N_225_5 N_172 N_225_6 N_173 N_228_1 N_225 N_228_2 N_228 N_69_i_1 \
-# CLK_000_D0_i N_69_i_2 BGACK_030_INT_i N_69_i_3 CLK_030_i N_69_i_4 cpu_est_i_3__n N_69_i_5 sm_amiga_i_6__n state_machine_un8_bgack_030_int_i_0_0_1_n \
-# nEXP_SPACE_i N_72_0_1 CLK_000_D4_i N_51_0_1 sm_amiga_i_5__n N_51_0_2 sm_amiga_i_4__n cpu_est_ns_0_1_1__n AS_000_i cpu_est_ns_0_2_1__n \
-# LDS_000_i N_128_1 UDS_000_i N_128_2 cpu_est_i_1__n N_118_1 cpu_est_i_0__n N_118_2 DTACK_D0_i N_118_3 \
-# VMA_INT_i N_206_1 VPA_D_i N_206_2 AS_000_DMA_i sm_amiga_ns_0_1_0__n CLK_030_H_i cpu_est_ns_0_1_2__n RW_i N_53_0_1 \
-# cpu_est_i_2__n N_43_i_1 sm_amiga_i_0__n state_machine_lds_000_int_7_0_1_n sm_amiga_i_3__n state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_199_0_1 A0_i N_152_1 \
-# size_i_1__n N_147_1 DS_030_i N_139_1 a_i_19__n N_137_1 a_i_16__n N_127_1 a_i_18__n N_120_1 \
-# a_i_30__n state_machine_a0_dma_2_1_n a_i_31__n N_116_1 a_i_28__n N_115_1 a_i_29__n state_machine_un13_clk_000_d0_1_n a_i_26__n N_203_1 \
-# a_i_27__n state_machine_uds_000_int_7_0_m3_un3_n a_i_24__n state_machine_uds_000_int_7_0_m3_un1_n a_i_25__n state_machine_uds_000_int_7_0_m3_un0_n RST_i dsack1_int_0_un3_n dsack1_int_0_un1_n dsack1_int_0_un0_n \
-# N_205_i vma_int_0_un3_n FPU_CS_INT_i vma_int_0_un1_n CLK_OUT_PRE_50_D_i vma_int_0_un0_n AS_030_c bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_000_c \
-# bgack_030_int_0_un0_n ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n \
-# ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n \
-# a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n amiga_bus_enable_0_un3_n a_c_20__n \
-# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_21__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_22__n as_030_000_sync_0_un0_n clk_030_h_0_un3_n a_c_23__n clk_030_h_0_un1_n \
-# clk_030_h_0_un0_n a_c_24__n uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_25__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_26__n lds_000_int_0_un1_n lds_000_int_0_un0_n \
-# a_c_27__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_28__n fpu_cs_int_0_un0_n bg_000_0_un3_n a_c_29__n bg_000_0_un1_n bg_000_0_un0_n a_c_30__n \
-# ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_31__n ds_000_dma_0_un0_n as_000_dma_0_un3_n A0_c as_000_dma_0_un1_n as_000_dma_0_un0_n nEXP_SPACE_c as_000_int_0_un3_n \
-# as_000_int_0_un1_n as_000_int_0_un0_n BG_030_c BG_000DFFSHreg BGACK_000_c
+#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_
+#$ NODES 410 BG_030_c BG_000DFFSHreg inst_BGACK_030_INTreg BGACK_000_c inst_FPU_CS_INTreg inst_avec_expreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC CLK_000_c \
+# inst_BGACK_030_INT_D inst_AS_000_DMA CLK_OSZI_c inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 \
+# IPL_030DFFSH_0_reg inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ vcc_n_n IPL_030DFFSH_2_reg gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n \
+# inst_AS_000_INT SM_AMIGA_6_ ipl_c_1__n SM_AMIGA_0_ SM_AMIGA_5_ ipl_c_2__n SM_AMIGA_2_ inst_RW_000_INT DSACK1_c inst_UDS_000_INT \
+# inst_LDS_000_INT inst_DSACK1_INT state_machine_un3_clk_out_pre_50_n inst_CLK_000_D3 inst_CLK_030_H state_machine_un12_clk_000_d0_n inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ RST_c \
+# inst_A0_DMA AMIGA_BUS_ENABLE_INT_2_sqmuxa RESETDFFRHreg SM_AMIGA_4_ SM_AMIGA_3_ RW_c SM_AMIGA_1_ un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n \
+# state_machine_un10_bg_030_n state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i N_197_0 state_machine_ds_000_dma_3_0_n \
+# N_171_i state_machine_size_dma_4_0_1__n N_130_i N_131_i CLK_OUT_PRE_25_0 N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i \
+# N_139_i cpu_est_0_ N_140_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_141_i cpu_est_3_reg N_52_i N_143_i \
+# N_142_i state_machine_rw_000_int_7_iv_i_n cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 \
+# N_28 N_66_i N_30 N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 \
+# N_66 N_199_0 N_67 sm_amiga_i_2__n N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n \
+# N_75 N_167_i N_76 N_170_i N_77 N_136_i N_79 N_137_i N_90 N_202_0 \
+# N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i N_115 un1_DSACK1_INT_0_sqmuxa_3_0 \
+# N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 N_71_i N_121 N_69_i \
+# N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 N_145_i N_132 \
+# N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 N_142 \
+# N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i \
+# N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n \
+# N_168 N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i \
+# N_230 N_118_i N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i \
+# N_201 N_115_i N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 state_machine_un10_clk_000_d0_i_n \
+# N_135 state_machine_un12_clk_000_d0_0_n N_134 N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 \
+# state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n N_230_1 \
+# N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 \
+# sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n N_122_3 \
+# RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 \
+# AS_000_i N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n \
+# cpu_est_i_3__n state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 \
+# VMA_INT_i N_140_1 VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 \
+# A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 \
+# a_i_31__n bgack_030_int_0_un3_n a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n \
+# a_i_24__n as_000_dma_0_un0_n a_i_25__n ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n \
+# FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n \
+# RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c \
+# ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n \
+# cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n \
+# a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_23__n \
+# lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n avec_exp_0_un1_n \
+# avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \
+# a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c \
+#
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \
- VPA.BLIF RST.BLIF RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
- A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
- IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF DSACK_1_.BLIF AS_030.BLIF AS_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DTACK.BLIF SIZE_0_.BLIF DSACK_0_.BLIF CLK_030_c.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.BLIF CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \
- inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF IPL_030DFFSH_1_reg.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF IPL_030DFFSH_2_reg.BLIF \
- inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF ipl_c_0__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D4.BLIF ipl_c_1__n.BLIF inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF ipl_c_2__n.BLIF \
- inst_CLK_OUT_PRE_25.BLIF vcc_n_n.BLIF gnd_n_n.BLIF dsack_c_1__n.BLIF state_machine_un13_clk_000_d0_n.BLIF inst_AS_000_INT.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \
- SM_AMIGA_5_.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF clk_un3_clk_out_pre_50_n.BLIF RST_c.BLIF inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF RESETDFFRHreg.BLIF \
- state_machine_un6_bgack_000_n.BLIF state_machine_un15_clk_000_d0_n.BLIF RW_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF fc_c_0__n.BLIF SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF fc_c_1__n.BLIF \
- SM_AMIGA_7_.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF SM_AMIGA_4_.BLIF AMIGA_BUS_DATA_DIR_c.BLIF state_machine_ds_000_dma_3_n.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF cpu_est_ns_0_1__n.BLIF \
- state_machine_un10_bg_030_n.BLIF N_134_i.BLIF state_machine_lds_000_int_7_n.BLIF N_169_i.BLIF state_machine_uds_000_int_7_n.BLIF N_133_i.BLIF N_167_i.BLIF N_51_0.BLIF N_140_i.BLIF \
- N_202_0.BLIF N_86_0.BLIF N_171_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_82_i.BLIF sm_amiga_i_1__n.BLIF N_78_i.BLIF N_170_i.BLIF N_77_0.BLIF \
- CLK_000_D1_i.BLIF CLK_OUT_PRE_25_0.BLIF N_76_i.BLIF N_74_i.BLIF N_72_0.BLIF AS_030_000_SYNC_i.BLIF CLK_000_D2_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF cpu_est_0_.BLIF \
- N_69_i.BLIF cpu_est_1_.BLIF AS_030_c_i.BLIF cpu_est_2_.BLIF N_65_i.BLIF cpu_est_3_reg.BLIF N_64_i.BLIF N_62_i.BLIF N_152_i.BLIF \
- N_153_i.BLIF cpu_est_ns_1__n.BLIF N_61_0.BLIF cpu_est_ns_2__n.BLIF N_150_i.BLIF state_machine_un8_bgack_030_int_i_0_n.BLIF N_148_i.BLIF N_197.BLIF N_149_i.BLIF \
- N_198.BLIF N_199.BLIF N_123_i.BLIF N_200.BLIF N_145_i.BLIF N_201.BLIF N_146_i.BLIF sm_amiga_ns_0_0__n.BLIF N_51.BLIF \
- N_142_i.BLIF N_53.BLIF N_143_i.BLIF N_61.BLIF N_144_i.BLIF N_62.BLIF cpu_est_ns_0_2__n.BLIF N_64.BLIF N_141_i.BLIF \
- N_65.BLIF N_53_0.BLIF N_66.BLIF N_139_i.BLIF N_69.BLIF state_machine_amiga_bus_enable_4_iv_i_n.BLIF N_72.BLIF N_138_i.BLIF N_74.BLIF \
- N_48_i.BLIF N_76.BLIF N_136_i.BLIF N_77.BLIF N_137_i.BLIF N_78.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_82.BLIF N_135_i.BLIF \
- N_86.BLIF N_168_i.BLIF N_202.BLIF N_151_i.BLIF N_203.BLIF N_132_i.BLIF N_205.BLIF N_164_i.BLIF N_206.BLIF \
- N_115.BLIF N_130_i.BLIF N_116.BLIF N_131_i.BLIF N_117.BLIF N_41_0.BLIF N_118.BLIF N_128_i.BLIF N_120.BLIF \
- N_129_i.BLIF N_121.BLIF sm_amiga_ns_0_5__n.BLIF N_122.BLIF N_126_i.BLIF N_123.BLIF N_127_i.BLIF N_124.BLIF N_125.BLIF \
- N_125_i.BLIF N_126.BLIF N_127.BLIF N_124_i.BLIF N_128.BLIF N_129.BLIF N_122_i.BLIF N_130.BLIF N_131.BLIF \
- N_172_i.BLIF N_132.BLIF state_machine_size_dma_4_0_1__n.BLIF N_133.BLIF state_machine_ds_000_dma_3_0_n.BLIF N_134.BLIF N_66_i.BLIF N_135.BLIF N_120_i.BLIF \
- N_136.BLIF state_machine_lds_000_int_7_0_n.BLIF N_137.BLIF state_machine_uds_000_int_7_0_n.BLIF N_138.BLIF N_118_i.BLIF N_139.BLIF N_201_0.BLIF N_140.BLIF \
- N_117_i.BLIF N_141.BLIF N_200_0.BLIF N_142.BLIF N_115_i.BLIF N_143.BLIF N_116_i.BLIF N_144.BLIF N_199_0.BLIF \
- N_145.BLIF BG_030_c_i.BLIF N_146.BLIF N_206_i.BLIF N_147.BLIF state_machine_un10_bg_030_0_n.BLIF N_148.BLIF N_198_0.BLIF N_149.BLIF \
- N_197_0.BLIF N_150.BLIF N_203_i.BLIF N_152.BLIF state_machine_un13_clk_000_d0_i_n.BLIF N_153.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_164.BLIF state_machine_un6_bgack_000_0_n.BLIF \
- N_167.BLIF N_225_1.BLIF N_168.BLIF N_225_2.BLIF N_169.BLIF N_225_3.BLIF N_170.BLIF N_225_4.BLIF N_171.BLIF \
- N_225_5.BLIF N_172.BLIF N_225_6.BLIF N_173.BLIF N_228_1.BLIF N_225.BLIF N_228_2.BLIF N_228.BLIF N_69_i_1.BLIF \
- CLK_000_D0_i.BLIF N_69_i_2.BLIF BGACK_030_INT_i.BLIF N_69_i_3.BLIF CLK_030_i.BLIF N_69_i_4.BLIF cpu_est_i_3__n.BLIF N_69_i_5.BLIF sm_amiga_i_6__n.BLIF \
- state_machine_un8_bgack_030_int_i_0_0_1_n.BLIF nEXP_SPACE_i.BLIF N_72_0_1.BLIF CLK_000_D4_i.BLIF N_51_0_1.BLIF sm_amiga_i_5__n.BLIF N_51_0_2.BLIF sm_amiga_i_4__n.BLIF cpu_est_ns_0_1_1__n.BLIF \
- AS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF LDS_000_i.BLIF N_128_1.BLIF UDS_000_i.BLIF N_128_2.BLIF cpu_est_i_1__n.BLIF N_118_1.BLIF cpu_est_i_0__n.BLIF \
- N_118_2.BLIF DTACK_D0_i.BLIF N_118_3.BLIF VMA_INT_i.BLIF N_206_1.BLIF VPA_D_i.BLIF N_206_2.BLIF AS_000_DMA_i.BLIF sm_amiga_ns_0_1_0__n.BLIF \
- CLK_030_H_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_i.BLIF N_53_0_1.BLIF cpu_est_i_2__n.BLIF N_43_i_1.BLIF sm_amiga_i_0__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF sm_amiga_i_3__n.BLIF \
- state_machine_uds_000_int_7_0_1_n.BLIF sm_amiga_i_7__n.BLIF N_199_0_1.BLIF A0_i.BLIF N_152_1.BLIF size_i_1__n.BLIF N_147_1.BLIF DS_030_i.BLIF N_139_1.BLIF \
- a_i_19__n.BLIF N_137_1.BLIF a_i_16__n.BLIF N_127_1.BLIF a_i_18__n.BLIF N_120_1.BLIF a_i_30__n.BLIF state_machine_a0_dma_2_1_n.BLIF a_i_31__n.BLIF \
- N_116_1.BLIF a_i_28__n.BLIF N_115_1.BLIF a_i_29__n.BLIF state_machine_un13_clk_000_d0_1_n.BLIF a_i_26__n.BLIF N_203_1.BLIF a_i_27__n.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
- a_i_24__n.BLIF state_machine_uds_000_int_7_0_m3_un1_n.BLIF a_i_25__n.BLIF state_machine_uds_000_int_7_0_m3_un0_n.BLIF RST_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_205_i.BLIF \
- vma_int_0_un3_n.BLIF FPU_CS_INT_i.BLIF vma_int_0_un1_n.BLIF CLK_OUT_PRE_50_D_i.BLIF vma_int_0_un0_n.BLIF AS_030_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF AS_000_c.BLIF \
- bgack_030_int_0_un0_n.BLIF ipl_030_0_0__un3_n.BLIF DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF LDS_000_c.BLIF \
- ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_16__n.BLIF \
- cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_19__n.BLIF \
- cpu_estse_2_un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF a_c_20__n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF a_c_21__n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF a_c_22__n.BLIF \
- as_030_000_sync_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_23__n.BLIF clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_24__n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_25__n.BLIF \
- uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_26__n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_27__n.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_28__n.BLIF \
- fpu_cs_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF a_c_29__n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF a_c_30__n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_31__n.BLIF \
- ds_000_dma_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF A0_c.BLIF as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF nEXP_SPACE_c.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF \
- BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN \
- SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN
+ VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
+ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF \
+ IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF inst_BGACK_030_INTreg.BLIF BGACK_000_c.BLIF inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF CLK_030_c.BLIF \
+ inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF CLK_OSZI_c.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF \
+ CLK_OUT_INTreg.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF IPL_030DFFSH_1_reg.BLIF SM_AMIGA_7_.BLIF \
+ vcc_n_n.BLIF IPL_030DFFSH_2_reg.BLIF gnd_n_n.BLIF state_machine_un10_clk_000_d0_n.BLIF ipl_c_0__n.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF ipl_c_1__n.BLIF SM_AMIGA_0_.BLIF \
+ SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF DSACK1_c.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
+ inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF state_machine_un12_clk_000_d0_n.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF RST_c.BLIF inst_A0_DMA.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \
+ RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF un1_DSACK1_INT_0_sqmuxa_3.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un10_bg_030_n.BLIF \
+ state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF state_machine_un6_bgack_000_0_n.BLIF N_194_0.BLIF N_119_i.BLIF N_120_i.BLIF N_197_0.BLIF state_machine_ds_000_dma_3_0_n.BLIF \
+ N_171_i.BLIF state_machine_size_dma_4_0_1__n.BLIF N_130_i.BLIF N_131_i.BLIF CLK_OUT_PRE_25_0.BLIF N_132_i.BLIF N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n.BLIF \
+ N_135_i.BLIF N_139_i.BLIF cpu_est_0_.BLIF N_140_i.BLIF cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_141_i.BLIF cpu_est_3_reg.BLIF \
+ N_52_i.BLIF N_143_i.BLIF N_142_i.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF cpu_est_ns_1__n.BLIF N_62_0.BLIF cpu_est_ns_2__n.BLIF N_161_i.BLIF N_193.BLIF \
+ N_155_i.BLIF N_196.BLIF N_63_0.BLIF N_28.BLIF N_66_i.BLIF N_30.BLIF N_76_i.BLIF N_55.BLIF CLK_000_D1_i.BLIF \
+ N_62.BLIF N_77_i.BLIF N_63.BLIF N_79_0.BLIF N_66.BLIF N_199_0.BLIF N_67.BLIF sm_amiga_i_2__n.BLIF N_69.BLIF \
+ N_201_0.BLIF N_70.BLIF N_203_0.BLIF N_71.BLIF cpu_est_ns_0_1__n.BLIF N_75.BLIF N_167_i.BLIF N_76.BLIF N_170_i.BLIF \
+ N_77.BLIF N_136_i.BLIF N_79.BLIF N_137_i.BLIF N_90.BLIF N_202_0.BLIF N_200.BLIF N_200_0.BLIF N_202.BLIF \
+ N_169_i.BLIF N_204.BLIF N_198_0.BLIF N_114.BLIF N_168_i.BLIF N_115.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_116.BLIF N_90_i.BLIF \
+ N_117.BLIF AS_030_c_i.BLIF N_118.BLIF N_75_i.BLIF N_120.BLIF N_71_i.BLIF N_121.BLIF N_69_i.BLIF N_122.BLIF \
+ N_67_i.BLIF N_124.BLIF N_150_i.BLIF N_125.BLIF N_151_i.BLIF N_128.BLIF N_129.BLIF N_145_i.BLIF N_132.BLIF \
+ N_146_i.BLIF N_136.BLIF N_147_i.BLIF N_137.BLIF cpu_est_ns_0_2__n.BLIF N_138.BLIF N_144_i.BLIF N_140.BLIF N_55_0.BLIF \
+ N_142.BLIF N_138_i.BLIF N_144.BLIF N_172_i.BLIF N_145.BLIF N_149_i.BLIF N_146.BLIF N_129_i.BLIF N_147.BLIF \
+ N_148.BLIF N_128_i.BLIF N_150.BLIF sm_amiga_ns_0_0__n.BLIF N_151.BLIF N_70_i.BLIF N_155.BLIF N_124_i.BLIF N_166.BLIF \
+ state_machine_lds_000_int_7_0_n.BLIF N_167.BLIF state_machine_uds_000_int_7_0_n.BLIF N_168.BLIF N_122_i.BLIF N_169.BLIF N_30_0.BLIF N_170.BLIF N_121_i.BLIF \
+ N_172.BLIF N_28_0.BLIF N_220.BLIF N_117_i.BLIF N_230.BLIF N_118_i.BLIF N_133.BLIF N_196_0.BLIF N_143.BLIF \
+ N_116_i.BLIF N_143_2.BLIF N_195_i.BLIF N_203.BLIF BG_030_c_i.BLIF N_201.BLIF N_115_i.BLIF N_199.BLIF state_machine_un10_bg_030_0_n.BLIF \
+ N_161.BLIF N_193_0.BLIF N_141.BLIF N_204_i.BLIF N_139.BLIF state_machine_un10_clk_000_d0_i_n.BLIF N_135.BLIF state_machine_un12_clk_000_d0_0_n.BLIF N_134.BLIF \
+ N_69_i_1.BLIF N_131.BLIF N_76_i_1.BLIF N_130.BLIF N_76_i_2.BLIF N_171.BLIF N_76_i_3.BLIF state_machine_ds_000_dma_3_n.BLIF N_76_i_4.BLIF \
+ N_197.BLIF N_76_i_5.BLIF N_119.BLIF N_220_1.BLIF N_194.BLIF N_220_2.BLIF state_machine_un6_bgack_000_n.BLIF N_230_1.BLIF N_143_2_i.BLIF \
+ N_230_2.BLIF a_i_18__n.BLIF N_230_3.BLIF a_i_16__n.BLIF N_230_4.BLIF a_i_19__n.BLIF N_230_5.BLIF sm_amiga_i_4__n.BLIF N_230_6.BLIF \
+ sm_amiga_i_5__n.BLIF cpu_est_ns_0_1_1__n.BLIF sm_amiga_i_3__n.BLIF cpu_est_ns_0_2_1__n.BLIF CLK_000_D0_i.BLIF N_122_1.BLIF sm_amiga_i_0__n.BLIF N_122_2.BLIF sm_amiga_i_1__n.BLIF \
+ N_122_3.BLIF RW_i.BLIF N_115_1.BLIF CLK_030_H_i.BLIF N_115_2.BLIF CLK_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF \
+ BGACK_030_INT_i.BLIF N_133_1.BLIF AS_000_i.BLIF N_133_2.BLIF UDS_000_i.BLIF N_143_1.BLIF LDS_000_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_000_i.BLIF \
+ N_55_0_1.BLIF sm_amiga_i_6__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF cpu_est_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF sm_amiga_i_7__n.BLIF N_196_0_1.BLIF CLK_000_D2_i.BLIF N_155_1.BLIF \
+ cpu_est_i_1__n.BLIF N_148_1.BLIF cpu_est_i_0__n.BLIF N_142_1.BLIF VMA_INT_i.BLIF N_140_1.BLIF VPA_D_i.BLIF N_132_1.BLIF AS_000_DMA_i.BLIF \
+ N_124_1.BLIF nEXP_SPACE_i.BLIF state_machine_a0_dma_2_1_n.BLIF cpu_est_i_2__n.BLIF N_120_1.BLIF A0_i.BLIF N_118_1.BLIF size_i_1__n.BLIF N_117_1.BLIF \
+ DS_030_i.BLIF N_116_1.BLIF AS_030_000_SYNC_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF a_i_30__n.BLIF N_204_1.BLIF a_i_31__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_28__n.BLIF \
+ bgack_030_int_0_un1_n.BLIF a_i_29__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_26__n.BLIF as_000_dma_0_un3_n.BLIF a_i_27__n.BLIF as_000_dma_0_un1_n.BLIF a_i_24__n.BLIF as_000_dma_0_un0_n.BLIF \
+ a_i_25__n.BLIF ds_000_dma_0_un3_n.BLIF RST_i.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF N_114_i.BLIF clk_030_h_0_un1_n.BLIF FPU_CS_INT_i.BLIF \
+ clk_030_h_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_int_0_un3_n.BLIF AS_030_c.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF AS_000_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF state_machine_uds_000_int_7_0_m3_un1_n.BLIF \
+ RW_000_c.BLIF state_machine_uds_000_int_7_0_m3_un0_n.BLIF ipl_030_0_0__un3_n.BLIF DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF \
+ LDS_000_c.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF \
+ a_c_16__n.BLIF cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF \
+ a_c_19__n.BLIF cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF a_c_20__n.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF a_c_21__n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF \
+ a_c_22__n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_23__n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_24__n.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF \
+ a_c_25__n.BLIF fpu_cs_int_0_un0_n.BLIF avec_exp_0_un3_n.BLIF a_c_26__n.BLIF avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF a_c_27__n.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \
+ a_c_28__n.BLIF bg_000_0_un0_n.BLIF as_000_int_0_un3_n.BLIF a_c_29__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF a_c_30__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF \
+ a_c_31__n.BLIF dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF A0_c.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF nEXP_SPACE_c.BLIF AS_030.PIN AS_000.PIN \
+ RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN \
+ RW.PIN
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC AVEC_EXP E VMA \
RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D \
cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \
@@ -101,53 +103,53 @@
IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \
SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \
inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \
- inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \
- inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
- inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP AMIGA_BUS_ENABLEDFFSHreg.D AMIGA_BUS_ENABLEDFFSHreg.C AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C \
- inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D3.D inst_CLK_000_D3.C \
- inst_CLK_000_D3.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \
+ inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \
+ inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
+ inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C \
+ inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \
+ inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \
- inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 DTACK SIZE_0_ DSACK_0_ CLK_030_c CLK_000_c CLK_OSZI_c \
- ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n state_machine_un13_clk_000_d0_n clk_un3_clk_out_pre_50_n RST_c state_machine_un6_bgack_000_n state_machine_un15_clk_000_d0_n \
- RW_c fc_c_0__n fc_c_1__n un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 AMIGA_BUS_DATA_DIR_c state_machine_ds_000_dma_3_n cpu_est_ns_0_1__n state_machine_un10_bg_030_n N_134_i state_machine_lds_000_int_7_n N_169_i \
- state_machine_uds_000_int_7_n N_133_i N_167_i N_51_0 N_140_i N_202_0 N_86_0 N_171_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 N_82_i sm_amiga_i_1__n \
- N_78_i N_170_i N_77_0 CLK_000_D1_i N_76_i N_74_i N_72_0 AS_030_000_SYNC_i CLK_000_D2_i state_machine_un8_bgack_030_int_i_0_0_n N_69_i \
- AS_030_c_i N_65_i N_64_i N_62_i N_152_i N_153_i cpu_est_ns_1__n N_61_0 cpu_est_ns_2__n N_150_i state_machine_un8_bgack_030_int_i_0_n \
- N_148_i N_197 N_149_i N_198 N_199 N_123_i N_200 N_145_i N_201 N_146_i sm_amiga_ns_0_0__n \
- N_51 N_142_i N_53 N_143_i N_61 N_144_i N_62 cpu_est_ns_0_2__n N_64 N_141_i N_65 \
- N_53_0 N_66 N_139_i N_69 state_machine_amiga_bus_enable_4_iv_i_n N_72 N_138_i N_74 N_48_i N_76 N_136_i \
- N_77 N_137_i N_78 AMIGA_BUS_DATA_DIR_c_0 N_82 N_135_i N_86 N_168_i N_202 N_151_i N_203 \
- N_132_i N_205 N_164_i N_206 N_115 N_130_i N_116 N_131_i N_117 N_41_0 N_118 \
- N_128_i N_120 N_129_i N_121 sm_amiga_ns_0_5__n N_122 N_126_i N_123 N_127_i N_124 N_125 \
- N_125_i N_126 N_127 N_124_i N_128 N_129 N_122_i N_130 N_131 N_172_i N_132 \
- state_machine_size_dma_4_0_1__n N_133 state_machine_ds_000_dma_3_0_n N_134 N_66_i N_135 N_120_i N_136 state_machine_lds_000_int_7_0_n N_137 state_machine_uds_000_int_7_0_n \
- N_138 N_118_i N_139 N_201_0 N_140 N_117_i N_141 N_200_0 N_142 N_115_i N_143 \
- N_116_i N_144 N_199_0 N_145 BG_030_c_i N_146 N_206_i N_147 state_machine_un10_bg_030_0_n N_148 N_198_0 \
- N_149 N_197_0 N_150 N_203_i N_152 state_machine_un13_clk_000_d0_i_n N_153 state_machine_un15_clk_000_d0_0_n N_164 state_machine_un6_bgack_000_0_n N_167 \
- N_225_1 N_168 N_225_2 N_169 N_225_3 N_170 N_225_4 N_171 N_225_5 N_172 N_225_6 \
- N_173 N_228_1 N_225 N_228_2 N_228 N_69_i_1 CLK_000_D0_i N_69_i_2 BGACK_030_INT_i N_69_i_3 CLK_030_i \
- N_69_i_4 cpu_est_i_3__n N_69_i_5 sm_amiga_i_6__n state_machine_un8_bgack_030_int_i_0_0_1_n nEXP_SPACE_i N_72_0_1 CLK_000_D4_i N_51_0_1 sm_amiga_i_5__n N_51_0_2 \
- sm_amiga_i_4__n cpu_est_ns_0_1_1__n AS_000_i cpu_est_ns_0_2_1__n LDS_000_i N_128_1 UDS_000_i N_128_2 cpu_est_i_1__n N_118_1 cpu_est_i_0__n \
- N_118_2 DTACK_D0_i N_118_3 VMA_INT_i N_206_1 VPA_D_i N_206_2 AS_000_DMA_i sm_amiga_ns_0_1_0__n CLK_030_H_i cpu_est_ns_0_1_2__n \
- RW_i N_53_0_1 cpu_est_i_2__n N_43_i_1 sm_amiga_i_0__n state_machine_lds_000_int_7_0_1_n sm_amiga_i_3__n state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_199_0_1 A0_i \
- N_152_1 size_i_1__n N_147_1 DS_030_i N_139_1 a_i_19__n N_137_1 a_i_16__n N_127_1 a_i_18__n N_120_1 \
- a_i_30__n state_machine_a0_dma_2_1_n a_i_31__n N_116_1 a_i_28__n N_115_1 a_i_29__n state_machine_un13_clk_000_d0_1_n a_i_26__n N_203_1 a_i_27__n \
- state_machine_uds_000_int_7_0_m3_un3_n a_i_24__n state_machine_uds_000_int_7_0_m3_un1_n a_i_25__n state_machine_uds_000_int_7_0_m3_un0_n RST_i dsack1_int_0_un3_n dsack1_int_0_un1_n dsack1_int_0_un0_n N_205_i vma_int_0_un3_n \
- FPU_CS_INT_i vma_int_0_un1_n CLK_OUT_PRE_50_D_i vma_int_0_un0_n AS_030_c bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_000_c bgack_030_int_0_un0_n ipl_030_0_0__un3_n DS_030_c \
- ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \
- size_c_1__n cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n \
- cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n amiga_bus_enable_0_un3_n a_c_20__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_21__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_22__n \
- as_030_000_sync_0_un0_n clk_030_h_0_un3_n a_c_23__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_24__n uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_25__n uds_000_int_0_un0_n lds_000_int_0_un3_n \
- a_c_26__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_27__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_28__n fpu_cs_int_0_un0_n bg_000_0_un3_n a_c_29__n bg_000_0_un1_n \
- bg_000_0_un0_n a_c_30__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_31__n ds_000_dma_0_un0_n as_000_dma_0_un3_n A0_c as_000_dma_0_un1_n as_000_dma_0_un0_n nEXP_SPACE_c \
- as_000_int_0_un3_n as_000_int_0_un1_n as_000_int_0_un0_n BG_030_c BGACK_000_c AS_030.OE AS_000.OE DS_030.OE UDS_000.OE \
- LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE \
- CIIN.OE
+ inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ BG_030_c BGACK_000_c CLK_030_c \
+ CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c state_machine_un3_clk_out_pre_50_n state_machine_un12_clk_000_d0_n \
+ RST_c AMIGA_BUS_ENABLE_INT_2_sqmuxa RW_c un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n \
+ N_194_0 N_119_i N_120_i N_197_0 state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n N_130_i N_131_i N_132_i N_133_i \
+ N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i N_140_i AMIGA_BUS_DATA_DIR_c_0 N_141_i N_52_i N_143_i N_142_i state_machine_rw_000_int_7_iv_i_n \
+ cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i N_30 \
+ N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n \
+ N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 \
+ N_136_i N_79 N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 \
+ N_114 N_168_i N_115 un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 \
+ N_71_i N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 \
+ N_145_i N_132 N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 \
+ N_142 N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i \
+ N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n N_168 \
+ N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i N_230 N_118_i \
+ N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i N_201 N_115_i N_199 \
+ state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n N_134 N_69_i_1 \
+ N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 \
+ N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n N_230_1 N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 \
+ a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n \
+ N_122_2 sm_amiga_i_1__n N_122_3 RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n DTACK_D0_i state_machine_un10_clk_000_d0_2_n \
+ BGACK_030_INT_i N_133_1 AS_000_i N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 sm_amiga_i_6__n \
+ state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 \
+ VMA_INT_i N_140_1 VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 A0_i \
+ N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n bgack_030_int_0_un3_n \
+ a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n a_i_25__n \
+ ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n \
+ AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n \
+ ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n \
+ cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n \
+ a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n \
+ lds_000_int_0_un3_n a_c_23__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n \
+ avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \
+ a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c \
+ AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE \
+ DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE
.names inst_AS_000_DMA.BLIF AS_030
1 1
.names AS_030.PIN AS_030_c
1 1
-.names N_147.BLIF AS_030.OE
+.names N_148.BLIF AS_030.OE
1 1
.names inst_AS_000_INT.BLIF AS_000
1 1
@@ -155,11 +157,17 @@
1 1
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+.names RW_000.PIN RW_000_c
+1 1
+.names inst_BGACK_030_INTreg.BLIF RW_000.OE
+1 1
.names inst_DS_000_DMA.BLIF DS_030
1 1
.names DS_030.PIN DS_030_c
1 1
-.names N_147.BLIF DS_030.OE
+.names N_148.BLIF DS_030.OE
1 1
.names inst_UDS_000_INT.BLIF UDS_000
1 1
@@ -177,1061 +185,1068 @@
1 1
.names SIZE_0_.PIN size_c_0__n
1 1
-.names N_147.BLIF SIZE_0_.OE
+.names N_148.BLIF SIZE_0_.OE
1 1
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
.names SIZE_1_.PIN size_c_1__n
1 1
-.names N_147.BLIF SIZE_1_.OE
+.names N_148.BLIF SIZE_1_.OE
1 1
.names inst_A0_DMA.BLIF A0
1 1
.names A0.PIN A0_c
1 1
-.names N_147.BLIF A0.OE
+.names N_148.BLIF A0.OE
1 1
-.names inst_DSACK1_INT.BLIF DSACK_1_
+.names inst_DSACK1_INT.BLIF DSACK1
1 1
-.names DSACK_1_.PIN dsack_c_1__n
+.names DSACK1.PIN DSACK1_c
1 1
-.names nEXP_SPACE_c.BLIF DSACK_1_.OE
+.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
-.names dsack_c_1__n.BLIF DTACK
+.names DSACK1_c.BLIF DTACK
1 1
.names DTACK.PIN inst_DTACK_D0.D
1 1
-.names N_147.BLIF DTACK.OE
+.names N_148.BLIF DTACK.OE
+1 1
+.names inst_RW_000_INT.BLIF RW
+1 1
+.names RW.PIN RW_c
+1 1
+.names BGACK_030_INT_i.BLIF RW.OE
1 1
.names gnd_n_n.BLIF BERR
1 1
.names FPU_CS_INT_i.BLIF BERR.OE
1 1
-.names vcc_n_n.BLIF DSACK_0_
+.names N_220.BLIF CIIN
1 1
-.names nEXP_SPACE_c.BLIF DSACK_0_.OE
+.names N_230.BLIF CIIN.OE
1 1
-.names gnd_n_n.BLIF AVEC_EXP
+.names N_90_i.BLIF N_90
+0 1
+.names AS_030_c.BLIF AS_030_c_i
+0 1
+.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR
1 1
-.names FPU_CS_INT_i.BLIF AVEC_EXP.OE
+.names N_75_i.BLIF N_75
+0 1
+.names N_71_i.BLIF N_71
+0 1
+.names N_69_i.BLIF N_69
+0 1
+.names CLK_000_c.BLIF inst_CLK_000_D0.D
1 1
-.names N_228.BLIF CIIN
+.names N_67_i.BLIF N_67
+0 1
+.names N_150.BLIF N_150_i
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
-.names N_225.BLIF CIIN.OE
+.names N_151.BLIF N_151_i
+0 1
+.names N_161.BLIF N_161_i
+0 1
+.names RST_i.BLIF inst_CLK_000_D0.AP
+1 1
+.names N_155.BLIF N_155_i
+0 1
+.names N_63_0.BLIF N_63
+0 1
+.names N_66_i.BLIF N_66
+0 1
+.names N_76_i.BLIF N_76
+0 1
+.names CLK_OSZI_c.BLIF inst_VPA_D.C
+1 1
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
+0 1
+.names N_77_i.BLIF N_77
+0 1
+.names RST_i.BLIF inst_VPA_D.AP
+1 1
+.names N_79_0.BLIF N_79
+0 1
+.names N_199_0.BLIF N_199
+0 1
+.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+0 1
+.names CLK_OSZI_c.BLIF cpu_est_0_.C
+1 1
+.names N_201_0.BLIF N_201
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
+1 1
+.names N_203_0.BLIF N_203
+0 1
+.names RST_i.BLIF cpu_est_0_.AR
+1 1
+.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
+0 1
+.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR
+1 1
+.names N_167.BLIF N_167_i
+0 1
+.names N_170.BLIF N_170_i
+0 1
+.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
+0 1
+.names CLK_OSZI_c.BLIF cpu_est_1_.C
+1 1
+.names vcc_n_n.BLIF RESETDFFRHreg.D
1 1
.names N_130.BLIF N_130_i
0 1
.names N_131.BLIF N_131_i
0 1
-.names CLK_000_c.BLIF inst_CLK_000_D0.D
-1 1
-.names N_41_0.BLIF SM_AMIGA_1_.D
-0 1
-.names N_128.BLIF N_128_i
-0 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
-1 1
-.names N_129.BLIF N_129_i
-0 1
-.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
-0 1
-.names RST_i.BLIF inst_CLK_000_D0.AP
-1 1
-.names N_153.BLIF N_153_i
-0 1
-.names N_61_0.BLIF N_61
-0 1
-.names N_150.BLIF N_150_i
-0 1
-.names N_148.BLIF N_148_i
-0 1
-.names CLK_OSZI_c.BLIF inst_VPA_D.C
-1 1
-.names N_149.BLIF N_149_i
-0 1
-.names N_123.BLIF N_123_i
-0 1
-.names RST_i.BLIF inst_VPA_D.AP
-1 1
-.names N_145.BLIF N_145_i
-0 1
-.names N_146.BLIF N_146_i
-0 1
-.names CLK_OSZI_c.BLIF cpu_est_0_.C
-1 1
-.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
-0 1
-.names N_142.BLIF N_142_i
-0 1
-.names RST_i.BLIF cpu_est_0_.AR
-1 1
-.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
-1 1
-.names N_143.BLIF N_143_i
-0 1
-.names N_144.BLIF N_144_i
-0 1
-.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR
-1 1
-.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
-0 1
-.names N_141.BLIF N_141_i
-0 1
-.names CLK_OSZI_c.BLIF cpu_est_1_.C
-1 1
-.names N_53_0.BLIF N_53
-0 1
-.names vcc_n_n.BLIF RESETDFFRHreg.D
-1 1
-.names N_170.BLIF N_170_i
-0 1
.names RST_i.BLIF cpu_est_1_.AR
1 1
-.names N_77_0.BLIF N_77
-0 1
.names CLK_OSZI_c.BLIF RESETDFFRHreg.C
1 1
-.names inst_CLK_000_D1.BLIF CLK_000_D1_i
-0 1
-.names N_76_i.BLIF N_76
-0 1
-.names RST_i.BLIF RESETDFFRHreg.AR
-1 1
-.names N_74_i.BLIF N_74
-0 1
-.names CLK_OSZI_c.BLIF cpu_est_2_.C
-1 1
-.names N_72_0.BLIF N_72
-0 1
-.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
-0 1
-.names RST_i.BLIF cpu_est_2_.AR
-1 1
-.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1
-1 1
-.names inst_CLK_000_D2.BLIF CLK_000_D2_i
-0 1
-.names state_machine_un8_bgack_030_int_i_0_0_n.BLIF state_machine_un8_bgack_030_int_i_0_n
-0 1
-.names clk_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2
-1 1
-.names N_69_i.BLIF N_69
-0 1
-.names AS_030_c.BLIF AS_030_c_i
-0 1
-.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
-1 1
-.names N_65_i.BLIF N_65
-0 1
-.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
-1 1
-.names N_64_i.BLIF N_64
-0 1
-.names RST_i.BLIF cpu_est_3_reg.AR
-1 1
-.names N_62_i.BLIF N_62
-0 1
-.names N_152.BLIF N_152_i
-0 1
-.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
-0 1
-.names N_134.BLIF N_134_i
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
-1 1
-.names N_169.BLIF N_169_i
+.names N_132.BLIF N_132_i
0 1
.names N_133.BLIF N_133_i
0 1
-.names RST_i.BLIF SM_AMIGA_0_.AR
+.names RST_i.BLIF RESETDFFRHreg.AR
1 1
-.names N_167.BLIF N_167_i
+.names N_134.BLIF N_134_i
0 1
-.names N_51_0.BLIF N_51
+.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
+.names CLK_OSZI_c.BLIF cpu_est_2_.C
+1 1
+.names N_135.BLIF N_135_i
+0 1
+.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1
+1 1
+.names N_139.BLIF N_139_i
+0 1
+.names RST_i.BLIF cpu_est_2_.AR
+1 1
.names N_140.BLIF N_140_i
0 1
-.names N_202_0.BLIF N_202
+.names state_machine_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2
+1 1
+.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
+0 1
+.names N_141.BLIF N_141_i
+0 1
+.names N_143.BLIF N_143_i
+0 1
+.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
+1 1
+.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
+1 1
+.names N_142.BLIF N_142_i
+0 1
+.names N_62_0.BLIF N_62
+0 1
+.names RST_i.BLIF cpu_est_3_reg.AR
+1 1
+.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+0 1
+.names N_194_0.BLIF N_194
+0 1
+.names N_119.BLIF N_119_i
+0 1
+.names N_120.BLIF N_120_i
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
+1 1
+.names N_197_0.BLIF N_197
+0 1
+.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
+0 1
+.names RST_i.BLIF SM_AMIGA_0_.AR
+1 1
+.names N_171.BLIF N_171_i
+0 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names a_c_18__n.BLIF a_i_18__n
+0 1
+.names a_c_16__n.BLIF a_i_16__n
0 1
.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
1 1
-.names N_86_0.BLIF N_86
-0 1
-.names N_171.BLIF N_171_i
-0 1
-.names RST_i.BLIF SIZE_DMA_1_.AP
-1 1
-.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2
-0 1
-.names N_82_i.BLIF N_82
-0 1
-.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
-0 1
-.names N_78_i.BLIF N_78
-0 1
-.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
-1 1
-.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
-0 1
-.names inst_CLK_000_D0.BLIF CLK_000_D0_i
-0 1
-.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
-1 1
-.names inst_CLK_000_D4.BLIF SM_AMIGA_5_.BLIF N_64_i
-11 1
-.names AS_030_c_i.BLIF N_205_i.BLIF N_65_i
-11 1
-.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n
-0 1
-.names N_64.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n
-11 1
-.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
-1 1
-.names N_62.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF state_machine_uds_000_int_7_0_m3_un0_n
-11 1
-.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_66
-1- 1
--1 1
-.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
-1 1
-.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
-0 1
-.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
-0 1
-.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_74_i
-11 1
-.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_76_i
-11 1
-.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
-1 1
-.names CLK_000_D0_i.BLIF N_170_i.BLIF N_77_0
-11 1
-.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_78_i
-11 1
-.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
-1 1
-.names cpu_est_3_reg.BLIF cpu_est_i_3__n
-0 1
-.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_82_i
-11 1
-.names N_65_i.BLIF N_171_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0
-11 1
-.names CLK_000_D0_i.BLIF N_74_i.BLIF N_86_0
-11 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
-1 1
-.names CLK_030_c.BLIF CLK_030_i
-0 1
-.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_202_0
-11 1
-.names RST_i.BLIF SM_AMIGA_7_.AP
-1 1
-.names inst_CLK_000_D0.BLIF N_124_i.BLIF SM_AMIGA_5_.D
-11 1
-.names CLK_000_D0_i.BLIF N_125_i.BLIF SM_AMIGA_4_.D
-11 1
-.names N_126_i.BLIF N_127_i.BLIF SM_AMIGA_3_.D
-11 1
-.names N_128_i.BLIF N_129_i.BLIF sm_amiga_ns_0_5__n
-11 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
-1 1
-.names N_130_i.BLIF N_131_i.BLIF N_41_0
-11 1
-.names N_135_i.BLIF N_168_i.BLIF N_151_i
-11 1
-.names RST_i.BLIF SM_AMIGA_6_.AR
-1 1
-.names N_136_i.BLIF N_137_i.BLIF AMIGA_BUS_DATA_DIR_c_0
-11 1
-.names N_138_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_48_i
-11 1
-.names inst_BGACK_030_INTreg.BLIF N_139_i.BLIF state_machine_amiga_bus_enable_4_iv_i_n
-11 1
-.names N_148_i.BLIF N_149_i.BLIF cpu_est_0_.D
-11 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
-1 1
-.names N_152_i.BLIF N_153_i.BLIF N_61_0
-11 1
-.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
-0 1
-.names RST_i.BLIF SM_AMIGA_5_.AR
-1 1
-.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_62_i
-11 1
-.names inst_CLK_000_D4.BLIF CLK_000_D4_i
-0 1
-.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
-0 1
-.names LDS_000_c.BLIF LDS_000_i
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
-1 1
-.names UDS_000_c.BLIF UDS_000_i
-0 1
-.names LDS_000_i.BLIF UDS_000_i.BLIF N_172
-11 1
-.names RST_i.BLIF SM_AMIGA_4_.AR
-1 1
-.names AS_000_c.BLIF AS_000_i
-0 1
-.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_173
-11 1
-.names BGACK_000_c.BLIF N_76.BLIF state_machine_un6_bgack_000_0_n
-11 1
-.names N_203_i.BLIF state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n
-11 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
-1 1
-.names AS_030_c_i.BLIF N_64.BLIF N_197_0
-11 1
-.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_198_0
-11 1
-.names RST_i.BLIF SM_AMIGA_3_.AR
-1 1
-.names BG_030_c_i.BLIF N_206_i.BLIF state_machine_un10_bg_030_0_n
-11 1
-.names A_16_.BLIF a_c_16__n
-1 1
-.names AS_030_c_i.BLIF N_117_i.BLIF N_200_0
-11 1
-.names A_17_.BLIF a_c_17__n
-1 1
-.names N_118_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_201_0
-11 1
-.names A_18_.BLIF a_c_18__n
-1 1
-.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF state_machine_ds_000_dma_3_0_n
-11 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
-1 1
-.names A_19_.BLIF a_c_19__n
-1 1
-.names N_172_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF state_machine_size_dma_4_0_1__n
-11 1
-.names A_20_.BLIF a_c_20__n
-1 1
-.names N_122_i.BLIF N_123_i.BLIF SM_AMIGA_6_.D
-11 1
-.names RST_i.BLIF SM_AMIGA_2_.AR
-1 1
-.names A_21_.BLIF a_c_21__n
-1 1
-.names N_76.BLIF cpu_est_i_0__n.BLIF N_148
-11 1
-.names A_22_.BLIF a_c_22__n
-1 1
-.names N_76_i.BLIF cpu_est_0_.BLIF N_149
-11 1
-.names A_23_.BLIF a_c_23__n
-1 1
-.names LDS_000_c.BLIF UDS_000_c.BLIF N_150
-11 1
-.names A_24_.BLIF a_c_24__n
-1 1
-.names inst_VMA_INTreg.BLIF VMA_INT_i
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
-1 1
-.names A_25_.BLIF a_c_25__n
-1 1
-.names inst_VPA_D.BLIF VPA_D_i
-0 1
-.names A_26_.BLIF a_c_26__n
-1 1
-.names inst_DTACK_D0.BLIF DTACK_D0_i
-0 1
-.names RST_i.BLIF SM_AMIGA_1_.AR
-1 1
-.names A_27_.BLIF a_c_27__n
-1 1
-.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_153
-11 1
-.names A_28_.BLIF a_c_28__n
-1 1
-.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF N_164
-11 1
-.names A_29_.BLIF a_c_29__n
-1 1
-.names cpu_est_0_.BLIF cpu_est_i_0__n
-0 1
-.names A_30_.BLIF a_c_30__n
-1 1
-.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167
-11 1
-.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C
-1 1
-.names A_31_.BLIF a_c_31__n
-1 1
-.names N_167.BLIF cpu_est_i_3__n.BLIF N_168
-11 1
-.names cpu_est_1_.BLIF cpu_est_i_1__n
-0 1
-.names RST_i.BLIF inst_DSACK1_INT.AP
-1 1
-.names nEXP_SPACE.BLIF nEXP_SPACE_c
-1 1
-.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_169
-11 1
-.names inst_CLK_000_D3.BLIF CLK_000_D4_i.BLIF N_170
-11 1
-.names BG_030.BLIF BG_030_c
-1 1
-.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_171
-11 1
-.names BG_000DFFSHreg.BLIF BG_000
-1 1
-.names cpu_est_2_.BLIF cpu_est_i_2__n
-0 1
-.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
-1 1
-.names inst_BGACK_030_INTreg.BLIF BGACK_030
-1 1
-.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_134
-11 1
-.names BGACK_000.BLIF BGACK_000_c
-1 1
-.names N_82.BLIF cpu_est_2_.BLIF N_135
-11 1
-.names RST_i.BLIF inst_VMA_INTreg.AP
-1 1
-.names CLK_030.BLIF CLK_030_c
-1 1
-.names RW_c.BLIF RW_i
-0 1
-.names CLK_000.BLIF CLK_000_c
-1 1
-.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_136
-11 1
-.names CLK_OSZI.BLIF CLK_OSZI_c
-1 1
-.names inst_CLK_030_H.BLIF CLK_030_H_i
-0 1
-.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
-1 1
-.names CLK_030_H_i.BLIF N_202.BLIF N_138
-11 1
-.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
-1 1
-.names CLK_OUT_INTreg.BLIF CLK_EXP
-1 1
-.names AS_030_c.BLIF N_78.BLIF N_140
-11 1
-.names inst_FPU_CS_INTreg.BLIF FPU_CS
-1 1
-.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_141
-11 1
-.names RST_i.BLIF inst_BGACK_030_INTreg.AP
-1 1
-.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
-1 1
-.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_142
-11 1
-.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
-1 1
-.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_143
-11 1
-.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
-1 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_144
-11 1
-.names IPL_0_.BLIF ipl_c_0__n
-1 1
-.names CLK_000_D0_i.BLIF N_171.BLIF N_145
-11 1
-.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
-1 1
-.names IPL_1_.BLIF ipl_c_1__n
-1 1
-.names N_164.BLIF SM_AMIGA_0_.BLIF N_146
-11 1
-.names IPL_2_.BLIF ipl_c_2__n
-1 1
-.names inst_AS_000_DMA.BLIF AS_000_DMA_i
-0 1
-.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR
-1 1
-.names size_c_1__n.BLIF size_i_1__n
-0 1
-.names N_172.BLIF N_173.BLIF N_121
-11 1
-.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
-0 1
-.names vcc_n_n.BLIF AVEC
-1 1
-.names N_86.BLIF sm_amiga_i_7__n.BLIF N_122
-11 1
-.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
-1 1
-.names N_72.BLIF SM_AMIGA_7_.BLIF N_123
-11 1
-.names cpu_est_3_reg.BLIF E
-1 1
-.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_124
-11 1
-.names RST_i.BLIF SIZE_DMA_0_.AP
-1 1
-.names VPA.BLIF inst_VPA_D.D
-1 1
-.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_125
-11 1
-.names inst_VMA_INTreg.BLIF VMA
-1 1
-.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
-0 1
-.names RST.BLIF RST_c
-1 1
-.names N_62.BLIF sm_amiga_i_3__n.BLIF N_126
-11 1
-.names RESETDFFRHreg.BLIF RESET
-1 1
-.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_129
-11 1
-.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
-1 1
-.names RW.BLIF RW_c
-1 1
-.names N_77.BLIF SM_AMIGA_1_.BLIF N_130
-11 1
-.names FC_0_.BLIF fc_c_0__n
-1 1
-.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_131
-11 1
-.names RST_i.BLIF inst_UDS_000_INT.AP
-1 1
-.names FC_1_.BLIF fc_c_1__n
-1 1
-.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
-0 1
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE
-1 1
-.names N_77.BLIF sm_amiga_i_0__n.BLIF N_132
-11 1
-.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
-1 1
-.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_133
-11 1
-.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
-1 1
-.names a_c_25__n.BLIF a_i_25__n
-0 1
-.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
-1 1
-.names a_c_26__n.BLIF a_i_26__n
-0 1
-.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n
-11 1
-.names a_c_27__n.BLIF a_i_27__n
-0 1
-.names RST_i.BLIF inst_LDS_000_INT.AP
-1 1
-.names state_machine_a0_dma_2_1_n.BLIF N_173.BLIF inst_A0_DMA.D
-11 1
-.names a_c_28__n.BLIF a_i_28__n
-0 1
-.names DS_030_i.BLIF N_62_i.BLIF N_116_1
-11 1
-.names a_c_29__n.BLIF a_i_29__n
-0 1
-.names N_116_1.BLIF RW_i.BLIF N_116
-11 1
-.names a_c_30__n.BLIF a_i_30__n
-0 1
-.names DS_030_i.BLIF N_64_i.BLIF N_115_1
-11 1
-.names a_c_31__n.BLIF a_i_31__n
-0 1
-.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C
-1 1
-.names N_115_1.BLIF RW_c.BLIF N_115
-11 1
-.names a_c_16__n.BLIF a_i_16__n
-0 1
-.names cpu_est_2_.BLIF N_164.BLIF state_machine_un13_clk_000_d0_1_n
-11 1
-.names a_c_18__n.BLIF a_i_18__n
-0 1
-.names RST_i.BLIF inst_FPU_CS_INTreg.AP
-1 1
-.names state_machine_un13_clk_000_d0_1_n.BLIF N_168.BLIF state_machine_un13_clk_000_d0_n
-11 1
-.names a_c_19__n.BLIF a_i_19__n
-0 1
-.names CLK_000_D0_i.BLIF N_169.BLIF N_203_1
-11 1
-.names N_203_1.BLIF VPA_D_i.BLIF N_203
-11 1
-.names N_170.BLIF SM_AMIGA_1_.BLIF N_205
-11 1
-.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF state_machine_uds_000_int_7_0_n
-11 1
-.names DS_030_c.BLIF DS_030_i
-0 1
-.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
-1 1
-.names N_116_i.BLIF AS_030_c_i.BLIF N_199_0_1
-11 1
-.names CLK_030_c.BLIF N_69_i.BLIF N_117
-11 1
-.names N_199_0_1.BLIF N_115_i.BLIF N_199_0
-11 1
-.names A0_c.BLIF A0_i
-0 1
-.names RST_i.BLIF BG_000DFFSHreg.AP
-1 1
-.names N_82_i.BLIF VMA_INT_i.BLIF N_152_1
-11 1
-.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
-0 1
-.names N_152_1.BLIF VPA_D_i.BLIF N_152
-11 1
-.names RST_c.BLIF RST_i
-0 1
-.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_147_1
-11 1
-.names a_c_24__n.BLIF a_i_24__n
-0 1
-.names N_147_1.BLIF nEXP_SPACE_i.BLIF N_147
-11 1
-.names N_121.BLIF SIZE_DMA_0_.D
-0 1
-.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
-1 1
-.names N_74_i.BLIF inst_BGACK_030_INT_D.BLIF N_139_1
-11 1
-.names N_205.BLIF N_205_i
-0 1
-.names N_139_1.BLIF CLK_000_D4_i.BLIF N_139
-11 1
-.names N_65.BLIF dsack1_int_0_un3_n
-0 1
-.names RST_i.BLIF inst_DS_000_DMA.AP
-1 1
-.names N_173.BLIF RW_c.BLIF N_137_1
-11 1
-.names N_205_i.BLIF N_65.BLIF dsack1_int_0_un1_n
-11 1
-.names N_137_1.BLIF nEXP_SPACE_i.BLIF N_137
-11 1
-.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
-11 1
-.names N_61.BLIF CLK_000_D0_i.BLIF N_127_1
-11 1
-.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
-1- 1
--1 1
-.names N_127_1.BLIF inst_CLK_000_D1.BLIF N_127
-11 1
-.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
-1 1
-.names A0_i.BLIF size_c_0__n.BLIF N_120_1
-11 1
-.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n
-11 1
-.names N_120_1.BLIF size_i_1__n.BLIF N_120
-11 1
-.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
-11 1
-.names RST_i.BLIF inst_AS_000_DMA.AP
-1 1
-.names N_118_3.BLIF nEXP_SPACE_c.BLIF N_118
-11 1
-.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
-1- 1
--1 1
-.names AS_030_c.BLIF CLK_000_c.BLIF N_206_1
-11 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
-.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_206_2
-11 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
11 1
-.names N_206_1.BLIF N_206_2.BLIF N_206
-11 1
-.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
-11 1
-.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
+.names RST_i.BLIF SIZE_DMA_1_.AP
1 1
-.names N_146_i.BLIF N_123_i.BLIF sm_amiga_ns_0_1_0__n
+.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
11 1
.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D
1- 1
-1 1
-.names sm_amiga_ns_0_1_0__n.BLIF N_145_i.BLIF sm_amiga_ns_0_0__n
-11 1
-.names N_76.BLIF ipl_030_0_0__un3_n
+.names N_143_2.BLIF N_143_2_i
0 1
-.names RST_i.BLIF inst_AS_000_INT.AP
+.names N_194.BLIF as_000_dma_0_un3_n
+0 1
+.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
1 1
-.names N_144_i.BLIF N_142_i.BLIF cpu_est_ns_0_1_2__n
+.names N_143_2_i.BLIF N_194.BLIF as_000_dma_0_un1_n
11 1
-.names IPL_030DFFSH_0_reg.BLIF N_76.BLIF ipl_030_0_0__un1_n
+.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
11 1
-.names cpu_est_ns_0_1_2__n.BLIF N_143_i.BLIF cpu_est_ns_0_2__n
-11 1
-.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
-11 1
-.names N_141_i.BLIF RW_i.BLIF N_53_0_1
-11 1
-.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
+.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
+1 1
+.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D
1- 1
-1 1
-.names N_53_0_1.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_53_0
-11 1
-.names N_76.BLIF ipl_030_0_1__un3_n
+.names N_55.BLIF ds_000_dma_0_un3_n
0 1
-.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFSHreg.C
+.names state_machine_ds_000_dma_3_n.BLIF N_55.BLIF ds_000_dma_0_un1_n
+11 1
+.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+11 1
+.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
1 1
-.names N_78.BLIF N_132_i.BLIF N_43_i_1
-11 1
-.names IPL_030DFFSH_1_reg.BLIF N_76.BLIF ipl_030_0_1__un1_n
-11 1
-.names N_43_i_1.BLIF N_164_i.BLIF SM_AMIGA_0_.D
-11 1
-.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
-11 1
-.names RST_i.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP
-1 1
-.names N_120_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n
-11 1
-.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
+.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D
1- 1
-1 1
-.names state_machine_lds_000_int_7_0_1_n.BLIF N_66_i.BLIF state_machine_lds_000_int_7_0_n
-11 1
-.names N_76.BLIF ipl_030_0_2__un3_n
-0 1
-.names N_66_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n
-11 1
-.names IPL_030DFFSH_2_reg.BLIF N_76.BLIF ipl_030_0_2__un1_n
-11 1
-.names state_machine_un8_bgack_030_int_i_0_0_1_n.BLIF BGACK_030_INT_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n
-11 1
-.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
-11 1
-.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
-1 1
-.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF N_72_0_1
-11 1
-.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
-1- 1
--1 1
-.names N_72_0_1.BLIF CLK_000_D2_i.BLIF N_72_0
-11 1
-.names N_76.BLIF cpu_estse_0_un3_n
-0 1
-.names RST_i.BLIF inst_AS_030_000_SYNC.AP
-1 1
-.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_51_0_1
-11 1
-.names cpu_est_1_.BLIF N_76.BLIF cpu_estse_0_un1_n
-11 1
-.names N_74.BLIF N_140_i.BLIF N_51_0_2
-11 1
-.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
-11 1
-.names N_51_0_1.BLIF N_51_0_2.BLIF N_51_0
-11 1
-.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
-1- 1
--1 1
-.names N_133_i.BLIF N_134_i.BLIF cpu_est_ns_0_1_1__n
-11 1
-.names N_76.BLIF cpu_estse_1_un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
-1 1
-.names N_167_i.BLIF N_169_i.BLIF cpu_est_ns_0_2_1__n
-11 1
-.names cpu_est_2_.BLIF N_76.BLIF cpu_estse_1_un1_n
-11 1
-.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
-11 1
-.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
-11 1
-.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_128_1
-11 1
-.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D
-1- 1
--1 1
-.names N_61.BLIF SM_AMIGA_3_.BLIF N_128_2
-11 1
-.names N_76.BLIF cpu_estse_2_un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_A0_DMA.C
-1 1
-.names N_128_1.BLIF N_128_2.BLIF N_128
-11 1
-.names cpu_est_3_reg.BLIF N_76.BLIF cpu_estse_2_un1_n
-11 1
-.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_118_1
-11 1
-.names N_151_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
-11 1
-.names RST_i.BLIF inst_A0_DMA.AP
-1 1
-.names N_69.BLIF SM_AMIGA_7_.BLIF N_118_2
-11 1
-.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
-1- 1
--1 1
-.names N_118_1.BLIF N_118_2.BLIF N_118_3
-11 1
-.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
-0 1
-.names a_i_28__n.BLIF a_i_29__n.BLIF N_225_3
-11 1
-.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF clk_un3_clk_out_pre_50_n
-11 1
-.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
-1 1
-.names a_i_30__n.BLIF a_i_31__n.BLIF N_225_4
-11 1
-.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
-0 1
-.names N_225_1.BLIF N_225_2.BLIF N_225_5
-11 1
-.names N_51.BLIF amiga_bus_enable_0_un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C
-1 1
-.names N_225_3.BLIF N_225_4.BLIF N_225_6
-11 1
-.names state_machine_amiga_bus_enable_4_iv_i_n.BLIF N_51.BLIF amiga_bus_enable_0_un1_n
-11 1
-.names N_225_5.BLIF N_225_6.BLIF N_225
-11 1
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n
-11 1
-.names RST_i.BLIF inst_CLK_000_D4.AP
-1 1
-.names a_c_20__n.BLIF a_c_21__n.BLIF N_228_1
-11 1
-.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFSHreg.D
-1- 1
--1 1
-.names a_c_22__n.BLIF a_c_23__n.BLIF N_228_2
-11 1
-.names N_201.BLIF as_030_000_sync_0_un3_n
-0 1
-.names N_228_1.BLIF N_228_2.BLIF N_228
-11 1
-.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_201.BLIF as_030_000_sync_0_un1_n
-11 1
-.names a_c_17__n.BLIF BGACK_000_c.BLIF N_69_i_1
-11 1
-.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n
-11 1
-.names CLK_OSZI_c.BLIF inst_DTACK_D0.C
-1 1
-.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_69_i_2
-11 1
-.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D
-1- 1
--1 1
-.names a_i_19__n.BLIF a_i_16__n.BLIF N_69_i_3
-11 1
.names RST_c.BLIF clk_030_h_0_un3_n
0 1
-.names RST_i.BLIF inst_DTACK_D0.AP
+.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
1 1
-.names N_69_i_1.BLIF N_69_i_2.BLIF N_69_i_4
-11 1
-.names N_48_i.BLIF RST_c.BLIF clk_030_h_0_un1_n
-11 1
-.names N_69_i_3.BLIF a_i_18__n.BLIF N_69_i_5
+.names N_52_i.BLIF RST_c.BLIF clk_030_h_0_un1_n
11 1
.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
11 1
-.names N_69_i_4.BLIF N_69_i_5.BLIF N_69_i
-11 1
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
-.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
+.names N_197.BLIF rw_000_int_0_un3_n
+0 1
+.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
1 1
-.names N_150_i.BLIF AS_000_i.BLIF state_machine_un8_bgack_030_int_i_0_0_1_n
+.names state_machine_rw_000_int_7_iv_i_n.BLIF N_197.BLIF rw_000_int_0_un1_n
11 1
-.names N_199.BLIF uds_000_int_0_un3_n
-0 1
-.names N_200_0.BLIF N_200
-0 1
-.names state_machine_uds_000_int_7_n.BLIF N_199.BLIF uds_000_int_0_un1_n
+.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
11 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
+.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
1 1
-.names N_115.BLIF N_115_i
+.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
+1- 1
+-1 1
+.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
0 1
+.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+0 1
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_135
+11 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
+1 1
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_134
+11 1
+.names RST_i.BLIF SM_AMIGA_7_.AP
+1 1
+.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
+0 1
+.names N_66.BLIF sm_amiga_i_3__n.BLIF N_131
+11 1
+.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
+1 1
+.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_130
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_128
+11 1
+.names RST_i.BLIF SM_AMIGA_6_.AR
+1 1
+.names inst_CLK_000_D0.BLIF N_201.BLIF SM_AMIGA_1_.D
+11 1
+.names N_166.BLIF N_171.BLIF N_125
+11 1
+.names inst_CLK_000_D0.BLIF N_199.BLIF N_119
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114
+11 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
+1 1
+.names BGACK_000_c.BLIF N_77.BLIF state_machine_un6_bgack_000_0_n
+11 1
+.names UDS_000_c.BLIF UDS_000_i
+0 1
+.names RST_i.BLIF SM_AMIGA_5_.AR
+1 1
+.names LDS_000_c.BLIF LDS_000_i
+0 1
+.names LDS_000_i.BLIF UDS_000_i.BLIF N_171
+11 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names AS_000_c.BLIF AS_000_i
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
+1 1
+.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_166
+11 1
+.names inst_DTACK_D0.BLIF DTACK_D0_i
+0 1
+.names RST_i.BLIF SM_AMIGA_4_.AR
+1 1
+.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_161
+11 1
+.names CLK_030_c.BLIF CLK_030_i
+0 1
+.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_144
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_H_i
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
+1 1
+.names A_16_.BLIF a_c_16__n
+1 1
+.names CLK_030_H_i.BLIF N_203.BLIF N_141
+11 1
+.names A_17_.BLIF a_c_17__n
+1 1
+.names RW_c.BLIF RW_i
+0 1
+.names RST_i.BLIF SM_AMIGA_3_.AR
+1 1
+.names A_18_.BLIF a_c_18__n
+1 1
+.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_139
+11 1
+.names A_19_.BLIF a_c_19__n
+1 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_77_i
+11 1
+.names A_20_.BLIF a_c_20__n
+1 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_66_i
+11 1
+.names A_21_.BLIF a_c_21__n
+1 1
+.names N_155_i.BLIF N_161_i.BLIF N_63_0
+11 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
+1 1
+.names A_22_.BLIF a_c_22__n
+1 1
+.names LDS_000_c.BLIF UDS_000_c.BLIF N_62_0
+11 1
+.names A_23_.BLIF a_c_23__n
+1 1
+.names N_142_i.BLIF N_143_i.BLIF state_machine_rw_000_int_7_iv_i_n
+11 1
+.names RST_i.BLIF SM_AMIGA_2_.AR
+1 1
+.names A_24_.BLIF a_c_24__n
+1 1
+.names N_141_i.BLIF N_143_2.BLIF N_52_i
+11 1
+.names A_25_.BLIF a_c_25__n
+1 1
+.names N_139_i.BLIF N_140_i.BLIF AMIGA_BUS_DATA_DIR_c_0
+11 1
+.names A_26_.BLIF a_c_26__n
+1 1
+.names CLK_000_D0_i.BLIF N_135_i.BLIF SM_AMIGA_0_.D
+11 1
+.names A_27_.BLIF a_c_27__n
+1 1
+.names N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n
+11 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
+1 1
+.names A_28_.BLIF a_c_28__n
+1 1
+.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_3_.D
+11 1
+.names A_29_.BLIF a_c_29__n
+1 1
+.names CLK_000_D0_i.BLIF N_130_i.BLIF SM_AMIGA_4_.D
+11 1
+.names RST_i.BLIF SM_AMIGA_1_.AR
+1 1
+.names A_30_.BLIF a_c_30__n
+1 1
+.names N_143_2.BLIF N_171_i.BLIF state_machine_size_dma_4_0_1__n
+11 1
+.names A_31_.BLIF a_c_31__n
+1 1
+.names AS_000_DMA_i.BLIF N_143_2.BLIF state_machine_ds_000_dma_3_0_n
+11 1
+.names N_119_i.BLIF N_120_i.BLIF N_197_0
+11 1
+.names nEXP_SPACE.BLIF nEXP_SPACE_c
+1 1
+.names CLK_030_c.BLIF N_143_2.BLIF N_194_0
+11 1
+.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C
+1 1
+.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_71_i
+11 1
+.names BG_030.BLIF BG_030_c
+1 1
+.names AS_030_c_i.BLIF N_114_i.BLIF N_75_i
+11 1
+.names RST_i.BLIF inst_DSACK1_INT.AP
+1 1
+.names BG_000DFFSHreg.BLIF BG_000
+1 1
+.names cpu_est_3_reg.BLIF cpu_est_i_3__n
+0 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030
+1 1
+.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_90_i
+11 1
+.names BGACK_000.BLIF BGACK_000_c
+1 1
+.names N_75_i.BLIF N_168_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0
+11 1
+.names CLK_030.BLIF CLK_030_c
+1 1
+.names N_71.BLIF N_169_i.BLIF N_198_0
+11 1
+.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
+1 1
+.names CLK_000.BLIF CLK_000_c
+1 1
+.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_200_0
+11 1
+.names CLK_OSZI.BLIF CLK_OSZI_c
+1 1
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names RST_i.BLIF inst_VMA_INTreg.AP
+1 1
+.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
+1 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_202_0
+11 1
+.names CLK_OUT_INTreg.BLIF CLK_EXP
+1 1
+.names N_62.BLIF N_166.BLIF N_143_2
+11 1
+.names inst_FPU_CS_INTreg.BLIF FPU_CS
+1 1
+.names RW_000_c.BLIF RW_000_i
+0 1
+.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
+1 1
+.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_203_0
+11 1
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
+1 1
+.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
+1 1
+.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_201_0
+11 1
+.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
+1 1
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_199_0
+11 1
+.names RST_i.BLIF inst_BGACK_030_INTreg.AP
+1 1
+.names IPL_0_.BLIF ipl_c_0__n
+1 1
+.names CLK_030_i.BLIF N_143_2.BLIF N_79_0
+11 1
+.names IPL_1_.BLIF ipl_c_1__n
+1 1
+.names N_167.BLIF cpu_est_i_3__n.BLIF N_172
+11 1
+.names IPL_2_.BLIF ipl_c_2__n
+1 1
+.names N_204_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n
+11 1
+.names AS_030_c_i.BLIF N_67.BLIF N_193_0
+11 1
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
+1 1
+.names BG_030_c_i.BLIF N_115_i.BLIF state_machine_un10_bg_030_0_n
+11 1
+.names vcc_n_n.BLIF AVEC
+1 1
+.names inst_BGACK_030_INTreg.BLIF N_116_i.BLIF N_195_i
+11 1
+.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR
+1 1
+.names inst_avec_expreg.BLIF AVEC_EXP
+1 1
+.names AS_030_c_i.BLIF N_121_i.BLIF N_28_0
+11 1
+.names cpu_est_3_reg.BLIF E
+1 1
+.names N_122_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_30_0
+11 1
+.names VPA.BLIF inst_VPA_D.D
+1 1
+.names N_128_i.BLIF N_198_0.BLIF sm_amiga_ns_0_0__n
+11 1
+.names inst_VMA_INTreg.BLIF VMA
+1 1
+.names N_129_i.BLIF N_198_0.BLIF SM_AMIGA_6_.D
+11 1
+.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
+1 1
+.names RST.BLIF RST_c
+1 1
+.names N_138_i.BLIF N_172_i.BLIF N_149_i
+11 1
+.names RESETDFFRHreg.BLIF RESET
+1 1
+.names N_150_i.BLIF N_151_i.BLIF cpu_est_0_.D
+11 1
+.names RST_i.BLIF SIZE_DMA_0_.AP
+1 1
+.names inst_CLK_000_D2.BLIF CLK_000_D2_i
+0 1
+.names FC_0_.BLIF fc_c_0__n
+1 1
+.names inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF N_67_i
+11 1
+.names FC_1_.BLIF fc_c_1__n
+1 1
+.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n
+0 1
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE
+1 1
+.names N_67.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n
+11 1
+.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
+1 1
+.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
+1 1
+.names N_66.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF state_machine_uds_000_int_7_0_m3_un0_n
+11 1
+.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
+1 1
+.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_70
+1- 1
+-1 1
+.names RST_i.BLIF inst_LDS_000_INT.AP
+1 1
+.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+0 1
+.names CLK_030_i.BLIF N_62.BLIF N_120_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_145
+11 1
+.names N_120_1.BLIF N_166.BLIF N_120
+11 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_146
+11 1
+.names DS_030_i.BLIF N_66_i.BLIF N_118_1
+11 1
+.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_147
+11 1
+.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C
+1 1
+.names N_118_1.BLIF RW_i.BLIF N_118
+11 1
+.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+0 1
+.names DS_030_i.BLIF N_67_i.BLIF N_117_1
+11 1
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
+0 1
+.names RST_i.BLIF inst_FPU_CS_INTreg.AP
+1 1
+.names N_117_1.BLIF RW_c.BLIF N_117
+11 1
+.names N_77.BLIF cpu_est_i_0__n.BLIF N_150
+11 1
+.names N_71.BLIF inst_BGACK_030_INT_D.BLIF N_116_1
+11 1
+.names N_77_i.BLIF cpu_est_0_.BLIF N_151
+11 1
+.names N_116_1.BLIF N_69_i.BLIF N_116
+11 1
+.names inst_VMA_INTreg.BLIF VMA_INT_i
+0 1
+.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
+11 1
+.names inst_VPA_D.BLIF VPA_D_i
+0 1
+.names CLK_OSZI_c.BLIF inst_avec_expreg.C
+1 1
+.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
+.names CLK_000_D0_i.BLIF N_170.BLIF N_204_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167
+11 1
+.names RST_i.BLIF inst_avec_expreg.AP
+1 1
+.names N_204_1.BLIF VPA_D_i.BLIF N_204
+11 1
+.names N_69_i.BLIF N_71_i.BLIF N_168
+11 1
+.names N_196_0_1.BLIF N_117_i.BLIF N_196_0
+11 1
+.names N_69.BLIF SM_AMIGA_7_.BLIF N_169
+11 1
+.names N_90_i.BLIF VMA_INT_i.BLIF N_155_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names N_155_1.BLIF VPA_D_i.BLIF N_155
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_170
+11 1
+.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
+1 1
+.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_148_1
+11 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
+.names N_148_1.BLIF nEXP_SPACE_i.BLIF N_148
+11 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names RST_i.BLIF BG_000DFFSHreg.AP
+1 1
+.names N_79.BLIF RW_i.BLIF N_142_1
+11 1
+.names a_c_31__n.BLIF a_i_31__n
+0 1
+.names N_142_1.BLIF SM_AMIGA_6_.BLIF N_142
+11 1
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names N_166.BLIF RW_c.BLIF N_140_1
+11 1
+.names N_140_1.BLIF nEXP_SPACE_i.BLIF N_140
+11 1
+.names DS_030_c.BLIF DS_030_i
+0 1
+.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
+1 1
+.names N_63.BLIF CLK_000_D0_i.BLIF N_132_1
+11 1
+.names CLK_030_c.BLIF N_76_i.BLIF N_121
+11 1
+.names N_132_1.BLIF inst_CLK_000_D1.BLIF N_132
+11 1
+.names A0_c.BLIF A0_i
+0 1
+.names RST_i.BLIF inst_DS_000_DMA.AP
+1 1
+.names A0_i.BLIF size_c_0__n.BLIF N_124_1
+11 1
+.names size_c_1__n.BLIF size_i_1__n
+0 1
+.names N_124_1.BLIF size_i_1__n.BLIF N_124
+11 1
+.names inst_CLK_000_D0.BLIF N_200.BLIF SM_AMIGA_5_.D
+11 1
+.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n
+11 1
+.names N_202.BLIF sm_amiga_i_7__n.BLIF N_129
+11 1
+.names state_machine_a0_dma_2_1_n.BLIF N_166.BLIF inst_A0_DMA.D
+11 1
+.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_136
+11 1
+.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
+1 1
+.names state_machine_un10_clk_000_d0_1_n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n
+11 1
+.names cpu_est_2_.BLIF cpu_est_i_2__n
+0 1
+.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_133_1
+11 1
+.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_137
+11 1
+.names RST_i.BLIF inst_AS_000_DMA.AP
+1 1
+.names N_63.BLIF SM_AMIGA_3_.BLIF N_133_2
+11 1
+.names N_90.BLIF cpu_est_2_.BLIF N_138
+11 1
+.names N_133_1.BLIF N_133_2.BLIF N_133
+11 1
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
+0 1
+.names CLK_030_i.BLIF N_143_2.BLIF N_143_1
+11 1
+.names RST_c.BLIF RST_i
+0 1
+.names N_143_1.BLIF RW_000_i.BLIF N_143
+11 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
+.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
+1 1
+.names N_147_i.BLIF N_145_i.BLIF cpu_est_ns_0_1_2__n
+11 1
+.names a_c_25__n.BLIF a_i_25__n
+0 1
+.names cpu_est_ns_0_1_2__n.BLIF N_146_i.BLIF cpu_est_ns_0_2__n
+11 1
+.names a_c_26__n.BLIF a_i_26__n
+0 1
+.names RST_i.BLIF inst_AS_000_INT.AP
+1 1
+.names N_143_2.BLIF N_144_i.BLIF N_55_0_1
+11 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names N_55_0_1.BLIF RW_000_i.BLIF N_55_0
+11 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
+.names N_124_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n
+11 1
+.names N_125.BLIF SIZE_DMA_0_.D
+0 1
+.names state_machine_lds_000_int_7_0_1_n.BLIF N_70_i.BLIF state_machine_lds_000_int_7_0_n
+11 1
+.names N_77.BLIF ipl_030_0_0__un3_n
+0 1
+.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
+1 1
+.names N_70_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n
+11 1
+.names IPL_030DFFSH_0_reg.BLIF N_77.BLIF ipl_030_0_0__un1_n
+11 1
+.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF state_machine_uds_000_int_7_0_n
+11 1
+.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
+11 1
+.names RST_i.BLIF inst_RW_000_INT.AP
+1 1
+.names N_118_i.BLIF AS_030_c_i.BLIF N_196_0_1
+11 1
+.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
+1- 1
+-1 1
+.names N_230_1.BLIF N_230_2.BLIF N_230_5
+11 1
+.names N_77.BLIF ipl_030_0_1__un3_n
+0 1
+.names N_230_3.BLIF N_230_4.BLIF N_230_6
+11 1
+.names IPL_030DFFSH_1_reg.BLIF N_77.BLIF ipl_030_0_1__un1_n
+11 1
+.names N_230_5.BLIF N_230_6.BLIF N_230
+11 1
+.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
+1 1
+.names N_136_i.BLIF N_137_i.BLIF cpu_est_ns_0_1_1__n
+11 1
+.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
+1- 1
+-1 1
+.names N_167_i.BLIF N_170_i.BLIF cpu_est_ns_0_2_1__n
+11 1
+.names N_77.BLIF ipl_030_0_2__un3_n
+0 1
+.names RST_i.BLIF inst_AS_030_000_SYNC.AP
+1 1
+.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
+11 1
+.names IPL_030DFFSH_2_reg.BLIF N_77.BLIF ipl_030_0_2__un1_n
+11 1
+.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_122_1
+11 1
+.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names N_76.BLIF SM_AMIGA_7_.BLIF N_122_2
+11 1
+.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
+1- 1
+-1 1
+.names N_122_1.BLIF N_122_2.BLIF N_122_3
+11 1
+.names N_77.BLIF cpu_estse_0_un3_n
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
+1 1
+.names N_122_3.BLIF nEXP_SPACE_c.BLIF N_122
+11 1
+.names cpu_est_1_.BLIF N_77.BLIF cpu_estse_0_un1_n
+11 1
+.names AS_030_c.BLIF CLK_000_c.BLIF N_115_1
+11 1
+.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
+11 1
+.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_115_2
+11 1
+.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
+1- 1
+-1 1
+.names N_115_1.BLIF N_115_2.BLIF N_115
+11 1
+.names N_77.BLIF cpu_estse_1_un3_n
+0 1
+.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
+1 1
+.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF state_machine_un10_clk_000_d0_1_n
+11 1
+.names cpu_est_2_.BLIF N_77.BLIF cpu_estse_1_un1_n
+11 1
+.names N_172.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
+11 1
+.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
+11 1
+.names RST_i.BLIF inst_UDS_000_INT.AP
+1 1
+.names CLK_000_D2_i.BLIF AS_030_000_SYNC_i.BLIF N_69_i_1
+11 1
+.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D
+1- 1
+-1 1
+.names N_69_i_1.BLIF inst_CLK_000_D3.BLIF N_69_i
+11 1
+.names N_77.BLIF cpu_estse_2_un3_n
+0 1
+.names BGACK_000_c.BLIF a_i_19__n.BLIF N_76_i_1
+11 1
+.names cpu_est_3_reg.BLIF N_77.BLIF cpu_estse_2_un1_n
+11 1
+.names a_i_16__n.BLIF a_i_18__n.BLIF N_76_i_2
+11 1
+.names N_149_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
+11 1
+.names CLK_OSZI_c.BLIF inst_A0_DMA.C
+1 1
+.names a_c_17__n.BLIF fc_c_0__n.BLIF N_76_i_3
+11 1
+.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
+1- 1
+-1 1
+.names N_76_i_1.BLIF N_76_i_2.BLIF N_76_i_4
+11 1
+.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
+0 1
+.names RST_i.BLIF inst_A0_DMA.AP
+1 1
+.names N_76_i_3.BLIF fc_c_1__n.BLIF N_76_i_5
+11 1
+.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF state_machine_un3_clk_out_pre_50_n
+11 1
+.names N_76_i_4.BLIF N_76_i_5.BLIF N_76_i
+11 1
+.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
+0 1
+.names a_c_20__n.BLIF a_c_21__n.BLIF N_220_1
+11 1
+.names N_30.BLIF as_030_000_sync_0_un3_n
+0 1
+.names a_c_22__n.BLIF a_c_23__n.BLIF N_220_2
+11 1
+.names un1_DSACK1_INT_0_sqmuxa_3.BLIF N_30.BLIF as_030_000_sync_0_un1_n
+11 1
+.names CLK_OSZI_c.BLIF inst_DTACK_D0.C
+1 1
+.names N_220_1.BLIF N_220_2.BLIF N_220
+11 1
+.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n
+11 1
+.names a_i_24__n.BLIF a_i_25__n.BLIF N_230_1
+11 1
+.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D
+1- 1
+-1 1
+.names RST_i.BLIF inst_DTACK_D0.AP
+1 1
+.names a_i_26__n.BLIF a_i_27__n.BLIF N_230_2
+11 1
+.names N_196.BLIF uds_000_int_0_un3_n
+0 1
+.names a_i_28__n.BLIF a_i_29__n.BLIF N_230_3
+11 1
+.names state_machine_uds_000_int_7_n.BLIF N_196.BLIF uds_000_int_0_un1_n
+11 1
+.names a_i_30__n.BLIF a_i_31__n.BLIF N_230_4
+11 1
.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
11 1
-.names N_116.BLIF N_116_i
+.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
+1 1
+.names N_122.BLIF N_122_i
0 1
.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
1- 1
-1 1
-.names RST_i.BLIF inst_CLK_000_D3.AP
+.names N_30_0.BLIF N_30
+0 1
+.names N_196.BLIF lds_000_int_0_un3_n
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C
1 1
-.names N_199_0.BLIF N_199
+.names N_121.BLIF N_121_i
0 1
-.names N_199.BLIF lds_000_int_0_un3_n
-0 1
-.names BG_030_c.BLIF BG_030_c_i
-0 1
-.names state_machine_lds_000_int_7_n.BLIF N_199.BLIF lds_000_int_0_un1_n
+.names state_machine_lds_000_int_7_n.BLIF N_196.BLIF lds_000_int_0_un1_n
11 1
-.names N_206.BLIF N_206_i
+.names N_28_0.BLIF N_28
0 1
.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
11 1
-.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
+.names RST_i.BLIF inst_CLK_000_D2.AP
1 1
-.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
+.names N_117.BLIF N_117_i
0 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
-.names N_198_0.BLIF N_198
+.names N_118.BLIF N_118_i
0 1
-.names N_200.BLIF fpu_cs_int_0_un3_n
+.names N_28.BLIF fpu_cs_int_0_un3_n
0 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C
-1 1
-.names N_197_0.BLIF N_197
+.names N_196_0.BLIF N_196
0 1
-.names AS_030_c.BLIF N_200.BLIF fpu_cs_int_0_un1_n
+.names AS_030_c.BLIF N_28.BLIF fpu_cs_int_0_un1_n
11 1
-.names N_203.BLIF N_203_i
+.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D
+1 1
+.names N_116.BLIF N_116_i
0 1
.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
-.names RST_i.BLIF inst_CLK_000_D2.AP
-1 1
-.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n
+.names BG_030_c.BLIF BG_030_c_i
0 1
.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D
1- 1
-1 1
-.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n
-0 1
-.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
-0 1
-.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
-0 1
-.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
-11 1
-.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D
-1 1
-.names a_i_24__n.BLIF a_i_25__n.BLIF N_225_1
-11 1
-.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
-11 1
-.names a_i_26__n.BLIF a_i_27__n.BLIF N_225_2
-11 1
-.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
-1- 1
--1 1
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
-.names N_126.BLIF N_126_i
+.names N_115.BLIF N_115_i
0 1
-.names N_53.BLIF ds_000_dma_0_un3_n
+.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n
0 1
-.names N_127.BLIF N_127_i
+.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
-.names state_machine_ds_000_dma_3_n.BLIF N_53.BLIF ds_000_dma_0_un1_n
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un1_n
11 1
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
-.names N_125.BLIF N_125_i
+.names N_193_0.BLIF N_193
0 1
-.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+.names N_195_i.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n
11 1
-.names N_124.BLIF N_124_i
+.names N_204.BLIF N_204_i
0 1
-.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D
+.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D
1- 1
-1 1
-.names N_122.BLIF N_122_i
+.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
-.names N_198.BLIF as_000_dma_0_un3_n
+.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
-.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
+.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
-.names N_172.BLIF N_172_i
+.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
-.names state_machine_un8_bgack_030_int_i_0_n.BLIF N_198.BLIF as_000_dma_0_un1_n
+.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
-.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
+.names N_145.BLIF N_145_i
0 1
-.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
+.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
+.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
1 1
-.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
+.names N_146.BLIF N_146_i
0 1
-.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D
+.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
-.names N_66.BLIF N_66_i
+.names N_147.BLIF N_147_i
0 1
-.names N_197.BLIF as_000_int_0_un3_n
+.names N_193.BLIF as_000_int_0_un3_n
0 1
-.names RST_i.BLIF inst_CLK_000_D1.AP
+.names RST_i.BLIF inst_CLK_000_D3.AP
1 1
-.names N_120.BLIF N_120_i
+.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
0 1
-.names N_64.BLIF N_197.BLIF as_000_int_0_un1_n
+.names N_67.BLIF N_193.BLIF as_000_int_0_un1_n
11 1
-.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n
+.names N_144.BLIF N_144_i
0 1
.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
-.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n
+.names N_55_0.BLIF N_55
0 1
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
-.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
-1 1
-.names N_118.BLIF N_118_i
-0 1
-.names vcc_n_n
-1
-.names N_201_0.BLIF N_201
-0 1
-.names gnd_n_n
-.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
-1 1
-.names N_117.BLIF N_117_i
-0 1
-.names N_139.BLIF N_139_i
-0 1
-.names RST_i.BLIF inst_BGACK_030_INT_D.AP
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
.names N_138.BLIF N_138_i
0 1
+.names N_114.BLIF N_114_i
+0 1
+.names N_172.BLIF N_172_i
+0 1
+.names N_75.BLIF dsack1_int_0_un3_n
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
+1 1
+.names N_129.BLIF N_129_i
+0 1
+.names N_114_i.BLIF N_75.BLIF dsack1_int_0_un1_n
+11 1
+.names N_128.BLIF N_128_i
+0 1
+.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
+11 1
+.names RST_i.BLIF inst_CLK_000_D1.AP
+1 1
+.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
+0 1
+.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
+1- 1
+-1 1
+.names N_70.BLIF N_70_i
+0 1
+.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
+0 1
+.names N_124.BLIF N_124_i
+0 1
+.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
+11 1
+.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
+1 1
+.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n
+0 1
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+11 1
+.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n
+0 1
+.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
+1- 1
+-1 1
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
+1 1
.names N_136.BLIF N_136_i
0 1
+.names vcc_n_n
+1
.names N_137.BLIF N_137_i
0 1
+.names gnd_n_n
+.names RST_i.BLIF inst_BGACK_030_INT_D.AP
+1 1
+.names N_202_0.BLIF N_202
+0 1
+.names N_200_0.BLIF N_200
+0 1
+.names N_169.BLIF N_169_i
+0 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D
1 1
-.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
+.names N_168.BLIF N_168_i
0 1
-.names N_135.BLIF N_135_i
+.names un1_DSACK1_INT_0_sqmuxa_3_0.BLIF un1_DSACK1_INT_0_sqmuxa_3
0 1
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C
1 1
-.names N_168.BLIF N_168_i
-0 1
-.names N_132.BLIF N_132_i
-0 1
-.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR
-1 1
-.names N_164.BLIF N_164_i
-0 1
.end
diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1
index 8a49c92..e3d94f4 100644
--- a/Logic/BUS68030.bl1
+++ b/Logic/BUS68030.bl1
@@ -1,175 +1,176 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 29 22:04:27 2014
+#$ DATE Sun Jun 01 01:03:24 2014
#$ MODULE bus68030
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ \
-# IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 \
-# UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
-# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \
-# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
-# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 405 CLK_030_c CLK_000_c CLK_OSZI_c inst_BGACK_030_INTreg CLK_OUT_INTreg \
-# inst_FPU_CS_INTreg inst_VMA_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_0_reg \
-# inst_BGACK_030_INT_D inst_AS_000_DMA IPL_030DFFSH_1_reg inst_VPA_D \
-# inst_CLK_OUT_PRE_50_D IPL_030DFFSH_2_reg inst_CLK_000_D0 inst_CLK_000_D1 \
-# ipl_c_0__n inst_CLK_000_D2 inst_CLK_000_D4 ipl_c_1__n inst_DTACK_D0 \
-# inst_CLK_OUT_PRE_50 ipl_c_2__n inst_CLK_OUT_PRE_25 vcc_n_n gnd_n_n dsack_c_1__n \
-# state_machine_un13_clk_000_d0_n inst_AS_000_INT SM_AMIGA_1_ SM_AMIGA_0_ \
-# SM_AMIGA_6_ SM_AMIGA_5_ inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \
-# clk_un3_clk_out_pre_50_n RST_c inst_CLK_000_D3 inst_CLK_030_H RESETDFFRHreg \
-# state_machine_un6_bgack_000_n state_machine_un15_clk_000_d0_n RW_c \
-# inst_DS_000_DMA SIZE_DMA_0_ fc_c_0__n SIZE_DMA_1_ inst_A0_DMA fc_c_1__n SM_AMIGA_7_ \
-# un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 AMIGA_BUS_ENABLEDFFSHreg SM_AMIGA_4_ \
-# AMIGA_BUS_DATA_DIR_c state_machine_ds_000_dma_3_n SM_AMIGA_3_ SM_AMIGA_2_ \
-# cpu_est_ns_0_1__n state_machine_un10_bg_030_n N_134_i \
-# state_machine_lds_000_int_7_n N_169_i state_machine_uds_000_int_7_n N_133_i \
-# N_167_i N_51_0 N_140_i N_202_0 N_86_0 N_171_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 \
-# N_82_i sm_amiga_i_1__n N_78_i N_170_i N_77_0 CLK_000_D1_i CLK_OUT_PRE_25_0 N_76_i \
-# N_74_i N_72_0 AS_030_000_SYNC_i CLK_000_D2_i \
-# state_machine_un8_bgack_030_int_i_0_0_n cpu_est_0_ N_69_i cpu_est_1_ AS_030_c_i \
-# cpu_est_2_ N_65_i cpu_est_3_reg N_64_i N_62_i N_152_i N_153_i cpu_est_ns_1__n N_61_0 \
-# cpu_est_ns_2__n N_150_i state_machine_un8_bgack_030_int_i_0_n N_148_i N_197 N_149_i \
-# N_198 N_199 N_123_i N_200 N_145_i N_201 N_146_i sm_amiga_ns_0_0__n N_51 N_142_i N_53 \
-# N_143_i N_61 N_144_i N_62 cpu_est_ns_0_2__n N_64 N_141_i N_65 N_53_0 N_66 N_139_i N_69 \
-# state_machine_amiga_bus_enable_4_iv_i_n N_72 N_138_i N_74 N_48_i N_76 N_136_i N_77 \
-# N_137_i N_78 AMIGA_BUS_DATA_DIR_c_0 N_82 N_135_i N_86 N_168_i N_202 N_151_i N_203 \
-# N_132_i N_205 N_164_i N_206 N_115 N_130_i N_116 N_131_i N_117 N_41_0 N_118 N_128_i N_120 \
-# N_129_i N_121 sm_amiga_ns_0_5__n N_122 N_126_i N_123 N_127_i N_124 N_125 N_125_i N_126 \
-# N_127 N_124_i N_128 N_129 N_122_i N_130 N_131 N_172_i N_132 \
-# state_machine_size_dma_4_0_1__n N_133 state_machine_ds_000_dma_3_0_n N_134 N_66_i \
-# N_135 N_120_i N_136 state_machine_lds_000_int_7_0_n N_137 \
-# state_machine_uds_000_int_7_0_n N_138 N_118_i N_139 N_201_0 N_140 N_117_i N_141 \
-# N_200_0 N_142 N_115_i N_143 N_116_i N_144 N_199_0 N_145 BG_030_c_i N_146 N_206_i N_147 \
-# state_machine_un10_bg_030_0_n N_148 N_198_0 N_149 N_197_0 N_150 N_203_i N_152 \
-# state_machine_un13_clk_000_d0_i_n N_153 state_machine_un15_clk_000_d0_0_n N_164 \
-# state_machine_un6_bgack_000_0_n N_167 N_225_1 N_168 N_225_2 N_169 N_225_3 N_170 \
-# N_225_4 N_171 N_225_5 N_172 N_225_6 N_173 N_228_1 N_225 N_228_2 N_228 N_69_i_1 \
-# CLK_000_D0_i N_69_i_2 BGACK_030_INT_i N_69_i_3 CLK_030_i N_69_i_4 cpu_est_i_3__n \
-# N_69_i_5 sm_amiga_i_6__n state_machine_un8_bgack_030_int_i_0_0_1_n nEXP_SPACE_i \
-# N_72_0_1 CLK_000_D4_i N_51_0_1 sm_amiga_i_5__n N_51_0_2 sm_amiga_i_4__n \
-# cpu_est_ns_0_1_1__n AS_000_i cpu_est_ns_0_2_1__n LDS_000_i N_128_1 UDS_000_i N_128_2 \
-# cpu_est_i_1__n N_118_1 cpu_est_i_0__n N_118_2 DTACK_D0_i N_118_3 VMA_INT_i N_206_1 \
-# VPA_D_i N_206_2 AS_000_DMA_i sm_amiga_ns_0_1_0__n CLK_030_H_i cpu_est_ns_0_1_2__n \
-# RW_i N_53_0_1 cpu_est_i_2__n N_43_i_1 sm_amiga_i_0__n \
-# state_machine_lds_000_int_7_0_1_n sm_amiga_i_3__n \
-# state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_199_0_1 A0_i N_152_1 \
-# size_i_1__n N_147_1 DS_030_i N_139_1 a_i_19__n N_137_1 a_i_16__n N_127_1 a_i_18__n \
-# N_120_1 a_i_30__n state_machine_a0_dma_2_1_n a_i_31__n N_116_1 a_i_28__n N_115_1 \
-# a_i_29__n state_machine_un13_clk_000_d0_1_n a_i_26__n N_203_1 a_i_27__n \
-# state_machine_uds_000_int_7_0_m3_un3_n a_i_24__n \
-# state_machine_uds_000_int_7_0_m3_un1_n a_i_25__n \
-# state_machine_uds_000_int_7_0_m3_un0_n RST_i dsack1_int_0_un3_n \
-# dsack1_int_0_un1_n dsack1_int_0_un0_n N_205_i vma_int_0_un3_n FPU_CS_INT_i \
-# vma_int_0_un1_n CLK_OUT_PRE_50_D_i vma_int_0_un0_n AS_030_c bgack_030_int_0_un3_n \
-# bgack_030_int_0_un1_n AS_000_c bgack_030_int_0_un0_n ipl_030_0_0__un3_n DS_030_c \
+#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ \
+# IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 \
+# IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 \
+# CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET \
+# RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
+# A_28_ A_27_
+#$ NODES 410 BG_030_c BG_000DFFSHreg inst_BGACK_030_INTreg BGACK_000_c \
+# inst_FPU_CS_INTreg inst_avec_expreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC \
+# CLK_000_c inst_BGACK_030_INT_D inst_AS_000_DMA CLK_OSZI_c inst_VPA_D \
+# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 \
+# inst_CLK_000_D2 inst_DTACK_D0 IPL_030DFFSH_0_reg inst_CLK_OUT_PRE_50 \
+# inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ vcc_n_n IPL_030DFFSH_2_reg \
+# gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n inst_AS_000_INT SM_AMIGA_6_ \
+# ipl_c_1__n SM_AMIGA_0_ SM_AMIGA_5_ ipl_c_2__n SM_AMIGA_2_ inst_RW_000_INT DSACK1_c \
+# inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \
+# state_machine_un3_clk_out_pre_50_n inst_CLK_000_D3 inst_CLK_030_H \
+# state_machine_un12_clk_000_d0_n inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ RST_c \
+# inst_A0_DMA AMIGA_BUS_ENABLE_INT_2_sqmuxa RESETDFFRHreg SM_AMIGA_4_ SM_AMIGA_3_ \
+# RW_c SM_AMIGA_1_ un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n \
+# state_machine_un10_bg_030_n state_machine_lds_000_int_7_n \
+# state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c \
+# state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i N_197_0 \
+# state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n N_130_i \
+# N_131_i CLK_OUT_PRE_25_0 N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \
+# cpu_est_0_ N_140_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_141_i \
+# cpu_est_3_reg N_52_i N_143_i N_142_i state_machine_rw_000_int_7_iv_i_n \
+# cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i \
+# N_30 N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n \
+# N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i \
+# N_79 N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i N_115 \
+# un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 N_71_i \
+# N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 N_145_i N_132 N_146_i \
+# N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 N_142 N_138_i N_144 \
+# N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 \
+# N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 \
+# state_machine_uds_000_int_7_0_n N_168 N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 \
+# N_220 N_117_i N_230 N_118_i N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i \
+# N_201 N_115_i N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \
+# state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n N_134 \
+# N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 state_machine_ds_000_dma_3_n \
+# N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n \
+# N_230_1 N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 \
+# sm_amiga_i_4__n N_230_6 sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n \
+# cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n \
+# N_122_3 RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \
+# DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \
+# N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \
+# sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \
+# state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 \
+# cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 VPA_D_i N_132_1 \
+# AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 \
+# A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i \
+# AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n bgack_030_int_0_un3_n \
+# a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n \
+# as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n \
+# a_i_25__n ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n \
+# clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n \
+# CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n \
+# rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n \
+# state_machine_uds_000_int_7_0_m3_un1_n RW_000_c \
+# state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \
# ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \
# ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \
# ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \
# cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \
# cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n \
-# a_c_19__n cpu_estse_2_un0_n amiga_bus_enable_0_un3_n a_c_20__n \
-# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_21__n \
-# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_22__n as_030_000_sync_0_un0_n \
-# clk_030_h_0_un3_n a_c_23__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_24__n \
-# uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_25__n uds_000_int_0_un0_n \
-# lds_000_int_0_un3_n a_c_26__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_27__n \
-# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_28__n fpu_cs_int_0_un0_n bg_000_0_un3_n \
-# a_c_29__n bg_000_0_un1_n bg_000_0_un0_n a_c_30__n ds_000_dma_0_un3_n \
-# ds_000_dma_0_un1_n a_c_31__n ds_000_dma_0_un0_n as_000_dma_0_un3_n A0_c \
-# as_000_dma_0_un1_n as_000_dma_0_un0_n nEXP_SPACE_c as_000_int_0_un3_n \
-# as_000_int_0_un1_n as_000_int_0_un0_n BG_030_c BG_000DFFSHreg BGACK_000_c
+# a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_20__n \
+# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n \
+# uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_23__n \
+# lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n \
+# fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n \
+# avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n \
+# bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \
+# a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n \
+# vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
-RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
-A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \
-A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF \
-DSACK_1_.BLIF AS_030.BLIF AS_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF \
-A0.BLIF DTACK.BLIF SIZE_0_.BLIF DSACK_0_.BLIF CLK_030_c.BLIF CLK_000_c.BLIF \
-CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.BLIF CLK_OUT_INTreg.BLIF \
-inst_FPU_CS_INTreg.BLIF inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
-IPL_030DFFSH_0_reg.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \
-IPL_030DFFSH_1_reg.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF \
-IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
-ipl_c_0__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D4.BLIF ipl_c_1__n.BLIF \
-inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF ipl_c_2__n.BLIF \
-inst_CLK_OUT_PRE_25.BLIF vcc_n_n.BLIF gnd_n_n.BLIF dsack_c_1__n.BLIF \
-state_machine_un13_clk_000_d0_n.BLIF inst_AS_000_INT.BLIF SM_AMIGA_1_.BLIF \
-SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF inst_UDS_000_INT.BLIF \
-inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF clk_un3_clk_out_pre_50_n.BLIF \
-RST_c.BLIF inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF RESETDFFRHreg.BLIF \
-state_machine_un6_bgack_000_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \
-RW_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF fc_c_0__n.BLIF \
-SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF fc_c_1__n.BLIF SM_AMIGA_7_.BLIF \
-un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF \
-SM_AMIGA_4_.BLIF AMIGA_BUS_DATA_DIR_c.BLIF state_machine_ds_000_dma_3_n.BLIF \
-SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF cpu_est_ns_0_1__n.BLIF \
-state_machine_un10_bg_030_n.BLIF N_134_i.BLIF \
-state_machine_lds_000_int_7_n.BLIF N_169_i.BLIF \
-state_machine_uds_000_int_7_n.BLIF N_133_i.BLIF N_167_i.BLIF N_51_0.BLIF \
-N_140_i.BLIF N_202_0.BLIF N_86_0.BLIF N_171_i.BLIF \
-un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_82_i.BLIF sm_amiga_i_1__n.BLIF \
-N_78_i.BLIF N_170_i.BLIF N_77_0.BLIF CLK_000_D1_i.BLIF CLK_OUT_PRE_25_0.BLIF \
-N_76_i.BLIF N_74_i.BLIF N_72_0.BLIF AS_030_000_SYNC_i.BLIF CLK_000_D2_i.BLIF \
-state_machine_un8_bgack_030_int_i_0_0_n.BLIF cpu_est_0_.BLIF N_69_i.BLIF \
-cpu_est_1_.BLIF AS_030_c_i.BLIF cpu_est_2_.BLIF N_65_i.BLIF cpu_est_3_reg.BLIF \
-N_64_i.BLIF N_62_i.BLIF N_152_i.BLIF N_153_i.BLIF cpu_est_ns_1__n.BLIF \
-N_61_0.BLIF cpu_est_ns_2__n.BLIF N_150_i.BLIF \
-state_machine_un8_bgack_030_int_i_0_n.BLIF N_148_i.BLIF N_197.BLIF \
-N_149_i.BLIF N_198.BLIF N_199.BLIF N_123_i.BLIF N_200.BLIF N_145_i.BLIF \
-N_201.BLIF N_146_i.BLIF sm_amiga_ns_0_0__n.BLIF N_51.BLIF N_142_i.BLIF \
-N_53.BLIF N_143_i.BLIF N_61.BLIF N_144_i.BLIF N_62.BLIF cpu_est_ns_0_2__n.BLIF \
-N_64.BLIF N_141_i.BLIF N_65.BLIF N_53_0.BLIF N_66.BLIF N_139_i.BLIF N_69.BLIF \
-state_machine_amiga_bus_enable_4_iv_i_n.BLIF N_72.BLIF N_138_i.BLIF N_74.BLIF \
-N_48_i.BLIF N_76.BLIF N_136_i.BLIF N_77.BLIF N_137_i.BLIF N_78.BLIF \
-AMIGA_BUS_DATA_DIR_c_0.BLIF N_82.BLIF N_135_i.BLIF N_86.BLIF N_168_i.BLIF \
-N_202.BLIF N_151_i.BLIF N_203.BLIF N_132_i.BLIF N_205.BLIF N_164_i.BLIF \
-N_206.BLIF N_115.BLIF N_130_i.BLIF N_116.BLIF N_131_i.BLIF N_117.BLIF \
-N_41_0.BLIF N_118.BLIF N_128_i.BLIF N_120.BLIF N_129_i.BLIF N_121.BLIF \
-sm_amiga_ns_0_5__n.BLIF N_122.BLIF N_126_i.BLIF N_123.BLIF N_127_i.BLIF \
-N_124.BLIF N_125.BLIF N_125_i.BLIF N_126.BLIF N_127.BLIF N_124_i.BLIF \
-N_128.BLIF N_129.BLIF N_122_i.BLIF N_130.BLIF N_131.BLIF N_172_i.BLIF \
-N_132.BLIF state_machine_size_dma_4_0_1__n.BLIF N_133.BLIF \
-state_machine_ds_000_dma_3_0_n.BLIF N_134.BLIF N_66_i.BLIF N_135.BLIF \
-N_120_i.BLIF N_136.BLIF state_machine_lds_000_int_7_0_n.BLIF N_137.BLIF \
-state_machine_uds_000_int_7_0_n.BLIF N_138.BLIF N_118_i.BLIF N_139.BLIF \
-N_201_0.BLIF N_140.BLIF N_117_i.BLIF N_141.BLIF N_200_0.BLIF N_142.BLIF \
-N_115_i.BLIF N_143.BLIF N_116_i.BLIF N_144.BLIF N_199_0.BLIF N_145.BLIF \
-BG_030_c_i.BLIF N_146.BLIF N_206_i.BLIF N_147.BLIF \
-state_machine_un10_bg_030_0_n.BLIF N_148.BLIF N_198_0.BLIF N_149.BLIF \
-N_197_0.BLIF N_150.BLIF N_203_i.BLIF N_152.BLIF \
-state_machine_un13_clk_000_d0_i_n.BLIF N_153.BLIF \
-state_machine_un15_clk_000_d0_0_n.BLIF N_164.BLIF \
-state_machine_un6_bgack_000_0_n.BLIF N_167.BLIF N_225_1.BLIF N_168.BLIF \
-N_225_2.BLIF N_169.BLIF N_225_3.BLIF N_170.BLIF N_225_4.BLIF N_171.BLIF \
-N_225_5.BLIF N_172.BLIF N_225_6.BLIF N_173.BLIF N_228_1.BLIF N_225.BLIF \
-N_228_2.BLIF N_228.BLIF N_69_i_1.BLIF CLK_000_D0_i.BLIF N_69_i_2.BLIF \
-BGACK_030_INT_i.BLIF N_69_i_3.BLIF CLK_030_i.BLIF N_69_i_4.BLIF \
-cpu_est_i_3__n.BLIF N_69_i_5.BLIF sm_amiga_i_6__n.BLIF \
-state_machine_un8_bgack_030_int_i_0_0_1_n.BLIF nEXP_SPACE_i.BLIF N_72_0_1.BLIF \
-CLK_000_D4_i.BLIF N_51_0_1.BLIF sm_amiga_i_5__n.BLIF N_51_0_2.BLIF \
-sm_amiga_i_4__n.BLIF cpu_est_ns_0_1_1__n.BLIF AS_000_i.BLIF \
-cpu_est_ns_0_2_1__n.BLIF LDS_000_i.BLIF N_128_1.BLIF UDS_000_i.BLIF \
-N_128_2.BLIF cpu_est_i_1__n.BLIF N_118_1.BLIF cpu_est_i_0__n.BLIF N_118_2.BLIF \
-DTACK_D0_i.BLIF N_118_3.BLIF VMA_INT_i.BLIF N_206_1.BLIF VPA_D_i.BLIF \
-N_206_2.BLIF AS_000_DMA_i.BLIF sm_amiga_ns_0_1_0__n.BLIF CLK_030_H_i.BLIF \
-cpu_est_ns_0_1_2__n.BLIF RW_i.BLIF N_53_0_1.BLIF cpu_est_i_2__n.BLIF \
-N_43_i_1.BLIF sm_amiga_i_0__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF \
-sm_amiga_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF \
-sm_amiga_i_7__n.BLIF N_199_0_1.BLIF A0_i.BLIF N_152_1.BLIF size_i_1__n.BLIF \
-N_147_1.BLIF DS_030_i.BLIF N_139_1.BLIF a_i_19__n.BLIF N_137_1.BLIF \
-a_i_16__n.BLIF N_127_1.BLIF a_i_18__n.BLIF N_120_1.BLIF a_i_30__n.BLIF \
-state_machine_a0_dma_2_1_n.BLIF a_i_31__n.BLIF N_116_1.BLIF a_i_28__n.BLIF \
-N_115_1.BLIF a_i_29__n.BLIF state_machine_un13_clk_000_d0_1_n.BLIF \
-a_i_26__n.BLIF N_203_1.BLIF a_i_27__n.BLIF \
-state_machine_uds_000_int_7_0_m3_un3_n.BLIF a_i_24__n.BLIF \
-state_machine_uds_000_int_7_0_m3_un1_n.BLIF a_i_25__n.BLIF \
-state_machine_uds_000_int_7_0_m3_un0_n.BLIF RST_i.BLIF dsack1_int_0_un3_n.BLIF \
-dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_205_i.BLIF \
-vma_int_0_un3_n.BLIF FPU_CS_INT_i.BLIF vma_int_0_un1_n.BLIF \
-CLK_OUT_PRE_50_D_i.BLIF vma_int_0_un0_n.BLIF AS_030_c.BLIF \
-bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF AS_000_c.BLIF \
-bgack_030_int_0_un0_n.BLIF ipl_030_0_0__un3_n.BLIF DS_030_c.BLIF \
-ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF \
+A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
+A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
+A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \
+AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \
+DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \
+inst_BGACK_030_INTreg.BLIF BGACK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \
+inst_avec_expreg.BLIF CLK_030_c.BLIF inst_VMA_INTreg.BLIF \
+inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_AS_000_DMA.BLIF CLK_OSZI_c.BLIF inst_VPA_D.BLIF \
+inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF \
+inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF \
+IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF \
+IPL_030DFFSH_1_reg.BLIF SM_AMIGA_7_.BLIF vcc_n_n.BLIF IPL_030DFFSH_2_reg.BLIF \
+gnd_n_n.BLIF state_machine_un10_clk_000_d0_n.BLIF ipl_c_0__n.BLIF \
+inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF ipl_c_1__n.BLIF SM_AMIGA_0_.BLIF \
+SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF \
+DSACK1_c.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \
+state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D3.BLIF \
+inst_CLK_030_H.BLIF state_machine_un12_clk_000_d0_n.BLIF inst_DS_000_DMA.BLIF \
+SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF RST_c.BLIF inst_A0_DMA.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF \
+SM_AMIGA_3_.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF un1_DSACK1_INT_0_sqmuxa_3.BLIF \
+fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un10_bg_030_n.BLIF \
+state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \
+AMIGA_BUS_DATA_DIR_c.BLIF state_machine_un6_bgack_000_0_n.BLIF N_194_0.BLIF \
+N_119_i.BLIF N_120_i.BLIF N_197_0.BLIF state_machine_ds_000_dma_3_0_n.BLIF \
+N_171_i.BLIF state_machine_size_dma_4_0_1__n.BLIF N_130_i.BLIF N_131_i.BLIF \
+CLK_OUT_PRE_25_0.BLIF N_132_i.BLIF N_133_i.BLIF N_134_i.BLIF \
+sm_amiga_ns_0_5__n.BLIF N_135_i.BLIF N_139_i.BLIF cpu_est_0_.BLIF N_140_i.BLIF \
+cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_141_i.BLIF \
+cpu_est_3_reg.BLIF N_52_i.BLIF N_143_i.BLIF N_142_i.BLIF \
+state_machine_rw_000_int_7_iv_i_n.BLIF cpu_est_ns_1__n.BLIF N_62_0.BLIF \
+cpu_est_ns_2__n.BLIF N_161_i.BLIF N_193.BLIF N_155_i.BLIF N_196.BLIF \
+N_63_0.BLIF N_28.BLIF N_66_i.BLIF N_30.BLIF N_76_i.BLIF N_55.BLIF \
+CLK_000_D1_i.BLIF N_62.BLIF N_77_i.BLIF N_63.BLIF N_79_0.BLIF N_66.BLIF \
+N_199_0.BLIF N_67.BLIF sm_amiga_i_2__n.BLIF N_69.BLIF N_201_0.BLIF N_70.BLIF \
+N_203_0.BLIF N_71.BLIF cpu_est_ns_0_1__n.BLIF N_75.BLIF N_167_i.BLIF N_76.BLIF \
+N_170_i.BLIF N_77.BLIF N_136_i.BLIF N_79.BLIF N_137_i.BLIF N_90.BLIF \
+N_202_0.BLIF N_200.BLIF N_200_0.BLIF N_202.BLIF N_169_i.BLIF N_204.BLIF \
+N_198_0.BLIF N_114.BLIF N_168_i.BLIF N_115.BLIF \
+un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_116.BLIF N_90_i.BLIF N_117.BLIF \
+AS_030_c_i.BLIF N_118.BLIF N_75_i.BLIF N_120.BLIF N_71_i.BLIF N_121.BLIF \
+N_69_i.BLIF N_122.BLIF N_67_i.BLIF N_124.BLIF N_150_i.BLIF N_125.BLIF \
+N_151_i.BLIF N_128.BLIF N_129.BLIF N_145_i.BLIF N_132.BLIF N_146_i.BLIF \
+N_136.BLIF N_147_i.BLIF N_137.BLIF cpu_est_ns_0_2__n.BLIF N_138.BLIF \
+N_144_i.BLIF N_140.BLIF N_55_0.BLIF N_142.BLIF N_138_i.BLIF N_144.BLIF \
+N_172_i.BLIF N_145.BLIF N_149_i.BLIF N_146.BLIF N_129_i.BLIF N_147.BLIF \
+N_148.BLIF N_128_i.BLIF N_150.BLIF sm_amiga_ns_0_0__n.BLIF N_151.BLIF \
+N_70_i.BLIF N_155.BLIF N_124_i.BLIF N_166.BLIF \
+state_machine_lds_000_int_7_0_n.BLIF N_167.BLIF \
+state_machine_uds_000_int_7_0_n.BLIF N_168.BLIF N_122_i.BLIF N_169.BLIF \
+N_30_0.BLIF N_170.BLIF N_121_i.BLIF N_172.BLIF N_28_0.BLIF N_220.BLIF \
+N_117_i.BLIF N_230.BLIF N_118_i.BLIF N_133.BLIF N_196_0.BLIF N_143.BLIF \
+N_116_i.BLIF N_143_2.BLIF N_195_i.BLIF N_203.BLIF BG_030_c_i.BLIF N_201.BLIF \
+N_115_i.BLIF N_199.BLIF state_machine_un10_bg_030_0_n.BLIF N_161.BLIF \
+N_193_0.BLIF N_141.BLIF N_204_i.BLIF N_139.BLIF \
+state_machine_un10_clk_000_d0_i_n.BLIF N_135.BLIF \
+state_machine_un12_clk_000_d0_0_n.BLIF N_134.BLIF N_69_i_1.BLIF N_131.BLIF \
+N_76_i_1.BLIF N_130.BLIF N_76_i_2.BLIF N_171.BLIF N_76_i_3.BLIF \
+state_machine_ds_000_dma_3_n.BLIF N_76_i_4.BLIF N_197.BLIF N_76_i_5.BLIF \
+N_119.BLIF N_220_1.BLIF N_194.BLIF N_220_2.BLIF \
+state_machine_un6_bgack_000_n.BLIF N_230_1.BLIF N_143_2_i.BLIF N_230_2.BLIF \
+a_i_18__n.BLIF N_230_3.BLIF a_i_16__n.BLIF N_230_4.BLIF a_i_19__n.BLIF \
+N_230_5.BLIF sm_amiga_i_4__n.BLIF N_230_6.BLIF sm_amiga_i_5__n.BLIF \
+cpu_est_ns_0_1_1__n.BLIF sm_amiga_i_3__n.BLIF cpu_est_ns_0_2_1__n.BLIF \
+CLK_000_D0_i.BLIF N_122_1.BLIF sm_amiga_i_0__n.BLIF N_122_2.BLIF \
+sm_amiga_i_1__n.BLIF N_122_3.BLIF RW_i.BLIF N_115_1.BLIF CLK_030_H_i.BLIF \
+N_115_2.BLIF CLK_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF \
+DTACK_D0_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \
+N_133_1.BLIF AS_000_i.BLIF N_133_2.BLIF UDS_000_i.BLIF N_143_1.BLIF \
+LDS_000_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_000_i.BLIF N_55_0_1.BLIF \
+sm_amiga_i_6__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF \
+cpu_est_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF \
+sm_amiga_i_7__n.BLIF N_196_0_1.BLIF CLK_000_D2_i.BLIF N_155_1.BLIF \
+cpu_est_i_1__n.BLIF N_148_1.BLIF cpu_est_i_0__n.BLIF N_142_1.BLIF \
+VMA_INT_i.BLIF N_140_1.BLIF VPA_D_i.BLIF N_132_1.BLIF AS_000_DMA_i.BLIF \
+N_124_1.BLIF nEXP_SPACE_i.BLIF state_machine_a0_dma_2_1_n.BLIF \
+cpu_est_i_2__n.BLIF N_120_1.BLIF A0_i.BLIF N_118_1.BLIF size_i_1__n.BLIF \
+N_117_1.BLIF DS_030_i.BLIF N_116_1.BLIF AS_030_000_SYNC_i.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF a_i_30__n.BLIF N_204_1.BLIF \
+a_i_31__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_28__n.BLIF \
+bgack_030_int_0_un1_n.BLIF a_i_29__n.BLIF bgack_030_int_0_un0_n.BLIF \
+a_i_26__n.BLIF as_000_dma_0_un3_n.BLIF a_i_27__n.BLIF as_000_dma_0_un1_n.BLIF \
+a_i_24__n.BLIF as_000_dma_0_un0_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un3_n.BLIF \
+RST_i.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \
+clk_030_h_0_un3_n.BLIF N_114_i.BLIF clk_030_h_0_un1_n.BLIF FPU_CS_INT_i.BLIF \
+clk_030_h_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_int_0_un3_n.BLIF \
+AS_030_c.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF AS_000_c.BLIF \
+state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
+state_machine_uds_000_int_7_0_m3_un1_n.BLIF RW_000_c.BLIF \
+state_machine_uds_000_int_7_0_m3_un0_n.BLIF ipl_030_0_0__un3_n.BLIF \
+DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF \
ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF LDS_000_c.BLIF \
ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF \
ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF \
@@ -177,24 +178,22 @@ cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_16__n.BLIF \
cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF \
cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF \
cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_19__n.BLIF \
-cpu_estse_2_un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF a_c_20__n.BLIF \
-amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF a_c_21__n.BLIF \
-as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF a_c_22__n.BLIF \
-as_030_000_sync_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_23__n.BLIF \
-clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_24__n.BLIF \
-uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_25__n.BLIF \
-uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_26__n.BLIF \
-lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_27__n.BLIF \
-fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_28__n.BLIF \
-fpu_cs_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF a_c_29__n.BLIF bg_000_0_un1_n.BLIF \
-bg_000_0_un0_n.BLIF a_c_30__n.BLIF ds_000_dma_0_un3_n.BLIF \
-ds_000_dma_0_un1_n.BLIF a_c_31__n.BLIF ds_000_dma_0_un0_n.BLIF \
-as_000_dma_0_un3_n.BLIF A0_c.BLIF as_000_dma_0_un1_n.BLIF \
-as_000_dma_0_un0_n.BLIF nEXP_SPACE_c.BLIF as_000_int_0_un3_n.BLIF \
-as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF BG_030_c.BLIF \
-BG_000DFFSHreg.BLIF BGACK_000_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
-DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
-SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
+cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF a_c_20__n.BLIF \
+as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF a_c_21__n.BLIF \
+uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_22__n.BLIF \
+uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_23__n.BLIF \
+lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_24__n.BLIF \
+fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_25__n.BLIF \
+fpu_cs_int_0_un0_n.BLIF avec_exp_0_un3_n.BLIF a_c_26__n.BLIF \
+avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF a_c_27__n.BLIF bg_000_0_un3_n.BLIF \
+bg_000_0_un1_n.BLIF a_c_28__n.BLIF bg_000_0_un0_n.BLIF as_000_int_0_un3_n.BLIF \
+a_c_29__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF a_c_30__n.BLIF \
+dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF a_c_31__n.BLIF \
+dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF A0_c.BLIF vma_int_0_un1_n.BLIF \
+vma_int_0_un0_n.BLIF nEXP_SPACE_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
+RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
+SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \
+RW.PIN.BLIF
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \
@@ -212,93 +211,91 @@ inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D \
inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D \
inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \
-SIZE_DMA_0_.AP inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \
-inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \
-inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
-BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \
-inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \
-inst_AS_000_INT.C inst_AS_000_INT.AP AMIGA_BUS_ENABLEDFFSHreg.D \
-AMIGA_BUS_ENABLEDFFSHreg.C AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_030_000_SYNC.D \
+SIZE_DMA_0_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \
+inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \
+inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \
+BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \
+inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
+inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D \
+inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D \
inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D \
-inst_CLK_030_H.C inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_000_D4.D \
-inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_DTACK_D0.D inst_DTACK_D0.C \
-inst_DTACK_D0.AP inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP \
-inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D \
-CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \
+inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \
+inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C \
+inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \
+CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D \
+inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C \
inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C \
inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \
inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \
-RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ DSACK_1_ AS_030 \
-AS_000 DS_030 UDS_000 LDS_000 A0 DTACK SIZE_0_ DSACK_0_ CLK_030_c CLK_000_c \
-CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n \
-state_machine_un13_clk_000_d0_n clk_un3_clk_out_pre_50_n RST_c \
-state_machine_un6_bgack_000_n state_machine_un15_clk_000_d0_n RW_c fc_c_0__n \
-fc_c_1__n un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 AMIGA_BUS_DATA_DIR_c \
-state_machine_ds_000_dma_3_n cpu_est_ns_0_1__n state_machine_un10_bg_030_n \
-N_134_i state_machine_lds_000_int_7_n N_169_i state_machine_uds_000_int_7_n \
-N_133_i N_167_i N_51_0 N_140_i N_202_0 N_86_0 N_171_i \
-un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 N_82_i sm_amiga_i_1__n N_78_i N_170_i N_77_0 \
-CLK_000_D1_i N_76_i N_74_i N_72_0 AS_030_000_SYNC_i CLK_000_D2_i \
-state_machine_un8_bgack_030_int_i_0_0_n N_69_i AS_030_c_i N_65_i N_64_i N_62_i \
-N_152_i N_153_i cpu_est_ns_1__n N_61_0 cpu_est_ns_2__n N_150_i \
-state_machine_un8_bgack_030_int_i_0_n N_148_i N_197 N_149_i N_198 N_199 \
-N_123_i N_200 N_145_i N_201 N_146_i sm_amiga_ns_0_0__n N_51 N_142_i N_53 \
-N_143_i N_61 N_144_i N_62 cpu_est_ns_0_2__n N_64 N_141_i N_65 N_53_0 N_66 \
-N_139_i N_69 state_machine_amiga_bus_enable_4_iv_i_n N_72 N_138_i N_74 N_48_i \
-N_76 N_136_i N_77 N_137_i N_78 AMIGA_BUS_DATA_DIR_c_0 N_82 N_135_i N_86 \
-N_168_i N_202 N_151_i N_203 N_132_i N_205 N_164_i N_206 N_115 N_130_i N_116 \
-N_131_i N_117 N_41_0 N_118 N_128_i N_120 N_129_i N_121 sm_amiga_ns_0_5__n \
-N_122 N_126_i N_123 N_127_i N_124 N_125 N_125_i N_126 N_127 N_124_i N_128 \
-N_129 N_122_i N_130 N_131 N_172_i N_132 state_machine_size_dma_4_0_1__n N_133 \
-state_machine_ds_000_dma_3_0_n N_134 N_66_i N_135 N_120_i N_136 \
-state_machine_lds_000_int_7_0_n N_137 state_machine_uds_000_int_7_0_n N_138 \
-N_118_i N_139 N_201_0 N_140 N_117_i N_141 N_200_0 N_142 N_115_i N_143 N_116_i \
-N_144 N_199_0 N_145 BG_030_c_i N_146 N_206_i N_147 \
-state_machine_un10_bg_030_0_n N_148 N_198_0 N_149 N_197_0 N_150 N_203_i N_152 \
-state_machine_un13_clk_000_d0_i_n N_153 state_machine_un15_clk_000_d0_0_n \
-N_164 state_machine_un6_bgack_000_0_n N_167 N_225_1 N_168 N_225_2 N_169 \
-N_225_3 N_170 N_225_4 N_171 N_225_5 N_172 N_225_6 N_173 N_228_1 N_225 N_228_2 \
-N_228 N_69_i_1 CLK_000_D0_i N_69_i_2 BGACK_030_INT_i N_69_i_3 CLK_030_i \
-N_69_i_4 cpu_est_i_3__n N_69_i_5 sm_amiga_i_6__n \
-state_machine_un8_bgack_030_int_i_0_0_1_n nEXP_SPACE_i N_72_0_1 CLK_000_D4_i \
-N_51_0_1 sm_amiga_i_5__n N_51_0_2 sm_amiga_i_4__n cpu_est_ns_0_1_1__n AS_000_i \
-cpu_est_ns_0_2_1__n LDS_000_i N_128_1 UDS_000_i N_128_2 cpu_est_i_1__n N_118_1 \
-cpu_est_i_0__n N_118_2 DTACK_D0_i N_118_3 VMA_INT_i N_206_1 VPA_D_i N_206_2 \
-AS_000_DMA_i sm_amiga_ns_0_1_0__n CLK_030_H_i cpu_est_ns_0_1_2__n RW_i \
-N_53_0_1 cpu_est_i_2__n N_43_i_1 sm_amiga_i_0__n \
-state_machine_lds_000_int_7_0_1_n sm_amiga_i_3__n \
-state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_199_0_1 A0_i N_152_1 \
-size_i_1__n N_147_1 DS_030_i N_139_1 a_i_19__n N_137_1 a_i_16__n N_127_1 \
-a_i_18__n N_120_1 a_i_30__n state_machine_a0_dma_2_1_n a_i_31__n N_116_1 \
-a_i_28__n N_115_1 a_i_29__n state_machine_un13_clk_000_d0_1_n a_i_26__n \
-N_203_1 a_i_27__n state_machine_uds_000_int_7_0_m3_un3_n a_i_24__n \
-state_machine_uds_000_int_7_0_m3_un1_n a_i_25__n \
-state_machine_uds_000_int_7_0_m3_un0_n RST_i dsack1_int_0_un3_n \
-dsack1_int_0_un1_n dsack1_int_0_un0_n N_205_i vma_int_0_un3_n FPU_CS_INT_i \
-vma_int_0_un1_n CLK_OUT_PRE_50_D_i vma_int_0_un0_n AS_030_c \
-bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_000_c bgack_030_int_0_un0_n \
-ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c \
-ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n \
-ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n \
-size_c_1__n cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n \
-cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n \
-cpu_estse_2_un3_n cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n \
-amiga_bus_enable_0_un3_n a_c_20__n amiga_bus_enable_0_un1_n \
-amiga_bus_enable_0_un0_n a_c_21__n as_030_000_sync_0_un3_n \
-as_030_000_sync_0_un1_n a_c_22__n as_030_000_sync_0_un0_n clk_030_h_0_un3_n \
-a_c_23__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_24__n uds_000_int_0_un3_n \
-uds_000_int_0_un1_n a_c_25__n uds_000_int_0_un0_n lds_000_int_0_un3_n \
-a_c_26__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_27__n fpu_cs_int_0_un3_n \
-fpu_cs_int_0_un1_n a_c_28__n fpu_cs_int_0_un0_n bg_000_0_un3_n a_c_29__n \
-bg_000_0_un1_n bg_000_0_un0_n a_c_30__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n \
-a_c_31__n ds_000_dma_0_un0_n as_000_dma_0_un3_n A0_c as_000_dma_0_un1_n \
-as_000_dma_0_un0_n nEXP_SPACE_c as_000_int_0_un3_n as_000_int_0_un1_n \
-as_000_int_0_un0_n BG_030_c BGACK_000_c AS_030.OE AS_000.OE DS_030.OE \
-UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE \
-DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
-.names N_148_i.BLIF N_149_i.BLIF cpu_est_0_.D
+RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \
+DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ BG_030_c BGACK_000_c \
+CLK_030_c CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n state_machine_un10_clk_000_d0_n \
+ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c state_machine_un3_clk_out_pre_50_n \
+state_machine_un12_clk_000_d0_n RST_c AMIGA_BUS_ENABLE_INT_2_sqmuxa RW_c \
+un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n \
+state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n \
+AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i \
+N_197_0 state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n \
+N_130_i N_131_i N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \
+N_140_i AMIGA_BUS_DATA_DIR_c_0 N_141_i N_52_i N_143_i N_142_i \
+state_machine_rw_000_int_7_iv_i_n cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n \
+N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i N_30 N_76_i N_55 CLK_000_D1_i \
+N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n N_69 N_201_0 N_70 \
+N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i N_79 \
+N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i \
+N_115 un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i \
+N_120 N_71_i N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 \
+N_145_i N_132 N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i \
+N_140 N_55_0 N_142 N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 \
+N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 \
+state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n N_168 \
+N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i N_230 N_118_i \
+N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i N_201 N_115_i \
+N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \
+state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n \
+N_134 N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 \
+state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 \
+N_220_2 state_machine_un6_bgack_000_n N_230_1 N_143_2_i N_230_2 a_i_18__n \
+N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 \
+sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n \
+CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n N_122_3 RW_i \
+N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \
+DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \
+N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \
+sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \
+state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i \
+N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 \
+VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n \
+cpu_est_i_2__n N_120_1 A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 \
+AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n \
+bgack_030_int_0_un3_n a_i_28__n bgack_030_int_0_un1_n a_i_29__n \
+bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n \
+as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n a_i_25__n ds_000_dma_0_un3_n \
+RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i \
+clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i \
+rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c \
+state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n \
+RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \
+ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \
+ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \
+ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \
+cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \
+cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n \
+cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n \
+a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n \
+uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n \
+lds_000_int_0_un3_n a_c_23__n lds_000_int_0_un1_n lds_000_int_0_un0_n \
+a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n \
+avec_exp_0_un3_n a_c_26__n avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n \
+bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n \
+a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n a_c_30__n dsack1_int_0_un3_n \
+dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c \
+vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c AS_030.OE AS_000.OE RW_000.OE \
+DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE \
+RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0
+.names N_150_i.BLIF N_151_i.BLIF cpu_est_0_.D
11 1
.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
1- 1
@@ -309,7 +306,7 @@ DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
1- 1
-1 1
-.names N_43_i_1.BLIF N_164_i.BLIF SM_AMIGA_0_.D
+.names CLK_000_D0_i.BLIF N_135_i.BLIF SM_AMIGA_0_.D
11 1
.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
0 1
@@ -324,18 +321,18 @@ DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
-1 1
.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
0 1
-.names N_122_i.BLIF N_123_i.BLIF SM_AMIGA_6_.D
+.names N_129_i.BLIF N_198_0.BLIF SM_AMIGA_6_.D
11 1
-.names inst_CLK_000_D0.BLIF N_124_i.BLIF SM_AMIGA_5_.D
+.names inst_CLK_000_D0.BLIF N_200.BLIF SM_AMIGA_5_.D
11 1
-.names CLK_000_D0_i.BLIF N_125_i.BLIF SM_AMIGA_4_.D
+.names CLK_000_D0_i.BLIF N_130_i.BLIF SM_AMIGA_4_.D
11 1
-.names N_126_i.BLIF N_127_i.BLIF SM_AMIGA_3_.D
+.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_3_.D
11 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
-.names N_41_0.BLIF SM_AMIGA_1_.D
-0 1
+.names inst_CLK_000_D0.BLIF N_201.BLIF SM_AMIGA_1_.D
+11 1
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
1- 1
-1 1
@@ -346,17 +343,17 @@ DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_OUT_PRE_25_0
inst_BGACK_030_INTreg.D
1- 1
-1 1
-.names N_121.BLIF SIZE_DMA_0_.D
+.names N_125.BLIF SIZE_DMA_0_.D
0 1
-.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
-1- 1
--1 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D
1- 1
-1 1
+.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D
+1- 1
+-1 1
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
@@ -369,8 +366,7 @@ inst_BGACK_030_INTreg.D
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
-.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \
-AMIGA_BUS_ENABLEDFFSHreg.D
+.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
1- 1
-1 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \
@@ -380,673 +376,680 @@ inst_AS_030_000_SYNC.D
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
-.names state_machine_a0_dma_2_1_n.BLIF N_173.BLIF inst_A0_DMA.D
+.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
+1- 1
+-1 1
+.names state_machine_a0_dma_2_1_n.BLIF N_166.BLIF inst_A0_DMA.D
11 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
.names vcc_n_n
1
.names gnd_n_n
-.names state_machine_un13_clk_000_d0_1_n.BLIF N_168.BLIF \
-state_machine_un13_clk_000_d0_n
+.names state_machine_un10_clk_000_d0_1_n.BLIF \
+state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n
11 1
.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \
-clk_un3_clk_out_pre_50_n
+state_machine_un3_clk_out_pre_50_n
11 1
-.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
-.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n
-0 1
-.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2
-0 1
-.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
-0 1
-.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
-0 1
-.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
+.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa
11 1
+.names un1_DSACK1_INT_0_sqmuxa_3_0.BLIF un1_DSACK1_INT_0_sqmuxa_3
+0 1
.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
-.names N_134.BLIF N_134_i
-0 1
.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n
0 1
-.names N_169.BLIF N_169_i
-0 1
.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n
0 1
-.names N_133.BLIF N_133_i
+.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
0 1
-.names N_167.BLIF N_167_i
-0 1
-.names N_51_0_1.BLIF N_51_0_2.BLIF N_51_0
+.names BGACK_000_c.BLIF N_77.BLIF state_machine_un6_bgack_000_0_n
11 1
-.names N_140.BLIF N_140_i
-0 1
-.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_202_0
+.names CLK_030_c.BLIF N_143_2.BLIF N_194_0
11 1
-.names CLK_000_D0_i.BLIF N_74_i.BLIF N_86_0
+.names N_119.BLIF N_119_i
+0 1
+.names N_120.BLIF N_120_i
+0 1
+.names N_119_i.BLIF N_120_i.BLIF N_197_0
+11 1
+.names AS_000_DMA_i.BLIF N_143_2.BLIF state_machine_ds_000_dma_3_0_n
11 1
.names N_171.BLIF N_171_i
0 1
-.names N_65_i.BLIF N_171_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0
-11 1
-.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_82_i
-11 1
-.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
-0 1
-.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_78_i
-11 1
-.names N_170.BLIF N_170_i
-0 1
-.names CLK_000_D0_i.BLIF N_170_i.BLIF N_77_0
-11 1
-.names inst_CLK_000_D1.BLIF CLK_000_D1_i
-0 1
-.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_76_i
-11 1
-.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_74_i
-11 1
-.names N_72_0_1.BLIF CLK_000_D2_i.BLIF N_72_0
-11 1
-.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
-0 1
-.names inst_CLK_000_D2.BLIF CLK_000_D2_i
-0 1
-.names state_machine_un8_bgack_030_int_i_0_0_1_n.BLIF BGACK_030_INT_i.BLIF \
-state_machine_un8_bgack_030_int_i_0_0_n
-11 1
-.names N_69_i_4.BLIF N_69_i_5.BLIF N_69_i
-11 1
-.names AS_030_c.BLIF AS_030_c_i
-0 1
-.names AS_030_c_i.BLIF N_205_i.BLIF N_65_i
-11 1
-.names inst_CLK_000_D4.BLIF SM_AMIGA_5_.BLIF N_64_i
-11 1
-.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_62_i
-11 1
-.names N_152.BLIF N_152_i
-0 1
-.names N_153.BLIF N_153_i
-0 1
-.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
-0 1
-.names N_152_i.BLIF N_153_i.BLIF N_61_0
-11 1
-.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
-0 1
-.names N_150.BLIF N_150_i
-0 1
-.names state_machine_un8_bgack_030_int_i_0_0_n.BLIF \
-state_machine_un8_bgack_030_int_i_0_n
-0 1
-.names N_148.BLIF N_148_i
-0 1
-.names N_197_0.BLIF N_197
-0 1
-.names N_149.BLIF N_149_i
-0 1
-.names N_198_0.BLIF N_198
-0 1
-.names N_199_0.BLIF N_199
-0 1
-.names N_123.BLIF N_123_i
-0 1
-.names N_200_0.BLIF N_200
-0 1
-.names N_145.BLIF N_145_i
-0 1
-.names N_201_0.BLIF N_201
-0 1
-.names N_146.BLIF N_146_i
-0 1
-.names sm_amiga_ns_0_1_0__n.BLIF N_145_i.BLIF sm_amiga_ns_0_0__n
-11 1
-.names N_51_0.BLIF N_51
-0 1
-.names N_142.BLIF N_142_i
-0 1
-.names N_53_0.BLIF N_53
-0 1
-.names N_143.BLIF N_143_i
-0 1
-.names N_61_0.BLIF N_61
-0 1
-.names N_144.BLIF N_144_i
-0 1
-.names N_62_i.BLIF N_62
-0 1
-.names cpu_est_ns_0_1_2__n.BLIF N_143_i.BLIF cpu_est_ns_0_2__n
-11 1
-.names N_64_i.BLIF N_64
-0 1
-.names N_141.BLIF N_141_i
-0 1
-.names N_65_i.BLIF N_65
-0 1
-.names N_53_0_1.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_53_0
-11 1
-.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF \
-state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_66
-1- 1
--1 1
-.names N_139.BLIF N_139_i
-0 1
-.names N_69_i.BLIF N_69
-0 1
-.names inst_BGACK_030_INTreg.BLIF N_139_i.BLIF \
-state_machine_amiga_bus_enable_4_iv_i_n
-11 1
-.names N_72_0.BLIF N_72
-0 1
-.names N_138.BLIF N_138_i
-0 1
-.names N_74_i.BLIF N_74
-0 1
-.names N_138_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_48_i
-11 1
-.names N_76_i.BLIF N_76
-0 1
-.names N_136.BLIF N_136_i
-0 1
-.names N_77_0.BLIF N_77
-0 1
-.names N_137.BLIF N_137_i
-0 1
-.names N_78_i.BLIF N_78
-0 1
-.names N_136_i.BLIF N_137_i.BLIF AMIGA_BUS_DATA_DIR_c_0
-11 1
-.names N_82_i.BLIF N_82
-0 1
-.names N_135.BLIF N_135_i
-0 1
-.names N_86_0.BLIF N_86
-0 1
-.names N_168.BLIF N_168_i
-0 1
-.names N_202_0.BLIF N_202
-0 1
-.names N_135_i.BLIF N_168_i.BLIF N_151_i
-11 1
-.names N_203_1.BLIF VPA_D_i.BLIF N_203
-11 1
-.names N_132.BLIF N_132_i
-0 1
-.names N_170.BLIF SM_AMIGA_1_.BLIF N_205
-11 1
-.names N_164.BLIF N_164_i
-0 1
-.names N_206_1.BLIF N_206_2.BLIF N_206
-11 1
-.names N_115_1.BLIF RW_c.BLIF N_115
+.names N_143_2.BLIF N_171_i.BLIF state_machine_size_dma_4_0_1__n
11 1
.names N_130.BLIF N_130_i
0 1
-.names N_116_1.BLIF RW_i.BLIF N_116
-11 1
.names N_131.BLIF N_131_i
0 1
-.names CLK_030_c.BLIF N_69_i.BLIF N_117
-11 1
-.names N_130_i.BLIF N_131_i.BLIF N_41_0
-11 1
-.names N_118_3.BLIF nEXP_SPACE_c.BLIF N_118
-11 1
-.names N_128.BLIF N_128_i
+.names N_132.BLIF N_132_i
0 1
-.names N_120_1.BLIF size_i_1__n.BLIF N_120
-11 1
-.names N_129.BLIF N_129_i
+.names N_133.BLIF N_133_i
0 1
-.names N_172.BLIF N_173.BLIF N_121
-11 1
-.names N_128_i.BLIF N_129_i.BLIF sm_amiga_ns_0_5__n
-11 1
-.names N_86.BLIF sm_amiga_i_7__n.BLIF N_122
-11 1
-.names N_126.BLIF N_126_i
+.names N_134.BLIF N_134_i
0 1
-.names N_72.BLIF SM_AMIGA_7_.BLIF N_123
+.names N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n
11 1
-.names N_127.BLIF N_127_i
+.names N_135.BLIF N_135_i
0 1
-.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_124
-11 1
-.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_125
-11 1
-.names N_125.BLIF N_125_i
+.names N_139.BLIF N_139_i
0 1
-.names N_62.BLIF sm_amiga_i_3__n.BLIF N_126
-11 1
-.names N_127_1.BLIF inst_CLK_000_D1.BLIF N_127
-11 1
-.names N_124.BLIF N_124_i
+.names N_140.BLIF N_140_i
0 1
-.names N_128_1.BLIF N_128_2.BLIF N_128
+.names N_139_i.BLIF N_140_i.BLIF AMIGA_BUS_DATA_DIR_c_0
11 1
-.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_129
-11 1
-.names N_122.BLIF N_122_i
+.names N_141.BLIF N_141_i
0 1
-.names N_77.BLIF SM_AMIGA_1_.BLIF N_130
+.names N_141_i.BLIF N_143_2.BLIF N_52_i
11 1
-.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_131
+.names N_143.BLIF N_143_i
+0 1
+.names N_142.BLIF N_142_i
+0 1
+.names N_142_i.BLIF N_143_i.BLIF state_machine_rw_000_int_7_iv_i_n
+11 1
+.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
+0 1
+.names LDS_000_c.BLIF UDS_000_c.BLIF N_62_0
+11 1
+.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
+0 1
+.names N_161.BLIF N_161_i
+0 1
+.names N_193_0.BLIF N_193
+0 1
+.names N_155.BLIF N_155_i
+0 1
+.names N_196_0.BLIF N_196
+0 1
+.names N_155_i.BLIF N_161_i.BLIF N_63_0
+11 1
+.names N_28_0.BLIF N_28
+0 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_66_i
+11 1
+.names N_30_0.BLIF N_30
+0 1
+.names N_76_i_4.BLIF N_76_i_5.BLIF N_76_i
+11 1
+.names N_55_0.BLIF N_55
+0 1
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
+0 1
+.names N_62_0.BLIF N_62
+0 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_77_i
+11 1
+.names N_63_0.BLIF N_63
+0 1
+.names CLK_030_i.BLIF N_143_2.BLIF N_79_0
+11 1
+.names N_66_i.BLIF N_66
+0 1
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_199_0
+11 1
+.names N_67_i.BLIF N_67
+0 1
+.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+0 1
+.names N_69_i.BLIF N_69
+0 1
+.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_201_0
+11 1
+.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF \
+state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_70
+1- 1
+-1 1
+.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_203_0
+11 1
+.names N_71_i.BLIF N_71
+0 1
+.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
+11 1
+.names N_75_i.BLIF N_75
+0 1
+.names N_167.BLIF N_167_i
+0 1
+.names N_76_i.BLIF N_76
+0 1
+.names N_170.BLIF N_170_i
+0 1
+.names N_77_i.BLIF N_77
+0 1
+.names N_136.BLIF N_136_i
+0 1
+.names N_79_0.BLIF N_79
+0 1
+.names N_137.BLIF N_137_i
+0 1
+.names N_90_i.BLIF N_90
+0 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_202_0
+11 1
+.names N_200_0.BLIF N_200
+0 1
+.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_200_0
+11 1
+.names N_202_0.BLIF N_202
+0 1
+.names N_169.BLIF N_169_i
+0 1
+.names N_204_1.BLIF VPA_D_i.BLIF N_204
+11 1
+.names N_71.BLIF N_169_i.BLIF N_198_0
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114
+11 1
+.names N_168.BLIF N_168_i
+0 1
+.names N_115_1.BLIF N_115_2.BLIF N_115
+11 1
+.names N_75_i.BLIF N_168_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0
+11 1
+.names N_116_1.BLIF N_69_i.BLIF N_116
+11 1
+.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_90_i
+11 1
+.names N_117_1.BLIF RW_c.BLIF N_117
+11 1
+.names AS_030_c.BLIF AS_030_c_i
+0 1
+.names N_118_1.BLIF RW_i.BLIF N_118
+11 1
+.names AS_030_c_i.BLIF N_114_i.BLIF N_75_i
+11 1
+.names N_120_1.BLIF N_166.BLIF N_120
+11 1
+.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_71_i
+11 1
+.names CLK_030_c.BLIF N_76_i.BLIF N_121
+11 1
+.names N_69_i_1.BLIF inst_CLK_000_D3.BLIF N_69_i
+11 1
+.names N_122_3.BLIF nEXP_SPACE_c.BLIF N_122
+11 1
+.names inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF N_67_i
+11 1
+.names N_124_1.BLIF size_i_1__n.BLIF N_124
+11 1
+.names N_150.BLIF N_150_i
+0 1
+.names N_166.BLIF N_171.BLIF N_125
+11 1
+.names N_151.BLIF N_151_i
+0 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_128
+11 1
+.names N_202.BLIF sm_amiga_i_7__n.BLIF N_129
+11 1
+.names N_145.BLIF N_145_i
+0 1
+.names N_132_1.BLIF inst_CLK_000_D1.BLIF N_132
+11 1
+.names N_146.BLIF N_146_i
+0 1
+.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_136
+11 1
+.names N_147.BLIF N_147_i
+0 1
+.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_137
+11 1
+.names cpu_est_ns_0_1_2__n.BLIF N_146_i.BLIF cpu_est_ns_0_2__n
+11 1
+.names N_90.BLIF cpu_est_2_.BLIF N_138
+11 1
+.names N_144.BLIF N_144_i
+0 1
+.names N_140_1.BLIF nEXP_SPACE_i.BLIF N_140
+11 1
+.names N_55_0_1.BLIF RW_000_i.BLIF N_55_0
+11 1
+.names N_142_1.BLIF SM_AMIGA_6_.BLIF N_142
+11 1
+.names N_138.BLIF N_138_i
+0 1
+.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_144
11 1
.names N_172.BLIF N_172_i
0 1
-.names N_77.BLIF sm_amiga_i_0__n.BLIF N_132
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_145
11 1
-.names N_172_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF \
-state_machine_size_dma_4_0_1__n
+.names N_138_i.BLIF N_172_i.BLIF N_149_i
11 1
-.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_133
+.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_146
11 1
-.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF \
-state_machine_ds_000_dma_3_0_n
-11 1
-.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_134
-11 1
-.names N_66.BLIF N_66_i
+.names N_129.BLIF N_129_i
0 1
-.names N_82.BLIF cpu_est_2_.BLIF N_135
+.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_147
11 1
-.names N_120.BLIF N_120_i
+.names N_148_1.BLIF nEXP_SPACE_i.BLIF N_148
+11 1
+.names N_128.BLIF N_128_i
0 1
-.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_136
+.names N_77.BLIF cpu_est_i_0__n.BLIF N_150
11 1
-.names state_machine_lds_000_int_7_0_1_n.BLIF N_66_i.BLIF \
+.names N_128_i.BLIF N_198_0.BLIF sm_amiga_ns_0_0__n
+11 1
+.names N_77_i.BLIF cpu_est_0_.BLIF N_151
+11 1
+.names N_70.BLIF N_70_i
+0 1
+.names N_155_1.BLIF VPA_D_i.BLIF N_155
+11 1
+.names N_124.BLIF N_124_i
+0 1
+.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_166
+11 1
+.names state_machine_lds_000_int_7_0_1_n.BLIF N_70_i.BLIF \
state_machine_lds_000_int_7_0_n
11 1
-.names N_137_1.BLIF nEXP_SPACE_i.BLIF N_137
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167
11 1
.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF \
state_machine_uds_000_int_7_0_n
11 1
-.names CLK_030_H_i.BLIF N_202.BLIF N_138
+.names N_69_i.BLIF N_71_i.BLIF N_168
11 1
-.names N_118.BLIF N_118_i
+.names N_122.BLIF N_122_i
0 1
-.names N_139_1.BLIF CLK_000_D4_i.BLIF N_139
+.names N_69.BLIF SM_AMIGA_7_.BLIF N_169
11 1
-.names N_118_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_201_0
+.names N_122_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_30_0
11 1
-.names AS_030_c.BLIF N_78.BLIF N_140
+.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_170
+11 1
+.names N_121.BLIF N_121_i
+0 1
+.names N_167.BLIF cpu_est_i_3__n.BLIF N_172
+11 1
+.names AS_030_c_i.BLIF N_121_i.BLIF N_28_0
+11 1
+.names N_220_1.BLIF N_220_2.BLIF N_220
11 1
.names N_117.BLIF N_117_i
0 1
-.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_141
+.names N_230_5.BLIF N_230_6.BLIF N_230
11 1
-.names AS_030_c_i.BLIF N_117_i.BLIF N_200_0
-11 1
-.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_142
-11 1
-.names N_115.BLIF N_115_i
+.names N_118.BLIF N_118_i
0 1
-.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_143
+.names N_133_1.BLIF N_133_2.BLIF N_133
+11 1
+.names N_196_0_1.BLIF N_117_i.BLIF N_196_0
+11 1
+.names N_143_1.BLIF RW_000_i.BLIF N_143
11 1
.names N_116.BLIF N_116_i
0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_144
+.names N_62.BLIF N_166.BLIF N_143_2
11 1
-.names N_199_0_1.BLIF N_115_i.BLIF N_199_0
-11 1
-.names CLK_000_D0_i.BLIF N_171.BLIF N_145
+.names inst_BGACK_030_INTreg.BLIF N_116_i.BLIF N_195_i
11 1
+.names N_203_0.BLIF N_203
+0 1
.names BG_030_c.BLIF BG_030_c_i
0 1
-.names N_164.BLIF SM_AMIGA_0_.BLIF N_146
-11 1
-.names N_206.BLIF N_206_i
+.names N_201_0.BLIF N_201
0 1
-.names N_147_1.BLIF nEXP_SPACE_i.BLIF N_147
-11 1
-.names BG_030_c_i.BLIF N_206_i.BLIF state_machine_un10_bg_030_0_n
-11 1
-.names N_76.BLIF cpu_est_i_0__n.BLIF N_148
-11 1
-.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_i_0_0_n.BLIF N_198_0
-11 1
-.names N_76_i.BLIF cpu_est_0_.BLIF N_149
-11 1
-.names AS_030_c_i.BLIF N_64.BLIF N_197_0
-11 1
-.names LDS_000_c.BLIF UDS_000_c.BLIF N_150
-11 1
-.names N_203.BLIF N_203_i
+.names N_115.BLIF N_115_i
0 1
-.names N_152_1.BLIF VPA_D_i.BLIF N_152
-11 1
-.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n
+.names N_199_0.BLIF N_199
0 1
-.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_153
+.names BG_030_c_i.BLIF N_115_i.BLIF state_machine_un10_bg_030_0_n
11 1
-.names N_203_i.BLIF state_machine_un13_clk_000_d0_i_n.BLIF \
-state_machine_un15_clk_000_d0_0_n
+.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_161
11 1
-.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF N_164
+.names AS_030_c_i.BLIF N_67.BLIF N_193_0
11 1
-.names BGACK_000_c.BLIF N_76.BLIF state_machine_un6_bgack_000_0_n
+.names CLK_030_H_i.BLIF N_203.BLIF N_141
11 1
-.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167
-11 1
-.names a_i_24__n.BLIF a_i_25__n.BLIF N_225_1
-11 1
-.names N_167.BLIF cpu_est_i_3__n.BLIF N_168
-11 1
-.names a_i_26__n.BLIF a_i_27__n.BLIF N_225_2
-11 1
-.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_169
-11 1
-.names a_i_28__n.BLIF a_i_29__n.BLIF N_225_3
-11 1
-.names inst_CLK_000_D3.BLIF CLK_000_D4_i.BLIF N_170
-11 1
-.names a_i_30__n.BLIF a_i_31__n.BLIF N_225_4
-11 1
-.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_171
-11 1
-.names N_225_1.BLIF N_225_2.BLIF N_225_5
-11 1
-.names LDS_000_i.BLIF UDS_000_i.BLIF N_172
-11 1
-.names N_225_3.BLIF N_225_4.BLIF N_225_6
-11 1
-.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_173
-11 1
-.names a_c_20__n.BLIF a_c_21__n.BLIF N_228_1
-11 1
-.names N_225_5.BLIF N_225_6.BLIF N_225
-11 1
-.names a_c_22__n.BLIF a_c_23__n.BLIF N_228_2
-11 1
-.names N_228_1.BLIF N_228_2.BLIF N_228
-11 1
-.names a_c_17__n.BLIF BGACK_000_c.BLIF N_69_i_1
-11 1
-.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+.names N_204.BLIF N_204_i
0 1
-.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_69_i_2
+.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_139
11 1
-.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
-.names a_i_19__n.BLIF a_i_16__n.BLIF N_69_i_3
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_135
11 1
-.names CLK_030_c.BLIF CLK_030_i
-0 1
-.names N_69_i_1.BLIF N_69_i_2.BLIF N_69_i_4
+.names N_204_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF \
+state_machine_un12_clk_000_d0_0_n
11 1
-.names cpu_est_3_reg.BLIF cpu_est_i_3__n
-0 1
-.names N_69_i_3.BLIF a_i_18__n.BLIF N_69_i_5
+.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_134
11 1
-.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
-0 1
-.names N_150_i.BLIF AS_000_i.BLIF state_machine_un8_bgack_030_int_i_0_0_1_n
+.names CLK_000_D2_i.BLIF AS_030_000_SYNC_i.BLIF N_69_i_1
11 1
-.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
-0 1
-.names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF N_72_0_1
+.names N_66.BLIF sm_amiga_i_3__n.BLIF N_131
11 1
-.names inst_CLK_000_D4.BLIF CLK_000_D4_i
-0 1
-.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_51_0_1
+.names BGACK_000_c.BLIF a_i_19__n.BLIF N_76_i_1
11 1
-.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
-0 1
-.names N_74.BLIF N_140_i.BLIF N_51_0_2
+.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_130
11 1
-.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
-0 1
-.names N_133_i.BLIF N_134_i.BLIF cpu_est_ns_0_1_1__n
+.names a_i_16__n.BLIF a_i_18__n.BLIF N_76_i_2
11 1
-.names AS_000_c.BLIF AS_000_i
-0 1
-.names N_167_i.BLIF N_169_i.BLIF cpu_est_ns_0_2_1__n
+.names LDS_000_i.BLIF UDS_000_i.BLIF N_171
11 1
-.names LDS_000_c.BLIF LDS_000_i
-0 1
-.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_128_1
+.names a_c_17__n.BLIF fc_c_0__n.BLIF N_76_i_3
11 1
-.names UDS_000_c.BLIF UDS_000_i
+.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
0 1
-.names N_61.BLIF SM_AMIGA_3_.BLIF N_128_2
+.names N_76_i_1.BLIF N_76_i_2.BLIF N_76_i_4
11 1
-.names cpu_est_1_.BLIF cpu_est_i_1__n
+.names N_197_0.BLIF N_197
0 1
-.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_118_1
+.names N_76_i_3.BLIF fc_c_1__n.BLIF N_76_i_5
11 1
-.names cpu_est_0_.BLIF cpu_est_i_0__n
-0 1
-.names N_69.BLIF SM_AMIGA_7_.BLIF N_118_2
+.names inst_CLK_000_D0.BLIF N_199.BLIF N_119
11 1
-.names inst_DTACK_D0.BLIF DTACK_D0_i
-0 1
-.names N_118_1.BLIF N_118_2.BLIF N_118_3
+.names a_c_20__n.BLIF a_c_21__n.BLIF N_220_1
11 1
-.names inst_VMA_INTreg.BLIF VMA_INT_i
+.names N_194_0.BLIF N_194
0 1
-.names AS_030_c.BLIF CLK_000_c.BLIF N_206_1
+.names a_c_22__n.BLIF a_c_23__n.BLIF N_220_2
11 1
-.names inst_VPA_D.BLIF VPA_D_i
+.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
0 1
-.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_206_2
+.names a_i_24__n.BLIF a_i_25__n.BLIF N_230_1
11 1
-.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+.names N_143_2.BLIF N_143_2_i
0 1
-.names N_146_i.BLIF N_123_i.BLIF sm_amiga_ns_0_1_0__n
-11 1
-.names inst_CLK_030_H.BLIF CLK_030_H_i
-0 1
-.names N_144_i.BLIF N_142_i.BLIF cpu_est_ns_0_1_2__n
-11 1
-.names RW_c.BLIF RW_i
-0 1
-.names N_141_i.BLIF RW_i.BLIF N_53_0_1
-11 1
-.names cpu_est_2_.BLIF cpu_est_i_2__n
-0 1
-.names N_78.BLIF N_132_i.BLIF N_43_i_1
-11 1
-.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
-0 1
-.names N_120_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n
-11 1
-.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
-0 1
-.names N_66_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n
-11 1
-.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
-0 1
-.names N_116_i.BLIF AS_030_c_i.BLIF N_199_0_1
-11 1
-.names A0_c.BLIF A0_i
-0 1
-.names N_82_i.BLIF VMA_INT_i.BLIF N_152_1
-11 1
-.names size_c_1__n.BLIF size_i_1__n
-0 1
-.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_147_1
-11 1
-.names DS_030_c.BLIF DS_030_i
-0 1
-.names N_74_i.BLIF inst_BGACK_030_INT_D.BLIF N_139_1
-11 1
-.names a_c_19__n.BLIF a_i_19__n
-0 1
-.names N_173.BLIF RW_c.BLIF N_137_1
-11 1
-.names a_c_16__n.BLIF a_i_16__n
-0 1
-.names N_61.BLIF CLK_000_D0_i.BLIF N_127_1
+.names a_i_26__n.BLIF a_i_27__n.BLIF N_230_2
11 1
.names a_c_18__n.BLIF a_i_18__n
0 1
-.names A0_i.BLIF size_c_0__n.BLIF N_120_1
+.names a_i_28__n.BLIF a_i_29__n.BLIF N_230_3
11 1
-.names a_c_30__n.BLIF a_i_30__n
+.names a_c_16__n.BLIF a_i_16__n
+0 1
+.names a_i_30__n.BLIF a_i_31__n.BLIF N_230_4
+11 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names N_230_1.BLIF N_230_2.BLIF N_230_5
+11 1
+.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names N_230_3.BLIF N_230_4.BLIF N_230_6
+11 1
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names N_136_i.BLIF N_137_i.BLIF cpu_est_ns_0_1_1__n
+11 1
+.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
+0 1
+.names N_167_i.BLIF N_170_i.BLIF cpu_est_ns_0_2_1__n
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
+.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_122_1
+11 1
+.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
+0 1
+.names N_76.BLIF SM_AMIGA_7_.BLIF N_122_2
+11 1
+.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+0 1
+.names N_122_1.BLIF N_122_2.BLIF N_122_3
+11 1
+.names RW_c.BLIF RW_i
+0 1
+.names AS_030_c.BLIF CLK_000_c.BLIF N_115_1
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_H_i
+0 1
+.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_115_2
+11 1
+.names CLK_030_c.BLIF CLK_030_i
+0 1
+.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF \
+state_machine_un10_clk_000_d0_1_n
+11 1
+.names inst_DTACK_D0.BLIF DTACK_D0_i
+0 1
+.names N_172.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
+11 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_133_1
+11 1
+.names AS_000_c.BLIF AS_000_i
+0 1
+.names N_63.BLIF SM_AMIGA_3_.BLIF N_133_2
+11 1
+.names UDS_000_c.BLIF UDS_000_i
+0 1
+.names CLK_030_i.BLIF N_143_2.BLIF N_143_1
+11 1
+.names LDS_000_c.BLIF LDS_000_i
+0 1
+.names N_147_i.BLIF N_145_i.BLIF cpu_est_ns_0_1_2__n
+11 1
+.names RW_000_c.BLIF RW_000_i
+0 1
+.names N_143_2.BLIF N_144_i.BLIF N_55_0_1
+11 1
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names N_124_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n
+11 1
+.names cpu_est_3_reg.BLIF cpu_est_i_3__n
+0 1
+.names N_70_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n
+11 1
+.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+0 1
+.names N_118_i.BLIF AS_030_c_i.BLIF N_196_0_1
+11 1
+.names inst_CLK_000_D2.BLIF CLK_000_D2_i
+0 1
+.names N_90_i.BLIF VMA_INT_i.BLIF N_155_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_148_1
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
+.names N_79.BLIF RW_i.BLIF N_142_1
+11 1
+.names inst_VMA_INTreg.BLIF VMA_INT_i
+0 1
+.names N_166.BLIF RW_c.BLIF N_140_1
+11 1
+.names inst_VPA_D.BLIF VPA_D_i
+0 1
+.names N_63.BLIF CLK_000_D0_i.BLIF N_132_1
+11 1
+.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+0 1
+.names A0_i.BLIF size_c_0__n.BLIF N_124_1
+11 1
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n
11 1
+.names cpu_est_2_.BLIF cpu_est_i_2__n
+0 1
+.names CLK_030_i.BLIF N_62.BLIF N_120_1
+11 1
+.names A0_c.BLIF A0_i
+0 1
+.names DS_030_i.BLIF N_66_i.BLIF N_118_1
+11 1
+.names size_c_1__n.BLIF size_i_1__n
+0 1
+.names DS_030_i.BLIF N_67_i.BLIF N_117_1
+11 1
+.names DS_030_c.BLIF DS_030_i
+0 1
+.names N_71.BLIF inst_BGACK_030_INT_D.BLIF N_116_1
+11 1
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
+11 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names CLK_000_D0_i.BLIF N_170.BLIF N_204_1
+11 1
.names a_c_31__n.BLIF a_i_31__n
0 1
-.names DS_030_i.BLIF N_62_i.BLIF N_116_1
-11 1
-.names a_c_28__n.BLIF a_i_28__n
-0 1
-.names DS_030_i.BLIF N_64_i.BLIF N_115_1
-11 1
-.names a_c_29__n.BLIF a_i_29__n
-0 1
-.names cpu_est_2_.BLIF N_164.BLIF state_machine_un13_clk_000_d0_1_n
-11 1
-.names a_c_26__n.BLIF a_i_26__n
-0 1
-.names CLK_000_D0_i.BLIF N_169.BLIF N_203_1
-11 1
-.names a_c_27__n.BLIF a_i_27__n
-0 1
-.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n
-0 1
-.names a_c_24__n.BLIF a_i_24__n
-0 1
-.names N_64.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n
-11 1
-.names a_c_25__n.BLIF a_i_25__n
-0 1
-.names N_62.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
-state_machine_uds_000_int_7_0_m3_un0_n
-11 1
-.names RST_c.BLIF RST_i
-0 1
-.names N_65.BLIF dsack1_int_0_un3_n
-0 1
-.names N_205_i.BLIF N_65.BLIF dsack1_int_0_un1_n
-11 1
-.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
-11 1
-.names N_205.BLIF N_205_i
-0 1
-.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n
-0 1
-.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
-0 1
-.names state_machine_un13_clk_000_d0_n.BLIF \
-state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n
-11 1
-.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
-0 1
-.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
-11 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
11 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
-.names N_76.BLIF ipl_030_0_0__un3_n
+.names a_c_26__n.BLIF a_i_26__n
0 1
-.names IPL_030DFFSH_0_reg.BLIF N_76.BLIF ipl_030_0_0__un1_n
+.names N_194.BLIF as_000_dma_0_un3_n
+0 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names N_143_2_i.BLIF N_194.BLIF as_000_dma_0_un1_n
+11 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
+.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
+11 1
+.names a_c_25__n.BLIF a_i_25__n
+0 1
+.names N_55.BLIF ds_000_dma_0_un3_n
+0 1
+.names RST_c.BLIF RST_i
+0 1
+.names state_machine_ds_000_dma_3_n.BLIF N_55.BLIF ds_000_dma_0_un1_n
+11 1
+.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+11 1
+.names RST_c.BLIF clk_030_h_0_un3_n
+0 1
+.names N_114.BLIF N_114_i
+0 1
+.names N_52_i.BLIF RST_c.BLIF clk_030_h_0_un1_n
+11 1
+.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
+0 1
+.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
+11 1
+.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
+0 1
+.names N_197.BLIF rw_000_int_0_un3_n
+0 1
+.names state_machine_rw_000_int_7_iv_i_n.BLIF N_197.BLIF rw_000_int_0_un1_n
+11 1
+.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
+11 1
+.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n
+0 1
+.names N_67.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n
+11 1
+.names N_66.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \
+state_machine_uds_000_int_7_0_m3_un0_n
+11 1
+.names N_77.BLIF ipl_030_0_0__un3_n
+0 1
+.names IPL_030DFFSH_0_reg.BLIF N_77.BLIF ipl_030_0_0__un1_n
11 1
.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
-.names N_76.BLIF ipl_030_0_1__un3_n
+.names N_77.BLIF ipl_030_0_1__un3_n
0 1
-.names IPL_030DFFSH_1_reg.BLIF N_76.BLIF ipl_030_0_1__un1_n
+.names IPL_030DFFSH_1_reg.BLIF N_77.BLIF ipl_030_0_1__un1_n
11 1
.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
11 1
-.names N_76.BLIF ipl_030_0_2__un3_n
+.names N_77.BLIF ipl_030_0_2__un3_n
0 1
-.names IPL_030DFFSH_2_reg.BLIF N_76.BLIF ipl_030_0_2__un1_n
+.names IPL_030DFFSH_2_reg.BLIF N_77.BLIF ipl_030_0_2__un1_n
11 1
.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
11 1
-.names N_76.BLIF cpu_estse_0_un3_n
+.names N_77.BLIF cpu_estse_0_un3_n
0 1
-.names cpu_est_1_.BLIF N_76.BLIF cpu_estse_0_un1_n
+.names cpu_est_1_.BLIF N_77.BLIF cpu_estse_0_un1_n
11 1
.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
11 1
-.names N_76.BLIF cpu_estse_1_un3_n
+.names N_77.BLIF cpu_estse_1_un3_n
0 1
-.names cpu_est_2_.BLIF N_76.BLIF cpu_estse_1_un1_n
+.names cpu_est_2_.BLIF N_77.BLIF cpu_estse_1_un1_n
11 1
.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
11 1
-.names N_76.BLIF cpu_estse_2_un3_n
+.names N_77.BLIF cpu_estse_2_un3_n
0 1
-.names cpu_est_3_reg.BLIF N_76.BLIF cpu_estse_2_un1_n
+.names cpu_est_3_reg.BLIF N_77.BLIF cpu_estse_2_un1_n
11 1
-.names N_151_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
+.names N_149_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
11 1
-.names N_51.BLIF amiga_bus_enable_0_un3_n
+.names N_30.BLIF as_030_000_sync_0_un3_n
0 1
-.names state_machine_amiga_bus_enable_4_iv_i_n.BLIF N_51.BLIF \
-amiga_bus_enable_0_un1_n
-11 1
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF amiga_bus_enable_0_un3_n.BLIF \
-amiga_bus_enable_0_un0_n
-11 1
-.names N_201.BLIF as_030_000_sync_0_un3_n
-0 1
-.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_201.BLIF as_030_000_sync_0_un1_n
+.names un1_DSACK1_INT_0_sqmuxa_3.BLIF N_30.BLIF as_030_000_sync_0_un1_n
11 1
.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \
as_030_000_sync_0_un0_n
11 1
-.names RST_c.BLIF clk_030_h_0_un3_n
+.names N_196.BLIF uds_000_int_0_un3_n
0 1
-.names N_48_i.BLIF RST_c.BLIF clk_030_h_0_un1_n
-11 1
-.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
-11 1
-.names N_199.BLIF uds_000_int_0_un3_n
-0 1
-.names state_machine_uds_000_int_7_n.BLIF N_199.BLIF uds_000_int_0_un1_n
+.names state_machine_uds_000_int_7_n.BLIF N_196.BLIF uds_000_int_0_un1_n
11 1
.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
11 1
-.names N_199.BLIF lds_000_int_0_un3_n
+.names N_196.BLIF lds_000_int_0_un3_n
0 1
-.names state_machine_lds_000_int_7_n.BLIF N_199.BLIF lds_000_int_0_un1_n
+.names state_machine_lds_000_int_7_n.BLIF N_196.BLIF lds_000_int_0_un1_n
11 1
.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
11 1
-.names N_200.BLIF fpu_cs_int_0_un3_n
+.names N_28.BLIF fpu_cs_int_0_un3_n
0 1
-.names AS_030_c.BLIF N_200.BLIF fpu_cs_int_0_un1_n
+.names AS_030_c.BLIF N_28.BLIF fpu_cs_int_0_un1_n
11 1
.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
+.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n
+0 1
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \
+avec_exp_0_un1_n
+11 1
+.names N_195_i.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n
+11 1
.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
-.names N_53.BLIF ds_000_dma_0_un3_n
+.names N_193.BLIF as_000_int_0_un3_n
0 1
-.names state_machine_ds_000_dma_3_n.BLIF N_53.BLIF ds_000_dma_0_un1_n
-11 1
-.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
-11 1
-.names N_198.BLIF as_000_dma_0_un3_n
-0 1
-.names state_machine_un8_bgack_030_int_i_0_n.BLIF N_198.BLIF \
-as_000_dma_0_un1_n
-11 1
-.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
-11 1
-.names N_197.BLIF as_000_int_0_un3_n
-0 1
-.names N_64.BLIF N_197.BLIF as_000_int_0_un1_n
+.names N_67.BLIF N_193.BLIF as_000_int_0_un1_n
11 1
.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
+.names N_75.BLIF dsack1_int_0_un3_n
+0 1
+.names N_114_i.BLIF N_75.BLIF dsack1_int_0_un1_n
+11 1
+.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
+11 1
+.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
+0 1
+.names state_machine_un10_clk_000_d0_n.BLIF \
+state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
+11 1
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+11 1
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
@@ -1071,7 +1074,7 @@ as_000_dma_0_un1_n
.names vcc_n_n.BLIF AVEC
1 1
0 0
-.names gnd_n_n.BLIF AVEC_EXP
+.names inst_avec_expreg.BLIF AVEC_EXP
1 1
0 0
.names cpu_est_3_reg.BLIF E
@@ -1083,7 +1086,7 @@ as_000_dma_0_un1_n
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
-.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE
+.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
@@ -1092,7 +1095,7 @@ as_000_dma_0_un1_n
.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
-.names N_228.BLIF CIIN
+.names N_220.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
@@ -1230,12 +1233,6 @@ as_000_dma_0_un1_n
.names RST_i.BLIF SIZE_DMA_0_.AP
1 1
0 0
-.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
-1 1
-0 0
-.names RST_i.BLIF inst_UDS_000_INT.AP
-1 1
-0 0
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
1 1
0 0
@@ -1248,6 +1245,12 @@ as_000_dma_0_un1_n
.names RST_i.BLIF inst_FPU_CS_INTreg.AP
1 1
0 0
+.names CLK_OSZI_c.BLIF inst_avec_expreg.C
+1 1
+0 0
+.names RST_i.BLIF inst_avec_expreg.AP
+1 1
+0 0
.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
1 1
0 0
@@ -1272,10 +1275,10 @@ as_000_dma_0_un1_n
.names RST_i.BLIF inst_AS_000_INT.AP
1 1
0 0
-.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFSHreg.C
+.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
1 1
0 0
-.names RST_i.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP
+.names RST_i.BLIF inst_RW_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
@@ -1287,21 +1290,18 @@ as_000_dma_0_un1_n
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
1 1
0 0
+.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
+1 1
+0 0
+.names RST_i.BLIF inst_UDS_000_INT.AP
+1 1
+0 0
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
1 1
0 0
.names RST_i.BLIF inst_A0_DMA.AP
1 1
0 0
-.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
-1 1
-0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C
-1 1
-0 0
-.names RST_i.BLIF inst_CLK_000_D4.AP
-1 1
-0 0
.names DTACK.PIN.BLIF inst_DTACK_D0.D
1 1
0 0
@@ -1311,15 +1311,6 @@ as_000_dma_0_un1_n
.names RST_i.BLIF inst_DTACK_D0.AP
1 1
0 0
-.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
-1 1
-0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
-1 1
-0 0
-.names RST_i.BLIF inst_CLK_000_D3.AP
-1 1
-0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
@@ -1338,6 +1329,15 @@ as_000_dma_0_un1_n
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
0 0
+.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
+1 1
+0 0
+.names RST_i.BLIF inst_CLK_000_D3.AP
+1 1
+0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
@@ -1401,15 +1401,15 @@ as_000_dma_0_un1_n
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
-.names inst_DSACK1_INT.BLIF DSACK_1_
-1 1
-0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
@@ -1422,13 +1422,22 @@ as_000_dma_0_un1_n
.names inst_A0_DMA.BLIF A0
1 1
0 0
-.names dsack_c_1__n.BLIF DTACK
+.names inst_DSACK1_INT.BLIF DSACK1
+1 1
+0 0
+.names DSACK1_c.BLIF DTACK
+1 1
+0 0
+.names inst_RW_000_INT.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
-.names vcc_n_n.BLIF DSACK_0_
+.names BG_030.BLIF BG_030_c
+1 1
+0 0
+.names BGACK_000.BLIF BGACK_000_c
1 1
0 0
.names CLK_030.BLIF CLK_030_c
@@ -1449,13 +1458,13 @@ as_000_dma_0_un1_n
.names IPL_2_.BLIF ipl_c_2__n
1 1
0 0
-.names DSACK_1_.PIN.BLIF dsack_c_1__n
+.names DSACK1.PIN.BLIF DSACK1_c
1 1
0 0
.names RST.BLIF RST_c
1 1
0 0
-.names RW.BLIF RW_c
+.names RW.PIN.BLIF RW_c
1 1
0 0
.names FC_0_.BLIF fc_c_0__n
@@ -1470,6 +1479,9 @@ as_000_dma_0_un1_n
.names AS_000.PIN.BLIF AS_000_c
1 1
0 0
+.names RW_000.PIN.BLIF RW_000_c
+1 1
+0 0
.names DS_030.PIN.BLIF DS_030_c
1 1
0 0
@@ -1539,19 +1551,16 @@ as_000_dma_0_un1_n
.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
-.names BG_030.BLIF BG_030_c
-1 1
-0 0
-.names BGACK_000.BLIF BGACK_000_c
-1 1
-0 0
-.names N_147.BLIF AS_030.OE
+.names N_148.BLIF AS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
-.names N_147.BLIF DS_030.OE
+.names inst_BGACK_030_INTreg.BLIF RW_000.OE
+1 1
+0 0
+.names N_148.BLIF DS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
@@ -1560,34 +1569,32 @@ as_000_dma_0_un1_n
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
-.names N_147.BLIF SIZE_0_.OE
+.names N_148.BLIF SIZE_0_.OE
1 1
0 0
-.names N_147.BLIF SIZE_1_.OE
+.names N_148.BLIF SIZE_1_.OE
1 1
0 0
-.names N_147.BLIF A0.OE
+.names N_148.BLIF A0.OE
1 1
0 0
-.names nEXP_SPACE_c.BLIF DSACK_1_.OE
+.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
0 0
-.names N_147.BLIF DTACK.OE
+.names N_148.BLIF DTACK.OE
+1 1
+0 0
+.names BGACK_030_INT_i.BLIF RW.OE
1 1
0 0
.names FPU_CS_INT_i.BLIF BERR.OE
1 1
0 0
-.names nEXP_SPACE_c.BLIF DSACK_0_.OE
+.names N_230.BLIF CIIN.OE
1 1
0 0
-.names FPU_CS_INT_i.BLIF AVEC_EXP.OE
-1 1
-0 0
-.names N_225.BLIF CIIN.OE
-1 1
-0 0
-.names inst_CLK_OUT_PRE_25.BLIF clk_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0
+.names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
+CLK_OUT_PRE_25_0
01 1
10 1
11 0
diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi
index fbedc5e..54cd165 100644
--- a/Logic/BUS68030.edi
+++ b/Logic/BUS68030.edi
@@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
- (timeStamp 2014 5 29 22 4 22)
+ (timeStamp 2014 6 1 1 3 19)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R"))
)
@@ -122,10 +122,10 @@
(port (array (rename a "A(31:16)") 16) (direction INPUT))
(port (array (rename ipl_030 "IPL_030(2:0)") 3) (direction OUTPUT))
(port (array (rename ipl "IPL(2:0)") 3) (direction INPUT))
- (port (array (rename dsack "DSACK(1:0)") 2) (direction INOUT))
(port (array (rename fc "FC(1:0)") 2) (direction INPUT))
(port AS_030 (direction INOUT))
(port AS_000 (direction INOUT))
+ (port RW_000 (direction INOUT))
(port DS_030 (direction INOUT))
(port UDS_000 (direction INOUT))
(port LDS_000 (direction INOUT))
@@ -142,6 +142,7 @@
(port CLK_DIV_OUT (direction OUTPUT))
(port CLK_EXP (direction OUTPUT))
(port FPU_CS (direction OUTPUT))
+ (port DSACK1 (direction INOUT))
(port DTACK (direction INOUT))
(port AVEC (direction OUTPUT))
(port AVEC_EXP (direction OUTPUT))
@@ -150,7 +151,7 @@
(port VMA (direction OUTPUT))
(port RST (direction INPUT))
(port RESET (direction OUTPUT))
- (port RW (direction INPUT))
+ (port RW (direction INOUT))
(port AMIGA_BUS_ENABLE (direction OUTPUT))
(port AMIGA_BUS_DATA_DIR (direction OUTPUT))
(port AMIGA_BUS_ENABLE_LOW (direction OUTPUT))
@@ -199,12 +200,12 @@
)
(instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
- (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach)))
- )
(instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
(instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
+ (instance avec_exp (viewRef prim (cellRef DFFSH (libraryRef mach)))
+ )
(instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
(instance DS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach)))
@@ -213,24 +214,24 @@
)
(instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
- (instance AMIGA_BUS_ENABLEDFFSH (viewRef prim (cellRef DFFSH (libraryRef mach)))
+ (instance RW_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
(instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
(instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach)))
)
+ (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach)))
+ )
(instance A0_DMA (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
- (instance CLK_000_D4 (viewRef prim (cellRef DFFSH (libraryRef mach)))
- )
(instance DTACK_D0 (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
- (instance CLK_000_D3 (viewRef prim (cellRef DFFSH (libraryRef mach)))
- )
(instance CLK_000_D2 (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
(instance CLK_OUT_INT (viewRef prim (cellRef DFFRH (libraryRef mach)))
)
+ (instance CLK_000_D3 (viewRef prim (cellRef DFFSH (libraryRef mach)))
+ )
(instance CLK_000_D1 (viewRef prim (cellRef DFFSH (libraryRef mach)))
)
(instance BGACK_030_INT_D (viewRef prim (cellRef DFFSH (libraryRef mach)))
@@ -247,6 +248,7 @@
)
(instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
+ (instance RW_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance DS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance UDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance LDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
@@ -287,309 +289,316 @@
(instance (rename IPL_0 "IPL[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance (rename IPL_1 "IPL[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance (rename IPL_2 "IPL[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
- (instance (rename DSACK_0 "DSACK[0]") (viewRef prim (cellRef BUFTH (libraryRef mach))) )
- (instance (rename DSACK_1 "DSACK[1]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
+ (instance DSACK1 (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance DTACK (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance AVEC (viewRef prim (cellRef OBUF (libraryRef mach))) )
- (instance AVEC_EXP (viewRef prim (cellRef BUFTH (libraryRef mach))) )
+ (instance (rename AVEC_EXPZ0 "AVEC_EXP") (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance E (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance VPA (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance VMA (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance RST (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance RESET (viewRef prim (cellRef OBUF (libraryRef mach))) )
- (instance RW (viewRef prim (cellRef IBUF (libraryRef mach))) )
+ (instance RW (viewRef prim (cellRef BI_DIR (libraryRef mach))) )
(instance (rename FC_0 "FC[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance (rename FC_1 "FC[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance AMIGA_BUS_ENABLE (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) )
- (instance (rename state_machine_A0_DMA_2_0_a3_1 "state_machine.A0_DMA_2_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_A0_DMA_2_0_a3 "state_machine.A0_DMA_2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un1_AS_030_2_i_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un1_AS_030_2_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un1_AS_030_2_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un1_AS_030_2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d0_0_a3_0_1 "state_machine.un15_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d0_0_a3_0 "state_machine.un15_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d0_0_a3_1 "state_machine.un15_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d0_0_a3 "state_machine.un15_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_AS_030_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0_a3_1 "state_machine.un12_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0_a3 "state_machine.un12_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un1_AS_030_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_i_a2_1_4 "SM_AMIGA_ns_i_a2_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un3_dtack_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un3_dtack_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3_1 "state_machine.AMIGA_BUS_ENABLE_4_iv_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3 "state_machine.AMIGA_BUS_ENABLE_4_iv_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_a3_1 "state_machine.RW_000_INT_7_iv_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_a3 "state_machine.RW_000_INT_7_iv_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance AMIGA_BUS_DATA_DIR_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance AMIGA_BUS_DATA_DIR_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_i_a3_0_1_4 "SM_AMIGA_ns_i_a3_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_i_a3_0_4 "SM_AMIGA_ns_i_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_LDS_000_INT_7_0_a3_1 "state_machine.LDS_000_INT_7_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_LDS_000_INT_7_0_a3 "state_machine.LDS_000_INT_7_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un10_bg_030_0_a3_1 "state_machine.un10_bg_030_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un10_bg_030_0_a3_2 "state_machine.un10_bg_030_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un10_bg_030_0_a3 "state_machine.un10_bg_030_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_A0_DMA_2_0_a3_1 "state_machine.A0_DMA_2_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_A0_DMA_2_0_a3 "state_machine.A0_DMA_2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0_a3_0 "state_machine.un12_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_a3_1_5 "SM_AMIGA_ns_0_a3_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_a3_2_5 "SM_AMIGA_ns_0_a3_2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_a3_5 "SM_AMIGA_ns_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_a3_0_1 "state_machine.RW_000_INT_7_iv_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_a3_0 "state_machine.RW_000_INT_7_iv_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_ns_0_0_1_2 "cpu_est_ns_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_ns_0_0_2 "cpu_est_ns_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance DS_000_DMA_1_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance DS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_1_7 "SM_AMIGA_ns_i_1[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_LDS_000_INT_7_0_1 "state_machine.LDS_000_INT_7_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_UDS_000_INT_7_0_1 "state_machine.UDS_000_INT_7_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_000_DMA_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_1_1 "SM_AMIGA_ns_i_o2_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_1 "SM_AMIGA_ns_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_1_1 "cpu_est_ns_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_2_1 "cpu_est_ns_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_1 "cpu_est_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a3_1_5 "SM_AMIGA_ns_0_a3_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a3_2_5 "SM_AMIGA_ns_0_a3_2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a3_5 "SM_AMIGA_ns_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_AS_030_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_1_1 "cpu_est_ns_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_2_1 "cpu_est_ns_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_1 "cpu_est_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un10_bg_030_0_a3_1 "state_machine.un10_bg_030_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un10_bg_030_0_a3_2 "state_machine.un10_bg_030_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un10_bg_030_0_a3 "state_machine.un10_bg_030_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0_a3_0_1 "state_machine.un12_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0_a3_0_2 "state_machine.un12_clk_000_d0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_o2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_000_DMA_1_sqmuxa_i_o3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_as_030_000_sync8_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance un1_AS_030_2_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un10_bg_030_0_i "state_machine.un10_bg_030_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_000_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_203_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d0_0_i "state_machine.un15_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_172_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_SIZE_DMA_4_0_i_1 "state_machine.SIZE_DMA_4_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_DS_000_DMA_3_0_i "state_machine.DS_000_DMA_3_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_66_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_LDS_000_INT_7_0_i "state_machine.LDS_000_INT_7_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_7_0_i "state_machine.UDS_000_INT_7_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_as_030_000_sync8_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_136_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_i_i_6 "SM_AMIGA_ns_i_i_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_149_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_AS_030_2_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un10_bg_030_0_i "state_machine.un10_bg_030_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_000_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_204_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0_i "state_machine.un12_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename cpu_est_ns_0_0_i_2 "cpu_est_ns_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance DS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_i_o2_i_6 "SM_AMIGA_ns_i_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_un3_clk_000_d1_0_o2_i "clk.un3_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_i_1 "SM_AMIGA_ns_i_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_000_DMA_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_172_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_70_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_LDS_000_INT_7_0_i "state_machine.LDS_000_INT_7_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_7_0_i "state_machine.UDS_000_INT_7_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_136_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_o2_i_1 "SM_AMIGA_ns_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_o2_i_2 "SM_AMIGA_ns_a2_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_DSACK1_INT_0_sqmuxa_3_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_i_0_o2_i_3 "cpu_est_ns_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance AS_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance DSACK1_INT_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance AS_000_INT_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_i_o2_0_i_4 "SM_AMIGA_ns_i_o2_0_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_152_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_i_1 "cpu_est_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un3_clk_000_d1_0_o2_i "state_machine.un3_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_o2_i "state_machine.RW_000_INT_7_iv_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_o2_i_6 "SM_AMIGA_ns_a2_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename state_machine_CLK_030_H_2_f0_i_o2_i "state_machine.CLK_030_H_2_f0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_0_i_1 "SM_AMIGA_ns_i_o2_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_i_1 "cpu_est_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_SIZE_DMA_4_0_i_1 "state_machine.SIZE_DMA_4_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_DS_000_DMA_3_0_i "state_machine.DS_000_DMA_3_0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_171_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_ns_i_0_o2_i_3 "cpu_est_ns_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_i_7 "SM_AMIGA_ns_i_o2_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_000_INT_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance DSACK1_INT_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_7_0_m3_r "state_machine.UDS_000_INT_7_0_m3.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_7_0_m3_m "state_machine.UDS_000_INT_7_0_m3.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_7_0_m3_n "state_machine.UDS_000_INT_7_0_m3.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_7_0_m3_p "state_machine.UDS_000_INT_7_0_m3.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_un3_clk_000_d1_0_o2 "clk.un3_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_i_o2_6 "SM_AMIGA_ns_i_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_7 "SM_AMIGA_ns_i_o2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_ns_i_0_o2_3 "cpu_est_ns_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_0_1 "SM_AMIGA_ns_i_o2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_CLK_030_H_2_f0_i_o2 "state_machine.CLK_030_H_2_f0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_0_2 "SM_AMIGA_ns_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_i_6 "SM_AMIGA_ns_i_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_i_0_3 "cpu_est_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_CLK_030_H_2_f0_i "state_machine.CLK_030_H_2_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_AMIGA_BUS_ENABLE_4_iv_0 "state_machine.AMIGA_BUS_ENABLE_4_iv_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance cpu_estse_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_0_4 "SM_AMIGA_ns_i_o2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance CLK_000_D4_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance I_144 (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance I_145 (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_SIZE_DMA_4_0_a2_1 "state_machine.SIZE_DMA_4_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance I_143 (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_A0_DMA_2_0_a2 "state_machine.A0_DMA_2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_000_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_as_030_000_sync8_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_000_SYNC_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance cpu_estse_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance cpu_estse_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_000_DMA_1_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_7 "SM_AMIGA_ns_i_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a2_1 "cpu_est_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_i_0_a2_3 "cpu_est_ns_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a2_0_1 "cpu_est_ns_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_DSACK1_INT_0_sqmuxa_i_o3_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a3_0_1 "cpu_est_ns_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_i_0_a3_3 "cpu_est_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AMIGA_BUS_DATA_DIR_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_CLK_030_H_2_f0_i_a3 "state_machine.CLK_030_H_2_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AMIGA_BUS_ENABLE_0_sqmuxa_2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance DS_000_DMA_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a3_2 "cpu_est_ns_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a3_0_2 "cpu_est_ns_0_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a3_1_2 "cpu_est_ns_0_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a3_0 "SM_AMIGA_ns_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a3_0_0 "SM_AMIGA_ns_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance I_147 (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_SIZE_DMA_4_i_a3_0 "state_machine.SIZE_DMA_4_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a3_1 "SM_AMIGA_ns_i_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a3_0_1 "SM_AMIGA_ns_i_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_0_a3_2 "SM_AMIGA_ns_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a3_4 "SM_AMIGA_ns_i_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_i_a3_6 "SM_AMIGA_ns_i_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_i_a3_0_6 "SM_AMIGA_ns_i_i_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a3_7 "SM_AMIGA_ns_i_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_ns_0_0_a3_1 "cpu_est_ns_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) )
- (instance un1_DSACK1_INT_0_sqmuxa_i_o3_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance I_148 (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance un1_as_030_000_sync8_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance I_146 (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_205_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance N_143_2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename CLK_030_H_0_r "CLK_030_H_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename CLK_030_H_0_m "CLK_030_H_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename CLK_030_H_0_n "CLK_030_H_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename CLK_030_H_0_p "CLK_030_H_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_a3_7 "SM_AMIGA_ns_i_0_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a3_4 "SM_AMIGA_ns_i_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_a3_0 "SM_AMIGA_ns_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_a3_6 "SM_AMIGA_ns_a2_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_SIZE_DMA_4_i_a3_0 "state_machine.SIZE_DMA_4_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance N_98_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance I_143 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance I_144 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_SIZE_DMA_4_0_a2_1 "state_machine.SIZE_DMA_4_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance I_142 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance DS_000_DMA_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_CLK_030_H_2_f0_i_a3 "state_machine.CLK_030_H_2_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance I_141 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AMIGA_BUS_DATA_DIR_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un3_clk_000_d1_0_o2 "state_machine.un3_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_0_4 "SM_AMIGA_ns_i_o2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0 "state_machine.RW_000_INT_7_iv_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_CLK_030_H_2_f0_i "state_machine.CLK_030_H_2_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_7 "SM_AMIGA_ns_i_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance DSACK1_INT_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_i_0_o2_3 "cpu_est_ns_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_DSACK1_INT_0_sqmuxa_3_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_o3_0 "SM_AMIGA_ns_0_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_o2_2 "SM_AMIGA_ns_a2_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_a3_0_2 "state_machine.RW_000_INT_7_iv_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance I_145 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_CLK_030_H_2_f0_i_o2 "state_machine.CLK_030_H_2_f0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_o2_6 "SM_AMIGA_ns_a2_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance RW_000_INT_0_sqmuxa_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_RW_000_INT_7_iv_0_o2 "state_machine.RW_000_INT_7_iv_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_i_0_a2_3 "cpu_est_ns_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un12_clk_000_d0_0 "state_machine.un12_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_000_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bgack_030_int_d_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_as_030_000_sync8_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_1 "SM_AMIGA_ns_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_i_0_3 "cpu_est_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance cpu_estse_i (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_000_INT_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_7_0_m3_r "state_machine.UDS_000_INT_7_0_m3.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_7_0_m3_m "state_machine.UDS_000_INT_7_0_m3.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_7_0_m3_n "state_machine.UDS_000_INT_7_0_m3.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_7_0_m3_p "state_machine.UDS_000_INT_7_0_m3.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a3_2 "cpu_est_ns_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a3_0_2 "cpu_est_ns_0_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a3_1_2 "cpu_est_ns_0_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance cpu_estse_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance cpu_estse_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a2_1 "cpu_est_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_DSACK1_INT_0_sqmuxa_3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a2_0_1 "cpu_est_ns_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) )
+ (instance I_148 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_as_030_000_sync8_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance I_146 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance I_147 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_a3_2 "SM_AMIGA_ns_a2_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0_a3_1 "SM_AMIGA_ns_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a3_1 "cpu_est_ns_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_ns_0_0_a3_0_1 "cpu_est_ns_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_ns_i_0_a3_3 "cpu_est_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
@@ -615,20 +624,12 @@
(instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance CLK_OUT_PRE_50_D_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_un3_clk_out_pre_50 "clk.un3_clk_out_pre_50") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un3_clk_out_pre_50 "state_machine.un3_clk_out_pre_50") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename CLK_030_H_0_r "CLK_030_H_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename CLK_030_H_0_m "CLK_030_H_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename CLK_030_H_0_n "CLK_030_H_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename CLK_030_H_0_p "CLK_030_H_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
@@ -641,34 +642,40 @@
(instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename avec_exp_0_r "avec_exp_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename avec_exp_0_m "avec_exp_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename avec_exp_0_n "avec_exp_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename avec_exp_0_p "avec_exp_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(net BGACK_030_INT (joined
(portRef Q (instanceRef BGACK_030_INT))
- (portRef I0 (instanceRef BGACK_030_INT_0_n))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i))
(portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3))
- (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0))
(portRef I0 (instanceRef BGACK_030_INT_i))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_1))
+ (portRef I0 (instanceRef BGACK_030_INT_0_n))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_1))
+ (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1))
(portRef OE (instanceRef AS_000))
(portRef I0 (instanceRef BGACK_030))
(portRef D (instanceRef BGACK_030_INT_D))
(portRef OE (instanceRef LDS_000))
+ (portRef OE (instanceRef RW_000))
(portRef OE (instanceRef UDS_000))
))
(net FPU_CS_INT (joined
@@ -677,6 +684,12 @@
(portRef I0 (instanceRef FPU_CS_INT_i))
(portRef I0 (instanceRef FPU_CS))
))
+ (net (rename avec_expZ0 "avec_exp") (joined
+ (portRef Q (instanceRef avec_exp))
+ (portRef I0 (instanceRef avec_exp_0_m))
+ (portRef I0 (instanceRef AMIGA_BUS_ENABLE))
+ (portRef I0 (instanceRef AVEC_EXPZ0))
+ ))
(net VMA_INT (joined
(portRef Q (instanceRef VMA_INT))
(portRef I0 (instanceRef VMA_INT_0_n))
@@ -690,19 +703,19 @@
))
(net BGACK_030_INT_D (joined
(portRef Q (instanceRef BGACK_030_INT_D))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_1))
- (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3_1))
+ (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1))
+ (portRef I1 (instanceRef un1_bgack_030_int_d_i_a3_1))
))
(net AS_000_DMA (joined
(portRef Q (instanceRef AS_000_DMA))
- (portRef I0 (instanceRef AS_000_DMA_0_n))
(portRef I0 (instanceRef AS_000_DMA_i))
+ (portRef I0 (instanceRef AS_000_DMA_0_n))
(portRef I0 (instanceRef AS_030))
))
(net VPA_D (joined
(portRef Q (instanceRef VPA_D))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4))
(portRef I0 (instanceRef VPA_D_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4))
))
(net CLK_OUT_PRE_50_D (joined
(portRef Q (instanceRef CLK_OUT_PRE_50_D))
@@ -710,12 +723,15 @@
))
(net CLK_000_D0 (joined
(portRef Q (instanceRef CLK_000_D0))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a3_0_6))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_7))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_a3_2))
(portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_4))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_0_2))
- (portRef I0 (instanceRef clk_un3_clk_000_d1_0_o2))
+ (portRef I0 (instanceRef state_machine_un3_clk_000_d1_0_o2))
+ (portRef I0 (instanceRef N_98_i_i_a3))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a3))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_a3_6))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0))
(portRef I0 (instanceRef CLK_000_D0_i))
+ (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_1))
(portRef D (instanceRef CLK_000_D1))
))
(net CLK_000_D1 (joined
@@ -727,21 +743,17 @@
))
(net CLK_000_D2 (joined
(portRef Q (instanceRef CLK_000_D2))
+ (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_o2))
(portRef I0 (instanceRef CLK_000_D2_i))
(portRef D (instanceRef CLK_000_D3))
))
- (net CLK_000_D4 (joined
- (portRef Q (instanceRef CLK_000_D4))
- (portRef I0 (instanceRef CLK_000_D4_i))
- (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_o2))
- ))
(net DTACK_D0 (joined
(portRef Q (instanceRef DTACK_D0))
(portRef I0 (instanceRef DTACK_D0_i))
))
(net CLK_OUT_PRE_50 (joined
(portRef Q (instanceRef CLK_OUT_PRE_50))
- (portRef I0 (instanceRef clk_un3_clk_out_pre_50))
+ (portRef I0 (instanceRef state_machine_un3_clk_out_pre_50))
(portRef I0 (instanceRef CLK_OUT_PRE_50_i))
(portRef D (instanceRef CLK_OUT_PRE_50_D))
))
@@ -750,48 +762,60 @@
(portRef I0 (instanceRef CLK_OUT_PRE_25_0))
(portRef D (instanceRef CLK_OUT_INT))
))
+ (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined
+ (portRef Q (instanceRef SM_AMIGA_7))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0))
+ (portRef I0 (instanceRef SM_AMIGA_i_7))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2))
+ (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_2))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_2))
+ ))
(net VCC (joined
(portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW))
(portRef I0 (instanceRef AVEC))
- (portRef I0 (instanceRef DSACK_0))
(portRef D (instanceRef RESETDFFRH))
))
(net GND (joined
- (portRef I0 (instanceRef AVEC_EXP))
(portRef I0 (instanceRef BERR))
))
- (net (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0))
+ (net (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_0))
(portRef I0 (instanceRef VMA_INT_0_m))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d0_i))
+ (portRef I0 (instanceRef state_machine_un10_clk_000_d0_i))
))
(net AS_000_INT (joined
(portRef Q (instanceRef AS_000_INT))
(portRef I0 (instanceRef AS_000_INT_0_n))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_7))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_1))
(portRef I0 (instanceRef AS_000))
))
- (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined
- (portRef Q (instanceRef SM_AMIGA_1))
- (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o3_i_a3))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a3_6))
- (portRef I0 (instanceRef SM_AMIGA_i_1))
- ))
- (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined
- (portRef Q (instanceRef SM_AMIGA_0))
- (portRef I0 (instanceRef SM_AMIGA_i_0))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_0))
- ))
(net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined
(portRef Q (instanceRef SM_AMIGA_6))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_1))
(portRef I0 (instanceRef SM_AMIGA_i_6))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3))
+ ))
+ (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined
+ (portRef Q (instanceRef SM_AMIGA_0))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0))
+ (portRef I0 (instanceRef SM_AMIGA_i_0))
))
(net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined
(portRef Q (instanceRef SM_AMIGA_5))
- (portRef I0 (instanceRef SM_AMIGA_i_5))
(portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i_o2))
+ (portRef I0 (instanceRef SM_AMIGA_i_5))
+ ))
+ (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined
+ (portRef Q (instanceRef SM_AMIGA_2))
+ (portRef I1 (instanceRef N_98_i_i_a3))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5))
+ (portRef I0 (instanceRef SM_AMIGA_i_2))
+ ))
+ (net RW_000_INT (joined
+ (portRef Q (instanceRef RW_000_INT))
+ (portRef I0 (instanceRef RW_000_INT_0_n))
+ (portRef I0 (instanceRef RW))
+ (portRef I0 (instanceRef RW_000))
))
(net UDS_000_INT (joined
(portRef Q (instanceRef UDS_000_INT))
@@ -806,31 +830,24 @@
(net DSACK1_INT (joined
(portRef Q (instanceRef DSACK1_INT))
(portRef I0 (instanceRef DSACK1_INT_0_n))
- (portRef I0 (instanceRef DSACK_1))
+ (portRef I0 (instanceRef DSACK1))
))
- (net (rename clk_un3_clk_out_pre_50 "clk.un3_clk_out_pre_50") (joined
- (portRef O (instanceRef clk_un3_clk_out_pre_50))
+ (net (rename state_machine_un3_clk_out_pre_50 "state_machine.un3_clk_out_pre_50") (joined
+ (portRef O (instanceRef state_machine_un3_clk_out_pre_50))
(portRef I1 (instanceRef CLK_OUT_PRE_25_0))
))
(net CLK_000_D3 (joined
(portRef Q (instanceRef CLK_000_D3))
- (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o3_i_a2))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_1_1))
- (portRef D (instanceRef CLK_000_D4))
+ (portRef I1 (instanceRef un1_bgack_030_int_d_i_o2_0))
))
(net CLK_030_H (joined
(portRef Q (instanceRef CLK_030_H))
- (portRef I0 (instanceRef CLK_030_H_0_n))
- (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_a3))
(portRef I0 (instanceRef CLK_030_H_i))
+ (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_a3))
+ (portRef I0 (instanceRef CLK_030_H_0_n))
))
- (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined
- (portRef O (instanceRef state_machine_un6_bgack_000_0_i))
- (portRef I1 (instanceRef BGACK_030_INT_0_m))
- (portRef I0 (instanceRef BGACK_030_INT_0_r))
- ))
- (net (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d0_0_i))
+ (net (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0_i))
(portRef I1 (instanceRef VMA_INT_0_m))
(portRef I0 (instanceRef VMA_INT_0_r))
))
@@ -851,43 +868,36 @@
(portRef Q (instanceRef A0_DMA))
(portRef I0 (instanceRef A0))
))
- (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined
- (portRef Q (instanceRef SM_AMIGA_7))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_1))
- (portRef I0 (instanceRef SM_AMIGA_i_7))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2))
- (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_2))
- ))
- (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 (joined
- (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i))
- (portRef I0 (instanceRef AS_030_000_SYNC_0_m))
+ (net AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined
+ (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3))
+ (portRef I1 (instanceRef avec_exp_0_m))
+ (portRef I0 (instanceRef avec_exp_0_r))
))
(net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined
(portRef Q (instanceRef SM_AMIGA_4))
(portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0_4))
(portRef I0 (instanceRef SM_AMIGA_i_4))
))
- (net (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (joined
- (portRef O (instanceRef state_machine_A0_DMA_2_0_a3))
- (portRef D (instanceRef A0_DMA))
- ))
- (net (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (joined
- (portRef O (instanceRef state_machine_DS_000_DMA_3_0_i))
- (portRef I0 (instanceRef DS_000_DMA_0_m))
- ))
- (net (rename state_machine_SIZE_DMA_4_1 "state_machine.SIZE_DMA_4[1]") (joined
- (portRef O (instanceRef state_machine_SIZE_DMA_4_0_i_1))
- (portRef D (instanceRef SIZE_DMA_1))
- ))
(net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined
(portRef Q (instanceRef SM_AMIGA_3))
(portRef I0 (instanceRef SM_AMIGA_i_3))
(portRef I1 (instanceRef SM_AMIGA_ns_0_a3_2_5))
))
- (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined
- (portRef Q (instanceRef SM_AMIGA_2))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a3_0_6))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5))
+ (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined
+ (portRef Q (instanceRef SM_AMIGA_1))
+ (portRef I0 (instanceRef SM_AMIGA_i_1))
+ ))
+ (net un1_DSACK1_INT_0_sqmuxa_3 (joined
+ (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3_i))
+ (portRef I0 (instanceRef AS_030_000_SYNC_0_m))
+ ))
+ (net (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (joined
+ (portRef O (instanceRef state_machine_A0_DMA_2_0_a3))
+ (portRef D (instanceRef A0_DMA))
+ ))
+ (net (rename state_machine_SIZE_DMA_4_1 "state_machine.SIZE_DMA_4[1]") (joined
+ (portRef O (instanceRef state_machine_SIZE_DMA_4_0_i_1))
+ (portRef D (instanceRef SIZE_DMA_1))
))
(net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined
(portRef O (instanceRef state_machine_un10_bg_030_0_i))
@@ -903,8 +913,8 @@
(portRef I0 (instanceRef UDS_000_INT_0_m))
))
(net N_1 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_p))
- (portRef D (instanceRef AMIGA_BUS_ENABLEDFFSH))
+ (portRef O (instanceRef RW_000_INT_0_p))
+ (portRef D (instanceRef RW_000_INT))
))
(net N_2 (joined
(portRef O (instanceRef AS_030_000_SYNC_0_p))
@@ -927,46 +937,50 @@
(portRef D (instanceRef FPU_CS_INT))
))
(net N_7 (joined
+ (portRef O (instanceRef avec_exp_0_p))
+ (portRef D (instanceRef avec_exp))
+ ))
+ (net N_8 (joined
(portRef O (instanceRef BG_000_0_p))
(portRef D (instanceRef BG_000DFFSH))
))
- (net N_8 (joined
+ (net N_9 (joined
(portRef O (instanceRef DS_000_DMA_0_p))
(portRef D (instanceRef DS_000_DMA))
))
- (net N_9 (joined
+ (net N_10 (joined
(portRef O (instanceRef AS_000_DMA_0_p))
(portRef D (instanceRef AS_000_DMA))
))
- (net N_10 (joined
+ (net N_11 (joined
(portRef O (instanceRef AS_000_INT_0_p))
(portRef D (instanceRef AS_000_INT))
))
- (net N_11 (joined
+ (net N_12 (joined
(portRef O (instanceRef DSACK1_INT_0_p))
(portRef D (instanceRef DSACK1_INT))
))
- (net N_12 (joined
+ (net N_13 (joined
(portRef O (instanceRef VMA_INT_0_p))
(portRef D (instanceRef VMA_INT))
))
- (net N_13 (joined
+ (net N_14 (joined
(portRef O (instanceRef BGACK_030_INT_0_p))
(portRef D (instanceRef BGACK_030_INT))
))
- (net N_14 (joined
+ (net N_15 (joined
(portRef O (instanceRef CLK_OUT_PRE_25_0))
(portRef D (instanceRef CLK_OUT_PRE_25))
))
- (net N_15 (joined
+ (net N_16 (joined
(portRef O (instanceRef IPL_030_0_0__p))
(portRef D (instanceRef IPL_030DFFSH_0))
))
- (net N_16 (joined
+ (net N_17 (joined
(portRef O (instanceRef IPL_030_0_1__p))
(portRef D (instanceRef IPL_030DFFSH_1))
))
- (net N_17 (joined
+ (net N_18 (joined
(portRef O (instanceRef IPL_030_0_2__p))
(portRef D (instanceRef IPL_030DFFSH_2))
))
@@ -978,34 +992,42 @@
(portRef O (instanceRef SM_AMIGA_ns_0_i_5))
(portRef D (instanceRef SM_AMIGA_2))
))
+ (net (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_a3_2))
+ (portRef D (instanceRef SM_AMIGA_5))
+ ))
+ (net (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_a3_6))
+ (portRef D (instanceRef SM_AMIGA_1))
+ ))
(net (rename cpu_est_0 "cpu_est[0]") (joined
(portRef Q (instanceRef cpu_est_0))
- (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_2))
(portRef I0 (instanceRef cpu_est_ns_0_0_a2_0_1))
(portRef I0 (instanceRef cpu_est_i_0))
(portRef I1 (instanceRef cpu_estse_i_a3_0))
+ (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1_2))
))
(net (rename cpu_est_1 "cpu_est[1]") (joined
(portRef Q (instanceRef cpu_est_1))
(portRef I0 (instanceRef cpu_estse_0_m))
- (portRef I0 (instanceRef cpu_est_ns_0_0_a3_2))
(portRef I0 (instanceRef cpu_est_i_1))
(portRef I0 (instanceRef cpu_est_ns_0_0_a2_1))
+ (portRef I0 (instanceRef cpu_est_ns_0_0_a3_2))
))
(net (rename cpu_est_2 "cpu_est[2]") (joined
(portRef Q (instanceRef cpu_est_2))
(portRef I0 (instanceRef cpu_estse_1_m))
- (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1))
- (portRef I1 (instanceRef cpu_est_ns_0_0_a3_2))
(portRef I1 (instanceRef cpu_est_ns_i_0_a3_3))
(portRef I0 (instanceRef cpu_est_i_2))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1))
+ (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_a3_2))
+ (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_2))
))
(net (rename cpu_est_3 "cpu_est[3]") (joined
(portRef Q (instanceRef cpu_est_3))
(portRef I0 (instanceRef cpu_estse_2_m))
(portRef I1 (instanceRef cpu_est_ns_0_0_a3_1))
- (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_2))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1_2))
(portRef I0 (instanceRef cpu_est_ns_i_0_o2_3))
(portRef I0 (instanceRef cpu_est_i_3))
(portRef I0 (instanceRef E))
@@ -1030,90 +1052,78 @@
(portRef O (instanceRef cpu_est_ns_0_0_i_2))
(portRef I0 (instanceRef cpu_estse_1_n))
))
- (net (rename state_machine_un8_bgack_030_int_i_0 "state_machine.un8_bgack_030_int_i_0") (joined
- (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_o3_i))
- (portRef I0 (instanceRef AS_000_DMA_0_m))
- ))
- (net N_197 (joined
+ (net N_193 (joined
(portRef O (instanceRef AS_000_INT_1_sqmuxa_i_i))
(portRef I1 (instanceRef AS_000_INT_0_m))
(portRef I0 (instanceRef AS_000_INT_0_r))
))
- (net N_198 (joined
- (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_i))
- (portRef I1 (instanceRef AS_000_DMA_0_m))
- (portRef I0 (instanceRef AS_000_DMA_0_r))
- ))
- (net N_199 (joined
+ (net N_196 (joined
(portRef O (instanceRef un1_AS_030_2_i_i))
(portRef I1 (instanceRef LDS_000_INT_0_m))
(portRef I0 (instanceRef LDS_000_INT_0_r))
(portRef I1 (instanceRef UDS_000_INT_0_m))
(portRef I0 (instanceRef UDS_000_INT_0_r))
))
- (net N_200 (joined
+ (net N_28 (joined
(portRef O (instanceRef un1_as_030_000_sync8_1_i_i))
(portRef I1 (instanceRef FPU_CS_INT_0_m))
(portRef I0 (instanceRef FPU_CS_INT_0_r))
))
- (net N_201 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i))
+ (net N_30 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_i))
(portRef I1 (instanceRef AS_030_000_SYNC_0_m))
(portRef I0 (instanceRef AS_030_000_SYNC_0_r))
))
- (net N_41 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_i_i_6))
- (portRef D (instanceRef SM_AMIGA_1))
- ))
- (net N_51 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_i))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_m))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_r))
- ))
- (net N_53 (joined
+ (net N_55 (joined
(portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_i))
(portRef I1 (instanceRef DS_000_DMA_0_m))
(portRef I0 (instanceRef DS_000_DMA_0_r))
))
- (net N_61 (joined
+ (net N_62 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_o2_i))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_2))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_a3_0_1))
+ ))
+ (net N_63 (joined
(portRef O (instanceRef SM_AMIGA_ns_i_o2_i_4))
(portRef I0 (instanceRef SM_AMIGA_ns_0_a3_2_5))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_1_4))
))
- (net N_62 (joined
+ (net N_66 (joined
(portRef O (instanceRef SM_AMIGA_ns_i_o2_0_i_4))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_4))
(portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_n))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_4))
))
- (net N_64 (joined
+ (net N_67 (joined
(portRef O (instanceRef AS_000_INT_1_sqmuxa_i_o2_i))
(portRef I0 (instanceRef AS_000_INT_0_m))
- (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i))
(portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_m))
+ (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i))
))
- (net N_65 (joined
+ (net N_69 (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i_o2_0_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0))
+ ))
+ (net N_70 (joined
+ (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_p))
+ (portRef I0 (instanceRef N_70_i))
+ ))
+ (net N_71 (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i_o2_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_o3_0))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_a3_1))
+ ))
+ (net N_75 (joined
(portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_o3_i))
(portRef I1 (instanceRef DSACK1_INT_0_m))
(portRef I0 (instanceRef DSACK1_INT_0_r))
))
- (net N_66 (joined
- (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_p))
- (portRef I0 (instanceRef N_66_i))
- ))
- (net N_69 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2))
- ))
- (net N_72 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_1))
- ))
- (net N_74 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2_i))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_2))
- ))
(net N_76 (joined
- (portRef O (instanceRef clk_un3_clk_000_d1_0_o2_i))
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_i))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_2))
+ ))
+ (net N_77 (joined
+ (portRef O (instanceRef state_machine_un3_clk_000_d1_0_o2_i))
(portRef I1 (instanceRef cpu_estse_2_m))
(portRef I0 (instanceRef cpu_estse_2_r))
(portRef I1 (instanceRef cpu_estse_1_m))
@@ -1129,165 +1139,115 @@
(portRef I0 (instanceRef cpu_estse_i_a3))
(portRef I1 (instanceRef state_machine_un6_bgack_000_0))
))
- (net N_77 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_i_6))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_7))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a3_6))
+ (net N_79 (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_o2_i))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_1))
))
- (net N_78 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_7))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_a3))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_1_7))
- ))
- (net N_82 (joined
+ (net N_90 (joined
(portRef O (instanceRef cpu_est_ns_i_0_o2_i_3))
(portRef I0 (instanceRef cpu_est_ns_i_0_a3_3))
))
- (net N_86 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_0_i_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_1))
+ (net N_200 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_o2_i_2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_a3_2))
))
(net N_202 (joined
- (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_o2_i))
- (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0_i_a3))
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_i_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_1))
))
- (net N_203 (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3))
- (portRef I0 (instanceRef N_203_i))
+ (net N_204 (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3))
+ (portRef I0 (instanceRef N_204_i))
))
- (net N_205 (joined
- (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o3_i_a3))
- (portRef I0 (instanceRef N_205_i))
- ))
- (net N_206 (joined
- (portRef O (instanceRef state_machine_un10_bg_030_0_a3))
- (portRef I0 (instanceRef N_206_i))
+ (net N_114 (joined
+ (portRef O (instanceRef N_98_i_i_a3))
+ (portRef I0 (instanceRef N_114_i))
))
(net N_115 (joined
- (portRef O (instanceRef un1_AS_030_2_i_a3))
+ (portRef O (instanceRef state_machine_un10_bg_030_0_a3))
(portRef I0 (instanceRef N_115_i))
))
(net N_116 (joined
- (portRef O (instanceRef un1_AS_030_2_i_a3_0))
+ (portRef O (instanceRef un1_bgack_030_int_d_i_a3))
(portRef I0 (instanceRef N_116_i))
))
(net N_117 (joined
- (portRef O (instanceRef un1_as_030_000_sync8_1_i_a3))
+ (portRef O (instanceRef un1_AS_030_2_i_a3))
(portRef I0 (instanceRef N_117_i))
))
(net N_118 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3))
+ (portRef O (instanceRef un1_AS_030_2_i_a3_0))
(portRef I0 (instanceRef N_118_i))
))
(net N_120 (joined
- (portRef O (instanceRef state_machine_LDS_000_INT_7_0_a3))
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_a3_0))
(portRef I0 (instanceRef N_120_i))
))
(net N_121 (joined
- (portRef O (instanceRef state_machine_SIZE_DMA_4_i_a3_0))
+ (portRef O (instanceRef un1_as_030_000_sync8_1_i_a3))
(portRef I0 (instanceRef N_121_i))
))
(net N_122 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a3_1))
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3))
(portRef I0 (instanceRef N_122_i))
))
- (net N_123 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_1))
- (portRef I0 (instanceRef N_123_i))
- ))
(net N_124 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_2))
+ (portRef O (instanceRef state_machine_LDS_000_INT_7_0_a3))
(portRef I0 (instanceRef N_124_i))
))
(net N_125 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_3))
+ (portRef O (instanceRef state_machine_SIZE_DMA_4_i_a3_0))
(portRef I0 (instanceRef N_125_i))
))
- (net N_126 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a3_4))
- (portRef I0 (instanceRef N_126_i))
- ))
- (net N_127 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_4))
- (portRef I0 (instanceRef N_127_i))
- ))
(net N_128 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a3_5))
+ (portRef O (instanceRef SM_AMIGA_ns_0_a3_0))
(portRef I0 (instanceRef N_128_i))
))
(net N_129 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_5))
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_1))
(portRef I0 (instanceRef N_129_i))
))
- (net N_130 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_i_a3_6))
- (portRef I0 (instanceRef N_130_i))
- ))
- (net N_131 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_i_a3_0_6))
- (portRef I0 (instanceRef N_131_i))
- ))
(net N_132 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a3_7))
+ (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_4))
(portRef I0 (instanceRef N_132_i))
))
- (net N_133 (joined
- (portRef O (instanceRef cpu_est_ns_0_0_a3_1))
- (portRef I0 (instanceRef N_133_i))
- ))
- (net N_134 (joined
- (portRef O (instanceRef cpu_est_ns_0_0_a3_0_1))
- (portRef I0 (instanceRef N_134_i))
- ))
- (net N_135 (joined
- (portRef O (instanceRef cpu_est_ns_i_0_a3_3))
- (portRef I0 (instanceRef N_135_i))
- ))
(net N_136 (joined
- (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3))
+ (portRef O (instanceRef cpu_est_ns_0_0_a3_1))
(portRef I0 (instanceRef N_136_i))
))
(net N_137 (joined
- (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0))
+ (portRef O (instanceRef cpu_est_ns_0_0_a3_0_1))
(portRef I0 (instanceRef N_137_i))
))
(net N_138 (joined
- (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_a3))
+ (portRef O (instanceRef cpu_est_ns_i_0_a3_3))
(portRef I0 (instanceRef N_138_i))
))
- (net N_139 (joined
- (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3))
- (portRef I0 (instanceRef N_139_i))
- ))
(net N_140 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_a3))
+ (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0))
(portRef I0 (instanceRef N_140_i))
))
- (net N_141 (joined
- (portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_a3))
- (portRef I0 (instanceRef N_141_i))
- ))
(net N_142 (joined
- (portRef O (instanceRef cpu_est_ns_0_0_a3_2))
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3))
(portRef I0 (instanceRef N_142_i))
))
- (net N_143 (joined
- (portRef O (instanceRef cpu_est_ns_0_0_a3_0_2))
- (portRef I0 (instanceRef N_143_i))
- ))
(net N_144 (joined
- (portRef O (instanceRef cpu_est_ns_0_0_a3_1_2))
+ (portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_a3))
(portRef I0 (instanceRef N_144_i))
))
(net N_145 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a3_0))
+ (portRef O (instanceRef cpu_est_ns_0_0_a3_2))
(portRef I0 (instanceRef N_145_i))
))
(net N_146 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_0))
+ (portRef O (instanceRef cpu_est_ns_0_0_a3_0_2))
(portRef I0 (instanceRef N_146_i))
))
(net N_147 (joined
+ (portRef O (instanceRef cpu_est_ns_0_0_a3_1_2))
+ (portRef I0 (instanceRef N_147_i))
+ ))
+ (net N_148 (joined
(portRef O (instanceRef un3_dtack_i_a3))
(portRef OE (instanceRef A0))
(portRef OE (instanceRef AS_030))
@@ -1296,31 +1256,25 @@
(portRef OE (instanceRef SIZE_0))
(portRef OE (instanceRef SIZE_1))
))
- (net N_148 (joined
- (portRef O (instanceRef cpu_estse_i_a3))
- (portRef I0 (instanceRef N_148_i))
- ))
- (net N_149 (joined
- (portRef O (instanceRef cpu_estse_i_a3_0))
- (portRef I0 (instanceRef N_149_i))
- ))
(net N_150 (joined
- (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_a2))
+ (portRef O (instanceRef cpu_estse_i_a3))
(portRef I0 (instanceRef N_150_i))
))
- (net N_152 (joined
+ (net N_151 (joined
+ (portRef O (instanceRef cpu_estse_i_a3_0))
+ (portRef I0 (instanceRef N_151_i))
+ ))
+ (net N_155 (joined
(portRef O (instanceRef SM_AMIGA_ns_i_a2_4))
- (portRef I0 (instanceRef N_152_i))
+ (portRef I0 (instanceRef N_155_i))
))
- (net N_153 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4))
- (portRef I0 (instanceRef N_153_i))
- ))
- (net N_164 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_7))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_0))
- (portRef I0 (instanceRef N_164_i))
- (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1))
+ (net N_166 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_a2))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_2))
+ (portRef I0 (instanceRef state_machine_SIZE_DMA_4_i_a3_0))
+ (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a3))
+ (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_a3_0))
))
(net N_167 (joined
(portRef O (instanceRef cpu_est_ns_0_0_a2_1))
@@ -1328,123 +1282,242 @@
(portRef I0 (instanceRef N_167_i))
))
(net N_168 (joined
- (portRef O (instanceRef cpu_est_ns_i_0_a2_3))
+ (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_a2))
(portRef I0 (instanceRef N_168_i))
- (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0))
))
(net N_169 (joined
- (portRef O (instanceRef cpu_est_ns_0_0_a2_0_1))
+ (portRef O (instanceRef SM_AMIGA_ns_0_a2_0))
(portRef I0 (instanceRef N_169_i))
- (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_1))
))
(net N_170 (joined
- (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o3_i_a2))
- (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o3_i_a3))
+ (portRef O (instanceRef cpu_est_ns_0_0_a2_0_1))
(portRef I0 (instanceRef N_170_i))
- ))
- (net N_171 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a2_0))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0))
- (portRef I0 (instanceRef N_171_i))
+ (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_1))
))
(net N_172 (joined
- (portRef O (instanceRef state_machine_SIZE_DMA_4_0_a2_1))
- (portRef I0 (instanceRef state_machine_SIZE_DMA_4_i_a3_0))
+ (portRef O (instanceRef cpu_est_ns_i_0_a2_3))
(portRef I0 (instanceRef N_172_i))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_2))
))
- (net N_173 (joined
- (portRef O (instanceRef state_machine_A0_DMA_2_0_a2))
- (portRef I1 (instanceRef state_machine_SIZE_DMA_4_i_a3_0))
- (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1))
- (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a3))
- ))
- (net N_225 (joined
- (portRef O (instanceRef un8_ciin))
- (portRef OE (instanceRef CIIN))
- ))
- (net N_228 (joined
+ (net N_220 (joined
(portRef O (instanceRef un4_ciin))
(portRef I0 (instanceRef CIIN))
))
- (net CLK_000_D0_i (joined
- (portRef O (instanceRef CLK_000_D0_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_6))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_1_5))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_1_4))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_1))
+ (net N_230 (joined
+ (portRef O (instanceRef un8_ciin))
+ (portRef OE (instanceRef CIIN))
))
- (net BGACK_030_INT_i (joined
- (portRef O (instanceRef BGACK_030_INT_i))
- (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a2))
- (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_o3))
- (portRef I1 (instanceRef un3_dtack_i_a3_1))
+ (net N_133 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_a3_5))
+ (portRef I0 (instanceRef N_133_i))
))
- (net CLK_030_i (joined
- (portRef O (instanceRef CLK_030_i))
- (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_a3))
+ (net N_143 (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0))
+ (portRef I0 (instanceRef N_143_i))
))
- (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined
- (portRef O (instanceRef cpu_est_i_3))
- (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_1))
- (portRef I1 (instanceRef cpu_est_ns_i_0_a2_3))
+ (net N_143_2 (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_2))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_o2))
+ (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i))
+ (portRef I1 (instanceRef state_machine_DS_000_DMA_3_0))
+ (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_1))
+ (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0_i))
+ (portRef I0 (instanceRef N_143_2_i))
+ (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_1))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_1))
))
- (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined
- (portRef O (instanceRef SM_AMIGA_i_6))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_2))
+ (net N_203 (joined
+ (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_o2_i))
+ (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0_i_a3))
))
- (net nEXP_SPACE_i (joined
- (portRef O (instanceRef nEXP_SPACE_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0))
- (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0))
- (portRef I1 (instanceRef un3_dtack_i_a3))
+ (net N_201 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_o2_i_6))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_a3_6))
))
- (net CLK_000_D4_i (joined
- (portRef O (instanceRef CLK_000_D4_i))
- (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o3_i_a2))
- (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3))
+ (net N_199 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_o2_0_i))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_a3))
))
- (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined
- (portRef O (instanceRef SM_AMIGA_i_5))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_3))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_2))
+ (net N_161 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4))
+ (portRef I0 (instanceRef N_161_i))
+ ))
+ (net N_141 (joined
+ (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_a3))
+ (portRef I0 (instanceRef N_141_i))
+ ))
+ (net N_139 (joined
+ (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3))
+ (portRef I0 (instanceRef N_139_i))
+ ))
+ (net N_135 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_7))
+ (portRef I0 (instanceRef N_135_i))
+ ))
+ (net N_134 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_5))
+ (portRef I0 (instanceRef N_134_i))
+ ))
+ (net N_131 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a3_4))
+ (portRef I0 (instanceRef N_131_i))
+ ))
+ (net N_130 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_a3_3))
+ (portRef I0 (instanceRef N_130_i))
+ ))
+ (net N_171 (joined
+ (portRef O (instanceRef state_machine_SIZE_DMA_4_0_a2_1))
+ (portRef I1 (instanceRef state_machine_SIZE_DMA_4_i_a3_0))
+ (portRef I0 (instanceRef N_171_i))
+ ))
+ (net (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (joined
+ (portRef O (instanceRef state_machine_DS_000_DMA_3_0_i))
+ (portRef I0 (instanceRef DS_000_DMA_0_m))
+ ))
+ (net N_197 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_i))
+ (portRef I1 (instanceRef RW_000_INT_0_m))
+ (portRef I0 (instanceRef RW_000_INT_0_r))
+ ))
+ (net N_119 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_a3))
+ (portRef I0 (instanceRef N_119_i))
+ ))
+ (net N_194 (joined
+ (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_i))
+ (portRef I1 (instanceRef AS_000_DMA_0_m))
+ (portRef I0 (instanceRef AS_000_DMA_0_r))
+ ))
+ (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined
+ (portRef O (instanceRef state_machine_un6_bgack_000_0_i))
+ (portRef I1 (instanceRef BGACK_030_INT_0_m))
+ (portRef I0 (instanceRef BGACK_030_INT_0_r))
+ ))
+ (net N_143_2_i (joined
+ (portRef O (instanceRef N_143_2_i))
+ (portRef I0 (instanceRef AS_000_DMA_0_m))
+ ))
+ (net (rename A_i_18 "A_i[18]") (joined
+ (portRef O (instanceRef A_i_18))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_2))
+ ))
+ (net (rename A_i_16 "A_i[16]") (joined
+ (portRef O (instanceRef A_i_16))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_2))
+ ))
+ (net (rename A_i_19 "A_i[19]") (joined
+ (portRef O (instanceRef A_i_19))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_1))
))
(net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined
(portRef O (instanceRef SM_AMIGA_i_4))
(portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_3))
))
+ (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_5))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_3))
+ ))
+ (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_3))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_4))
+ ))
+ (net CLK_000_D0_i (joined
+ (portRef O (instanceRef CLK_000_D0_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_7))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_1_5))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_1_4))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_1))
+ ))
+ (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_0))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2_0))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_7))
+ ))
+ (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_6))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_7))
+ ))
+ (net RW_i (joined
+ (portRef O (instanceRef I_141))
+ (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_1))
+ (portRef I1 (instanceRef un1_AS_030_2_i_a3_0))
+ ))
+ (net CLK_030_H_i (joined
+ (portRef O (instanceRef CLK_030_H_i))
+ (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_a3))
+ ))
+ (net CLK_030_i (joined
+ (portRef O (instanceRef CLK_030_i))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_o2))
+ (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_a3))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_1))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a3_0_1))
+ ))
+ (net DTACK_D0_i (joined
+ (portRef O (instanceRef DTACK_D0_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4))
+ ))
+ (net BGACK_030_INT_i (joined
+ (portRef O (instanceRef BGACK_030_INT_i))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_a2))
+ (portRef I1 (instanceRef un3_dtack_i_a3_1))
+ (portRef OE (instanceRef RW))
+ ))
(net AS_000_i (joined
+ (portRef O (instanceRef I_142))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a2))
+ ))
+ (net UDS_000_i (joined
(portRef O (instanceRef I_143))
- (portRef I0 (instanceRef state_machine_A0_DMA_2_0_a2))
- (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_o3_1))
+ (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0_a2_1))
))
(net LDS_000_i (joined
(portRef O (instanceRef I_144))
(portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_a2_1))
(portRef I1 (instanceRef state_machine_A0_DMA_2_0_a3_1))
))
- (net UDS_000_i (joined
+ (net RW_000_i (joined
(portRef O (instanceRef I_145))
- (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0_a2_1))
+ (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0))
+ ))
+ (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_6))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_o2_0))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_o2_2))
+ ))
+ (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined
+ (portRef O (instanceRef cpu_est_i_3))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_1))
+ (portRef I1 (instanceRef cpu_est_ns_i_0_a2_3))
+ ))
+ (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_7))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_1))
+ (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3))
+ ))
+ (net CLK_000_D2_i (joined
+ (portRef O (instanceRef CLK_000_D2_i))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_0_1))
))
(net (rename cpu_est_i_1 "cpu_est_i[1]") (joined
(portRef O (instanceRef cpu_est_i_1))
- (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1_2))
(portRef I1 (instanceRef cpu_est_ns_0_0_a2_0_1))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_2))
(portRef I1 (instanceRef cpu_est_ns_i_0_o2_3))
))
(net (rename cpu_est_i_0 "cpu_est_i[0]") (joined
(portRef O (instanceRef cpu_est_i_0))
- (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1_2))
(portRef I1 (instanceRef cpu_est_ns_0_0_a2_1))
(portRef I1 (instanceRef cpu_estse_i_a3))
- ))
- (net DTACK_D0_i (joined
- (portRef O (instanceRef DTACK_D0_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4))
+ (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_2))
))
(net VMA_INT_i (joined
(portRef O (instanceRef VMA_INT_i))
@@ -1453,41 +1526,24 @@
(net VPA_D_i (joined
(portRef O (instanceRef VPA_D_i))
(portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4))
- (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3))
+ (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3))
))
(net AS_000_DMA_i (joined
(portRef O (instanceRef AS_000_DMA_i))
- (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0))
(portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_o2))
+ (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0))
(portRef I0 (instanceRef un3_dtack_i_a3_1))
))
- (net CLK_030_H_i (joined
- (portRef O (instanceRef CLK_030_H_i))
- (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_a3))
- ))
- (net RW_i (joined
- (portRef O (instanceRef RW_i))
- (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3))
- (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_1))
- (portRef I1 (instanceRef un1_AS_030_2_i_a3_0))
+ (net nEXP_SPACE_i (joined
+ (portRef O (instanceRef nEXP_SPACE_i))
+ (portRef I1 (instanceRef un1_bgack_030_int_d_i_o2))
+ (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0))
+ (portRef I1 (instanceRef un3_dtack_i_a3))
))
(net (rename cpu_est_i_2 "cpu_est_i[2]") (joined
(portRef O (instanceRef cpu_est_i_2))
(portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_1))
))
- (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined
- (portRef O (instanceRef SM_AMIGA_i_0))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_7))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_7))
- ))
- (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined
- (portRef O (instanceRef SM_AMIGA_i_3))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_4))
- ))
- (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined
- (portRef O (instanceRef SM_AMIGA_i_7))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_1))
- ))
(net A0_i (joined
(portRef O (instanceRef I_146))
(portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_1))
@@ -1499,22 +1555,14 @@
))
(net DS_030_i (joined
(portRef O (instanceRef I_148))
- (portRef I1 (instanceRef state_machine_LDS_000_INT_7_0_1))
(portRef I1 (instanceRef state_machine_UDS_000_INT_7_0))
+ (portRef I1 (instanceRef state_machine_LDS_000_INT_7_0_1))
(portRef I0 (instanceRef un1_AS_030_2_i_a3_1))
(portRef I0 (instanceRef un1_AS_030_2_i_a3_0_1))
))
- (net (rename A_i_19 "A_i[19]") (joined
- (portRef O (instanceRef A_i_19))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3))
- ))
- (net (rename A_i_16 "A_i[16]") (joined
- (portRef O (instanceRef A_i_16))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3))
- ))
- (net (rename A_i_18 "A_i[18]") (joined
- (portRef O (instanceRef A_i_18))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5))
+ (net AS_030_000_SYNC_i (joined
+ (portRef O (instanceRef AS_030_000_SYNC_i))
+ (portRef I1 (instanceRef un1_bgack_030_int_d_i_o2_0_1))
))
(net (rename A_i_30 "A_i[30]") (joined
(portRef O (instanceRef A_i_30))
@@ -1551,7 +1599,6 @@
(net RST_i (joined
(portRef O (instanceRef RST_i))
(portRef S (instanceRef A0_DMA))
- (portRef S (instanceRef AMIGA_BUS_ENABLEDFFSH))
(portRef S (instanceRef AS_000_DMA))
(portRef S (instanceRef AS_000_INT))
(portRef S (instanceRef AS_030_000_SYNC))
@@ -1562,7 +1609,6 @@
(portRef S (instanceRef CLK_000_D1))
(portRef S (instanceRef CLK_000_D2))
(portRef S (instanceRef CLK_000_D3))
- (portRef S (instanceRef CLK_000_D4))
(portRef R (instanceRef CLK_OUT_INT))
(portRef R (instanceRef CLK_OUT_PRE_25))
(portRef R (instanceRef CLK_OUT_PRE_50))
@@ -1576,6 +1622,7 @@
(portRef S (instanceRef IPL_030DFFSH_2))
(portRef S (instanceRef LDS_000_INT))
(portRef R (instanceRef RESETDFFRH))
+ (portRef S (instanceRef RW_000_INT))
(portRef S (instanceRef SIZE_DMA_0))
(portRef S (instanceRef SIZE_DMA_1))
(portRef R (instanceRef SM_AMIGA_0))
@@ -1589,6 +1636,7 @@
(portRef S (instanceRef UDS_000_INT))
(portRef S (instanceRef VMA_INT))
(portRef S (instanceRef VPA_D))
+ (portRef S (instanceRef avec_exp))
(portRef R (instanceRef cpu_est_0))
(portRef R (instanceRef cpu_est_1))
(portRef R (instanceRef cpu_est_2))
@@ -1598,28 +1646,26 @@
(portRef O (instanceRef CLK_OUT_PRE_50_i))
(portRef D (instanceRef CLK_OUT_PRE_50))
))
- (net N_121_i (joined
- (portRef O (instanceRef N_121_i))
+ (net N_125_i (joined
+ (portRef O (instanceRef N_125_i))
(portRef D (instanceRef SIZE_DMA_0))
))
- (net N_205_i (joined
- (portRef O (instanceRef N_205_i))
+ (net N_114_i (joined
+ (portRef O (instanceRef N_114_i))
(portRef I0 (instanceRef DSACK1_INT_0_m))
(portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_o3))
))
(net FPU_CS_INT_i (joined
(portRef O (instanceRef FPU_CS_INT_i))
- (portRef OE (instanceRef AVEC_EXP))
(portRef OE (instanceRef BERR))
))
(net CLK_OUT_PRE_50_D_i (joined
(portRef O (instanceRef CLK_OUT_PRE_50_D_i))
- (portRef I1 (instanceRef clk_un3_clk_out_pre_50))
+ (portRef I1 (instanceRef state_machine_un3_clk_out_pre_50))
))
(net AS_030_c (joined
(portRef O (instanceRef AS_030))
(portRef I0 (instanceRef FPU_CS_INT_0_m))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_a3))
(portRef I0 (instanceRef AS_030_c_i))
(portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_1))
))
@@ -1629,12 +1675,20 @@
))
(net AS_000_c (joined
(portRef O (instanceRef AS_000))
- (portRef I0 (instanceRef I_143))
+ (portRef I0 (instanceRef I_142))
))
(net AS_000 (joined
(portRef IO (instanceRef AS_000))
(portRef AS_000)
))
+ (net RW_000_c (joined
+ (portRef O (instanceRef RW_000))
+ (portRef I0 (instanceRef I_145))
+ ))
+ (net RW_000 (joined
+ (portRef IO (instanceRef RW_000))
+ (portRef RW_000)
+ ))
(net DS_030_c (joined
(portRef O (instanceRef DS_030))
(portRef I0 (instanceRef I_148))
@@ -1645,8 +1699,8 @@
))
(net UDS_000_c (joined
(portRef O (instanceRef UDS_000))
- (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_a2))
- (portRef I0 (instanceRef I_145))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_o2))
+ (portRef I0 (instanceRef I_143))
(portRef I0 (instanceRef state_machine_A0_DMA_2_0_a3_1))
))
(net UDS_000 (joined
@@ -1655,7 +1709,7 @@
))
(net LDS_000_c (joined
(portRef O (instanceRef LDS_000))
- (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_a2))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2))
(portRef I0 (instanceRef I_144))
))
(net LDS_000 (joined
@@ -1688,7 +1742,7 @@
))
(net (rename A_c_17 "A_c[17]") (joined
(portRef O (instanceRef A_17))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_3))
))
(net (rename A_17 "A[17]") (joined
(portRef (member a 14))
@@ -1816,12 +1870,10 @@
))
(net nEXP_SPACE_c (joined
(portRef O (instanceRef nEXP_SPACE))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2))
(portRef I0 (instanceRef nEXP_SPACE_i))
(portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_2))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3))
- (portRef OE (instanceRef DSACK_0))
- (portRef OE (instanceRef DSACK_1))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3))
+ (portRef OE (instanceRef DSACK1))
))
(net nEXP_SPACE (joined
(portRef nEXP_SPACE)
@@ -1855,9 +1907,9 @@
))
(net BGACK_000_c (joined
(portRef O (instanceRef BGACK_000))
- (portRef I0 (instanceRef BGACK_030_INT_0_m))
(portRef I0 (instanceRef state_machine_un6_bgack_000_0))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1))
+ (portRef I0 (instanceRef BGACK_030_INT_0_m))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_1))
))
(net BGACK_000 (joined
(portRef BGACK_000)
@@ -1866,10 +1918,10 @@
(net CLK_030_c (joined
(portRef O (instanceRef CLK_030))
(portRef I0 (instanceRef un1_as_030_000_sync8_1_i_a3))
- (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i))
(portRef I1 (instanceRef state_machine_CLK_030_H_2_f0_i_o2))
+ (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i))
(portRef I0 (instanceRef CLK_030_i))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_1))
))
(net CLK_030 (joined
(portRef CLK_030)
@@ -1887,7 +1939,6 @@
(net CLK_OSZI_c (joined
(portRef O (instanceRef CLK_OSZI))
(portRef CLK (instanceRef A0_DMA))
- (portRef CLK (instanceRef AMIGA_BUS_ENABLEDFFSH))
(portRef CLK (instanceRef AS_000_DMA))
(portRef CLK (instanceRef AS_000_INT))
(portRef CLK (instanceRef AS_030_000_SYNC))
@@ -1898,7 +1949,6 @@
(portRef CLK (instanceRef CLK_000_D1))
(portRef CLK (instanceRef CLK_000_D2))
(portRef CLK (instanceRef CLK_000_D3))
- (portRef CLK (instanceRef CLK_000_D4))
(portRef CLK (instanceRef CLK_030_H))
(portRef CLK (instanceRef CLK_OUT_INT))
(portRef CLK (instanceRef CLK_OUT_PRE_25))
@@ -1913,6 +1963,7 @@
(portRef CLK (instanceRef IPL_030DFFSH_2))
(portRef CLK (instanceRef LDS_000_INT))
(portRef CLK (instanceRef RESETDFFRH))
+ (portRef CLK (instanceRef RW_000_INT))
(portRef CLK (instanceRef SIZE_DMA_0))
(portRef CLK (instanceRef SIZE_DMA_1))
(portRef CLK (instanceRef SM_AMIGA_0))
@@ -1926,6 +1977,7 @@
(portRef CLK (instanceRef UDS_000_INT))
(portRef CLK (instanceRef VMA_INT))
(portRef CLK (instanceRef VPA_D))
+ (portRef CLK (instanceRef avec_exp))
(portRef CLK (instanceRef cpu_est_0))
(portRef CLK (instanceRef cpu_est_1))
(portRef CLK (instanceRef cpu_est_2))
@@ -2003,17 +2055,13 @@
(portRef (member ipl 0))
(portRef I0 (instanceRef IPL_2))
))
- (net (rename DSACK_0 "DSACK[0]") (joined
- (portRef O (instanceRef DSACK_0))
- (portRef (member dsack 1))
- ))
- (net (rename DSACK_c_1 "DSACK_c[1]") (joined
- (portRef O (instanceRef DSACK_1))
+ (net DSACK1_c (joined
+ (portRef O (instanceRef DSACK1))
(portRef I0 (instanceRef DTACK))
))
- (net (rename DSACK_1 "DSACK[1]") (joined
- (portRef (member dsack 0))
- (portRef IO (instanceRef DSACK_1))
+ (net DSACK1 (joined
+ (portRef IO (instanceRef DSACK1))
+ (portRef DSACK1)
))
(net DTACK_c (joined
(portRef O (instanceRef DTACK))
@@ -2028,7 +2076,7 @@
(portRef AVEC)
))
(net AVEC_EXP (joined
- (portRef O (instanceRef AVEC_EXP))
+ (portRef O (instanceRef AVEC_EXPZ0))
(portRef AVEC_EXP)
))
(net E (joined
@@ -2049,9 +2097,9 @@
))
(net RST_c (joined
(portRef O (instanceRef RST))
+ (portRef I0 (instanceRef RST_i))
(portRef I1 (instanceRef CLK_030_H_0_m))
(portRef I0 (instanceRef CLK_030_H_0_r))
- (portRef I0 (instanceRef RST_i))
))
(net RST (joined
(portRef RST)
@@ -2067,19 +2115,19 @@
))
(net RW_c (joined
(portRef O (instanceRef RW))
- (portRef I0 (instanceRef RW_i))
(portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_m))
(portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_r))
+ (portRef I0 (instanceRef I_141))
(portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1))
(portRef I1 (instanceRef un1_AS_030_2_i_a3))
))
(net RW (joined
+ (portRef IO (instanceRef RW))
(portRef RW)
- (portRef I0 (instanceRef RW))
))
(net (rename FC_c_0 "FC_c[0]") (joined
(portRef O (instanceRef FC_0))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_3))
))
(net (rename FC_0 "FC[0]") (joined
(portRef (member fc 1))
@@ -2087,17 +2135,12 @@
))
(net (rename FC_c_1 "FC_c[1]") (joined
(portRef O (instanceRef FC_1))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_5))
))
(net (rename FC_1 "FC[1]") (joined
(portRef (member fc 0))
(portRef I0 (instanceRef FC_1))
))
- (net AMIGA_BUS_ENABLE_c (joined
- (portRef Q (instanceRef AMIGA_BUS_ENABLEDFFSH))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_n))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE))
- ))
(net AMIGA_BUS_ENABLE (joined
(portRef O (instanceRef AMIGA_BUS_ENABLE))
(portRef AMIGA_BUS_ENABLE)
@@ -2118,113 +2161,216 @@
(portRef O (instanceRef CIIN))
(portRef CIIN)
))
- (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined
- (portRef O (instanceRef cpu_est_ns_0_0_1))
- (portRef I0 (instanceRef cpu_est_ns_0_0_i_1))
+ (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined
+ (portRef O (instanceRef state_machine_un6_bgack_000_0))
+ (portRef I0 (instanceRef state_machine_un6_bgack_000_0_i))
))
- (net N_134_i (joined
- (portRef O (instanceRef N_134_i))
- (portRef I1 (instanceRef cpu_est_ns_0_0_1_1))
+ (net N_194_0 (joined
+ (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i))
+ (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i))
))
- (net N_169_i (joined
- (portRef O (instanceRef N_169_i))
- (portRef I1 (instanceRef cpu_est_ns_0_0_2_1))
+ (net N_119_i (joined
+ (portRef O (instanceRef N_119_i))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i))
+ ))
+ (net N_120_i (joined
+ (portRef O (instanceRef N_120_i))
+ (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i))
+ ))
+ (net N_197_0 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_i))
+ ))
+ (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined
+ (portRef O (instanceRef state_machine_DS_000_DMA_3_0))
+ (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0_i))
+ ))
+ (net N_171_i (joined
+ (portRef O (instanceRef N_171_i))
+ (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0_1))
+ ))
+ (net (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (joined
+ (portRef O (instanceRef state_machine_SIZE_DMA_4_0_1))
+ (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_i_1))
+ ))
+ (net N_130_i (joined
+ (portRef O (instanceRef N_130_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_3))
+ ))
+ (net N_68_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_3))
+ (portRef D (instanceRef SM_AMIGA_4))
+ ))
+ (net N_131_i (joined
+ (portRef O (instanceRef N_131_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_4))
+ ))
+ (net N_132_i (joined
+ (portRef O (instanceRef N_132_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_4))
+ ))
+ (net N_45_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_4))
+ (portRef D (instanceRef SM_AMIGA_3))
))
(net N_133_i (joined
(portRef O (instanceRef N_133_i))
- (portRef I0 (instanceRef cpu_est_ns_0_0_1_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_5))
+ ))
+ (net N_134_i (joined
+ (portRef O (instanceRef N_134_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_5))
+ ))
+ (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_5))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_i_5))
+ ))
+ (net N_135_i (joined
+ (portRef O (instanceRef N_135_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_7))
+ ))
+ (net N_73_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_7))
+ (portRef D (instanceRef SM_AMIGA_0))
+ ))
+ (net N_139_i (joined
+ (portRef O (instanceRef N_139_i))
+ (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0))
+ ))
+ (net N_140_i (joined
+ (portRef O (instanceRef N_140_i))
+ (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0))
+ ))
+ (net AMIGA_BUS_DATA_DIR_c_0 (joined
+ (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0))
+ (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i))
+ ))
+ (net N_141_i (joined
+ (portRef O (instanceRef N_141_i))
+ (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i))
+ ))
+ (net N_52_i (joined
+ (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i))
+ (portRef I0 (instanceRef CLK_030_H_0_m))
+ ))
+ (net N_143_i (joined
+ (portRef O (instanceRef N_143_i))
+ (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0))
+ ))
+ (net N_142_i (joined
+ (portRef O (instanceRef N_142_i))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0))
+ ))
+ (net (rename state_machine_RW_000_INT_7_iv_i "state_machine.RW_000_INT_7_iv_i") (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0))
+ (portRef I0 (instanceRef RW_000_INT_0_m))
+ ))
+ (net N_62_0 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_o2))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2_i))
+ ))
+ (net N_161_i (joined
+ (portRef O (instanceRef N_161_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4))
+ ))
+ (net N_155_i (joined
+ (portRef O (instanceRef N_155_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_4))
+ ))
+ (net N_63_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_4))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4))
+ ))
+ (net N_66_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_0_4))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_i_4))
+ (portRef I1 (instanceRef un1_AS_030_2_i_a3_0_1))
+ ))
+ (net N_76_i (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2))
+ (portRef I1 (instanceRef un1_as_030_000_sync8_1_i_a3))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_i))
+ ))
+ (net CLK_000_D1_i (joined
+ (portRef O (instanceRef CLK_000_D1_i))
+ (portRef I1 (instanceRef state_machine_un3_clk_000_d1_0_o2))
+ ))
+ (net N_77_i (joined
+ (portRef O (instanceRef state_machine_un3_clk_000_d1_0_o2))
+ (portRef I0 (instanceRef cpu_estse_i_a3_0))
+ (portRef I0 (instanceRef state_machine_un3_clk_000_d1_0_o2_i))
+ ))
+ (net N_79_0 (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_o2))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_o2_i))
+ ))
+ (net N_199_0 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_o2_0))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2_0_i))
+ ))
+ (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_o2_6))
+ ))
+ (net N_201_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_o2_6))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_i_6))
+ ))
+ (net N_203_0 (joined
+ (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_o2))
+ (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_o2_i))
+ ))
+ (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined
+ (portRef O (instanceRef cpu_est_ns_0_0_1))
+ (portRef I0 (instanceRef cpu_est_ns_0_0_i_1))
))
(net N_167_i (joined
(portRef O (instanceRef N_167_i))
(portRef I0 (instanceRef cpu_est_ns_0_0_2_1))
))
- (net N_51_0 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_i))
+ (net N_170_i (joined
+ (portRef O (instanceRef N_170_i))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_2_1))
))
- (net N_140_i (joined
- (portRef O (instanceRef N_140_i))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_2))
+ (net N_136_i (joined
+ (portRef O (instanceRef N_136_i))
+ (portRef I0 (instanceRef cpu_est_ns_0_0_1_1))
+ ))
+ (net N_137_i (joined
+ (portRef O (instanceRef N_137_i))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_1_1))
))
(net N_202_0 (joined
- (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_o2))
- (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_o2_i))
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_1))
))
- (net N_86_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_0_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_i_1))
+ (net N_200_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_o2_2))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_i_2))
))
- (net N_171_i (joined
- (portRef O (instanceRef N_171_i))
- (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3))
+ (net N_169_i (joined
+ (portRef O (instanceRef N_169_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_o3_0))
))
- (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 (joined
- (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i))
- (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i))
+ (net N_198_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_o3_0))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0_1))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_0))
))
- (net N_82_i (joined
+ (net N_168_i (joined
+ (portRef O (instanceRef N_168_i))
+ (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3))
+ ))
+ (net un1_DSACK1_INT_0_sqmuxa_3_0 (joined
+ (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i))
+ (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3_i))
+ ))
+ (net N_90_i (joined
(portRef O (instanceRef cpu_est_ns_i_0_o2_3))
(portRef I0 (instanceRef cpu_est_ns_i_0_o2_i_3))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1_4))
))
- (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined
- (portRef O (instanceRef SM_AMIGA_i_1))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_7))
- ))
- (net N_78_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_7))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_7))
- ))
- (net N_170_i (joined
- (portRef O (instanceRef N_170_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_i_o2_6))
- ))
- (net N_77_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_6))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_i_6))
- ))
- (net CLK_000_D1_i (joined
- (portRef O (instanceRef CLK_000_D1_i))
- (portRef I1 (instanceRef clk_un3_clk_000_d1_0_o2))
- ))
- (net N_76_i (joined
- (portRef O (instanceRef clk_un3_clk_000_d1_0_o2))
- (portRef I0 (instanceRef cpu_estse_i_a3_0))
- (portRef I0 (instanceRef clk_un3_clk_000_d1_0_o2_i))
- ))
- (net N_74_i (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0_1))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_o2_i))
- (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3_1))
- ))
- (net N_72_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_1))
- ))
- (net AS_030_000_SYNC_i (joined
- (portRef O (instanceRef AS_030_000_SYNC_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_1_1))
- ))
- (net CLK_000_D2_i (joined
- (portRef O (instanceRef CLK_000_D2_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_1))
- ))
- (net (rename state_machine_un8_bgack_030_int_i_0_0 "state_machine.un8_bgack_030_int_i_0_0") (joined
- (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_o3))
- (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0_1))
- (portRef I1 (instanceRef state_machine_DS_000_DMA_3_0))
- (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i))
- (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0_i))
- (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_o3_i))
- (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i))
- ))
- (net N_69_i (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2))
- (portRef I1 (instanceRef un1_as_030_000_sync8_1_i_a3))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i))
- ))
(net AS_030_c_i (joined
(portRef O (instanceRef AS_030_c_i))
(portRef I0 (instanceRef un1_as_030_000_sync8_1_i))
@@ -2232,221 +2378,98 @@
(portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o3))
(portRef I1 (instanceRef un1_AS_030_2_i_1))
))
- (net N_65_i (joined
+ (net N_75_i (joined
(portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_o3))
- (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3))
+ (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3))
(portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o3_i))
))
- (net N_64_i (joined
+ (net N_71_i (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i_o2))
+ (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_a2))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_i))
+ ))
+ (net N_69_i (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i_o2_0))
+ (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_a2))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_0_i))
+ (portRef I1 (instanceRef un1_bgack_030_int_d_i_a3))
+ ))
+ (net N_67_i (joined
(portRef O (instanceRef AS_000_INT_1_sqmuxa_i_o2))
(portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_o2_i))
(portRef I1 (instanceRef un1_AS_030_2_i_a3_1))
))
- (net N_62_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_0_4))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_i_4))
- (portRef I1 (instanceRef un1_AS_030_2_i_a3_0_1))
- ))
- (net N_152_i (joined
- (portRef O (instanceRef N_152_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_4))
- ))
- (net N_153_i (joined
- (portRef O (instanceRef N_153_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4))
- ))
- (net N_61_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_4))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4))
- ))
(net N_150_i (joined
(portRef O (instanceRef N_150_i))
- (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_o3_1))
- ))
- (net N_148_i (joined
- (portRef O (instanceRef N_148_i))
(portRef I0 (instanceRef cpu_estse_i))
))
- (net N_149_i (joined
- (portRef O (instanceRef N_149_i))
+ (net N_151_i (joined
+ (portRef O (instanceRef N_151_i))
(portRef I1 (instanceRef cpu_estse_i))
))
- (net N_59_i (joined
+ (net N_60_i (joined
(portRef O (instanceRef cpu_estse_i))
(portRef D (instanceRef cpu_est_0))
))
- (net N_123_i (joined
- (portRef O (instanceRef N_123_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_1))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_1_0))
- ))
(net N_145_i (joined
(portRef O (instanceRef N_145_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_0))
+ (portRef I1 (instanceRef cpu_est_ns_0_0_1_2))
))
(net N_146_i (joined
(portRef O (instanceRef N_146_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_1_0))
- ))
- (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_0))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_i_0))
- ))
- (net N_142_i (joined
- (portRef O (instanceRef N_142_i))
- (portRef I1 (instanceRef cpu_est_ns_0_0_1_2))
- ))
- (net N_143_i (joined
- (portRef O (instanceRef N_143_i))
(portRef I1 (instanceRef cpu_est_ns_0_0_2))
))
- (net N_144_i (joined
- (portRef O (instanceRef N_144_i))
+ (net N_147_i (joined
+ (portRef O (instanceRef N_147_i))
(portRef I0 (instanceRef cpu_est_ns_0_0_1_2))
))
(net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined
(portRef O (instanceRef cpu_est_ns_0_0_2))
(portRef I0 (instanceRef cpu_est_ns_0_0_i_2))
))
- (net N_141_i (joined
- (portRef O (instanceRef N_141_i))
- (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_1))
+ (net N_144_i (joined
+ (portRef O (instanceRef N_144_i))
+ (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_1))
))
- (net N_53_0 (joined
+ (net N_55_0 (joined
(portRef O (instanceRef DS_000_DMA_1_sqmuxa_i))
(portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_i))
))
- (net N_139_i (joined
- (portRef O (instanceRef N_139_i))
- (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0))
- ))
- (net (rename state_machine_AMIGA_BUS_ENABLE_4_iv_i "state_machine.AMIGA_BUS_ENABLE_4_iv_i") (joined
- (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_m))
- ))
(net N_138_i (joined
(portRef O (instanceRef N_138_i))
- (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i))
- ))
- (net N_48_i (joined
- (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i))
- (portRef I0 (instanceRef CLK_030_H_0_m))
- ))
- (net N_136_i (joined
- (portRef O (instanceRef N_136_i))
- (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0))
- ))
- (net N_137_i (joined
- (portRef O (instanceRef N_137_i))
- (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0))
- ))
- (net AMIGA_BUS_DATA_DIR_c_0 (joined
- (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0))
- (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i))
- ))
- (net N_135_i (joined
- (portRef O (instanceRef N_135_i))
(portRef I0 (instanceRef cpu_est_ns_i_0_3))
))
- (net N_168_i (joined
- (portRef O (instanceRef N_168_i))
- (portRef I1 (instanceRef cpu_est_ns_i_0_3))
- ))
- (net N_151_i (joined
- (portRef O (instanceRef cpu_est_ns_i_0_3))
- (portRef I0 (instanceRef cpu_estse_2_n))
- ))
- (net N_132_i (joined
- (portRef O (instanceRef N_132_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_1_7))
- ))
- (net N_164_i (joined
- (portRef O (instanceRef N_164_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_7))
- ))
- (net N_43_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_7))
- (portRef D (instanceRef SM_AMIGA_0))
- ))
- (net N_130_i (joined
- (portRef O (instanceRef N_130_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_i_6))
- ))
- (net N_131_i (joined
- (portRef O (instanceRef N_131_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_i_6))
- ))
- (net N_41_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_i_6))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_i_i_6))
- ))
- (net N_128_i (joined
- (portRef O (instanceRef N_128_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_5))
- ))
- (net N_129_i (joined
- (portRef O (instanceRef N_129_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_5))
- ))
- (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_5))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_i_5))
- ))
- (net N_126_i (joined
- (portRef O (instanceRef N_126_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_4))
- ))
- (net N_127_i (joined
- (portRef O (instanceRef N_127_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_4))
- ))
- (net N_38_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_4))
- (portRef D (instanceRef SM_AMIGA_3))
- ))
- (net N_125_i (joined
- (portRef O (instanceRef N_125_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_0_3))
- ))
- (net N_75_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_0_3))
- (portRef D (instanceRef SM_AMIGA_4))
- ))
- (net N_124_i (joined
- (portRef O (instanceRef N_124_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_0_2))
- ))
- (net N_73_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_0_2))
- (portRef D (instanceRef SM_AMIGA_5))
- ))
- (net N_122_i (joined
- (portRef O (instanceRef N_122_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_1))
- ))
- (net N_34_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_1))
- (portRef D (instanceRef SM_AMIGA_6))
- ))
(net N_172_i (joined
(portRef O (instanceRef N_172_i))
- (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_1))
+ (portRef I1 (instanceRef cpu_est_ns_i_0_3))
))
- (net (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (joined
- (portRef O (instanceRef state_machine_SIZE_DMA_4_0_1))
- (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_i_1))
+ (net N_149_i (joined
+ (portRef O (instanceRef cpu_est_ns_i_0_3))
+ (portRef I0 (instanceRef cpu_estse_2_n))
))
- (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined
- (portRef O (instanceRef state_machine_DS_000_DMA_3_0))
- (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0_i))
+ (net N_129_i (joined
+ (portRef O (instanceRef N_129_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_0_1))
))
- (net N_66_i (joined
- (portRef O (instanceRef N_66_i))
+ (net N_65_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_0_1))
+ (portRef D (instanceRef SM_AMIGA_6))
+ ))
+ (net N_128_i (joined
+ (portRef O (instanceRef N_128_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_0))
+ ))
+ (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_0))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_i_0))
+ ))
+ (net N_70_i (joined
+ (portRef O (instanceRef N_70_i))
(portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_1))
(portRef I1 (instanceRef state_machine_LDS_000_INT_7_0))
))
- (net N_120_i (joined
- (portRef O (instanceRef N_120_i))
+ (net N_124_i (joined
+ (portRef O (instanceRef N_124_i))
(portRef I0 (instanceRef state_machine_LDS_000_INT_7_0_1))
))
(net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined
@@ -2457,137 +2480,125 @@
(portRef O (instanceRef state_machine_UDS_000_INT_7_0))
(portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_i))
))
- (net N_118_i (joined
- (portRef O (instanceRef N_118_i))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i))
+ (net N_122_i (joined
+ (portRef O (instanceRef N_122_i))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i))
))
- (net N_201_0 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i))
+ (net N_30_0 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_i))
))
- (net N_117_i (joined
- (portRef O (instanceRef N_117_i))
+ (net N_121_i (joined
+ (portRef O (instanceRef N_121_i))
(portRef I1 (instanceRef un1_as_030_000_sync8_1_i))
))
- (net N_200_0 (joined
+ (net N_28_0 (joined
(portRef O (instanceRef un1_as_030_000_sync8_1_i))
(portRef I0 (instanceRef un1_as_030_000_sync8_1_i_i))
))
- (net N_115_i (joined
- (portRef O (instanceRef N_115_i))
+ (net N_117_i (joined
+ (portRef O (instanceRef N_117_i))
(portRef I1 (instanceRef un1_AS_030_2_i))
))
+ (net N_118_i (joined
+ (portRef O (instanceRef N_118_i))
+ (portRef I0 (instanceRef un1_AS_030_2_i_1))
+ ))
+ (net N_196_0 (joined
+ (portRef O (instanceRef un1_AS_030_2_i))
+ (portRef I0 (instanceRef un1_AS_030_2_i_i))
+ ))
(net N_116_i (joined
(portRef O (instanceRef N_116_i))
- (portRef I0 (instanceRef un1_AS_030_2_i_1))
+ (portRef I1 (instanceRef un1_bgack_030_int_d_i))
))
- (net N_199_0 (joined
- (portRef O (instanceRef un1_AS_030_2_i))
- (portRef I0 (instanceRef un1_AS_030_2_i_i))
+ (net N_195_i (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i))
+ (portRef I0 (instanceRef avec_exp_0_n))
))
(net BG_030_c_i (joined
(portRef O (instanceRef BG_030_c_i))
(portRef I0 (instanceRef state_machine_un10_bg_030_0))
))
- (net N_206_i (joined
- (portRef O (instanceRef N_206_i))
+ (net N_115_i (joined
+ (portRef O (instanceRef N_115_i))
(portRef I1 (instanceRef state_machine_un10_bg_030_0))
))
(net (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (joined
(portRef O (instanceRef state_machine_un10_bg_030_0))
(portRef I0 (instanceRef state_machine_un10_bg_030_0_i))
))
- (net N_198_0 (joined
- (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i))
- (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i))
- ))
- (net N_197_0 (joined
+ (net N_193_0 (joined
(portRef O (instanceRef AS_000_INT_1_sqmuxa_i))
(portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_i))
))
- (net N_203_i (joined
- (portRef O (instanceRef N_203_i))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0))
+ (net N_204_i (joined
+ (portRef O (instanceRef N_204_i))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0))
))
- (net (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d0_i))
- (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0))
+ (net (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (joined
+ (portRef O (instanceRef state_machine_un10_clk_000_d0_i))
+ (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0))
))
- (net (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d0_0))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_i))
+ (net (rename state_machine_un12_clk_000_d0_0 "state_machine.un12_clk_000_d0_0") (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_i))
))
- (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined
- (portRef O (instanceRef state_machine_un6_bgack_000_0))
- (portRef I0 (instanceRef state_machine_un6_bgack_000_0_i))
+ (net N_69_i_1 (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i_o2_0_1))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_0))
))
- (net N_225_1 (joined
- (portRef O (instanceRef un8_ciin_1))
- (portRef I0 (instanceRef un8_ciin_5))
+ (net N_76_i_1 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_1))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_4))
))
- (net N_225_2 (joined
- (portRef O (instanceRef un8_ciin_2))
- (portRef I1 (instanceRef un8_ciin_5))
+ (net N_76_i_2 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_2))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_4))
))
- (net N_225_3 (joined
- (portRef O (instanceRef un8_ciin_3))
- (portRef I0 (instanceRef un8_ciin_6))
+ (net N_76_i_3 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_3))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_5))
))
- (net N_225_4 (joined
- (portRef O (instanceRef un8_ciin_4))
- (portRef I1 (instanceRef un8_ciin_6))
+ (net N_76_i_4 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_4))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2))
))
- (net N_225_5 (joined
- (portRef O (instanceRef un8_ciin_5))
- (portRef I0 (instanceRef un8_ciin))
+ (net N_76_i_5 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_5))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2))
))
- (net N_225_6 (joined
- (portRef O (instanceRef un8_ciin_6))
- (portRef I1 (instanceRef un8_ciin))
- ))
- (net N_228_1 (joined
+ (net N_220_1 (joined
(portRef O (instanceRef un4_ciin_1))
(portRef I0 (instanceRef un4_ciin))
))
- (net N_228_2 (joined
+ (net N_220_2 (joined
(portRef O (instanceRef un4_ciin_2))
(portRef I1 (instanceRef un4_ciin))
))
- (net N_69_i_1 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4))
+ (net N_230_1 (joined
+ (portRef O (instanceRef un8_ciin_1))
+ (portRef I0 (instanceRef un8_ciin_5))
))
- (net N_69_i_2 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4))
+ (net N_230_2 (joined
+ (portRef O (instanceRef un8_ciin_2))
+ (portRef I1 (instanceRef un8_ciin_5))
))
- (net N_69_i_3 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5))
+ (net N_230_3 (joined
+ (portRef O (instanceRef un8_ciin_3))
+ (portRef I0 (instanceRef un8_ciin_6))
))
- (net N_69_i_4 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2))
+ (net N_230_4 (joined
+ (portRef O (instanceRef un8_ciin_4))
+ (portRef I1 (instanceRef un8_ciin_6))
))
- (net N_69_i_5 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2))
+ (net N_230_5 (joined
+ (portRef O (instanceRef un8_ciin_5))
+ (portRef I0 (instanceRef un8_ciin))
))
- (net (rename state_machine_un8_bgack_030_int_i_0_0_1 "state_machine.un8_bgack_030_int_i_0_0_1") (joined
- (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_o3_1))
- (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_o3))
- ))
- (net N_72_0_1 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_1_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_1))
- ))
- (net N_51_0_1 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_1))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i))
- ))
- (net N_51_0_2 (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i_2))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_2_i))
+ (net N_230_6 (joined
+ (portRef O (instanceRef un8_ciin_6))
+ (portRef I1 (instanceRef un8_ciin))
))
(net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined
(portRef O (instanceRef cpu_est_ns_0_0_1_1))
@@ -2597,50 +2608,54 @@
(portRef O (instanceRef cpu_est_ns_0_0_2_1))
(portRef I1 (instanceRef cpu_est_ns_0_0_1))
))
- (net N_128_1 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a3_1_5))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5))
+ (net N_122_1 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_1))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_3))
))
- (net N_128_2 (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_a3_2_5))
- (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_5))
+ (net N_122_2 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_2))
+ (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_3))
))
- (net N_118_1 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_3))
+ (net N_122_3 (joined
+ (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_3))
+ (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3))
))
- (net N_118_2 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2))
- (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_3))
- ))
- (net N_118_3 (joined
- (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_3))
- (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3))
- ))
- (net N_206_1 (joined
+ (net N_115_1 (joined
(portRef O (instanceRef state_machine_un10_bg_030_0_a3_1))
(portRef I0 (instanceRef state_machine_un10_bg_030_0_a3))
))
- (net N_206_2 (joined
+ (net N_115_2 (joined
(portRef O (instanceRef state_machine_un10_bg_030_0_a3_2))
(portRef I1 (instanceRef state_machine_un10_bg_030_0_a3))
))
- (net (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (joined
- (portRef O (instanceRef SM_AMIGA_ns_0_1_0))
- (portRef I0 (instanceRef SM_AMIGA_ns_0_0))
+ (net (rename state_machine_un10_clk_000_d0_1 "state_machine.un10_clk_000_d0_1") (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_0_1))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_0))
+ ))
+ (net (rename state_machine_un10_clk_000_d0_2 "state_machine.un10_clk_000_d0_2") (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_0_2))
+ (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_0))
+ ))
+ (net N_133_1 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_a3_1_5))
+ (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5))
+ ))
+ (net N_133_2 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_0_a3_2_5))
+ (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_5))
+ ))
+ (net N_143_1 (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_1))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0))
))
(net (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (joined
(portRef O (instanceRef cpu_est_ns_0_0_1_2))
(portRef I0 (instanceRef cpu_est_ns_0_0_2))
))
- (net N_53_0_1 (joined
+ (net N_55_0_1 (joined
(portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_1))
(portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i))
))
- (net N_43_i_1 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_1_7))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_7))
- ))
(net (rename state_machine_LDS_000_INT_7_0_1 "state_machine.LDS_000_INT_7_0_1") (joined
(portRef O (instanceRef state_machine_LDS_000_INT_7_0_1))
(portRef I0 (instanceRef state_machine_LDS_000_INT_7_0))
@@ -2649,31 +2664,31 @@
(portRef O (instanceRef state_machine_UDS_000_INT_7_0_1))
(portRef I0 (instanceRef state_machine_UDS_000_INT_7_0))
))
- (net N_199_0_1 (joined
+ (net N_196_0_1 (joined
(portRef O (instanceRef un1_AS_030_2_i_1))
(portRef I0 (instanceRef un1_AS_030_2_i))
))
- (net N_152_1 (joined
+ (net N_155_1 (joined
(portRef O (instanceRef SM_AMIGA_ns_i_a2_1_4))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a2_4))
))
- (net N_147_1 (joined
+ (net N_148_1 (joined
(portRef O (instanceRef un3_dtack_i_a3_1))
(portRef I0 (instanceRef un3_dtack_i_a3))
))
- (net N_139_1 (joined
- (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3_1))
- (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3))
+ (net N_142_1 (joined
+ (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3_1))
+ (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3))
))
- (net N_137_1 (joined
+ (net N_140_1 (joined
(portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1))
(portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0))
))
- (net N_127_1 (joined
+ (net N_132_1 (joined
(portRef O (instanceRef SM_AMIGA_ns_i_a3_0_1_4))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_4))
))
- (net N_120_1 (joined
+ (net N_124_1 (joined
(portRef O (instanceRef state_machine_LDS_000_INT_7_0_a3_1))
(portRef I0 (instanceRef state_machine_LDS_000_INT_7_0_a3))
))
@@ -2681,57 +2696,29 @@
(portRef O (instanceRef state_machine_A0_DMA_2_0_a3_1))
(portRef I0 (instanceRef state_machine_A0_DMA_2_0_a3))
))
- (net N_116_1 (joined
+ (net N_120_1 (joined
+ (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_a3_0_1))
+ (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a3_0))
+ ))
+ (net N_118_1 (joined
(portRef O (instanceRef un1_AS_030_2_i_a3_0_1))
(portRef I0 (instanceRef un1_AS_030_2_i_a3_0))
))
- (net N_115_1 (joined
+ (net N_117_1 (joined
(portRef O (instanceRef un1_AS_030_2_i_a3_1))
(portRef I0 (instanceRef un1_AS_030_2_i_a3))
))
- (net (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0))
+ (net N_116_1 (joined
+ (portRef O (instanceRef un1_bgack_030_int_d_i_a3_1))
+ (portRef I0 (instanceRef un1_bgack_030_int_d_i_a3))
))
- (net N_203_1 (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_1))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3))
+ (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (joined
+ (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1))
+ (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3))
))
- (net (rename state_machine_UDS_000_INT_7_0_m3_un3 "state_machine.UDS_000_INT_7_0_m3.un3") (joined
- (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_r))
- (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_n))
- ))
- (net (rename state_machine_UDS_000_INT_7_0_m3_un1 "state_machine.UDS_000_INT_7_0_m3.un1") (joined
- (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_m))
- (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_p))
- ))
- (net (rename state_machine_UDS_000_INT_7_0_m3_un0 "state_machine.UDS_000_INT_7_0_m3.un0") (joined
- (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_n))
- (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_p))
- ))
- (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined
- (portRef O (instanceRef DSACK1_INT_0_r))
- (portRef I1 (instanceRef DSACK1_INT_0_n))
- ))
- (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined
- (portRef O (instanceRef DSACK1_INT_0_m))
- (portRef I0 (instanceRef DSACK1_INT_0_p))
- ))
- (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined
- (portRef O (instanceRef DSACK1_INT_0_n))
- (portRef I1 (instanceRef DSACK1_INT_0_p))
- ))
- (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined
- (portRef O (instanceRef VMA_INT_0_r))
- (portRef I1 (instanceRef VMA_INT_0_n))
- ))
- (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined
- (portRef O (instanceRef VMA_INT_0_m))
- (portRef I0 (instanceRef VMA_INT_0_p))
- ))
- (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined
- (portRef O (instanceRef VMA_INT_0_n))
- (portRef I1 (instanceRef VMA_INT_0_p))
+ (net N_204_1 (joined
+ (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_1))
+ (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3))
))
(net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined
(portRef O (instanceRef BGACK_030_INT_0_r))
@@ -2745,6 +2732,66 @@
(portRef O (instanceRef BGACK_030_INT_0_n))
(portRef I1 (instanceRef BGACK_030_INT_0_p))
))
+ (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined
+ (portRef O (instanceRef AS_000_DMA_0_r))
+ (portRef I1 (instanceRef AS_000_DMA_0_n))
+ ))
+ (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined
+ (portRef O (instanceRef AS_000_DMA_0_m))
+ (portRef I0 (instanceRef AS_000_DMA_0_p))
+ ))
+ (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined
+ (portRef O (instanceRef AS_000_DMA_0_n))
+ (portRef I1 (instanceRef AS_000_DMA_0_p))
+ ))
+ (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined
+ (portRef O (instanceRef DS_000_DMA_0_r))
+ (portRef I1 (instanceRef DS_000_DMA_0_n))
+ ))
+ (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined
+ (portRef O (instanceRef DS_000_DMA_0_m))
+ (portRef I0 (instanceRef DS_000_DMA_0_p))
+ ))
+ (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined
+ (portRef O (instanceRef DS_000_DMA_0_n))
+ (portRef I1 (instanceRef DS_000_DMA_0_p))
+ ))
+ (net (rename CLK_030_H_0_un3 "CLK_030_H_0.un3") (joined
+ (portRef O (instanceRef CLK_030_H_0_r))
+ (portRef I1 (instanceRef CLK_030_H_0_n))
+ ))
+ (net (rename CLK_030_H_0_un1 "CLK_030_H_0.un1") (joined
+ (portRef O (instanceRef CLK_030_H_0_m))
+ (portRef I0 (instanceRef CLK_030_H_0_p))
+ ))
+ (net (rename CLK_030_H_0_un0 "CLK_030_H_0.un0") (joined
+ (portRef O (instanceRef CLK_030_H_0_n))
+ (portRef I1 (instanceRef CLK_030_H_0_p))
+ ))
+ (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined
+ (portRef O (instanceRef RW_000_INT_0_r))
+ (portRef I1 (instanceRef RW_000_INT_0_n))
+ ))
+ (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined
+ (portRef O (instanceRef RW_000_INT_0_m))
+ (portRef I0 (instanceRef RW_000_INT_0_p))
+ ))
+ (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined
+ (portRef O (instanceRef RW_000_INT_0_n))
+ (portRef I1 (instanceRef RW_000_INT_0_p))
+ ))
+ (net (rename state_machine_UDS_000_INT_7_0_m3_un3 "state_machine.UDS_000_INT_7_0_m3.un3") (joined
+ (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_r))
+ (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_n))
+ ))
+ (net (rename state_machine_UDS_000_INT_7_0_m3_un1 "state_machine.UDS_000_INT_7_0_m3.un1") (joined
+ (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_m))
+ (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_p))
+ ))
+ (net (rename state_machine_UDS_000_INT_7_0_m3_un0 "state_machine.UDS_000_INT_7_0_m3.un0") (joined
+ (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_n))
+ (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_p))
+ ))
(net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined
(portRef O (instanceRef IPL_030_0_0__r))
(portRef I1 (instanceRef IPL_030_0_0__n))
@@ -2817,18 +2864,6 @@
(portRef O (instanceRef cpu_estse_2_n))
(portRef I1 (instanceRef cpu_estse_2_p))
))
- (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n))
- ))
- (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m))
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p))
- ))
- (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined
- (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n))
- (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p))
- ))
(net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined
(portRef O (instanceRef AS_030_000_SYNC_0_r))
(portRef I1 (instanceRef AS_030_000_SYNC_0_n))
@@ -2841,18 +2876,6 @@
(portRef O (instanceRef AS_030_000_SYNC_0_n))
(portRef I1 (instanceRef AS_030_000_SYNC_0_p))
))
- (net (rename CLK_030_H_0_un3 "CLK_030_H_0.un3") (joined
- (portRef O (instanceRef CLK_030_H_0_r))
- (portRef I1 (instanceRef CLK_030_H_0_n))
- ))
- (net (rename CLK_030_H_0_un1 "CLK_030_H_0.un1") (joined
- (portRef O (instanceRef CLK_030_H_0_m))
- (portRef I0 (instanceRef CLK_030_H_0_p))
- ))
- (net (rename CLK_030_H_0_un0 "CLK_030_H_0.un0") (joined
- (portRef O (instanceRef CLK_030_H_0_n))
- (portRef I1 (instanceRef CLK_030_H_0_p))
- ))
(net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined
(portRef O (instanceRef UDS_000_INT_0_r))
(portRef I1 (instanceRef UDS_000_INT_0_n))
@@ -2889,6 +2912,18 @@
(portRef O (instanceRef FPU_CS_INT_0_n))
(portRef I1 (instanceRef FPU_CS_INT_0_p))
))
+ (net (rename avec_exp_0_un3 "avec_exp_0.un3") (joined
+ (portRef O (instanceRef avec_exp_0_r))
+ (portRef I1 (instanceRef avec_exp_0_n))
+ ))
+ (net (rename avec_exp_0_un1 "avec_exp_0.un1") (joined
+ (portRef O (instanceRef avec_exp_0_m))
+ (portRef I0 (instanceRef avec_exp_0_p))
+ ))
+ (net (rename avec_exp_0_un0 "avec_exp_0.un0") (joined
+ (portRef O (instanceRef avec_exp_0_n))
+ (portRef I1 (instanceRef avec_exp_0_p))
+ ))
(net (rename BG_000_0_un3 "BG_000_0.un3") (joined
(portRef O (instanceRef BG_000_0_r))
(portRef I1 (instanceRef BG_000_0_n))
@@ -2901,30 +2936,6 @@
(portRef O (instanceRef BG_000_0_n))
(portRef I1 (instanceRef BG_000_0_p))
))
- (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined
- (portRef O (instanceRef DS_000_DMA_0_r))
- (portRef I1 (instanceRef DS_000_DMA_0_n))
- ))
- (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined
- (portRef O (instanceRef DS_000_DMA_0_m))
- (portRef I0 (instanceRef DS_000_DMA_0_p))
- ))
- (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined
- (portRef O (instanceRef DS_000_DMA_0_n))
- (portRef I1 (instanceRef DS_000_DMA_0_p))
- ))
- (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined
- (portRef O (instanceRef AS_000_DMA_0_r))
- (portRef I1 (instanceRef AS_000_DMA_0_n))
- ))
- (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined
- (portRef O (instanceRef AS_000_DMA_0_m))
- (portRef I0 (instanceRef AS_000_DMA_0_p))
- ))
- (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined
- (portRef O (instanceRef AS_000_DMA_0_n))
- (portRef I1 (instanceRef AS_000_DMA_0_p))
- ))
(net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined
(portRef O (instanceRef AS_000_INT_0_r))
(portRef I1 (instanceRef AS_000_INT_0_n))
@@ -2937,6 +2948,30 @@
(portRef O (instanceRef AS_000_INT_0_n))
(portRef I1 (instanceRef AS_000_INT_0_p))
))
+ (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined
+ (portRef O (instanceRef DSACK1_INT_0_r))
+ (portRef I1 (instanceRef DSACK1_INT_0_n))
+ ))
+ (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined
+ (portRef O (instanceRef DSACK1_INT_0_m))
+ (portRef I0 (instanceRef DSACK1_INT_0_p))
+ ))
+ (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined
+ (portRef O (instanceRef DSACK1_INT_0_n))
+ (portRef I1 (instanceRef DSACK1_INT_0_p))
+ ))
+ (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined
+ (portRef O (instanceRef VMA_INT_0_r))
+ (portRef I1 (instanceRef VMA_INT_0_n))
+ ))
+ (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined
+ (portRef O (instanceRef VMA_INT_0_m))
+ (portRef I0 (instanceRef VMA_INT_0_p))
+ ))
+ (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined
+ (portRef O (instanceRef VMA_INT_0_n))
+ (portRef I1 (instanceRef VMA_INT_0_p))
+ ))
)
(property orig_inst_of (string "BUS68030"))
)
diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse
index 2d57677..78a2dab 100644
--- a/Logic/BUS68030.fse
+++ b/Logic/BUS68030.fse
@@ -1,46 +1,46 @@
-fsm_encoding {723322331} onehot
+fsm_encoding {7129321291} onehot
-fsm_state_encoding {723322331} idle_p {00000001}
+fsm_state_encoding {7129321291} idle_p {00000001}
-fsm_state_encoding {723322331} idle_n {00000010}
+fsm_state_encoding {7129321291} idle_n {00000010}
-fsm_state_encoding {723322331} as_set_p {00000100}
+fsm_state_encoding {7129321291} as_set_p {00000100}
-fsm_state_encoding {723322331} as_set_n {00001000}
+fsm_state_encoding {7129321291} as_set_n {00001000}
-fsm_state_encoding {723322331} sample_dtack_p {00010000}
+fsm_state_encoding {7129321291} sample_dtack_p {00010000}
-fsm_state_encoding {723322331} data_fetch_n {00100000}
+fsm_state_encoding {7129321291} data_fetch_n {00100000}
-fsm_state_encoding {723322331} data_fetch_p {01000000}
+fsm_state_encoding {7129321291} data_fetch_p {01000000}
-fsm_state_encoding {723322331} end_cycle_n {10000000}
+fsm_state_encoding {7129321291} end_cycle_n {10000000}
-fsm_registers {723322331} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]}
+fsm_registers {7129321291} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]}
-fsm_encoding {7117341172} original
+fsm_encoding {7120341202} original
-fsm_state_encoding {7117341172} e20 {0000}
+fsm_state_encoding {7120341202} e20 {0000}
-fsm_state_encoding {7117341172} e5 {0010}
+fsm_state_encoding {7120341202} e5 {0010}
-fsm_state_encoding {7117341172} e6 {0011}
+fsm_state_encoding {7120341202} e6 {0011}
-fsm_state_encoding {7117341172} e3 {0100}
+fsm_state_encoding {7120341202} e3 {0100}
-fsm_state_encoding {7117341172} e4 {0101}
+fsm_state_encoding {7120341202} e4 {0101}
-fsm_state_encoding {7117341172} e1 {0110}
+fsm_state_encoding {7120341202} e1 {0110}
-fsm_state_encoding {7117341172} e2 {0111}
+fsm_state_encoding {7120341202} e2 {0111}
-fsm_state_encoding {7117341172} e7 {1010}
+fsm_state_encoding {7120341202} e7 {1010}
-fsm_state_encoding {7117341172} e8 {1011}
+fsm_state_encoding {7120341202} e8 {1011}
-fsm_state_encoding {7117341172} e9 {1100}
+fsm_state_encoding {7120341202} e9 {1100}
-fsm_state_encoding {7117341172} e10 {1111}
+fsm_state_encoding {7120341202} e10 {1111}
-fsm_registers {7117341172} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]}
+fsm_registers {7120341202} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]}
diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf
index 4ccf646..a5c62d1 100644
--- a/Logic/BUS68030.naf
+++ b/Logic/BUS68030.naf
@@ -1,5 +1,6 @@
AS_030 b
AS_000 b
+RW_000 b
DS_030 b
UDS_000 b
LDS_000 b
@@ -40,8 +41,7 @@ IPL_030[0] o
IPL[2] i
IPL[1] i
IPL[0] i
-DSACK[1] b
-DSACK[0] b
+DSACK1 b
DTACK b
AVEC o
AVEC_EXP b
@@ -50,7 +50,7 @@ VPA i
VMA o
RST i
RESET o
-RW i
+RW b
FC[1] i
FC[0] i
AMIGA_BUS_ENABLE o
diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj
index a1cdb76..e1cd2cd 100644
--- a/Logic/BUS68030.prj
+++ b/Logic/BUS68030.prj
@@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Thu May 29 22:04:20 2014
+#-- Written on Sun Jun 01 01:03:18 2014
#device options
diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm
index 1cee750..245e4b6 100644
--- a/Logic/BUS68030.srm
+++ b/Logic/BUS68030.srm
@@ -223,298 +223,190 @@ RNH3Ds0_HFsolMNCqR"1d_jj
RU@@::4(4(:4:qn:1j_jj1Rq_jjj;H
NR03sDs_FHNoMl"CRqj1_j;j"
RNH#_$M0#sH0CN0R
-4;L@R@UU:4:44:U::n7j1_d7jR1d_jjN;
-HsR30FD_sMHoNRlC"_71j"dj;H
+4;L@R@UU:4:44:U::n)jW_j)jRWj_jjN;
+HsR30FD_sMHoNRlC"_)Wj"jj;H
NRM#$_H0s#00NC;R4
-@LR@4U:g::44(g::1z7_jjjR1z7_jjj;H
-NR03sDs_FHNoMl"CRz_71j"jj;H
-NRM#$_H0s#00NC;R4
-@LR@.U:j::4.(j::1p7_jjjR1p7_jjj;H
-NR03sDs_FHNoMl"CRp_71j"jj;H
-NRM#$_H0s#00NC;R4
-@LR@.U:4::4.c4::Z1Q :r4j19RQrZ 49:jRZ1Q :r4j
-9;N3HRs_0DFosHMCNlRQ"1Z; "
-RNH3HC8VsNsNN$Ml'CR#CHx'N;
+@LR@4U:g::44ng::_71jRdj7j1_d
+j;N3HRs_0DFosHMCNlR1"7_jjd"N;
H$R#Ms_0HN#004CR;R
-H@:@U.4.:::..4r:qd44:nq9Rr:d44Rn9q4rd:94n;H
-NR03sDs_FHNoMl"CRq
-";N3HRCV8HNNss$lMNCNR''L;
-RU@@::.d4d:.:q.:jjRq;H
-NR03sDs_FHNoMl"CRq;j"
-RNH#_$M0#sH0CN0R
-4;H@R@Uc:.:.4:cj:4:XM uu_1qRB Mu X_q1uB
- ;N3HRs_0DFosHMCNlR "MX1u_u qB"F;
-RU@@::.646:.:Ac: R))A) );H
-NR03sDs_FHNoMl"CRA) )"N;
-H#R3DsbFHHo8sHR"M0Fk"N;
-HbR3FNs0Ds8HRk"F0
-";H@R@Un:.:.4:n::nAjt_dAjRtd_jjN;
-HsR30FD_sMHoNRlC"_Atj"dj;R
-F@:@U.4(:::.(nt:A_jjjR_Atj;jj
-RNH3Ds0_HFsolMNCAR"tj_jj
-";F@R@UU:.:.4:U::gABtqid_jjtRAq_Bij;dj
-RNH3Ds0_HFsolMNCAR"tiqB_jjd"H;
-RU@@::.g4g:.:Ag:tiqB_jjjRqAtBji_j
-j;N3HRs_0DFosHMCNlRt"Aq_Bij"jj;R
-H@:@Ud4j:::dj(p:Bid_jjpRBid_jjN;
-HsR30FD_sMHoNRlC"iBp_jjd"H;
-RU@@::d444:d:B(:pji_jBjRpji_j
-j;N3HRs_0DFosHMCNlRp"Bij_jj
-";H@R@U.:d:d4:.::UB_pimQ1ZRiBp_Zm1QN;
-HsR30FD_sMHoNRlC"iBp_Zm1Q
-";F@R@Ud:d:d4:d4:4:iBp_e7Q_amzRiBp_e7Q_amz;H
-NR03sDs_FHNoMl"CRB_pi7_Qem"za;R
-F@:@Ud4c:::dc(p:BiX_ upRBiX_ uN;
-HsR30FD_sMHoNRlC"iBp_u X"F;
-RU@@::d646:d:wn:uBz_1uRwz1_B;H
-NR03sDs_FHNoMl"CRw_uzB;1"
-@FR@dU:n::4d(n::pQu_jjdrj.:9uRQpd_jj:r.jQ9Rujp_d.jr:;j9
-RNH3Ds0_HFsolMNCQR"ujp_d;j"
-RNH3HC8VsNsNN$Ml'CRH_bDj'dj;R
-H@:@Ud4(:::d(du:Qp:r.jQ9Ru.pr:Rj9Qrup.9:j;H
-NR03sDs_FHNoMl"CRQ"up;H
-NR83CHsVNsMN$NRlC'DHb'L;
-RU@@::dU4U:d:76:1iqBrj4:91R7qrBi49:jRq71B4ir:;j9
-RNH3Ds0_HFsolMNC7R"1iqB"N;
-H#R3DsbFHHo8sHR"M0Fk"N;
-HCR38NHVs$sNMCNlR#'8N'O ;R
-L@:@Ud4g:::dg6a:7qRBi7BaqiN;
-HsR30FD_sMHoNRlC"q7aB;i"
-RNH#_$M0#sH0CN0R
-4;F@R@Uj:c:c4:j::cqBe R qeBN;
-HsR30FD_sMHoNRlC" qeB
-";F@R@U4:c:c4:4::UqBe _u XR qeBX_ uN;
-HsR30FD_sMHoNRlC" qeBX_ u
+L@:@U.4j:::.j(7:z1j_jj7Rz1j_jjN;
+HsR30FD_sMHoNRlC"1z7_jjj"N;
+H$R#Ms_0HN#004CR;R
+L@:@U.44:::.4(7:p1j_jj7Rp1j_jjN;
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+RoM)jW_jQj_hja_3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MWR)_jjj_aQh_kj3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoM)jW_jQj_hja_3jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+M0R#N_0ClENOH\MC31z7_jjj_aQh_j(__3ldk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRN#00lC_NHOEM3C\z_71j_jjQ_ha(__jlkd3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoM#00NCN_lOMEHCz\37j1_jQj_h(a__lj_dM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__3j_k;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_jj__M3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__3j_k;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_4j__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__34_k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_4j__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__3._k;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_.j__M3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__3._k;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C##jC_3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MbROk#_C0_#CjM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oOMRbCk_#C0#_kj3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMO_bkC##0C3_4k;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C##4C_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
+MbROk#_C0_#C4M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oOMRbCk_#C0#_k.3M
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMO_bkC##0C3_.k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C##.C_3jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+M1Rq_jjd_jjj_h1YB3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_q1j_djj_jj1BYh_kj3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMqj1_djj_j1j_Y_hBjM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ozMR7j1_jQj_hja_3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+M7Rz1j_jjh_Qa3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR1z7_jjj_aQh_kj3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMp_71j_jjQ_hajM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;opMR7j1_jQj_hja_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
+M7Rp1j_jjh_Qa3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRzwu__B1Q_hajM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;owMRuBz_1h_Qa3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRzwu__B1Q_hajM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oNMRP_COC_GbjM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oNMRP_COC_GbjM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oNMRP_COC_GbjM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oAMRtj_jj3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_Atj_jjjM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oAMRtj_jj3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_q1j_jjQ_hajM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oqMR1j_jjh_Qa3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_q1j_jjQ_hajM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o7MR1iqB4h_Qa3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRq71B_i4Q_hajM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o7MR1iqB4h_Qa3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRqev_aQh_kj3M
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMe_vqQ_hajM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oeMRvQq_hja_3jkM;M
+NRN3#PMC_CV0_D#No46R.nb;
+R4@@:44::.4:+:4.0CskR:fjjsR0k0CRsRkCe;BB
+@bR@44::44::4.+.N:VDR#Cfjj:RDVN#VCRNCD#R7th;R
+b@:@U4:.gd4.:.dg:c.+4:_1vqtvQq:rj(f9RjR:jo#EF0vR1_Qqvtjqr:R(9hg_4,.h_j_,h.h4,_,..hd_.,.h_c_,h.h6,_;.n
+RNH3Ds0CF_0R
+4;N#HR$VM_#Hl_8(R"4d.g.g4.4
";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
NR#3VlF_0#"0R1qv_vqQtR;U"
@@ -540,9 +540,9 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j
RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
NR#3Vl0_#Ns0CC4oR;H
NR03#N_0ClbNbHRMo"RRRjjjjj4jjRR->jjjjj4jj\RMRRjjjj4jjj>R-Rjjjj4jjjR\MRjRjj4jjj-jR>jRjj4jjjMj\RjRRj4jjjRjj-j>Rj4jjj\jjMRRRj4jjjjjjRR->j4jjjjjj\RMRR4jjjjjjj>R-R4jjjjjjjR\MR4Rjjjjjj-jR>4RjjjjjjMj\R4RRjjjjjRjj-4>Rjjjjj\jjM
-";b@R@U4:4(c:d:(44:+dn4O.:bCk_#j0r:94jR:fjjERoFR#0O_bkCr#0jj:49_Rh4,jchj_46_,h4,jnhj_4(_,h4,jUhj_4g_,h4,4jh4_44_,h4,4.h4_4d_,h4;4c
+";b@R@U.:4jc:d:j4.:+dn4O.:bCk_#j0r:94jR:fjjERoFR#0O_bkCr#0jj:49_Rh4,j.hj_4d_,h4,jchj_46_,h4,jnhj_4(_,h4,jUhj_4g_,h4,4jh4_44_,h4;4.
RNH3Ds0CF_0R
-4;N#HR$VM_#Hl_8(R"4d4(c(44.
+4;N#HR$VM_#Hl_8(R"4d.jcj4..
";N3HRs_0DFosHMCNlRb"Ok#_C0
";N#HR$CM_M8OFHRMo"HFsoNHMD
";N3HRV_#lVlsF#"0RO_bkCR#0c
@@ -551,13 +551,13 @@ NR#3VlN_0L#DC0jR"jRjjjjjjs4jjjjRj4jjsjR44j4j4sjj4j4Rjjjjs4Rj4j44js4j4j4Rj4jjs4R4
";N3HRV_#lFosHMCNlRb"Ok#_C0
";N3HRV_#l#00NCosCR
4;N3HR#00NCN_lbMbHoRR"RjRjjjjjjjjj4>R-RjjjjR\MRjRjjjjjj4jjj>R-R4jjjR\MRjRjjjjjjjj4j>R-R4jj4R\MRjRjjjjjjj4jj>R-Rjj4jR\MRjRjjjjj4jjjj>R-Rjj44R\MRjRjj4jjjjjjj>R-R4j4jR\MRjRjjjj4jjjjj>R-R4j44R\MRjRjjj4jjjjjj>R-R44jjR\MRjRj4jjjjjjjj>R-R44j4R\MR4Rjjjjjjjjjj>R-Rj44jR\MRjR4jjjjjjjjj>R-R4444"\M;R
-s@:@U4:4(d4c:4d(:n.+4:kOb_0C#r4j:jf9RjR:jlENORw7w)b]RsRHlO_bkCr#0jS9
+s@:@U4:.jd4c:.dj:n.+4:kOb_0C#r4j:jf9RjR:jlENORw7w)b]RsRHlO_bkCr#0jS9
Tb=Ok#_C09rj
-=S7hg_6_SH
+=S7hj_n_SH
B=piB_pimQ1Z_SO
)1=)a;_H
RNH3Ds0CF_0R
-4;N#HR$VM_#Hl_8(R"4d4(c(44.
+4;N#HR$VM_#Hl_8(R"4d.jcj4..
";N3HRs_0DFosHMCNlRb"Ok#_C0
";N#HR$CM_M8OFHRMo"HFsoNHMD
";N3HRV_#lVlsF#"0RO_bkCR#0c
@@ -566,13 +566,13 @@ NR#3VlN_0L#DC0jR"jRjjjjjjs4jjjjRj4jjsjR44j4j4sjj4j4Rjjjjs4Rj4j44js4j4j4Rj4jjs4R4
";N3HRV_#lFosHMCNlRb"Ok#_C0
";N3HRV_#l#00NCosCR
4;N3HRFosHH0M#MCNlRb'Ok#_C0:rj4'j9;R
-s@:@U4:4(d4c:4d(:n.+4:kOb_0C#r4j:jf9RjR:jlENORw7w)b]RsRHlO_bkCr#04S9
+s@:@U4:.jd4c:.dj:n.+4:kOb_0C#r4j:jf9RjR:jlENORw7w)b]RsRHlO_bkCr#04S9
Tb=Ok#_C09r4
=S7O_bkC_#0MC#_r
49SiBp=iBp_Zm1Q
_OS))=1Ha_;H
NR03sD0C_F;R4
-RNH#_$MV_#lH"8R((44d4c4(;."
+RNH#_$MV_#lH"8R(j4.d.c4j;."
RNH3Ds0_HFsolMNCOR"bCk_#;0"
RNH#_$MCFMO8oHMRs"FHMoHN;D"
RNH3lV#_FVslR#0"kOb_0C#R;c"
@@ -581,13 +581,13 @@ HVR3#0l_NCLD#"0RjjjjRjjjjjsj4jjRjs4jj4j4R4jj44sjjjjR4sjjj44jRjj444sj4jjR4s4jj444
RNH3lV#_HFsolMNCOR"bCk_#;0"
RNH3lV#_N#00CCso;R4
RNH3HFso#HM0lMNCOR'bCk_#j0r:94j's;
-RU@@:(44::dc4:4(d4n+.b:Ok#_C0:rj4Rj9fjj:ROlNEwR7wR)]blsHRkOb_0C#r
+RU@@:j4.::dc4:.jd4n+.b:Ok#_C0:rj4Rj9fjj:ROlNEwR7wR)]blsHRkOb_0C#r
.9SOT=bCk_#.0r97
S=kOb_0C#__M#C9r.
pSBip=Bi1_mZOQ_
=S))_1aHN;
HsR30_DC04FR;H
-NRM#$_lV#_RH8"4(4(4dc4"(.;H
+NRM#$_lV#_RH8".(4j4dc."j.;H
NR03sDs_FHNoMl"CRO_bkC"#0;H
NRM#$_OCMFM8HoFR"sHHoM"ND;H
NR#3Vls_VF0l#Rb"Ok#_C0"Rc;H
@@ -596,13 +596,13 @@ NR#3VlF_0#"0RO_bkCR#0c
NR#3Vls_FHNoMl"CRO_bkC"#0;H
NR#3Vl0_#Ns0CC4oR;H
NRs3FHMoH#N0Ml'CRO_bkCr#0jj:49
-';s@R@U4:4(c:d:(44:+dn4O.:bCk_#j0r:94jR:fjjNRlO7ERw]w)RHbslbROk#_C09rd
+';s@R@U.:4jc:d:j4.:+dn4O.:bCk_#j0r:94jR:fjjNRlO7ERw]w)RHbslbROk#_C09rd
=STO_bkCr#0dS9
7b=Ok#_C0#_M_dCr9B
SpBi=pmi_1_ZQO)
S=a)1_
H;N3HRsC0D_R0F4N;
-H$R#M#_Vl8_HR4"(4c(d4.4("N;
+H$R#M#_Vl8_HR4"(.cjd4..j"N;
HsR30FD_sMHoNRlC"kOb_0C#"N;
H$R#MM_COHF8M"oRFosHHDMN"N;
HVR3#Vl_s#Fl0OR"bCk_#c0R"N;
@@ -611,13 +611,98 @@ RNH3lV#_L0ND0C#Rj"jjjjRjsjjjjj4R4jjjjsj4j4Rjs44jj4jRjj4j4sjjj4R4sj4jj44R4j4j4sj4
HVR3#Fl_sMHoNRlC"kOb_0C#"N;
HVR3##l_0CN0sRCo4N;
HFR3sHHoMM#0NRlC'kOb_0C#r4j:j;9'
-@sR@dU:gcj::jdg:+..41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtjqr9T
+@sR@dU:Ucn::ndU:+..41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtjqr9T
S=_1vqtvQq9rj
-=S7hd_c_SH
+=S7hd_(_SH
B=piB_pimQ1Z_SO
)1=)a;_H
RNH3Ds0CF_0R
-4;N#HR$VM_#Hl_8(R"..dd.4dd"N;
+4;N#HR$VM_#Hl_8(R"4d.g.g4.4
+";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
+NR#3VlF_0#"0R1qv_vqQtR;U"
+RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
+RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vl0_#Ns0CC4oR;H
+NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
+';s@R@Uj:4.n:d:.4j:+dU41.:Q_Z 7rvq49:jR:fjjNRlO7ERw]w1RHbslQR1Z7 _v4qr9T
+S=Z1Q v_7q9r4
+=S7#00NCN_lOMEHC1\3Q_Z 7_vqc9r4
+pSBip=Bi1_mZOQ_
+=S1)_1aHN;
+HsR30FD_sMHoNRlC"Z1Q v_7q
+";N3HRksMVNHO_MG8CR
+4;N3HR#_$MH0MHPRND";4"
+@sR@4U:jd.:nj:4.U:d+:4.Q_upjrdj.9:jR:fjjNRlO7ERw]w1RHbsluRQpd_jjw7w1j]r9T
+S=pQu_jjd_jOr97
+S=4h_nB
+SpBi=pmi_1_ZQO1
+S=a)1_
+H;N3HRs_0DFosHMCNlRu"Qpd_jj
+";N3HRksMVNHO_MG8CR
+j;s@R@Uj:4.n:d:.4j:+dU4Q.:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9r4
+=STQ_upj_djO9r4
+=S7h(_4
+pSBip=Bi1_mZOQ_
+=S1)_1aHN;
+HsR30FD_sMHoNRlC"pQu_jjd"N;
+HkR3MNVsOM_H8RCG4s;
+RU@@:.4j::dn4:j.d4U+.u:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r
+.9SQT=ujp_dOj_r
+.9Sh7=_
+4USiBp=iBp_Zm1Q
+_OS)1=1Ha_;H
+NR03sDs_FHNoMl"CRQ_upj"dj;H
+NRM3kVOsN_8HMC.GR;R
+s@:@U.:nc..(:ncc:c.+4:_1vqtvQq:rj(f9RjR:jlENORw7w1b]RsRHl1qv_vqQtr
+(9S1T=vv_qQrtq(S9
+7v=1_QqvtMq_#9rj
+pSBip=Bi1_mZOQ_
+=S1)_1aHN;
+HsR30_DC04FR;H
+NRM#$_lV#_RH8".(4g4d.."g4;H
+NR03sDs_FHNoMl"CR1qv_vqQt"N;
+HVR3#Vl_s#Fl01R"vv_qQRtqd
+";N3HRV_#l00F#Rv"1_QqvtUqR"N;
+HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
+HVR3#Fl_sMHoNRlC"_1vqtvQq
+";N3HRV_#l#00NCosCR
+4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
+s@:@Ud:.cc.:dcg:4+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqnS9
+Tv=1_Qqvtnqr97
+S=nh_6
+_HSiBp=iBp_Zm1Q
+_OS))=1Ha_;H
+NR03sD0C_F;R4
+RNH#_$MV_#lH"8R(g4.d..4g;4"
+RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vls_VF0l#Rv"1_QqvtdqR"N;
+HVR3#0l_FR#0"_1vqtvQq"RU;H
+NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H
+NR#3Vls_FHNoMl"CR1qv_vqQt"N;
+HVR3##l_0CN0sRCo4N;
+HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9'
+@sR@dU:.cg::gd.:+.j41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvt6qr9T
+S=_1vqtvQq9r6
+=S71qv_vqQt_rM#.S9
+B=piB_pimQ1Z_SO
+)1=)a;_H
+RNH3Ds0CF_0R
+4;N#HR$VM_#Hl_8(R"4d.g.g4.4
+";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
+NR#3VlF_0#"0R1qv_vqQtR;U"
+RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
+RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vl0_#Ns0CC4oR;H
+NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
+';s@R@U6:dj::cd:6j.4j+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rc
+=ST1qv_vqQtr
+c9Sh7=__nUHB
+SpBi=pmi_1_ZQO)
+S=a)1_
+H;N3HRsC0D_R0F4N;
+H$R#M#_Vl8_HR4"(..gd44.g"N;
HsR30FD_sMHoNRlC"_1vqtvQq
";N3HRV_#lVlsF#"0R1qv_vqQtR;d"
RNH3lV#_#0F01R"vv_qQRtqU
@@ -625,70 +710,41 @@ RNH3lV#_#0F01R"vv_qQRtqU
";N3HRV_#lFosHMCNlRv"1_Qqvt;q"
RNH3lV#_N#00CCso;R4
RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s;
-RU@@::ggdgn:gU:d+:4.1 QZ_q7vrj4:9jRf:ljRNROE71ww]sRbH1lRQ_Z 7rvq4S9
-TQ=1Z7 _v4qr97
-S=N#00lC_NHOEM3C\1 QZ_q7v_4cr9B
-SpBi=pmi_1_ZQO1
-S=a)1_
-H;N3HRs_0DFosHMCNlRQ"1Z7 _v;q"
-RNH3VkMs_NOHCM8G;R4
-RNH3M#$_HHM0DPNR""4;R
-s@:@Ugdg:ng:g:+dU4Q.:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9rj
-=STQ_upj_djO9rj
-=S7h6_4
+RU@@:ndn:dc:n.n:c.+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr
+d9S1T=vv_qQrtqdS9
+7_=hcH6_
pSBip=Bi1_mZOQ_
-=S1)_1aHN;
-HsR30FD_sMHoNRlC"pQu_jjd"N;
-HkR3MNVsOM_H8RCGjs;
-RU@@::ggdgn:gU:d+:4.Q_upjrdj.9:jR:fjjNRlO7ERw]w1RHbsluRQpd_jjw7w14]r9T
-S=pQu_jjd_4Or97
-S=4h_nB
-SpBi=pmi_1_ZQO1
-S=a)1_
-H;N3HRs_0DFosHMCNlRu"Qpd_jj
-";N3HRksMVNHO_MG8CR
-4;s@R@Ug:g::dngdg:U.+4:pQu_jjdrj.:9jRf:ljRNROE71ww]sRbHQlRujp_dwj7wr1].S9
-Tu=Qpd_jjr_O.S9
-7_=h4S(
-B=piB_pimQ1Z_SO
-11=)a;_H
-RNH3Ds0_HFsolMNCQR"ujp_d;j"
-RNH3VkMs_NOHCM8G;R.
-@sR@.U:n.U:(n:.Uc:c+:4.1qv_vqQtr(j:9jRf:ljRNROE71ww]sRbH1lRvv_qQrtq(S9
-Tv=1_Qqvt(qr97
+=S))_1aHN;
+HsR30_DC04FR;H
+NRM#$_lV#_RH8".(4g4d.."g4;H
+NR03sDs_FHNoMl"CR1qv_vqQt"N;
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+HVR3#Fl_sMHoNRlC"_1vqtvQq
+";N3HRV_#l#00NCosCR
+4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
+s@:@Ud:(dc(:dd.:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq.S9
+Tv=1_Qqvt.qr97
S=_1vqtvQq#_Mr
-j9SiBp=iBp_Zm1Q
-_OS)1=1Ha_;H
-NR03sD0C_F;R4
-RNH#_$MV_#lH"8R(d.d.d.d4
-";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
-RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
-NR#3VlF_0#"0R1qv_vqQtR;U"
-RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
-RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
-NR#3Vl0_#Ns0CC4oR;H
-NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
-';s@R@U.:dj::cd:.j44g+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rn
-=ST1qv_vqQtr
-n9Sh7=__dcHB
-SpBi=pmi_1_ZQO)
-S=a)1_
-H;N3HRsC0D_R0F4N;
-H$R#M#_Vl8_HR."(d.d.d"d4;H
-NR03sDs_FHNoMl"CR1qv_vqQt"N;
-HVR3#Vl_s#Fl01R"vv_qQRtqd
-";N3HRV_#l00F#Rv"1_QqvtUqR"N;
-HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
-HVR3#Fl_sMHoNRlC"_1vqtvQq
-";N3HRV_#l#00NCosCR
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-s@:@Ud:d4cd:d4j:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq6S9
-Tv=1_Qqvt6qr97
-S=(h_d
-_HSiBp=iBp_Zm1Q
+69SiBp=iBp_Zm1Q
_OS))=1Ha_;H
NR03sD0C_F;R4
-RNH#_$MV_#lH"8R(d.d.d.d4
+RNH#_$MV_#lH"8R(g4.d..4g;4"
+RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vls_VF0l#Rv"1_QqvtdqR"N;
+HVR3#0l_FR#0"_1vqtvQq"RU;H
+NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H
+NR#3Vls_FHNoMl"CR1qv_vqQt"N;
+HVR3##l_0CN0sRCo4N;
+HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9'
+@sR@dU:(cg::gd(:+.d41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvt4qr9T
+S=_1vqtvQq9r4
+=S71qv_vqQt_rM#nS9
+B=piB_pimQ1Z_SO
+)1=)a;_H
+RNH3Ds0CF_0R
+4;N#HR$VM_#Hl_8(R"4d.g.g4.4
";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
NR#3VlF_0#"0R1qv_vqQtR;U"
@@ -696,1419 +752,1435 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j
RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
NR#3Vl0_#Ns0CC4oR;H
NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
-';s@R@U6:d4::cd:64.4j+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rc
-=ST1qv_vqQtr
-c9Sh7=__(6HB
-SpBi=pmi_1_ZQO)
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-H$R#M#_Vl8_HR."(d.d.d"d4;H
-NR03sDs_FHNoMl"CR1qv_vqQt"N;
-HVR3#Vl_s#Fl01R"vv_qQRtqd
-";N3HRV_#l00F#Rv"1_QqvtUqR"N;
-HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
-HVR3#Fl_sMHoNRlC"_1vqtvQq
-";N3HRV_#l#00NCosCR
-4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
-s@:@Ud:n(cn:d(c:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqdS9
-Tv=1_Qqvtdqr97
-S=dh_U
-_HSiBp=iBp_Zm1Q
-_OS))=1Ha_;H
-NR03sD0C_F;R4
-RNH#_$MV_#lH"8R(d.d.d.d4
-";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
-RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
-NR#3VlF_0#"0R1qv_vqQtR;U"
-RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
-RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
-NR#3Vl0_#Ns0CC4oR;H
-NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
-';s@R@U(:dc::cd:(c.4.+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r.
-=ST1qv_vqQtr
-.9S17=vv_qQ_tqM6#r9B
-SpBi=pmi_1_ZQO)
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-H$R#M#_Vl8_HR."(d.d.d"d4;H
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-HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
-HVR3#Fl_sMHoNRlC"_1vqtvQq
-";N3HRV_#l#00NCosCR
-4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
-s@:@Ud:(Uc(:dUd:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq4S9
-Tv=1_Qqvt4qr97
-S=ch_4B
-SpBi=pmi_1_ZQO)
-S=a)1_
-H;N3HRsC0D_R0F4N;
-H$R#M#_Vl8_HR."(d.d.d"d4;H
-NR03sDs_FHNoMl"CR1qv_vqQt"N;
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-";N3HRV_#l00F#Rv"1_QqvtUqR"N;
-HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
-HVR3#Fl_sMHoNRlC"_1vqtvQq
-";N3HRV_#l#00NCosCR
-4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
-s@:@Ugdg:ng:g:+dU47.:1iqB4h_QajRf:ljRNROE71ww]sRbH7lR1iqB4h_QaT
+';s@R@Uj:4.n:d:.4j:+dU47.:1iqB4h_QajRf:ljRNROE71ww]sRbH7lR1iqB4h_QaT
S=q71B_i4Q
haSh7=_
-44SiBp=iBp_Zm1Q
-_OS)1=1Ha_;H
-NR03sDs_FHNoMl"CR7B1qiQ4_h;a"
-RNH3M#$_HHM0DPNR""4;H
-NRM3H_FDFb;Rg
-@sR@4U:46.:d4:4.n:6+:4.e_vqQRhafjj:ROlNEwR7wR1]blsHRqev_aQh
-=STe_vqQ
-haSh7=_
4.SiBp=iBp_Zm1Q
_OS)1=1Ha_;H
-NR03sDs_FHNoMl"CRe_vqQ"ha;H
-NR$3#MM_HHN0PD4R""N;
-HHR3MF_DF4bRjs;
-RU@@:.44::6d4:4.64n+.t:Aq_Bij_djQRhafjj:ROlNEwR7wR1]blsHRqAtBji_dQj_hSa
-Tt=Aq_Bij_djQ
-haSh7=_
-4dSiBp=iBp_Zm1Q
-_OS)1=1Ha_;H
-NR03sDs_FHNoMl"CRABtqid_jjh_Qa
-";N3HR#_$MH0MHPRND";4"
-RNH3_HMDbFFR
-n;s@R@U4:4cU:d:c44:+cj4B.:pmi_zua_). _6jRf:ljRNROE7)ww]sRbHBlRpmi_zua_). _6T
-S=iBp_amz_ u)_
-.6Sh7=_
-4cSiBp=iBp_Zm1Q
-_OS))=1Ha_;H
-NR03sDs_FHNoMl"CRB_pim_zau_) .;6"
+NR03sDs_FHNoMl"CR7B1qiQ4_h;a"
RNH3M#$_HHM0DPNR""4;H
-NRM3H_FDFb;R(
-@sR@gU:gn:d::ggd4U+.Q:1Z7 _v4qr:Rj9fjj:ROlNEwR7wR1]blsHRZ1Q v_7q9rj
-=ST1 QZ_q7vr
-j9Sh7=_44._SH
-B=piB_pimQ1Z_SO
-11=)a;_H
-RNH3Ds0_HFsolMNC1R"Q_Z 7"vq;H
-NRM3kVOsN_8HMCjGR;H
-NR$3#MM_HHN0PD4R""s;
-RU@@:d.d:..:ddd:+:4.z_71j_jjQRhafjj:ROlNEwR7wR1]blsHR1z7_jjj_aQh
-=STz_71j_jjQ
-haSh7=_Sc
-B=piB_pimQ1Z_SO
-11=)a;_H
-RNH3Ds0_HFsolMNCzR"7j1_jQj_h;a"
-RNH3M#$_HHM0DPNR""4;H
-NRM3H_FDFb;Rd
-@sR@.U:d.d::d.d:4d+.7:p1j_jjh_QajRf:ljRNROE71ww]sRbHplR7j1_jQj_hSa
-T7=p1j_jjh_Qa7
-S=6h_
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+s@:@U4:4664d:466:n.+4:qev_aQhR:fjjNRlO7ERw]w1RHbslvReqh_QaT
+S=qev_aQh
+=S7hd_4
pSBip=Bi1_mZOQ_
=S1)_1aHN;
-HsR30FD_sMHoNRlC"1p7_jjj_aQh"N;
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H#R3$HM_MPH0N"DR4
-";N3HRHDM_FRFbcs;
-RU@@:.44::6d4:4.64n+.u:wz1_B_aQhR:fjjNRlO7ERw]w1RHbsluRwz1_B_aQh
-=STw_uzBQ1_hSa
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+haSAT=tiqB_jjd_aQh
+=S7hc_4
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+=S1)_1aHN;
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+Tp=Biz_ma)_u 6_.
+=S7h6_4
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+=S))_1aHN;
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SpBi=pmi_1_ZQO1
S=a)1_
-H;N3HRs_0DFosHMCNlRu"wz1_B_aQh"N;
-H#R3$HM_MPH0N"DR4
-";N3HRHDM_FRFbUs;
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-S=_Atj_jjO7
-S=(h_
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+S=1p7_jjj_aQh
+=S7h
+_6SiBp=iBp_Zm1Q
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pSBip=Bi1_mZOQ_
=S1)_1aHN;
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-=ST7j1_j7j_vSq
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+=STNOPC_bCG
+=S7h
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+.;s@R@U4:46d:6:644:+6n4A.:tj_jjjRf:ljRNROE71ww]sRbHAlRtj_jjw7w1S]
+Tt=A_jjj_SO
7_=hUB
SpBi=pmi_1_ZQO1
S=a)1_
-H;N3HRs_0DFosHMCNlR1"7_jjj_q7v"N;
+H;N3HRs_0DFosHMCNlRt"A_jjj"N;
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+s@:@U4:j.d4n:jd.:U.+4:_71j_jj7Rvqfjj:ROlNEwR7wR1]blsHR_71j_jj7
+vqS7T=1j_jjv_7q7
+S=gh_
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+=S1)_1aHN;
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+HHR3MF_DFjbR;R
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+vqSqT=1j_jjv_7q7
+S=4h_jB
+SpBi=pmi_1_ZQO1
+S=a)1_
+H;N3HRs_0DFosHMCNlR1"q_jjj_q7v"N;
H#R3$HM_MPH0N"DR4
";N3HRHDM_FRFbjs;
-RU@@::ggdgn:gU:d+:4.qj1_j7j_vfqRjR:jlENORw7w1b]RsRHlqj1_j7j_vSq
-T1=q_jjj_q7v
-=S7h
-_gSiBp=iBp_Zm1Q
-_OS)1=1Ha_;H
-NR03sDs_FHNoMl"CRqj1_j7j_v;q"
-RNH3M#$_HHM0DPNR""4;H
-NRM3H_FDFb;Rj
-@sR@.U:d.d::d.d:4d+.1:q_jjj_aQhR:fjjNRlO7ERw]w1RHbsl1Rq_jjj_aQh
+RU@@:g4.::d.4:.gd4c+.1:q_jjj_aQhR:fjjNRlO7ERw]w1RHbsl1Rq_jjj_aQh
=STqj1_jQj_hSa
-7_=h4Sj
+7_=h4S4
B=piB_pimQ1Z_SO
11=)a;_H
RNH3Ds0_HFsolMNCqR"1j_jjh_Qa
";N3HR#_$MH0MHPRND";4"
RNH3_HMDbFFR
-4;s@R@Ug:g::dngdg:U.+4:QqvtAq_z 1_hpqA jRf:ljRNROE71ww]sRbHqlRvqQt_1Az_q hA7p w]w1
-=STqtvQqz_A1h_ q Ap_SO
-7_=h4B
-SpBi=pmi_1_ZQO1
-S=a)1_
-H;N3HRs_0DFosHMCNlRv"qQ_tqA_z1 Ahqp; "
-RNH3_HMDbFFR;44
-@sR@.U:d.d::d.d:4d+.1:q_jjd_jjj_h1YBjRf:ljRNROE71ww]sRbHqlR1d_jjj_jjY_1hSB
-T1=q_jjd_jjj_h1YB7
-S=.h_
-pSBip=Bi1_mZOQ_
-=S1)_1aHN;
-HsR30FD_sMHoNRlC"_q1j_djj_jj1BYh"N;
-H#R3$HM_MPH0N"DR4
-";s@R@Ug:g::dngdg:U.+4:iBp_jjd_f]RjR:jlENORw7wRHbslpRBid_jj
-_]SBT=pji_d]j_
-=S7h
-_dSiBp=iBp_Zm1Q;_O
-RNH3Ds0_HFsolMNCBR"pji_d]j_"N;
-H#R3$HM_MPH0N"DR4
-";s@R@Ug:g::dngdg:U.+4:_qj7Rvqfjj:ROlNEwR7wR1]blsHR_qj7
-vqSqT=jv_7q7
-S=N#00lC_NHOEM3C\q7j_v.q_
-pSBip=Bi1_mZOQ_
-=S1)_1aHN;
-HsR30FD_sMHoNRlC"_qj7"vq;H
-NR$3#MM_HHN0PD4R""s;
-RU@@:.4.::dc4:..d4n+.p:Bij_jjc_7R:fjjNRlO7ERw]w1RHbslpRBij_jjc_7
-=STB_pij_jj7Sc
-7p=Bij_jjd_7
-pSBip=Bi1_mZOQ_
-=S1)_1aHN;
-HsR30FD_sMHoNRlC"iBp_jjj_"7c;H
-NR$3#MM_HHN0PD4R""s;
-RU@@:n4j::.g4:jnd44+.a:7q_Bi7fjRjR:jlENORw7w1b]RsRHl7Baqij_7
-=ST7Baqij_7
-=S77Baqi
-_OSiBp=iBp_Zm1Q
-_OS)1=1Ha_;H
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-S=qAtBji_dQj_h7a_
-=S7ABtqid_jjh_QaB
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SpBi=pmi_1_ZQO1
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-H;N3HRs_0DFosHMCNlRt"Aq_Bij_djQ_ha7
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";N3HR#_$MH0MHPRND";4"
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pSBip=Bi1_mZOQ_
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H#R3$HM_MPH0N"DR4
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NR$3#MM_HHN0PD4R""s;
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pSBip=Bi1_mZOQ_
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-S=1) Oa_
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-(;sjRf:ljRNROEA7Q_Qb)RsRHlqj1_jSj
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- Sm=qAtBji_dQj_h
-a;sjRf:ljRNROEA7Q_Qb)RsRHl7j1_dSj
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-(;sjRf:ljRNROEA7Q_Qb)RsRHlz_71j
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-mSQ=1z7_jjj
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-a;sjRf:ljRNROEA7Q_Qb)RsRHlp_71j
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- Sm=4h_c
-(;sjRf:ljRNROEA7Q_Qb)RsRHl1 QZr
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- Sm=4h_c
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-(;sjRf:ljRNROEQwAzRHbsl RMX1u_u qB
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+=Smz_71j_jjOQ
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+=Smp_71j_jjOQ
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+=Sm1 QZ_jOr9Q
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+=Sm1 QZ_4Or9Q
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+=Smqr_O4
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+=Smqr_O.
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+=SmAjt_dOj_
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+=SmB_pi7_Qem
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R:fjjNRlOmERARzwblsHRpQu_jjdr
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-m1=7qrBijS9
-Qej=BSB
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+=Sm7Baqi
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+=SmqBe _u X
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+= S=QjO_bkCr#0d
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m_=h4
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fsRjR:jlENOR7qh.sRbH7lR1j_jjv_7q__4#kJlGHN_
-=Smhd_6_Sj
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sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCp\37j1_jQj_h(a__4j_
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4SQ=_71j_djHs;
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_jS#m=0CN0_OlNECHM\73p1j_jjh_Qa__(jQ
Sj0=#N_0ClENOH\MC31p7_jjj_aQh_j(__S4
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R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\z_71j_jjQ_ha(__j4m
S=N#00lC_NHOEM3C\z_71j_jjQ_ha(__j4Q
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4SQ=_qjHs;
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mp=Bij_jj4_7_SH
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S4_=h(
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R:fjjNRlOQERhbeRsRHlO_bkC##0C3_jsm
S=kOb_0C##jC_3dkM
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R:fjjNRlOqERhR7.blsHRkOb_0C##jC_3Sl
mb=Ok#_C0_#CjM3k4Q
Sjb=Ok#_C09r4
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R:fjjNRlOqERhR7.blsHRkOb_0C##jC_3SM
mb=Ok#_C0_#CjM3kjQ
Sjb=Ok#_C0#_Mr
@@ -2232,11 +2268,11 @@ QO4=bCk_#C0#_kj3M
j;sjRf:ljRNROEQRheblsHRkOb_0C##4C_3Ss
mb=Ok#_C0_#C4M3kdQ
Sj_=h(
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3MSOm=bCk_#C0#_k43MSj
QOj=bCk_#M0_#9r.
4SQ=kOb_0C##4C_3dkM;R
@@ -2246,14 +2282,14 @@ sfjj:ROlNE)Rm.sRbHOlRbCk_#C0#_b43
M4S=Q4O_bkC##0C3_4k;Mj
fsRjR:jlENOReQhRHbslbROk#_C0_#C.
3sSOm=bCk_#C0#_k.3MSd
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fsRjR:jlENOR7qh.sRbHOlRbCk_#C0#_l.3
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fsRjR:jlENOR.m)RHbslbROk#_C0_#C.
3bSOm=bCk_#M0_#r_CdS9
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j;sjRf:ljRNROEQRheblsHRiBp_amz_ u)__6j7
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m1=q_jjd_jjj_h1YB3_jk
MjS=Qjqj1_djj_j1j_Y
@@ -2299,66 +2320,66 @@ R:fjjNRlOmER)b.RsRHlqj1_djj_j1j_Y_hBj
3bShm=_S.
Qqj=1d_jjj_jjY_1hjB_34kM
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jSQ=4h_g
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+=Smp_71j_jjQ_hajM3kjQ
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+=Smw_uzBQ1_hja_3jkM
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fsRjR:jlENOReQhRHbsltRA_jjj_sj3
=SmAjt_jjj_3dkM
jSQ=N#00lC_NHOEM3C\kjM4__Loj;dj
@@ -2371,53 +2392,56 @@ R:fjjNRlOqERhR7.blsHR_Atj_jjj
MjS=QjAjt_jOj_
4SQ=_Atj_jjjM3kds;
R:fjjNRlOmER)b.RsRHlAjt_jjj_3Sb
-m_=h(Q
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Sjt=A_jjj_kj3MS4
QA4=tj_jj3_jk;Mj
-fsRjR:jlENOReQhRHbsl1R7_jjj_q7v_sj3
-=Sm7j1_j7j_vjq_3dkM
-jSQ=6h_ds;
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-m1=7_jjj_q7v_kj3MSj
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+=Smqj1_jQj_hja_3dkM
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+=Smqj1_jQj_hja_34kM
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+=Sm7B1qiQ4_hja_3dkM
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3bShm=_
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+Q#4=0CN0_OlNECHM\M3k4O._Dj _j8j_js;
+R:fjjNRlOqERhR7.blsHRqev_aQh_Mj3
+=Sme_vqQ_hajM3kjQ
+Sjv=eqh_QaQ
+S4v=eqh_Qa3_jk;Md
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;
diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr
index f7c1f00..767bba0 100644
--- a/Logic/BUS68030.srr
+++ b/Logic/BUS68030.srr
@@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
-#Thu May 29 22:04:21 2014
+#Sun Jun 01 01:03:18 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@@ -19,14 +19,15 @@ VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Pruning register CLK_REF(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D6
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:34:123:36|Pruning register CLK_000_D5
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":114:38:114:40|Pruning register CLK_OUT_PRE_33
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":146:2:146:3|Pruning register CLK_CNT_P(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:2:133:3|Pruning register CLK_CNT_N(1 downto 0)
-@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":99:36:99:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Pruning register CLK_REF(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0)
+@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@@ -37,7 +38,7 @@ State machine has 8 reachable states with original encodings of:
101
110
111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:34:117:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:34:120:36|Trying to extract state machine for register cpu_est
Extracted state machine for register cpu_est
State machine has 11 reachable states with original encodings of:
0000
@@ -53,7 +54,7 @@ State machine has 11 reachable states with original encodings of:
1111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 29 22:04:21 2014
+# Sun Jun 01 01:03:18 2014
###########################################################]
Map & Optimize Report
@@ -92,13 +93,13 @@ Simple gate primitives:
DFFRH 16 uses
DFFSH 27 uses
DFF 1 use
-BI_DIR 10 uses
-IBUF 30 uses
-BUFTH 4 uses
-OBUF 15 uses
-AND2 181 uses
+BI_DIR 12 uses
+IBUF 29 uses
+BUFTH 2 uses
+OBUF 16 uses
+AND2 185 uses
INV 151 uses
-OR2 20 uses
+OR2 21 uses
XOR2 1 use
@@ -109,6 +110,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 29 22:04:22 2014
+# Sun Jun 01 01:03:19 2014
###########################################################]
diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs
index 3e9274d..fda9761 100644
Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ
diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf
index c49a7cb..4a22d7b 100644
--- a/Logic/bus68030.exf
+++ b/Logic/bus68030.exf
@@ -5,7 +5,6 @@ Section Type Array Num Name Real Name Base
Port 3 FC(1:0) FC 1 2 -1
Port 4 IPL_030(2:0) IPL_030 2 3 -1
Port 5 SIZE(1:0) SIZE 1 2 -1
- Port 6 DSACK(1:0) DSACK 1 2 -1
End
Section Member Rename Array-Notation Array Number Index
// -------------------------------------------------------------------------------------
@@ -33,243 +32,235 @@ Section Member Rename Array-Notation Array Number
Port IPL_2_ IPL[2] 2 0
Port IPL_1_ IPL[1] 2 1
Port IPL_0_ IPL[0] 2 2
- Port DSACK_1_ DSACK[1] 6 0
- Port DSACK_0_ DSACK[0] 6 1
Port FC_1_ FC[1] 3 0
Port FC_0_ FC[0] 3 1
End
Section Cross Reference File
-Design 'BUS68030' created Thu May 29 22:04:27 2014
+Design 'BUS68030' created Sun Jun 01 01:03:24 2014
Type New Name Original Name
// ----------------------------------------------------------------------
Inst i_z2O2O AS_030
Inst i_z2P2P AS_000
- Inst i_z2Q2Q DS_030
- Inst i_z2R2R UDS_000
- Inst i_z2S2S LDS_000
- Inst i_z3F3F A0
- Inst i_z3H3H BERR
+ Inst i_z2Q2Q RW_000
+ Inst i_z2R2R DS_030
+ Inst i_z2S2S UDS_000
+ Inst i_z2T2T LDS_000
+ Inst i_z3G3G A0
+ Inst i_z3I3I BERR
+ Inst i_z4343 DSACK1
Inst i_z4444 DTACK
- Inst i_z4646 AVEC_EXP
+ Inst i_z4C4C RW
Inst i_z4I4I CIIN
- Inst SM_AMIGA_ns_i_i_i_6_ SM_AMIGA_ns_i_i_i[6]
- Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5]
- Inst SM_AMIGA_ns_i_o2_i_4_ SM_AMIGA_ns_i_o2_i[4]
- Inst SM_AMIGA_ns_0_i_0_ SM_AMIGA_ns_0_i[0]
- Inst cpu_est_ns_0_0_i_2_ cpu_est_ns_0_0_i[2]
- Inst SM_AMIGA_ns_i_i_o2_i_6_ SM_AMIGA_ns_i_i_o2_i[6]
- Inst clk_un3_clk_000_d1_0_o2_i clk.un3_clk_000_d1_0_o2_i
- Inst SM_AMIGA_ns_i_o2_i_1_ SM_AMIGA_ns_i_o2_i[1]
- Inst SM_AMIGA_ns_i_o2_0_i_4_ SM_AMIGA_ns_i_o2_0_i[4]
- Inst cpu_est_ns_0_0_i_1_ cpu_est_ns_0_0_i[1]
- Inst state_machine_CLK_030_H_2_f0_i_o2_i state_machine.CLK_030_H_2_f0_i_o2_i
- Inst cpu_est_0_ cpu_est[0]
- Inst SM_AMIGA_ns_i_o2_0_i_1_ SM_AMIGA_ns_i_o2_0_i[1]
- Inst cpu_est_1_ cpu_est[1]
- Inst cpu_est_2_ cpu_est[2]
- Inst cpu_est_3_ cpu_est[3]
Inst cpu_est_ns_i_0_o2_i_3_ cpu_est_ns_i_0_o2_i[3]
+ Inst SM_AMIGA_ns_i_o2_i_4_ SM_AMIGA_ns_i_o2_i[4]
+ Inst SM_AMIGA_ns_i_o2_0_i_4_ SM_AMIGA_ns_i_o2_0_i[4]
+ Inst state_machine_un3_clk_000_d1_0_o2_i state_machine.un3_clk_000_d1_0_o2_i
+ Inst state_machine_RW_000_INT_7_iv_0_o2_i state_machine.RW_000_INT_7_iv_0_o2_i
+ Inst SM_AMIGA_i_2_ SM_AMIGA_i[2]
+ Inst SM_AMIGA_ns_a2_0_o2_i_6_ SM_AMIGA_ns_a2_0_o2_i[6]
+ Inst state_machine_CLK_030_H_2_f0_i_o2_i state_machine.CLK_030_H_2_f0_i_o2_i
+ Inst cpu_est_ns_0_0_i_1_ cpu_est_ns_0_0_i[1]
+ Inst state_machine_SIZE_DMA_4_0_i_1_ state_machine.SIZE_DMA_4_0_i[1]
+ Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5]
+ Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i
+ Inst state_machine_DS_000_DMA_3_0_i state_machine.DS_000_DMA_3_0_i
+ Inst cpu_est_0_ cpu_est[0]
+ Inst cpu_est_1_ cpu_est[1]
+ Inst A_i_19_ A_i[19]
+ Inst cpu_est_2_ cpu_est[2]
+ Inst A_i_18_ A_i[18]
+ Inst cpu_est_3_ cpu_est[3]
+ Inst A_i_16_ A_i[16]
Inst SM_AMIGA_0_ SM_AMIGA[0]
- Inst SM_AMIGA_i_1_ SM_AMIGA_i[1]
+ Inst BGACK_030_INT_0_r BGACK_030_INT_0.r
Inst SIZE_DMA_1_ SIZE_DMA[1]
- Inst SM_AMIGA_ns_i_o2_i_7_ SM_AMIGA_ns_i_o2_i[7]
+ Inst BGACK_030_INT_0_m BGACK_030_INT_0.m
Inst IPL_030DFFSH_0_ IPL_030DFFSH[0]
+ Inst BGACK_030_INT_0_n BGACK_030_INT_0.n
Inst IPL_030DFFSH_1_ IPL_030DFFSH[1]
+ Inst BGACK_030_INT_0_p BGACK_030_INT_0.p
Inst IPL_030DFFSH_2_ IPL_030DFFSH[2]
Inst SM_AMIGA_7_ SM_AMIGA[7]
+ Inst AS_000_DMA_0_r AS_000_DMA_0.r
Inst SM_AMIGA_6_ SM_AMIGA[6]
- Inst state_machine_UDS_000_INT_7_0_m3_r state_machine.UDS_000_INT_7_0_m3.r
+ Inst AS_000_DMA_0_m AS_000_DMA_0.m
Inst SM_AMIGA_5_ SM_AMIGA[5]
- Inst state_machine_UDS_000_INT_7_0_m3_m state_machine.UDS_000_INT_7_0_m3.m
+ Inst AS_000_DMA_0_n AS_000_DMA_0.n
Inst SM_AMIGA_4_ SM_AMIGA[4]
- Inst state_machine_UDS_000_INT_7_0_m3_n state_machine.UDS_000_INT_7_0_m3.n
+ Inst AS_000_DMA_0_p AS_000_DMA_0.p
Inst SM_AMIGA_3_ SM_AMIGA[3]
- Inst state_machine_UDS_000_INT_7_0_m3_p state_machine.UDS_000_INT_7_0_m3.p
+ Inst DS_000_DMA_0_r DS_000_DMA_0.r
Inst SM_AMIGA_2_ SM_AMIGA[2]
- Inst SM_AMIGA_i_6_ SM_AMIGA_i[6]
+ Inst DS_000_DMA_0_m DS_000_DMA_0.m
Inst SM_AMIGA_1_ SM_AMIGA[1]
- Inst clk_un3_clk_000_d1_0_o2 clk.un3_clk_000_d1_0_o2
- Inst SM_AMIGA_ns_i_i_o2_6_ SM_AMIGA_ns_i_i_o2[6]
- Inst SM_AMIGA_ns_i_o2_7_ SM_AMIGA_ns_i_o2[7]
+ Inst DS_000_DMA_0_n DS_000_DMA_0.n
+ Inst DS_000_DMA_0_p DS_000_DMA_0.p
+ Inst CLK_030_H_0_r CLK_030_H_0.r
+ Inst CLK_030_H_0_m CLK_030_H_0.m
+ Inst CLK_030_H_0_n CLK_030_H_0.n
Inst SIZE_DMA_0_ SIZE_DMA[0]
- Inst cpu_est_i_3_ cpu_est_i[3]
- Inst cpu_est_ns_i_0_o2_3_ cpu_est_ns_i_0_o2[3]
- Inst SM_AMIGA_ns_i_o2_0_1_ SM_AMIGA_ns_i_o2_0[1]
- Inst state_machine_CLK_030_H_2_f0_i_o2 state_machine.CLK_030_H_2_f0_i_o2
- Inst SM_AMIGA_ns_i_0_2_ SM_AMIGA_ns_i_0[2]
- Inst SM_AMIGA_ns_i_0_3_ SM_AMIGA_ns_i_0[3]
- Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4]
- Inst SM_AMIGA_ns_0_5_ SM_AMIGA_ns_0[5]
- Inst SM_AMIGA_ns_i_i_6_ SM_AMIGA_ns_i_i[6]
- Inst cpu_est_ns_i_0_3_ cpu_est_ns_i_0[3]
- Inst state_machine_CLK_030_H_2_f0_i state_machine.CLK_030_H_2_f0_i
- Inst state_machine_AMIGA_BUS_ENABLE_4_iv_0 state_machine.AMIGA_BUS_ENABLE_4_iv_0
- Inst SM_AMIGA_ns_i_o2_4_ SM_AMIGA_ns_i_o2[4]
- Inst SM_AMIGA_i_4_ SM_AMIGA_i[4]
- Inst SM_AMIGA_ns_i_o2_0_4_ SM_AMIGA_ns_i_o2_0[4]
- Inst SM_AMIGA_i_5_ SM_AMIGA_i[5]
- Inst state_machine_SIZE_DMA_4_0_a2_1_ state_machine.SIZE_DMA_4_0_a2[1]
- Inst state_machine_A0_DMA_2_0_a2 state_machine.A0_DMA_2_0_a2
- Inst state_machine_un6_bgack_000_0 state_machine.un6_bgack_000_0
- Inst state_machine_un15_clk_000_d0_0 state_machine.un15_clk_000_d0_0
- Inst SIZE_0_ SIZE[0]
- Inst SIZE_1_ SIZE[1]
- Inst state_machine_un10_bg_030_0 state_machine.un10_bg_030_0
- Inst A_16_ A[16]
- Inst A_17_ A[17]
- Inst A_18_ A[18]
- Inst state_machine_DS_000_DMA_3_0 state_machine.DS_000_DMA_3_0
- Inst A_19_ A[19]
- Inst state_machine_SIZE_DMA_4_0_1_ state_machine.SIZE_DMA_4_0[1]
- Inst A_20_ A[20]
- Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1]
- Inst A_21_ A[21]
- Inst A_22_ A[22]
- Inst A_23_ A[23]
- Inst A_24_ A[24]
- Inst A_25_ A[25]
- Inst A_26_ A[26]
- Inst A_27_ A[27]
- Inst SM_AMIGA_ns_i_a2_0_4_ SM_AMIGA_ns_i_a2_0[4]
- Inst A_28_ A[28]
- Inst SM_AMIGA_ns_i_a2_7_ SM_AMIGA_ns_i_a2[7]
- Inst A_29_ A[29]
- Inst cpu_est_i_0_ cpu_est_i[0]
- Inst A_30_ A[30]
- Inst cpu_est_ns_0_0_a2_1_ cpu_est_ns_0_0_a2[1]
- Inst A_31_ A[31]
- Inst cpu_est_ns_i_0_a2_3_ cpu_est_ns_i_0_a2[3]
- Inst cpu_est_i_1_ cpu_est_i[1]
- Inst cpu_est_ns_0_0_a2_0_1_ cpu_est_ns_0_0_a2_0[1]
- Inst SM_AMIGA_ns_0_a2_0_ SM_AMIGA_ns_0_a2[0]
- Inst cpu_est_i_2_ cpu_est_i[2]
- Inst cpu_est_ns_0_0_a3_0_1_ cpu_est_ns_0_0_a3_0[1]
- Inst cpu_est_ns_i_0_a3_3_ cpu_est_ns_i_0_a3[3]
- Inst state_machine_CLK_030_H_2_f0_i_a3 state_machine.CLK_030_H_2_f0_i_a3
- Inst IPL_030_0_ IPL_030[0]
- Inst cpu_est_ns_0_0_a3_2_ cpu_est_ns_0_0_a3[2]
- Inst IPL_030_1_ IPL_030[1]
- Inst cpu_est_ns_0_0_a3_0_2_ cpu_est_ns_0_0_a3_0[2]
- Inst IPL_030_2_ IPL_030[2]
- Inst cpu_est_ns_0_0_a3_1_2_ cpu_est_ns_0_0_a3_1[2]
- Inst IPL_0_ IPL[0]
- Inst SM_AMIGA_ns_0_a3_0_ SM_AMIGA_ns_0_a3[0]
- Inst IPL_1_ IPL[1]
- Inst SM_AMIGA_ns_0_a3_0_0_ SM_AMIGA_ns_0_a3_0[0]
- Inst IPL_2_ IPL[2]
- Inst DSACK_0_ DSACK[0]
- Inst DSACK_1_ DSACK[1]
- Inst state_machine_SIZE_DMA_4_i_a3_0_ state_machine.SIZE_DMA_4_i_a3[0]
- Inst SM_AMIGA_i_7_ SM_AMIGA_i[7]
- Inst SM_AMIGA_ns_i_a3_1_ SM_AMIGA_ns_i_a3[1]
- Inst SM_AMIGA_ns_i_a3_0_1_ SM_AMIGA_ns_i_a3_0[1]
- Inst SM_AMIGA_ns_i_0_a3_2_ SM_AMIGA_ns_i_0_a3[2]
- Inst SM_AMIGA_ns_i_0_a3_3_ SM_AMIGA_ns_i_0_a3[3]
+ Inst CLK_030_H_0_p CLK_030_H_0.p
+ Inst RW_000_INT_0_r RW_000_INT_0.r
+ Inst RW_000_INT_0_m RW_000_INT_0.m
+ Inst RW_000_INT_0_n RW_000_INT_0.n
+ Inst RW_000_INT_0_p RW_000_INT_0.p
+ Inst SM_AMIGA_i_0_ SM_AMIGA_i[0]
+ Inst SM_AMIGA_i_1_ SM_AMIGA_i[1]
+ Inst SM_AMIGA_ns_i_0_a3_7_ SM_AMIGA_ns_i_0_a3[7]
+ Inst SM_AMIGA_ns_0_a3_0_5_ SM_AMIGA_ns_0_a3_0[5]
Inst SM_AMIGA_i_3_ SM_AMIGA_i[3]
Inst SM_AMIGA_ns_i_a3_4_ SM_AMIGA_ns_i_a3[4]
- Inst SM_AMIGA_ns_0_a3_0_5_ SM_AMIGA_ns_0_a3_0[5]
- Inst SM_AMIGA_ns_i_i_a3_6_ SM_AMIGA_ns_i_i_a3[6]
+ Inst SM_AMIGA_i_4_ SM_AMIGA_i[4]
+ Inst SM_AMIGA_i_5_ SM_AMIGA_i[5]
+ Inst SM_AMIGA_ns_i_0_a3_3_ SM_AMIGA_ns_i_0_a3[3]
+ Inst SM_AMIGA_ns_0_a3_0_ SM_AMIGA_ns_0_a3[0]
+ Inst SM_AMIGA_ns_a2_0_a3_6_ SM_AMIGA_ns_a2_0_a3[6]
+ Inst state_machine_SIZE_DMA_4_i_a3_0_ state_machine.SIZE_DMA_4_i_a3[0]
+ Inst state_machine_un6_bgack_000_0 state_machine.un6_bgack_000_0
+ Inst state_machine_SIZE_DMA_4_0_a2_1_ state_machine.SIZE_DMA_4_0_a2[1]
+ Inst SM_AMIGA_ns_i_a2_0_4_ SM_AMIGA_ns_i_a2_0[4]
+ Inst SIZE_0_ SIZE[0]
+ Inst SIZE_1_ SIZE[1]
+ Inst A_16_ A[16]
+ Inst state_machine_CLK_030_H_2_f0_i_a3 state_machine.CLK_030_H_2_f0_i_a3
+ Inst A_17_ A[17]
+ Inst A_18_ A[18]
+ Inst A_19_ A[19]
+ Inst state_machine_un3_clk_000_d1_0_o2 state_machine.un3_clk_000_d1_0_o2
+ Inst A_20_ A[20]
+ Inst SM_AMIGA_ns_i_o2_0_4_ SM_AMIGA_ns_i_o2_0[4]
+ Inst A_21_ A[21]
+ Inst SM_AMIGA_ns_i_o2_4_ SM_AMIGA_ns_i_o2[4]
+ Inst A_22_ A[22]
+ Inst A_23_ A[23]
+ Inst state_machine_RW_000_INT_7_iv_0 state_machine.RW_000_INT_7_iv_0
+ Inst A_24_ A[24]
+ Inst state_machine_CLK_030_H_2_f0_i state_machine.CLK_030_H_2_f0_i
+ Inst A_25_ A[25]
+ Inst A_26_ A[26]
+ Inst SM_AMIGA_ns_i_0_7_ SM_AMIGA_ns_i_0[7]
+ Inst A_27_ A[27]
+ Inst SM_AMIGA_ns_0_5_ SM_AMIGA_ns_0[5]
+ Inst A_28_ A[28]
+ Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4]
+ Inst A_29_ A[29]
+ Inst SM_AMIGA_ns_i_0_3_ SM_AMIGA_ns_i_0[3]
+ Inst A_30_ A[30]
+ Inst state_machine_SIZE_DMA_4_0_1_ state_machine.SIZE_DMA_4_0[1]
+ Inst A_31_ A[31]
+ Inst state_machine_DS_000_DMA_3_0 state_machine.DS_000_DMA_3_0
+ Inst cpu_est_i_3_ cpu_est_i[3]
+ Inst cpu_est_ns_i_0_o2_3_ cpu_est_ns_i_0_o2[3]
+ Inst SM_AMIGA_ns_0_o3_0_ SM_AMIGA_ns_0_o3[0]
+ Inst SM_AMIGA_ns_a2_0_o2_2_ SM_AMIGA_ns_a2_0_o2[2]
+ Inst SM_AMIGA_i_6_ SM_AMIGA_i[6]
+ Inst SM_AMIGA_ns_i_0_o2_1_ SM_AMIGA_ns_i_0_o2[1]
+ Inst state_machine_RW_000_INT_7_iv_0_a3_0_2 state_machine.RW_000_INT_7_iv_0_a3_0_2
+ Inst IPL_030_0_ IPL_030[0]
+ Inst state_machine_CLK_030_H_2_f0_i_o2 state_machine.CLK_030_H_2_f0_i_o2
+ Inst IPL_030_1_ IPL_030[1]
+ Inst SM_AMIGA_ns_a2_0_o2_6_ SM_AMIGA_ns_a2_0_o2[6]
+ Inst IPL_030_2_ IPL_030[2]
+ Inst IPL_0_ IPL[0]
+ Inst state_machine_RW_000_INT_7_iv_0_o2 state_machine.RW_000_INT_7_iv_0_o2
+ Inst IPL_1_ IPL[1]
+ Inst cpu_est_ns_i_0_a2_3_ cpu_est_ns_i_0_a2[3]
+ Inst IPL_2_ IPL[2]
+ Inst state_machine_un12_clk_000_d0_0 state_machine.un12_clk_000_d0_0
+ Inst state_machine_un10_bg_030_0 state_machine.un10_bg_030_0
+ Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0]
+ Inst SM_AMIGA_ns_i_0_1_ SM_AMIGA_ns_i_0[1]
+ Inst cpu_est_ns_i_0_3_ cpu_est_ns_i_0[3]
Inst FC_0_ FC[0]
- Inst SM_AMIGA_ns_i_i_a3_0_6_ SM_AMIGA_ns_i_i_a3_0[6]
Inst FC_1_ FC[1]
- Inst SM_AMIGA_i_0_ SM_AMIGA_i[0]
- Inst SM_AMIGA_ns_i_a3_7_ SM_AMIGA_ns_i_a3[7]
- Inst cpu_est_ns_0_0_a3_1_ cpu_est_ns_0_0_a3[1]
- Inst A_i_25_ A_i[25]
- Inst A_i_26_ A_i[26]
- Inst state_machine_A0_DMA_2_0_a3_1 state_machine.A0_DMA_2_0_a3_1
- Inst A_i_27_ A_i[27]
- Inst state_machine_A0_DMA_2_0_a3 state_machine.A0_DMA_2_0_a3
- Inst A_i_28_ A_i[28]
+ Inst state_machine_UDS_000_INT_7_0_m3_r state_machine.UDS_000_INT_7_0_m3.r
+ Inst state_machine_UDS_000_INT_7_0_m3_m state_machine.UDS_000_INT_7_0_m3.m
+ Inst state_machine_UDS_000_INT_7_0_m3_n state_machine.UDS_000_INT_7_0_m3.n
+ Inst state_machine_UDS_000_INT_7_0_m3_p state_machine.UDS_000_INT_7_0_m3.p
+ Inst SM_AMIGA_i_7_ SM_AMIGA_i[7]
+ Inst cpu_est_ns_0_0_a3_2_ cpu_est_ns_0_0_a3[2]
+ Inst cpu_est_ns_0_0_a3_0_2_ cpu_est_ns_0_0_a3_0[2]
+ Inst cpu_est_ns_0_0_a3_1_2_ cpu_est_ns_0_0_a3_1[2]
+ Inst cpu_est_i_0_ cpu_est_i[0]
+ Inst state_machine_un12_clk_000_d0_0_a3_1 state_machine.un12_clk_000_d0_0_a3_1
+ Inst cpu_est_ns_0_0_a2_1_ cpu_est_ns_0_0_a2[1]
+ Inst state_machine_un12_clk_000_d0_0_a3 state_machine.un12_clk_000_d0_0_a3
+ Inst SM_AMIGA_ns_0_a2_0_ SM_AMIGA_ns_0_a2[0]
+ Inst SM_AMIGA_ns_i_a2_1_4_ SM_AMIGA_ns_i_a2_1[4]
+ Inst cpu_est_i_1_ cpu_est_i[1]
+ Inst SM_AMIGA_ns_i_a2_4_ SM_AMIGA_ns_i_a2[4]
+ Inst cpu_est_ns_0_0_a2_0_1_ cpu_est_ns_0_0_a2_0[1]
Inst A_i_29_ A_i[29]
Inst A_i_30_ A_i[30]
+ Inst state_machine_RW_000_INT_7_iv_0_a3_1 state_machine.RW_000_INT_7_iv_0_a3_1
Inst A_i_31_ A_i[31]
- Inst A_i_16_ A_i[16]
- Inst state_machine_un15_clk_000_d0_0_a3_0_1 state_machine.un15_clk_000_d0_0_a3_0_1
- Inst A_i_18_ A_i[18]
- Inst state_machine_un15_clk_000_d0_0_a3_0 state_machine.un15_clk_000_d0_0_a3_0
- Inst A_i_19_ A_i[19]
- Inst state_machine_un15_clk_000_d0_0_a3_1 state_machine.un15_clk_000_d0_0_a3_1
- Inst state_machine_un15_clk_000_d0_0_a3 state_machine.un15_clk_000_d0_0_a3
- Inst state_machine_UDS_000_INT_7_0 state_machine.UDS_000_INT_7_0
- Inst SM_AMIGA_ns_i_a2_1_4_ SM_AMIGA_ns_i_a2_1[4]
- Inst SM_AMIGA_ns_i_a2_4_ SM_AMIGA_ns_i_a2[4]
- Inst A_i_24_ A_i[24]
- Inst state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3_1 state_machine.AMIGA_BUS_ENABLE_4_iv_0_a3_1
- Inst state_machine_AMIGA_BUS_ENABLE_4_iv_0_a3 state_machine.AMIGA_BUS_ENABLE_4_iv_0_a3
- Inst DSACK1_INT_0_r DSACK1_INT_0.r
- Inst DSACK1_INT_0_m DSACK1_INT_0.m
- Inst DSACK1_INT_0_n DSACK1_INT_0.n
+ Inst state_machine_RW_000_INT_7_iv_0_a3 state_machine.RW_000_INT_7_iv_0_a3
Inst SM_AMIGA_ns_i_a3_0_1_4_ SM_AMIGA_ns_i_a3_0_1[4]
- Inst DSACK1_INT_0_p DSACK1_INT_0.p
Inst SM_AMIGA_ns_i_a3_0_4_ SM_AMIGA_ns_i_a3_0[4]
- Inst VMA_INT_0_r VMA_INT_0.r
Inst state_machine_LDS_000_INT_7_0_a3_1 state_machine.LDS_000_INT_7_0_a3_1
- Inst VMA_INT_0_m VMA_INT_0.m
Inst state_machine_LDS_000_INT_7_0_a3 state_machine.LDS_000_INT_7_0_a3
- Inst VMA_INT_0_n VMA_INT_0.n
- Inst VMA_INT_0_p VMA_INT_0.p
- Inst state_machine_un10_bg_030_0_a3_1 state_machine.un10_bg_030_0_a3_1
- Inst BGACK_030_INT_0_r BGACK_030_INT_0.r
- Inst state_machine_un10_bg_030_0_a3_2 state_machine.un10_bg_030_0_a3_2
- Inst BGACK_030_INT_0_m BGACK_030_INT_0.m
- Inst state_machine_un10_bg_030_0_a3 state_machine.un10_bg_030_0_a3
- Inst BGACK_030_INT_0_n BGACK_030_INT_0.n
- Inst SM_AMIGA_ns_0_1_0_ SM_AMIGA_ns_0_1[0]
- Inst BGACK_030_INT_0_p BGACK_030_INT_0.p
- Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0]
- Inst IPL_030_0_0__r IPL_030_0_0_.r
+ Inst SM_AMIGA_ns_a2_0_a3_2_ SM_AMIGA_ns_a2_0_a3[2]
+ Inst state_machine_A0_DMA_2_0_a3_1 state_machine.A0_DMA_2_0_a3_1
+ Inst SM_AMIGA_ns_i_0_a3_1_ SM_AMIGA_ns_i_0_a3[1]
+ Inst state_machine_A0_DMA_2_0_a3 state_machine.A0_DMA_2_0_a3
+ Inst cpu_est_ns_0_0_a3_1_ cpu_est_ns_0_0_a3[1]
+ Inst state_machine_un12_clk_000_d0_0_a3_0 state_machine.un12_clk_000_d0_0_a3_0
+ Inst cpu_est_i_2_ cpu_est_i[2]
+ Inst SM_AMIGA_ns_0_a3_1_5_ SM_AMIGA_ns_0_a3_1[5]
+ Inst cpu_est_ns_0_0_a3_0_1_ cpu_est_ns_0_0_a3_0[1]
+ Inst SM_AMIGA_ns_0_a3_2_5_ SM_AMIGA_ns_0_a3_2[5]
+ Inst cpu_est_ns_i_0_a3_3_ cpu_est_ns_i_0_a3[3]
+ Inst SM_AMIGA_ns_0_a3_5_ SM_AMIGA_ns_0_a3[5]
+ Inst state_machine_RW_000_INT_7_iv_0_a3_0_1 state_machine.RW_000_INT_7_iv_0_a3_0_1
+ Inst state_machine_RW_000_INT_7_iv_0_a3_0 state_machine.RW_000_INT_7_iv_0_a3_0
+ Inst A_i_24_ A_i[24]
Inst cpu_est_ns_0_0_1_2_ cpu_est_ns_0_0_1[2]
- Inst IPL_030_0_0__m IPL_030_0_0_.m
+ Inst A_i_25_ A_i[25]
Inst cpu_est_ns_0_0_2_ cpu_est_ns_0_0[2]
+ Inst A_i_26_ A_i[26]
+ Inst A_i_27_ A_i[27]
+ Inst A_i_28_ A_i[28]
+ Inst state_machine_LDS_000_INT_7_0_1 state_machine.LDS_000_INT_7_0_1
+ Inst state_machine_LDS_000_INT_7_0 state_machine.LDS_000_INT_7_0
+ Inst IPL_030_0_0__r IPL_030_0_0_.r
+ Inst state_machine_UDS_000_INT_7_0_1 state_machine.UDS_000_INT_7_0_1
+ Inst IPL_030_0_0__m IPL_030_0_0_.m
+ Inst state_machine_UDS_000_INT_7_0 state_machine.UDS_000_INT_7_0
Inst IPL_030_0_0__n IPL_030_0_0_.n
Inst IPL_030_0_0__p IPL_030_0_0_.p
Inst IPL_030_0_1__r IPL_030_0_1_.r
- Inst SM_AMIGA_ns_i_1_7_ SM_AMIGA_ns_i_1[7]
Inst IPL_030_0_1__m IPL_030_0_1_.m
- Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7]
Inst IPL_030_0_1__n IPL_030_0_1_.n
- Inst state_machine_LDS_000_INT_7_0_1 state_machine.LDS_000_INT_7_0_1
+ Inst cpu_est_ns_0_0_1_1_ cpu_est_ns_0_0_1[1]
Inst IPL_030_0_1__p IPL_030_0_1_.p
- Inst state_machine_LDS_000_INT_7_0 state_machine.LDS_000_INT_7_0
+ Inst cpu_est_ns_0_0_2_1_ cpu_est_ns_0_0_2[1]
Inst IPL_030_0_2__r IPL_030_0_2_.r
- Inst state_machine_UDS_000_INT_7_0_1 state_machine.UDS_000_INT_7_0_1
+ Inst cpu_est_ns_0_0_1_ cpu_est_ns_0_0[1]
Inst IPL_030_0_2__m IPL_030_0_2_.m
Inst IPL_030_0_2__n IPL_030_0_2_.n
- Inst SM_AMIGA_ns_i_o2_1_1_ SM_AMIGA_ns_i_o2_1[1]
Inst IPL_030_0_2__p IPL_030_0_2_.p
- Inst SM_AMIGA_ns_i_o2_1_ SM_AMIGA_ns_i_o2[1]
Inst cpu_estse_0_r cpu_estse_0.r
Inst cpu_estse_0_m cpu_estse_0.m
+ Inst state_machine_un10_bg_030_0_a3_1 state_machine.un10_bg_030_0_a3_1
Inst cpu_estse_0_n cpu_estse_0.n
+ Inst state_machine_un10_bg_030_0_a3_2 state_machine.un10_bg_030_0_a3_2
Inst cpu_estse_0_p cpu_estse_0.p
- Inst cpu_est_ns_0_0_1_1_ cpu_est_ns_0_0_1[1]
+ Inst state_machine_un10_bg_030_0_a3 state_machine.un10_bg_030_0_a3
Inst cpu_estse_1_r cpu_estse_1.r
- Inst cpu_est_ns_0_0_2_1_ cpu_est_ns_0_0_2[1]
+ Inst state_machine_un12_clk_000_d0_0_a3_0_1 state_machine.un12_clk_000_d0_0_a3_0_1
Inst cpu_estse_1_m cpu_estse_1.m
- Inst cpu_est_ns_0_0_1_ cpu_est_ns_0_0[1]
+ Inst state_machine_un12_clk_000_d0_0_a3_0_2 state_machine.un12_clk_000_d0_0_a3_0_2
Inst cpu_estse_1_n cpu_estse_1.n
- Inst SM_AMIGA_ns_0_a3_1_5_ SM_AMIGA_ns_0_a3_1[5]
Inst cpu_estse_1_p cpu_estse_1.p
- Inst SM_AMIGA_ns_0_a3_2_5_ SM_AMIGA_ns_0_a3_2[5]
Inst cpu_estse_2_r cpu_estse_2.r
- Inst SM_AMIGA_ns_0_a3_5_ SM_AMIGA_ns_0_a3[5]
Inst cpu_estse_2_m cpu_estse_2.m
Inst cpu_estse_2_n cpu_estse_2.n
Inst cpu_estse_2_p cpu_estse_2.p
- Inst clk_un3_clk_out_pre_50 clk.un3_clk_out_pre_50
- Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r
- Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m
- Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n
- Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p
+ Inst state_machine_un3_clk_out_pre_50 state_machine.un3_clk_out_pre_50
Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r
Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m
Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n
Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p
- Inst CLK_030_H_0_r CLK_030_H_0.r
- Inst CLK_030_H_0_m CLK_030_H_0.m
- Inst CLK_030_H_0_n CLK_030_H_0.n
- Inst CLK_030_H_0_p CLK_030_H_0.p
Inst UDS_000_INT_0_r UDS_000_INT_0.r
Inst UDS_000_INT_0_m UDS_000_INT_0.m
Inst UDS_000_INT_0_n UDS_000_INT_0.n
@@ -277,77 +268,81 @@ Design 'BUS68030' created Thu May 29 22:04:27 2014
Inst LDS_000_INT_0_r LDS_000_INT_0.r
Inst LDS_000_INT_0_m LDS_000_INT_0.m
Inst LDS_000_INT_0_n LDS_000_INT_0.n
- Inst state_machine_un10_bg_030_0_i state_machine.un10_bg_030_0_i
Inst LDS_000_INT_0_p LDS_000_INT_0.p
Inst FPU_CS_INT_0_r FPU_CS_INT_0.r
Inst FPU_CS_INT_0_m FPU_CS_INT_0.m
Inst FPU_CS_INT_0_n FPU_CS_INT_0.n
- Inst state_machine_un13_clk_000_d0_i state_machine.un13_clk_000_d0_i
Inst FPU_CS_INT_0_p FPU_CS_INT_0.p
- Inst state_machine_un15_clk_000_d0_0_i state_machine.un15_clk_000_d0_0_i
+ Inst avec_exp_0_r avec_exp_0.r
+ Inst state_machine_un10_bg_030_0_i state_machine.un10_bg_030_0_i
+ Inst avec_exp_0_m avec_exp_0.m
+ Inst avec_exp_0_n avec_exp_0.n
+ Inst avec_exp_0_p avec_exp_0.p
+ Inst state_machine_un10_clk_000_d0_i state_machine.un10_clk_000_d0_i
Inst BG_000_0_r BG_000_0.r
- Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i
+ Inst state_machine_un12_clk_000_d0_0_i state_machine.un12_clk_000_d0_0_i
Inst BG_000_0_m BG_000_0.m
Inst BG_000_0_n BG_000_0.n
Inst BG_000_0_p BG_000_0.p
- Inst DS_000_DMA_0_r DS_000_DMA_0.r
- Inst DS_000_DMA_0_m DS_000_DMA_0.m
- Inst DS_000_DMA_0_n DS_000_DMA_0.n
- Inst DS_000_DMA_0_p DS_000_DMA_0.p
- Inst AS_000_DMA_0_r AS_000_DMA_0.r
- Inst AS_000_DMA_0_m AS_000_DMA_0.m
- Inst state_machine_SIZE_DMA_4_0_i_1_ state_machine.SIZE_DMA_4_0_i[1]
- Inst AS_000_DMA_0_n AS_000_DMA_0.n
- Inst state_machine_DS_000_DMA_3_0_i state_machine.DS_000_DMA_3_0_i
- Inst AS_000_DMA_0_p AS_000_DMA_0.p
Inst AS_000_INT_0_r AS_000_INT_0.r
+ Inst cpu_est_ns_0_0_i_2_ cpu_est_ns_0_0_i[2]
Inst AS_000_INT_0_m AS_000_INT_0.m
- Inst state_machine_LDS_000_INT_7_0_i state_machine.LDS_000_INT_7_0_i
Inst AS_000_INT_0_n AS_000_INT_0.n
- Inst state_machine_UDS_000_INT_7_0_i state_machine.UDS_000_INT_7_0_i
Inst AS_000_INT_0_p AS_000_INT_0.p
+ Inst DSACK1_INT_0_r DSACK1_INT_0.r
+ Inst DSACK1_INT_0_m DSACK1_INT_0.m
+ Inst DSACK1_INT_0_n DSACK1_INT_0.n
+ Inst SM_AMIGA_ns_0_i_0_ SM_AMIGA_ns_0_i[0]
+ Inst DSACK1_INT_0_p DSACK1_INT_0.p
+ Inst VMA_INT_0_r VMA_INT_0.r
+ Inst VMA_INT_0_m VMA_INT_0.m
+ Inst state_machine_LDS_000_INT_7_0_i state_machine.LDS_000_INT_7_0_i
+ Inst VMA_INT_0_n VMA_INT_0.n
+ Inst state_machine_UDS_000_INT_7_0_i state_machine.UDS_000_INT_7_0_i
+ Inst VMA_INT_0_p VMA_INT_0.p
+ Inst SM_AMIGA_ns_i_0_o2_i_1_ SM_AMIGA_ns_i_0_o2_i[1]
+ Inst SM_AMIGA_ns_a2_0_o2_i_2_ SM_AMIGA_ns_a2_0_o2_i[2]
Net ipl_030_c_0__n IPL_030_c[0]
Net ipl_030_0__n IPL_030[0]
Net ipl_030_c_1__n IPL_030_c[1]
+ Net sm_amiga_7__n SM_AMIGA[7]
Net ipl_030_1__n IPL_030[1]
+ Net vcc_n_n VCC
Net ipl_030_c_2__n IPL_030_c[2]
+ Net gnd_n_n GND
+ Net state_machine_un10_clk_000_d0_n state_machine.un10_clk_000_d0
Net ipl_c_0__n IPL_c[0]
Net ipl_0__n IPL[0]
- Net ipl_c_1__n IPL_c[1]
- Net ipl_1__n IPL[1]
- Net ipl_c_2__n IPL_c[2]
- Net vcc_n_n VCC
- Net dsack_0__n DSACK[0]
- Net gnd_n_n GND
- Net dsack_c_1__n DSACK_c[1]
- Net state_machine_un13_clk_000_d0_n state_machine.un13_clk_000_d0
- Net sm_amiga_1__n SM_AMIGA[1]
- Net sm_amiga_0__n SM_AMIGA[0]
Net sm_amiga_6__n SM_AMIGA[6]
+ Net ipl_c_1__n IPL_c[1]
+ Net sm_amiga_0__n SM_AMIGA[0]
+ Net ipl_1__n IPL[1]
Net sm_amiga_5__n SM_AMIGA[5]
- Net clk_un3_clk_out_pre_50_n clk.un3_clk_out_pre_50
- Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000
- Net state_machine_un15_clk_000_d0_n state_machine.un15_clk_000_d0
- Net size_dma_0__n SIZE_DMA[0]
- Net fc_c_0__n FC_c[0]
- Net size_dma_1__n SIZE_DMA[1]
- Net fc_0__n FC[0]
- Net fc_c_1__n FC_c[1]
- Net sm_amiga_7__n SM_AMIGA[7]
- Net sm_amiga_4__n SM_AMIGA[4]
- Net state_machine_a0_dma_2_n state_machine.A0_DMA_2
- Net state_machine_ds_000_dma_3_n state_machine.DS_000_DMA_3
- Net state_machine_size_dma_4_1__n state_machine.SIZE_DMA_4[1]
- Net sm_amiga_3__n SM_AMIGA[3]
+ Net ipl_c_2__n IPL_c[2]
Net sm_amiga_2__n SM_AMIGA[2]
- Net cpu_est_ns_0_1__n cpu_est_ns_0[1]
+ Net state_machine_un3_clk_out_pre_50_n state_machine.un3_clk_out_pre_50
+ Net state_machine_un12_clk_000_d0_n state_machine.un12_clk_000_d0
+ Net size_dma_0__n SIZE_DMA[0]
+ Net size_dma_1__n SIZE_DMA[1]
+ Net sm_amiga_4__n SM_AMIGA[4]
+ Net sm_amiga_3__n SM_AMIGA[3]
+ Net sm_amiga_1__n SM_AMIGA[1]
+ Net fc_c_0__n FC_c[0]
+ Net state_machine_a0_dma_2_n state_machine.A0_DMA_2
+ Net fc_0__n FC[0]
+ Net state_machine_size_dma_4_1__n state_machine.SIZE_DMA_4[1]
+ Net fc_c_1__n FC_c[1]
Net state_machine_un10_bg_030_n state_machine.un10_bg_030
Net state_machine_lds_000_int_7_n state_machine.LDS_000_INT_7
Net state_machine_uds_000_int_7_n state_machine.UDS_000_INT_7
- Net sm_amiga_i_1__n SM_AMIGA_i[1]
+ Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0
+ Net state_machine_ds_000_dma_3_0_n state_machine.DS_000_DMA_3_0
+ Net state_machine_size_dma_4_0_1__n state_machine.SIZE_DMA_4_0[1]
Net sm_amiga_ns_0__n SM_AMIGA_ns[0]
+ Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5]
Net sm_amiga_ns_5__n SM_AMIGA_ns[5]
- Net state_machine_un8_bgack_030_int_i_0_0_n state_machine.un8_bgack_030_int_i_0_0
+ Net sm_amiga_ns_2__n SM_AMIGA_ns[2]
+ Net sm_amiga_ns_6__n SM_AMIGA_ns[6]
Net cpu_est_0__n cpu_est[0]
Net cpu_est_1__n cpu_est[1]
Net cpu_est_2__n cpu_est[2]
@@ -355,64 +350,69 @@ Design 'BUS68030' created Thu May 29 22:04:27 2014
Net cpu_est_ns_e_1__n cpu_est_ns_e[1]
Net cpu_est_ns_e_2__n cpu_est_ns_e[2]
Net cpu_est_ns_e_3__n cpu_est_ns_e[3]
+ Net state_machine_rw_000_int_7_iv_i_n state_machine.RW_000_INT_7_iv_i
Net cpu_est_ns_1__n cpu_est_ns[1]
Net cpu_est_ns_2__n cpu_est_ns[2]
- Net state_machine_un8_bgack_030_int_i_0_n state_machine.un8_bgack_030_int_i_0
- Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0]
+ Net sm_amiga_i_2__n SM_AMIGA_i[2]
+ Net cpu_est_ns_0_1__n cpu_est_ns_0[1]
Net cpu_est_ns_0_2__n cpu_est_ns_0[2]
- Net state_machine_amiga_bus_enable_4_iv_i_n state_machine.AMIGA_BUS_ENABLE_4_iv_i
- Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5]
- Net state_machine_size_dma_4_0_1__n state_machine.SIZE_DMA_4_0[1]
- Net state_machine_ds_000_dma_3_0_n state_machine.DS_000_DMA_3_0
+ Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0]
Net state_machine_lds_000_int_7_0_n state_machine.LDS_000_INT_7_0
Net state_machine_uds_000_int_7_0_n state_machine.UDS_000_INT_7_0
Net state_machine_un10_bg_030_0_n state_machine.un10_bg_030_0
- Net state_machine_un13_clk_000_d0_i_n state_machine.un13_clk_000_d0_i
- Net state_machine_un15_clk_000_d0_0_n state_machine.un15_clk_000_d0_0
- Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0
- Net cpu_est_i_3__n cpu_est_i[3]
- Net sm_amiga_i_6__n SM_AMIGA_i[6]
- Net state_machine_un8_bgack_030_int_i_0_0_1_n state_machine.un8_bgack_030_int_i_0_0_1
- Net sm_amiga_i_5__n SM_AMIGA_i[5]
+ Net state_machine_un10_clk_000_d0_i_n state_machine.un10_clk_000_d0_i
+ Net state_machine_un12_clk_000_d0_0_n state_machine.un12_clk_000_d0_0
+ Net state_machine_ds_000_dma_3_n state_machine.DS_000_DMA_3
+ Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000
+ Net a_i_18__n A_i[18]
+ Net a_i_16__n A_i[16]
+ Net a_i_19__n A_i[19]
Net sm_amiga_i_4__n SM_AMIGA_i[4]
+ Net sm_amiga_i_5__n SM_AMIGA_i[5]
Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1]
- Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1]
- Net cpu_est_i_1__n cpu_est_i[1]
- Net cpu_est_i_0__n cpu_est_i[0]
- Net sm_amiga_ns_0_1_0__n SM_AMIGA_ns_0_1[0]
- Net cpu_est_ns_0_1_2__n cpu_est_ns_0_1[2]
- Net cpu_est_i_2__n cpu_est_i[2]
- Net sm_amiga_i_0__n SM_AMIGA_i[0]
- Net state_machine_lds_000_int_7_0_1_n state_machine.LDS_000_INT_7_0_1
Net sm_amiga_i_3__n SM_AMIGA_i[3]
+ Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1]
+ Net sm_amiga_i_0__n SM_AMIGA_i[0]
+ Net sm_amiga_i_1__n SM_AMIGA_i[1]
+ Net state_machine_un10_clk_000_d0_1_n state_machine.un10_clk_000_d0_1
+ Net state_machine_un10_clk_000_d0_2_n state_machine.un10_clk_000_d0_2
+ Net cpu_est_ns_0_1_2__n cpu_est_ns_0_1[2]
+ Net sm_amiga_i_6__n SM_AMIGA_i[6]
+ Net state_machine_lds_000_int_7_0_1_n state_machine.LDS_000_INT_7_0_1
+ Net cpu_est_i_3__n cpu_est_i[3]
Net state_machine_uds_000_int_7_0_1_n state_machine.UDS_000_INT_7_0_1
Net sm_amiga_i_7__n SM_AMIGA_i[7]
- Net size_i_1__n SIZE_i[1]
- Net a_i_19__n A_i[19]
- Net a_i_16__n A_i[16]
- Net a_i_18__n A_i[18]
- Net a_i_30__n A_i[30]
+ Net cpu_est_i_1__n cpu_est_i[1]
+ Net cpu_est_i_0__n cpu_est_i[0]
Net state_machine_a0_dma_2_1_n state_machine.A0_DMA_2_1
+ Net cpu_est_i_2__n cpu_est_i[2]
+ Net size_i_1__n SIZE_i[1]
+ Net a_i_30__n A_i[30]
Net a_i_31__n A_i[31]
- Net a_i_28__n A_i[28]
- Net a_i_29__n A_i[29]
- Net state_machine_un13_clk_000_d0_1_n state_machine.un13_clk_000_d0_1
- Net a_i_26__n A_i[26]
- Net a_i_27__n A_i[27]
- Net state_machine_uds_000_int_7_0_m3_un3_n state_machine.UDS_000_INT_7_0_m3.un3
- Net a_i_24__n A_i[24]
- Net state_machine_uds_000_int_7_0_m3_un1_n state_machine.UDS_000_INT_7_0_m3.un1
- Net a_i_25__n A_i[25]
- Net state_machine_uds_000_int_7_0_m3_un0_n state_machine.UDS_000_INT_7_0_m3.un0
- Net dsack1_int_0_un3_n DSACK1_INT_0.un3
- Net dsack1_int_0_un1_n DSACK1_INT_0.un1
- Net dsack1_int_0_un0_n DSACK1_INT_0.un0
- Net vma_int_0_un3_n VMA_INT_0.un3
- Net vma_int_0_un1_n VMA_INT_0.un1
- Net vma_int_0_un0_n VMA_INT_0.un0
Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3
+ Net a_i_28__n A_i[28]
Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1
+ Net a_i_29__n A_i[29]
Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0
+ Net a_i_26__n A_i[26]
+ Net as_000_dma_0_un3_n AS_000_DMA_0.un3
+ Net a_i_27__n A_i[27]
+ Net as_000_dma_0_un1_n AS_000_DMA_0.un1
+ Net a_i_24__n A_i[24]
+ Net as_000_dma_0_un0_n AS_000_DMA_0.un0
+ Net a_i_25__n A_i[25]
+ Net ds_000_dma_0_un3_n DS_000_DMA_0.un3
+ Net ds_000_dma_0_un1_n DS_000_DMA_0.un1
+ Net ds_000_dma_0_un0_n DS_000_DMA_0.un0
+ Net clk_030_h_0_un3_n CLK_030_H_0.un3
+ Net clk_030_h_0_un1_n CLK_030_H_0.un1
+ Net clk_030_h_0_un0_n CLK_030_H_0.un0
+ Net rw_000_int_0_un3_n RW_000_INT_0.un3
+ Net rw_000_int_0_un1_n RW_000_INT_0.un1
+ Net rw_000_int_0_un0_n RW_000_INT_0.un0
+ Net state_machine_uds_000_int_7_0_m3_un3_n state_machine.UDS_000_INT_7_0_m3.un3
+ Net state_machine_uds_000_int_7_0_m3_un1_n state_machine.UDS_000_INT_7_0_m3.un1
+ Net state_machine_uds_000_int_7_0_m3_un0_n state_machine.UDS_000_INT_7_0_m3.un0
Net ipl_030_0_0__un3_n IPL_030_0_0_.un3
Net ipl_030_0_0__un1_n IPL_030_0_0_.un1
Net ipl_030_0_0__un0_n IPL_030_0_0_.un0
@@ -442,59 +442,56 @@ Design 'BUS68030' created Thu May 29 22:04:27 2014
Net a_c_19__n A_c[19]
Net cpu_estse_2_un0_n cpu_estse_2.un0
Net a_19__n A[19]
- Net amiga_bus_enable_0_un3_n AMIGA_BUS_ENABLE_0.un3
- Net a_c_20__n A_c[20]
- Net amiga_bus_enable_0_un1_n AMIGA_BUS_ENABLE_0.un1
- Net a_20__n A[20]
- Net amiga_bus_enable_0_un0_n AMIGA_BUS_ENABLE_0.un0
- Net a_c_21__n A_c[21]
Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3
- Net a_21__n A[21]
+ Net a_c_20__n A_c[20]
Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1
- Net a_c_22__n A_c[22]
+ Net a_20__n A[20]
Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0
- Net a_22__n A[22]
- Net clk_030_h_0_un3_n CLK_030_H_0.un3
- Net a_c_23__n A_c[23]
- Net clk_030_h_0_un1_n CLK_030_H_0.un1
- Net a_23__n A[23]
- Net clk_030_h_0_un0_n CLK_030_H_0.un0
- Net a_c_24__n A_c[24]
+ Net a_c_21__n A_c[21]
Net uds_000_int_0_un3_n UDS_000_INT_0.un3
- Net a_24__n A[24]
+ Net a_21__n A[21]
Net uds_000_int_0_un1_n UDS_000_INT_0.un1
- Net a_c_25__n A_c[25]
+ Net a_c_22__n A_c[22]
Net uds_000_int_0_un0_n UDS_000_INT_0.un0
- Net a_25__n A[25]
+ Net a_22__n A[22]
Net lds_000_int_0_un3_n LDS_000_INT_0.un3
- Net a_c_26__n A_c[26]
+ Net a_c_23__n A_c[23]
Net lds_000_int_0_un1_n LDS_000_INT_0.un1
- Net a_26__n A[26]
+ Net a_23__n A[23]
Net lds_000_int_0_un0_n LDS_000_INT_0.un0
- Net a_c_27__n A_c[27]
+ Net a_c_24__n A_c[24]
Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3
- Net a_27__n A[27]
+ Net a_24__n A[24]
Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1
- Net a_c_28__n A_c[28]
+ Net a_c_25__n A_c[25]
Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0
- Net a_28__n A[28]
+ Net a_25__n A[25]
+ Net avec_exp_0_un3_n avec_exp_0.un3
+ Net a_c_26__n A_c[26]
+ Net avec_exp_0_un1_n avec_exp_0.un1
+ Net a_26__n A[26]
+ Net avec_exp_0_un0_n avec_exp_0.un0
+ Net a_c_27__n A_c[27]
Net bg_000_0_un3_n BG_000_0.un3
- Net a_c_29__n A_c[29]
+ Net a_27__n A[27]
Net bg_000_0_un1_n BG_000_0.un1
- Net a_29__n A[29]
+ Net a_c_28__n A_c[28]
Net bg_000_0_un0_n BG_000_0.un0
- Net a_c_30__n A_c[30]
- Net ds_000_dma_0_un3_n DS_000_DMA_0.un3
- Net a_30__n A[30]
- Net ds_000_dma_0_un1_n DS_000_DMA_0.un1
- Net a_c_31__n A_c[31]
- Net ds_000_dma_0_un0_n DS_000_DMA_0.un0
- Net as_000_dma_0_un3_n AS_000_DMA_0.un3
- Net as_000_dma_0_un1_n AS_000_DMA_0.un1
- Net as_000_dma_0_un0_n AS_000_DMA_0.un0
+ Net a_28__n A[28]
Net as_000_int_0_un3_n AS_000_INT_0.un3
+ Net a_c_29__n A_c[29]
Net as_000_int_0_un1_n AS_000_INT_0.un1
+ Net a_29__n A[29]
Net as_000_int_0_un0_n AS_000_INT_0.un0
+ Net a_c_30__n A_c[30]
+ Net dsack1_int_0_un3_n DSACK1_INT_0.un3
+ Net a_30__n A[30]
+ Net dsack1_int_0_un1_n DSACK1_INT_0.un1
+ Net a_c_31__n A_c[31]
+ Net dsack1_int_0_un0_n DSACK1_INT_0.un0
+ Net vma_int_0_un3_n VMA_INT_0.un3
+ Net vma_int_0_un1_n VMA_INT_0.un1
+ Net vma_int_0_un0_n VMA_INT_0.un0
End
Section Type Name
// ----------------------------------------------------------------------
@@ -509,7 +506,6 @@ Section Type Name
Input CLK_OSZI
Input VPA
Input RST
- Input RW
Input A_30_
Input A_29_
Input A_28_
@@ -547,14 +543,15 @@ Section Type Name
Output IPL_030_1_
Output IPL_030_0_
Bidi SIZE_1_
- Bidi DSACK_1_
Bidi AS_030
Bidi AS_000
+ Bidi RW_000
Bidi DS_030
Bidi UDS_000
Bidi LDS_000
Bidi A0
+ Bidi DSACK1
Bidi DTACK
+ Bidi RW
Bidi SIZE_0_
- Bidi DSACK_0_
End
diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf
index f7c1f00..767bba0 100644
--- a/Logic/bus68030.srf
+++ b/Logic/bus68030.srf
@@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
-#Thu May 29 22:04:21 2014
+#Sun Jun 01 01:03:18 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@@ -19,14 +19,15 @@ VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Pruning register CLK_REF(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D6
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:34:123:36|Pruning register CLK_000_D5
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":114:38:114:40|Pruning register CLK_OUT_PRE_33
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":146:2:146:3|Pruning register CLK_CNT_P(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:2:133:3|Pruning register CLK_CNT_N(1 downto 0)
-@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":99:36:99:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Pruning register CLK_REF(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0)
+@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@@ -37,7 +38,7 @@ State machine has 8 reachable states with original encodings of:
101
110
111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:34:117:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:34:120:36|Trying to extract state machine for register cpu_est
Extracted state machine for register cpu_est
State machine has 11 reachable states with original encodings of:
0000
@@ -53,7 +54,7 @@ State machine has 11 reachable states with original encodings of:
1111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 29 22:04:21 2014
+# Sun Jun 01 01:03:18 2014
###########################################################]
Map & Optimize Report
@@ -92,13 +93,13 @@ Simple gate primitives:
DFFRH 16 uses
DFFSH 27 uses
DFF 1 use
-BI_DIR 10 uses
-IBUF 30 uses
-BUFTH 4 uses
-OBUF 15 uses
-AND2 181 uses
+BI_DIR 12 uses
+IBUF 29 uses
+BUFTH 2 uses
+OBUF 16 uses
+AND2 185 uses
INV 151 uses
-OR2 20 uses
+OR2 21 uses
XOR2 1 use
@@ -109,6 +110,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 29 22:04:22 2014
+# Sun Jun 01 01:03:19 2014
###########################################################]
diff --git a/Logic/run_options.txt b/Logic/run_options.txt
index 3a4279f..7467fad 100644
--- a/Logic/run_options.txt
+++ b/Logic/run_options.txt
@@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
-#-- Written on Thu May 29 22:04:21 2014
+#-- Written on Sun Jun 01 01:03:18 2014
#project files
diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr
index 8856f72..ff3d9f0 100644
--- a/Logic/synlog/bus68030_fpga_mapper.srr
+++ b/Logic/synlog/bus68030_fpga_mapper.srr
@@ -32,13 +32,13 @@ Simple gate primitives:
DFFRH 16 uses
DFFSH 27 uses
DFF 1 use
-BI_DIR 10 uses
-IBUF 30 uses
-BUFTH 4 uses
-OBUF 15 uses
-AND2 181 uses
+BI_DIR 12 uses
+IBUF 29 uses
+BUFTH 2 uses
+OBUF 16 uses
+AND2 185 uses
INV 151 uses
-OR2 20 uses
+OR2 21 uses
XOR2 1 use
@@ -49,6 +49,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 29 22:04:22 2014
+# Sun Jun 01 01:03:19 2014
###########################################################]
diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt
index fb2f786..91f14a6 100644
--- a/Logic/synlog/report/BUS68030_compiler_errors.txt
+++ b/Logic/synlog/report/BUS68030_compiler_errors.txt
@@ -1,4 +1,3 @@
-@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":381:9:381:23|No matching overload for "="
-@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":381:29:381:44|Unable to evaluate expression type
-@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":381:29:381:44|Can't implement expression (no function signature?)
+@E: CL219 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":51:1:51:16|Multiple non-tristate drivers for net AMIGA_BUS_ENABLE in BUS68030
+@E: CL229 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":51:1:51:16|Unresolved tristate drivers for net AMIGA_BUS_ENABLE in BUS68030
diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt
index caf9b56..a4d0fce 100644
--- a/Logic/synlog/report/BUS68030_compiler_notes.txt
+++ b/Logic/synlog/report/BUS68030_compiler_notes.txt
@@ -2,6 +2,6 @@
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Trying to extract state machine for register SM_AMIGA
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:34:117:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Trying to extract state machine for register SM_AMIGA
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:34:120:36|Trying to extract state machine for register cpu_est
diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml
index 72201be..03277cf 100644
--- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml
+++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml
@@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt
- 6
+ 7
C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt
@@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
-
- 1401393861
+ 1401577398
\ No newline at end of file
diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt
index a83685b..4692fd5 100644
--- a/Logic/synlog/report/BUS68030_compiler_warnings.txt
+++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt
@@ -1,7 +1,8 @@
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Pruning register CLK_REF(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D6
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:34:123:36|Pruning register CLK_000_D5
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":114:38:114:40|Pruning register CLK_OUT_PRE_33
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":146:2:146:3|Pruning register CLK_CNT_P(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:2:133:3|Pruning register CLK_CNT_N(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Pruning register CLK_REF(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0)
diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
index 0a799f7..7cf21a2 100644
--- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
+++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
@@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
95MB
-1401393862
+1401577399
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index fdb8c3d..040bf97 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
- Written on Thu May 29 22:04:21 2014
+ Written on Sun Jun 01 01:03:18 2014
-->
diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep
index 2df5696..3067dfa 100644
--- a/Logic/synwork/BUS68030_compiler.fdep
+++ b/Logic/synwork/BUS68030_compiler.fdep
@@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401393859
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401577392
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig
index 8e31361..8b9175a 100644
--- a/Logic/synwork/BUS68030_compiler.fdeporig
+++ b/Logic/synwork/BUS68030_compiler.fdeporig
@@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401393859
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401577392
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs
index 3e9274d..fda9761 100644
Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ
diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg
index 6bd0619..7fd4607 100644
--- a/Logic/synwork/BUS68030_compiler.tlg
+++ b/Logic/synwork/BUS68030_compiler.tlg
@@ -1,13 +1,14 @@
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Pruning register CLK_REF(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D6
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:34:123:36|Pruning register CLK_000_D5
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":114:38:114:40|Pruning register CLK_OUT_PRE_33
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":146:2:146:3|Pruning register CLK_CNT_P(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:2:133:3|Pruning register CLK_CNT_N(1 downto 0)
-@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":99:36:99:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":233:2:233:3|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Pruning register CLK_REF(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0)
+@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@@ -18,7 +19,7 @@ State machine has 8 reachable states with original encodings of:
101
110
111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:34:117:36|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:34:120:36|Trying to extract state machine for register cpu_est
Extracted state machine for register cpu_est
State machine has 11 reachable states with original encodings of:
0000