diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 0a4c926..a599daf 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -102,6 +102,7 @@ signal BGACK_030_INT:STD_LOGIC := '1'; signal BGACK_030_INT_D:STD_LOGIC := '1'; signal AS_000_DMA:STD_LOGIC := '1'; signal DS_000_DMA:STD_LOGIC := '1'; +signal RW_000_DMA:STD_LOGIC := '1'; signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; signal A0_DMA: STD_LOGIC := '1'; signal FPU_CS_INT:STD_LOGIC := '1'; @@ -109,6 +110,7 @@ signal VMA_INT: STD_LOGIC := '1'; signal VPA_D: STD_LOGIC := '1'; signal UDS_000_INT: STD_LOGIC := '1'; signal LDS_000_INT: STD_LOGIC := '1'; +signal DS_000_ENABLE: STD_LOGIC := '0'; signal DSACK1_INT: STD_LOGIC := '1'; signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; @@ -117,15 +119,19 @@ signal CLK_OUT_PRE_50: STD_LOGIC := '1'; signal CLK_OUT_PRE_50_D: STD_LOGIC := '1'; signal CLK_OUT_PRE_25: STD_LOGIC := '1'; signal CLK_OUT_PRE_33: STD_LOGIC := '1'; +signal CLK_OUT_PRE: STD_LOGIC := '1'; +signal CLK_OUT_PRE_D: STD_LOGIC := '1'; +signal CLK_OUT_NE: STD_LOGIC := '1'; signal CLK_OUT_INT: STD_LOGIC := '1'; signal CLK_030_H: STD_LOGIC := '1'; signal CLK_000_D0: STD_LOGIC := '1'; signal CLK_000_D1: STD_LOGIC := '1'; signal CLK_000_D2: STD_LOGIC := '1'; signal CLK_000_D3: STD_LOGIC := '1'; -signal CLK_000_D4: STD_LOGIC := '1'; -signal CLK_000_D5: STD_LOGIC := '1'; -signal CLK_000_D6: STD_LOGIC := '1'; +signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000"; +signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000"; +signal CLK_000_PE: STD_LOGIC := '0'; +signal CLK_000_NE: STD_LOGIC := '0'; signal DTACK_D0: STD_LOGIC := '1'; begin @@ -147,29 +153,31 @@ begin state_machine: process(RST, CLK_OSZI) begin if(RST = '0' ) then - CLK_CNT_P <= "00"; - RESET <= '0'; - CLK_OUT_PRE_50 <= '0'; + CLK_CNT_P <= "00"; + RESET <= '0'; + CLK_OUT_PRE_50 <= '0'; CLK_OUT_PRE_50_D <= '0'; - CLK_OUT_PRE_33 <= '0'; - CLK_OUT_PRE_25 <= '0'; - CLK_OUT_INT <= '0'; - cpu_est <= E20; - CLK_000_D0 <= '1'; - CLK_000_D1 <= '1'; - CLK_000_D2 <= '1'; - CLK_000_D3 <= '1'; - CLK_000_D4 <= '1'; - CLK_000_D5 <= '1'; - CLK_000_D6 <= '1'; - VPA_D <= '1'; + CLK_OUT_PRE_33 <= '0'; + CLK_OUT_PRE_25 <= '0'; + CLK_OUT_PRE <= '0'; + CLK_OUT_PRE_D <= '0'; + CLK_OUT_NE <= '0'; + CLK_OUT_INT <= '0'; + cpu_est <= E20; + CLK_000_D0 <= '1'; + CLK_000_D1 <= '1'; + CLK_000_D2 <= '1'; + CLK_000_D3 <= '1'; + VPA_D <= '1'; DTACK_D0 <= '1'; SM_AMIGA <= IDLE_P; AS_000_INT <= '1'; RW_000_INT <= '1'; + RW_000_DMA <= '1'; AS_030_000_SYNC <= '1'; UDS_000_INT <= '1'; LDS_000_INT <= '1'; + DS_000_ENABLE <= '0'; CLK_REF <= "00"; VMA_INT <= '1'; FPU_CS_INT <= '1'; @@ -178,6 +186,10 @@ begin BGACK_030_INT_D <= '1'; DSACK1_INT <= '1'; IPL_030 <= "111"; + CLK_000_P_SYNC <= "0000000000000"; + CLK_000_N_SYNC <= "0000000000000"; + CLK_000_PE <= '0'; + CLK_000_NE <= '0'; AS_000_DMA <= '1'; DS_000_DMA <= '1'; SIZE_DMA <= "11"; @@ -207,23 +219,42 @@ begin CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25; end if; + --here the clock is selected + CLK_OUT_PRE <= CLK_OUT_PRE_25; + CLK_OUT_PRE_D <= CLK_OUT_PRE; + + --a negative edge is comming next cycle + if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then + CLK_OUT_NE <= '1'; + else + CLK_OUT_NE <= '0'; + end if; -- the external clock to the processor is generated here - CLK_OUT_INT <= CLK_OUT_PRE_25; --this way we know the clock of the next state: Its like looking in the future, cool! + CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool! --delayed Clocks and signals for edge detection CLK_000_D0 <= CLK_000; CLK_000_D1 <= CLK_000_D0; CLK_000_D2 <= CLK_000_D1; CLK_000_D3 <= CLK_000_D2; - CLK_000_D4 <= CLK_000_D3; - CLK_000_D5 <= CLK_000_D4; - CLK_000_D6 <= CLK_000_D5; + + --shift registers for edge detection + CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 ); + CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1 AND NOT CLK_000_D2 AND NOT CLK_000_D3; + CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 ); + CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1 AND CLK_000_D2 AND CLK_000_D3; + + -- values are determined empiracally for 7.09 MHz Clock + -- since the clock is not symmetrically these values differ! + CLK_000_PE <= CLK_000_P_SYNC(9); + CLK_000_NE <= CLK_000_N_SYNC(11); + DTACK_D0 <= DTACK; VPA_D <= VPA; --now: 68000 state machine and signals -- e-clock - if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then + if(CLK_000_PE = '1') then case (cpu_est) is when E1 => cpu_est <= E2 ; when E2 => cpu_est <= E3 ; @@ -281,11 +312,8 @@ begin FPU_CS_INT <= '1'; DSACK1_INT <= '1'; AS_000_INT <= '1'; - UDS_000_INT <= '1'; - LDS_000_INT <= '1'; - --AMIGA_BUS_ENABLE <= '1'; - elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks - + DS_000_ENABLE <= '0'; + elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks AS_030 = '0') then if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then FPU_CS_INT <= '0'; @@ -305,77 +333,70 @@ begin elsif(CLK_000_D0='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert VMA_INT <= '1'; end if; + + --uds/lds precalculation + if (DS_030 = '0') then --DS: set udl/lds + if(A0='0') then + UDS_000_INT <= '0'; + else + UDS_000_INT <= '1'; + end if; + if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then + LDS_000_INT <= '0'; + else + LDS_000_INT <= '1'; + end if; + end if; --Amiga statemachine case (SM_AMIGA) is when IDLE_P => --68000:S0 wait for a falling edge AMIGA_BUS_ENABLE_INT <= '1'; - + RW_000_INT <= '1'; if( CLK_000_D1='0' and CLK_000_D2= '1' and AS_030_000_SYNC = '0')then - if(nEXP_SPACE ='1')then + if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga SM_AMIGA<=IDLE_N; --go to s1 - else -- if this a delayed expansion space detection, aboard this cycle! - AS_030_000_SYNC <= '1'; end if; end if; when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe - if(CLK_000_D0='1')then --go to s2 + if(CLK_000_PE='1')then --go to s2 SM_AMIGA <= AS_SET_P; --as for amiga set! AS_000_INT <= '0'; RW_000_INT <= RW; - if (RW='1' and DS_030 = '0') then --read: set udl/lds - if(A0='0') then - UDS_000_INT <= '0'; - else - UDS_000_INT <= '1'; - end if; - if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then - LDS_000_INT <= '0'; - else - LDS_000_INT <= '1'; - end if; + if (RW='1' ) then --read: set udl/lds + DS_000_ENABLE <= '1'; end if; end if; when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here - if(CLK_000_D0='0')then --go to s3 + if(CLK_000_NE='1')then --go to s3 SM_AMIGA<=AS_SET_N; - if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late - if(A0='0') then - UDS_000_INT <= '0'; - else - UDS_000_INT <= '1'; - end if; - if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then - LDS_000_INT <= '0'; - else - LDS_000_INT <= '1'; - end if; - end if; end if; when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write - if(CLK_000_D0='1')then --go to s4 + + if(CLK_000_PE='1')then --go to s4 + DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late + -- set DS-Enable without respect to rw: this simplifies the life for the syntesizer SM_AMIGA <= SAMPLE_DTACK_P; end if; when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA - if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge - ((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle + if( CLK_000_NE='1' and --falling edge + ((VPA_D = '1' AND DTACK='0') OR --DTACK end cycle (VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle )then --go to s5 SM_AMIGA<=DATA_FETCH_N; end if; when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock - if(CLK_000_D0 = '1')then --go to s6 + if(CLK_000_PE = '1')then --go to s6 SM_AMIGA<=DATA_FETCH_P; end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! - --if( CLK_000_D2 ='1' AND CLK_000_D3 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge + if( CLK_000_D1='1' and CLK_OUT_NE = '0') then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge DSACK1_INT <='0'; - AS_030_000_SYNC <= '1'; --cycle end - --els - if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge + end if; + if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge SM_AMIGA<=END_CYCLE_N; if(AS_030 ='1') then AMIGA_BUS_ENABLE_INT <= '1'; @@ -386,9 +407,8 @@ begin AMIGA_BUS_ENABLE_INT <= '1'; end if; - if(CLK_000_D0='1')then --go to s0 - SM_AMIGA<=IDLE_P; - RW_000_INT <= '1'; + if(CLK_000_PE='1')then --go to s0 + SM_AMIGA<=IDLE_P; end if; end case; @@ -406,7 +426,7 @@ begin --set AS_000 if( CLK_030='0') then AS_000_DMA <= '0'; - RW_000_INT <= RW_000; + RW_000_DMA <= RW_000; elsif(AS_000_DMA = '0' and CLK_030='1')then CLK_030_H <= '1'; end if; @@ -436,6 +456,7 @@ begin DS_000_DMA <= '1'; SIZE_DMA <= "11"; A0_DMA <= '0'; + RW_000_DMA <= '1'; CLK_030_H <= '0'; end if; end if; @@ -444,7 +465,7 @@ begin --output clock assignment CLK_DIV_OUT <= CLK_OUT_INT; CLK_EXP <= CLK_OUT_INT; - AVEC_EXP <= AMIGA_BUS_ENABLE_INT; + AVEC_EXP <= CLK_000_PE; AMIGA_BUS_ENABLE <= AMIGA_BUS_ENABLE_INT; --dma stuff DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else @@ -459,10 +480,13 @@ begin SIZE_DMA; --fpu - FPU_CS <= FPU_CS_INT; + FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' + else '1'; --if no copro is installed: - BERR <= 'Z' when FPU_CS_INT ='1' else '0'; + --BERR <= 'Z' when FPU_CS_INT ='1' else '0'; + BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' + else 'Z'; @@ -478,7 +502,7 @@ begin '1' WHEN (RW='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space '0' WHEN (RW='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space '0'; --Point towarts TK - AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off + AMIGA_BUS_ENABLE_LOW <= CLK_OUT_NE; --for now: allways off --e and VMA E <= cpu_est(3); @@ -495,8 +519,10 @@ begin RW_000_INT; UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle + '1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet UDS_000_INT; LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle + '1' when DS_000_ENABLE ='0' else -- datastrobe not ready jet LDS_000_INT; --dsack @@ -504,7 +530,7 @@ begin DSACK1_INT; --rw RW <= 'Z' when BGACK_030_INT ='1' else - RW_000_INT; + RW_000_DMA; BGACK_030 <= BGACK_030_INT; end Behavioral; \ No newline at end of file diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index f0ce556..0db0777 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,6 +1,6 @@ +[synthesis-type] +tool=Synplify [STRATEGY-LIST] Normal=True, 1385910337 [TOUCHED-REPORT] -Design.tt4File=1401573640 -[synthesis-type] -tool=Synplify +Design.tt4File=1402219813 diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi index f537a6f..8e0c72c 100644 --- a/Logic/68030_TK.cmi +++ b/Logic/68030_TK.cmi @@ -1,15 +1,15 @@ [WINDOWS] MAIN_WINDOW_POSITION=0,0,1920,1200 LEFT_PANE_WIDTH=634 -CHILD_FRAME_STATE=Maximal -CHILD_WINDOW_SIZE=1920,974 -CHILD_WINDOW_POS=-8,-30 +CHILD_FRAME_STATE=Normal +CHILD_WINDOW_SIZE=950,901 +CHILD_WINDOW_POS=950,0 [GUI SETTING] Remember_Setting=1 Open_PV_Opt=2 Open_PV=0 PV_IS_ACTIVE=0 -ACTIVE_SHEET=Pin Attributes +ACTIVE_SHEET=Global Constraints Show_Def_Opt=2 Show_Def_Val=1 Expand_All_Column=0 diff --git a/Logic/68030_TK.lci b/Logic/68030_TK.lci index b48508e..2335c4e 100644 --- a/Logic/68030_TK.lci +++ b/Logic/68030_TK.lci @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 06/01/2014; -TIME = 00:00:40; +DATE = 06/08/2014; +TIME = 11:30:13; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -24,14 +24,15 @@ Synthesis = Synplify; [Backannotate Assignments] [Global Constraints] -Spread_placement = No; +Spread_placement = Yes; Zero_hold_time = Yes; Max_pterm_split = 16; Max_pterm_collapse = 16; Nodes_collapsing_mode = Speed; Max_fanin = 32; Set_reset_dont_care = Yes; -Balanced_partitioning = No; +Balanced_partitioning = Yes; +Max_macrocell_percent = 100; [Location Assignments] layer = OFF; diff --git a/Logic/68030_TK.lct b/Logic/68030_TK.lct index b48508e..2335c4e 100644 --- a/Logic/68030_TK.lct +++ b/Logic/68030_TK.lct @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 06/01/2014; -TIME = 00:00:40; +DATE = 06/08/2014; +TIME = 11:30:13; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -24,14 +24,15 @@ Synthesis = Synplify; [Backannotate Assignments] [Global Constraints] -Spread_placement = No; +Spread_placement = Yes; Zero_hold_time = Yes; Max_pterm_split = 16; Max_pterm_collapse = 16; Nodes_collapsing_mode = Speed; Max_fanin = 32; Set_reset_dont_care = Yes; -Balanced_partitioning = No; +Balanced_partitioning = Yes; +Max_macrocell_percent = 100; [Location Assignments] layer = OFF; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 96487b0..b48eb81 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -189562,3 +189562,11862 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 06/07/14 23:03:13 ########### + +########## Tcl recorder starts at 06/08/14 11:19:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:19:18 ########### + + +########## Tcl recorder starts at 06/08/14 11:19:18 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:19:18 ########### + + +########## Tcl recorder starts at 06/08/14 11:19:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:19:42 ########### + + +########## Tcl recorder starts at 06/08/14 11:19:42 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:19:42 ########### + + +########## Tcl recorder starts at 06/08/14 11:22:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:22:24 ########### + + +########## Tcl recorder starts at 06/08/14 11:22:24 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:22:24 ########### + + +########## Tcl recorder starts at 06/08/14 11:22:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:22:43 ########### + + +########## Tcl recorder starts at 06/08/14 11:22:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:22:43 ########### + + +########## Tcl recorder starts at 06/08/14 11:23:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:23:09 ########### + + +########## Tcl recorder starts at 06/08/14 11:23:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:23:09 ########### + + +########## Tcl recorder starts at 06/08/14 11:24:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:24:15 ########### + + +########## Tcl recorder starts at 06/08/14 11:24:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:24:15 ########### + + +########## Tcl recorder starts at 06/08/14 11:25:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:25:46 ########### + + +########## Tcl recorder starts at 06/08/14 11:25:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:25:47 ########### + + +########## Tcl recorder starts at 06/08/14 11:26:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:26:27 ########### + + +########## Tcl recorder starts at 06/08/14 11:26:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:26:27 ########### + + +########## Tcl recorder starts at 06/08/14 11:27:03 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:27:03 ########### + + +########## Tcl recorder starts at 06/08/14 11:27:29 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:27:29 ########### + + +########## Tcl recorder starts at 06/08/14 11:27:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:27:33 ########### + + +########## Tcl recorder starts at 06/08/14 11:27:56 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:27:56 ########### + + +########## Tcl recorder starts at 06/08/14 11:28:01 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:28:01 ########### + + +########## Tcl recorder starts at 06/08/14 11:28:44 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:28:44 ########### + + +########## Tcl recorder starts at 06/08/14 11:29:26 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:29:26 ########### + + +########## Tcl recorder starts at 06/08/14 11:29:43 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:29:43 ########### + + +########## Tcl recorder starts at 06/08/14 11:29:54 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:29:54 ########### + + +########## Tcl recorder starts at 06/08/14 11:36:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:36:01 ########### + + +########## Tcl recorder starts at 06/08/14 11:36:01 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:36:01 ########### + + +########## Tcl recorder starts at 06/08/14 11:38:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:38:27 ########### + + +########## Tcl recorder starts at 06/08/14 11:38:28 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:38:28 ########### + + +########## Tcl recorder starts at 06/08/14 11:45:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:45:11 ########### + + +########## Tcl recorder starts at 06/08/14 11:45:11 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:45:11 ########### + + +########## Tcl recorder starts at 06/08/14 11:59:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:59:15 ########### + + +########## Tcl recorder starts at 06/08/14 11:59:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 11:59:15 ########### + + +########## Tcl recorder starts at 06/08/14 12:00:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:00:59 ########### + + +########## Tcl recorder starts at 06/08/14 12:00:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:00:59 ########### + + +########## Tcl recorder starts at 06/08/14 12:04:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:04:26 ########### + + +########## Tcl recorder starts at 06/08/14 12:04:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:04:26 ########### + + +########## Tcl recorder starts at 06/08/14 12:08:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:08:07 ########### + + +########## Tcl recorder starts at 06/08/14 12:08:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:08:07 ########### + + +########## Tcl recorder starts at 06/08/14 12:14:02 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:14:03 ########### + + +########## Tcl recorder starts at 06/08/14 12:14:03 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:14:03 ########### + + +########## Tcl recorder starts at 06/08/14 12:16:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:16:27 ########### + + +########## Tcl recorder starts at 06/08/14 12:16:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:16:27 ########### + + +########## Tcl recorder starts at 06/08/14 12:18:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:18:10 ########### + + +########## Tcl recorder starts at 06/08/14 12:18:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:18:10 ########### + + +########## Tcl recorder starts at 06/08/14 12:21:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:21:12 ########### + + +########## Tcl recorder starts at 06/08/14 12:21:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:21:12 ########### + + +########## Tcl recorder starts at 06/08/14 12:23:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:23:42 ########### + + +########## Tcl recorder starts at 06/08/14 12:23:42 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:23:42 ########### + + +########## Tcl recorder starts at 06/08/14 12:24:28 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:24:28 ########### + + +########## Tcl recorder starts at 06/08/14 12:24:28 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:24:28 ########### + + +########## Tcl recorder starts at 06/08/14 12:26:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:26:18 ########### + + +########## Tcl recorder starts at 06/08/14 12:26:18 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:26:18 ########### + + +########## Tcl recorder starts at 06/08/14 12:27:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:27:24 ########### + + +########## Tcl recorder starts at 06/08/14 12:27:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:27:25 ########### + + +########## Tcl recorder starts at 06/08/14 12:28:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:28:10 ########### + + +########## Tcl recorder starts at 06/08/14 12:28:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:28:10 ########### + + +########## Tcl recorder starts at 06/08/14 12:29:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:29:59 ########### + + +########## Tcl recorder starts at 06/08/14 12:29:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:29:59 ########### + + +########## Tcl recorder starts at 06/08/14 12:31:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:31:14 ########### + + +########## Tcl recorder starts at 06/08/14 12:31:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:31:15 ########### + + +########## Tcl recorder starts at 06/08/14 12:32:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:32:49 ########### + + +########## Tcl recorder starts at 06/08/14 12:32:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:32:49 ########### + + +########## Tcl recorder starts at 06/08/14 12:40:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:40:52 ########### + + +########## Tcl recorder starts at 06/08/14 12:40:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 12:40:52 ########### + + +########## Tcl recorder starts at 06/08/14 13:29:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:29:51 ########### + + +########## Tcl recorder starts at 06/08/14 13:29:51 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:29:51 ########### + + +########## Tcl recorder starts at 06/08/14 13:30:45 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:30:45 ########### + + +########## Tcl recorder starts at 06/08/14 13:30:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:30:45 ########### + + +########## Tcl recorder starts at 06/08/14 13:31:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:31:30 ########### + + +########## Tcl recorder starts at 06/08/14 13:31:30 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:31:30 ########### + + +########## Tcl recorder starts at 06/08/14 13:32:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:32:12 ########### + + +########## Tcl recorder starts at 06/08/14 13:32:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:32:12 ########### + + +########## Tcl recorder starts at 06/08/14 13:52:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:52:42 ########### + + +########## Tcl recorder starts at 06/08/14 13:52:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:52:43 ########### + + +########## Tcl recorder starts at 06/08/14 13:53:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:53:44 ########### + + +########## Tcl recorder starts at 06/08/14 13:53:44 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:53:44 ########### + + +########## Tcl recorder starts at 06/08/14 13:55:25 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:55:25 ########### + + +########## Tcl recorder starts at 06/08/14 13:55:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:55:25 ########### + + +########## Tcl recorder starts at 06/08/14 13:56:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:56:51 ########### + + +########## Tcl recorder starts at 06/08/14 13:56:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 13:56:52 ########### + + +########## Tcl recorder starts at 06/08/14 14:00:00 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 14:00:00 ########### + + +########## Tcl recorder starts at 06/08/14 14:00:00 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/08/14 14:00:00 ########### + + +########## Tcl recorder starts at 06/09/14 09:31:28 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:31:28 ########### + + +########## Tcl recorder starts at 06/09/14 09:31:29 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:31:29 ########### + + +########## Tcl recorder starts at 06/09/14 09:36:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:36:18 ########### + + +########## Tcl recorder starts at 06/09/14 09:36:18 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:36:18 ########### + + +########## Tcl recorder starts at 06/09/14 09:42:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:42:04 ########### + + +########## Tcl recorder starts at 06/09/14 09:42:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:42:05 ########### + + +########## Tcl recorder starts at 06/09/14 09:43:28 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:43:28 ########### + + +########## Tcl recorder starts at 06/09/14 09:43:28 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:43:28 ########### + + +########## Tcl recorder starts at 06/09/14 09:45:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:45:27 ########### + + +########## Tcl recorder starts at 06/09/14 09:45:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:45:27 ########### + + +########## Tcl recorder starts at 06/09/14 09:46:36 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:46:36 ########### + + +########## Tcl recorder starts at 06/09/14 09:46:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:46:36 ########### + + +########## Tcl recorder starts at 06/09/14 09:47:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:47:27 ########### + + +########## Tcl recorder starts at 06/09/14 09:47:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:47:27 ########### + + +########## Tcl recorder starts at 06/09/14 09:48:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:48:08 ########### + + +########## Tcl recorder starts at 06/09/14 09:48:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:48:09 ########### + + +########## Tcl recorder starts at 06/09/14 09:49:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:49:27 ########### + + +########## Tcl recorder starts at 06/09/14 09:49:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:49:27 ########### + + +########## Tcl recorder starts at 06/09/14 09:50:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:50:47 ########### + + +########## Tcl recorder starts at 06/09/14 09:50:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:50:47 ########### + + +########## Tcl recorder starts at 06/09/14 09:53:49 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:53:49 ########### + + +########## Tcl recorder starts at 06/09/14 09:53:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 09:53:49 ########### + + +########## Tcl recorder starts at 06/09/14 10:07:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:07:58 ########### + + +########## Tcl recorder starts at 06/09/14 10:07:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:07:58 ########### + + +########## Tcl recorder starts at 06/09/14 10:09:00 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:09:00 ########### + + +########## Tcl recorder starts at 06/09/14 10:09:00 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:09:00 ########### + + +########## Tcl recorder starts at 06/09/14 10:09:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:09:31 ########### + + +########## Tcl recorder starts at 06/09/14 10:09:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:09:31 ########### + + +########## Tcl recorder starts at 06/09/14 10:10:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:10:32 ########### + + +########## Tcl recorder starts at 06/09/14 10:10:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:10:32 ########### + + +########## Tcl recorder starts at 06/09/14 10:14:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:14:15 ########### + + +########## Tcl recorder starts at 06/09/14 10:14:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:14:16 ########### + + +########## Tcl recorder starts at 06/09/14 10:16:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:16:07 ########### + + +########## Tcl recorder starts at 06/09/14 10:16:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:16:07 ########### + + +########## Tcl recorder starts at 06/09/14 10:17:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:17:15 ########### + + +########## Tcl recorder starts at 06/09/14 10:17:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:17:15 ########### + + +########## Tcl recorder starts at 06/09/14 10:18:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:18:14 ########### + + +########## Tcl recorder starts at 06/09/14 10:18:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:18:14 ########### + + +########## Tcl recorder starts at 06/09/14 10:18:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:18:56 ########### + + +########## Tcl recorder starts at 06/09/14 10:18:57 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:18:57 ########### + + +########## Tcl recorder starts at 06/09/14 10:19:54 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:19:54 ########### + + +########## Tcl recorder starts at 06/09/14 10:19:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:19:54 ########### + + +########## Tcl recorder starts at 06/09/14 10:21:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:21:31 ########### + + +########## Tcl recorder starts at 06/09/14 10:21:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:21:31 ########### + + +########## Tcl recorder starts at 06/09/14 10:23:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:23:06 ########### + + +########## Tcl recorder starts at 06/09/14 10:23:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:23:06 ########### + + +########## Tcl recorder starts at 06/09/14 10:27:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:27:17 ########### + + +########## Tcl recorder starts at 06/09/14 10:27:18 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/09/14 10:27:18 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 26691b5..226f80b 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,111 +1,115 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE 68030_tk -#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \ -# IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ -# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \ -# A_25_ A_24_ A_23_ -#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n \ -# inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \ -# nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c \ -# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \ -# inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n \ -# gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ \ -# inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ -# IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n inst_CLK_000_D2 \ -# IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \ -# SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ \ -# ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n CLK_OUT_PRE_25_0 \ -# fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n \ -# cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n \ -# cpu_est_3_reg N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa \ -# N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \ -# state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i \ -# N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ -# state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ -# state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ -# FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ -# state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ -# state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 \ -# state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ -# state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 \ -# state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \ -# un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ -# UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \ -# state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 \ -# RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \ -# state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i \ -# state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 \ -# AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ -# N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ -# un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ -# state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ -# state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ -# AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ -# AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ -# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ -# state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ -# AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ -# state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \ -# state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 \ -# AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ -# un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ -# state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ -# state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ -# state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ -# state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ -# AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ -# state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ -# CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ -# un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ -# state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ -# cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ -# cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 \ -# N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 \ -# state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i \ -# UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n \ -# UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n \ -# N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ -# CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n \ -# N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ -# AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ -# state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ -# a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ -# a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ -# state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ -# sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ -# state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ -# sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ -# state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ -# state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ -# state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ -# cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ -# state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ -# state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ -# cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ -# UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ -# cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ -# state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \ -# state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i \ -# ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n \ -# a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \ -# ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n \ -# a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n \ -# CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n \ -# as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \ -# dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n \ -# UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \ -# avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n \ -# bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -# a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ -# rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n \ -# as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n \ -# ds_000_dma_0_un0_n clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n \ -# a_c_25__n a_c_26__n a_c_27__n +#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 SIZE_0_ RW_000 A_30_ \ +# DS_030 A_29_ UDS_000 A_28_ LDS_000 A_27_ A0 A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ \ +# BG_000 A_22_ BGACK_030 A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ \ +# CLK_DIV_OUT A_16_ CLK_EXP IPL_030_1_ FPU_CS IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC \ +# FC_0_ AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW CIIN +#$ NODES 425 amiga_bus_enable_int_0_un3_n a_c_16__n amiga_bus_enable_int_0_un1_n \ +# amiga_bus_enable_int_0_un0_n a_c_17__n bg_000_0_un3_n bg_000_0_un1_n a_c_18__n \ +# bg_000_0_un0_n inst_BGACK_030_INTreg lds_000_int_0_un3_n vcc_n_n a_c_19__n \ +# lds_000_int_0_un1_n inst_avec_expreg lds_000_int_0_un0_n inst_VMA_INTreg a_c_20__n \ +# ds_000_enable_0_un3_n inst_AMIGA_BUS_ENABLE_INTreg ds_000_enable_0_un1_n \ +# inst_CLK_OUT_NEreg a_c_21__n ds_000_enable_0_un0_n inst_AS_030_000_SYNC \ +# uds_000_int_0_un3_n inst_BGACK_030_INT_D a_c_22__n uds_000_int_0_un1_n \ +# inst_AS_000_DMA uds_000_int_0_un0_n inst_VPA_D a_c_23__n inst_CLK_OUT_PRE_50_D \ +# inst_CLK_OUT_PRE a_c_24__n inst_CLK_000_D0 inst_CLK_000_D1 a_c_25__n \ +# inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 a_c_26__n inst_CLK_000_D2 inst_CLK_000_D3 \ +# a_c_27__n inst_CLK_000_NE gnd_n_n a_c_28__n inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ \ +# a_c_29__n CLK_000_N_SYNC_11_ inst_AS_000_INT a_c_30__n SM_AMIGA_7_ SM_AMIGA_6_ \ +# a_c_31__n SM_AMIGA_1_ SM_AMIGA_0_ A0_c SM_AMIGA_4_ inst_RW_000_INT nEXP_SPACE_c \ +# inst_DSACK1_INT state_machine_un3_clk_out_pre_50_n BG_030_c inst_CLK_030_H \ +# inst_RW_000_DMA BG_000DFFSHreg un1_LDS_000_INT inst_LDS_000_INT inst_DS_000_ENABLE \ +# BGACK_000_c un1_UDS_000_INT inst_UDS_000_INT CLK_030_c CLK_000_c inst_DS_000_DMA \ +# SIZE_DMA_0_ CLK_OSZI_c SIZE_DMA_1_ inst_A0_DMA CLK_000_N_SYNC_0_ CLK_OUT_INTreg \ +# CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ IPL_030DFFSH_0_reg \ +# CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ IPL_030DFFSH_1_reg CLK_000_N_SYNC_6_ \ +# CLK_000_N_SYNC_7_ IPL_030DFFSH_2_reg CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ \ +# ipl_c_0__n CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ ipl_c_1__n CLK_000_P_SYNC_1_ \ +# CLK_000_P_SYNC_2_ ipl_c_2__n CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ DSACK1_c \ +# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ DTACK_c CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \ +# un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \ +# SM_AMIGA_5_ SM_AMIGA_3_ RST_c SM_AMIGA_2_ RESETDFFRHreg RW_c fc_c_0__n fc_c_1__n \ +# AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i DS_000_ENABLE_0_sqmuxa_i \ +# un1_SM_AMIGA_0_sqmuxa_1_i state_machine_un10_clk_000_ne_i_n \ +# state_machine_un4_clk_000_ne_i_n CLK_OUT_PRE_25_0 \ +# state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i \ +# sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n \ +# state_machine_un6_bgack_000_0_n N_167_i cpu_est_0_ N_166_i cpu_est_1_ \ +# AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_162_i cpu_est_3_reg N_161_i cpu_estse N_152_i \ +# state_machine_un10_clk_000_d0_i_n state_machine_un5_clk_000_d0_i_n \ +# state_machine_un12_clk_000_d0_0_n N_198 cpu_est_ns_0_1__n N_207 N_156_i \ +# SM_AMIGA_0_sqmuxa N_155_i N_89 N_163_i N_90 state_machine_un5_clk_000_d0_1_i_n \ +# state_machine_un8_bg_030_n state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 \ +# N_160_i N_87 cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 \ +# state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 \ +# state_machine_size_dma_4_0_1__n N_101 CLK_030_H_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ +# CLK_030_H_1_sqmuxa_i N_85 state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa \ +# un3_dtack_i AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n \ +# un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ +# state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \ +# AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 \ +# AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 N_93_i N_66 state_machine_rw_000_int_3_n \ +# AS_030_000_SYNC_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ +# AS_030_000_SYNC_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \ +# state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n \ +# un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \ +# CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa N_92_i \ +# DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i \ +# state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \ +# sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i \ +# state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n \ +# sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 \ +# sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i \ +# state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 \ +# state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 \ +# cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n un1_UDS_000_INT_0 \ +# state_machine_un6_clk_000_p_sync_n state_machine_un7_ds_030_i_n \ +# state_machine_un10_clk_000_d0_n A0_c_i state_machine_un5_clk_000_d0_n \ +# size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 state_machine_un10_clk_000_ne_1_n \ +# N_84_0_1 N_162 N_84_0_2 state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 \ +# cpu_est_ns_0_1_2__n N_167 N_198_1 DSACK1_INT_1_sqmuxa N_198_2 \ +# state_machine_un6_bgack_000_n N_207_1 DS_000_ENABLE_0_sqmuxa N_207_2 \ +# state_machine_un10_clk_000_ne_n N_207_3 N_86 N_207_4 \ +# state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \ +# state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n \ +# state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i \ +# DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \ +# AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 VPA_D_i \ +# cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i \ +# state_machine_un10_clk_000_d0_1_n a_i_19__n state_machine_un10_clk_000_d0_2_0_n \ +# DSACK1_INT_0_sqmuxa_i state_machine_un10_clk_000_d0_3_n a_i_16__n \ +# state_machine_clk_000_n_sync_2_1_0__n a_i_18__n \ +# state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i \ +# state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i un19_fpu_cs_1 \ +# CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 cpu_est_i_3__n un19_fpu_cs_4 \ +# cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n un19_fpu_cs_6 \ +# state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 CLK_000_D1_i \ +# state_machine_un10_clk_000_ne_1_0_n state_machine_un5_clk_000_d0_2_i_0_n \ +# dsack1_int_0_un3_n cpu_est_i_2__n dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i \ +# dsack1_int_0_un0_n state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n \ +# CLK_030_i bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \ +# cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n RW_000_i \ +# cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n vma_int_0_un3_n \ +# AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n AS_000_i \ +# ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i ipl_030_0_0__un0_n \ +# N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i ipl_030_0_1__un1_n \ +# sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i ipl_030_0_2__un3_n sm_amiga_i_0__n \ +# ipl_030_0_2__un1_n sm_amiga_i_1__n ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n \ +# a_i_31__n cpu_estse_2_un1_n a_i_28__n cpu_estse_2_un0_n a_i_29__n \ +# as_000_dma_0_un3_n a_i_26__n as_000_dma_0_un1_n a_i_27__n as_000_dma_0_un0_n \ +# a_i_24__n ds_000_dma_0_un3_n a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n \ +# rw_000_dma_0_un3_n CLK_OUT_PRE_i rw_000_dma_0_un1_n CLK_OUT_PRE_50_D_i \ +# rw_000_dma_0_un0_n AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c \ +# clk_030_h_0_un0_n cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n \ +# DS_030_c rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n \ +# as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n \ +# as_030_000_sync_0_un0_n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ @@ -113,280 +117,308 @@ A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \ AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \ -DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \ -a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF \ -inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF A0_c.BLIF inst_VMA_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ -inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF \ -inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF \ -inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF vcc_n_n.BLIF \ -gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ -CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \ -CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ -inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \ -state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF \ -IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF \ -IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF \ -inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF \ -RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \ -fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF \ -state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF \ -state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF \ -cpu_est_3_reg.BLIF N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF \ -N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF \ -state_machine_un8_bgack_030_int_n.BLIF N_160_i.BLIF N_92.BLIF N_154_i.BLIF \ -state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ -N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF CLK_030_H_1_sqmuxa.BLIF \ -cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF \ -state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \ -state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF \ -FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \ -un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF \ -un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF \ -state_machine_un3_clk_030_i_n.BLIF N_94.BLIF \ -state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF \ -state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF \ -state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF \ -state_machine_un3_bgack_030_int_d_i_n.BLIF \ -state_machine_un10_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF \ -UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ -UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \ -state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \ -RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF \ -N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF N_100.BLIF N_95_i.BLIF N_91.BLIF \ -sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF \ -state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF \ -state_machine_uds_000_int_7_n.BLIF sm_amiga_ns_0_0__n.BLIF \ -RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \ -un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF \ -BG_030_c_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ -state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF \ -state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF \ -state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF \ -N_59_0.BLIF N_86.BLIF state_machine_un10_bgack_030_int_0_n.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF \ -state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF \ -N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF \ -N_97.BLIF N_100_i.BLIF N_99.BLIF un1_SM_AMIGA_8_0.BLIF \ -state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF \ -un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ -RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF \ -AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF \ -DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF \ -state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \ -state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF \ -state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF \ -N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \ -AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF \ -state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF \ -state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF \ -un1_as_030_000_sync8.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF \ -un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF \ -state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF \ -N_157.BLIF state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF \ -cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF \ -N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF N_152.BLIF N_220_2.BLIF \ -N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF \ -cpu_est_ns_1__n.BLIF N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF \ -DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF \ -UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF cpu_est_i_2__n.BLIF \ -UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF \ -cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF \ -N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF \ -state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \ -state_machine_un8_bg_030_2_n.BLIF sm_amiga_i_1__n.BLIF \ -state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF \ -state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \ -state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF \ -state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF \ -state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF \ -state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF \ -state_machine_un28_clk_030_5_n.BLIF N_99_i.BLIF \ -state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF \ -state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \ -state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF \ -state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \ -state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF \ -LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF \ -state_machine_un28_clk_000_d1_1_n.BLIF \ -state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \ -state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF \ -sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF \ -RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ -cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF \ -AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF \ -state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF CLK_030_i.BLIF \ -ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ -ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF \ -sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \ -ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \ -ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \ -bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF \ -as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF \ -as_030_000_sync_0_un0_n.BLIF FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF \ -CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF \ -fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF \ -as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF RW_000_c.BLIF \ -dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF \ -dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF \ -vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF \ -avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF \ -bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ -a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF \ -a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ -a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ -a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF \ -rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF \ -as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF \ -ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF \ -ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF \ -clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF \ -a_c_27__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \ -UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ -A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF +DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF amiga_bus_enable_int_0_un3_n.BLIF \ +a_c_16__n.BLIF amiga_bus_enable_int_0_un1_n.BLIF \ +amiga_bus_enable_int_0_un0_n.BLIF a_c_17__n.BLIF bg_000_0_un3_n.BLIF \ +bg_000_0_un1_n.BLIF a_c_18__n.BLIF bg_000_0_un0_n.BLIF \ +inst_BGACK_030_INTreg.BLIF lds_000_int_0_un3_n.BLIF vcc_n_n.BLIF \ +a_c_19__n.BLIF lds_000_int_0_un1_n.BLIF inst_avec_expreg.BLIF \ +lds_000_int_0_un0_n.BLIF inst_VMA_INTreg.BLIF a_c_20__n.BLIF \ +ds_000_enable_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF \ +ds_000_enable_0_un1_n.BLIF inst_CLK_OUT_NEreg.BLIF a_c_21__n.BLIF \ +ds_000_enable_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF uds_000_int_0_un3_n.BLIF \ +inst_BGACK_030_INT_D.BLIF a_c_22__n.BLIF uds_000_int_0_un1_n.BLIF \ +inst_AS_000_DMA.BLIF uds_000_int_0_un0_n.BLIF inst_VPA_D.BLIF a_c_23__n.BLIF \ +inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_OUT_PRE.BLIF a_c_24__n.BLIF \ +inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF a_c_25__n.BLIF \ +inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF a_c_26__n.BLIF \ +inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF a_c_27__n.BLIF inst_CLK_000_NE.BLIF \ +gnd_n_n.BLIF a_c_28__n.BLIF inst_CLK_OUT_PRE_D.BLIF CLK_000_P_SYNC_9_.BLIF \ +a_c_29__n.BLIF CLK_000_N_SYNC_11_.BLIF inst_AS_000_INT.BLIF a_c_30__n.BLIF \ +SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF a_c_31__n.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_0_.BLIF A0_c.BLIF SM_AMIGA_4_.BLIF inst_RW_000_INT.BLIF \ +nEXP_SPACE_c.BLIF inst_DSACK1_INT.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ +BG_030_c.BLIF inst_CLK_030_H.BLIF inst_RW_000_DMA.BLIF BG_000DFFSHreg.BLIF \ +un1_LDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \ +BGACK_000_c.BLIF un1_UDS_000_INT.BLIF inst_UDS_000_INT.BLIF CLK_030_c.BLIF \ +CLK_000_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF CLK_OSZI_c.BLIF \ +SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF CLK_000_N_SYNC_0_.BLIF CLK_OUT_INTreg.BLIF \ +CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \ +IPL_030DFFSH_0_reg.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \ +IPL_030DFFSH_1_reg.BLIF CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF \ +IPL_030DFFSH_2_reg.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \ +ipl_c_0__n.BLIF CLK_000_N_SYNC_10_.BLIF CLK_000_P_SYNC_0_.BLIF ipl_c_1__n.BLIF \ +CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF ipl_c_2__n.BLIF \ +CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF DSACK1_c.BLIF \ +CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF DTACK_c.BLIF \ +CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +un1_as_030.BLIF un19_fpu_cs.BLIF state_machine_un10_bg_030_n.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF RST_c.BLIF SM_AMIGA_2_.BLIF \ +RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \ +DS_000_ENABLE_0_sqmuxa_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF \ +state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un4_clk_000_ne_i_n.BLIF \ +CLK_OUT_PRE_25_0.BLIF state_machine_un6_clk_000_ne_i_n.BLIF N_97_i.BLIF \ +sm_amiga_ns_0_4__n.BLIF N_99_i.BLIF N_98_i.BLIF sm_amiga_ns_0_5__n.BLIF \ +N_86_i.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_167_i.BLIF cpu_est_0_.BLIF N_166_i.BLIF \ +cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_162_i.BLIF \ +cpu_est_3_reg.BLIF N_161_i.BLIF cpu_estse.BLIF N_152_i.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un5_clk_000_d0_i_n.BLIF \ +state_machine_un12_clk_000_d0_0_n.BLIF N_198.BLIF cpu_est_ns_0_1__n.BLIF \ +N_207.BLIF N_156_i.BLIF SM_AMIGA_0_sqmuxa.BLIF N_155_i.BLIF N_89.BLIF \ +N_163_i.BLIF N_90.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF \ +state_machine_un8_bg_030_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +N_91.BLIF N_159_i.BLIF N_92.BLIF N_160_i.BLIF N_87.BLIF cpu_est_ns_0_2__n.BLIF \ +N_94.BLIF state_machine_un10_bgack_030_int_0_n.BLIF N_95.BLIF \ +state_machine_ds_000_dma_3_0_n.BLIF N_96.BLIF \ +state_machine_size_dma_4_0_0__n.BLIF N_100.BLIF \ +state_machine_size_dma_4_0_1__n.BLIF N_101.BLIF CLK_030_H_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_030_H_1_sqmuxa_i.BLIF N_85.BLIF \ +state_machine_clk_030_h_2_f1_0_n.BLIF DSACK1_INT_0_sqmuxa.BLIF \ +un3_dtack_i.BLIF AS_030_000_SYNC_0_sqmuxa.BLIF \ +state_machine_un5_bgack_030_int_d_i_n.BLIF un1_bgack_030_int_d.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ +state_machine_un3_bgack_030_int_d_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF state_machine_rw_000_int_3_0_n.BLIF \ +N_84.BLIF N_66_0.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_91_i.BLIF N_93.BLIF \ +N_93_i.BLIF N_66.BLIF state_machine_rw_000_int_3_n.BLIF AS_030_000_SYNC_i.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_84_0.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF N_167_1.BLIF \ +N_87_0.BLIF state_machine_un10_bgack_030_int_n.BLIF N_85_0.BLIF \ +CLK_030_H_1_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF \ +AS_000_DMA_1_sqmuxa.BLIF N_92_i.BLIF DS_000_DMA_1_sqmuxa.BLIF \ +DS_000_DMA_1_sqmuxa_1.BLIF N_100_i.BLIF \ +state_machine_un24_bgack_030_int_n.BLIF N_101_i.BLIF \ +state_machine_clk_030_h_2_n.BLIF sm_amiga_ns_0_6__n.BLIF \ +state_machine_clk_030_h_2_f1_n.BLIF N_95_i.BLIF \ +state_machine_un31_bgack_030_int_n.BLIF N_96_i.BLIF \ +state_machine_ds_000_dma_3_n.BLIF sm_amiga_ns_0_3__n.BLIF cpu_est_ns_2__n.BLIF \ +N_94_i.BLIF N_160.BLIF sm_amiga_ns_0_2__n.BLIF N_159.BLIF \ +sm_amiga_ns_0_0__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BG_030_c_i.BLIF \ +state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un8_bg_030_i_n.BLIF \ +N_163.BLIF state_machine_un10_bg_030_0_n.BLIF N_155.BLIF LDS_000_INT_i.BLIF \ +N_156.BLIF un1_LDS_000_INT_0.BLIF cpu_est_ns_1__n.BLIF UDS_000_INT_i.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF un1_UDS_000_INT_0.BLIF \ +state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un7_ds_030_i_n.BLIF \ +state_machine_un10_clk_000_d0_n.BLIF A0_c_i.BLIF \ +state_machine_un5_clk_000_d0_n.BLIF size_c_i_1__n.BLIF N_161.BLIF \ +un1_bgack_030_int_d_0_1.BLIF state_machine_un10_clk_000_ne_1_n.BLIF \ +N_84_0_1.BLIF N_162.BLIF N_84_0_2.BLIF state_machine_un5_clk_000_d0_2_n.BLIF \ +un3_dtack_i_1.BLIF N_166.BLIF cpu_est_ns_0_1_2__n.BLIF N_167.BLIF N_198_1.BLIF \ +DSACK1_INT_1_sqmuxa.BLIF N_198_2.BLIF state_machine_un6_bgack_000_n.BLIF \ +N_207_1.BLIF DS_000_ENABLE_0_sqmuxa.BLIF N_207_2.BLIF \ +state_machine_un10_clk_000_ne_n.BLIF N_207_3.BLIF N_86.BLIF N_207_4.BLIF \ +state_machine_un6_clk_000_ne_n.BLIF N_207_5.BLIF N_98.BLIF N_207_6.BLIF \ +N_99.BLIF state_machine_un7_ds_030_i_1_n.BLIF N_97.BLIF \ +state_machine_un8_bg_030_1_n.BLIF state_machine_un4_clk_000_ne_n.BLIF \ +state_machine_un8_bg_030_2_n.BLIF un19_fpu_cs_i.BLIF \ +DSACK1_INT_0_sqmuxa_1.BLIF DTACK_i.BLIF AS_030_000_SYNC_0_sqmuxa_1_0.BLIF \ +avec_exp_i.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF CLK_000_NE_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF VPA_D_i.BLIF cpu_est_ns_0_1_1__n.BLIF \ +VMA_INT_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_030_i.BLIF \ +state_machine_un10_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF DSACK1_INT_0_sqmuxa_i.BLIF \ +state_machine_un10_clk_000_d0_3_n.BLIF a_i_16__n.BLIF \ +state_machine_clk_000_n_sync_2_1_0__n.BLIF a_i_18__n.BLIF \ +state_machine_clk_000_n_sync_2_2_0__n.BLIF nEXP_SPACE_i.BLIF \ +state_machine_clk_000_p_sync_3_1_0__n.BLIF RW_i.BLIF N_167_1_0.BLIF \ +CLK_000_D3_i.BLIF un19_fpu_cs_1.BLIF CLK_000_D2_i.BLIF un19_fpu_cs_2.BLIF \ +CLK_000_D0_i.BLIF un19_fpu_cs_3.BLIF cpu_est_i_3__n.BLIF un19_fpu_cs_4.BLIF \ +cpu_est_i_0__n.BLIF un19_fpu_cs_5.BLIF cpu_est_i_1__n.BLIF un19_fpu_cs_6.BLIF \ +state_machine_un10_clk_000_ne_1_i_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF \ +CLK_000_D1_i.BLIF state_machine_un10_clk_000_ne_1_0_n.BLIF \ +state_machine_un5_clk_000_d0_2_i_0_n.BLIF dsack1_int_0_un3_n.BLIF \ +cpu_est_i_2__n.BLIF dsack1_int_0_un1_n.BLIF DS_000_DMA_1_sqmuxa_1_i.BLIF \ +dsack1_int_0_un0_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF \ +bgack_030_int_0_un3_n.BLIF CLK_030_i.BLIF bgack_030_int_0_un1_n.BLIF \ +UDS_000_i.BLIF bgack_030_int_0_un0_n.BLIF LDS_000_i.BLIF \ +cpu_estse_0_un3_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF \ +cpu_estse_0_un1_n.BLIF RW_000_i.BLIF cpu_estse_0_un0_n.BLIF \ +state_machine_un24_bgack_030_int_i_n.BLIF vma_int_0_un3_n.BLIF \ +AS_000_DMA_i.BLIF vma_int_0_un1_n.BLIF BGACK_030_INT_i.BLIF \ +vma_int_0_un0_n.BLIF AS_000_i.BLIF ipl_030_0_0__un3_n.BLIF N_90_i.BLIF \ +ipl_030_0_0__un1_n.BLIF BGACK_030_INT_D_i.BLIF ipl_030_0_0__un0_n.BLIF \ +N_89_i.BLIF ipl_030_0_1__un3_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \ +ipl_030_0_1__un1_n.BLIF sm_amiga_i_7__n.BLIF ipl_030_0_1__un0_n.BLIF \ +CLK_OUT_NE_i.BLIF ipl_030_0_2__un3_n.BLIF sm_amiga_i_0__n.BLIF \ +ipl_030_0_2__un1_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF \ +a_i_30__n.BLIF cpu_estse_2_un3_n.BLIF a_i_31__n.BLIF cpu_estse_2_un1_n.BLIF \ +a_i_28__n.BLIF cpu_estse_2_un0_n.BLIF a_i_29__n.BLIF as_000_dma_0_un3_n.BLIF \ +a_i_26__n.BLIF as_000_dma_0_un1_n.BLIF a_i_27__n.BLIF as_000_dma_0_un0_n.BLIF \ +a_i_24__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un1_n.BLIF \ +RST_i.BLIF ds_000_dma_0_un0_n.BLIF rw_000_dma_0_un3_n.BLIF CLK_OUT_PRE_i.BLIF \ +rw_000_dma_0_un1_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_dma_0_un0_n.BLIF \ +AS_030_c.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un1_n.BLIF AS_000_c.BLIF \ +clk_030_h_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF RW_000_c.BLIF \ +cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF DS_030_c.BLIF \ +rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF UDS_000_c.BLIF \ +rw_000_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF LDS_000_c.BLIF \ +as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF size_c_0__n.BLIF \ +as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF size_c_1__n.BLIF \ +as_030_000_sync_0_un0_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ -cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \ -cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ +cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \ +cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ +SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ +SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D \ +CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D \ +CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D \ +CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D \ +CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D \ +CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \ +SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP CLK_000_N_SYNC_0_.D \ +CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.D \ +CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.D \ +CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.D \ +CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.D \ +CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D \ +CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D \ +CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D \ +CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.D \ +CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.D \ +CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \ inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \ -inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \ -SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \ -inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \ -inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D inst_DSACK1_INT.C \ -inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ -inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ -inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \ -inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D \ -inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +inst_CLK_OUT_PRE_25.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +inst_DS_000_ENABLE.AR inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_RW_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \ +inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_RW_000_DMA.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ +inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C \ +inst_AMIGA_BUS_ENABLE_INTreg.AP inst_CLK_OUT_NEreg.D inst_CLK_OUT_NEreg.C \ +inst_CLK_OUT_NEreg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ +inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D \ +inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \ +inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR \ +inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \ +inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C \ +inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_000_NE.AR \ inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \ -DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n \ -a_c_30__n a_c_31__n A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n \ -gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \ -ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n \ -AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n \ -state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n N_159_i N_158_i N_149_i \ -N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n \ -N_160_i N_92 N_154_i state_machine_un49_clk_000_d0_n \ -state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i \ -CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ -state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ -state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ -FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ -state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ -state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \ -N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ -state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n \ -N_164_1 state_machine_un3_bgack_030_int_d_i_n \ -state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 \ -UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 \ -N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 \ -N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n \ -N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n \ -sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ -un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ -state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ -state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ -AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ -state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ -state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 \ -un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i \ -un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ -un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ -state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ -state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ -state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ -state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ -AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ -state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ -CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ -un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ -state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ -cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ -cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \ -N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \ -cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 \ -AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \ -UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \ -cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n \ -RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 \ -VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ -AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ -state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ -a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ -a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ -state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ -sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ -state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ -sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ -state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ -state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ -state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ -cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ -state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ -state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ -cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ -UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ -cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ -state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i \ -ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n \ -AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n \ -ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n \ -a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \ -bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n \ -as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ -FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c \ -fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n \ -as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c \ -dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \ -LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n \ -bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n \ -lds_000_int_0_un3_n lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n \ -uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n \ -a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n rw_000_int_0_un0_n \ -as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n \ -ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \ -clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n \ -a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \ +DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ amiga_bus_enable_int_0_un3_n \ +a_c_16__n amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_17__n \ +bg_000_0_un3_n bg_000_0_un1_n a_c_18__n bg_000_0_un0_n lds_000_int_0_un3_n \ +vcc_n_n a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n \ +ds_000_enable_0_un3_n ds_000_enable_0_un1_n a_c_21__n ds_000_enable_0_un0_n \ +uds_000_int_0_un3_n a_c_22__n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n gnd_n_n a_c_28__n a_c_29__n \ +a_c_30__n a_c_31__n A0_c nEXP_SPACE_c state_machine_un3_clk_out_pre_50_n \ +BG_030_c un1_LDS_000_INT BGACK_000_c un1_UDS_000_INT CLK_030_c CLK_000_c \ +CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c DTACK_c \ +un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \ +RST_c RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i \ +DS_000_ENABLE_0_sqmuxa_i un1_SM_AMIGA_0_sqmuxa_1_i \ +state_machine_un10_clk_000_ne_i_n state_machine_un4_clk_000_ne_i_n \ +state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i \ +sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n \ +state_machine_un6_bgack_000_0_n N_167_i N_166_i AMIGA_BUS_DATA_DIR_c_0 N_162_i \ +N_161_i N_152_i state_machine_un10_clk_000_d0_i_n \ +state_machine_un5_clk_000_d0_i_n state_machine_un12_clk_000_d0_0_n N_198 \ +cpu_est_ns_0_1__n N_207 N_156_i SM_AMIGA_0_sqmuxa N_155_i N_89 N_163_i N_90 \ +state_machine_un5_clk_000_d0_1_i_n state_machine_un8_bg_030_n \ +state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 N_160_i N_87 \ +cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 \ +state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 \ +state_machine_size_dma_4_0_1__n N_101 CLK_030_H_i \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_030_H_1_sqmuxa_i N_85 \ +state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa un3_dtack_i \ +AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n \ +un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ +state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 N_93_i N_66 \ +state_machine_rw_000_int_3_n AS_030_000_SYNC_i \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa_i AS_030_000_SYNC_0_sqmuxa_1 \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \ +state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n \ +un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \ +CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa \ +N_92_i DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i \ +state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \ +sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i \ +state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n \ +sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 \ +sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i \ +state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 \ +state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 \ +cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n \ +un1_UDS_000_INT_0 state_machine_un6_clk_000_p_sync_n \ +state_machine_un7_ds_030_i_n state_machine_un10_clk_000_d0_n A0_c_i \ +state_machine_un5_clk_000_d0_n size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 \ +state_machine_un10_clk_000_ne_1_n N_84_0_1 N_162 N_84_0_2 \ +state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 cpu_est_ns_0_1_2__n N_167 \ +N_198_1 DSACK1_INT_1_sqmuxa N_198_2 state_machine_un6_bgack_000_n N_207_1 \ +DS_000_ENABLE_0_sqmuxa N_207_2 state_machine_un10_clk_000_ne_n N_207_3 N_86 \ +N_207_4 state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \ +state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n \ +state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i \ +DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \ +AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 \ +VPA_D_i cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i \ +state_machine_un10_clk_000_d0_1_n a_i_19__n \ +state_machine_un10_clk_000_d0_2_0_n DSACK1_INT_0_sqmuxa_i \ +state_machine_un10_clk_000_d0_3_n a_i_16__n \ +state_machine_clk_000_n_sync_2_1_0__n a_i_18__n \ +state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i \ +state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i \ +un19_fpu_cs_1 CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 \ +cpu_est_i_3__n un19_fpu_cs_4 cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n \ +un19_fpu_cs_6 state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 \ +CLK_000_D1_i state_machine_un10_clk_000_ne_1_0_n \ +state_machine_un5_clk_000_d0_2_i_0_n dsack1_int_0_un3_n cpu_est_i_2__n \ +dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i dsack1_int_0_un0_n \ +state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n CLK_030_i \ +bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \ +cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n \ +RW_000_i cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n \ +vma_int_0_un3_n AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n \ +AS_000_i ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i \ +ipl_030_0_0__un0_n N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i \ +ipl_030_0_1__un1_n sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i \ +ipl_030_0_2__un3_n sm_amiga_i_0__n ipl_030_0_2__un1_n sm_amiga_i_1__n \ +ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n a_i_31__n cpu_estse_2_un1_n \ +a_i_28__n cpu_estse_2_un0_n a_i_29__n as_000_dma_0_un3_n a_i_26__n \ +as_000_dma_0_un1_n a_i_27__n as_000_dma_0_un0_n a_i_24__n ds_000_dma_0_un3_n \ +a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n rw_000_dma_0_un3_n \ +CLK_OUT_PRE_i rw_000_dma_0_un1_n CLK_OUT_PRE_50_D_i rw_000_dma_0_un0_n \ +AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c clk_030_h_0_un0_n \ +cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n DS_030_c \ +rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n \ +as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n \ +as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n \ +as_030_000_sync_0_un0_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \ LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE \ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D @@ -398,6 +430,26 @@ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D +0 1 +.names N_91_i.BLIF N_93_i.BLIF SM_AMIGA_6_.D +11 1 +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names sm_amiga_ns_0_3__n.BLIF SM_AMIGA_4_.D +0 1 +.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D +0 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF N_92_i.BLIF SM_AMIGA_0_.D +11 1 +.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D +0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -407,21 +459,11 @@ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D -0 1 -.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D +.names state_machine_clk_000_n_sync_2_1_0__n.BLIF \ +state_machine_clk_000_n_sync_2_2_0__n.BLIF CLK_000_N_SYNC_0_.D 11 1 -.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D -11 1 -.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D -11 1 -.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D -0 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D -11 1 -.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D +.names state_machine_clk_000_p_sync_3_1_0__n.BLIF \ +state_machine_un6_clk_000_p_sync_n.BLIF CLK_000_P_SYNC_0_.D 11 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 @@ -430,716 +472,61 @@ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D -0 1 -.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D -0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D -1- 1 --1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D 1- 1 -1 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D 1- 1 -1 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D +1- 1 +-1 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +1- 1 +-1 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF \ +inst_DS_000_ENABLE.D +1- 1 +-1 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D +1- 1 +-1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D +1- 1 +-1 1 +.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +11 1 +.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D +1- 1 +-1 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF inst_RW_000_DMA.D +1- 1 +-1 1 .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D 1- 1 -1 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D 1- 1 -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +.names amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF \ +inst_AMIGA_BUS_ENABLE_INTreg.D 1- 1 -1 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D -1- 1 --1 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D -1- 1 --1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D -1- 1 --1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D -1- 1 --1 1 -.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_i.BLIF inst_CLK_OUT_NEreg.D 11 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names vcc_n_n - 1 -.names gnd_n_n -.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \ -state_machine_un3_clk_out_pre_50_n -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n -0 1 -.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF \ -state_machine_un6_bgack_000_0_n -11 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names N_159.BLIF N_159_i -0 1 -.names N_158.BLIF N_158_i -0 1 -.names N_158_i.BLIF N_159_i.BLIF N_149_i -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i -11 1 -.names N_153.BLIF N_153_i -0 1 -.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -AS_000_DMA_0_sqmuxa -11 1 -.names N_152.BLIF N_152_i -0 1 -.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \ -state_machine_un8_bgack_030_int_n -11 1 -.names N_160.BLIF N_160_i -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92 -11 1 -.names N_154.BLIF N_154_i -0 1 -.names state_machine_un49_clk_000_d0_1_n.BLIF \ -state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n -11 1 -.names state_machine_un10_clk_000_d0_2_n.BLIF \ -state_machine_un10_clk_000_d0_2_i_n -0 1 -.names N_210_1.BLIF N_210_2.BLIF N_210 -11 1 -.names N_156.BLIF N_156_i -0 1 -.names N_220_5.BLIF N_220_6.BLIF N_220 -11 1 -.names N_157.BLIF N_157_i -0 1 -.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa -11 1 -.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ -cpu_est_ns_0_2__n -11 1 -.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -AS_000_DMA_1_sqmuxa -11 1 -.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n -0 1 -.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ -DS_000_DMA_1_sqmuxa -11 1 -.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ -state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n -11 1 -.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n -11 1 -.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i -0 1 -.names state_machine_clk_030_h_2_f1_n.BLIF \ -state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n -11 1 -.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF \ -un1_as_030_000_sync8_1_0 -11 1 -.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n -0 1 -.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i -0 1 -.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n -0 1 -.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF \ -un1_as_030_000_sync8_0 -11 1 -.names N_87_0.BLIF N_87 -0 1 -.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0 -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93 -11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n -11 1 -.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94 -11 1 -.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n -0 1 -.names N_84.BLIF SM_AMIGA_7_.BLIF N_88 -11 1 -.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n -0 1 -.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90 -11 1 -.names state_machine_un51_clk_000_d0_i_n.BLIF \ -state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1 -11 1 -.names state_machine_un3_bgack_030_int_d_n.BLIF \ -state_machine_un3_bgack_030_int_d_i_n -0 1 -.names state_machine_un10_bgack_030_int_0_n.BLIF \ -state_machine_un10_bgack_030_int_n -0 1 -.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ -un1_bgack_030_int_d_0 -11 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -UDS_000_INT_0_sqmuxa_1 -11 1 -.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i -0 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ -UDS_000_INT_0_sqmuxa -11 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i -0 1 -.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0 -11 1 -.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164 -11 1 -.names N_101.BLIF N_101_i -0 1 -.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m -11 1 -.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181 -11 1 -.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0 -11 1 -.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m -11 1 -.names N_97.BLIF N_97_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163 -11 1 -.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8 -0 1 -.names N_96.BLIF N_96_i -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100 -11 1 -.names N_95.BLIF N_95_i -0 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91 -11 1 -.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n -11 1 -.names N_88.BLIF N_88_i -0 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names N_89.BLIF N_89_i -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 -.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1 -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i -0 1 -.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2 -11 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i -0 1 -.names N_59_0.BLIF N_59 -0 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 -11 1 -.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa -0 1 -.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \ -state_machine_un10_bg_030_0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \ -state_machine_un3_bgack_030_int_d_n -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -state_machine_un5_bgack_030_int_d_i_n -11 1 -.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ -AMIGA_BUS_ENABLE_INT_3_sqmuxa -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0 -11 1 -.names N_86_0.BLIF N_86 -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 -11 1 -.names N_181.BLIF N_181_i -0 1 -.names N_84_0.BLIF N_84 -0 1 -.names A0_c.BLIF A0_c_i -0 1 -.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 -11 1 -.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n -11 1 -.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ -state_machine_un8_bg_030_n -11 1 -.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF \ -state_machine_lds_000_int_7_0_n -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89 -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 -11 1 -.names N_91.BLIF N_91_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97 -11 1 -.names N_100.BLIF N_100_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99 -11 1 -.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0 -11 1 -.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF \ -state_machine_un28_clk_000_d1_n -11 1 -.names N_164.BLIF N_164_i -0 1 -.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101 -11 1 -.names N_163.BLIF N_163_i -0 1 -.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12 -0 1 -.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa -11 1 -.names RW_000_i_m.BLIF RW_000_i_m_i -0 1 -.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1 -0 1 -.names RW_li_m.BLIF RW_li_m_i -0 1 -.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa -11 1 -.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n -11 1 -.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \ -state_machine_un10_clk_000_d0_n -11 1 -.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un25_clk_000_d0_i_n -11 1 -.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n -0 1 -.names N_90.BLIF N_90_i -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n -11 1 -.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF \ -state_machine_un57_clk_000_d0_n -11 1 -.names N_93.BLIF N_93_i -0 1 -.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2 -11 1 -.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n -11 1 -.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF \ -AS_030_000_SYNC_0_sqmuxa -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0 -11 1 -.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n -0 1 -.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_ds_000_dma_3_0_n -11 1 -.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa -11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF \ -state_machine_un28_clk_030_n -11 1 -.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i -0 1 -.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8 -0 1 -.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \ -state_machine_clk_030_h_2_f1_0_n -11 1 -.names N_150_i.BLIF N_150 -0 1 -.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i -11 1 -.names state_machine_un5_clk_000_d0_1_n.BLIF \ -state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n -11 1 -.names N_92.BLIF N_92_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n -11 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157 -11 1 -.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n -11 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156 -11 1 -.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152 -11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2 -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3 -11 1 -.names N_150.BLIF cpu_est_2_.BLIF N_158 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4 -11 1 -.names N_160.BLIF cpu_est_i_3__n.BLIF N_159 -11 1 -.names N_220_1.BLIF N_220_2.BLIF N_220_5 -11 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n -0 1 -.names N_220_3.BLIF N_220_4.BLIF N_220_6 -11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -DS_000_DMA_1_sqmuxa_1 -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_164_1.BLIF RW_c.BLIF N_164_1_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 -11 1 -.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names state_machine_un3_bgack_030_int_d_i_n.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n -11 1 -.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \ -state_machine_un49_clk_000_d0_1_n -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1 -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2_0 -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n -11 1 -.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n -0 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF \ -state_machine_un28_clk_030_4_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF \ -state_machine_un28_clk_030_5_n -11 1 -.names N_99.BLIF N_99_i -0 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \ -state_machine_un10_clk_000_d0_1_n -11 1 -.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i -0 1 -.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \ -state_machine_un10_clk_000_d0_2_0_n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names state_machine_un10_clk_000_d0_1_n.BLIF \ -state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n -11 1 -.names UDS_000_c.BLIF UDS_000_i -0 1 -.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i -0 1 -.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF \ -state_machine_un28_clk_000_d1_1_n -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_un8_bgack_030_int_i_n -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n -0 1 -.names state_machine_un31_bgack_030_int_n.BLIF \ -state_machine_un31_bgack_030_int_i_n -0 1 -.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ -cpu_estse_1_un1_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ -cpu_estse_0_un1_n -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n -11 1 -.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n -11 1 -.names state_machine_un24_bgack_030_int_n.BLIF \ -state_machine_un24_bgack_030_int_i_n -0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ -bgack_030_int_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n -0 1 -.names RST_c.BLIF RST_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ -as_030_000_sync_0_un1_n -11 1 -.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n -0 1 -.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i -0 1 -.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n -11 1 -.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n -11 1 -.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n -0 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n -11 1 -.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ -state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un3_n 0 1 -.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ -avec_exp_0_un1_n +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un1_n 11 1 -.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n +.names un1_bgack_030_int_d.BLIF amiga_bus_enable_int_0_un3_n.BLIF \ +amiga_bus_enable_int_0_un0_n 11 1 .names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n 0 1 @@ -1147,54 +534,690 @@ avec_exp_0_un1_n 11 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names un1_AS_030_2.BLIF lds_000_int_0_un3_n +.names DS_030_c.BLIF lds_000_int_0_un3_n 0 1 -.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n +.names vcc_n_n + 1 +.names inst_LDS_000_INT.BLIF DS_030_c.BLIF lds_000_int_0_un1_n 11 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \ +.names state_machine_un7_ds_030_i_n.BLIF lds_000_int_0_un3_n.BLIF \ lds_000_int_0_un0_n 11 1 -.names un1_AS_030_2.BLIF uds_000_int_0_un3_n +.names un1_as_030.BLIF ds_000_enable_0_un3_n 0 1 -.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n +.names inst_DS_000_ENABLE.BLIF un1_as_030.BLIF ds_000_enable_0_un1_n 11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n 11 1 -.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +.names DS_030_c.BLIF uds_000_int_0_un3_n 0 1 -.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +.names inst_UDS_000_INT.BLIF DS_030_c.BLIF uds_000_int_0_un1_n 11 1 -.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF \ -rw_000_int_0_un0_n +.names A0_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 +.names gnd_n_n +.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \ +state_machine_un3_clk_out_pre_50_n +11 1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT +0 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names AS_030_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_as_030 +11 1 +.names un19_fpu_cs_5.BLIF un19_fpu_cs_6.BLIF un19_fpu_cs +11 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names SM_AMIGA_0_sqmuxa.BLIF SM_AMIGA_0_sqmuxa_i +0 1 +.names DS_000_ENABLE_0_sqmuxa.BLIF DS_000_ENABLE_0_sqmuxa_i +0 1 +.names DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1_i +11 1 +.names state_machine_un10_clk_000_ne_n.BLIF state_machine_un10_clk_000_ne_i_n +0 1 +.names state_machine_un4_clk_000_ne_n.BLIF state_machine_un4_clk_000_ne_i_n +0 1 +.names state_machine_un4_clk_000_ne_i_n.BLIF \ +state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_i_n +11 1 +.names N_97.BLIF N_97_i +0 1 +.names N_97_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF sm_amiga_ns_0_4__n +11 1 +.names N_99.BLIF N_99_i +0 1 +.names N_98.BLIF N_98_i +0 1 +.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names inst_CLK_000_NE.BLIF state_machine_un6_clk_000_ne_n.BLIF N_86_i +11 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF \ +state_machine_un6_clk_000_p_sync_i_n +0 1 +.names BGACK_000_c.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF \ +state_machine_un6_bgack_000_0_n +11 1 +.names N_167.BLIF N_167_i +0 1 +.names N_166.BLIF N_166_i +0 1 +.names N_166_i.BLIF N_167_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_162.BLIF N_162_i +0 1 +.names N_161.BLIF N_161_i +0 1 +.names N_161_i.BLIF N_162_i.BLIF N_152_i +11 1 +.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n +0 1 +.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_n +0 1 +.names state_machine_un5_clk_000_d0_i_n.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n +11 1 +.names N_198_1.BLIF N_198_2.BLIF N_198 +11 1 +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n +11 1 +.names N_207_5.BLIF N_207_6.BLIF N_207 +11 1 +.names N_156.BLIF N_156_i +0 1 +.names SM_AMIGA_4_.BLIF inst_avec_expreg.BLIF SM_AMIGA_0_sqmuxa +11 1 +.names N_155.BLIF N_155_i +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_89 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names SM_AMIGA_6_.BLIF inst_avec_expreg.BLIF N_90 +11 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF \ +state_machine_un5_clk_000_d0_1_i_n +0 1 +.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ +state_machine_un8_bg_030_n +11 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF \ +state_machine_un10_clk_000_d0_2_i_n +0 1 +.names N_84.BLIF SM_AMIGA_7_.BLIF N_91 +11 1 +.names N_159.BLIF N_159_i +0 1 +.names SM_AMIGA_0_.BLIF inst_avec_expreg.BLIF N_92 +11 1 +.names N_160.BLIF N_160_i +0 1 +.names N_87_0.BLIF N_87 +0 1 +.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +cpu_est_ns_0_2__n +11 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_94 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n +11 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_5_.BLIF N_95 +11 1 +.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_ds_000_dma_3_0_n +11 1 +.names SM_AMIGA_4_.BLIF avec_exp_i.BLIF N_96 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n +11 1 +.names SM_AMIGA_2_.BLIF inst_avec_expreg.BLIF N_100 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n +11 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_101 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_85.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +11 1 +.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i +0 1 +.names N_85_0.BLIF N_85 +0 1 +.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \ +state_machine_clk_030_h_2_f1_0_n +11 1 +.names DSACK1_INT_0_sqmuxa_1.BLIF SM_AMIGA_1_.BLIF DSACK1_INT_0_sqmuxa +11 1 +.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1_0.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF \ +AS_030_000_SYNC_0_sqmuxa +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +state_machine_un5_bgack_030_int_d_i_n +11 1 +.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d +0 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \ +state_machine_un3_bgack_030_int_d_n +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i +0 1 +.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 +11 1 +.names N_89_i.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa +11 1 +.names RW_i.BLIF sm_amiga_i_7__n.BLIF state_machine_rw_000_int_3_0_n +11 1 +.names N_84_0.BLIF N_84 +0 1 +.names N_90_i.BLIF sm_amiga_i_7__n.BLIF N_66_0 +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF \ +state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa +11 1 +.names N_91.BLIF N_91_i +0 1 +.names N_87.BLIF sm_amiga_i_7__n.BLIF N_93 +11 1 +.names N_93.BLIF N_93_i +0 1 +.names N_66_0.BLIF N_66 +0 1 +.names state_machine_rw_000_int_3_0_n.BLIF state_machine_rw_000_int_3_n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa +0 1 +.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0 +11 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 +11 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i +0 1 +.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1 +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i +0 1 +.names AS_030_i.BLIF N_90_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names state_machine_un3_bgack_030_int_d_n.BLIF \ +state_machine_un3_bgack_030_int_d_i_n +0 1 +.names N_167_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_n +11 1 +.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +un1_bgack_030_int_d_0 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_167_1 +11 1 +.names SM_AMIGA_6_.BLIF avec_exp_i.BLIF N_87_0 +11 1 +.names state_machine_un10_bgack_030_int_0_n.BLIF \ +state_machine_un10_bgack_030_int_n +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_85_0 +11 1 +.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i +0 1 +.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +AS_000_DMA_1_sqmuxa +11 1 +.names N_92.BLIF N_92_i +0 1 +.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ +DS_000_DMA_1_sqmuxa +11 1 +.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +DS_000_DMA_1_sqmuxa_1 +11 1 +.names N_100.BLIF N_100_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n +11 1 +.names N_101.BLIF N_101_i +0 1 +.names state_machine_clk_030_h_2_f1_n.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n +11 1 +.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_6__n +11 1 +.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n +0 1 +.names N_95.BLIF N_95_i +0 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n +11 1 +.names N_96.BLIF N_96_i +0 1 +.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n +0 1 +.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_3__n +11 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_160 +11 1 +.names N_90_i.BLIF N_94_i.BLIF sm_amiga_ns_0_2__n +11 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_159 +11 1 +.names N_91_i.BLIF N_92_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_1_n +11 1 +.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_163 +11 1 +.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \ +state_machine_un10_bg_030_0_n +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_155 +11 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_156 +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +11 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n +0 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF \ +state_machine_un6_clk_000_p_sync_n +11 1 +.names state_machine_un7_ds_030_i_1_n.BLIF size_c_0__n.BLIF \ +state_machine_un7_ds_030_i_n +11 1 +.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un10_clk_000_d0_n +11 1 +.names A0_c.BLIF A0_c_i +0 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF \ +state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names cpu_est_2_.BLIF state_machine_un10_clk_000_ne_1_i_n.BLIF N_161 +11 1 +.names state_machine_un3_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF \ +state_machine_un10_clk_000_ne_1_n +11 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_D1_i.BLIF N_84_0_1 +11 1 +.names N_163.BLIF cpu_est_i_3__n.BLIF N_162 +11 1 +.names inst_CLK_000_D2.BLIF nEXP_SPACE_c.BLIF N_84_0_2 +11 1 +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_2_n +11 1 +.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_166 +11 1 +.names N_160_i.BLIF N_159_i.BLIF cpu_est_ns_0_1_2__n +11 1 +.names N_167_1_0.BLIF nEXP_SPACE_i.BLIF N_167 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_198_1 +11 1 +.names AS_030_i.BLIF DSACK1_INT_0_sqmuxa_i.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_198_2 +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_207_1 +11 1 +.names DS_000_ENABLE_0_sqmuxa_1.BLIF inst_avec_expreg.BLIF \ +DS_000_ENABLE_0_sqmuxa +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_207_2 +11 1 +.names state_machine_un10_clk_000_ne_1_0_n.BLIF VPA_D_i.BLIF \ +state_machine_un10_clk_000_ne_n +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_207_3 +11 1 +.names N_86_i.BLIF N_86 +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_207_4 +11 1 +.names state_machine_un6_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_n +0 1 +.names N_207_1.BLIF N_207_2.BLIF N_207_5 +11 1 +.names SM_AMIGA_2_.BLIF avec_exp_i.BLIF N_98 +11 1 +.names N_207_3.BLIF N_207_4.BLIF N_207_6 +11 1 +.names N_86_i.BLIF SM_AMIGA_3_.BLIF N_99 +11 1 +.names size_c_i_1__n.BLIF A0_c_i.BLIF state_machine_un7_ds_030_i_1_n +11 1 +.names N_86.BLIF SM_AMIGA_3_.BLIF N_97 +11 1 +.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n +11 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF state_machine_un4_clk_000_ne_n +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n +11 1 +.names un19_fpu_cs.BLIF un19_fpu_cs_i +0 1 +.names inst_CLK_000_D1.BLIF CLK_OUT_NE_i.BLIF DSACK1_INT_0_sqmuxa_1 +11 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1_0 +11 1 +.names inst_avec_expreg.BLIF avec_exp_i +0 1 +.names nEXP_SPACE_c.BLIF un19_fpu_cs_i.BLIF AS_030_000_SYNC_0_sqmuxa_2 +11 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_155_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_1__n +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_163_i.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF \ +cpu_est_ns_0_2_1__n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \ +state_machine_un10_clk_000_d0_1_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n +11 1 +.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i +0 1 +.names state_machine_un10_clk_000_d0_1_n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \ +state_machine_clk_000_n_sync_2_1_0__n +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF \ +state_machine_clk_000_n_sync_2_2_0__n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names CLK_000_D2_i.BLIF CLK_000_D3_i.BLIF \ +state_machine_clk_000_p_sync_3_1_0__n +11 1 +.names RW_c.BLIF RW_i +0 1 +.names N_167_1.BLIF RW_c.BLIF N_167_1_0 +11 1 +.names inst_CLK_000_D3.BLIF CLK_000_D3_i +0 1 +.names AS_030_i.BLIF a_c_17__n.BLIF un19_fpu_cs_1 +11 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names a_i_16__n.BLIF a_i_18__n.BLIF un19_fpu_cs_2 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names a_i_19__n.BLIF BGACK_000_c.BLIF un19_fpu_cs_3 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF un19_fpu_cs_4 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names un19_fpu_cs_1.BLIF un19_fpu_cs_2.BLIF un19_fpu_cs_5 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names un19_fpu_cs_3.BLIF un19_fpu_cs_4.BLIF un19_fpu_cs_6 +11 1 +.names state_machine_un10_clk_000_ne_1_n.BLIF \ +state_machine_un10_clk_000_ne_1_i_n +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa_1 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names state_machine_un10_clk_000_ne_1_n.BLIF VMA_INT_i.BLIF \ +state_machine_un10_clk_000_ne_1_0_n +11 1 +.names state_machine_un5_clk_000_d0_2_n.BLIF \ +state_machine_un5_clk_000_d0_2_i_0_n +0 1 +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +11 1 +.names DS_000_DMA_1_sqmuxa_1.BLIF DS_000_DMA_1_sqmuxa_1_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_i_n +0 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ +bgack_030_int_0_un1_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names inst_avec_expreg.BLIF cpu_estse_0_un3_n +0 1 +.names state_machine_un31_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n +0 1 +.names cpu_est_ns_1__n.BLIF inst_avec_expreg.BLIF cpu_estse_0_un1_n +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names state_machine_un24_bgack_030_int_n.BLIF \ +state_machine_un24_bgack_030_int_i_n +0 1 +.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names state_machine_un5_clk_000_d0_2_i_0_n.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_90.BLIF N_90_i +0 1 +.names ipl_c_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \ +ipl_030_0_0__un1_n +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_89.BLIF N_89_i +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un3_n +0 1 +.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i +0 1 +.names ipl_c_1__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \ +ipl_030_0_1__un1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names inst_CLK_OUT_NEreg.BLIF CLK_OUT_NE_i +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un3_n +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names ipl_c_2__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \ +ipl_030_0_2__un1_n +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names inst_avec_expreg.BLIF cpu_estse_2_un3_n +0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names N_152_i.BLIF inst_avec_expreg.BLIF cpu_estse_2_un1_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 .names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n 0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \ as_000_dma_0_un0_n 11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 .names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n 0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 .names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 +.names RST_c.BLIF RST_i +0 1 .names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \ ds_000_dma_0_un0_n 11 1 +.names AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i +0 1 +.names inst_RW_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un1_n +11 1 +.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i +0 1 +.names DS_000_DMA_1_sqmuxa_1_i.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 .names RST_c.BLIF clk_030_h_0_un3_n 0 1 .names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n 11 1 .names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n 11 1 +.names inst_avec_expreg.BLIF cpu_estse_1_un3_n +0 1 +.names cpu_est_ns_2__n.BLIF inst_avec_expreg.BLIF cpu_estse_1_un1_n +11 1 +.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names N_66.BLIF rw_000_int_0_un3_n +0 1 +.names state_machine_rw_000_int_3_n.BLIF N_66.BLIF rw_000_int_0_un1_n +11 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names N_90_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un3_n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF \ +as_030_000_sync_0_un1_n +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 .names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ CLK_OUT_PRE_25_0 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse +.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_estse 01 1 10 1 11 0 @@ -1217,7 +1240,7 @@ CLK_OUT_PRE_25_0 .names CLK_OUT_INTreg.BLIF CLK_EXP 1 1 0 0 -.names inst_FPU_CS_INTreg.BLIF FPU_CS +.names un19_fpu_cs_i.BLIF FPU_CS 1 1 0 0 .names vcc_n_n.BLIF AVEC @@ -1235,16 +1258,16 @@ CLK_OUT_PRE_25_0 .names RESETDFFRHreg.BLIF RESET 1 1 0 0 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE 1 1 0 0 .names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR 1 1 0 0 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +.names inst_CLK_OUT_NEreg.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_210.BLIF CIIN +.names N_198.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1253,6 +1276,15 @@ CLK_OUT_PRE_25_0 .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names cpu_estse.BLIF cpu_est_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 @@ -1271,33 +1303,6 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF cpu_est_3_reg.AR 1 1 0 0 -.names cpu_estse.BLIF cpu_est_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 0 0 @@ -1346,6 +1351,228 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_2_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_3_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_4_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_5_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_6_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_7_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_8_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_9_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_0_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_1_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_2_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_3_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_4_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_5_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_6_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_7_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_8_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_9_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_10_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_11_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_0_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_1_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 @@ -1367,16 +1594,16 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_CLK_OUT_PRE_25.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names RST_i.BLIF SIZE_DMA_0_.AP +.names RST_i.BLIF inst_AS_030_000_SYNC.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C 1 1 0 0 -.names RST_i.BLIF SIZE_DMA_1_.AP +.names RST_i.BLIF BG_000DFFSHreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INT.C @@ -1385,22 +1612,49 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_LDS_000_INT.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP +.names RST_i.BLIF inst_AS_000_INT.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_avec_expreg.C +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names RST_i.BLIF inst_avec_expreg.AP +.names RST_i.BLIF inst_DS_000_ENABLE.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C 1 1 0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_UDS_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_RW_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_A0_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_RW_000_DMA.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C @@ -1415,52 +1669,16 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_AS_000_DMA.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C 1 1 0 0 -.names RST_i.BLIF inst_AS_000_INT.AP +.names RST_i.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +.names CLK_OSZI_c.BLIF inst_CLK_OUT_NEreg.C 1 1 0 0 -.names RST_i.BLIF inst_DSACK1_INT.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names RST_i.BLIF inst_RW_000_INT.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -0 0 -.names RST_i.BLIF inst_UDS_000_INT.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -0 0 -.names RST_i.BLIF inst_A0_DMA.AP -1 1 -0 0 -.names DTACK.PIN.BLIF inst_DTACK_D0.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_D0.AP +.names RST_i.BLIF inst_CLK_OUT_NEreg.AR 1 1 0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D @@ -1472,7 +1690,25 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_CLK_000_D2.AP 1 1 0 0 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D +.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR +1 1 +0 0 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_000_D3.AP +1 1 +0 0 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C @@ -1508,6 +1744,15 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR 1 1 0 0 +.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_OUT_PRE_D.AR +1 1 +0 0 .names CLK_000_c.BLIF inst_CLK_000_D0.D 1 1 0 0 @@ -1526,6 +1771,24 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_VPA_D.AP 1 1 0 0 +.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_avec_expreg.C +1 1 +0 0 +.names RST_i.BLIF inst_avec_expreg.AR +1 1 +0 0 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_000_NE.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 0 0 @@ -1556,10 +1819,10 @@ CLK_OUT_PRE_25_0 .names inst_DS_000_DMA.BLIF DS_030 1 1 0 0 -.names inst_UDS_000_INT.BLIF UDS_000 +.names un1_UDS_000_INT.BLIF UDS_000 1 1 0 0 -.names inst_LDS_000_INT.BLIF LDS_000 +.names un1_LDS_000_INT.BLIF LDS_000 1 1 0 0 .names inst_A0_DMA.BLIF A0 @@ -1571,12 +1834,48 @@ CLK_OUT_PRE_25_0 .names DSACK1_c.BLIF DTACK 1 1 0 0 -.names inst_RW_000_INT.BLIF RW +.names inst_RW_000_DMA.BLIF RW 1 1 0 0 .names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 +.names A_16_.BLIF a_c_16__n +1 1 +0 0 +.names A_17_.BLIF a_c_17__n +1 1 +0 0 +.names A_18_.BLIF a_c_18__n +1 1 +0 0 +.names A_19_.BLIF a_c_19__n +1 1 +0 0 +.names A_20_.BLIF a_c_20__n +1 1 +0 0 +.names A_21_.BLIF a_c_21__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 +.names A_24_.BLIF a_c_24__n +1 1 +0 0 +.names A_25_.BLIF a_c_25__n +1 1 +0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 .names A_28_.BLIF a_c_28__n 1 1 0 0 @@ -1622,6 +1921,9 @@ CLK_OUT_PRE_25_0 .names DSACK1.PIN.BLIF DSACK1_c 1 1 0 0 +.names DTACK.PIN.BLIF DTACK_c +1 1 +0 0 .names RST.BLIF RST_c 1 1 0 0 @@ -1658,42 +1960,6 @@ CLK_OUT_PRE_25_0 .names SIZE_1_.PIN.BLIF size_c_1__n 1 1 0 0 -.names A_16_.BLIF a_c_16__n -1 1 -0 0 -.names A_17_.BLIF a_c_17__n -1 1 -0 0 -.names A_18_.BLIF a_c_18__n -1 1 -0 0 -.names A_19_.BLIF a_c_19__n -1 1 -0 0 -.names A_20_.BLIF a_c_20__n -1 1 -0 0 -.names A_21_.BLIF a_c_21__n -1 1 -0 0 -.names A_22_.BLIF a_c_22__n -1 1 -0 0 -.names A_23_.BLIF a_c_23__n -1 1 -0 0 -.names A_24_.BLIF a_c_24__n -1 1 -0 0 -.names A_25_.BLIF a_c_25__n -1 1 -0 0 -.names A_26_.BLIF a_c_26__n -1 1 -0 0 -.names A_27_.BLIF a_c_27__n -1 1 -0 0 .names un3_dtack_i.BLIF AS_030.OE 1 1 0 0 @@ -1730,10 +1996,10 @@ CLK_OUT_PRE_25_0 .names BGACK_030_INT_i.BLIF RW.OE 1 1 0 0 -.names FPU_CS_INT_i.BLIF BERR.OE +.names un19_fpu_cs.BLIF BERR.OE 1 1 0 0 -.names N_220.BLIF CIIN.OE +.names N_207.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index cd4a0b2..317f810 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,108 +1,261 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE 68030_tk -#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \ -# IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ -# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \ -# A_25_ A_24_ A_23_ -#$ NODES 43 inst_BGACK_030_INTreg inst_FPU_CS_INTreg inst_avec_expreg \ -# inst_VMA_INTreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA \ -# inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 \ -# inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ inst_AS_000_INT \ -# SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT \ -# inst_LDS_000_INT inst_DSACK1_INT IPL_030DFFSH_0_reg inst_CLK_000_D2 \ -# IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \ -# SIZE_DMA_1_ inst_A0_DMA SM_AMIGA_5_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ \ -# RESETDFFRHreg cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_reg +#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 SIZE_0_ RW_000 A_30_ \ +# DS_030 A_29_ UDS_000 A_28_ LDS_000 A_27_ A0 A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ \ +# BG_000 A_22_ BGACK_030 A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ \ +# CLK_DIV_OUT A_16_ CLK_EXP IPL_030_1_ FPU_CS IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC \ +# FC_0_ AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW CIIN +#$ NODES 71 inst_BGACK_030_INTreg inst_avec_expreg inst_VMA_INTreg \ +# inst_AMIGA_BUS_ENABLE_INTreg inst_CLK_OUT_NEreg inst_AS_030_000_SYNC \ +# inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D inst_CLK_OUT_PRE_50_D \ +# inst_CLK_OUT_PRE inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE_50 \ +# inst_CLK_OUT_PRE_25 inst_CLK_000_D2 inst_CLK_000_D3 inst_CLK_000_NE \ +# inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ CLK_000_N_SYNC_11_ inst_AS_000_INT \ +# SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ inst_RW_000_INT \ +# inst_DSACK1_INT inst_CLK_030_H inst_RW_000_DMA BG_000DFFSHreg inst_LDS_000_INT \ +# inst_DS_000_ENABLE inst_UDS_000_INT inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ \ +# inst_A0_DMA CLK_000_N_SYNC_0_ CLK_OUT_INTreg CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ \ +# CLK_000_N_SYNC_3_ IPL_030DFFSH_0_reg CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ \ +# IPL_030DFFSH_1_reg CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ IPL_030DFFSH_2_reg \ +# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ \ +# CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \ +# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \ +# SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ RESETDFFRHreg cpu_est_0_ cpu_est_1_ cpu_est_2_ \ +# cpu_est_3_reg .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ -inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF \ -BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF \ -inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF \ -inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF \ -inst_RW_000_INT.BLIF CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF \ -inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_CLK_000_D2.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF \ -inst_DS_000_DMA.BLIF IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \ -inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ -SM_AMIGA_2_.BLIF RESETDFFRHreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -cpu_est_2_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ -SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \ -RW.PIN.BLIF +inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF \ +inst_CLK_OUT_NEreg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AS_000_DMA.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ +inst_CLK_OUT_PRE.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF inst_CLK_000_D2.BLIF \ +inst_CLK_000_D3.BLIF inst_CLK_000_NE.BLIF inst_CLK_OUT_PRE_D.BLIF \ +CLK_000_P_SYNC_9_.BLIF CLK_000_N_SYNC_11_.BLIF inst_AS_000_INT.BLIF \ +SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_4_.BLIF inst_RW_000_INT.BLIF inst_DSACK1_INT.BLIF inst_CLK_030_H.BLIF \ +inst_RW_000_DMA.BLIF BG_000DFFSHreg.BLIF inst_LDS_000_INT.BLIF \ +inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF inst_DS_000_DMA.BLIF \ +SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF CLK_000_N_SYNC_0_.BLIF \ +CLK_OUT_INTreg.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF \ +CLK_000_N_SYNC_3_.BLIF IPL_030DFFSH_0_reg.BLIF CLK_000_N_SYNC_4_.BLIF \ +CLK_000_N_SYNC_5_.BLIF IPL_030DFFSH_1_reg.BLIF CLK_000_N_SYNC_6_.BLIF \ +CLK_000_N_SYNC_7_.BLIF IPL_030DFFSH_2_reg.BLIF CLK_000_N_SYNC_8_.BLIF \ +CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF CLK_000_P_SYNC_0_.BLIF \ +CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \ +CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \ +CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF SM_AMIGA_5_.BLIF \ +SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF RESETDFFRHreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF \ +DTACK.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ -cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR \ -cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ +cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \ +cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ +SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ +SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D \ +CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D \ +CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D \ +CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D \ +CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D \ +CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \ +SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.C inst_VMA_INTreg.AP \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP CLK_000_N_SYNC_0_.D \ +CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.D \ +CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.D \ +CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.D \ +CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.D \ +CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D \ +CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D \ +CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D \ +CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.D \ +CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.D \ +CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR inst_VMA_INTreg.C inst_VMA_INTreg.AP \ inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR \ -SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C \ -SIZE_DMA_1_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \ -BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +inst_DS_000_ENABLE.AR inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_RW_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \ +inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_RW_000_DMA.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D \ -inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D \ -inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \ -inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP \ -inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D \ -CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \ -inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C \ -inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \ -inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C \ +inst_AMIGA_BUS_ENABLE_INTreg.AP inst_CLK_OUT_NEreg.D inst_CLK_OUT_NEreg.C \ +inst_CLK_OUT_NEreg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ +inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D \ +inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \ +inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR \ +inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \ +inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C \ +inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_000_NE.AR \ inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \ DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ AS_030.OE AS_000.OE \ RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE \ DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE inst_VMA_INTreg.D.X1 \ -inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_1_.D -1010-- 1 ---01-- 1 -10--00 1 -10--11 1 --1-1-- 1 -0--1-- 1 -101110 0 -101101 0 ---0010 0 ---0001 0 --1-0-- 0 -0--0-- 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D -1000-- 1 ----11- 1 -101--1 1 --1--1- 1 -0---1- 1 ---1-00 0 -1010-0 0 ---010- 0 --1--0- 0 -0---0- 0 +inst_VMA_INTreg.D.X2 +.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_reg.BLIF cpu_est_1_.D +110-- 1 +-01-- 1 +0-1-- 1 +1--00 1 +1--11 1 +11110 0 +11101 0 +-0010 0 +-0001 0 +0-0-- 0 +.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_reg.BLIF cpu_est_2_.D +100-- 1 +--11- 1 +0--1- 1 +11--1 1 +--100 0 +110-0 0 +-010- 0 +0--0- 0 +.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_reg.BLIF cpu_est_3_reg.D +11-0- 1 +1-00- 1 +--0-1 1 +0---1 1 +---01 1 +1-11- 0 +-01-0 0 +0---0 0 +---10 0 +.names nEXP_SPACE.BLIF inst_avec_expreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_7_.D +----01- 1 +---1-1- 1 +--1--1- 1 +0----1- 1 +-1----1 1 +10001-- 0 +1-001-0 0 +-0---0- 0 +-----00 0 +.names nEXP_SPACE.BLIF inst_avec_expreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_6_.D +1-0011- 1 +-0---01 1 +-1---0- 0 +----01- 0 +---1-1- 0 +--1--1- 0 +0----1- 0 +-----00 0 +.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +1-1- 1 +-0-1 1 +-10- 0 +01-- 0 +--00 0 +0--0 0 +.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_4_.D +0-1- 1 +-1-1 1 +-00- 0 +10-- 0 +--00 0 +1--0 0 +.names inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF \ +inst_CLK_000_NE.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF cpu_est_1_.BLIF \ +cpu_est_3_reg.BLIF DTACK.PIN.BLIF SM_AMIGA_3_.D +--0--1-0- 1 +--0--11-- 1 +-10--1--- 1 +1---1---- 1 +---0-1--- 1 +--1--1--1 1 +-0010-01- 0 +0001--01- 0 +--110---0 0 +0-11----0 0 +----00--- 0 +0----0--- 0 +.names inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF \ +inst_CLK_000_NE.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF cpu_est_1_.BLIF \ +cpu_est_3_reg.BLIF DTACK.PIN.BLIF SM_AMIGA_2_.D +-0011-01- 1 +--111---0 1 +0----1--- 1 +--0--0-0- 0 +1-0----0- 0 +--0--01-- 0 +1-0---1-- 0 +-10--0--- 0 +110------ 0 +----00--- 0 +---0-0--- 0 +1---0---- 0 +1--0----- 0 +--1--0--1 0 +1-1-----1 0 +.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_2_.BLIF SM_AMIGA_1_.D +-01- 1 +1--1 1 +0-0- 0 +01-- 0 +--00 0 +-1-0 0 +.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +-110 1 +0--1 1 +1--1 0 +--00 0 +-0-0 0 +.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_DMA_0_.D +--1- 1 +-1-- 1 +1--- 1 +---1 1 +0000 0 +.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_DMA_1_.D +--00 1 +--11 1 +-1-- 1 +1--- 1 +0010 0 +0001 0 .names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D 110- 1 @@ -127,76 +280,20 @@ IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D 010- 0 --10 0 -0-0 0 -.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D2.BLIF \ -SM_AMIGA_7_.D ---1-1-- 1 ----1-1- 1 --1---1- 1 -0----1- 1 ------10 1 -10-00-1 0 -1000--1 0 -----00- 0 ---0--0- 0 -.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D2.BLIF \ -SM_AMIGA_6_.D -10-0-11 1 ---0-10- 1 -----00- 0 ---1--0- 0 ----1-1- 0 --1---1- 0 -0----1- 0 ------10 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -11- 1 -1-1 1 --00 0 -0-- 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D -01- 1 -0-1 1 --00 0 -1-- 0 -.names inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ -cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_3_.D --1--1-1-- 1 --0----11- 1 -10----1-- 1 ---1--1--- 1 ----0--1-- 1 --0----1-0 1 ---1---1-- 1 -0001---01 0 --1010---- 0 ------00-- 0 ---0---0-- 0 -.names inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ -cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_2_.D -0001-1-01 1 --10101--- 1 ---0---1-- 1 --1--1-0-- 0 --0----01- 0 -10----0-- 0 ------00-- 0 ----0--0-- 0 --0----0-0 0 ---1------ 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D -11- 1 -1-1 1 --00 0 -0-- 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D -01- 1 -0-1 1 --00 0 -1-- 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \ +inst_CLK_000_D3.BLIF CLK_000_N_SYNC_0_.D +0111 1 +--0- 0 +-0-- 0 +1--- 0 +---0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \ +inst_CLK_000_D3.BLIF CLK_000_P_SYNC_0_.D +1000 1 +--1- 0 +-1-- 0 +0--- 0 +---1 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D 1-10 1 @@ -204,91 +301,116 @@ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D -00- 0 0--- 0 -0-1 0 -.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF SIZE_DMA_0_.D ---1- 1 --1-- 1 -1--- 1 ----1 1 -0000 0 -.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF SIZE_DMA_1_.D ---00 1 ---11 1 --1-- 1 -1--- 1 -0010 0 -0001 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF inst_LDS_000_INT.BLIF \ -SM_AMIGA_5_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF A0.PIN.BLIF RW.PIN.BLIF inst_LDS_000_INT.D -0-10------ 1 --01------1 1 -0--01----- 1 --0--1----1 1 -0--1-01000 1 -11---01001 1 -1---1----0 1 -1-1------0 1 -0---1----1 1 -0-1------1 1 -----11---- 1 ---1--1---- 1 -0-000----- 0 --00-0----1 0 -0--1-0--10 0 -0--1-0-1-0 0 -0--1-00--0 0 -11---0--11 0 -11---0-1-1 0 -11---00--1 0 ---0-01---- 0 -1-0-0----0 0 -0-0-0----1 0 -.names FC_1_.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ -A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF AS_030.PIN.BLIF \ -inst_FPU_CS_INTreg.D --------01- 1 -------1-1- 1 ------0--1- 1 -----1---1- 1 ----1----1- 1 ---0-----1- 1 --0------1- 1 -0-------1- 1 ----------1 1 -11100101-0 0 ---------00 0 -.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_avec_expreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF \ -inst_CLK_000_D2.BLIF AS_030.PIN.BLIF inst_avec_expreg.D --1-----0010- 1 --1----1001-- 1 --1-1---001-- 1 -01-----001-- 1 --11------0-- 1 --11-----1--- 1 --1---0-1---1 1 --11----1---- 1 --1-----1-1-1 1 --1--0------- 1 --1------1--1 1 -1--01-00011- 0 ---0-11--00-- 0 ---0-1--000-- 0 ---0-1---1--0 0 ---0-1--1---0 0 --0---------- 0 -.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF BG_000DFFSHreg.BLIF \ -SM_AMIGA_7_.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D ----10- 1 ---01-- 1 -0--1-- 1 ----1-0 1 +.names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF A_19_.BLIF A_18_.BLIF \ +A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF SM_AMIGA_7_.BLIF AS_030.PIN.BLIF \ +inst_AS_030_000_SYNC.D +1-100101-1-- 1 +---------10- 1 +--------01-- 1 +-0-------1-- 1 +-----------1 1 +-1-----01-10 0 +-1----1-1-10 0 +-1---0--1-10 0 +-1--1---1-10 0 +-1-1----1-10 0 +-10-----1-10 0 +01------1-10 0 +---------0-0 0 +.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF SM_AMIGA_7_.BLIF \ +BG_000DFFSHreg.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D +---01- 1 +--0-1- 1 +0---1- 1 +----10 1 -1---- 1 -101-11 0 --0-0-- 0 +1011-1 0 +-0--0- 0 +.names inst_LDS_000_INT.BLIF DS_030.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +A0.PIN.BLIF inst_LDS_000_INT.D +-0100 1 +11--- 1 +01--- 0 +-0-1- 0 +-00-- 0 +-0--1 0 +.names inst_avec_expreg.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +AS_030.PIN.BLIF inst_AS_000_INT.D +-10- 1 +01-- 1 +--01 1 +0--1 1 +1-1- 0 +-0-0 0 +.names inst_avec_expreg.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF \ +inst_DS_000_ENABLE.BLIF AS_030.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D +---10- 1 +1-1--- 1 +11---1 1 +-00-1- 0 +-000-- 0 +--0-10 0 +0---1- 0 +--00-0 0 +0--0-- 0 +.names inst_CLK_OUT_NEreg.BLIF inst_CLK_000_D1.BLIF SM_AMIGA_1_.BLIF \ +inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D +--01- 1 +-0-1- 1 +1--1- 1 +--0-1 1 +-0--1 1 +1---1 1 +011-- 0 +---00 0 +.names inst_UDS_000_INT.BLIF DS_030.PIN.BLIF A0.PIN.BLIF inst_UDS_000_INT.D +11- 1 +-01 1 +01- 0 +-00 0 +.names inst_avec_expreg.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF \ +inst_RW_000_INT.BLIF RW.PIN.BLIF inst_RW_000_INT.D +--01- 1 +0--1- 1 +1-1-1 1 +-1--- 1 +101-0 0 +-000- 0 +00-0- 0 +.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF inst_A0_DMA.D +0010 1 +--0- 0 +-1-- 0 +1--- 0 +---1 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +inst_CLK_030_H.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +inst_CLK_030_H.D +1100-00- 1 +1100-0-0 1 +--0-100- 1 +--0-10-0 1 +-0--1--- 1 +-1---1-- 0 +-11----- 0 +-1----11 0 +---10--- 0 +-0--0--- 0 +0---0--- 0 +.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_RW_000_DMA.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +inst_RW_000_DMA.D +1-1---- 1 +0---1-- 1 +---1--- 1 +-1----- 1 +-----11 1 +00-000- 0 +1000-0- 0 +00-00-0 0 +1000--0 0 .names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_DS_000_DMA.D @@ -317,121 +439,32 @@ AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AS_000_DMA.D 00-00- 0 -000-0 0 00-0-0 0 -.names inst_CLK_000_D0.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ -AS_030.PIN.BLIF inst_AS_000_INT.D --10- 1 -01-- 1 ---01 1 -0--1 1 -1-1- 0 --0-0 0 -.names SM_AMIGA_1_.BLIF inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D -01- 1 -0-1 1 --00 0 -1-- 0 -.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF RW.PIN.BLIF \ -inst_RW_000_INT.D -00----01-0- 1 -00----010-- 1 ----0-1--11- 1 ---101---11- 1 ---0--1--11- 1 ---11----111 1 ----0-11---- 1 --1-0-1----- 1 -1--0-1----- 1 ---101-1---- 1 --1101------ 1 -1-101------ 1 ---0--11---- 1 --10--1----- 1 -1-0--1----- 1 ---11--1---1 1 --111------1 1 -1-11------1 1 -00----00-0- 0 -00----000-- 0 ----000--11- 0 ---11----110 0 ---0--0--11- 0 ----0001---- 0 --1-000----- 0 -1--000----- 0 ---11--1---0 0 --111------0 0 -1-11------0 0 ---0--01---- 0 --10--0----- 0 -1-0--0----- 0 -.names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \ -A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_CLK_000_D1.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_7_.BLIF inst_CLK_000_D2.BLIF AS_030.PIN.BLIF inst_AS_030_000_SYNC.D -1-1-00101-1----- 1 --0---------0-11- 1 -----------1--0-- 1 ----------01----- 1 ----0------1----- 1 --0--------1----- 1 -------------1--- 1 ----------------1 1 --1-1----01--01-0 0 --1-1---1-1--01-0 0 --1-1--0--1--01-0 0 --1-1-1---1--01-0 0 --1-11----1--01-0 0 --101-----1--01-0 0 -01-1-----1--01-0 0 -----------0-0-00 0 -----------0-00-0 0 -----------010--0 0 --1--------0-0--0 0 -.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ -inst_CLK_030_H.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ -inst_CLK_030_H.D -1100-00- 1 -1100-0-0 1 ---0-100- 1 ---0-10-0 1 --0--1--- 1 --1---1-- 0 --11----- 0 --1----11 0 ----10--- 0 --0--0--- 0 -0---0--- 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF inst_UDS_000_INT.BLIF \ -SM_AMIGA_5_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF A0.PIN.BLIF RW.PIN.BLIF \ -inst_UDS_000_INT.D ---10---0 1 --01----1 1 ----01--0 1 --0--1--1 1 -0--1-010 1 -11---011 1 -1-1----0 1 -0-1----1 1 ---1--1-- 1 -1---1--0 1 -0---1--1 1 -----11-- 1 ---000--0 0 --00-0--1 0 -0--1-000 0 -11---001 0 ---0-01-- 0 -1-0-0--0 0 -0-0-0--1 0 -.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF inst_A0_DMA.D -0010 1 ---0- 0 --1-- 0 -1--- 0 ----1 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AMIGA_BUS_ENABLE_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_BGACK_030_INT_D.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \ +inst_CLK_000_NE.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ +AS_030.PIN.BLIF inst_AMIGA_BUS_ENABLE_INTreg.D +-1----0-100- 1 +-1---1--100- 1 +-1-1----100- 1 +01------100- 1 +-11-------1- 1 +-11-----0--- 1 +-1-----1-1-1 1 +-11------1-- 1 +-1------11-1 1 +-1--0------- 1 +-1--------11 1 +1--0101-100- 0 +--0-1--00-0- 0 +--0-1---000- 0 +--0-1-----10 0 +--0-1----1-0 0 +-0---------- 0 +.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_NEreg.D +01 1 +1- 0 +-0 0 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 1 0 @@ -452,9 +485,17 @@ LDS_000.PIN.BLIF inst_A0_DMA.D .names CLK_OUT_INTreg.BLIF CLK_EXP 1 1 0 0 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -0 0 +.names FC_1_.BLIF BGACK_000.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ +FC_0_.BLIF AS_030.PIN.BLIF FPU_CS +------0- 1 +-----1-- 1 +----0--- 1 +---1---- 1 +--1----- 1 +-0------ 1 +0------- 1 +-------1 1 +11001010 0 .names AVEC 1 .names inst_avec_expreg.BLIF AVEC_EXP @@ -469,7 +510,7 @@ LDS_000.PIN.BLIF inst_A0_DMA.D .names RESETDFFRHreg.BLIF RESET 1 1 0 0 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE 1 1 0 0 .names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF RW.PIN.BLIF \ @@ -480,8 +521,9 @@ AMIGA_BUS_DATA_DIR --11 0 -0-0 0 -1-1 0 -.names AMIGA_BUS_ENABLE_LOW - 1 +.names inst_CLK_OUT_NEreg.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +0 0 .names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN 1111 1 --0- 0 @@ -494,6 +536,17 @@ AMIGA_BUS_DATA_DIR .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_0_.D +10 1 +01 1 +00 0 +11 0 +.names CLK_OSZI.BLIF cpu_est_0_.C +1 1 +0 0 +.names RST.BLIF cpu_est_0_.AR +0 1 +1 0 .names CLK_OSZI.BLIF cpu_est_1_.C 1 1 0 0 @@ -512,37 +565,6 @@ AMIGA_BUS_DATA_DIR .names RST.BLIF cpu_est_3_reg.AR 0 1 1 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D -100 1 --11 1 -0-1 1 -101 0 --10 0 -0-0 0 -.names CLK_OSZI.BLIF cpu_est_0_.C -1 1 -0 0 -.names RST.BLIF cpu_est_0_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_0_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_1_reg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST.BLIF IPL_030DFFSH_2_reg.AP -0 1 -1 0 .names CLK_OSZI.BLIF SM_AMIGA_7_.C 1 1 0 0 @@ -591,6 +613,228 @@ AMIGA_BUS_DATA_DIR .names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_2_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_3_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_4_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_5_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_6_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_7_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_8_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_9_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names RST.BLIF SIZE_DMA_0_.AP +0 1 +1 0 +.names CLK_OSZI.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST.BLIF SIZE_DMA_1_.AP +0 1 +1 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_0_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_1_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST.BLIF IPL_030DFFSH_2_reg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_0_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_1_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_2_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_3_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_4_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_5_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_6_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_7_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_8_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_9_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_10_.AR +0 1 +1 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C +1 1 +0 0 +.names RST.BLIF CLK_000_N_SYNC_11_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_0_.AR +0 1 +1 0 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C +1 1 +0 0 +.names RST.BLIF CLK_000_P_SYNC_1_.AR +0 1 +1 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 @@ -617,16 +861,16 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_CLK_OUT_PRE_25.AR 0 1 1 0 -.names CLK_OSZI.BLIF SIZE_DMA_0_.C +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names RST.BLIF SIZE_DMA_0_.AP +.names RST.BLIF inst_AS_030_000_SYNC.AP 0 1 1 0 -.names CLK_OSZI.BLIF SIZE_DMA_1_.C +.names CLK_OSZI.BLIF BG_000DFFSHreg.C 1 1 0 0 -.names RST.BLIF SIZE_DMA_1_.AP +.names RST.BLIF BG_000DFFSHreg.AP 0 1 1 0 .names CLK_OSZI.BLIF inst_LDS_000_INT.C @@ -635,22 +879,49 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_LDS_000_INT.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C +.names CLK_OSZI.BLIF inst_AS_000_INT.C 1 1 0 0 -.names RST.BLIF inst_FPU_CS_INTreg.AP +.names RST.BLIF inst_AS_000_INT.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_avec_expreg.C +.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names RST.BLIF inst_avec_expreg.AP +.names RST.BLIF inst_DS_000_ENABLE.AR 0 1 1 0 -.names CLK_OSZI.BLIF BG_000DFFSHreg.C +.names CLK_OSZI.BLIF inst_DSACK1_INT.C 1 1 0 0 -.names RST.BLIF BG_000DFFSHreg.AP +.names RST.BLIF inst_DSACK1_INT.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names RST.BLIF inst_UDS_000_INT.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names RST.BLIF inst_RW_000_INT.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_A0_DMA.C +1 1 +0 0 +.names RST.BLIF inst_A0_DMA.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names RST.BLIF inst_RW_000_DMA.AP 0 1 1 0 .names CLK_OSZI.BLIF inst_DS_000_DMA.C @@ -665,52 +936,16 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_AS_000_DMA.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_AS_000_INT.C +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C 1 1 0 0 -.names RST.BLIF inst_AS_000_INT.AP +.names RST.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_DSACK1_INT.C +.names CLK_OSZI.BLIF inst_CLK_OUT_NEreg.C 1 1 0 0 -.names RST.BLIF inst_DSACK1_INT.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names RST.BLIF inst_RW_000_INT.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_AS_030_000_SYNC.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_CLK_030_H.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_UDS_000_INT.C -1 1 -0 0 -.names RST.BLIF inst_UDS_000_INT.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_A0_DMA.C -1 1 -0 0 -.names RST.BLIF inst_A0_DMA.AP -0 1 -1 0 -.names DTACK.PIN.BLIF inst_DTACK_D0.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DTACK_D0.C -1 1 -0 0 -.names RST.BLIF inst_DTACK_D0.AP +.names RST.BLIF inst_CLK_OUT_NEreg.AR 0 1 1 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D @@ -722,7 +957,25 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_CLK_000_D2.AP 0 1 1 0 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D +.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names RST.BLIF inst_CLK_OUT_PRE.AR +0 1 +1 0 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_D3.C +1 1 +0 0 +.names RST.BLIF inst_CLK_000_D3.AP +0 1 +1 0 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI.BLIF CLK_OUT_INTreg.C @@ -758,6 +1011,15 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_CLK_OUT_PRE_50_D.AR 0 1 1 0 +.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names RST.BLIF inst_CLK_OUT_PRE_D.AR +0 1 +1 0 .names CLK_000.BLIF inst_CLK_000_D0.D 1 1 0 0 @@ -776,6 +1038,24 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_VPA_D.AP 0 1 1 0 +.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_avec_expreg.C +1 1 +0 0 +.names RST.BLIF inst_avec_expreg.AR +0 1 +1 0 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +0 0 +.names CLK_OSZI.BLIF inst_CLK_000_NE.C +1 1 +0 0 +.names RST.BLIF inst_CLK_000_NE.AR +0 1 +1 0 .names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C 1 1 0 0 @@ -805,12 +1085,14 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names inst_DS_000_DMA.BLIF DS_030 1 1 0 0 -.names inst_UDS_000_INT.BLIF UDS_000 -1 1 -0 0 -.names inst_LDS_000_INT.BLIF LDS_000 -1 1 -0 0 +.names inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF UDS_000 +0- 1 +-1 1 +10 0 +.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000 +1- 1 +-0 1 +01 0 .names inst_A0_DMA.BLIF A0 1 1 0 0 @@ -820,7 +1102,7 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names DSACK1.PIN.BLIF DTACK 1 1 0 0 -.names inst_RW_000_INT.BLIF RW +.names inst_RW_000_DMA.BLIF RW 1 1 0 0 .names SIZE_DMA_0_.BLIF SIZE_0_ @@ -879,9 +1161,17 @@ DTACK.OE .names inst_BGACK_030_INTreg.BLIF RW.OE 0 1 1 0 -.names inst_FPU_CS_INTreg.BLIF BERR.OE -0 1 -1 0 +.names FC_1_.BLIF BGACK_000.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ +FC_0_.BLIF AS_030.PIN.BLIF BERR.OE +11001010 1 +------0- 0 +-----1-- 0 +----0--- 0 +---1---- 0 +--1----- 0 +-0------ 0 +0------- 0 +-------1 0 .names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ A_25_.BLIF A_24_.BLIF CIIN.OE 00000000 1 @@ -911,21 +1201,4 @@ cpu_est_3_reg.BLIF inst_VMA_INTreg.D.X2 0----0-- 0 0-----0- 0 0------1 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_1_.BLIF \ -cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X1 -10111 1 -0---- 0 --1--- 0 ---0-- 0 ----0- 0 -----0 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ -cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X2 ------1 1 -101-0- 1 -10-00- 1 -0----0 0 --1---0 0 -----10 0 ---01-0 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 4f888df..61bf396 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Sat Jun 07 23:03:19 2014 +// Design '68030_tk' created Mon Jun 09 10:27:24 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 1a4d320..32280e2 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,27 +2,25 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Sat Jun 07 23:03:19 2014 +Design bus68030 created Mon Jun 09 10:27:24 2014 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- - 1 1 1 Pin RW_000 - 1 1 1 Pin RW_000.OE + 1 2 1 Pin UDS_000- + 1 1 1 Pin UDS_000.OE + 1 2 1 Pin LDS_000- + 1 1 1 Pin LDS_000.OE 0 0 1 Pin BERR - 1 1 1 Pin BERR.OE + 1 8 1 Pin BERR.OE 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C + 1 8 1 Pin FPU_CS- 1 1 1 Pin DTACK 1 3 1 Pin DTACK.OE 1 0 1 Pin AVEC - 1 1 1 Pin AVEC_EXP - 1 1 1 Pin RW - 1 1 1 Pin RW.OE - 1 1 1 Pin AMIGA_BUS_ENABLE 2 4 1 Pin AMIGA_BUS_DATA_DIR - 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE 1 3 1 Pin SIZE_1_.OE @@ -32,12 +30,6 @@ Design bus68030 created Sat Jun 07 23:03:19 2014 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C - 3 4 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C - 3 4 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin AS_030.OE 4 6 1 Pin AS_030.D 1 1 1 Pin AS_030.AP @@ -46,18 +38,18 @@ Design bus68030 created Sat Jun 07 23:03:19 2014 2 4 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C + 1 3 1 Pin SIZE_0_.OE + 1 4 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.AP + 1 1 1 Pin SIZE_0_.C + 1 1 1 Pin RW_000.OE + 3 5 1 Pin RW_000.D- + 1 1 1 Pin RW_000.AP + 1 1 1 Pin RW_000.C 1 3 1 Pin DS_030.OE 7 9 1 Pin DS_030.D 1 1 1 Pin DS_030.AP 1 1 1 Pin DS_030.C - 1 1 1 Pin UDS_000.OE - 7 8 1 Pin UDS_000.D- - 1 1 1 Pin UDS_000.AP - 1 1 1 Pin UDS_000.C - 1 1 1 Pin LDS_000.OE - 11 10 1 Pin LDS_000.D- - 1 1 1 Pin LDS_000.AP - 1 1 1 Pin LDS_000.C 1 3 1 Pin A0.OE 1 4 1 Pin A0.D 1 1 1 Pin A0.AP @@ -71,16 +63,21 @@ Design bus68030 created Sat Jun 07 23:03:19 2014 1 1 1 Pin CLK_EXP.AR 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C - 2 10 1 Pin FPU_CS.D- - 1 1 1 Pin FPU_CS.AP - 1 1 1 Pin FPU_CS.C + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C 1 1 1 Pin DSACK1.OE - 2 3 1 Pin DSACK1.D + 2 5 1 Pin DSACK1.D- 1 1 1 Pin DSACK1.AP 1 1 1 Pin DSACK1.C - 3 6 1 PinX1 E.D.X1 - 1 1 1 PinX2 E.D.X2 + 1 1 1 Pin AVEC_EXP.AR + 1 1 1 Pin AVEC_EXP.D + 1 1 1 Pin AVEC_EXP.C 1 1 1 Pin E.AR + 4 5 1 Pin E.D- 1 1 1 Pin E.C 2 7 1 PinX1 VMA.D.X1 1 5 1 PinX2 VMA.D.X2 @@ -89,14 +86,17 @@ Design bus68030 created Sat Jun 07 23:03:19 2014 1 1 1 Pin RESET.AR 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C - 1 3 1 Pin SIZE_0_.OE - 1 4 1 Pin SIZE_0_.D- - 1 1 1 Pin SIZE_0_.AP - 1 1 1 Pin SIZE_0_.C - 6 12 1 Node inst_avec_expreg.D- - 1 1 1 Node inst_avec_expreg.AP - 1 1 1 Node inst_avec_expreg.C - 8 16 1 Node inst_AS_030_000_SYNC.D + 1 1 1 Pin RW.OE + 4 7 1 Pin RW.D- + 1 1 1 Pin RW.AP + 1 1 1 Pin RW.C + 6 12 1 Pin AMIGA_BUS_ENABLE.D- + 1 1 1 Pin AMIGA_BUS_ENABLE.AP + 1 1 1 Pin AMIGA_BUS_ENABLE.C + 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.AR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW.D + 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.C + 5 12 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C 1 1 1 Node inst_BGACK_030_INT_D.D @@ -108,105 +108,181 @@ Design bus68030 created Sat Jun 07 23:03:19 2014 1 1 1 Node inst_CLK_OUT_PRE_50_D.AR 1 1 1 Node inst_CLK_OUT_PRE_50_D.D 1 1 1 Node inst_CLK_OUT_PRE_50_D.C + 1 1 1 Node inst_CLK_OUT_PRE.AR + 1 1 1 Node inst_CLK_OUT_PRE.D + 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node inst_CLK_000_D0.D 1 1 1 Node inst_CLK_000_D0.AP 1 1 1 Node inst_CLK_000_D0.C 1 1 1 Node inst_CLK_000_D1.D 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C - 1 1 1 Node inst_DTACK_D0.D - 1 1 1 Node inst_DTACK_D0.AP - 1 1 1 Node inst_DTACK_D0.C 1 1 1 Node inst_CLK_OUT_PRE_50.AR 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 1 1 Node inst_CLK_OUT_PRE_25.AR 3 3 1 Node inst_CLK_OUT_PRE_25.D 1 1 1 Node inst_CLK_OUT_PRE_25.C - 1 1 1 Node SM_AMIGA_1_.AR - 2 3 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 1 1 1 Node SM_AMIGA_6_.AR - 2 7 1 Node SM_AMIGA_6_.D - 1 1 1 Node SM_AMIGA_6_.C - 1 1 1 Node SM_AMIGA_0_.AR - 2 3 1 Node SM_AMIGA_0_.D - 1 1 1 Node SM_AMIGA_0_.C - 4 7 1 Node SM_AMIGA_7_.D- - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C - 14 11 1 Node inst_RW_000_INT.D- - 1 1 1 Node inst_RW_000_INT.AP - 1 1 1 Node inst_RW_000_INT.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.AP 1 1 1 Node inst_CLK_000_D2.C + 1 1 1 Node inst_CLK_000_D3.D + 1 1 1 Node inst_CLK_000_D3.AP + 1 1 1 Node inst_CLK_000_D3.C + 1 1 1 Node inst_CLK_000_NE.AR + 1 1 1 Node inst_CLK_000_NE.D + 1 1 1 Node inst_CLK_000_NE.C + 1 1 1 Node inst_CLK_OUT_PRE_D.AR + 1 1 1 Node inst_CLK_OUT_PRE_D.D + 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 1 1 Node CLK_000_P_SYNC_9_.AR + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_11_.AR + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 4 7 1 Node SM_AMIGA_7_.D- + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_6_.AR + 2 7 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C + 1 1 1 Node SM_AMIGA_1_.AR + 2 4 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node SM_AMIGA_0_.AR + 2 4 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 1 1 1 Node SM_AMIGA_4_.AR + 2 4 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C 5 8 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C + 2 5 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.AP + 1 1 1 Node inst_LDS_000_INT.C + 1 1 1 Node inst_DS_000_ENABLE.AR + 3 6 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 2 3 1 Node inst_UDS_000_INT.D + 1 1 1 Node inst_UDS_000_INT.AP + 1 1 1 Node inst_UDS_000_INT.C + 1 1 1 Node CLK_000_N_SYNC_0_.AR + 1 4 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_N_SYNC_1_.AR + 1 1 1 Node CLK_000_N_SYNC_1_.D + 1 1 1 Node CLK_000_N_SYNC_1_.C + 1 1 1 Node CLK_000_N_SYNC_2_.AR + 1 1 1 Node CLK_000_N_SYNC_2_.D + 1 1 1 Node CLK_000_N_SYNC_2_.C + 1 1 1 Node CLK_000_N_SYNC_3_.AR + 1 1 1 Node CLK_000_N_SYNC_3_.D + 1 1 1 Node CLK_000_N_SYNC_3_.C + 1 1 1 Node CLK_000_N_SYNC_4_.AR + 1 1 1 Node CLK_000_N_SYNC_4_.D + 1 1 1 Node CLK_000_N_SYNC_4_.C + 1 1 1 Node CLK_000_N_SYNC_5_.AR + 1 1 1 Node CLK_000_N_SYNC_5_.D + 1 1 1 Node CLK_000_N_SYNC_5_.C + 1 1 1 Node CLK_000_N_SYNC_6_.AR + 1 1 1 Node CLK_000_N_SYNC_6_.D + 1 1 1 Node CLK_000_N_SYNC_6_.C + 1 1 1 Node CLK_000_N_SYNC_7_.AR + 1 1 1 Node CLK_000_N_SYNC_7_.D + 1 1 1 Node CLK_000_N_SYNC_7_.C + 1 1 1 Node CLK_000_N_SYNC_8_.AR + 1 1 1 Node CLK_000_N_SYNC_8_.D + 1 1 1 Node CLK_000_N_SYNC_8_.C + 1 1 1 Node CLK_000_N_SYNC_9_.AR + 1 1 1 Node CLK_000_N_SYNC_9_.D + 1 1 1 Node CLK_000_N_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_10_.AR + 1 1 1 Node CLK_000_N_SYNC_10_.D + 1 1 1 Node CLK_000_N_SYNC_10_.C + 1 1 1 Node CLK_000_P_SYNC_0_.AR + 1 4 1 Node CLK_000_P_SYNC_0_.D + 1 1 1 Node CLK_000_P_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_1_.AR + 1 1 1 Node CLK_000_P_SYNC_1_.D + 1 1 1 Node CLK_000_P_SYNC_1_.C + 1 1 1 Node CLK_000_P_SYNC_2_.AR + 1 1 1 Node CLK_000_P_SYNC_2_.D + 1 1 1 Node CLK_000_P_SYNC_2_.C + 1 1 1 Node CLK_000_P_SYNC_3_.AR + 1 1 1 Node CLK_000_P_SYNC_3_.D + 1 1 1 Node CLK_000_P_SYNC_3_.C + 1 1 1 Node CLK_000_P_SYNC_4_.AR + 1 1 1 Node CLK_000_P_SYNC_4_.D + 1 1 1 Node CLK_000_P_SYNC_4_.C + 1 1 1 Node CLK_000_P_SYNC_5_.AR + 1 1 1 Node CLK_000_P_SYNC_5_.D + 1 1 1 Node CLK_000_P_SYNC_5_.C + 1 1 1 Node CLK_000_P_SYNC_6_.AR + 1 1 1 Node CLK_000_P_SYNC_6_.D + 1 1 1 Node CLK_000_P_SYNC_6_.C + 1 1 1 Node CLK_000_P_SYNC_7_.AR + 1 1 1 Node CLK_000_P_SYNC_7_.D + 1 1 1 Node CLK_000_P_SYNC_7_.C + 1 1 1 Node CLK_000_P_SYNC_8_.AR + 1 1 1 Node CLK_000_P_SYNC_8_.D + 1 1 1 Node CLK_000_P_SYNC_8_.C 1 1 1 Node SM_AMIGA_5_.AR - 2 3 1 Node SM_AMIGA_5_.D + 2 4 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C - 1 1 1 Node SM_AMIGA_4_.AR - 2 3 1 Node SM_AMIGA_4_.D - 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node SM_AMIGA_3_.AR - 4 9 1 Node SM_AMIGA_3_.D- + 5 9 1 Node SM_AMIGA_3_.T 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_2_.AR 3 9 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR - 3 3 1 Node cpu_est_0_.D + 2 2 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 1 1 1 Node cpu_est_1_.AR - 4 6 1 Node cpu_est_1_.T + 5 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 3 6 1 NodeX1 cpu_est_2_.D.X1 - 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.AR + 4 5 1 Node cpu_est_2_.D 1 1 1 Node cpu_est_2_.C ========= - 249 P-Term Total: 249 + 308 P-Term Total: 308 Total Pins: 59 - Total Nodes: 24 - Average P-Term/Output: 2 + Total Nodes: 50 + Average P-Term/Output: 1 Equations: -RW_000 = (inst_RW_000_INT.Q); +!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); -RW_000.OE = (BGACK_030.Q); +UDS_000.OE = (BGACK_030.Q); + +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); + +LDS_000.OE = (BGACK_030.Q); BERR = (0); -BERR.OE = (!FPU_CS.Q); +BERR.OE = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); CLK_DIV_OUT.AR = (!RST); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); CLK_DIV_OUT.C = (CLK_OSZI); +!FPU_CS = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + DTACK = (DSACK1.PIN); DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AVEC = (1); -AVEC_EXP = (inst_avec_expreg.Q); - -RW = (inst_RW_000_INT.Q); - -RW.OE = (!BGACK_030.Q); - -AMIGA_BUS_ENABLE = (inst_avec_expreg.Q); - AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN); -AMIGA_BUS_ENABLE_LOW = (1); - CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); @@ -228,22 +304,6 @@ IPL_030_2_.AP = (!RST); IPL_030_2_.C = (CLK_OSZI); -IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q - # inst_CLK_000_D1.Q & IPL_030_1_.Q - # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - -IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q - # inst_CLK_000_D1.Q & IPL_030_0_.Q - # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AS_030.D = (BGACK_030.Q @@ -257,13 +317,31 @@ AS_030.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); -!AS_000.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q +!AS_000.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q # !AS_000.Q & !AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); + +!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_0_.AP = (!RST); + +SIZE_0_.C = (CLK_OSZI); + +RW_000.OE = (BGACK_030.Q); + +!RW_000.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & !RW_000.Q + # !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !RW_000.Q + # AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q & !RW.PIN); + +RW_000.AP = (!RST); + +RW_000.C = (CLK_OSZI); + DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); DS_030.D = (BGACK_030.Q @@ -278,38 +356,6 @@ DS_030.AP = (!RST); DS_030.C = (CLK_OSZI); -UDS_000.OE = (BGACK_030.Q); - -!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_6_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN - # !UDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !A0.PIN & RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); - -UDS_000.AP = (!RST); - -UDS_000.C = (CLK_OSZI); - -LDS_000.OE = (BGACK_030.Q); - -!LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D0.Q & !LDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN - # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_6_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & A0.PIN & RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); - -LDS_000.AP = (!RST); - -LDS_000.C = (CLK_OSZI); - A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); @@ -334,34 +380,48 @@ BGACK_030.C = (CLK_OSZI); CLK_EXP.AR = (!RST); -CLK_EXP.D = (inst_CLK_OUT_PRE_25.Q); +CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); -!FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN - # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); +IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q + # inst_CLK_000_D1.Q & IPL_030_1_.Q + # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); -FPU_CS.AP = (!RST); +IPL_030_1_.AP = (!RST); -FPU_CS.C = (CLK_OSZI); +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q + # inst_CLK_000_D1.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); DSACK1.OE = (nEXP_SPACE); -DSACK1.D = (!SM_AMIGA_1_.Q & DSACK1.Q - # !SM_AMIGA_1_.Q & AS_030.PIN); +!DSACK1.D = (!DSACK1.Q & !AS_030.PIN + # !AMIGA_BUS_ENABLE_LOW.Q & inst_CLK_000_D1.Q & SM_AMIGA_1_.Q); DSACK1.AP = (!RST); DSACK1.C = (CLK_OSZI); -E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); +AVEC_EXP.AR = (!RST); -E.D.X2 = (E.Q); +AVEC_EXP.D = (CLK_000_P_SYNC_9_.Q); + +AVEC_EXP.C = (CLK_OSZI); E.AR = (!RST); +!E.D = (!AVEC_EXP.Q & !E.Q + # cpu_est_2_.Q & !E.Q + # AVEC_EXP.Q & cpu_est_1_.Q & cpu_est_2_.Q + # !cpu_est_0_.Q & cpu_est_1_.Q & !E.Q); + E.C = (CLK_OSZI); VMA.D.X1 = (VMA.Q @@ -379,32 +439,38 @@ RESET.D = (1); RESET.C = (CLK_OSZI); -SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); +RW.OE = (!BGACK_030.Q); -!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); +!RW.D = (CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN + # CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN); -SIZE_0_.AP = (!RST); +RW.AP = (!RST); -SIZE_0_.C = (CLK_OSZI); +RW.C = (CLK_OSZI); -!inst_avec_expreg.D = (!BGACK_030.Q - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); +!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_NE.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); -inst_avec_expreg.AP = (!RST); +AMIGA_BUS_ENABLE.AP = (!RST); -inst_avec_expreg.C = (CLK_OSZI); +AMIGA_BUS_ENABLE.C = (CLK_OSZI); -inst_AS_030_000_SYNC.D = (SM_AMIGA_1_.Q - # AS_030.PIN +AMIGA_BUS_ENABLE_LOW.AR = (!RST); + +AMIGA_BUS_ENABLE_LOW.D = (!inst_CLK_OUT_PRE.Q & inst_CLK_OUT_PRE_D.Q); + +AMIGA_BUS_ENABLE_LOW.C = (CLK_OSZI); + +inst_AS_030_000_SYNC.D = (AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q - # !CLK_030 & inst_AS_030_000_SYNC.Q # !BGACK_030.Q & inst_AS_030_000_SYNC.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q - # !nEXP_SPACE & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); @@ -429,6 +495,12 @@ inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI); +inst_CLK_OUT_PRE.AR = (!RST); + +inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_25.Q); + +inst_CLK_OUT_PRE.C = (CLK_OSZI); + inst_CLK_000_D0.D = (CLK_000); inst_CLK_000_D0.AP = (!RST); @@ -441,12 +513,6 @@ inst_CLK_000_D1.AP = (!RST); inst_CLK_000_D1.C = (CLK_OSZI); -inst_DTACK_D0.D = (DTACK.PIN); - -inst_DTACK_D0.AP = (!RST); - -inst_DTACK_D0.C = (CLK_OSZI); - inst_CLK_OUT_PRE_50.AR = (!RST); inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); @@ -461,61 +527,79 @@ inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_25.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); - -SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - -SM_AMIGA_6_.AR = (!RST); - -SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); - -SM_AMIGA_6_.C = (CLK_OSZI); - -SM_AMIGA_0_.AR = (!RST); - -SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_1_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); - -SM_AMIGA_0_.C = (CLK_OSZI); - -!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q - # !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D2.Q); - -SM_AMIGA_7_.AP = (!RST); - -SM_AMIGA_7_.C = (CLK_OSZI); - -!inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q - # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q - # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN - # CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q - # BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q - # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN - # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN - # CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN - # BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN - # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN - # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN - # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN); - -inst_RW_000_INT.AP = (!RST); - -inst_RW_000_INT.C = (CLK_OSZI); - inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.AP = (!RST); inst_CLK_000_D2.C = (CLK_OSZI); +inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); + +inst_CLK_000_D3.AP = (!RST); + +inst_CLK_000_D3.C = (CLK_OSZI); + +inst_CLK_000_NE.AR = (!RST); + +inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); + +inst_CLK_000_NE.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_D.AR = (!RST); + +inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE.Q); + +inst_CLK_OUT_PRE_D.C = (CLK_OSZI); + +CLK_000_P_SYNC_9_.AR = (!RST); + +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); + +CLK_000_P_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_11_.AR = (!RST); + +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +!SM_AMIGA_7_.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q + # !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q + # nEXP_SPACE & !AVEC_EXP.Q & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q); + +SM_AMIGA_7_.AP = (!RST); + +SM_AMIGA_7_.C = (CLK_OSZI); + +SM_AMIGA_6_.AR = (!RST); + +SM_AMIGA_6_.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & SM_AMIGA_7_.Q); + +SM_AMIGA_6_.C = (CLK_OSZI); + +SM_AMIGA_1_.AR = (!RST); + +SM_AMIGA_1_.D = (!inst_CLK_000_NE.Q & SM_AMIGA_1_.Q + # AVEC_EXP.Q & SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + +SM_AMIGA_0_.AR = (!RST); + +SM_AMIGA_0_.D = (!AVEC_EXP.Q & SM_AMIGA_0_.Q + # inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); + +SM_AMIGA_0_.C = (CLK_OSZI); + +SM_AMIGA_4_.AR = (!RST); + +SM_AMIGA_4_.D = (!AVEC_EXP.Q & SM_AMIGA_4_.Q + # inst_CLK_000_NE.Q & SM_AMIGA_5_.Q); + +SM_AMIGA_4_.C = (CLK_OSZI); + inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN @@ -524,62 +608,197 @@ inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q inst_CLK_030_H.C = (CLK_OSZI); +inst_LDS_000_INT.D = (inst_LDS_000_INT.Q & DS_030.PIN + # !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + +inst_LDS_000_INT.AP = (!RST); + +inst_LDS_000_INT.C = (CLK_OSZI); + +inst_DS_000_ENABLE.AR = (!RST); + +inst_DS_000_ENABLE.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q + # inst_DS_000_ENABLE.Q & !AS_030.PIN + # AVEC_EXP.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +inst_UDS_000_INT.D = (inst_UDS_000_INT.Q & DS_030.PIN + # !DS_030.PIN & A0.PIN); + +inst_UDS_000_INT.AP = (!RST); + +inst_UDS_000_INT.C = (CLK_OSZI); + +CLK_000_N_SYNC_0_.AR = (!RST); + +CLK_000_N_SYNC_0_.D = (!inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & inst_CLK_000_D3.Q); + +CLK_000_N_SYNC_0_.C = (CLK_OSZI); + +CLK_000_N_SYNC_1_.AR = (!RST); + +CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); + +CLK_000_N_SYNC_1_.C = (CLK_OSZI); + +CLK_000_N_SYNC_2_.AR = (!RST); + +CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); + +CLK_000_N_SYNC_2_.C = (CLK_OSZI); + +CLK_000_N_SYNC_3_.AR = (!RST); + +CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); + +CLK_000_N_SYNC_3_.C = (CLK_OSZI); + +CLK_000_N_SYNC_4_.AR = (!RST); + +CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); + +CLK_000_N_SYNC_4_.C = (CLK_OSZI); + +CLK_000_N_SYNC_5_.AR = (!RST); + +CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); + +CLK_000_N_SYNC_5_.C = (CLK_OSZI); + +CLK_000_N_SYNC_6_.AR = (!RST); + +CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); + +CLK_000_N_SYNC_6_.C = (CLK_OSZI); + +CLK_000_N_SYNC_7_.AR = (!RST); + +CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); + +CLK_000_N_SYNC_7_.C = (CLK_OSZI); + +CLK_000_N_SYNC_8_.AR = (!RST); + +CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); + +CLK_000_N_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_9_.AR = (!RST); + +CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); + +CLK_000_N_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_10_.AR = (!RST); + +CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); + +CLK_000_N_SYNC_10_.C = (CLK_OSZI); + +CLK_000_P_SYNC_0_.AR = (!RST); + +CLK_000_P_SYNC_0_.D = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & !inst_CLK_000_D3.Q); + +CLK_000_P_SYNC_0_.C = (CLK_OSZI); + +CLK_000_P_SYNC_1_.AR = (!RST); + +CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); + +CLK_000_P_SYNC_1_.C = (CLK_OSZI); + +CLK_000_P_SYNC_2_.AR = (!RST); + +CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); + +CLK_000_P_SYNC_2_.C = (CLK_OSZI); + +CLK_000_P_SYNC_3_.AR = (!RST); + +CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); + +CLK_000_P_SYNC_3_.C = (CLK_OSZI); + +CLK_000_P_SYNC_4_.AR = (!RST); + +CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); + +CLK_000_P_SYNC_4_.C = (CLK_OSZI); + +CLK_000_P_SYNC_5_.AR = (!RST); + +CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); + +CLK_000_P_SYNC_5_.C = (CLK_OSZI); + +CLK_000_P_SYNC_6_.AR = (!RST); + +CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); + +CLK_000_P_SYNC_6_.C = (CLK_OSZI); + +CLK_000_P_SYNC_7_.AR = (!RST); + +CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); + +CLK_000_P_SYNC_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_8_.AR = (!RST); + +CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); + +CLK_000_P_SYNC_8_.C = (CLK_OSZI); + SM_AMIGA_5_.AR = (!RST); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_5_.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q + # !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q); SM_AMIGA_5_.C = (CLK_OSZI); -SM_AMIGA_4_.AR = (!RST); - -SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); - -SM_AMIGA_4_.C = (CLK_OSZI); - SM_AMIGA_3_.AR = (!RST); -!SM_AMIGA_3_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q - # !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q - # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !cpu_est_1_.Q & E.Q); +SM_AMIGA_3_.T = (AVEC_EXP.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # !AVEC_EXP.Q & inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN + # inst_VPA_D.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !DTACK.PIN + # !AVEC_EXP.Q & !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q + # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.AR = (!RST); -SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q - # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); +SM_AMIGA_2_.D = (!AVEC_EXP.Q & SM_AMIGA_2_.Q + # inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN + # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_2_.C = (CLK_OSZI); cpu_est_0_.AR = (!RST); -cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q - # inst_CLK_000_D1.Q & cpu_est_0_.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q); +cpu_est_0_.D = (!AVEC_EXP.Q & cpu_est_0_.Q + # AVEC_EXP.Q & !cpu_est_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.AR = (!RST); -cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); +cpu_est_1_.D = (!AVEC_EXP.Q & cpu_est_1_.Q + # !cpu_est_0_.Q & cpu_est_1_.Q + # AVEC_EXP.Q & cpu_est_0_.Q & !cpu_est_1_.Q + # AVEC_EXP.Q & cpu_est_2_.Q & E.Q + # AVEC_EXP.Q & !cpu_est_2_.Q & !E.Q); cpu_est_1_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); - -cpu_est_2_.D.X2 = (cpu_est_2_.Q); - cpu_est_2_.AR = (!RST); +cpu_est_2_.D = (!AVEC_EXP.Q & cpu_est_2_.Q + # cpu_est_1_.Q & cpu_est_2_.Q + # AVEC_EXP.Q & !cpu_est_0_.Q & !cpu_est_1_.Q + # AVEC_EXP.Q & cpu_est_0_.Q & E.Q); + cpu_est_2_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index b71dba5..cf8a9f8 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -1,16 +1,16 @@ #PLAFILE 68030_tk.tt4 -#DATE 06/01/2014 +#DATE 06/08/2014 #DESIGN #DEVICE mach447a DATA LOCATION A0:G_8_69 // IO DATA LOCATION AMIGA_BUS_DATA_DIR:E_0_48 // OUT -DATA LOCATION AMIGA_BUS_ENABLE:D_3_34 // OUT -DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT +DATA LOCATION AMIGA_BUS_ENABLE:D_5_34 // IO {RN_AMIGA_BUS_ENABLE} +DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_12_20 // IO {RN_AMIGA_BUS_ENABLE_LOW} DATA LOCATION AS_000:D_4_33 // IO {RN_AS_000} DATA LOCATION AS_030:H_6_82 // IO {RN_AS_030} -DATA LOCATION AVEC:A_2_92 // OUT -DATA LOCATION AVEC_EXP:C_0_22 // OUT +DATA LOCATION AVEC:A_4_92 // OUT +DATA LOCATION AVEC_EXP:C_4_22 // IO {RN_AVEC_EXP} DATA LOCATION A_16_:A_*_96 // INP DATA LOCATION A_17_:F_*_59 // INP DATA LOCATION A_18_:A_*_95 // INP @@ -27,78 +27,106 @@ DATA LOCATION A_28_:C_*_15 // INP DATA LOCATION A_29_:B_*_6 // INP DATA LOCATION A_30_:B_*_5 // INP DATA LOCATION A_31_:B_*_4 // INP -DATA LOCATION BERR:E_2_41 // OUT +DATA LOCATION BERR:E_4_41 // OUT DATA LOCATION BGACK_000:D_*_28 // INP -DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} -DATA LOCATION BG_000:D_2_29 // IO {RN_BG_000} +DATA LOCATION BGACK_030:H_5_83 // IO {RN_BGACK_030} +DATA LOCATION BG_000:D_13_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP -DATA LOCATION CIIN:E_1_47 // OUT +DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP +DATA LOCATION CLK_000_N_SYNC_0_:F_6 // NOD +DATA LOCATION CLK_000_N_SYNC_10_:A_9 // NOD +DATA LOCATION CLK_000_N_SYNC_11_:A_10 // NOD +DATA LOCATION CLK_000_N_SYNC_1_:A_6 // NOD +DATA LOCATION CLK_000_N_SYNC_2_:E_5 // NOD +DATA LOCATION CLK_000_N_SYNC_3_:C_14 // NOD +DATA LOCATION CLK_000_N_SYNC_4_:A_2 // NOD +DATA LOCATION CLK_000_N_SYNC_5_:A_13 // NOD +DATA LOCATION CLK_000_N_SYNC_6_:F_2 // NOD +DATA LOCATION CLK_000_N_SYNC_7_:E_1 // NOD +DATA LOCATION CLK_000_N_SYNC_8_:C_10 // NOD +DATA LOCATION CLK_000_N_SYNC_9_:F_13 // NOD +DATA LOCATION CLK_000_P_SYNC_0_:F_9 // NOD +DATA LOCATION CLK_000_P_SYNC_1_:B_2 // NOD +DATA LOCATION CLK_000_P_SYNC_2_:C_6 // NOD +DATA LOCATION CLK_000_P_SYNC_3_:A_5 // NOD +DATA LOCATION CLK_000_P_SYNC_4_:G_6 // NOD +DATA LOCATION CLK_000_P_SYNC_5_:C_2 // NOD +DATA LOCATION CLK_000_P_SYNC_6_:C_13 // NOD +DATA LOCATION CLK_000_P_SYNC_7_:A_1 // NOD +DATA LOCATION CLK_000_P_SYNC_8_:F_5 // NOD +DATA LOCATION CLK_000_P_SYNC_9_:B_6 // NOD DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_DIV_OUT:G_3_65 // OUT +DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION DSACK1:H_8_81 // IO {RN_DSACK1} +DATA LOCATION DSACK1:H_12_81 // IO {RN_DSACK1} DATA LOCATION DS_030:A_0_98 // IO {RN_DS_030} DATA LOCATION DTACK:D_0_30 // IO -DATA LOCATION E:G_2_66 // IO {RN_E} +DATA LOCATION E:G_4_66 // IO {RN_E} DATA LOCATION FC_0_:F_*_57 // INP DATA LOCATION FC_1_:F_*_58 // INP -DATA LOCATION FPU_CS:H_2_78 // IO {RN_FPU_CS} -DATA LOCATION IPL_030_0_:B_4_8 // IO {RN_IPL_030_0_} -DATA LOCATION IPL_030_1_:B_6_7 // IO {RN_IPL_030_1_} -DATA LOCATION IPL_030_2_:B_2_9 // IO {RN_IPL_030_2_} +DATA LOCATION FPU_CS:H_2_78 // OUT +DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_} +DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_} +DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000} +DATA LOCATION LDS_000:D_12_31 // IO DATA LOCATION RESET:B_1_3 // OUT +DATA LOCATION RN_AMIGA_BUS_ENABLE:D_5 // NOD {AMIGA_BUS_ENABLE} +DATA LOCATION RN_AMIGA_BUS_ENABLE_LOW:C_12 // NOD {AMIGA_BUS_ENABLE_LOW} DATA LOCATION RN_AS_000:D_4 // NOD {AS_000} DATA LOCATION RN_AS_030:H_6 // NOD {AS_030} -DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} -DATA LOCATION RN_BG_000:D_2 // NOD {BG_000} -DATA LOCATION RN_DSACK1:H_8 // NOD {DSACK1} +DATA LOCATION RN_AVEC_EXP:C_4 // NOD {AVEC_EXP} +DATA LOCATION RN_BGACK_030:H_5 // NOD {BGACK_030} +DATA LOCATION RN_BG_000:D_13 // NOD {BG_000} +DATA LOCATION RN_DSACK1:H_12 // NOD {DSACK1} DATA LOCATION RN_DS_030:A_0 // NOD {DS_030} -DATA LOCATION RN_E:G_2 // NOD {E} -DATA LOCATION RN_FPU_CS:H_2 // NOD {FPU_CS} -DATA LOCATION RN_IPL_030_0_:B_4 // NOD {IPL_030_0_} -DATA LOCATION RN_IPL_030_1_:B_6 // NOD {IPL_030_1_} -DATA LOCATION RN_IPL_030_2_:B_2 // NOD {IPL_030_2_} -DATA LOCATION RN_LDS_000:D_8 // NOD {LDS_000} -DATA LOCATION RN_UDS_000:D_6 // NOD {UDS_000} +DATA LOCATION RN_E:G_4 // NOD {E} +DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} +DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} +DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} +DATA LOCATION RN_RW:G_0 // NOD {RW} +DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} DATA LOCATION RN_VMA:D_1 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RW:G_0_71 // IO -DATA LOCATION RW_000:H_0_80 // IO -DATA LOCATION SIZE_0_:G_1_70 // IO +DATA LOCATION RW:G_0_71 // IO {RN_RW} +DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} +DATA LOCATION SIZE_0_:G_12_70 // IO DATA LOCATION SIZE_1_:H_1_79 // IO -DATA LOCATION SM_AMIGA_0_:H_9 // NOD -DATA LOCATION SM_AMIGA_1_:B_3 // NOD -DATA LOCATION SM_AMIGA_2_:A_1 // NOD -DATA LOCATION SM_AMIGA_3_:A_4 // NOD -DATA LOCATION SM_AMIGA_4_:A_5 // NOD -DATA LOCATION SM_AMIGA_5_:D_11 // NOD -DATA LOCATION SM_AMIGA_6_:G_6 // NOD -DATA LOCATION SM_AMIGA_7_:H_5 // NOD -DATA LOCATION UDS_000:D_6_32 // IO {RN_UDS_000} +DATA LOCATION SM_AMIGA_0_:D_6 // NOD +DATA LOCATION SM_AMIGA_1_:F_8 // NOD +DATA LOCATION SM_AMIGA_2_:F_1 // NOD +DATA LOCATION SM_AMIGA_3_:F_12 // NOD +DATA LOCATION SM_AMIGA_4_:B_9 // NOD +DATA LOCATION SM_AMIGA_5_:B_13 // NOD +DATA LOCATION SM_AMIGA_6_:G_5 // NOD +DATA LOCATION SM_AMIGA_7_:D_2 // NOD +DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_1_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:D_10 // NOD -DATA LOCATION cpu_est_1_:D_7 // NOD -DATA LOCATION cpu_est_2_:D_9 // NOD -DATA LOCATION inst_AS_030_000_SYNC:H_7 // NOD -DATA LOCATION inst_BGACK_030_INT_D:B_9 // NOD -DATA LOCATION inst_CLK_000_D0:H_3 // NOD -DATA LOCATION inst_CLK_000_D1:D_5 // NOD -DATA LOCATION inst_CLK_000_D2:H_10 // NOD -DATA LOCATION inst_CLK_030_H:B_5 // NOD -DATA LOCATION inst_CLK_OUT_PRE_25:B_7 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:H_11 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50_D:H_12 // NOD -DATA LOCATION inst_DTACK_D0:B_8 // NOD -DATA LOCATION inst_RW_000_INT:G_5 // NOD -DATA LOCATION inst_VPA_D:A_3 // NOD -DATA LOCATION inst_avec_expreg:G_4 // NOD +DATA LOCATION cpu_est_0_:F_4 // NOD +DATA LOCATION cpu_est_1_:G_9 // NOD +DATA LOCATION cpu_est_2_:G_13 // NOD +DATA LOCATION inst_AS_030_000_SYNC:H_4 // NOD +DATA LOCATION inst_BGACK_030_INT_D:H_10 // NOD +DATA LOCATION inst_CLK_000_D0:F_0 // NOD +DATA LOCATION inst_CLK_000_D1:H_9 // NOD +DATA LOCATION inst_CLK_000_D2:D_9 // NOD +DATA LOCATION inst_CLK_000_D3:E_9 // NOD +DATA LOCATION inst_CLK_000_NE:A_8 // NOD +DATA LOCATION inst_CLK_030_H:A_12 // NOD +DATA LOCATION inst_CLK_OUT_PRE:B_10 // NOD +DATA LOCATION inst_CLK_OUT_PRE_25:C_1 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:E_8 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50_D:H_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:C_8 // NOD +DATA LOCATION inst_DS_000_ENABLE:B_5 // NOD +DATA LOCATION inst_LDS_000_INT:C_9 // NOD +DATA LOCATION inst_UDS_000_INT:C_5 // NOD +DATA LOCATION inst_VPA_D:G_2 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR A0:BI DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT @@ -160,98 +188,90 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL A_22_:0 -DATA SLEW A_22_:1 -DATA PW_LEVEL A_21_:0 -DATA SLEW A_21_:1 -DATA PW_LEVEL A_20_:0 -DATA SLEW A_20_:1 -DATA PW_LEVEL A_19_:0 -DATA SLEW A_19_:1 DATA PW_LEVEL A_31_:0 DATA SLEW A_31_:1 -DATA PW_LEVEL A_18_:0 -DATA SLEW A_18_:1 -DATA PW_LEVEL A_17_:0 -DATA SLEW A_17_:1 -DATA PW_LEVEL A_16_:0 -DATA SLEW A_16_:1 DATA PW_LEVEL IPL_2_:0 DATA SLEW IPL_2_:1 -DATA PW_LEVEL IPL_1_:0 -DATA SLEW IPL_1_:1 DATA PW_LEVEL FC_1_:0 DATA SLEW FC_1_:1 -DATA PW_LEVEL IPL_0_:0 -DATA SLEW IPL_0_:1 -DATA PW_LEVEL FC_0_:0 -DATA SLEW FC_0_:1 -DATA PW_LEVEL RW_000:0 -DATA SLEW RW_000:1 -DATA SLEW nEXP_SPACE:1 -DATA PW_LEVEL BERR:0 -DATA SLEW BERR:1 -DATA PW_LEVEL BG_030:0 -DATA SLEW BG_030:1 -DATA PW_LEVEL BGACK_000:0 -DATA SLEW BGACK_000:1 -DATA SLEW CLK_030:1 -DATA SLEW CLK_000:1 -DATA SLEW CLK_OSZI:1 -DATA PW_LEVEL CLK_DIV_OUT:0 -DATA SLEW CLK_DIV_OUT:1 -DATA PW_LEVEL DTACK:0 -DATA SLEW DTACK:1 -DATA PW_LEVEL AVEC:0 -DATA SLEW AVEC:1 -DATA PW_LEVEL AVEC_EXP:0 -DATA SLEW AVEC_EXP:1 -DATA SLEW VPA:1 -DATA SLEW RST:1 -DATA PW_LEVEL RW:0 -DATA SLEW RW:1 -DATA PW_LEVEL AMIGA_BUS_ENABLE:0 -DATA SLEW AMIGA_BUS_ENABLE:1 -DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 -DATA SLEW AMIGA_BUS_DATA_DIR:1 -DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 -DATA SLEW AMIGA_BUS_ENABLE_LOW:1 -DATA PW_LEVEL CIIN:0 -DATA SLEW CIIN:1 DATA PW_LEVEL A_30_:0 DATA SLEW A_30_:1 DATA PW_LEVEL A_29_:0 DATA SLEW A_29_:1 +DATA PW_LEVEL UDS_000:0 +DATA SLEW UDS_000:1 DATA PW_LEVEL A_28_:0 DATA SLEW A_28_:1 +DATA PW_LEVEL LDS_000:0 +DATA SLEW LDS_000:1 DATA PW_LEVEL A_27_:0 DATA SLEW A_27_:1 DATA PW_LEVEL A_26_:0 DATA SLEW A_26_:1 +DATA SLEW nEXP_SPACE:1 DATA PW_LEVEL A_25_:0 DATA SLEW A_25_:1 +DATA PW_LEVEL BERR:0 +DATA SLEW BERR:1 DATA PW_LEVEL A_24_:0 DATA SLEW A_24_:1 +DATA PW_LEVEL BG_030:0 +DATA SLEW BG_030:1 DATA PW_LEVEL A_23_:0 DATA SLEW A_23_:1 +DATA PW_LEVEL A_22_:0 +DATA SLEW A_22_:1 +DATA PW_LEVEL A_21_:0 +DATA SLEW A_21_:1 +DATA PW_LEVEL BGACK_000:0 +DATA SLEW BGACK_000:1 +DATA PW_LEVEL A_20_:0 +DATA SLEW A_20_:1 +DATA SLEW CLK_030:1 +DATA PW_LEVEL A_19_:0 +DATA SLEW A_19_:1 +DATA SLEW CLK_000:1 +DATA PW_LEVEL A_18_:0 +DATA SLEW A_18_:1 +DATA SLEW CLK_OSZI:1 +DATA PW_LEVEL A_17_:0 +DATA SLEW A_17_:1 +DATA PW_LEVEL CLK_DIV_OUT:0 +DATA SLEW CLK_DIV_OUT:1 +DATA PW_LEVEL A_16_:0 +DATA SLEW A_16_:1 +DATA PW_LEVEL FPU_CS:0 +DATA SLEW FPU_CS:1 +DATA PW_LEVEL IPL_1_:0 +DATA SLEW IPL_1_:1 +DATA PW_LEVEL DTACK:0 +DATA SLEW DTACK:1 +DATA PW_LEVEL IPL_0_:0 +DATA SLEW IPL_0_:1 +DATA PW_LEVEL AVEC:0 +DATA SLEW AVEC:1 +DATA PW_LEVEL FC_0_:0 +DATA SLEW FC_0_:1 +DATA SLEW VPA:1 +DATA SLEW RST:1 +DATA PW_LEVEL AMIGA_BUS_DATA_DIR:0 +DATA SLEW AMIGA_BUS_DATA_DIR:1 +DATA PW_LEVEL CIIN:0 +DATA SLEW CIIN:1 DATA PW_LEVEL SIZE_1_:0 DATA SLEW SIZE_1_:1 DATA PW_LEVEL IPL_030_2_:0 DATA SLEW IPL_030_2_:1 -DATA PW_LEVEL IPL_030_1_:0 -DATA SLEW IPL_030_1_:1 -DATA PW_LEVEL IPL_030_0_:0 -DATA SLEW IPL_030_0_:1 DATA PW_LEVEL AS_030:0 DATA SLEW AS_030:1 DATA PW_LEVEL AS_000:0 DATA SLEW AS_000:1 +DATA PW_LEVEL SIZE_0_:0 +DATA SLEW SIZE_0_:1 +DATA PW_LEVEL RW_000:0 +DATA SLEW RW_000:1 DATA PW_LEVEL DS_030:0 DATA SLEW DS_030:1 -DATA PW_LEVEL UDS_000:0 -DATA SLEW UDS_000:1 -DATA PW_LEVEL LDS_000:0 -DATA SLEW LDS_000:1 DATA PW_LEVEL A0:0 DATA SLEW A0:1 DATA PW_LEVEL BG_000:0 @@ -260,20 +280,26 @@ DATA PW_LEVEL BGACK_030:0 DATA SLEW BGACK_030:1 DATA PW_LEVEL CLK_EXP:0 DATA SLEW CLK_EXP:1 -DATA PW_LEVEL FPU_CS:0 -DATA SLEW FPU_CS:1 +DATA PW_LEVEL IPL_030_1_:0 +DATA SLEW IPL_030_1_:1 +DATA PW_LEVEL IPL_030_0_:0 +DATA SLEW IPL_030_0_:1 DATA PW_LEVEL DSACK1:0 DATA SLEW DSACK1:1 +DATA PW_LEVEL AVEC_EXP:0 +DATA SLEW AVEC_EXP:1 DATA PW_LEVEL E:0 DATA SLEW E:1 DATA PW_LEVEL VMA:0 DATA SLEW VMA:1 DATA PW_LEVEL RESET:0 DATA SLEW RESET:1 -DATA PW_LEVEL SIZE_0_:0 -DATA SLEW SIZE_0_:1 -DATA PW_LEVEL inst_avec_expreg:0 -DATA SLEW inst_avec_expreg:1 +DATA PW_LEVEL RW:0 +DATA SLEW RW:1 +DATA PW_LEVEL AMIGA_BUS_ENABLE:0 +DATA SLEW AMIGA_BUS_ENABLE:1 +DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 +DATA SLEW AMIGA_BUS_ENABLE_LOW:1 DATA PW_LEVEL inst_AS_030_000_SYNC:0 DATA SLEW inst_AS_030_000_SYNC:1 DATA PW_LEVEL inst_BGACK_030_INT_D:0 @@ -282,34 +308,88 @@ DATA PW_LEVEL inst_VPA_D:0 DATA SLEW inst_VPA_D:1 DATA PW_LEVEL inst_CLK_OUT_PRE_50_D:0 DATA SLEW inst_CLK_OUT_PRE_50_D:1 +DATA PW_LEVEL inst_CLK_OUT_PRE:0 +DATA SLEW inst_CLK_OUT_PRE:1 DATA PW_LEVEL inst_CLK_000_D0:0 DATA SLEW inst_CLK_000_D0:1 DATA PW_LEVEL inst_CLK_000_D1:0 DATA SLEW inst_CLK_000_D1:1 -DATA PW_LEVEL inst_DTACK_D0:0 -DATA SLEW inst_DTACK_D0:1 DATA PW_LEVEL inst_CLK_OUT_PRE_50:0 DATA SLEW inst_CLK_OUT_PRE_50:1 DATA PW_LEVEL inst_CLK_OUT_PRE_25:0 DATA SLEW inst_CLK_OUT_PRE_25:1 -DATA PW_LEVEL SM_AMIGA_1_:0 -DATA SLEW SM_AMIGA_1_:1 -DATA PW_LEVEL SM_AMIGA_6_:0 -DATA SLEW SM_AMIGA_6_:1 -DATA PW_LEVEL SM_AMIGA_0_:0 -DATA SLEW SM_AMIGA_0_:1 -DATA PW_LEVEL SM_AMIGA_7_:0 -DATA SLEW SM_AMIGA_7_:1 -DATA PW_LEVEL inst_RW_000_INT:0 -DATA SLEW inst_RW_000_INT:1 DATA PW_LEVEL inst_CLK_000_D2:0 DATA SLEW inst_CLK_000_D2:1 -DATA PW_LEVEL inst_CLK_030_H:0 -DATA SLEW inst_CLK_030_H:1 -DATA PW_LEVEL SM_AMIGA_5_:0 -DATA SLEW SM_AMIGA_5_:1 +DATA PW_LEVEL inst_CLK_000_D3:0 +DATA SLEW inst_CLK_000_D3:1 +DATA PW_LEVEL inst_CLK_000_NE:0 +DATA SLEW inst_CLK_000_NE:1 +DATA PW_LEVEL inst_CLK_OUT_PRE_D:0 +DATA SLEW inst_CLK_OUT_PRE_D:1 +DATA PW_LEVEL CLK_000_P_SYNC_9_:0 +DATA SLEW CLK_000_P_SYNC_9_:1 +DATA PW_LEVEL CLK_000_N_SYNC_11_:0 +DATA SLEW CLK_000_N_SYNC_11_:1 +DATA PW_LEVEL SM_AMIGA_7_:0 +DATA SLEW SM_AMIGA_7_:1 +DATA PW_LEVEL SM_AMIGA_6_:0 +DATA SLEW SM_AMIGA_6_:1 +DATA PW_LEVEL SM_AMIGA_1_:0 +DATA SLEW SM_AMIGA_1_:1 +DATA PW_LEVEL SM_AMIGA_0_:0 +DATA SLEW SM_AMIGA_0_:1 DATA PW_LEVEL SM_AMIGA_4_:0 DATA SLEW SM_AMIGA_4_:1 +DATA PW_LEVEL inst_CLK_030_H:0 +DATA SLEW inst_CLK_030_H:1 +DATA PW_LEVEL inst_LDS_000_INT:0 +DATA SLEW inst_LDS_000_INT:1 +DATA PW_LEVEL inst_DS_000_ENABLE:0 +DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL inst_UDS_000_INT:0 +DATA SLEW inst_UDS_000_INT:1 +DATA PW_LEVEL CLK_000_N_SYNC_0_:0 +DATA SLEW CLK_000_N_SYNC_0_:1 +DATA PW_LEVEL CLK_000_N_SYNC_1_:0 +DATA SLEW CLK_000_N_SYNC_1_:1 +DATA PW_LEVEL CLK_000_N_SYNC_2_:0 +DATA SLEW CLK_000_N_SYNC_2_:1 +DATA PW_LEVEL CLK_000_N_SYNC_3_:0 +DATA SLEW CLK_000_N_SYNC_3_:1 +DATA PW_LEVEL CLK_000_N_SYNC_4_:0 +DATA SLEW CLK_000_N_SYNC_4_:1 +DATA PW_LEVEL CLK_000_N_SYNC_5_:0 +DATA SLEW CLK_000_N_SYNC_5_:1 +DATA PW_LEVEL CLK_000_N_SYNC_6_:0 +DATA SLEW CLK_000_N_SYNC_6_:1 +DATA PW_LEVEL CLK_000_N_SYNC_7_:0 +DATA SLEW CLK_000_N_SYNC_7_:1 +DATA PW_LEVEL CLK_000_N_SYNC_8_:0 +DATA SLEW CLK_000_N_SYNC_8_:1 +DATA PW_LEVEL CLK_000_N_SYNC_9_:0 +DATA SLEW CLK_000_N_SYNC_9_:1 +DATA PW_LEVEL CLK_000_N_SYNC_10_:0 +DATA SLEW CLK_000_N_SYNC_10_:1 +DATA PW_LEVEL CLK_000_P_SYNC_0_:0 +DATA SLEW CLK_000_P_SYNC_0_:1 +DATA PW_LEVEL CLK_000_P_SYNC_1_:0 +DATA SLEW CLK_000_P_SYNC_1_:1 +DATA PW_LEVEL CLK_000_P_SYNC_2_:0 +DATA SLEW CLK_000_P_SYNC_2_:1 +DATA PW_LEVEL CLK_000_P_SYNC_3_:0 +DATA SLEW CLK_000_P_SYNC_3_:1 +DATA PW_LEVEL CLK_000_P_SYNC_4_:0 +DATA SLEW CLK_000_P_SYNC_4_:1 +DATA PW_LEVEL CLK_000_P_SYNC_5_:0 +DATA SLEW CLK_000_P_SYNC_5_:1 +DATA PW_LEVEL CLK_000_P_SYNC_6_:0 +DATA SLEW CLK_000_P_SYNC_6_:1 +DATA PW_LEVEL CLK_000_P_SYNC_7_:0 +DATA SLEW CLK_000_P_SYNC_7_:1 +DATA PW_LEVEL CLK_000_P_SYNC_8_:0 +DATA SLEW CLK_000_P_SYNC_8_:1 +DATA PW_LEVEL SM_AMIGA_5_:0 +DATA SLEW SM_AMIGA_5_:1 DATA PW_LEVEL SM_AMIGA_3_:0 DATA SLEW SM_AMIGA_3_:1 DATA PW_LEVEL SM_AMIGA_2_:0 @@ -321,17 +401,19 @@ DATA SLEW cpu_est_1_:1 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:1 DATA PW_LEVEL RN_IPL_030_2_:0 -DATA PW_LEVEL RN_IPL_030_1_:0 -DATA PW_LEVEL RN_IPL_030_0_:0 DATA PW_LEVEL RN_AS_030:0 DATA PW_LEVEL RN_AS_000:0 +DATA PW_LEVEL RN_RW_000:0 DATA PW_LEVEL RN_DS_030:0 -DATA PW_LEVEL RN_UDS_000:0 -DATA PW_LEVEL RN_LDS_000:0 DATA PW_LEVEL RN_BG_000:0 DATA PW_LEVEL RN_BGACK_030:0 -DATA PW_LEVEL RN_FPU_CS:0 +DATA PW_LEVEL RN_IPL_030_1_:0 +DATA PW_LEVEL RN_IPL_030_0_:0 DATA PW_LEVEL RN_DSACK1:0 +DATA PW_LEVEL RN_AVEC_EXP:0 DATA PW_LEVEL RN_E:0 DATA PW_LEVEL RN_VMA:0 +DATA PW_LEVEL RN_RW:0 +DATA PW_LEVEL RN_AMIGA_BUS_ENABLE:0 +DATA PW_LEVEL RN_AMIGA_BUS_ENABLE_LOW:0 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index aeb34c7..8070001 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,17 +1,24 @@ -GROUP MACH_SEG_A DS_030 RN_DS_030 SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_4_ inst_VPA_D - AVEC +GROUP MACH_SEG_A DS_030 RN_DS_030 inst_CLK_000_NE CLK_000_N_SYNC_11_ CLK_000_N_SYNC_1_ + CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_10_ CLK_000_P_SYNC_3_ + CLK_000_P_SYNC_7_ AVEC inst_CLK_030_H GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ CLK_EXP RESET inst_CLK_OUT_PRE_25 SM_AMIGA_1_ inst_DTACK_D0 - inst_BGACK_030_INT_D inst_CLK_030_H -GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW -GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 - RN_BG_000 AS_000 RN_AS_000 cpu_est_1_ cpu_est_2_ SM_AMIGA_5_ cpu_est_0_ - inst_CLK_000_D1 DTACK AMIGA_BUS_ENABLE -GROUP MACH_SEG_E CIIN AMIGA_BUS_DATA_DIR BERR -GROUP MACH_SEG_G E RN_E A0 SIZE_0_ CLK_DIV_OUT inst_avec_expreg inst_RW_000_INT - SM_AMIGA_6_ RW -GROUP MACH_SEG_H FPU_CS RN_FPU_CS AS_030 RN_AS_030 SIZE_1_ DSACK1 RN_DSACK1 - BGACK_030 RN_BGACK_030 inst_AS_030_000_SYNC SM_AMIGA_7_ SM_AMIGA_0_ - inst_CLK_000_D0 inst_CLK_OUT_PRE_50_D inst_CLK_OUT_PRE_50 inst_CLK_000_D2 - RW_000 \ No newline at end of file + RN_IPL_030_2_ CLK_EXP RESET inst_DS_000_ENABLE SM_AMIGA_4_ SM_AMIGA_5_ + CLK_000_P_SYNC_9_ CLK_000_P_SYNC_1_ inst_CLK_OUT_PRE +GROUP MACH_SEG_C AMIGA_BUS_ENABLE_LOW RN_AMIGA_BUS_ENABLE_LOW AVEC_EXP + RN_AVEC_EXP inst_LDS_000_INT inst_CLK_OUT_PRE_25 inst_UDS_000_INT + CLK_000_N_SYNC_3_ CLK_000_N_SYNC_8_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_5_ + CLK_000_P_SYNC_6_ inst_CLK_OUT_PRE_D +GROUP MACH_SEG_D AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE VMA RN_VMA BG_000 + RN_BG_000 AS_000 RN_AS_000 SM_AMIGA_7_ SM_AMIGA_0_ inst_CLK_000_D2 + DTACK LDS_000 UDS_000 +GROUP MACH_SEG_E CLK_000_N_SYNC_2_ CLK_000_N_SYNC_7_ inst_CLK_OUT_PRE_50 + inst_CLK_000_D3 CIIN BERR AMIGA_BUS_DATA_DIR +GROUP MACH_SEG_F SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_1_ CLK_000_N_SYNC_0_ + CLK_000_P_SYNC_0_ cpu_est_0_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_9_ + CLK_000_P_SYNC_8_ inst_CLK_000_D0 +GROUP MACH_SEG_G RW RN_RW A0 SIZE_0_ E RN_E CLK_DIV_OUT SM_AMIGA_6_ cpu_est_1_ + cpu_est_2_ inst_VPA_D CLK_000_P_SYNC_4_ +GROUP MACH_SEG_H AS_030 RN_AS_030 DSACK1 RN_DSACK1 RW_000 RN_RW_000 SIZE_1_ + BGACK_030 RN_BGACK_030 inst_AS_030_000_SYNC inst_CLK_OUT_PRE_50_D + inst_CLK_000_D1 inst_BGACK_030_INT_D FPU_CS \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 9f5ca81..6fe961f 100644 Binary files a/Logic/68030_tk.ipr and b/Logic/68030_tk.ipr differ diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 48a39c0..5b70ee8 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Sat Jun 07 23:03:24 2014 +DATE: Mon Jun 09 10:27:29 2014 ABEL mach447a * @@ -25,89 +25,99 @@ NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y * NOTE SET/RESET treated as DONT_CARE? Y * NOTE Reduce Unforced Global Clocks? N * NOTE Iterate between partitioning and place/route? Y * -NOTE Balanced partitioning? N * +NOTE Balanced partitioning? Y * NOTE Reduce Routes Per Placement? N * -NOTE Spread Placement? N * +NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS A_22_:85 A_21_:94 A_20_:93 A_19_:97 A_31_:4 A_18_:95* -NOTE PINS A_17_:59 A_16_:96 IPL_2_:68 IPL_1_:56 FC_1_:58* -NOTE PINS IPL_0_:67 FC_0_:57 RW_000:80 nEXP_SPACE:14 BERR:41* -NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* -NOTE PINS CLK_DIV_OUT:65 DTACK:30 AVEC:92 AVEC_EXP:22 VPA:36* -NOTE PINS RST:86 RW:71 AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48* -NOTE PINS AMIGA_BUS_ENABLE_LOW:20 CIIN:47 A_30_:5 A_29_:6* -NOTE PINS A_28_:15 A_27_:16 A_26_:17 A_25_:18 A_24_:19 A_23_:84* -NOTE PINS SIZE_1_:79 IPL_030_2_:9 IPL_030_1_:7 IPL_030_0_:8* -NOTE PINS AS_030:82 AS_000:33 DS_030:98 UDS_000:32 LDS_000:31* -NOTE PINS A0:69 BG_000:29 BGACK_030:83 CLK_EXP:10 FPU_CS:78* -NOTE PINS DSACK1:81 E:66 VMA:35 RESET:3 SIZE_0_:70 * +NOTE PINS A_31_:4 IPL_2_:68 FC_1_:58 A_30_:5 A_29_:6 UDS_000:32* +NOTE PINS A_28_:15 LDS_000:31 A_27_:16 A_26_:17 nEXP_SPACE:14* +NOTE PINS A_25_:18 BERR:41 A_24_:19 BG_030:21 A_23_:84 A_22_:85* +NOTE PINS A_21_:94 BGACK_000:28 A_20_:93 CLK_030:64 A_19_:97* +NOTE PINS CLK_000:11 A_18_:95 CLK_OSZI:61 A_17_:59 CLK_DIV_OUT:65* +NOTE PINS A_16_:96 FPU_CS:78 IPL_1_:56 DTACK:30 IPL_0_:67* +NOTE PINS AVEC:92 FC_0_:57 VPA:36 RST:86 AMIGA_BUS_DATA_DIR:48* +NOTE PINS CIIN:47 SIZE_1_:79 IPL_030_2_:9 AS_030:82 AS_000:33* +NOTE PINS SIZE_0_:70 RW_000:80 DS_030:98 A0:69 BG_000:29* +NOTE PINS BGACK_030:83 CLK_EXP:10 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS DSACK1:81 AVEC_EXP:22 E:66 VMA:35 RESET:3 RW:71* +NOTE PINS AMIGA_BUS_ENABLE:34 AMIGA_BUS_ENABLE_LOW:20 * NOTE Table of node names and numbers* -NOTE NODES RN_RW_000:269 RN_DTACK:173 RN_RW:245 RN_SIZE_1_:271 * -NOTE NODES RN_IPL_030_2_:128 RN_IPL_030_1_:134 RN_IPL_030_0_:131 * -NOTE NODES RN_AS_030:278 RN_AS_000:179 RN_DS_030:101 RN_UDS_000:182 * -NOTE NODES RN_LDS_000:185 RN_A0:257 RN_BG_000:176 RN_BGACK_030:275 * -NOTE NODES RN_FPU_CS:272 RN_DSACK1:281 RN_E:248 RN_VMA:175 * -NOTE NODES RN_SIZE_0_:247 inst_avec_expreg:251 inst_AS_030_000_SYNC:280 * -NOTE NODES inst_BGACK_030_INT_D:139 inst_VPA_D:106 inst_CLK_OUT_PRE_50_D:287 * -NOTE NODES inst_CLK_000_D0:274 inst_CLK_000_D1:181 inst_DTACK_D0:137 * -NOTE NODES inst_CLK_OUT_PRE_50:286 inst_CLK_OUT_PRE_25:136 * -NOTE NODES SM_AMIGA_1_:130 SM_AMIGA_6_:254 SM_AMIGA_0_:283 * -NOTE NODES SM_AMIGA_7_:277 inst_RW_000_INT:253 inst_CLK_000_D2:284 * -NOTE NODES inst_CLK_030_H:133 SM_AMIGA_5_:190 SM_AMIGA_4_:109 * -NOTE NODES SM_AMIGA_3_:107 SM_AMIGA_2_:103 cpu_est_0_:188 * -NOTE NODES cpu_est_1_:184 cpu_est_2_:187 * +NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_DTACK:173 RN_SIZE_1_:271 * +NOTE NODES RN_IPL_030_2_:131 RN_AS_030:278 RN_AS_000:179 * +NOTE NODES RN_SIZE_0_:263 RN_RW_000:269 RN_DS_030:101 RN_A0:257 * +NOTE NODES RN_BG_000:193 RN_BGACK_030:277 RN_IPL_030_1_:143 * +NOTE NODES RN_IPL_030_0_:137 RN_DSACK1:287 RN_AVEC_EXP:155 * +NOTE NODES RN_E:251 RN_VMA:175 RN_RW:245 RN_AMIGA_BUS_ENABLE:181 * +NOTE NODES RN_AMIGA_BUS_ENABLE_LOW:167 inst_AS_030_000_SYNC:275 * +NOTE NODES inst_BGACK_030_INT_D:284 inst_VPA_D:248 inst_CLK_OUT_PRE_50_D:289 * +NOTE NODES inst_CLK_OUT_PRE:140 inst_CLK_000_D0:221 inst_CLK_000_D1:283 * +NOTE NODES inst_CLK_OUT_PRE_50:209 inst_CLK_OUT_PRE_25:151 * +NOTE NODES inst_CLK_000_D2:187 inst_CLK_000_D3:211 inst_CLK_000_NE:113 * +NOTE NODES inst_CLK_OUT_PRE_D:161 CLK_000_P_SYNC_9_:134 * +NOTE NODES CLK_000_N_SYNC_11_:116 SM_AMIGA_7_:176 SM_AMIGA_6_:253 * +NOTE NODES SM_AMIGA_1_:233 SM_AMIGA_0_:182 SM_AMIGA_4_:139 * +NOTE NODES inst_CLK_030_H:119 inst_LDS_000_INT:163 inst_DS_000_ENABLE:133 * +NOTE NODES inst_UDS_000_INT:157 CLK_000_N_SYNC_0_:230 CLK_000_N_SYNC_1_:110 * +NOTE NODES CLK_000_N_SYNC_2_:205 CLK_000_N_SYNC_3_:170 CLK_000_N_SYNC_4_:104 * +NOTE NODES CLK_000_N_SYNC_5_:121 CLK_000_N_SYNC_6_:224 CLK_000_N_SYNC_7_:199 * +NOTE NODES CLK_000_N_SYNC_8_:164 CLK_000_N_SYNC_9_:241 CLK_000_N_SYNC_10_:115 * +NOTE NODES CLK_000_P_SYNC_0_:235 CLK_000_P_SYNC_1_:128 CLK_000_P_SYNC_2_:158 * +NOTE NODES CLK_000_P_SYNC_3_:109 CLK_000_P_SYNC_4_:254 CLK_000_P_SYNC_5_:152 * +NOTE NODES CLK_000_P_SYNC_6_:169 CLK_000_P_SYNC_7_:103 CLK_000_P_SYNC_8_:229 * +NOTE NODES SM_AMIGA_5_:145 SM_AMIGA_3_:239 SM_AMIGA_2_:223 * +NOTE NODES cpu_est_0_:227 cpu_est_1_:259 cpu_est_2_:265 * NOTE BLOCK 0 * L000000 - 111111111011111111111111111111111111111111111111111111111111111111 + 111111111011100111111101111111111111111111111111111111111111111111 111111111101111111111111111111111111111111111111111111111111111111 - 111111111111111101111111111111111111111111111111111111110111111111 - 111111111111111111111111111111111111111111111110111111111111111111 + 111011111111111111011111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111111111101111111111110111111111111111111111011111111111111111 - 110101111111110111111110011111111111111110101111110101111111111111 - 101111111111111111010111111111011101111111111111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111101111111111111011111111111111111111111111111111111 + 111101111111111111111111111111111111111111111111011111111011111111 + 111111111111111111111111011011111111111111101101111111111111111111 + 101111111111111111111111111111111111111111110111111111111101111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111111111111111111111111111111111111101111111111111111111111111* -L000726 111111111111111111111111111111111111111111111111111101111111111111* +L000660 111111111111111111111111110111111111111111111111111111111111111111* +L000726 111111111111111111111111111111111111111111111101111111111111111111* L000792 111111111111111111111111011111111111111111111111011111111111111111* -L000858 111111111011111111111111111111111111111111011111111111110111111111* -L000924 111111111111011111111111111111111111111111011111111111111111111111* -L000990 110111111111110110111110111111111111111111111111110111111111111111* -L001056 111111111111111111011110111111111111111111111111111111111111111111* -L001122 110111111111110111111110111011111110111111111101111011111111111111* +L000858 111111111011111111111111111111011111111111011111111111111111111111* +L000924 111111111111111111111111111111111111111111011111111111110111111111* +L000990 111111111111111111111101111111111111111111111111111111111111111111* +L001056 111111110111111111111111111111111111111111111111111111111001111111* +L001122 111111111111111111111111111111101111111111111111111111111001111111* L001188 000000000000000000000000000000000000000000000000000000000000000000* L001254 000000000000000000000000000000000000000000000000000000000000000000* L001320 111111111111111111111111111111111111111111111111111111111111111111* -L001386 111111111111111111111111111111111111111111111111111111111111111111* -L001452 111111110111101111111111111111011111111111111111111111111111111111* -L001518 111111111111101111111111111111011111111111111111111111111011111111* -L001584 000000000000000000000000000000000000000000000000000000000000000000* -L001650 000000000000000000000000000000000000000000000000000000000000000000* -L001716 111111111111111111110111111111111111111111111111111111111111111111* -L001782 000000000000000000000000000000000000000000000000000000000000000000* -L001848 000000000000000000000000000000000000000000000000000000000000000000* -L001914 000000000000000000000000000000000000000000000000000000000000000000* -L001980 000000000000000000000000000000000000000000000000000000000000000000* +L001386 111111111111110111111111111111111111111111111111111111111111111111* +L001452 111111111111111111111111111111111111111111111111111111111111111111* +L001518 111111111111111111111111111111111111111111111111111111111111111111* +L001584 111111111111111111111111111111111111111111111111111111111111111111* +L001650 111111111111111111111111111111111111111111111111111111111111111111* +L001716 111111111111111111111111111111111111111111111111111111111111111111* +L001782 111111111111111111111111111111111111111111111111111111111111111111* +L001848 111111111111111111111111111111111111111111111111111111111111111111* +L001914 111111111111111111111111111111111111111111111111111111111111111111* +L001980 111111111111111111111111111111111111111111111111111111111111111111* L002046 000000000000000000000000000000000000000000000000000000000000000000* -L002112 111111111111110110111110111111111111111111111111110111111111111111* -L002178 111011111111111111111110111111111111111111111111111111111111111111* -L002244 111010111111111111111111111111111111111111111111111111111111111111* -L002310 111111111111110111111110111011111110111111111101111011111111111111* -L002376 000000000000000000000000000000000000000000000000000000000000000000* -L002442 111111011111111111111110111111111111111111111111111111111111111111* -L002508 111101111111111111111110111111111111111111111111111111111111111111* -L002574 000000000000000000000000000000000000000000000000000000000000000000* -L002640 000000000000000000000000000000000000000000000000000000000000000000* -L002706 000000000000000000000000000000000000000000000000000000000000000000* +L002112 111111111111111111111111111111111111111111111111111111111111111111* +L002178 111111111111111111111111111111111111111111111111111111111111111111* +L002244 111111111111111111111111111111111111111111111111111111111111111111* +L002310 111111111111111111111111111111111111111111111111111111111111111111* +L002376 111111111111111111111111111111111111111111111111111111111111111111* +L002442 111111111111111111011111111111111111111111111111111111111111111111* +L002508 111111111111111111111111111111111111111111111111111111111111111111* +L002574 111111111111111111111111111111111111111111111111111111111111111111* +L002640 111111111111111111111111111111111111111111111111111111111111111111* +L002706 111111111111111111111111111111111111111111111111111111111111111111* L002772 000000000000000000000000000000000000000000000000000000000000000000* -L002838 111111111111111111111111111111111111111111111111111111111111111111* +L002838 110111111111111111111111111111111111111111111111111111111111111111* L002904 111111111111111111111111111111111111111111111111111111111111111111* L002970 111111111111111111111111111111111111111111111111111111111111111111* L003036 111111111111111111111111111111111111111111111111111111111111111111* @@ -119,19 +129,19 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111111111111111111111111111111111111111111111111111111111111111111* +L003564 111111111111111101111111111111111111111111111111111111111111111111* L003630 111111111111111111111111111111111111111111111111111111111111111111* L003696 111111111111111111111111111111111111111111111111111111111111111111* L003762 111111111111111111111111111111111111111111111111111111111111111111* L003828 111111111111111111111111111111111111111111111111111111111111111111* -L003894 111111111111111111111111111111111111111111111111111111111111111111* +L003894 111111111111011111111111111111111111111111111111111111111111111111* L003960 111111111111111111111111111111111111111111111111111111111111111111* L004026 111111111111111111111111111111111111111111111111111111111111111111* L004092 111111111111111111111111111111111111111111111111111111111111111111* L004158 111111111111111111111111111111111111111111111111111111111111111111* L004224 000000000000000000000000000000000000000000000000000000000000000000* -L004290 111111111111111111111111111111111111111111111111111111111111111111* +L004290 111101111111111111111111111111111111111111111111111111111111111111* L004356 111111111111111111111111111111111111111111111111111111111111111111* L004422 111111111111111111111111111111111111111111111111111111111111111111* L004488 111111111111111111111111111111111111111111111111111111111111111111* @@ -143,18 +153,18 @@ L004818 111111111111111111111111111111111111111111111111111111111111111111* L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111111111111111111111111111111111111111111111111111111111111111* -L005082 111111111111111111111111111111111111111111111111111111111111111111* -L005148 111111111111111111111111111111111111111111111111111111111111111111* -L005214 111111111111111111111111111111111111111111111111111111111111111111* -L005280 111111111111111111111111111111111111111111111111111111111111111111* -L005346 111111111111111111111111111111111111111111111111111111111111111111* +L005016 101111111111111111111111111111011111111111111111111111111111111111* +L005082 011111110111111111111111101011111111111111101110111111111111111111* +L005148 111111111111111111111111101011011111111111111110111111111111111111* +L005214 011111110111111111111111111011111111111111101110101111111111111111* +L005280 111111111111111111111111111011011111111111111110101111111111111111* +L005346 111111111111111111111111111111111111111111110111111111111111111111* L005412 111111111111111111111111111111111111111111111111111111111111111111* L005478 111111111111111111111111111111111111111111111111111111111111111111* L005544 111111111111111111111111111111111111111111111111111111111111111111* L005610 111111111111111111111111111111111111111111111111111111111111111111* L005676 - 111111111110111111111111111111111111111110101111111111111111111111* + 111111111110111111111111111011111111111111101111111111111111111111* L005742 111111111111111111111111111111111111111111111111111111111111111111* L005808 111111111111111111111111111111111111111111111111111111111111111111* L005874 111111111111111111111111111111111111111111111111111111111111111111* @@ -170,35 +180,35 @@ L006402 101111111111111111111111111111111111111111111111111111111111111111* L006534 0010* L006538 10100110011000* -L006552 10100100011110* -L006566 00001111110000* -L006580 00100110011111* -L006594 11100100010000* -L006608 10100100010010* -L006622 11011011110000* -L006636 11110011110011* -L006650 11111111110001* -L006664 11110011110011* -L006678 11111011110000* -L006692 11111111110010* -L006706 11110011110001* -L006720 11111011110011* -L006734 11110111110100* -L006748 11111111110011* +L006552 00110100011110* +L006566 00010100010100* +L006580 11100011111111* +L006594 00111111111001* +L006608 00000100010011* +L006622 00010100010000* +L006636 11100011110011* +L006650 00110100010000* +L006664 00000100010010* +L006678 00010100010000* +L006692 11101111110011* +L006706 10100110010001* +L006720 00000100010011* +L006734 11010011110100* +L006748 11111011110011* NOTE BLOCK 1 * L006762 - 111111111111111111111111111111111111111110111111111111111111111111 + 111111111111111111110111011111111111111111111111111111111111111111 + 111011111111011111111111111111111111111111111111111011111111111111 + 111111101011110101101111111111111111111111111111111111110111111111 + 101111111111111111111111111101111111111111111111111111011111111110 + 111111111110111111111111111111111111111111110111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111101101011111111111111111111111111111111111111011111110111111111 - 111111111101111111110111111111111011111111111111111111011111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111011111111111110111111111111111111111111111111111111111111111111 - 011111111111111111111111111101111111111111111111111111111111111111 - 111111111111110111111110011111111111111111111110111101111111101111 - 111111111111111111011111111111111111111111101111111111111111111111* + 111111111111111111111110111111111111011111111111111111111111111111 + 111111111111111111111111111111111111111011111111111111111111111111 + 111111111111111111111111111111111111111111101111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* -L007422 111111111111111111111111111111111111111111111111011111111111111111* +L007422 111111111111110111111111111111111111111111111111111111111111111111* L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* @@ -210,55 +220,55 @@ L007950 000000000000000000000000000000000000000000000000000000000000000000* L008016 000000000000000000000000000000000000000000000000000000000000000000* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 111111110111111011111101111111111111111111111111111111111111111111* -L008214 111111111111111111110110111111111111111111111111111111111111111111* -L008280 111111111111110111110111111111111111111111111111111111111111111111* -L008346 000000000000000000000000000000000000000000000000000000000000000000* -L008412 000000000000000000000000000000000000000000000000000000000000000000* -L008478 111111111101111111111101111111111111111111111111111111111111111111* -L008544 111111111111111111011101111111111111111111111111111111111111111111* -L008610 000000000000000000000000000000000000000000000000000000000000000000* -L008676 000000000000000000000000000000000000000000000000000000000000000000* -L008742 000000000000000000000000000000000000000000000000000000000000000000* +L008148 110111111111111111111111111111111111111111111111111111111111111111* +L008214 111111111111111111111111111111111111111111111111111111111111111111* +L008280 111111111111111111111111111111111111111111111111111111111111111111* +L008346 111111111111111111111111111111111111111111111111111111111111111111* +L008412 111111111111111111111111111111111111111111111111111111111111111111* +L008478 111111111111111111111111111111111111111111111111111111111111111111* +L008544 111111111111111111111111111111111111111111111111111111111111111111* +L008610 111111111111111111111111111111111111111111111111111111111111111111* +L008676 111111111111111111111111111111111111111111111111111111111111111111* +L008742 111111111111111111111111111111111111111111111111111111111111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111111111111111011111101111111110111111111111111111111111111111111* -L008940 111111111111111111111110111111111111111111111111111111011111111111* -L009006 111111111111110111111111111111111111111111111111111111011111111111* +L008874 111111110101111111111110111111111111111111111111111111111111111111* +L008940 111111111110111111111111111111111111111111111111111111011111111111* +L009006 111111111111111111111101111111111111111111111111111111011111111111* L009072 000000000000000000000000000000000000000000000000000000000000000000* L009138 000000000000000000000000000000000000000000000000000000000000000000* -L009204 111111111111111111111111111111111111111111101111111111110111111111* -L009270 111111111111111111111111101111111111111101011110111110111111101111* -L009336 111111111111111111111111101111111111111111111110111110110111111111* -L009402 101111111111111111111111111111111111111101011110111110111111101111* -L009468 101111111111111111111111111111111111111111111110111110110111111111* +L009204 111111111111011111111111111101111111111111111111111111111111111111* +L009270 111111111111111111111111111111111111111011111111111111110111111111* +L009336 111111111111111111111111111101111111111111111111110111111111111101* +L009402 000000000000000000000000000000000000000000000000000000000000000000* +L009468 000000000000000000000000000000000000000000000000000000000000000000* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111011111111011111101111111111111111111111111111111111111111111* -L009666 111101111111111111111110111111111111111111111111111111111111111111* -L009732 111101111111110111111111111111111111111111111111111111111111111111* -L009798 000000000000000000000000000000000000000000000000000000000000000000* -L009864 000000000000000000000000000000000000000000000000000000000000000000* -L009930 111111111111111101111111111111111111111111111111011111111111111111* -L009996 111011111111111111111111111111111111111111111111011111111111111111* -L010062 110111111111111110111111111111111111111111111111101111111111111111* -L010128 000000000000000000000000000000000000000000000000000000000000000000* -L010194 000000000000000000000000000000000000000000000000000000000000000000* +L009600 111111111111111111011111111111111111111111111111111111111111111111* +L009666 111111111111111111111111111111111111111111111111111111111111111111* +L009732 111111111111111111111111111111111111111111111111111111111111111111* +L009798 111111111111111111111111111111111111111111111111111111111111111111* +L009864 111111111111111111111111111111111111111111111111111111111111111111* +L009930 111111111111111111111111111111111111111111111111111111111111111111* +L009996 111111111111111111111111111111111111111111111111111111111111111111* +L010062 111111111111111111111111111111111111111111111111111111111111111111* +L010128 111111111111111111111111111111111111111111111111111111111111111111* +L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 000000000000000000000000000000000000000000000000000000000000000000* -L010326 111111111111111111111111111101111111111111111111111111111111111111* -L010392 000000000000000000000000000000000000000000000000000000000000000000* -L010458 000000000000000000000000000000000000000000000000000000000000000000* +L010326 011111111101111111111110111111111111111111111111111111111111111111* +L010392 111111111110111101111111111111111111111111111111111111111111111111* +L010458 111111111111111101111101111111111111111111111111111111111111111111* L010524 000000000000000000000000000000000000000000000000000000000000000000* L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 111111111111111111111111111111111111111111111101111111111111111111* -L010722 111111111111111111111111111111111111111111111111111111111111111111* -L010788 111111111111111111111111111111111111111111111111111111111111111111* -L010854 111111111111111111111111111111111111111111111111111111111111111111* -L010920 111111111111111111111111111111111111111111111111111111111111111111* +L010656 111111111111011111111111111110111111111111111111111111111111111111* +L010722 111111111111111111110111111111111111011111111111111111111111111111* +L010788 000000000000000000000000000000000000000000000000000000000000000000* +L010854 000000000000000000000000000000000000000000000000000000000000000000* +L010920 000000000000000000000000000000000000000000000000000000000000000000* L010986 000000000000000000000000000000000000000000000000000000000000000000* -L011052 111111111111111111111111111111111111111111111111111111111111111111* +L011052 111111111111111111111111111111111111111111110111111111111111111111* L011118 111111111111111111111111111111111111111111111111111111111111111111* L011184 111111111111111111111111111111111111111111111111111111111111111111* L011250 111111111111111111111111111111111111111111111111111111111111111111* @@ -270,16 +280,16 @@ L011580 111111111111111111111111111111111111111111111111111111111111111111* L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 000000000000000000000000000000000000000000000000000000000000000000* -L011778 111111111111111111111111111111111111111111111111111111111111111111* -L011844 111111111111111111111111111111111111111111111111111111111111111111* -L011910 111111111111111111111111111111111111111111111111111111111111111111* -L011976 111111111111111111111111111111111111111111111111111111111111111111* -L012042 111111111111111111111111111111111111111111111111111111111111111111* -L012108 111111111111111111111111111111111111111111111111111111111111111111* -L012174 111111111111111111111111111111111111111111111111111111111111111111* -L012240 111111111111111111111111111111111111111111111111111111111111111111* -L012306 111111111111111111111111111111111111111111111111111111111111111111* -L012372 111111111111111111111111111111111111111111111111111111111111111111* +L011778 111111011101111111111110111111111111111111111111111111111111111111* +L011844 111111111110111111111111011111111111111111111111111111111111111111* +L011910 111111111111111111111101011111111111111111111111111111111111111111* +L011976 000000000000000000000000000000000000000000000000000000000000000000* +L012042 000000000000000000000000000000000000000000000000000000000000000000* +L012108 111111111111111111111111111101111111111111111111111111111111111101* +L012174 111111111111111111110111111111111111101111111111111111111111111111* +L012240 000000000000000000000000000000000000000000000000000000000000000000* +L012306 000000000000000000000000000000000000000000000000000000000000000000* +L012372 000000000000000000000000000000000000000000000000000000000000000000* L012438 111111111111111111111111111111111111111111111111111111111111111111* L012504 111111111111111111111111111111111111111111111111111111111111111111* @@ -298,46 +308,46 @@ L013164 L013296 0010* L013300 00100100010000* L013314 00100100011110* -L013328 10100110010000* -L013342 10100100011111* -L013356 10100110010001* -L013370 10100110011111* -L013384 10100110010000* -L013398 10100100011110* -L013412 00100110010000* -L013426 00010110010011* -L013440 11011111110001* -L013454 11110011110011* -L013468 11111011110000* -L013482 11111111110010* -L013496 11110011111100* -L013510 11111011111111* +L013328 00010100010100* +L013342 11100011111111* +L013356 10100110010011* +L013370 10100100011111* +L013384 00010100010110* +L013398 11101111111111* +L013412 10100110011001* +L013426 10100100010011* +L013440 00010100010000* +L013454 11101011110010* +L013468 10100110011000* +L013482 10100100010011* +L013496 11011111111100* +L013510 11110011111110* NOTE BLOCK 2 * L013524 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111110111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 111101111111111111111111110110111111111111111111111111111111111111 + 111111111111111111111101111111110111101111111110111111111111111111 + 111111111111111111110111111111011111111111110111111111111111111111 + 110111111111111111111111011111111111111111111111111111111111111111 + 111111111111101011111111111111111111111111111111111111111111111111 + 111111111111111110111111111111111111111111111111111111111111111111 + 111111101111111111111111111111111111111111111111111111111111111111 + 101111111110111111111111111111111111111111111111111111111111111111* L014118 000000000000000000000000000000000000000000000000000000000000000000* -L014184 111101111111111111111111111111111111111111111111111111111111111111* -L014250 000000000000000000000000000000000000000000000000000000000000000000* -L014316 000000000000000000000000000000000000000000000000000000000000000000* -L014382 000000000000000000000000000000000000000000000000000000000000000000* -L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 111111111111111111111111111111111111111111111111111111111111111111* -L014580 111111111111111111111111111111111111111111111111111111111111111111* -L014646 111111111111111111111111111111111111111111111111111111111111111111* -L014712 111111111111111111111111111111111111111111111111111111111111111111* -L014778 111111111111111111111111111111111111111111111111111111111111111111* +L014184 111111111111111111111111111111111111111111111111111111111111111111* +L014250 111111111111111111111111111111111111111111111111111111111111111111* +L014316 111111111111111111111111111111111111111111111111111111111111111111* +L014382 111111111111111111111111111111111111111111111111111111111111111111* +L014448 111111111111111111111111111111111111111111111111111111111111111111* +L014514 110111111111110111111111111111111111111111111111111111111111111111* +L014580 110111111111111110111111111111111111111111111111111111111111111111* +L014646 111011111111111001111111111111111111111111111111111111111111111111* +L014712 000000000000000000000000000000000000000000000000000000000000000000* +L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 000000000000000000000000000000000000000000000000000000000000000000* -L014910 111111111111111111111111111111111111111111111111111111111111111111* +L014910 111111111111111111111111111111111111111111111101111111111111111111* L014976 111111111111111111111111111111111111111111111111111111111111111111* L015042 111111111111111111111111111111111111111111111111111111111111111111* L015108 111111111111111111111111111111111111111111111111111111111111111111* @@ -349,19 +359,19 @@ L015438 111111111111111111111111111111111111111111111111111111111111111111* L015504 111111111111111111111111111111111111111111111111111111111111111111* L015570 000000000000000000000000000000000000000000000000000000000000000000* -L015636 111111111111111111111111111111111111111111111111111111111111111111* +L015636 111111111111111111111101111111111111111111111111111111111111111111* L015702 111111111111111111111111111111111111111111111111111111111111111111* L015768 111111111111111111111111111111111111111111111111111111111111111111* L015834 111111111111111111111111111111111111111111111111111111111111111111* L015900 111111111111111111111111111111111111111111111111111111111111111111* -L015966 111111111111111111111111111111111111111111111111111111111111111111* -L016032 111111111111111111111111111111111111111111111111111111111111111111* -L016098 111111111111111111111111111111111111111111111111111111111111111111* -L016164 111111111111111111111111111111111111111111111111111111111111111111* -L016230 111111111111111111111111111111111111111111111111111111111111111111* +L015966 111111111111111111111111011111011111111111111111111111111111111111* +L016032 111111111111111111111111101111111111011111111111111111111111111111* +L016098 000000000000000000000000000000000000000000000000000000000000000000* +L016164 000000000000000000000000000000000000000000000000000000000000000000* +L016230 000000000000000000000000000000000000000000000000000000000000000000* L016296 000000000000000000000000000000000000000000000000000000000000000000* -L016362 111111111111111111111111111111111111111111111111111111111111111111* +L016362 111111111111111111110111111111111111111111111111111111111111111111* L016428 111111111111111111111111111111111111111111111111111111111111111111* L016494 111111111111111111111111111111111111111111111111111111111111111111* L016560 111111111111111111111111111111111111111111111111111111111111111111* @@ -373,19 +383,19 @@ L016890 111111111111111111111111111111111111111111111111111111111111111111* L016956 111111111111111111111111111111111111111111111111111111111111111111* L017022 000000000000000000000000000000000000000000000000000000000000000000* -L017088 111111111111111111111111111111111111111111111111111111111111111111* +L017088 111101111111111111111111111111111111111111111111111111111111111111* L017154 111111111111111111111111111111111111111111111111111111111111111111* L017220 111111111111111111111111111111111111111111111111111111111111111111* L017286 111111111111111111111111111111111111111111111111111111111111111111* L017352 111111111111111111111111111111111111111111111111111111111111111111* -L017418 111111111111111111111111111111111111111111111111111111111111111111* -L017484 111111111111111111111111111111111111111111111111111111111111111111* -L017550 111111111111111111111111111111111111111111111111111111111111111111* -L017616 111111111111111111111111111111111111111111111111111111111111111111* -L017682 111111111111111111111111111111111111111111111111111111111111111111* +L017418 111111111111111111111111010111111111111111111111111111111111111111* +L017484 111111111111101111111111101101111111101111111111111111111111111111* +L017550 000000000000000000000000000000000000000000000000000000000000000000* +L017616 000000000000000000000000000000000000000000000000000000000000000000* +L017682 000000000000000000000000000000000000000000000000000000000000000000* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 111111111111111111111111111111111111111111111111111111111111111111* +L017814 111111111101111111111111111111111111111111111111111111111111111111* L017880 111111111111111111111111111111111111111111111111111111111111111111* L017946 111111111111111111111111111111111111111111111111111111111111111111* L018012 111111111111111111111111111111111111111111111111111111111111111111* @@ -397,19 +407,19 @@ L018342 111111111111111111111111111111111111111111111111111111111111111111* L018408 111111111111111111111111111111111111111111111111111111111111111111* L018474 000000000000000000000000000000000000000000000000000000000000000000* -L018540 111111111111111111111111111111111111111111111111111111111111111111* +L018540 111110111111111111111111111111110111111111111111111111111111111111* L018606 111111111111111111111111111111111111111111111111111111111111111111* L018672 111111111111111111111111111111111111111111111111111111111111111111* L018738 111111111111111111111111111111111111111111111111111111111111111111* L018804 111111111111111111111111111111111111111111111111111111111111111111* -L018870 111111111111111111111111111111111111111111111111111111111111111111* +L018870 111111111111111111111111111111111111111111110111111111111111111111* L018936 111111111111111111111111111111111111111111111111111111111111111111* L019002 111111111111111111111111111111111111111111111111111111111111111111* L019068 111111111111111111111111111111111111111111111111111111111111111111* L019134 111111111111111111111111111111111111111111111111111111111111111111* L019200 111111111111111111111111111111111111111111111111111111111111111111* -L019266 111111111111111111111111111111111111111111111111111111111111111111* +L019266 111111011111111111111111111111111111111111111111111111111111111111* L019332 111111111111111111111111111111111111111111111111111111111111111111* L019398 111111111111111111111111111111111111111111111111111111111111111111* L019464 111111111111111111111111111111111111111111111111111111111111111111* @@ -420,117 +430,117 @@ L019728 111111111111111111111111111111111111111111111111111111111111111111* L019794 111111111111111111111111111111111111111111111111111111111111111111* L019860 111111111111111111111111111111111111111111111111111111111111111111* L019926 - 000000000000000000000000000000000000000000000000000000000000000000 + 101111111111111111111111111111111111111111111111111111111111111111 000000000000000000000000000000000000000000000000000000000000000000* -L020058 0000* -L020062 00100011111100* -L020076 00010111110011* -L020090 11010011110001* -L020104 11110111110011* -L020118 11110011110000* -L020132 11110111110011* -L020146 11110011110001* -L020160 11110111110011* -L020174 11110011110000* -L020188 11111011110011* -L020202 11110111111111* -L020216 11111111111111* -L020230 11110011110000* -L020244 11111011110011* -L020258 11110111110101* -L020272 11111111111111* +L020058 0010* +L020062 11100011110000* +L020076 10100110010011* +L020090 00000110010001* +L020104 11101011110011* +L020118 00110110011000* +L020132 10100100010010* +L020146 00010110010001* +L020160 11100011110011* +L020174 00110110010000* +L020188 10100100010010* +L020202 00010110010100* +L020216 11101111111111* +L020230 00110110011001* +L020244 00000110010011* +L020258 00010110010110* +L020272 11100011111111* NOTE BLOCK 3 * L020286 - 111111111111111111111111111111111111111111111111011111111111111111 - 111111111111111110111111111111011110111111110111111111111111111111 - 111111111111111111111111111111111111101111111110111111111111111111 - 111110111111111111111111111111111111111111111111111111111111111011 - 111111111101111111111111111111111111111111111111111111111111111111 - 111111111111101111111111111111111111110101111111111111111111111111 - 111111111111111111111111010111110111111111111111111111111111111110 - 101111111011111011101001111101111111111111111111110111111111011111 - 111111011111111111111111111111111111111111101111111111011111111111* + 111111111111111111101111111101111111111111111111111111111111111111 + 111111111111111111111111110111011111111111110111111111101111111111 + 111111111111111111111111111111111111111110111111111111111111110111 + 111111111111011111111110111111111111111111111110111111110110111110 + 111111111111111111111111111111111111111111111111111011111111111111 + 110111111111111111111111111111111111101111111111111111111111111111 + 111111111110111111111111011111111110111111111111111111111111011111 + 101111111011111011110111111111110111111011111111011111111111111111 + 111101011111111111111111111111111111111111101111111111111111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111111111111111111111111111111111111111111111111111111111111111101* +L020946 111111111111111111111111111111111101111111111111111111111111111111* L021012 000000000000000000000000000000000000000000000000000000000000000000* L021078 000000000000000000000000000000000000000000000000000000000000000000* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111111111111111111011111011111111111101111111111011011111111111* -L021342 111111111111111111111111111111111111111111111111111111011111111111* -L021408 111111111111111111110111010101111111111110111111111111101111111011* +L021276 111101111111111111111111111111111111111111111110111011101101111111* +L021342 111101111111111111111111111111111111111111111111111111111111111111* +L021408 111110111111111111010110111111111111111111111111110111011110111111* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111101111111111111111111111111111111111111011111111111111111111* -L021738 111111110111111111011111111111011111111111111011011111111111111111* -L021804 000000000000000000000000000000000000000000000000000000000000000000* -L021870 000000000000000000000000000000000000000000000000000000000000000000* +L021672 101111111110101111111111011111011111111111111111111111111111111111* +L021738 111111101111101111111111111111111111111111111111111111111111111111* +L021804 101111111110111111111111011111011011111111111111111111111111111111* +L021870 111111101111111111111111111111111011111111111111111111111111111111* L021936 000000000000000000000000000000000000000000000000000000000000000000* -L022002 111101111111111111111111111111111111111111111111111111111111111111* -L022068 000000000000000000000000000000000000000000000000000000000000000000* -L022134 000000000000000000000000000000000000000000000000000000000000000000* -L022200 000000000000000000000000000000000000000000000000000000000000000000* -L022266 000000000000000000000000000000000000000000000000000000000000000000* +L022002 111111111111111111111111111111111111111111111111111111111111111111* +L022068 111111111111111111111111111111111111111111111111111111111111111111* +L022134 111111111111111111111111111111111111111111111111111111111111111111* +L022200 111111111111111111111111111111111111111111111111111111111111111111* +L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 - 011111111111111111111111111111111111111111111111111111111111111111* -L022398 111111111111111111110111111111111111111111111101111111111111111111* -L022464 111111111111111111101111111110111111111111111111111111111111111111* + 111111110111111111111111111111111111111111111111111111111111111111* +L022398 111111111111011111111111111111111111111111111111111111111111111101* +L022464 111111111111111111111011111111111111111011111111111111111111111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* -L022728 111111111111111111110111111111111111111111111111111111111111111111* -L022794 111111111101111111101111111111111111111111111111111111111111101111* -L022860 111111111111111101101011111111111111111111111111111111111111101111* -L022926 111111111111111101101111111111111111111111111110111111111111101111* -L022992 111111111110111101110111111111111111101111111101111111111111111111* +L022728 111111111011111111111111111111111111111111111111111111111111111111* +L022794 111111101111111111111111111111111011011111111111101111111111101111* +L022860 101111011110111111111111011111011011011110111111111111111111111111* +L022926 111111101111111111111111111111111011011110111111101111111111111111* +L022992 111111111111111111111111111111111111011001111111101111111111111111* L023058 - 011111111111111111111111111111111111111111111111111111111111111111* -L023124 111111111111111110100111111111111111111111111111111111111111101111* -L023190 111111111111111110101111111111111111111011111111111111111111101111* -L023256 111111111110111110111011111111111111100111111111111111111111111111* + 111111110111111111111111111111111111111111111111111111111111111111* +L023124 111111111111101111111111111111110111111111111111111111111111111111* +L023190 111111111111111111111111111111111011111101111111111111111111011111* +L023256 000000000000000000000000000000000000000000000000000000000000000000* L023322 000000000000000000000000000000000000000000000000000000000000000000* L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 111111111111111111101011111111111011111011111111111111111111111111* -L023520 111111111101111111101111111111111011111111111111111111111111111111* -L023586 111111111111111101101011111111111011111111111111111111111111111111* -L023652 111111111111111101101111111111111011111111111110111111111111111111* -L023718 111111111110111101110111111111111110111111111101111111111111111111* +L023454 111111111111111111111111111111110111011011111111101111111111111111* +L023520 000000000000000000000000000000000000000000000000000000000000000000* +L023586 000000000000000000000000000000000000000000000000000000000000000000* +L023652 000000000000000000000000000000000000000000000000000000000000000000* +L023718 000000000000000000000000000000000000000000000000000000000000000000* L023784 - 011111111111111111111111111111111111111111111111111111111111111111* -L023850 111111111110011101110111111111111111111111111101111111111111111111* -L023916 111111111110111101110111111111111111011111111101111111111111111111* -L023982 111111111111111110100111111111111011111111111111111111111111111111* -L024048 111111111110111110111011111111111110110111111111111111111111111111* -L024114 111111111110011110111011111111111111110111111111111111111111111111* -L024180 111111111111111111111111011111111111111111111111111111111111111111* -L024246 111111111111111111110110101011111111111111111111111111111111111011* -L024312 111111111111111111110110011011111111111111111111111111111111110111* -L024378 111111111111111111110110101111111111111101111111111111111111110111* -L024444 111111111111111111110110011111111111111101111111111111111111111011* + 111111110111111111111111111111111111111111111111111111111111111111* +L023850 111111111111111111111111111111111111111111111111111111111011110111* +L023916 111111111111111111111111111111111111111111111111111111111111111111* +L023982 111111111111111111111111111111111111111111111111111111111111111111* +L024048 111111111111111111111111111111111111111111111111111111111111111111* +L024114 111111111111111111111111111111111111111111111111111111111111111111* +L024180 111111111101111111111111111111111111111111111111111111111111111111* +L024246 111111111111111111111111111111111111111111111111111111111111111111* +L024312 111111111111111111111111111111111111111111111111111111111111111111* +L024378 111111111111111111111111111111111111111111111111111111111111111111* +L024444 111111111111111111111111111111111111111111111111111111111111111111* L024510 - 101111111111111011111111111111101111111111111111111111111111111111* -L024576 111111111110111110111011111111111111010111111111111111111111111111* -L024642 000000000000000000000000000000000000000000000000000000000000000000* -L024708 000000000000000000000000000000000000000000000000000000000000000000* -L024774 000000000000000000000000000000000000000000000000000000000000000000* -L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 111111111111111111110110101111111111111101111111111111111111110111* -L024972 111111111111111111110110101011111111111110111111111111111111111111* -L025038 111111111111111111110110011011111111111101111111111111111111111011* -L025104 000000000000000000000000000000000000000000000000000000000000000000* -L025170 000000000000000000000000000000000000000000000000000000000000000000* + 111111111011111011111111111111101111111111111111111111111111111111* +L024576 111111111111111111111111111111111111111111111111111111111111111111* +L024642 111111111111111111111111111111111111111111111111111111111111111111* +L024708 111111111111111111111111111111111111111111111111111111111111111111* +L024774 111111111111111111111111111111111111111111111111111111111111111111* +L024840 111111111111111111111111111111111111111111111111111111111111111111* +L024906 111111111111111111111111111111111111111111111111111111111111111111* +L024972 111111111111111111111111111111111111111111111111111111111111111111* +L025038 111111111111111111111111111111111111111111111111111111111111111111* +L025104 111111111111111111111111111111111111111111111111111111111111111111* +L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111111111111011111111111111111101111111111111111111111111* -L025368 111111111111111111111101111111111111111101111111111111111111111111* -L025434 111111111111111111110110111111111111111110111111111111111111111111* -L025500 000000000000000000000000000000000000000000000000000000000000000000* -L025566 000000000000000000000000000000000000000000000000000000000000000000* -L025632 111111111111111111110111111111111111111111111101111111111111111111* -L025698 111111111111111111110111111111111111110111111111111111111111111111* +L025302 111111111111111111111111111011111111111111111111111111111111110111* +L025368 111111111111111111111111111111111111111111111111111111111111111111* +L025434 111111111111111111111111111111111111111111111111111111111111111111* +L025500 111111111111111111111111111111111111111111111111111111111111111111* +L025566 111111111111111111111111111111111111111111111111111111111111111111* +L025632 111011111111111111111111111111111111111111111011111111111111111111* +L025698 111111011111111111111111111101011111110111111011111111111111111111* L025764 000000000000000000000000000000000000000000000000000000000000000000* L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* @@ -552,46 +562,46 @@ L026688 L026820 0010* L026824 00100011111000* L026838 00100110011111* -L026852 11100110011001* -L026866 00101011111111* +L026852 11100110011101* +L026866 11101011111111* L026880 11100110010000* -L026894 00010110010010* -L026908 11100110010001* -L026922 10010101010011* -L026936 11100110010000* -L026950 00000100010010* -L026964 10000100010110* -L026978 10000100010011* -L026992 11001011110111* -L027006 11001111111111* -L027020 11110011110000* -L027034 11111011110010* +L026894 11100110010010* +L026908 10100100010101* +L026922 11000011110011* +L026936 01111111110010* +L026950 00000110010010* +L026964 11010011110110* +L026978 11111011110011* +L026992 01111111111001* +L027006 11100110011111* +L027020 11010011110000* +L027034 11111011110011* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 - 110111111111111111011111111111111111111111011111111011111111111111 - 111111110101111111111111011111111111111111111111111111111111111111 - 111111011111111111111111111111111101111111111111111111111111111111 + 110111111111111110111111111111111111111111011111111111110111111111 + 111111110111111111111111011101111110111111111111111111111111111111 + 111111011111111111011111111011101111111110111111111111111111111111 111111111111110111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 101111111111111111111111111111011111111111111101111111111101111111 - 111111111111111110111110111110111111111111111111111111111111111111* + 111111111111011111111111111111111111111111111111111111111111111101 + 111111111111111111110111111111111011111111111111110101111111110111 + 111111111101111111111111111111111111111011111101111111101101111111 + 101111111111111111111110111111111111101111111111111111111111111111* L027642 - 111111111111111111111111111110111111111111111111111111111111111111* -L027708 101111111111111111111111111111111111111111101110110111111111111111* -L027774 011111111111111111111111111111111111111111111111111011111111111111* + 111111111111101111111111110111111101111001111111111110111111111001* +L027708 111111111111111101111111111111111111111111101110111111101111111111* +L027774 111111111111111110111111111111111111111111111111111111011111111111* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 111111111111111101111101111111011111111111111111111111111101111111* -L028104 000000000000000000000000000000000000000000000000000000000000000000* -L028170 000000000000000000000000000000000000000000000000000000000000000000* -L028236 000000000000000000000000000000000000000000000000000000000000000000* -L028302 000000000000000000000000000000000000000000000000000000000000000000* +L028038 111111111111111111111111111111011111111111111111111111111111111111* +L028104 111111111111111111111111111111111111111111111111111111111111111111* +L028170 111111111111111111111111111111111111111111111111111111111111111111* +L028236 111111111111111111111111111111111111111111111111111111111111111111* +L028302 111111111111111111111111111111111111111111111111111111111111111111* L028368 000000000000000000000000000000000000000000000000000000000000000000* -L028434 000000000000000000000000000000000000000000000000000000000000000000* +L028434 111111111111111111111111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* L028632 111111111111111111111111111111111111111111111111111111111111111111* @@ -603,12 +613,12 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111111111111111111111111111111111111111111111111111111111111111* +L029160 000000000000000000000000000000000000000000000000000000000000000000* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 111111111111111111111111111111111111111111111111111111111111111111* +L029490 111111111111111111110111111111111111111111111111111111111111111111* L029556 111111111111111111111111111111111111111111111111111111111111111111* L029622 111111111111111111111111111111111111111111111111111111111111111111* L029688 111111111111111111111111111111111111111111111111111111111111111111* @@ -627,12 +637,12 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 111111111111111111111111111111111111111111111111111111111111111111* +L030612 111111111111111111111111111111111011111111111111111111111111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111111111111111111111111111111111111111111111111111111111111111111* +L030942 111111111111111111111111111111111111111111111111110111111111111111* L031008 111111111111111111111111111111111111111111111111111111111111111111* L031074 111111111111111111111111111111111111111111111111111111111111111111* L031140 111111111111111111111111111111111111111111111111111111111111111111* @@ -650,8 +660,8 @@ L031800 111111111111111111111111111111111111111111111111111111111111111111* L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 - 111011101010111011101111101111111110111111111111111111111111111111* -L032064 111111111111111111111111111111111111111111111111111111111111111111* + 111011101011111011101111101110111111111111111111111111111011111111* +L032064 111111111101111111111101111111111111011111111111111111111101111111* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* @@ -674,51 +684,51 @@ L033252 111111111111111111111111111111111111111111111111111111111111111111* L033318 111111111111111111111111111111111111111111111111111111111111111111* L033384 111111111111111111111111111111111111111111111111111111111111111111* L033450 - 000000000000000000000000000000000000000000000000000000000000000000 + 101111111111111111111111111111111111111111111111111111111111111111 000000000000000000000000000000000000000000000000000000000000000000* -L033582 0000* -L033586 10100011110100* -L033600 00100111111111* -L033614 00010011111001* -L033628 11010111111111* -L033642 11110011110000* -L033656 11110111111111* -L033670 11110011110001* -L033684 11110111111111* -L033698 11110011110000* -L033712 11111011111111* -L033726 11110111110001* -L033740 11111111111111* -L033754 11110011111010* -L033768 11111011111111* -L033782 11110111110101* +L033582 0010* +L033586 10100011110010* +L033600 00010110011111* +L033614 11010011110001* +L033628 11111111111111* +L033642 00111011111000* +L033656 00000110011111* +L033670 11011011110000* +L033684 11110011111110* +L033698 00110110010001* +L033712 00000100011111* +L033726 11010111110000* +L033740 11111111111110* +L033754 00110011110001* +L033768 11001011111111* +L033782 11110111110100* L033796 11111111111111* NOTE BLOCK 5 * L033810 + 111011011111111111111111111111111111111111111111111111111111111111 + 111111111111011101111111101111111111111111111111111111111111111111 + 111111111111111111111111111111111111111110111111111111111111111111 + 111111111011111111111110111110111111111111111111111111111101111111 + 111111111110111111111011111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111110111111111111111 + 111110111111110111111111111111111111011111111101111111101111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 101111111111111111011111111111111101111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111111111111111111111111111111111111111111111111111111111111111* -L034536 111111111111111111111111111111111111111111111111111111111111111111* -L034602 111111111111111111111111111111111111111111111111111111111111111111* -L034668 111111111111111111111111111111111111111111111111111111111111111111* -L034734 111111111111111111111111111111111111111111111111111111111111111111* -L034800 111111111111111111111111111111111111111111111111111111111111111111* -L034866 111111111111111111111111111111111111111111111111111111111111111111* -L034932 111111111111111111111111111111111111111111111111111111111111111111* -L034998 111111111111111111111111111111111111111111111111111111111111111111* -L035064 111111111111111111111111111111111111111111111111111111111111111111* +L034470 111111011111111111111111111111111111111111111111111111111111111111* +L034536 000000000000000000000000000000000000000000000000000000000000000000* +L034602 000000000000000000000000000000000000000000000000000000000000000000* +L034668 000000000000000000000000000000000000000000000000000000000000000000* +L034734 000000000000000000000000000000000000000000000000000000000000000000* +L034800 111111111111111111110111111111111111111111111111111111111110111111* +L034866 110111111011111111111101101111111110011111111111111111111111111111* +L034932 110111110111111111111111111111111111011111111110111111111111111111* +L034998 000000000000000000000000000000000000000000000000000000000000000000* +L035064 000000000000000000000000000000000000000000000000000000000000000000* L035130 000000000000000000000000000000000000000000000000000000000000000000* -L035196 111111111111111111111111111111111111111111111111111111111111111111* +L035196 111111111111111111111111111111111111111111111111110111111111111111* L035262 111111111111111111111111111111111111111111111111111111111111111111* L035328 111111111111111111111111111111111111111111111111111111111111111111* L035394 111111111111111111111111111111111111111111111111111111111111111111* @@ -730,19 +740,19 @@ L035724 111111111111111111111111111111111111111111111111111111111111111111* L035790 111111111111111111111111111111111111111111111111111111111111111111* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 111111111111111111111111111111111111111111111111111111111111111111* -L035988 111111111111111111111111111111111111111111111111111111111111111111* -L036054 111111111111111111111111111111111111111111111111111111111111111111* -L036120 111111111111111111111111111111111111111111111111111111111111111111* -L036186 111111111111111111111111111111111111111111111111111111111111111111* -L036252 111111111111111111111111111111111111111111111111111111111111111111* +L035922 111111111111111111111111111101111111111111111111111111111110111111* +L035988 111111111111111111111111111110111111111111111111111111111101111111* +L036054 000000000000000000000000000000000000000000000000000000000000000000* +L036120 000000000000000000000000000000000000000000000000000000000000000000* +L036186 000000000000000000000000000000000000000000000000000000000000000000* +L036252 111111111111111111011111111111111111111111111111111111111111111111* L036318 111111111111111111111111111111111111111111111111111111111111111111* L036384 111111111111111111111111111111111111111111111111111111111111111111* L036450 111111111111111111111111111111111111111111111111111111111111111111* L036516 111111111111111111111111111111111111111111111111111111111111111111* L036582 000000000000000000000000000000000000000000000000000000000000000000* -L036648 111111111111111111111111111111111111111111111111111111111111111111* +L036648 111101111110110111111111111111111111111111111111111111011111111111* L036714 111111111111111111111111111111111111111111111111111111111111111111* L036780 111111111111111111111111111111111111111111111111111111111111111111* L036846 111111111111111111111111111111111111111111111111111111111111111111* @@ -754,12 +764,12 @@ L037176 111111111111111111111111111111111111111111111111111111111111111111* L037242 111111111111111111111111111111111111111111111111111111111111111111* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 111111111111111111111111111111111111111111111111111111111111111111* -L037440 111111111111111111111111111111111111111111111111111111111111111111* -L037506 111111111111111111111111111111111111111111111111111111111111111111* -L037572 111111111111111111111111111111111111111111111111111111111111111111* -L037638 111111111111111111111111111111111111111111111111111111111111111111* -L037704 111111111111111111111111111111111111111111111111111111111111111111* +L037374 111111111111111111111111111111111111101101111111111111111111111111* +L037440 111111111111111111110111111111111111111111111111111111111101111111* +L037506 000000000000000000000000000000000000000000000000000000000000000000* +L037572 000000000000000000000000000000000000000000000000000000000000000000* +L037638 000000000000000000000000000000000000000000000000000000000000000000* +L037704 111110111101111011111111111111111111111111111111111111101111111111* L037770 111111111111111111111111111111111111111111111111111111111111111111* L037836 111111111111111111111111111111111111111111111111111111111111111111* L037902 111111111111111111111111111111111111111111111111111111111111111111* @@ -778,12 +788,12 @@ L038628 111111111111111111111111111111111111111111111111111111111111111111* L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 111111111111111111111111111111111111111111111111111111111111111111* -L038892 111111111111111111111111111111111111111111111111111111111111111111* -L038958 111111111111111111111111111111111111111111111111111111111111111111* -L039024 111111111111111111111111111111111111111111111111111111111111111111* -L039090 111111111111111111111111111111111111111111111111111111111111111111* -L039156 111111111111111111111111111111111111111111111111111111111111111111* +L038826 111011111111011111111111111111111111111111111111111111111101111111* +L038892 110111111011111111111101101111111110011111111111111111111110111111* +L038958 110111111011101111111101101111111110011111111111111111111111111111* +L039024 110111110111111111111111111111111111011111111110111111111110111111* +L039090 110111110111101111111111111111111111011111111110111111111111111111* +L039156 111111111111111101111111111111111111111111111111111111111111111111* L039222 111111111111111111111111111111111111111111111111111111111111111111* L039288 111111111111111111111111111111111111111111111111111111111111111111* L039354 111111111111111111111111111111111111111111111111111111111111111111* @@ -802,97 +812,97 @@ L040080 111111111111111111111111111111111111111111111111111111111111111111* L040146 111111111111111111111111111111111111111111111111111111111111111111* L040212 000000000000000000000000000000000000000000000000000000000000000000 - 000000000000000000000000000000000000000000000000000000000000000000* -L040344 0000* -L040348 11010011111110* -L040362 11110111111111* -L040376 11110011111111* -L040390 11110111110011* -L040404 11110011111110* -L040418 11110111110011* -L040432 11110011111111* -L040446 11110111110011* -L040460 11110011111110* -L040474 11111011110011* -L040488 11110111111111* -L040502 11111111111111* -L040516 11110011111110* -L040530 11111011111111* -L040544 11110111111111* -L040558 11111111111111* + 101111111111111111111111111111111111111111111111111111111111111111* +L040344 0010* +L040348 00100110011110* +L040362 10100100011110* +L040376 00010100011110* +L040390 11100011110011* +L040404 10100100011111* +L040418 00000100010011* +L040432 00010100011110* +L040446 11101111110011* +L040460 10100100011111* +L040474 00000100010011* +L040488 11011011111110* +L040502 11111111111110* +L040516 10100101011110* +L040530 00000100011111* +L040544 11010011111110* +L040558 11111011111110* NOTE BLOCK 6 * L040572 - 111111111011111111111111111111111111111111111111111111111111111111 - 111111111111011111111111111111011111111111111111111011111111111111 - 110111111111111111111111111111111111111111111110111111111111111111 - 111111101111111111111110110111111111111111111111111111111111111011 + 111111111011111111101111111111111111111111111111111111111111111111 + 111111111101111111111111101111111111111111111111111111111111111111 + 111111111111110111111111111111111111111111111111111111111111111111 + 111111111111011111111110111110111111111111111011111111111111111111 + 111111111111111111111111111111111110111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111101111111111111111111111111111111101111111111111111111111111111 - 011111111110110101111111111111111111111111111111111111111010111111 - 111111111111111111101011011111111111111110111111011101101111101111 - 111111111111111111111111111111111111111111101111111111111111111111* + 111111111111111111111111111111111111111111111111010111101011111111 + 111101111111111101111111111011111111111110101101111111111111111111 + 101111011111111111110111111111111111111111111111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 111111011111111111111111111111111111111111111111111111111111111111* -L041298 000000000000000000000000000000000000000000000000000000000000000000* -L041364 000000000000000000000000000000000000000000000000000000000000000000* -L041430 000000000000000000000000000000000000000000000000000000000000000000* +L041232 111111110111111110111111111011111110111111111110111111111111111111* +L041298 111111111011111110111111111011111111111111111110111111111011111111* +L041364 111111110111111111111111111011111110111111111110101111111111111111* +L041430 111111111011111111111111111011111111111111111110101111111011111111* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 101111111111111111111111101111111111111110111111111110111111111111* +L041562 111111111111110111111111111111111111111111111111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111111111111111111111111111111111111111111111111111111111111110111* -L042024 111111111111110101110111111111111111111111111111101111111111110111* -L042090 111111111111111010110111111111111111111111111111101111111111111011* -L042156 111101111111111011110111111111111111111111111111101111111111111011* -L042222 000000000000000000000000000000000000000000000000000000000000000000* -L042288 110111111111111111111111111111111111111111111111111111111111111111* -L042354 111111111111111111111111111111111111111110111111111111111111111111* -L042420 111111111110011111110110111111111111111111111111111111101111111111* -L042486 111111111110011111111110111011111111111111111111111111101111111111* -L042552 111111111110011111111111111011011111011111111111101111011110111111* +L041958 111111111111111111110111111111111111111111111111111111111111111111* +L042024 111111111111111111111111111111111111111111111111111111111111111111* +L042090 111111111111111111111111111111111111111111111111111111111111111111* +L042156 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BLOCK 7 * L047334 - 111111011111111111111111111111111111111111111111111111111011111111 - 111111111111111111111111111111011111111111111111111111111111111111 - 111111111111111111111111111111111110111111111111111111111111111111 - 111011111111111110111111111111111111110111111111111111111111111110 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111110111011111111111111111111111101111111011111111111111111111 - 011111111110111111111101111011111111111110111111111111111111110111 - 111111111111111011101011011111111111111111111110011101101111111111 - 111111111111111111111111111110111111111111101111111111111111111111* + 111111111111111111111111111111111111111110111101111111111111111111 + 111111111111111110111111111111011111111111111111111111111111111111 + 111110111111111111111111111111111110111111111111111111111111111111 + 111011111111111111111111111101111111111111111011111111101111111111 + 111111111111111111111111111111111111111111111111111011111111111111 + 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010111111011101111111110111111111101011111111111111111011111111111* +L049578 011111111111111111111111111011111111111111111111111111111111111111* +L049644 011111101111111111111111111111111111111111111111111111111111111111* +L049710 111111111111111111011111111111111111111111111111111111111111111111* +L049776 111111111111111111111111110111111111011111111111111111111111111111* +L049842 111111111110111111111111111111111111011111111111110111111111111111* +L049908 000000000000000000000000000000000000000000000000000000000000000000* +L049974 000000000000000000000000000000000000000000000000000000000000000000* L050040 000000000000000000000000000000000000000000000000000000000000000000* L050106 - 111111111111111011111111111111101111111111111110111111111111111111* -L050172 111111111111111111111111111111101111111101111111111111111111111111* -L050238 111111111111111111111111111111111111111101111111111111111011111111* -L050304 110111110111101101111110111111111101111101111111111111111111111011* -L050370 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000000000000000000000000000000000000000000000000000000000000000000* -L051426 000000000000000000000000000000000000000000000000000000000000000000* -L051492 000000000000000000000000000000000000000000000000000000000000000000* +L050898 111111111111111111111111111111111111111111111111111111111111111111* +L050964 111111111111111111111111111111111111111111111111111111111111111111* +L051030 111111111111111111111111111111111111111111111111111111111111111111* +L051096 111111111111111111111111111111111111111111111111111111111111111111* +L051162 111111111111111111111111111111111111111111111111111111111111111111* +L051228 111111111111111111111111111111111111111111111111110111111111111111* +L051294 111111111111111111111111111111111111111111111111111111111111111111* +L051360 111111111111111111111111111111111111111111111111111111111111111111* +L051426 111111111111111111111111111111111111111111111111111111111111111111* +L051492 111111111111111111111111111111111111111111111111111111111111111111* L051558 - 111111111111111111111111111111111111111111111101111111111111111111* -L051624 111111111111111111111111111111111111111111111111011111111111111111* -L051690 000000000000000000000000000000000000000000000000000000000000000000* -L051756 000000000000000000000000000000000000000000000000000000000000000000* -L051822 000000000000000000000000000000000000000000000000000000000000000000* -L051888 000000000000000000000000000000000000000000000000000000000000000000* -L051954 111111111111111111111111111111111111111111111011111111111111111111* -L052020 000000000000000000000000000000000000000000000000000000000000000000* -L052086 000000000000000000000000000000000000000000000000000000000000000000* -L052152 000000000000000000000000000000000000000000000000000000000000000000* -L052218 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111110111111111111111111111111111111111111111* +L051624 111111111111111111111111110111111111111111111111111111111111111111* +L051690 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-L052548 111111111111111111111111111111111111111111111111111111111111111111* -L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111011111111111011101111111111111111111111111111111111* +L052350 111101111101111111111111111111111111111111111110111111111111111111* +L052416 111111111111111111101111111111111111111111111111111111111110111111* +L052482 000000000000000000000000000000000000000000000000000000000000000000* +L052548 000000000000000000000000000000000000000000000000000000000000000000* +L052614 000000000000000000000000000000000000000000000000000000000000000000* +L052680 111111111111111111111111111111110111111111111111111111111111111111* L052746 111111111111111111111111111111111111111111111111111111111111111111* L052812 111111111111111111111111111111111111111111111111111111111111111111* L052878 111111111111111111111111111111111111111111111111111111111111111111* @@ -1058,21 +1068,21 @@ L053736 000000000000000000000000000000000000000000000000000000000000000000 111111111111111111111111111111111111111111101111111111111111111111* L053868 0010* -L053872 00100011111010* -L053886 11100110010011* -L053900 11100110011001* -L053914 00010110010011* -L053928 10010110010000* -L053942 11010110011110* -L053956 10010110010000* -L053970 10100110010011* -L053984 10100110010001* -L053998 10100100010011* -L054012 00100110010110* -L054026 00100100010010* -L054040 00010100011010* -L054054 11010011110011* -L054068 11111011110011* +L053872 11100110010010* +L053886 11100110010010* +L053900 01011111111000* +L053914 11101011110011* +L053928 10100110011000* +L053942 10100110011110* +L053956 10100110010001* +L053970 11010011110011* +L053984 11111111110010* +L053998 00110110010010* +L054012 00000110010110* +L054026 11100011110011* +L054040 11100110011011* +L054054 00000100010011* +L054068 11011011110010* L054082 11111111111111* E1 0 @@ -1093,6 +1103,6 @@ E1 10000010 1 * -C5EEA* +C601C* U00000000000000000000000000000000* -DC8D +B0BE diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index f6f21df..c2a71ab 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 6/7/14; -TIME = 23:03:24; +DATE = 6/9/14; +TIME = 10:27:29; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -68,7 +68,7 @@ Run_Time = 0; Set_Reset_Dont_Care = Yes; Clock_Optimize = No; In_Reg_Optimize = Yes; -Balanced_Partitioning = No; +Balanced_Partitioning = Yes; Device_max_fanin = 33; Device_max_pterms = 20; Usercode = 0; @@ -76,89 +76,115 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -A_22_ = pin,85,-,H,-; -A_21_ = pin,94,-,A,-; -A_20_ = pin,93,-,A,-; -A_19_ = pin,97,-,A,-; A_31_ = pin,4,-,B,-; -A_18_ = pin,95,-,A,-; -A_17_ = pin,59,-,F,-; -A_16_ = pin,96,-,A,-; IPL_2_ = pin,68,-,G,-; -IPL_1_ = pin,56,-,F,-; FC_1_ = pin,58,-,F,-; -IPL_0_ = pin,67,-,G,-; -FC_0_ = pin,57,-,F,-; -RW_000 = pin,80,-,H,-; -nEXP_SPACE = pin,14,-,-,-; -BERR = pin,41,-,E,-; -BG_030 = pin,21,-,C,-; -BGACK_000 = pin,28,-,D,-; -CLK_030 = pin,64,-,-,-; -CLK_000 = pin,11,-,-,-; -CLK_OSZI = pin,61,-,-,-; -CLK_DIV_OUT = pin,65,-,G,-; -DTACK = pin,30,-,D,-; -AVEC = pin,92,-,A,-; -AVEC_EXP = pin,22,-,C,-; -VPA = pin,36,-,-,-; -RST = pin,86,-,-,-; -RW = pin,71,-,G,-; -AMIGA_BUS_ENABLE = pin,34,-,D,-; -AMIGA_BUS_DATA_DIR = pin,48,-,E,-; -AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; -CIIN = pin,47,-,E,-; A_30_ = pin,5,-,B,-; A_29_ = pin,6,-,B,-; +UDS_000 = pin,32,-,D,-; A_28_ = pin,15,-,C,-; +LDS_000 = pin,31,-,D,-; A_27_ = pin,16,-,C,-; A_26_ = pin,17,-,C,-; +nEXP_SPACE = pin,14,-,-,-; A_25_ = pin,18,-,C,-; +BERR = pin,41,-,E,-; A_24_ = pin,19,-,C,-; +BG_030 = pin,21,-,C,-; A_23_ = pin,84,-,H,-; +A_22_ = pin,85,-,H,-; +A_21_ = pin,94,-,A,-; +BGACK_000 = pin,28,-,D,-; +A_20_ = pin,93,-,A,-; +CLK_030 = pin,64,-,-,-; +A_19_ = pin,97,-,A,-; +CLK_000 = pin,11,-,-,-; +A_18_ = pin,95,-,A,-; +CLK_OSZI = pin,61,-,-,-; +A_17_ = pin,59,-,F,-; +CLK_DIV_OUT = pin,65,-,G,-; +A_16_ = pin,96,-,A,-; +FPU_CS = pin,78,-,H,-; +IPL_1_ = pin,56,-,F,-; +DTACK = pin,30,-,D,-; +IPL_0_ = pin,67,-,G,-; +AVEC = pin,92,-,A,-; +FC_0_ = pin,57,-,F,-; +VPA = pin,36,-,-,-; +RST = pin,86,-,-,-; +AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +CIIN = pin,47,-,E,-; SIZE_1_ = pin,79,-,H,-; IPL_030_2_ = pin,9,-,B,-; -IPL_030_1_ = pin,7,-,B,-; -IPL_030_0_ = pin,8,-,B,-; AS_030 = pin,82,-,H,-; AS_000 = pin,33,-,D,-; +SIZE_0_ = pin,70,-,G,-; +RW_000 = pin,80,-,H,-; DS_030 = pin,98,-,A,-; -UDS_000 = pin,32,-,D,-; -LDS_000 = pin,31,-,D,-; A0 = pin,69,-,G,-; BG_000 = pin,29,-,D,-; BGACK_030 = pin,83,-,H,-; CLK_EXP = pin,10,-,B,-; -FPU_CS = pin,78,-,H,-; +IPL_030_1_ = pin,7,-,B,-; +IPL_030_0_ = pin,8,-,B,-; DSACK1 = pin,81,-,H,-; +AVEC_EXP = pin,22,-,C,-; E = pin,66,-,G,-; VMA = pin,35,-,D,-; RESET = pin,3,-,B,-; -SIZE_0_ = pin,70,-,G,-; -inst_avec_expreg = node,-,-,G,4; -inst_AS_030_000_SYNC = node,-,-,H,7; -inst_BGACK_030_INT_D = node,-,-,B,9; -inst_VPA_D = node,-,-,A,3; -inst_CLK_OUT_PRE_50_D = node,-,-,H,12; -inst_CLK_000_D0 = node,-,-,H,3; -inst_CLK_000_D1 = node,-,-,D,5; -inst_DTACK_D0 = node,-,-,B,8; -inst_CLK_OUT_PRE_50 = node,-,-,H,11; -inst_CLK_OUT_PRE_25 = node,-,-,B,7; -SM_AMIGA_1_ = node,-,-,B,3; -SM_AMIGA_6_ = node,-,-,G,6; -SM_AMIGA_0_ = node,-,-,H,9; -SM_AMIGA_7_ = node,-,-,H,5; -inst_RW_000_INT = node,-,-,G,5; -inst_CLK_000_D2 = node,-,-,H,10; -inst_CLK_030_H = node,-,-,B,5; -SM_AMIGA_5_ = node,-,-,D,11; -SM_AMIGA_4_ = node,-,-,A,5; -SM_AMIGA_3_ = node,-,-,A,4; -SM_AMIGA_2_ = node,-,-,A,1; -cpu_est_0_ = node,-,-,D,10; -cpu_est_1_ = node,-,-,D,7; -cpu_est_2_ = node,-,-,D,9; +RW = pin,71,-,G,-; +AMIGA_BUS_ENABLE = pin,34,-,D,-; +AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; +inst_AS_030_000_SYNC = node,-,-,H,4; +inst_BGACK_030_INT_D = node,-,-,H,10; +inst_VPA_D = node,-,-,G,2; +inst_CLK_OUT_PRE_50_D = node,-,-,H,13; +inst_CLK_OUT_PRE = node,-,-,B,10; +inst_CLK_000_D0 = node,-,-,F,0; +inst_CLK_000_D1 = node,-,-,H,9; +inst_CLK_OUT_PRE_50 = node,-,-,E,8; +inst_CLK_OUT_PRE_25 = node,-,-,C,1; +inst_CLK_000_D2 = node,-,-,D,9; +inst_CLK_000_D3 = node,-,-,E,9; +inst_CLK_000_NE = node,-,-,A,8; +inst_CLK_OUT_PRE_D = node,-,-,C,8; +CLK_000_P_SYNC_9_ = node,-,-,B,6; +CLK_000_N_SYNC_11_ = node,-,-,A,10; +SM_AMIGA_7_ = node,-,-,D,2; +SM_AMIGA_6_ = node,-,-,G,5; +SM_AMIGA_1_ = node,-,-,F,8; +SM_AMIGA_0_ = node,-,-,D,6; +SM_AMIGA_4_ = node,-,-,B,9; +inst_CLK_030_H = node,-,-,A,12; +inst_LDS_000_INT = node,-,-,C,9; +inst_DS_000_ENABLE = node,-,-,B,5; +inst_UDS_000_INT = node,-,-,C,5; +CLK_000_N_SYNC_0_ = node,-,-,F,6; +CLK_000_N_SYNC_1_ = node,-,-,A,6; +CLK_000_N_SYNC_2_ = node,-,-,E,5; +CLK_000_N_SYNC_3_ = node,-,-,C,14; +CLK_000_N_SYNC_4_ = node,-,-,A,2; +CLK_000_N_SYNC_5_ = node,-,-,A,13; +CLK_000_N_SYNC_6_ = node,-,-,F,2; +CLK_000_N_SYNC_7_ = node,-,-,E,1; +CLK_000_N_SYNC_8_ = node,-,-,C,10; +CLK_000_N_SYNC_9_ = node,-,-,F,13; +CLK_000_N_SYNC_10_ = node,-,-,A,9; +CLK_000_P_SYNC_0_ = node,-,-,F,9; +CLK_000_P_SYNC_1_ = node,-,-,B,2; +CLK_000_P_SYNC_2_ = node,-,-,C,6; +CLK_000_P_SYNC_3_ = node,-,-,A,5; +CLK_000_P_SYNC_4_ = node,-,-,G,6; +CLK_000_P_SYNC_5_ = node,-,-,C,2; +CLK_000_P_SYNC_6_ = node,-,-,C,13; +CLK_000_P_SYNC_7_ = node,-,-,A,1; +CLK_000_P_SYNC_8_ = node,-,-,F,5; +SM_AMIGA_5_ = node,-,-,B,13; +SM_AMIGA_3_ = node,-,-,F,12; +SM_AMIGA_2_ = node,-,-,F,1; +cpu_est_0_ = node,-,-,F,4; +cpu_est_1_ = node,-,-,G,9; +cpu_est_2_ = node,-,-,G,13; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 206f291..7f73a88 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -85679,6 +85679,7921 @@ 17 A_25_ 1 -1 -1 1 4 17 -1 16 A_26_ 1 -1 -1 1 4 16 -1 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +108 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 329 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 332 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 331 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 328 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 330 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 338 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 334 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 328 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 325 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 339 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 326 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 324 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 332 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 331 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 330 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 341 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 310 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 306 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 336 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 335 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 340 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 338 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 333 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 329 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 320 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 -1 1 2 -1 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 309 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 322 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 323 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 321 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 314 CLK_000_P_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 313 CLK_000_P_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 312 CLK_000_P_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 311 CLK_000_P_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 -1 0 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +108 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 329 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 332 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 331 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 328 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 330 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 338 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 334 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 328 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 325 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 339 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 326 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 324 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 332 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 331 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 330 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 341 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 310 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 306 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 336 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 335 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 340 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 338 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 333 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 329 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 320 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 -1 1 2 -1 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 309 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 322 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 323 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 321 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 314 CLK_000_P_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 313 CLK_000_P_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 312 CLK_000_P_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 311 CLK_000_P_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 -1 0 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 21 AVEC_EXP 0 -1 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 21 AVEC_EXP 0 -1 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 5 0 1 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 4 0 1 6 7 30 -1 11 0 21 + 31 UDS_000 5 323 3 4 0 1 6 7 31 -1 7 0 21 + 81 AS_030 5 320 7 3 3 6 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 1 3 4 6 7 82 -1 2 0 21 + 320 RN_AS_030 3 81 7 5 0 1 3 6 7 81 -1 4 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 6 3 2 3 6 -1 -1 6 0 21 + 315 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 306 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 303 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 294 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 8 0 21 + 309 inst_CLK_030_H 3 -1 1 2 0 1 -1 -1 5 0 21 + 316 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 314 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 313 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 7 2 6 7 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 308 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 312 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 2 0 21 + 300 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 1 1 6 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 4 0 1 6 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 327 7 0 80 -1 2 0 21 + 77 FPU_CS 0 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 -1 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_FPU_CS 3 77 7 1 7 77 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 318 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 321 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 320 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 317 7 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 319 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 324 7 0 80 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 323 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 317 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 8 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 326 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 324 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 318 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 318 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 321 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 320 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 317 7 3 3 4 7 81 -1 4 0 21 + 70 RW 5 -1 -1 2 3 4 70 -1 1 0 21 + 97 DS_030 5 319 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 -1 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 324 7 0 80 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 323 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 317 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 7 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 308 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 326 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 324 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 318 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 -1 0 -1 -1 14 0 21 + 311 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 312 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +96 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 317 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 321 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 320 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 316 7 3 3 4 7 81 -1 4 0 21 + 70 RW 5 327 6 3 3 4 6 70 -1 3 0 21 + 79 RW_000 5 318 7 2 0 7 79 -1 4 0 21 + 97 DS_030 5 319 0 1 3 97 -1 7 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 6 0 21 + 65 E 0 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 0 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 3 0 21 + 82 BGACK_030 0 7 0 82 -1 2 0 21 + 80 DSACK1 5 324 7 0 80 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 0 3 0 34 -1 2 1 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 29 DTACK 0 -1 0 29 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 323 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 -1 4 1 3 6 7 -1 -1 1 0 21 + 316 RN_AS_030 3 81 7 3 0 6 7 81 -1 4 0 21 + 313 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 314 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 3 1 21 + 312 cpu_est_0_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 -1 2 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_0_ 3 -1 -1 2 3 6 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 -1 2 3 6 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 -1 2 3 7 -1 -1 2 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 293 inst_AS_030_000_SYNC 3 -1 -1 1 3 -1 -1 7 0 21 + 328 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 307 inst_CLK_030_H 3 -1 -1 1 0 -1 -1 5 0 21 + 318 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 305 SM_AMIGA_7_ 3 -1 -1 1 3 -1 -1 4 0 21 + 330 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 329 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_RW 3 70 6 1 6 70 -1 3 0 21 + 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 326 RN_VMA 3 34 3 1 3 34 -1 2 1 21 + 324 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 317 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 308 SM_AMIGA_5_ 3 -1 -1 1 3 -1 -1 2 0 21 + 306 inst_CLK_000_D2 3 -1 -1 1 3 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 -1 1 3 -1 -1 1 0 21 + 310 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 4 0 21 + 311 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 3 0 21 + 309 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 35 VPA 1 -1 -1 0 35 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 321 7 6 1 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 330 6 3 2 4 6 70 -1 3 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 323 7 2 0 7 79 -1 4 0 21 + 97 DS_030 5 324 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 316 cpu_est_1_ 3 -1 0 4 0 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 4 0 2 3 6 65 -1 3 1 21 + 305 SM_AMIGA_6_ 3 -1 5 4 2 3 5 6 -1 -1 2 0 21 + 304 SM_AMIGA_0_ 3 -1 2 4 2 3 5 6 -1 -1 2 0 21 + 317 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 3 1 21 + 315 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 302 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 6 0 21 + 303 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 309 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 308 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 311 SM_AMIGA_5_ 3 -1 6 2 2 6 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 306 inst_CLK_000_D2 3 -1 7 2 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 0 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 307 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 323 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 330 RN_RW 3 70 6 1 6 70 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 1 2 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 6 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 321 7 6 0 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 330 6 3 0 4 6 70 -1 3 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 323 7 2 0 7 79 -1 4 0 21 + 97 DS_030 5 324 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 331 3 0 33 -1 6 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 315 cpu_est_0_ 3 -1 0 4 0 2 3 6 -1 -1 3 0 21 + 305 SM_AMIGA_6_ 3 -1 5 4 0 3 5 6 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 + 316 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 2 3 2 3 5 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 317 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 3 1 21 + 304 SM_AMIGA_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 306 inst_CLK_000_D2 3 -1 7 3 2 3 5 -1 -1 1 0 21 + 314 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 309 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 312 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 2 2 2 3 -1 -1 1 0 21 + 324 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 331 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 307 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 323 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 330 RN_RW 3 70 6 1 6 70 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 311 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 319 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 328 6 3 1 4 6 70 -1 3 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 321 7 2 0 7 79 -1 4 0 21 + 97 DS_030 5 322 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 325 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 6 0 21 + 65 E 5 326 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 1 21 + 28 BG_000 5 323 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 324 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 316 cpu_est_1_ 3 -1 0 4 0 2 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 4 0 2 3 6 65 -1 3 1 21 + 305 SM_AMIGA_6_ 3 -1 1 4 0 1 3 6 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 2 4 2 3 5 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 + 303 SM_AMIGA_7_ 3 -1 5 3 1 3 5 -1 -1 4 0 21 + 317 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 3 1 21 + 315 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 304 SM_AMIGA_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 306 inst_CLK_000_D2 3 -1 7 3 1 3 5 -1 -1 1 0 21 + 309 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 327 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 312 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 311 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 308 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 307 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 321 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_RW 3 70 6 1 6 70 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 325 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 323 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 10 CLK_000 1 -1 -1 2 2 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 319 7 5 0 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 328 6 3 0 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 321 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 322 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 325 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 6 0 21 + 65 E 5 326 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 1 21 + 28 BG_000 5 323 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 324 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 305 SM_AMIGA_6_ 3 -1 5 4 0 3 5 7 -1 -1 2 0 21 + 316 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 315 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 304 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 303 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 317 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 314 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 309 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 327 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 311 SM_AMIGA_5_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 306 inst_CLK_000_D2 3 -1 5 2 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 307 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 328 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 321 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 325 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 323 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 1 2 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 2 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 319 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 328 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 321 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 322 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 325 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 329 3 0 33 -1 6 0 21 + 65 E 5 326 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 331 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 330 1 0 6 -1 3 0 21 + 82 BGACK_030 5 324 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 1 21 + 28 BG_000 5 323 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 324 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 305 SM_AMIGA_6_ 3 -1 5 5 0 1 3 5 7 -1 -1 2 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 302 SM_AMIGA_1_ 3 -1 6 4 3 5 6 7 -1 -1 2 0 21 + 316 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 317 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 3 1 21 + 315 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 303 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 304 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 314 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 3 0 21 + 309 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 327 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 312 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 311 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 308 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 306 inst_CLK_000_D2 3 -1 5 2 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 329 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 321 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 307 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 328 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 313 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 331 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 330 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 325 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 323 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 10 CLK_000 1 -1 -1 5 0 1 3 5 7 10 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +109 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 330 7 5 0 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 331 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 341 6 3 0 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 333 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 335 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 338 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 342 3 0 33 -1 6 0 21 + 65 E 5 339 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 329 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 334 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 332 1 0 6 -1 3 0 21 + 82 BGACK_030 5 337 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 340 3 0 34 -1 2 1 21 + 28 BG_000 5 336 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 337 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 0 6 1 2 3 5 6 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 4 2 3 5 6 -1 -1 5 0 21 + 330 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 327 cpu_est_1_ 3 -1 5 4 2 3 5 6 -1 -1 4 0 21 + 308 SM_AMIGA_7_ 3 -1 2 4 2 3 5 6 -1 -1 4 0 21 + 339 RN_E 3 65 6 4 2 3 5 6 65 -1 3 1 21 + 306 SM_AMIGA_6_ 3 -1 6 4 0 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 4 2 3 4 6 -1 -1 1 0 21 + 328 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 3 1 21 + 326 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 307 SM_AMIGA_0_ 3 -1 3 3 2 3 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 311 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 4 2 2 3 -1 -1 1 0 21 + 335 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 342 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 324 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 334 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 333 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 325 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 338 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 336 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 331 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 2 0 21 + 322 CLK_000_P_SYNC_8_ 3 -1 7 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_7_ 3 -1 2 1 7 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_6_ 3 -1 2 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_4_ 3 -1 5 1 6 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_3_ 3 -1 0 1 5 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 314 CLK_000_P_SYNC_0_ 3 -1 6 1 5 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 4 1 6 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 4 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +109 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 330 7 5 0 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 331 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 341 6 3 0 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 333 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 335 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 338 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 342 3 0 33 -1 6 0 21 + 65 E 5 339 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 329 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 334 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 332 1 0 6 -1 3 0 21 + 82 BGACK_030 5 337 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 340 3 0 34 -1 2 1 21 + 28 BG_000 5 336 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 337 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 0 6 1 2 3 5 6 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 4 2 3 5 6 -1 -1 5 0 21 + 330 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 327 cpu_est_1_ 3 -1 5 4 2 3 5 6 -1 -1 4 0 21 + 308 SM_AMIGA_7_ 3 -1 2 4 2 3 5 6 -1 -1 4 0 21 + 339 RN_E 3 65 6 4 2 3 5 6 65 -1 3 1 21 + 306 SM_AMIGA_6_ 3 -1 6 4 0 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 4 2 3 4 6 -1 -1 1 0 21 + 328 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 3 1 21 + 326 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 307 SM_AMIGA_0_ 3 -1 3 3 2 3 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 311 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 340 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 4 2 2 3 -1 -1 1 0 21 + 335 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 342 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 341 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 324 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 334 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 333 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 325 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 338 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 336 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 331 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 2 0 21 + 322 CLK_000_P_SYNC_8_ 3 -1 7 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_7_ 3 -1 2 1 7 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_6_ 3 -1 2 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_4_ 3 -1 5 1 6 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_3_ 3 -1 0 1 5 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 314 CLK_000_P_SYNC_0_ 3 -1 6 1 5 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 4 1 6 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 4 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +121 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 353 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 0 2 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 68 A0 5 -1 6 2 0 2 68 -1 1 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 354 3 0 33 -1 6 0 21 + 65 E 5 351 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 352 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 0 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 5 1 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 351 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 310 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 340 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 352 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 2 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 1 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 354 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 353 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 337 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 1 1 1 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 4 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 5 1 4 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 7 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 1 1 7 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 0 1 5 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 2 1 2 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 6 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 4 1 6 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 1 6 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 68 A0 5 -1 6 2 1 6 68 -1 1 0 21 + 80 DSACK1 5 348 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 4 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 350 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 356 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 350 RN_AVEC_EXP 3 21 2 6 0 1 2 3 5 7 21 -1 1 0 21 + 309 SM_AMIGA_6_ 3 -1 1 5 0 1 2 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D1 3 -1 3 5 1 4 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 5 1 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 304 SM_AMIGA_1_ 3 -1 2 4 2 3 5 7 -1 -1 2 0 21 + 356 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 4 0 2 3 5 19 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 5 0 21 + 339 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 307 SM_AMIGA_7_ 3 -1 5 3 1 3 5 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 338 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 5 3 1 3 5 -1 -1 1 0 21 + 298 inst_CLK_000_D2 3 -1 4 3 1 3 5 -1 -1 1 0 21 + 340 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 325 SM_AMIGA_5_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 327 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 348 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 326 SM_AMIGA_4_ 3 -1 2 1 2 -1 -1 2 0 21 + 337 CLK_000_P_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_5_ 3 -1 4 1 2 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_4_ 3 -1 0 1 4 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_0_ 3 -1 1 1 0 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_10_ 3 -1 2 1 0 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_8_ 3 -1 4 1 0 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_7_ 3 -1 7 1 4 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_6_ 3 -1 0 1 7 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_4_ 3 -1 7 1 0 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_3_ 3 -1 5 1 7 -1 -1 1 0 21 + 316 CLK_000_N_SYNC_2_ 3 -1 6 1 5 -1 -1 1 0 21 + 315 CLK_000_N_SYNC_1_ 3 -1 4 1 6 -1 -1 1 0 21 + 314 CLK_000_N_SYNC_0_ 3 -1 1 1 4 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 4 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 4 2 3 4 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 0 2 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 68 A0 5 -1 6 2 0 2 68 -1 1 0 21 + 80 DSACK1 5 348 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 350 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 356 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 2 5 0 1 3 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 350 RN_AVEC_EXP 3 21 2 4 2 3 5 7 21 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 7 4 0 1 3 7 -1 -1 1 0 21 + 339 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 309 SM_AMIGA_6_ 3 -1 7 3 2 3 7 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 356 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 3 2 3 5 19 -1 1 0 21 + 310 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 3 2 3 7 -1 -1 4 0 21 + 340 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 326 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 3 2 0 1 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 327 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 0 21 + 348 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 325 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 337 CLK_000_P_SYNC_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_7_ 3 -1 5 1 2 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_3_ 3 -1 1 1 5 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_0_ 3 -1 1 1 0 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_9_ 3 -1 1 1 0 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_8_ 3 -1 4 1 1 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_4_ 3 -1 2 1 0 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 316 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 315 CLK_000_N_SYNC_1_ 3 -1 5 1 5 -1 -1 1 0 21 + 314 CLK_000_N_SYNC_0_ 3 -1 0 1 5 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 2 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 6 97 -1 7 0 21 + 80 DSACK1 5 348 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 68 A0 5 -1 6 1 6 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 350 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 356 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 1 6 0 1 2 3 6 7 -1 -1 1 0 21 + 350 RN_AVEC_EXP 3 21 2 5 0 1 2 3 7 21 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 4 0 2 3 5 -1 -1 5 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 339 cpu_est_1_ 3 -1 2 4 1 2 3 6 -1 -1 4 0 21 + 307 SM_AMIGA_7_ 3 -1 2 4 0 2 3 5 -1 -1 4 0 21 + 352 RN_E 3 65 6 4 1 2 3 6 65 -1 3 1 21 + 309 SM_AMIGA_6_ 3 -1 0 4 0 2 3 7 -1 -1 2 0 21 + 356 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 4 1 2 3 7 19 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 7 4 0 2 3 6 -1 -1 1 0 21 + 340 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 2 3 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 4 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 1 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 337 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 348 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 0 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 7 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 1 1 7 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 7 1 1 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 0 1 7 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 0 1 5 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 6 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 5 1 6 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 4 1 5 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 4 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 0 1 4 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 6 1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 4 1 6 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 0 1 4 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 2 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 6 1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 5 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 5 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 1 2 3 4 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 352 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 348 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 353 3 0 33 -1 7 0 21 + 65 E 5 350 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 356 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 354 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 351 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 349 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 355 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 1 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 349 RN_AVEC_EXP 3 21 2 5 2 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D2 3 -1 7 5 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 4 5 1 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 306 SM_AMIGA_0_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 + 308 SM_AMIGA_6_ 3 -1 6 4 2 3 6 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 1 3 1 3 6 -1 -1 5 0 21 + 339 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 350 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 338 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21 + 309 SM_AMIGA_7_ 3 -1 6 3 1 3 6 -1 -1 3 0 21 + 307 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 340 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 337 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 351 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 355 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 2 2 3 19 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 4 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 353 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 7 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 336 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 348 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 6 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 2 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 4 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 4 1 4 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 7 1 5 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 2 1 7 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 305 CLK_000_N_SYNC_11_ 3 -1 6 1 2 -1 -1 1 0 21 + 304 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 7 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 5 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 1 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 1 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 1 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 348 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 7 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 350 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 356 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 350 RN_AVEC_EXP 3 21 2 6 1 2 3 5 6 7 21 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 2 6 1 3 4 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 1 2 3 5 6 7 -1 -1 1 0 21 + 356 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 5 1 2 3 5 6 19 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 307 SM_AMIGA_1_ 3 -1 1 4 1 3 6 7 -1 -1 3 0 21 + 306 SM_AMIGA_0_ 3 -1 6 4 1 3 6 7 -1 -1 3 0 21 + 308 SM_AMIGA_6_ 3 -1 1 4 1 3 5 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 4 4 1 3 6 7 -1 -1 1 0 21 + 299 inst_CLK_000_D3 3 -1 1 4 1 3 6 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 5 0 21 + 339 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 309 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 338 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 310 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 340 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 337 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 5 2 2 5 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 7 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 336 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 348 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 4 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 2 1 4 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 6 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 7 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 6 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 7 1 0 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 0 1 7 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 0 1 4 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 7 1 6 -1 -1 1 0 21 + 305 CLK_000_N_SYNC_11_ 3 -1 2 1 2 -1 -1 1 0 21 + 304 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 2 5 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 2 5 68 -1 1 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 5 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 356 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 5 1 2 3 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 4 1 2 3 7 -1 -1 2 0 21 + 351 RN_AVEC_EXP 3 21 2 4 0 1 2 7 21 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 5 0 21 + 339 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 307 SM_AMIGA_7_ 3 -1 0 3 0 3 5 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 1 3 0 1 7 -1 -1 2 0 21 + 356 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 3 0 1 2 19 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 0 3 0 1 3 -1 -1 1 0 21 + 310 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 337 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 5 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 336 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 2 1 2 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 4 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 0 1 4 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 7 1 5 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 5 1 7 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 1 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 6 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 7 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 6 1 7 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 4 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 1 1 4 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 3 1 1 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 7 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 4 3 5 6 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 2 3 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 3 2 2 3 -1 -1 4 0 21 + 337 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 0 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 351 RN_AVEC_EXP 3 21 2 1 5 21 -1 1 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 6 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 2 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 7 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 4 1 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 7 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 6 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 341 7 5 1 2 3 4 7 81 -1 4 0 21 + 32 AS_000 5 342 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 353 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 343 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 344 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 349 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 354 3 0 33 -1 6 0 21 + 65 E 5 351 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 340 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 348 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 347 1 0 6 -1 3 0 21 + 82 BGACK_030 5 346 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 352 3 0 34 -1 2 1 21 + 28 BG_000 5 345 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 350 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 355 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 346 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 0 6 0 1 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 1 3 5 6 7 -1 -1 1 0 21 + 341 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 308 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 3 2 3 6 -1 -1 5 0 21 + 338 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 306 SM_AMIGA_7_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 351 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 339 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 3 1 21 + 337 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 300 inst_CLK_OUT_PRE_25 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_5_ 3 -1 7 3 1 5 7 -1 -1 2 0 21 + 307 SM_AMIGA_0_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 303 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 301 inst_CLK_000_D2 3 -1 7 3 2 3 6 -1 -1 1 0 21 + 336 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 311 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 352 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_CLK_OUT_PRE_50 3 -1 4 2 4 5 -1 -1 1 0 21 + 344 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 354 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 335 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 309 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 353 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 340 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 349 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 342 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 334 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 355 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 5 19 -1 1 0 21 + 350 RN_AVEC_EXP 3 21 2 1 5 21 -1 1 0 21 + 333 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_0_ 3 -1 6 1 4 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_10_ 3 -1 2 1 2 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_8_ 3 -1 4 1 0 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_7_ 3 -1 2 1 4 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_4_ 3 -1 7 1 0 -1 -1 1 0 21 + 316 CLK_000_N_SYNC_3_ 3 -1 0 1 7 -1 -1 1 0 21 + 315 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 314 CLK_000_N_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 313 CLK_000_N_SYNC_0_ 3 -1 6 1 0 -1 -1 1 0 21 + 305 CLK_000_N_SYNC_11_ 3 -1 2 1 2 -1 -1 1 0 21 + 304 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 302 inst_CLK_000_D3 3 -1 2 1 6 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 1 3 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 4 3 5 6 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 2 3 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 3 2 2 3 -1 -1 4 0 21 + 337 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 0 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 351 RN_AVEC_EXP 3 21 2 1 5 21 -1 1 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 6 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 2 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 7 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 4 1 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 7 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 6 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 1 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 5 5 1 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 338 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 340 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 337 SM_AMIGA_2_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 351 RN_AVEC_EXP 3 21 2 2 1 2 21 -1 1 0 21 + 302 inst_CLK_000_D2 3 -1 7 2 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 0 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 6 2 1 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 1 1 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 0 1 1 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 0 1 4 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 2 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 7 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 4 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 0 1 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 68 A0 5 -1 6 2 0 1 68 -1 1 0 21 + 80 DSACK1 5 348 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 351 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 352 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 349 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 356 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 2 6 1 2 3 5 6 7 -1 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 4 3 5 6 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 351 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 304 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 3 3 5 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 3 2 3 7 -1 -1 4 0 21 + 340 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 337 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 3 2 3 7 -1 -1 2 0 21 + 356 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 2 3 5 19 -1 1 0 21 + 349 RN_AVEC_EXP 3 21 2 2 2 5 21 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 4 2 2 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 348 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 1 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 2 1 1 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 1 1 0 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 2 1 1 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 5 1 4 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 5 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 6 1 5 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 2 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 4 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 4 3 5 6 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 2 3 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 3 2 2 3 -1 -1 4 0 21 + 337 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 0 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 351 RN_AVEC_EXP 3 21 2 1 5 21 -1 1 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 6 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 2 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 7 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 4 1 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 7 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 6 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 1 5 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 1 5 68 -1 1 0 21 + 80 DSACK1 5 349 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 350 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 3 6 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 351 RN_AVEC_EXP 3 21 2 4 0 2 5 7 21 -1 1 0 21 + 339 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 309 SM_AMIGA_6_ 3 -1 3 3 1 3 7 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 3 2 3 5 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 337 SM_AMIGA_2_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 336 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 349 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 5 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 4 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 0 1 4 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 4 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 7 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 5 1 7 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 7 1 5 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 2 1 7 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 2 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 5 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 1 5 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 1 5 68 -1 1 0 21 + 80 DSACK1 5 349 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 350 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 3 6 1 2 3 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 351 RN_AVEC_EXP 3 21 2 4 0 2 5 7 21 -1 1 0 21 + 339 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 309 SM_AMIGA_6_ 3 -1 3 3 1 3 7 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 7 3 2 3 5 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 337 SM_AMIGA_2_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 335 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 336 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 349 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 5 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 4 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 0 1 4 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 4 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 7 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 5 1 7 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 7 1 5 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 2 1 7 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 2 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 5 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 343 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 344 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 345 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 346 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 349 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 342 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 348 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 347 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 352 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 4 7 0 1 3 4 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 348 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 343 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 6 4 2 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 4 4 0 3 5 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 340 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 307 SM_AMIGA_7_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 353 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 339 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 352 RN_AVEC_EXP 3 21 2 3 1 5 7 21 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 3 2 4 7 -1 -1 1 0 21 + 341 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 338 SM_AMIGA_2_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 295 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 + 346 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 345 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 337 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 349 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 344 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 336 SM_AMIGA_4_ 3 -1 1 1 1 -1 -1 2 0 21 + 335 CLK_000_N_SYNC_10_ 3 -1 4 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_9_ 3 -1 0 1 4 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_3_ 3 -1 7 1 5 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_2_ 3 -1 5 1 7 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_1_ 3 -1 7 1 5 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_0_ 3 -1 0 1 7 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 5 1 6 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 2 1 6 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 0 1 2 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_10_ 3 -1 6 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 3 1 0 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 5 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +124 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 356 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 347 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 357 3 0 33 -1 6 0 21 + 65 E 5 354 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 352 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 351 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 355 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 353 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 7 0 1 3 4 5 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 6 4 3 5 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 4 4 0 1 3 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 3 2 3 6 -1 -1 5 0 21 + 341 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 307 SM_AMIGA_7_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 354 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 301 inst_CLK_OUT_PRE_25 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 353 RN_AVEC_EXP 3 21 2 3 5 6 7 21 -1 1 0 21 + 342 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 340 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 339 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 355 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 7 2 5 7 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 303 inst_CLK_000_D3 3 -1 3 2 0 1 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 4 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 357 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 2 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 0 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 5 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 0 1 5 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_10_ 3 -1 1 1 0 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_9_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 4 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 7 1 6 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 4 1 7 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 2 1 4 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 1 1 2 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 5 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 2 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 345 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 347 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 351 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 347 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 3 4 3 5 6 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 352 RN_E 3 65 6 3 3 5 6 65 -1 3 1 21 + 340 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_1_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 3 2 3 6 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 3 2 2 3 -1 -1 4 0 21 + 337 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 0 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 2 0 21 + 351 RN_AVEC_EXP 3 21 2 1 5 21 -1 1 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 6 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 2 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 7 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 4 1 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 7 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 6 1 2 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +121 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 342 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 343 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 353 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 345 0 2 0 2 97 -1 7 0 21 + 79 RW_000 5 344 7 2 0 6 79 -1 3 0 21 + 68 A0 5 -1 6 2 0 2 68 -1 1 0 21 + 80 DSACK1 5 350 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 354 3 0 33 -1 6 0 21 + 65 E 5 351 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 352 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 0 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 5 1 3 5 6 7 -1 -1 1 0 21 + 342 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 339 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 351 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 310 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 340 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 338 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 352 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 2 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 5 2 1 3 -1 -1 1 0 21 + 345 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 354 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 353 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 337 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 343 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 335 SM_AMIGA_4_ 3 -1 1 1 1 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_9_ 3 -1 4 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_8_ 3 -1 5 1 4 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_7_ 3 -1 7 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_6_ 3 -1 1 1 7 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_3_ 3 -1 0 1 5 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_1_ 3 -1 2 1 2 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 6 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 4 1 6 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 306 CLK_000_N_SYNC_11_ 3 -1 0 1 2 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +110 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 331 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 332 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 342 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 333 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 334 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 339 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 343 3 0 33 -1 6 0 21 + 65 E 5 340 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 330 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 336 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 335 1 0 6 -1 3 0 21 + 82 BGACK_030 5 338 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 341 3 0 34 -1 2 1 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 1 2 3 5 7 -1 -1 1 0 21 + 328 cpu_est_1_ 3 -1 5 4 1 3 5 6 -1 -1 5 0 21 + 340 RN_E 3 65 6 4 1 3 5 6 65 -1 4 0 21 + 331 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 298 inst_CLK_000_D0 3 -1 5 4 1 3 5 7 -1 -1 1 0 21 + 294 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 5 0 21 + 329 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 309 SM_AMIGA_7_ 3 -1 5 3 2 3 5 -1 -1 4 0 21 + 327 cpu_est_0_ 3 -1 6 3 3 5 6 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 307 SM_AMIGA_6_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 2 3 3 5 7 -1 -1 1 0 21 + 312 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 341 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 314 SM_AMIGA_5_ 3 -1 5 2 1 5 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 2 2 2 4 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 4 2 5 6 -1 -1 1 0 21 + 334 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 343 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 342 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 325 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 336 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 335 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 333 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 330 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 326 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 332 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 324 SM_AMIGA_4_ 3 -1 1 1 1 -1 -1 2 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 2 1 2 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 2 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 2 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 2 1 2 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 5 1 2 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 7 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 6 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +110 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 331 7 5 0 2 3 4 7 81 -1 4 0 21 + 32 AS_000 5 332 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 342 6 3 0 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 334 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 336 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 339 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 343 3 0 33 -1 6 0 21 + 65 E 5 340 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 330 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 335 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 333 1 0 6 -1 3 0 21 + 82 BGACK_030 5 338 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 341 3 0 34 -1 2 1 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D0 3 -1 4 6 0 1 2 3 5 7 -1 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 1 2 3 5 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 2 5 0 3 5 6 7 -1 -1 1 0 21 + 331 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 5 4 0 3 5 7 -1 -1 2 0 21 + 308 SM_AMIGA_0_ 3 -1 2 4 2 3 5 7 -1 -1 2 0 21 + 328 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 5 0 21 + 294 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 5 0 21 + 340 RN_E 3 65 6 3 3 5 6 65 -1 4 0 21 + 307 SM_AMIGA_7_ 3 -1 5 3 2 3 5 -1 -1 4 0 21 + 327 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 7 3 2 3 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 2 3 0 3 5 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 2 3 0 1 2 -1 -1 1 0 21 + 329 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 326 SM_AMIGA_2_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 341 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 324 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 2 0 21 + 313 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 296 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 336 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 343 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 334 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 310 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 342 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 325 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 4 0 21 + 335 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 333 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 339 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 332 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 323 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_7_ 3 -1 4 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_4_ 3 -1 4 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_3_ 3 -1 4 1 4 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_2_ 3 -1 0 1 4 -1 -1 1 0 21 + 316 CLK_000_P_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 315 CLK_000_P_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 0 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 0 1 1 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 347 0 2 0 2 97 -1 7 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 0 2 68 -1 1 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 3 0 21 + 82 BGACK_030 5 351 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 350 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 351 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D0 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 299 inst_CLK_000_D1 3 -1 7 4 1 3 5 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 6 4 2 3 6 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 1 3 6 65 -1 4 0 21 + 310 SM_AMIGA_6_ 3 -1 3 3 2 3 7 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 7 3 3 5 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 342 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 312 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 315 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 340 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 4 2 2 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 2 3 5 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 338 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 339 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 350 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 0 1 2 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 2 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 7 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 5 1 7 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 2 1 6 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 0 1 2 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 2 1 5 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 6 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 2 1 0 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 0 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 5 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 1 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 347 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 4 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 293 inst_avec_expreg 3 -1 5 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 1 5 1 3 5 6 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 2 4 1 2 3 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 4 1 2 3 6 65 -1 4 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 7 4 1 3 5 7 -1 -1 1 0 21 + 342 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 340 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 6 3 3 6 7 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 5 3 0 4 5 -1 -1 1 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 310 SM_AMIGA_7_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 339 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 315 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 316 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 2 2 5 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 2 3 5 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 5 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 4 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +122 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 343 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 344 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 354 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 345 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 346 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 355 3 0 33 -1 6 0 21 + 65 E 5 352 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 342 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 347 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 353 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 5 6 0 1 3 5 6 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 2 5 1 2 3 6 7 -1 -1 1 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 4 0 2 3 5 -1 -1 5 0 21 + 343 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_7_ 3 -1 0 4 0 2 3 5 -1 -1 4 0 21 + 310 SM_AMIGA_6_ 3 -1 2 4 1 2 3 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 + 340 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 5 0 21 + 352 RN_E 3 65 6 3 1 3 6 65 -1 4 0 21 + 308 SM_AMIGA_0_ 3 -1 7 3 0 3 7 -1 -1 2 0 21 + 304 SM_AMIGA_1_ 3 -1 6 3 3 6 7 -1 -1 2 0 21 + 341 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 338 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 314 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 353 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 339 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 315 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 0 2 0 6 -1 -1 1 0 21 + 346 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 355 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 345 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 337 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 312 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 354 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 344 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 336 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 335 CLK_000_P_SYNC_8_ 3 -1 2 1 4 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_10_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_9_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_6_ 3 -1 1 1 0 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_3_ 3 -1 5 1 4 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_1_ 3 -1 7 1 5 -1 -1 1 0 21 + 316 CLK_000_N_SYNC_0_ 3 -1 5 1 7 -1 -1 1 0 21 + 307 CLK_000_N_SYNC_11_ 3 -1 0 1 7 -1 -1 1 0 21 + 306 inst_CLK_000_NE 3 -1 7 1 1 -1 -1 1 0 21 + 305 CLK_000_P_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 0 1 6 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 1 1 3 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 347 0 2 0 2 97 -1 7 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 0 2 68 -1 1 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 293 inst_avec_expreg 3 -1 5 6 1 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 1 2 3 5 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 4 5 0 1 3 5 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 5 4 1 3 5 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 4 1 3 5 6 65 -1 4 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 2 4 2 3 4 5 -1 -1 1 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 5 0 21 + 342 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 310 SM_AMIGA_7_ 3 -1 3 3 2 3 5 -1 -1 4 0 21 + 340 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 7 3 0 3 7 -1 -1 2 0 21 + 307 inst_CLK_000_NE 3 -1 1 3 1 2 6 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 2 3 0 2 6 -1 -1 1 0 21 + 330 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 315 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 328 SM_AMIGA_5_ 3 -1 6 2 2 6 -1 -1 2 0 21 + 316 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 2 2 5 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 5 2 1 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 329 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 339 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_7_ 3 -1 4 1 0 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_4_ 3 -1 5 1 6 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_3_ 3 -1 5 1 5 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_4_ 3 -1 1 1 0 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_1_ 3 -1 2 1 6 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 4 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 0 1 6 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 347 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 4 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 293 inst_avec_expreg 3 -1 5 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 1 5 1 3 5 6 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 2 4 1 2 3 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 4 1 2 3 6 65 -1 4 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 7 4 1 3 5 7 -1 -1 1 0 21 + 342 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 340 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 6 3 3 6 7 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 5 3 0 4 5 -1 -1 1 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 310 SM_AMIGA_7_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 339 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 315 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 316 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 2 2 5 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 2 3 5 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 0 1 6 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 5 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 4 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 1 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 347 0 2 0 2 97 -1 7 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 0 2 68 -1 1 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 352 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 0 7 0 1 2 3 4 5 7 -1 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 293 inst_avec_expreg 3 -1 6 6 1 2 3 5 6 7 -1 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 4 5 0 1 3 5 7 -1 -1 1 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 341 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 1 3 6 65 -1 4 0 21 + 309 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 7 3 0 3 5 -1 -1 1 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 342 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 310 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 339 SM_AMIGA_2_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 315 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 340 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 2 2 2 6 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 1 1 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 1 1 1 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 5 1 2 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 0 1 1 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 4 1 5 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 0 1 4 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 6 1 2 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 7 1 4 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 0 1 7 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 5 1 0 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 0 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 3 1 0 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 7 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 5 1 6 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 347 0 1 1 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 68 A0 5 -1 6 1 1 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 293 inst_avec_expreg 3 -1 6 6 0 2 3 5 6 7 -1 -1 1 0 21 + 311 SM_AMIGA_6_ 3 -1 6 5 0 2 3 6 7 -1 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 3 5 0 1 2 3 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 5 4 2 3 5 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 4 2 3 5 6 65 -1 4 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 305 SM_AMIGA_1_ 3 -1 1 4 0 1 3 7 -1 -1 2 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 342 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 309 SM_AMIGA_7_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 340 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 310 SM_AMIGA_0_ 3 -1 0 3 0 3 7 -1 -1 2 0 21 + 306 inst_CLK_000_NE 3 -1 1 3 0 1 3 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 3 3 6 7 -1 -1 1 0 21 + 339 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 315 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 316 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 307 CLK_000_P_SYNC_9_ 3 -1 2 2 2 6 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 6 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 5 1 4 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 2 1 5 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 5 1 5 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 7 1 5 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 6 1 2 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 2 1 5 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 2 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 7 1 4 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 0 1 1 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 7 1 7 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 0 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 347 0 1 5 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 68 A0 5 -1 6 1 5 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 293 inst_avec_expreg 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 5 4 0 3 5 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 3 4 2 3 5 6 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 5 4 1 3 6 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 5 0 21 + 294 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 1 3 6 65 -1 4 0 21 + 310 SM_AMIGA_7_ 3 -1 2 3 2 3 5 -1 -1 4 0 21 + 340 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 0 3 0 1 5 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 7 3 2 3 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 342 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 315 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 316 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 5 2 1 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 338 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 339 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 1 1 4 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 2 1 1 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 2 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 7 1 2 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 2 1 7 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 6 1 0 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 2 1 4 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 1 1 2 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 4 1 5 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 5 1 0 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 3 1 6 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 2 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 347 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 356 3 0 33 -1 5 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 7 5 1 2 3 6 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 4 5 1 2 3 6 7 -1 -1 1 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 2 4 1 2 3 6 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 5 4 1 2 3 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 5 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 2 3 6 65 -1 4 0 21 + 309 SM_AMIGA_7_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 307 inst_CLK_000_NE 3 -1 0 3 2 6 7 -1 -1 1 0 21 + 342 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 315 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 340 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 6 2 2 6 -1 -1 2 0 21 + 316 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 310 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 2 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 0 2 2 4 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 2 2 1 2 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 5 2 4 5 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 4 2 2 3 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 356 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 5 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 339 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 336 CLK_000_N_SYNC_10_ 3 -1 1 1 7 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_9_ 3 -1 5 1 1 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_8_ 3 -1 5 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_3_ 3 -1 7 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_2_ 3 -1 2 1 7 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_1_ 3 -1 1 1 2 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 317 CLK_000_P_SYNC_0_ 3 -1 1 1 5 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 5 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 4 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +125 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 346 7 5 0 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 347 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 357 6 3 0 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 348 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 349 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 354 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 355 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 345 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 353 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 352 1 0 6 -1 3 0 21 + 82 BGACK_030 5 351 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 356 3 0 34 -1 2 1 21 + 28 BG_000 5 350 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 293 inst_avec_expreg 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 351 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D0 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 343 cpu_est_1_ 3 -1 3 4 1 3 5 6 -1 -1 5 0 21 + 355 RN_E 3 65 6 4 1 3 5 6 65 -1 4 0 21 + 346 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 342 cpu_est_0_ 3 -1 0 4 0 3 5 6 -1 -1 2 0 21 + 313 SM_AMIGA_6_ 3 -1 5 4 0 3 5 7 -1 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 5 4 1 3 5 7 -1 -1 1 0 21 + 344 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 311 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 304 inst_CLK_000_D2 3 -1 7 3 3 5 7 -1 -1 1 0 21 + 315 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 312 SM_AMIGA_7_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 341 SM_AMIGA_2_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 317 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE_25 3 -1 2 2 2 5 -1 -1 3 0 21 + 356 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 318 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 316 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 314 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 310 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 + 302 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 + 300 inst_CLK_000_D3 3 -1 7 2 5 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21 + 349 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 348 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 340 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 345 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 354 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 350 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 347 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 339 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_10_ 3 -1 2 1 2 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_8_ 3 -1 1 1 1 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_6_ 3 -1 4 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_5_ 3 -1 5 1 4 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_3_ 3 -1 2 1 6 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_2_ 3 -1 0 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_1_ 3 -1 4 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_0_ 3 -1 7 1 4 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_8_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_6_ 3 -1 0 1 2 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_3_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_1_ 3 -1 5 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 309 CLK_000_N_SYNC_11_ 3 -1 2 1 0 -1 -1 1 0 21 + 308 inst_CLK_000_NE 3 -1 0 1 0 -1 -1 1 0 21 + 307 CLK_000_P_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21 + 306 inst_CLK_OUT_PRE 3 -1 5 1 6 -1 -1 1 0 21 + 301 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 2 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 6 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 347 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 348 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 358 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 350 0 2 0 6 97 -1 7 0 21 + 79 RW_000 5 349 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 0 6 68 -1 1 0 21 + 80 DSACK1 5 355 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 359 3 0 33 -1 6 0 21 + 65 E 5 356 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 346 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 354 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 353 1 0 6 -1 3 0 21 + 82 BGACK_030 5 352 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 357 3 0 34 -1 2 1 21 + 28 BG_000 5 351 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 352 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 293 inst_avec_expreg 3 -1 1 6 1 2 3 5 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D1 3 -1 7 5 1 2 3 5 7 -1 -1 1 0 21 + 299 inst_CLK_000_D0 3 -1 4 5 1 2 3 5 7 -1 -1 1 0 21 + 347 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 314 SM_AMIGA_6_ 3 -1 3 4 1 2 3 7 -1 -1 2 0 21 + 304 inst_CLK_000_D2 3 -1 7 4 1 3 5 7 -1 -1 1 0 21 + 344 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 5 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 5 0 21 + 356 RN_E 3 65 6 3 2 3 6 65 -1 4 0 21 + 313 SM_AMIGA_7_ 3 -1 1 3 1 3 5 -1 -1 4 0 21 + 312 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 311 SM_AMIGA_0_ 3 -1 7 3 1 3 7 -1 -1 2 0 21 + 302 inst_CLK_OUT_PRE_50 3 -1 5 3 0 4 5 -1 -1 1 0 21 + 316 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 345 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 342 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 357 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 343 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 340 SM_AMIGA_5_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 319 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 317 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 309 inst_CLK_000_NE 3 -1 0 2 1 2 -1 -1 1 0 21 + 308 CLK_000_P_SYNC_9_ 3 -1 2 2 1 2 -1 -1 1 0 21 + 307 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 + 298 inst_CLK_OUT_PRE 3 -1 0 2 0 6 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 2 2 2 3 -1 -1 1 0 21 + 350 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 359 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 349 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 341 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 303 inst_CLK_OUT_PRE_25 3 -1 0 1 0 -1 -1 3 0 21 + 355 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 315 SM_AMIGA_4_ 3 -1 2 1 2 -1 -1 2 0 21 + 339 CLK_000_N_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_8_ 3 -1 4 1 2 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_7_ 3 -1 5 1 4 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_1_ 3 -1 5 1 4 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_8_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_6_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 310 CLK_000_N_SYNC_11_ 3 -1 0 1 0 -1 -1 1 0 21 + 306 inst_CLK_OUT_NE 3 -1 6 1 7 -1 -1 1 0 21 + 305 inst_CLK_000_D3 3 -1 7 1 5 -1 -1 1 0 21 + 301 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 0 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +125 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 346 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 347 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 357 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 97 DS_030 5 349 0 2 0 1 97 -1 7 0 21 + 79 RW_000 5 348 7 2 0 6 79 -1 5 0 21 + 68 A0 5 -1 6 2 0 1 68 -1 1 0 21 + 80 DSACK1 5 353 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 355 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 345 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 354 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 352 1 0 6 -1 3 0 21 + 82 BGACK_030 5 351 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 356 3 0 34 -1 2 1 21 + 28 BG_000 5 350 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 351 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 1 2 3 5 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 4 5 1 2 3 5 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 2 5 2 3 5 6 7 -1 -1 1 0 21 + 346 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 313 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 343 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 5 0 21 + 355 RN_E 3 65 6 3 2 3 6 65 -1 4 0 21 + 342 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 311 SM_AMIGA_0_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 294 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 344 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 312 SM_AMIGA_7_ 3 -1 3 2 3 5 -1 -1 4 0 21 + 317 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 4 -1 -1 3 0 21 + 356 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 318 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 316 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 306 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 3 2 3 5 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 7 2 2 3 -1 -1 1 0 21 + 349 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 348 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 340 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 315 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 345 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 341 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 3 0 21 + 353 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 350 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 347 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 339 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 314 SM_AMIGA_4_ 3 -1 2 1 2 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_10_ 3 -1 4 1 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_9_ 3 -1 0 1 4 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 327 CLK_000_P_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_4_ 3 -1 7 1 0 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_3_ 3 -1 5 1 7 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 310 CLK_000_N_SYNC_11_ 3 -1 5 1 5 -1 -1 1 0 21 + 309 inst_CLK_000_NE 3 -1 5 1 2 -1 -1 1 0 21 + 308 CLK_000_P_SYNC_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 307 inst_CLK_OUT_PRE 3 -1 4 1 5 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 5 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 7 1 2 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +125 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 357 6 3 4 5 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 348 0 1 5 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 68 A0 5 -1 6 1 5 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 355 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 354 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 352 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 356 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 353 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 353 RN_AVEC_EXP 3 21 2 6 0 1 3 5 6 7 21 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 0 5 1 2 3 5 7 -1 -1 1 0 21 + 342 cpu_est_1_ 3 -1 6 4 0 1 3 6 -1 -1 5 0 21 + 355 RN_E 3 65 6 4 0 1 3 6 65 -1 4 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 303 inst_CLK_000_D2 3 -1 7 4 0 1 2 3 -1 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 4 1 2 3 7 -1 -1 1 0 21 + 343 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 341 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 2 0 21 + 312 SM_AMIGA_6_ 3 -1 3 3 3 5 7 -1 -1 2 0 21 + 310 SM_AMIGA_0_ 3 -1 3 3 2 3 7 -1 -1 2 0 21 + 305 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 306 inst_CLK_OUT_PRE_D 3 -1 5 3 1 2 6 -1 -1 1 0 21 + 314 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 5 0 21 + 311 SM_AMIGA_7_ 3 -1 2 2 2 3 -1 -1 4 0 21 + 340 SM_AMIGA_2_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 316 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 2 6 -1 -1 3 0 21 + 356 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 317 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 5 2 1 5 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 4 6 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE 3 -1 2 2 2 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 339 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 338 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 2 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 2 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 5 1 4 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 7 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 0 1 7 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 6 1 4 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 4 1 2 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 0 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 309 CLK_000_N_SYNC_11_ 3 -1 0 1 5 -1 -1 1 0 21 + 308 inst_CLK_000_NE 3 -1 5 1 5 -1 -1 1 0 21 + 307 CLK_000_P_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 0 1 1 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 1 2 3 4 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 357 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 348 0 1 5 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 68 A0 5 -1 6 1 5 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 356 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 355 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 352 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 359 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 352 RN_AVEC_EXP 3 21 2 6 0 1 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 5 1 2 3 5 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 5 5 1 2 3 5 7 -1 -1 1 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 312 SM_AMIGA_6_ 3 -1 3 4 0 1 3 7 -1 -1 2 0 21 + 342 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 3 5 6 65 -1 4 0 21 + 341 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 2 3 1 2 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 3 1 2 3 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 5 0 21 + 343 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 311 SM_AMIGA_7_ 3 -1 3 2 2 3 -1 -1 4 0 21 + 316 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 4 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 338 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 317 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 307 inst_CLK_000_NE 3 -1 0 2 0 1 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 339 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 314 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 340 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 359 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 0 1 6 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 4 1 1 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 2 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 2 1 2 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 5 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 5 1 5 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 6 1 0 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 1 1 2 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 7 1 5 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE 3 -1 4 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 4 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 3 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 356 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 348 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 357 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 355 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 352 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 359 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 352 RN_AVEC_EXP 3 21 2 6 1 2 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 4 5 1 2 3 5 7 -1 -1 1 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 312 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 342 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 2 3 6 65 -1 4 0 21 + 311 SM_AMIGA_7_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 341 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 5 3 1 2 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 3 3 5 6 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 3 4 6 7 -1 -1 1 0 21 + 314 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 343 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 340 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 316 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 6 7 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 317 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_CLK_OUT_PRE 3 -1 7 2 2 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 339 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 357 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 338 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 359 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 0 1 4 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 4 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 4 1 2 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 2 1 1 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 357 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 348 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 353 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 355 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 352 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 351 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 356 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 354 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 359 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 354 RN_AVEC_EXP 3 21 2 6 1 2 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 4 5 1 2 3 5 7 -1 -1 1 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 312 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 342 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 355 RN_E 3 65 6 3 2 3 6 65 -1 4 0 21 + 311 SM_AMIGA_7_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 341 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 5 3 1 2 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 3 3 5 6 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 3 4 6 7 -1 -1 1 0 21 + 314 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 343 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 340 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 316 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 6 7 -1 -1 3 0 21 + 356 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 317 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_CLK_OUT_PRE 3 -1 7 2 2 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 339 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 353 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 338 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 359 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 0 1 4 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 4 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 4 1 2 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 2 1 1 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 1 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 5 0 21 + 97 DS_030 5 348 0 1 0 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 68 A0 5 -1 6 1 0 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 357 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 358 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 356 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 352 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 359 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 352 RN_AVEC_EXP 3 21 2 6 1 2 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 4 5 1 2 3 5 7 -1 -1 1 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 312 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 342 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 3 3 5 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 2 3 6 65 -1 4 0 21 + 311 SM_AMIGA_7_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 341 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 1 3 1 3 7 -1 -1 2 0 21 + 309 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 5 3 1 2 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 3 3 5 6 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 3 4 6 7 -1 -1 1 0 21 + 314 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 343 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 340 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 316 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 6 7 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 317 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_CLK_OUT_PRE 3 -1 7 2 2 5 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 357 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 339 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 358 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 356 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 338 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 359 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 0 1 4 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 4 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 4 1 2 -1 -1 1 0 21 + 307 inst_CLK_000_NE 3 -1 2 1 1 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 3 1 5 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 4 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 357 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 348 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 358 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 356 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 355 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 352 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 359 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 352 RN_AVEC_EXP 3 21 2 6 1 2 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 5 0 1 3 5 7 -1 -1 1 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 312 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 2 0 21 + 298 inst_CLK_000_D0 3 -1 6 4 0 1 3 7 -1 -1 1 0 21 + 342 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 1 3 6 65 -1 4 0 21 + 341 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 311 SM_AMIGA_0_ 3 -1 3 3 3 5 7 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 2 3 2 3 7 -1 -1 2 0 21 + 306 inst_CLK_OUT_PRE_D 3 -1 4 3 1 2 6 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 3 3 0 3 5 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 4 3 0 4 5 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 5 0 21 + 343 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 309 SM_AMIGA_7_ 3 -1 5 2 3 5 -1 -1 4 0 21 + 340 SM_AMIGA_2_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 316 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 0 2 0 4 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 317 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 305 inst_CLK_000_NE 3 -1 6 2 2 3 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE 3 -1 4 2 2 4 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 358 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 339 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 314 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 338 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 359 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 5 1 0 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 5 1 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 6 1 5 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 5 1 7 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 2 1 5 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 0 1 6 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 1 1 1 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 5 1 1 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 0 1 5 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 0 1 4 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 6 1 0 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 0 1 0 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 0 1 6 -1 -1 1 0 21 + 307 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 0 1 0 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 5 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 6 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 345 7 5 2 3 4 5 7 81 -1 4 0 21 + 32 AS_000 5 346 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 355 6 3 2 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 347 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 348 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 351 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 357 3 0 33 -1 6 0 21 + 65 E 5 353 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 358 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 356 1 0 6 -1 3 0 21 + 82 BGACK_030 5 350 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 354 3 0 34 -1 2 1 21 + 28 BG_000 5 349 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 352 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 359 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 352 RN_AVEC_EXP 3 21 2 7 0 1 2 3 5 6 7 21 -1 1 0 21 + 350 RN_BGACK_030 3 82 7 6 0 3 4 5 6 7 82 -1 2 0 21 + 309 SM_AMIGA_7_ 3 -1 6 5 0 3 5 6 7 -1 -1 4 0 21 + 299 inst_CLK_000_D1 3 -1 0 5 0 1 3 6 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 5 4 0 3 5 6 -1 -1 5 0 21 + 345 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 312 SM_AMIGA_6_ 3 -1 0 4 0 2 3 7 -1 -1 2 0 21 + 303 inst_CLK_000_D2 3 -1 3 4 0 1 3 6 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 3 4 0 1 3 7 -1 -1 1 0 21 + 342 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 5 0 21 + 353 RN_E 3 65 6 3 1 3 6 65 -1 4 0 21 + 311 SM_AMIGA_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 306 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 305 inst_CLK_000_NE 3 -1 1 3 2 3 5 -1 -1 1 0 21 + 343 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 340 SM_AMIGA_2_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 316 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 354 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 341 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 317 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 315 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 SM_AMIGA_4_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 5 7 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE 3 -1 5 2 2 6 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 + 348 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 357 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 339 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 314 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 355 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 358 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 356 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 347 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 5 1 5 -1 -1 3 0 21 + 351 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 346 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 338 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 2 0 21 + 359 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 337 CLK_000_N_SYNC_10_ 3 -1 5 1 5 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_8_ 3 -1 4 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_7_ 3 -1 4 1 4 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_5_ 3 -1 7 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_4_ 3 -1 0 1 7 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_1_ 3 -1 2 1 0 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_0_ 3 -1 1 1 2 -1 -1 1 0 21 + 326 CLK_000_P_SYNC_8_ 3 -1 0 1 4 -1 -1 1 0 21 + 325 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 324 CLK_000_P_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 323 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 322 CLK_000_P_SYNC_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_2_ 3 -1 2 1 4 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_1_ 3 -1 5 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_0_ 3 -1 1 1 5 -1 -1 1 0 21 + 308 CLK_000_N_SYNC_11_ 3 -1 5 1 1 -1 -1 1 0 21 + 307 CLK_000_P_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21 + 304 inst_CLK_000_D3 3 -1 1 1 1 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 5 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 27 BGACK_000 1 -1 -1 3 4 5 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +125 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 4 1 3 4 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 356 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 347 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 357 3 0 33 -1 6 0 21 + 65 E 5 354 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 355 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 353 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 358 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 353 RN_AVEC_EXP 3 21 2 5 1 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 5 1 3 5 6 7 -1 -1 1 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 311 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 4 3 4 5 6 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 5 4 1 3 5 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 5 0 21 + 354 RN_E 3 65 6 3 3 5 6 65 -1 4 0 21 + 308 SM_AMIGA_7_ 3 -1 3 3 3 6 7 -1 -1 4 0 21 + 340 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 309 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 2 3 1 2 6 -1 -1 1 0 21 + 304 inst_CLK_000_NE 3 -1 0 3 1 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 3 2 4 7 -1 -1 1 0 21 + 342 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 315 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 2 1 2 -1 -1 3 0 21 + 355 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 316 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 2 0 21 + 295 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 357 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 338 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 339 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 310 SM_AMIGA_0_ 3 -1 3 1 3 -1 -1 2 0 21 + 358 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 336 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_1_ 3 -1 1 1 2 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_6_ 3 -1 5 1 4 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_5_ 3 -1 0 1 5 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 307 CLK_000_N_SYNC_11_ 3 -1 0 1 0 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 4 1 5 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE 3 -1 1 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +125 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 344 7 4 1 3 4 7 81 -1 4 0 21 + 32 AS_000 5 345 3 4 0 4 6 7 32 -1 2 0 21 + 70 RW 5 356 6 3 1 4 7 70 -1 4 0 21 + 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 + 79 RW_000 5 346 7 2 0 6 79 -1 3 0 21 + 97 DS_030 5 347 0 1 2 97 -1 7 0 21 + 80 DSACK1 5 352 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 68 A0 5 -1 6 1 2 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 5 357 3 0 33 -1 6 0 21 + 65 E 5 354 6 0 65 -1 4 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 3 0 21 + 82 BGACK_030 5 349 7 0 82 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 355 3 0 34 -1 2 1 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 5 353 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 5 358 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 2 0 21 + 353 RN_AVEC_EXP 3 21 2 5 1 3 5 6 7 21 -1 1 0 21 + 299 inst_CLK_000_D1 3 -1 7 5 1 3 5 6 7 -1 -1 1 0 21 + 344 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 309 SM_AMIGA_6_ 3 -1 6 4 1 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 4 3 4 5 6 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 5 4 1 3 5 7 -1 -1 1 0 21 + 341 cpu_est_1_ 3 -1 6 3 3 5 6 -1 -1 5 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 5 0 21 + 354 RN_E 3 65 6 3 3 5 6 65 -1 4 0 21 + 308 SM_AMIGA_7_ 3 -1 3 3 3 6 7 -1 -1 4 0 21 + 340 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 310 SM_AMIGA_1_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 305 inst_CLK_OUT_PRE_D 3 -1 2 3 1 2 6 -1 -1 1 0 21 + 304 inst_CLK_000_NE 3 -1 0 3 1 3 5 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 4 3 2 4 7 -1 -1 1 0 21 + 342 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 315 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 2 1 2 -1 -1 3 0 21 + 355 RN_VMA 3 34 3 2 3 5 34 -1 2 1 21 + 316 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 314 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 2 0 21 + 295 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 347 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 357 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 6 0 21 + 338 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 313 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 4 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 339 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 0 21 + 352 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 345 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 337 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 SM_AMIGA_0_ 3 -1 3 1 3 -1 -1 2 0 21 + 358 RN_AMIGA_BUS_ENABLE_LOW 3 19 2 1 7 19 -1 1 0 21 + 336 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_2_ 3 -1 2 1 0 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_1_ 3 -1 1 1 2 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 326 CLK_000_N_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_6_ 3 -1 5 1 4 -1 -1 1 0 21 + 322 CLK_000_N_SYNC_5_ 3 -1 0 1 5 -1 -1 1 0 21 + 321 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 319 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 318 CLK_000_N_SYNC_1_ 3 -1 0 1 4 -1 -1 1 0 21 + 317 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 307 CLK_000_N_SYNC_11_ 3 -1 0 1 0 -1 -1 1 0 21 + 306 CLK_000_P_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 303 inst_CLK_000_D3 3 -1 4 1 5 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE 3 -1 1 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 14 A_28_ 1 -1 -1 1 4 14 -1 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 925b6d9..7b33568 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,111 +8,139 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Sat Jun 07 23:03:24 2014 +; DATE Mon Jun 09 10:27:29 2014 -Pin 85 A_22_ -Pin 94 A_21_ -Pin 93 A_20_ -Pin 97 A_19_ Pin 4 A_31_ -Pin 95 A_18_ -Pin 59 A_17_ -Pin 96 A_16_ Pin 68 IPL_2_ -Pin 56 IPL_1_ Pin 58 FC_1_ -Pin 67 IPL_0_ -Pin 57 FC_0_ -Pin 80 RW_000 Comb ; S6=1 S9=1 Pair 269 -Pin 14 nEXP_SPACE -Pin 41 BERR Comb ; S6=1 S9=1 Pair 200 -Pin 21 BG_030 -Pin 28 BGACK_000 -Pin 64 CLK_030 -Pin 11 CLK_000 -Pin 61 CLK_OSZI -Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 250 -Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173 -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 104 -Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 -Pin 36 VPA -Pin 86 RST -Pin 71 RW Comb ; S6=1 S9=1 Pair 245 -Pin 34 AMIGA_BUS_ENABLE Comb ; S6=1 S9=1 Pair 178 -Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 -Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151 -Pin 47 CIIN Comb ; S6=1 S9=1 Pair 199 Pin 5 A_30_ Pin 6 A_29_ +Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 Pin 15 A_28_ +Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 Pin 16 A_27_ Pin 17 A_26_ +Pin 14 nEXP_SPACE Pin 18 A_25_ +Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 Pin 19 A_24_ +Pin 21 BG_030 Pin 84 A_23_ +Pin 85 A_22_ +Pin 94 A_21_ +Pin 28 BGACK_000 +Pin 93 A_20_ +Pin 64 CLK_030 +Pin 97 A_19_ +Pin 11 CLK_000 +Pin 95 A_18_ +Pin 61 CLK_OSZI +Pin 59 A_17_ +Pin 65 CLK_DIV_OUT Reg ; S6=0 S9=1 Pair 247 +Pin 96 A_16_ +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 272 +Pin 56 IPL_1_ +Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173 +Pin 67 IPL_0_ +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 57 FC_0_ +Pin 36 VPA +Pin 86 RST +Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 +Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 271 -Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 128 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 134 -Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 131 +Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 82 AS_030 Reg ; S6=1 S9=1 Pair 278 Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 179 +Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 +Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101 -Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 182 -Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185 -Pin 69 A0 Reg ; S6=0 S9=1 Pair 257 -Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 176 -Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 +Pin 69 A0 Reg ; S6=1 S9=1 Pair 257 +Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 193 +Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 277 Pin 10 CLK_EXP Reg ; S6=0 S9=1 Pair 125 -Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 272 -Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 281 -Pin 66 E Reg ; S6=1 S9=1 Pair 248 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 +Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 287 +Pin 22 AVEC_EXP Reg ; S6=1 S9=1 Pair 155 +Pin 66 E Reg ; S6=0 S9=1 Pair 251 Pin 35 VMA Reg ; S6=1 S9=1 Pair 175 Pin 3 RESET Reg ; S6=0 S9=1 Pair 127 -Pin 70 SIZE_0_ Reg ; S6=0 S9=1 Pair 247 -Node 269 RN_RW_000 Comb ; S6=1 S9=1 +Pin 71 RW Reg ; S6=1 S9=1 Pair 245 +Pin 34 AMIGA_BUS_ENABLE Reg ; S6=1 S9=1 Pair 181 +Pin 20 AMIGA_BUS_ENABLE_LOW Reg ; S6=1 S9=1 Pair 167 +Node 185 RN_UDS_000 Comb ; S6=1 S9=1 +Node 191 RN_LDS_000 Comb ; S6=1 S9=1 Node 173 RN_DTACK Comb ; S6=1 S9=1 -Node 245 RN_RW Comb ; S6=1 S9=1 Node 271 RN_SIZE_1_ Reg ; S6=1 S9=1 -Node 128 RN_IPL_030_2_ Reg ; S6=1 S9=1 -Node 134 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 131 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 278 RN_AS_030 Reg ; S6=1 S9=1 Node 179 RN_AS_000 Reg ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 +Node 269 RN_RW_000 Reg ; S6=1 S9=1 Node 101 RN_DS_030 Reg ; S6=1 S9=1 -Node 182 RN_UDS_000 Reg ; S6=1 S9=1 -Node 185 RN_LDS_000 Reg ; S6=1 S9=1 -Node 257 RN_A0 Reg ; S6=0 S9=1 -Node 176 RN_BG_000 Reg ; S6=1 S9=1 -Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 -Node 272 RN_FPU_CS Reg ; S6=1 S9=1 -Node 281 RN_DSACK1 Reg ; S6=1 S9=1 -Node 248 RN_E Reg ; S6=1 S9=1 +Node 257 RN_A0 Reg ; S6=1 S9=1 +Node 193 RN_BG_000 Reg ; S6=1 S9=1 +Node 277 RN_BGACK_030 Reg ; S6=1 S9=1 +Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 287 RN_DSACK1 Reg ; S6=1 S9=1 +Node 155 RN_AVEC_EXP Reg ; S6=1 S9=1 +Node 251 RN_E Reg ; S6=0 S9=1 Node 175 RN_VMA Reg ; S6=1 S9=1 -Node 247 RN_SIZE_0_ Reg ; S6=0 S9=1 -Node 251 inst_avec_expreg Reg ; S6=0 S9=1 -Node 280 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 139 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 106 inst_VPA_D Reg ; S6=1 S9=1 -Node 287 inst_CLK_OUT_PRE_50_D Reg ; S6=0 S9=1 -Node 274 inst_CLK_000_D0 Reg ; S6=1 S9=1 -Node 181 inst_CLK_000_D1 Reg ; S6=1 S9=1 -Node 137 inst_DTACK_D0 Reg ; S6=1 S9=1 -Node 286 inst_CLK_OUT_PRE_50 Reg ; S6=0 S9=1 -Node 136 inst_CLK_OUT_PRE_25 Reg ; S6=0 S9=1 -Node 130 SM_AMIGA_1_ Reg ; S6=0 S9=1 -Node 254 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 283 SM_AMIGA_0_ Reg ; S6=0 S9=1 -Node 277 SM_AMIGA_7_ Reg ; S6=1 S9=1 -Node 253 inst_RW_000_INT Reg ; S6=0 S9=1 -Node 284 inst_CLK_000_D2 Reg ; S6=1 S9=1 -Node 133 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 190 SM_AMIGA_5_ Reg ; S6=0 S9=1 -Node 109 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 107 SM_AMIGA_3_ Reg ; S6=0 S9=1 -Node 103 SM_AMIGA_2_ Reg ; S6=0 S9=1 -Node 188 cpu_est_0_ Reg ; S6=0 S9=1 -Node 184 cpu_est_1_ Reg ; S6=0 S9=1 -Node 187 cpu_est_2_ Reg ; S6=0 S9=1 +Node 245 RN_RW Reg ; S6=1 S9=1 +Node 181 RN_AMIGA_BUS_ENABLE Reg ; S6=1 S9=1 +Node 167 RN_AMIGA_BUS_ENABLE_LOW Reg ; S6=1 S9=1 +Node 275 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 284 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 +Node 248 inst_VPA_D Reg ; S6=1 S9=1 +Node 289 inst_CLK_OUT_PRE_50_D Reg ; S6=0 S9=1 +Node 140 inst_CLK_OUT_PRE Reg ; S6=0 S9=1 +Node 221 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 283 inst_CLK_000_D1 Reg ; S6=1 S9=1 +Node 209 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 151 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1 +Node 187 inst_CLK_000_D2 Reg ; S6=1 S9=1 +Node 211 inst_CLK_000_D3 Reg ; S6=0 S9=1 +Node 113 inst_CLK_000_NE Reg ; S6=0 S9=1 +Node 161 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 134 CLK_000_P_SYNC_9_ Reg ; S6=0 S9=1 +Node 116 CLK_000_N_SYNC_11_ Reg ; S6=0 S9=1 +Node 176 SM_AMIGA_7_ Reg ; S6=1 S9=1 +Node 253 SM_AMIGA_6_ Reg ; S6=0 S9=1 +Node 233 SM_AMIGA_1_ Reg ; S6=0 S9=1 +Node 182 SM_AMIGA_0_ Reg ; S6=0 S9=1 +Node 139 SM_AMIGA_4_ Reg ; S6=0 S9=1 +Node 119 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 163 inst_LDS_000_INT Reg ; S6=0 S9=1 +Node 133 inst_DS_000_ENABLE Reg ; S6=0 S9=1 +Node 157 inst_UDS_000_INT Reg ; S6=0 S9=1 +Node 230 CLK_000_N_SYNC_0_ Reg ; S6=0 S9=1 +Node 110 CLK_000_N_SYNC_1_ Reg ; S6=0 S9=1 +Node 205 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 +Node 170 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 +Node 104 CLK_000_N_SYNC_4_ Reg ; S6=0 S9=1 +Node 121 CLK_000_N_SYNC_5_ Reg ; S6=0 S9=1 +Node 224 CLK_000_N_SYNC_6_ Reg ; S6=0 S9=1 +Node 199 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 +Node 164 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 +Node 241 CLK_000_N_SYNC_9_ Reg ; S6=0 S9=1 +Node 115 CLK_000_N_SYNC_10_ Reg ; S6=0 S9=1 +Node 235 CLK_000_P_SYNC_0_ Reg ; S6=0 S9=1 +Node 128 CLK_000_P_SYNC_1_ Reg ; S6=0 S9=1 +Node 158 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 +Node 109 CLK_000_P_SYNC_3_ Reg ; S6=0 S9=1 +Node 254 CLK_000_P_SYNC_4_ Reg ; S6=0 S9=1 +Node 152 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 +Node 169 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 +Node 103 CLK_000_P_SYNC_7_ Reg ; S6=0 S9=1 +Node 229 CLK_000_P_SYNC_8_ Reg ; S6=0 S9=1 +Node 145 SM_AMIGA_5_ Reg ; S6=0 S9=1 +Node 239 SM_AMIGA_3_ Reg ; S6=0 S9=1 +Node 223 SM_AMIGA_2_ Reg ; S6=0 S9=1 +Node 227 cpu_est_0_ Reg ; S6=0 S9=1 +Node 259 cpu_est_1_ Reg ; S6=0 S9=1 +Node 265 cpu_est_2_ Reg ; S6=0 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index c095a36..4fcf6c3 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,13 +5,13 @@ |--------------------------------------------| -Start: Sat Jun 07 23:03:24 2014 -End : Sat Jun 07 23:03:24 2014 $$$ Elapsed time: 00:00:00 +Start: Mon Jun 09 10:27:29 2014 +End : Mon Jun 09 10:27:29 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] -* Place/Route options (keycode = 16386) - = Spread Placement: OFF +* Place/Route options (keycode = 540674) + = Spread Placement: ON = No. Routing Attempts/Placement 2 * Placement Completion @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 6 | 6 => 100% | 8 | 7 => 87% | 33 | 23 => 69% - 1 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 22 => 66% - 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% - 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 29 => 87% - 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 17 => 51% - 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% - 6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 27 => 81% - 7 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 28 => 84% + 0 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 19 => 57% + 1 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 21 => 63% + 2 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 18 => 54% + 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 31 => 93% + 4 | 16 | 7 | 7 => 100% | 8 | 3 => 37% | 33 | 29 => 87% + 5 | 16 | 10 | 10 => 100% | 8 | 4 => 50% | 33 | 21 => 63% + 6 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 23 => 69% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 28 => 84% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 21.00 => 63% + | Avg number of array inputs in used blocks : 23.75 => 71% * Input/Clock Signal count: 29 -> placed: 29 = 100% @@ -40,14 +40,14 @@ _|____|____|____|_______________|____|_____________|___|________________ I/O Pins : 64 53 => 82% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% - Logic Blocks : 8 7 => 87% - Macrocells : 128 54 => 42% - PT Clusters : 128 40 => 31% - - Single PT Clusters : 128 22 => 17% + Logic Blocks : 8 8 => 100% + Macrocells : 128 80 => 62% + PT Clusters : 128 35 => 27% + - Single PT Clusters : 128 47 => 36% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 97] Route [ 0] +* Attempts: Place [ 550] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -57,20 +57,23 @@ _|____|____|____|_______________|____|_____________|___|________________ | | | +- Signal-to-Pin Assignment | | | | Fanout to Logic Blocks Signal Name ___|__|__|____|____________________________________________________________ - 1| 6| IO| 69|=> ...3|....| A0 + 1| 6| IO| 69|=> ..2.|....| A0 2| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR - 3| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE - 4| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 5| 3| IO| 33|=> 01..|4.67| AS_000 + 3| 3| IO| 34|=> ....|....| AMIGA_BUS_ENABLE + |=> Paired w/: RN_AMIGA_BUS_ENABLE + 4| 2| IO| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW + |=> Paired w/: RN_AMIGA_BUS_ENABLE_LOW + 5| 3| IO| 33|=> 0...|4.67| AS_000 |=> Paired w/: RN_AS_000 - 6| 7| IO| 82|=> ...3|..67| AS_030 + 6| 7| IO| 82|=> .1.3|4..7| AS_030 |=> Paired w/: RN_AS_030 7| 0|OUT| 92|=> ....|....| AVEC - 8| 2|OUT| 22|=> ....|....| AVEC_EXP - 9| 0|INP| 96|=> ....|...7| A_16_ - 10| 5|INP| 59|=> ....|...7| A_17_ - 11| 0|INP| 95|=> ....|...7| A_18_ - 12| 0|INP| 97|=> ....|...7| A_19_ + 8| 2| IO| 22|=> ....|....| AVEC_EXP + |=> Paired w/: RN_AVEC_EXP + 9| 0|INP| 96|=> ....|4..7| A_16_ + 10| 5|INP| 59|=> ....|4..7| A_17_ + 11| 0|INP| 95|=> ....|4..7| A_18_ + 12| 0|INP| 97|=> ....|4..7| A_19_ 13| 0|INP| 93|=> ....|4...| A_20_ 14| 0|INP| 94|=> ....|4...| A_21_ 15| 7|INP| 85|=> ....|4...| A_22_ @@ -84,104 +87,133 @@ ___|__|__|____|____________________________________________________________ 23| 1|INP| 5|=> ....|4...| A_30_ 24| 1|INP| 4|=> ....|4...| A_31_ 25| 4|OUT| 41|=> ....|....| BERR - 26| 3|INP| 28|=> ....|...7| BGACK_000 + 26| 3|INP| 28|=> ....|4..7| BGACK_000 27| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 28| 3| IO| 29|=> ....|....| BG_000 |=> Paired w/: RN_BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN - 31| +|INP| 11|=> ...3|...7| CLK_000 - 32| +|INP| 64|=> 01..|..67| CLK_030 - 33| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 34| 1|OUT| 10|=> ....|....| CLK_EXP - 35| +|Cin| 61|=> ....|....| CLK_OSZI - 36| 7| IO| 81|=> ...3|....| DSACK1 + 31| +|INP| 11|=> ...3|.5..| CLK_000 + 32| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_ + 33| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_10_ + 34| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_11_ + 35| 0|NOD| . |=> ....|4...| CLK_000_N_SYNC_1_ + 36| 4|NOD| . |=> ..2.|....| CLK_000_N_SYNC_2_ + 37| 2|NOD| . |=> 0...|....| CLK_000_N_SYNC_3_ + 38| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_4_ + 39| 0|NOD| . |=> ....|.5..| CLK_000_N_SYNC_5_ + 40| 5|NOD| . |=> ....|4...| CLK_000_N_SYNC_6_ + 41| 4|NOD| . |=> ..2.|....| CLK_000_N_SYNC_7_ + 42| 2|NOD| . |=> ....|.5..| CLK_000_N_SYNC_8_ + 43| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_9_ + 44| 5|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_ + 45| 1|NOD| . |=> ..2.|....| CLK_000_P_SYNC_1_ + 46| 2|NOD| . |=> 0...|....| CLK_000_P_SYNC_2_ + 47| 0|NOD| . |=> ....|..6.| CLK_000_P_SYNC_3_ + 48| 6|NOD| . |=> ..2.|....| CLK_000_P_SYNC_4_ + 49| 2|NOD| . |=> ..2.|....| CLK_000_P_SYNC_5_ + 50| 2|NOD| . |=> 0...|....| CLK_000_P_SYNC_6_ + 51| 0|NOD| . |=> ....|.5..| CLK_000_P_SYNC_7_ + 52| 5|NOD| . |=> .1..|....| CLK_000_P_SYNC_8_ + 53| 1|NOD| . |=> ..2.|....| CLK_000_P_SYNC_9_ + 54| +|INP| 64|=> 0...|..67| CLK_030 + 55| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 56| 1|OUT| 10|=> ....|....| CLK_EXP + 57| +|Cin| 61|=> ....|....| CLK_OSZI + 58| 7| IO| 81|=> ...3|....| DSACK1 |=> Paired w/: RN_DSACK1 - 37| 0| IO| 98|=> ...3|....| DS_030 + 59| 0| IO| 98|=> ..2.|....| DS_030 |=> Paired w/: RN_DS_030 - 38| 3| IO| 30|=> .1..|....| DTACK - 39| 6| IO| 66|=> ....|....| E + 60| 3| IO| 30|=> ....|.5..| DTACK + 61| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 40| 5|INP| 57|=> ....|...7| FC_0_ - 41| 5|INP| 58|=> ....|...7| FC_1_ - 42| 7| IO| 78|=> ....|....| FPU_CS - |=> Paired w/: RN_FPU_CS - 43| 1| IO| 8|=> ....|....| IPL_030_0_ + 62| 5|INP| 57|=> ....|4..7| FC_0_ + 63| 5|INP| 58|=> ....|4..7| FC_1_ + 64| 7|OUT| 78|=> ....|....| FPU_CS + 65| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 44| 1| IO| 7|=> ....|....| IPL_030_1_ + 66| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 45| 1| IO| 9|=> ....|....| IPL_030_2_ + 67| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 46| 6|INP| 67|=> .1..|....| IPL_0_ - 47| 5|INP| 56|=> .1..|....| IPL_1_ - 48| 6|INP| 68|=> .1..|....| IPL_2_ - 49| 3| IO| 31|=> 01..|..67| LDS_000 - |=> Paired w/: RN_LDS_000 - 50| 1|OUT| 3|=> ....|....| RESET - 51| 3|NOD| . |=> ...3|....| RN_AS_000 + 68| 6|INP| 67|=> .1..|....| IPL_0_ + 69| 5|INP| 56|=> .1..|....| IPL_1_ + 70| 6|INP| 68|=> .1..|....| IPL_2_ + 71| 3| IO| 31|=> 0...|..67| LDS_000 + 72| 1|OUT| 3|=> ....|....| RESET + 73| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE + |=> Paired w/: AMIGA_BUS_ENABLE + 74| 2|NOD| . |=> ....|...7| RN_AMIGA_BUS_ENABLE_LOW + |=> Paired w/: AMIGA_BUS_ENABLE_LOW + 75| 3|NOD| . |=> ...3|....| RN_AS_000 |=> Paired w/: AS_000 - 52| 7|NOD| . |=> 01.3|..67| RN_AS_030 + 76| 7|NOD| . |=> 0..3|..67| RN_AS_030 |=> Paired w/: AS_030 - 53| 7|NOD| . |=> 01.3|4.67| RN_BGACK_030 + 77| 2|NOD| . |=> .1.3|.567| RN_AVEC_EXP + |=> Paired w/: AVEC_EXP + 78| 7|NOD| . |=> 0..3|4.67| RN_BGACK_030 |=> Paired w/: BGACK_030 - 54| 3|NOD| . |=> ...3|....| RN_BG_000 + 79| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 55| 7|NOD| . |=> ....|...7| RN_DSACK1 + 80| 7|NOD| . |=> ....|...7| RN_DSACK1 |=> Paired w/: DSACK1 - 56| 0|NOD| . |=> 0...|....| RN_DS_030 + 81| 0|NOD| . |=> 0...|....| RN_DS_030 |=> Paired w/: DS_030 - 57| 6|NOD| . |=> 0..3|..6.| RN_E + 82| 6|NOD| . |=> ...3|.56.| RN_E |=> Paired w/: E - 58| 7|NOD| . |=> ....|4..7| RN_FPU_CS - |=> Paired w/: FPU_CS - 59| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 83| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 60| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 84| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 61| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 85| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 62| 3|NOD| . |=> ...3|....| RN_LDS_000 - |=> Paired w/: LDS_000 - 63| 3|NOD| . |=> ...3|....| RN_UDS_000 - |=> Paired w/: UDS_000 - 64| 3|NOD| . |=> 0..3|....| RN_VMA + 86| 6|NOD| . |=> ....|..6.| RN_RW + |=> Paired w/: RW + 87| 7|NOD| . |=> ....|...7| RN_RW_000 + |=> Paired w/: RW_000 + 88| 3|NOD| . |=> ...3|.5..| RN_VMA |=> Paired w/: VMA - 65| +|INP| 86|=> 01.3|..67| RST - 66| 6| IO| 71|=> ...3|4.6.| RW - 67| 7| IO| 80|=> 0...|..6.| RW_000 - 68| 6| IO| 70|=> ...3|....| SIZE_0_ - 69| 7| IO| 79|=> ...3|....| SIZE_1_ - 70| 7|NOD| . |=> ....|..67| SM_AMIGA_0_ - 71| 1|NOD| . |=> .1..|..67| SM_AMIGA_1_ - 72| 0|NOD| . |=> 01..|....| SM_AMIGA_2_ - 73| 0|NOD| . |=> 0...|....| SM_AMIGA_3_ - 74| 0|NOD| . |=> 0...|....| SM_AMIGA_4_ - 75| 3|NOD| . |=> 0..3|....| SM_AMIGA_5_ - 76| 6|NOD| . |=> ...3|..6.| SM_AMIGA_6_ - 77| 7|NOD| . |=> ...3|..67| SM_AMIGA_7_ - 78| 3| IO| 32|=> 01..|..67| UDS_000 - |=> Paired w/: RN_UDS_000 - 79| 3| IO| 35|=> ....|....| VMA + 89| +|INP| 86|=> 0123|4567| RST + 90| 6| IO| 71|=> .1..|4..7| RW + |=> Paired w/: RN_RW + 91| 7| IO| 80|=> 0...|..6.| RW_000 + |=> Paired w/: RN_RW_000 + 92| 6| IO| 70|=> ..2.|....| SIZE_0_ + 93| 7| IO| 79|=> ..2.|....| SIZE_1_ + 94| 3|NOD| . |=> ...3|....| SM_AMIGA_0_ + 95| 5|NOD| . |=> ...3|.5.7| SM_AMIGA_1_ + 96| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ + 97| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ + 98| 1|NOD| . |=> .1..|.5..| SM_AMIGA_4_ + 99| 1|NOD| . |=> .1..|....| SM_AMIGA_5_ + 100| 6|NOD| . |=> .1.3|..67| SM_AMIGA_6_ + 101| 3|NOD| . |=> ...3|..67| SM_AMIGA_7_ + 102| 3| IO| 32|=> 0...|..67| UDS_000 + 103| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 80| +|INP| 36|=> 0...|....| VPA - 81| 3|NOD| . |=> ...3|..6.| cpu_est_0_ - 82| 3|NOD| . |=> 0..3|..6.| cpu_est_1_ - 83| 3|NOD| . |=> ...3|..6.| cpu_est_2_ - 84| 7|NOD| . |=> ....|..67| inst_AS_030_000_SYNC - 85| 1|NOD| . |=> ....|..6.| inst_BGACK_030_INT_D - 86| 7|NOD| . |=> 01.3|..67| inst_CLK_000_D0 - 87| 3|NOD| . |=> 01.3|..67| inst_CLK_000_D1 - 88| 7|NOD| . |=> ....|..67| inst_CLK_000_D2 - 89| 1|NOD| . |=> 01..|....| inst_CLK_030_H - 90| 1|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_25 - 91| 7|NOD| . |=> .1..|...7| inst_CLK_OUT_PRE_50 - 92| 7|NOD| . |=> .1..|....| inst_CLK_OUT_PRE_50_D - 93| 1|NOD| . |=> 0...|....| inst_DTACK_D0 - 94| 6|NOD| . |=> ....|..67| inst_RW_000_INT - 95| 0|NOD| . |=> 0..3|....| inst_VPA_D - 96| 6|NOD| . |=> ..23|..6.| inst_avec_expreg - 97| +|INP| 14|=> 0..3|4.67| nEXP_SPACE + 104| +|INP| 36|=> ....|..6.| VPA + 105| 5|NOD| . |=> ...3|.56.| cpu_est_0_ + 106| 6|NOD| . |=> ...3|.56.| cpu_est_1_ + 107| 6|NOD| . |=> ...3|..6.| cpu_est_2_ + 108| 7|NOD| . |=> ...3|..67| inst_AS_030_000_SYNC + 109| 7|NOD| . |=> ...3|....| inst_BGACK_030_INT_D + 110| 5|NOD| . |=> .1.3|.5.7| inst_CLK_000_D0 + 111| 7|NOD| . |=> .1.3|.567| inst_CLK_000_D1 + 112| 3|NOD| . |=> ...3|456.| inst_CLK_000_D2 + 113| 4|NOD| . |=> ....|.5..| inst_CLK_000_D3 + 114| 0|NOD| . |=> .1.3|.5..| inst_CLK_000_NE + 115| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 116| 1|NOD| . |=> ..2.|....| inst_CLK_OUT_PRE + 117| 2|NOD| . |=> .12.|....| inst_CLK_OUT_PRE_25 + 118| 4|NOD| . |=> ..2.|4..7| inst_CLK_OUT_PRE_50 + 119| 7|NOD| . |=> ..2.|....| inst_CLK_OUT_PRE_50_D + 120| 2|NOD| . |=> .12.|..6.| inst_CLK_OUT_PRE_D + 121| 1|NOD| . |=> .1.3|....| inst_DS_000_ENABLE + 122| 2|NOD| . |=> ..23|....| inst_LDS_000_INT + 123| 2|NOD| . |=> ..23|....| inst_UDS_000_INT + 124| 6|NOD| . |=> ...3|.5..| inst_VPA_D + 125| +|INP| 14|=> 0..3|4.67| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -302,19 +334,19 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030| IO| | S | 7 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free - 2| AVEC|OUT| | S | 1 | 4 to [ 0]| 1 XOR to [ 2] for 1 PT sig - 3| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| SM_AMIGA_3_|NOD| | S | 4 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6| | ? | | S | | 4 free | 1 XOR free + 1|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 to [ 0]| 1 XOR to [ 1] for 1 PT sig + 2|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_000_NE|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free +12|inst_CLK_030_H|NOD| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT +13|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -328,21 +360,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DS_030| IO| | S | 7 |=> can support up to [ 9] logic PT(s) - 1| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 2| AVEC|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 3| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| SM_AMIGA_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) - 5| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) - 6| | ? | | S | |=> can support up to [ 15] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) + 0| DS_030| IO| | S | 7 |=> can support up to [ 13] logic PT(s) + 1|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 2|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 17] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 18] logic PT(s) + 5|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 6|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 17] logic PT(s) + 8|inst_CLK_000_NE|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 9|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +10|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12|inst_CLK_030_H|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) +13|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -354,19 +386,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1| SM_AMIGA_2_|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2| AVEC|OUT| | => | 6 7 0 ( 1)| 97 98 91 ( 92) - 3| inst_VPA_D|NOD| | => | 6 7 0 1 | 97 98 91 92 - 4| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 98 91 92 93 - 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6| | | | => | 0 1 2 3 | 91 92 93 94 + 1|CLK_000_P_SYNC_7_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2|CLK_000_N_SYNC_4_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 3| | | | => | 6 7 0 1 | 97 98 91 92 + 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 + 5|CLK_000_P_SYNC_3_|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6|CLK_000_N_SYNC_1_|NOD| | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| | | | => | 1 2 3 4 | 92 93 94 95 - 9| | | | => | 1 2 3 4 | 92 93 94 95 -10| | | | => | 2 3 4 5 | 93 94 95 96 + 8|inst_CLK_000_NE|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9|CLK_000_N_SYNC_10_|NOD| | => | 1 2 3 4 | 92 93 94 95 +10|CLK_000_N_SYNC_11_|NOD| | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 -12| | | | => | 3 4 5 6 | 94 95 96 97 -13| | | | => | 3 4 5 6 | 94 95 96 97 +12|inst_CLK_030_H|NOD| | => | 3 4 5 6 | 94 95 96 97 +13|CLK_000_N_SYNC_5_|NOD| | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- @@ -380,7 +412,7 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| | | | 91| => | 0 1 2 3 4 5 6 7 - 1| AVEC|OUT|*| 92| => | ( 2) 3 4 5 6 7 8 9 + 1| AVEC|OUT|*| 92| => | 2 3 ( 4) 5 6 7 8 9 2| A_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 3| A_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 @@ -419,37 +451,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] [MCell 0 |101|NOD RN_DS_030| |*] paired w/[ DS_030] - [MCell 1 |103|NOD SM_AMIGA_2_| |*] + [MCell 1 |103|NOD CLK_000_P_SYNC_7_| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|OUT AVEC| | ] - [MCell 3 |106|NOD inst_VPA_D| |*] + [MCell 2 |104|NOD CLK_000_N_SYNC_4_| |*] + [MCell 3 |106| -| | ] 2 [IOpin 2 | 93|INP A_20_|*|*] [RegIn 2 |108| -| | ] - [MCell 4 |107|NOD SM_AMIGA_3_| |*] - [MCell 5 |109|NOD SM_AMIGA_4_| |*] + [MCell 4 |107|OUT AVEC| | ] + [MCell 5 |109|NOD CLK_000_P_SYNC_3_| |*] 3 [IOpin 3 | 94|INP A_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110| -| | ] + [MCell 6 |110|NOD CLK_000_N_SYNC_1_| |*] [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113| -| | ] - [MCell 9 |115| -| | ] + [MCell 8 |113|NOD inst_CLK_000_NE| |*] + [MCell 9 |115|NOD CLK_000_N_SYNC_10_| |*] 5 [IOpin 5 | 96|INP A_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116| -| | ] + [MCell 10 |116|NOD CLK_000_N_SYNC_11_| |*] [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119| -| | ] - [MCell 13 |121| -| | ] + [MCell 12 |119|NOD inst_CLK_030_H| |*] + [MCell 13 |121|NOD CLK_000_N_SYNC_5_| |*] 7 [IOpin 7 | 98| IO DS_030|*|*] paired w/[ RN_DS_030] [RegIn 7 |123| -| | ] @@ -463,35 +495,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| Mcel 0 4 ( 107)| SM_AMIGA_3_ -Mux02| Mcel 0 5 ( 109)| SM_AMIGA_4_ -Mux03| Mcel 3 11 ( 190)| SM_AMIGA_5_ +Mux01| Mcel 5 6 ( 230)| CLK_000_N_SYNC_0_ +Mux02| Mcel 0 9 ( 115)| CLK_000_N_SYNC_10_ +Mux03| ... | ... Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D1 -Mux08| Mcel 1 8 ( 137)| inst_DTACK_D0 -Mux09| Mcel 0 1 ( 103)| SM_AMIGA_2_ -Mux10| Input Pin ( 36)| VPA -Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D0 +Mux06| Mcel 5 13 ( 241)| CLK_000_N_SYNC_9_ +Mux07| Mcel 2 14 ( 170)| CLK_000_N_SYNC_3_ +Mux08| Mcel 0 10 ( 116)| CLK_000_N_SYNC_11_ +Mux09| Mcel 2 6 ( 158)| CLK_000_P_SYNC_2_ +Mux10| ... | ... +Mux11| Mcel 2 13 ( 169)| CLK_000_P_SYNC_6_ Mux12| IOPin 3 3 ( 32)| UDS_000 -Mux13| Mcel 3 7 ( 184)| cpu_est_1_ +Mux13| Mcel 7 5 ( 277)| RN_BGACK_030 Mux14| ... | ... -Mux15| Mcel 0 0 ( 101)| RN_DS_030 +Mux15| Mcel 0 12 ( 119)| inst_CLK_030_H Mux16| ... | ... -Mux17| Mcel 3 1 ( 175)| RN_VMA +Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux20| ... | ... Mux21| Mcel 7 6 ( 278)| RN_AS_030 -Mux22| ... | ... -Mux23| Mcel 6 2 ( 248)| RN_E +Mux22| Mcel 0 2 ( 104)| CLK_000_N_SYNC_4_ +Mux23| IOPin 3 2 ( 33)| AS_000 Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 0 3 ( 106)| inst_VPA_D -Mux26| IOPin 3 2 ( 33)| AS_000 +Mux25| ... | ... +Mux26| ... | ... Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| inst_CLK_030_H -Mux29| ... | ... +Mux28| IOPin 7 5 ( 80)| RW_000 +Mux29| Mcel 0 0 ( 101)| RN_DS_030 Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... @@ -508,18 +540,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| IPL_030_2_| IO| | S | 3 | 4 to [ 2]| 1 XOR free - 3| SM_AMIGA_1_|NOD| | S | 2 | 4 to [ 3]| 1 XOR free - 4| IPL_030_0_| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5|inst_CLK_030_H|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| IPL_030_1_| IO| | S | 3 | 4 to [ 6]| 1 XOR free - 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 | 4 to [ 7]| 1 XOR free - 8| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig -10| | ? | | S | | 4 free | 1 XOR free + 2|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| IPL_030_2_| IO| | S | 3 | 4 to [ 4]| 1 XOR free + 5|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| IPL_030_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free + 9| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10|inst_CLK_OUT_PRE|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free +12| IPL_030_1_| IO| | S | 3 | 4 to [12]| 1 XOR free +13| SM_AMIGA_5_|NOD| | S | 2 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -533,21 +565,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| RESET|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 2| IPL_030_2_| IO| | S | 3 |=> can support up to [ 9] logic PT(s) - 3| SM_AMIGA_1_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) - 4| IPL_030_0_| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 5|inst_CLK_030_H|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) - 6| IPL_030_1_| IO| | S | 3 |=> can support up to [ 9] logic PT(s) - 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) - 8| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 9|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 19] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) + 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 1| RESET|OUT| | S | 1 |=> can support up to [ 18] logic PT(s) + 2|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 14] logic PT(s) + 5|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 6|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 14] logic PT(s) + 9| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) +10|inst_CLK_OUT_PRE|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -560,18 +592,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 - 2| IPL_030_2_| IO| | => | 6 7 0 ( 1)| 4 3 10 ( 9) - 3| SM_AMIGA_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 - 4| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) - 5|inst_CLK_030_H|NOD| | => | 7 0 1 2 | 3 10 9 8 - 6| IPL_030_1_| IO| | => | 0 1 2 ( 3)| 10 9 8 ( 7) - 7|inst_CLK_OUT_PRE_25|NOD| | => | 0 1 2 3 | 10 9 8 7 - 8| inst_DTACK_D0|NOD| | => | 1 2 3 4 | 9 8 7 6 - 9|inst_BGACK_030_INT_D|NOD| | => | 1 2 3 4 | 9 8 7 6 -10| | | | => | 2 3 4 5 | 8 7 6 5 + 2|CLK_000_P_SYNC_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 3| | | | => | 6 7 0 1 | 4 3 10 9 + 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 + 5|inst_DS_000_ENABLE|NOD| | => | 7 0 1 2 | 3 10 9 8 + 6|CLK_000_P_SYNC_9_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 7| | | | => | 0 1 2 3 | 10 9 8 7 + 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 + 9| SM_AMIGA_4_|NOD| | => | 1 2 3 4 | 9 8 7 6 +10|inst_CLK_OUT_PRE|NOD| | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 -12| | | | => | 3 4 5 6 | 7 6 5 4 -13| | | | => | 3 4 5 6 | 7 6 5 4 +12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 +13| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- @@ -585,9 +617,9 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| CLK_EXP|OUT|*| 10| => | ( 0) 1 2 3 4 5 6 7 - 1| IPL_030_2_| IO|*| 9| => | ( 2) 3 4 5 6 7 8 9 - 2| IPL_030_0_| IO|*| 8| => | ( 4) 5 6 7 8 9 10 11 - 3| IPL_030_1_| IO|*| 7| => | ( 6) 7 8 9 10 11 12 13 + 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 + 2| IPL_030_0_| IO|*| 8| => | 4 5 6 7 ( 8) 9 10 11 + 3| IPL_030_1_| IO|*| 7| => | 6 7 8 9 10 11 (12) 13 4| A_29_|INP|*| 6| => | 8 9 10 11 12 13 14 15 5| A_30_|INP|*| 5| => | 10 11 12 13 14 15 0 1 6| A_31_|INP|*| 4| => | 12 13 14 15 0 1 2 3 @@ -630,33 +662,33 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 3 |130|NOD SM_AMIGA_1_| |*] + [MCell 2 |128|NOD CLK_000_P_SYNC_1_| |*] + [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] - [MCell 4 |131|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 5 |133|NOD inst_CLK_030_H| |*] + [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] + [MCell 5 |133|NOD inst_DS_000_ENABLE| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 7 |136|NOD inst_CLK_OUT_PRE_25| |*] + [MCell 6 |134|NOD CLK_000_P_SYNC_9_| |*] + [MCell 7 |136| -| | ] 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] - [MCell 8 |137|NOD inst_DTACK_D0| |*] - [MCell 9 |139|NOD inst_BGACK_030_INT_D| |*] + [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] + [MCell 9 |139|NOD SM_AMIGA_4_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140| -| | ] + [MCell 10 |140|NOD inst_CLK_OUT_PRE| |*] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] - [MCell 12 |143| -| | ] - [MCell 13 |145| -| | ] + [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] + [MCell 13 |145|NOD SM_AMIGA_5_| |*] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] @@ -669,39 +701,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 3 4 ( 31)| LDS_000 -Mux01| Mcel 7 11 ( 286)| inst_CLK_OUT_PRE_50 -Mux02| Mcel 1 6 ( 134)| RN_IPL_030_1_ +Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux01| Mcel 5 9 ( 235)| CLK_000_P_SYNC_0_ +Mux02| ... | ... Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| Mcel 1 3 ( 130)| SM_AMIGA_1_ -Mux06| ... | ... -Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D1 -Mux08| Mcel 7 12 ( 287)| inst_CLK_OUT_PRE_50_D -Mux09| Mcel 0 1 ( 103)| SM_AMIGA_2_ -Mux10| Mcel 1 2 ( 128)| RN_IPL_030_2_ -Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D0 -Mux12| IOPin 3 3 ( 32)| UDS_000 +Mux05| Mcel 5 0 ( 221)| inst_CLK_000_D0 +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_4_ +Mux07| Mcel 2 8 ( 161)| inst_CLK_OUT_PRE_D +Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ +Mux09| Mcel 5 5 ( 229)| CLK_000_P_SYNC_8_ +Mux10| Mcel 1 13 ( 145)| SM_AMIGA_5_ +Mux11| Mcel 7 9 ( 283)| inst_CLK_000_D1 +Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ Mux13| ... | ... -Mux14| IOPin 3 5 ( 30)| DTACK +Mux14| Mcel 2 4 ( 155)| RN_AVEC_EXP Mux15| ... | ... -Mux16| IOPin 6 2 ( 67)| IPL_0_ +Mux16| ... | ... Mux17| ... | ... -Mux18| ... | ... -Mux19| ... | ... -Mux20| Input Pin ( 64)| CLK_030 +Mux18| Mcel 0 8 ( 113)| inst_CLK_000_NE +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| ... | ... Mux21| Input Pin ( 86)| RST -Mux22| ... | ... -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25 -Mux25| ... | ... -Mux26| IOPin 3 2 ( 33)| AS_000 -Mux27| Mcel 1 4 ( 131)| RN_IPL_030_0_ -Mux28| Mcel 1 5 ( 133)| inst_CLK_030_H +Mux22| Mcel 2 1 ( 151)| inst_CLK_OUT_PRE_25 +Mux23| ... | ... +Mux24| ... | ... +Mux25| IOPin 6 6 ( 71)| RW +Mux26| ... | ... +Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ +Mux28| Mcel 1 5 ( 133)| inst_DS_000_ENABLE Mux29| ... | ... -Mux30| Mcel 7 6 ( 278)| RN_AS_030 +Mux30| ... | ... Mux31| ... | ... -Mux32| ... | ... +Mux32| Mcel 6 5 ( 253)| SM_AMIGA_6_ --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Macrocell (MCell) Cluster Assignments @@ -713,21 +745,21 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| AVEC_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| | ? | | S | | 4 free | 1 XOR free + 0| | ? | | S | | 4 free | 1 XOR free + 1|inst_CLK_OUT_PRE_25|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free - 4| | ? | | S | | 4 free | 1 XOR free - 5| | ? | | S | | 4 free | 1 XOR free - 6| | ? | | S | | 4 free | 1 XOR free + 4| AVEC_EXP| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_LDS_000_INT|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free -14| | ? | | S | | 4 free | 1 XOR free +12|AMIGA_BUS_ENABLE_LOW| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -740,22 +772,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| AVEC_EXP|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) - 2| | ? | | S | |=> can support up to [ 19] logic PT(s) - 3| | ? | | S | |=> can support up to [ 20] logic PT(s) - 4| | ? | | S | |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 20] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0| | ? | | S | |=> can support up to [ 9] logic PT(s) + 1|inst_CLK_OUT_PRE_25|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) + 2|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4| AVEC_EXP| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 5|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 6|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 9|inst_LDS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) +10|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 17] logic PT(s) +12|AMIGA_BUS_ENABLE_LOW| IO| | S | 1 |=> can support up to [ 18] logic PT(s) +13|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +14|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -765,21 +797,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 2] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| AVEC_EXP|OUT| | => | 5 6 ( 7) 0 | 20 21 ( 22) 15 - 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2| | | | => | 6 7 0 1 | 21 22 15 16 + 0| | | | => | 5 6 7 0 | 20 21 22 15 + 1|inst_CLK_OUT_PRE_25|NOD| | => | 5 6 7 0 | 20 21 22 15 + 2|CLK_000_P_SYNC_5_|NOD| | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 - 4| | | | => | 7 0 1 2 | 22 15 16 17 - 5| | | | => | 7 0 1 2 | 22 15 16 17 - 6| | | | => | 0 1 2 3 | 15 16 17 18 + 4| AVEC_EXP| IO| | => |( 7) 0 1 2 |( 22) 15 16 17 + 5|inst_UDS_000_INT|NOD| | => | 7 0 1 2 | 22 15 16 17 + 6|CLK_000_P_SYNC_2_|NOD| | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 - 8| | | | => | 1 2 3 4 | 16 17 18 19 - 9| | | | => | 1 2 3 4 | 16 17 18 19 -10| | | | => | 2 3 4 5 | 17 18 19 20 + 8|inst_CLK_OUT_PRE_D|NOD| | => | 1 2 3 4 | 16 17 18 19 + 9|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 16 17 18 19 +10|CLK_000_N_SYNC_8_|NOD| | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 -12| | | | => | 3 4 5 6 | 18 19 20 21 -13| | | | => | 3 4 5 6 | 18 19 20 21 -14| | | | => | 4 5 6 7 | 19 20 21 22 +12|AMIGA_BUS_ENABLE_LOW| IO| | => | 3 4 ( 5) 6 | 18 19 ( 20) 21 +13|CLK_000_P_SYNC_6_|NOD| | => | 3 4 5 6 | 18 19 20 21 +14|CLK_000_N_SYNC_3_|NOD| | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== @@ -796,9 +828,9 @@ _|_________________|__|___|_____|___________________________________________ 2| A_26_|INP|*| 17| => | 4 5 6 7 8 9 10 11 3| A_25_|INP|*| 18| => | 6 7 8 9 10 11 12 13 4| A_24_|INP|*| 19| => | 8 9 10 11 12 13 14 15 - 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 0 ( 1) + 5|AMIGA_BUS_ENABLE_LOW| IO|*| 20| => | 10 11 (12) 13 14 15 0 1 6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3 - 7| AVEC_EXP|OUT|*| 22| => | 14 15 ( 0) 1 2 3 4 5 + 7| AVEC_EXP| IO|*| 22| => | 14 15 0 1 2 3 ( 4) 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table @@ -814,9 +846,11 @@ _|_________________|__|___|_____|__________________________________________ 2| A_26_|INP|*| 17| => | Input macrocell [ -] 3| A_25_|INP|*| 18| => | Input macrocell [ -] 4| A_24_|INP|*| 19| => | Input macrocell [ -] - 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -] + 5|AMIGA_BUS_ENABLE_LOW| IO|*| 20| => | Input macrocell [ -] + | | | | | | IO paired w/ node [RN_AMIGA_BUS_ENABLE_LOW] 6| BG_030|INP|*| 21| => | Input macrocell [ -] - 7| AVEC_EXP|OUT|*| 22| => | Input macrocell [ -] + 7| AVEC_EXP| IO|*| 22| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_AVEC_EXP] --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Input Multiplexer (IMX) Assignments @@ -829,42 +863,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 15|INP A_28_|*|*] [RegIn 0 |150| -| | ] - [MCell 0 |149|OUT AVEC_EXP| | ] - [MCell 1 |151|OUT AMIGA_BUS_ENABLE_LOW| | ] + [MCell 0 |149| -| | ] + [MCell 1 |151|NOD inst_CLK_OUT_PRE_25| |*] 1 [IOpin 1 | 16|INP A_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152| -| | ] + [MCell 2 |152|NOD CLK_000_P_SYNC_5_| |*] [MCell 3 |154| -| | ] 2 [IOpin 2 | 17|INP A_26_|*|*] [RegIn 2 |156| -| | ] - [MCell 4 |155| -| | ] - [MCell 5 |157| -| | ] + [MCell 4 |155|NOD RN_AVEC_EXP| |*] paired w/[ AVEC_EXP] + [MCell 5 |157|NOD inst_UDS_000_INT| |*] 3 [IOpin 3 | 18|INP A_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158| -| | ] + [MCell 6 |158|NOD CLK_000_P_SYNC_2_| |*] [MCell 7 |160| -| | ] 4 [IOpin 4 | 19|INP A_24_|*|*] [RegIn 4 |162| -| | ] - [MCell 8 |161| -| | ] - [MCell 9 |163| -| | ] + [MCell 8 |161|NOD inst_CLK_OUT_PRE_D| |*] + [MCell 9 |163|NOD inst_LDS_000_INT| |*] - 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] + 5 [IOpin 5 | 20| IO AMIGA_BUS_ENABLE_LOW|*| ] paired w/[RN_AMIGA_BUS_ENABLE_LOW] [RegIn 5 |165| -| | ] - [MCell 10 |164| -| | ] + [MCell 10 |164|NOD CLK_000_N_SYNC_8_| |*] [MCell 11 |166| -| | ] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] - [MCell 12 |167| -| | ] - [MCell 13 |169| -| | ] + [MCell 12 |167|NOD RN_AMIGA_BUS_ENABLE_LOW| |*] paired w/[AMIGA_BUS_ENABLE_LOW] + [MCell 13 |169|NOD CLK_000_P_SYNC_6_| |*] - 7 [IOpin 7 | 22|OUT AVEC_EXP|*| ] + 7 [IOpin 7 | 22| IO AVEC_EXP|*| ] paired w/[ RN_AVEC_EXP] [RegIn 7 |171| -| | ] - [MCell 14 |170| -| | ] + [MCell 14 |170|NOD CLK_000_N_SYNC_3_| |*] [MCell 15 |172| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -873,30 +907,30 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| ... | ... -Mux01| ... | ... -Mux02| Mcel 6 4 ( 251)| inst_avec_expreg -Mux03| ... | ... +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 2 1 ( 151)| inst_CLK_OUT_PRE_25 +Mux02| Mcel 1 10 ( 140)| inst_CLK_OUT_PRE +Mux03| Mcel 4 5 ( 205)| CLK_000_N_SYNC_2_ Mux04| ... | ... -Mux05| ... | ... -Mux06| ... | ... -Mux07| ... | ... -Mux08| ... | ... +Mux05| Mcel 4 1 ( 199)| CLK_000_N_SYNC_7_ +Mux06| IOPin 7 6 ( 79)| SIZE_1_ +Mux07| Mcel 7 13 ( 289)| inst_CLK_OUT_PRE_50_D +Mux08| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_50 Mux09| ... | ... -Mux10| ... | ... -Mux11| ... | ... -Mux12| ... | ... -Mux13| ... | ... -Mux14| ... | ... -Mux15| ... | ... -Mux16| ... | ... +Mux10| Mcel 1 2 ( 128)| CLK_000_P_SYNC_1_ +Mux11| Mcel 1 6 ( 134)| CLK_000_P_SYNC_9_ +Mux12| IOPin 0 7 ( 98)| DS_030 +Mux13| Mcel 2 9 ( 163)| inst_LDS_000_INT +Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux15| Mcel 2 5 ( 157)| inst_UDS_000_INT +Mux16| Mcel 2 8 ( 161)| inst_CLK_OUT_PRE_D Mux17| ... | ... -Mux18| ... | ... +Mux18| IOPin 6 4 ( 69)| A0 Mux19| ... | ... Mux20| ... | ... Mux21| ... | ... -Mux22| ... | ... -Mux23| ... | ... +Mux22| Mcel 2 2 ( 152)| CLK_000_P_SYNC_5_ +Mux23| Mcel 6 6 ( 254)| CLK_000_P_SYNC_4_ Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... @@ -919,18 +953,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| VMA| IO| | S | 2 :+: 1| 4 to [ 1]| 1 XOR to [ 1] - 2| BG_000| IO| | S | 2 | 4 to [ 2]| 1 XOR free - 3|AMIGA_BUS_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 2| SM_AMIGA_7_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 6]| 1 XOR to [ 5] for 1 PT sig - 6| UDS_000| IO| | S | 7 | 4 to [ 6]| 1 XOR to [ 6] as logic PT - 7| cpu_est_1_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free - 8| LDS_000| IO| | S |11 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 7]| 1 XOR to [ 9] -10| cpu_est_0_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free -11| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -12| | ? | | S | | 4 to [10]| 1 XOR free -13| | ? | | S | | 4 to [11]| 1 XOR free + 5|AMIGA_BUS_ENABLE| IO| | S | 6 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 7| | ? | | S | | 4 to [ 5]| 1 XOR free + 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| BG_000| IO| | S | 2 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -945,19 +979,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| VMA| IO| | S | 2 :+: 1|=> can support up to [ 12] logic PT(s) - 2| BG_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 3|AMIGA_BUS_ENABLE|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| AS_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 5|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 6| UDS_000| IO| | S | 7 |=> can support up to [ 9] logic PT(s) - 7| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 4] logic PT(s) - 8| LDS_000| IO| | S |11 |=> can support up to [ 15] logic PT(s) - 9| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 5] logic PT(s) -10| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) -11| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) -12| | ? | | S | |=> can support up to [ 6] logic PT(s) -13| | ? | | S | |=> can support up to [ 11] logic PT(s) + 1| VMA| IO| | S | 2 :+: 1|=> can support up to [ 13] logic PT(s) + 2| SM_AMIGA_7_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 5|AMIGA_BUS_ENABLE| IO| | S | 6 |=> can support up to [ 10] logic PT(s) + 6| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 9|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) +13| BG_000| IO| | S | 2 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -971,18 +1005,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 1| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) - 2| BG_000| IO| | => |( 6) 7 0 1 |( 29) 28 35 34 - 3|AMIGA_BUS_ENABLE|OUT| | => | 6 7 0 ( 1)| 29 28 35 ( 34) + 2| SM_AMIGA_7_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 3| | | | => | 6 7 0 1 | 29 28 35 34 4| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 5|inst_CLK_000_D1|NOD| | => | 7 0 1 2 | 28 35 34 33 - 6| UDS_000| IO| | => | 0 1 2 ( 3)| 35 34 33 ( 32) - 7| cpu_est_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 - 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) - 9| cpu_est_2_|NOD| | => | 1 2 3 4 | 34 33 32 31 -10| cpu_est_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 -11| SM_AMIGA_5_|NOD| | => | 2 3 4 5 | 33 32 31 30 -12| | | | => | 3 4 5 6 | 32 31 30 29 -13| | | | => | 3 4 5 6 | 32 31 30 29 + 5|AMIGA_BUS_ENABLE| IO| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 + 6| SM_AMIGA_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7| | | | => | 0 1 2 3 | 35 34 33 32 + 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 + 9|inst_CLK_000_D2|NOD| | => | 1 2 3 4 | 34 33 32 31 +10| | | | => | 2 3 4 5 | 33 32 31 30 +11| | | | => | 2 3 4 5 | 33 32 31 30 +12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 +13| BG_000| IO| | => | 3 4 5 ( 6)| 32 31 30 ( 29) 14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- @@ -996,12 +1030,12 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| VMA| IO|*| 35| => | 0 ( 1) 2 3 4 5 6 7 - 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | 2 ( 3) 4 5 6 7 8 9 + 1|AMIGA_BUS_ENABLE| IO|*| 34| => | 2 3 4 ( 5) 6 7 8 9 2| AS_000| IO|*| 33| => | ( 4) 5 6 7 8 9 10 11 - 3| UDS_000| IO|*| 32| => | ( 6) 7 8 9 10 11 12 13 - 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15 + 3| UDS_000| IO|*| 32| => | 6 7 ( 8) 9 10 11 12 13 + 4| LDS_000| IO|*| 31| => | 8 9 10 11 (12) 13 14 15 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 - 6| BG_000| IO|*| 29| => | 12 13 14 15 0 1 ( 2) 3 + 6| BG_000| IO|*| 29| => | 12 (13) 14 15 0 1 2 3 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== @@ -1015,13 +1049,12 @@ _|_________________|__|___|_____|___________________________________________ _|_________________|__|___|_____|__________________________________________ 0| VMA| IO|*| 35| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_VMA] - 1|AMIGA_BUS_ENABLE|OUT|*| 34| => | Input macrocell [ -] + 1|AMIGA_BUS_ENABLE| IO|*| 34| => | Input macrocell [ -] + | | | | | | IO paired w/ node [RN_AMIGA_BUS_ENABLE] 2| AS_000| IO|*| 33| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_AS_000] 3| UDS_000| IO|*| 32| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_UDS_000] 4| LDS_000| IO|*| 31| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_LDS_000] 5| DTACK| IO|*| 30| => | Input macrocell [ -] 6| BG_000| IO|*| 29| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BG_000] @@ -1041,35 +1074,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 0 |173| IO DTACK| | ] [MCell 1 |175|NOD RN_VMA| |*] paired w/[ VMA] - 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE|*| ] + 1 [IOpin 1 | 34| IO AMIGA_BUS_ENABLE|*| ] paired w/[RN_AMIGA_BUS_ENABLE] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD RN_BG_000| |*] paired w/[ BG_000] - [MCell 3 |178|OUT AMIGA_BUS_ENABLE| | ] + [MCell 2 |176|NOD SM_AMIGA_7_| |*] + [MCell 3 |178| -| | ] 2 [IOpin 2 | 33| IO AS_000|*|*] paired w/[ RN_AS_000] [RegIn 2 |180| -| | ] [MCell 4 |179|NOD RN_AS_000| |*] paired w/[ AS_000] - [MCell 5 |181|NOD inst_CLK_000_D1| |*] + [MCell 5 |181|NOD RN_AMIGA_BUS_ENABLE| |*] paired w/[AMIGA_BUS_ENABLE] - 3 [IOpin 3 | 32| IO UDS_000|*|*] paired w/[ RN_UDS_000] + 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD RN_UDS_000| |*] paired w/[ UDS_000] - [MCell 7 |184|NOD cpu_est_1_| |*] + [MCell 6 |182|NOD SM_AMIGA_0_| |*] + [MCell 7 |184| -| | ] - 4 [IOpin 4 | 31| IO LDS_000|*|*] paired w/[ RN_LDS_000] + 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] - [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] - [MCell 9 |187|NOD cpu_est_2_| |*] + [MCell 8 |185| IO UDS_000| | ] + [MCell 9 |187|NOD inst_CLK_000_D2| |*] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD cpu_est_0_| |*] - [MCell 11 |190|NOD SM_AMIGA_5_| |*] + [MCell 10 |188| -| | ] + [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] - [MCell 12 |191| -| | ] - [MCell 13 |193| -| | ] + [MCell 12 |191| IO LDS_000| | ] + [MCell 13 |193|NOD RN_BG_000| |*] paired w/[ BG_000] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] @@ -1082,39 +1115,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| ... | ... -Mux02| Mcel 6 4 ( 251)| inst_avec_expreg -Mux03| Mcel 3 2 ( 176)| RN_BG_000 -Mux04| Mcel 7 5 ( 277)| SM_AMIGA_7_ -Mux05| IOPin 0 7 ( 98)| DS_030 -Mux06| IOPin 7 6 ( 79)| SIZE_1_ +Mux00| Mcel 7 4 ( 275)| inst_AS_030_000_SYNC +Mux01| Mcel 3 13 ( 193)| RN_BG_000 +Mux02| Mcel 3 1 ( 175)| RN_VMA +Mux03| Mcel 3 2 ( 176)| SM_AMIGA_7_ +Mux04| Mcel 7 5 ( 277)| RN_BGACK_030 +Mux05| Mcel 7 9 ( 283)| inst_CLK_000_D1 +Mux06| Mcel 2 4 ( 155)| RN_AVEC_EXP Mux07| Mcel 7 6 ( 278)| RN_AS_030 -Mux08| IOPin 6 6 ( 71)| RW -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D0 -Mux11| Mcel 3 5 ( 181)| inst_CLK_000_D1 -Mux12| Mcel 3 9 ( 187)| cpu_est_2_ -Mux13| Mcel 3 7 ( 184)| cpu_est_1_ -Mux14| Mcel 3 4 ( 179)| RN_AS_000 +Mux08| ... | ... +Mux09| Mcel 6 13 ( 265)| cpu_est_2_ +Mux10| Mcel 3 4 ( 179)| RN_AS_000 +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 3 9 ( 187)| inst_CLK_000_D2 +Mux13| Mcel 2 9 ( 163)| inst_LDS_000_INT +Mux14| Input Pin ( 11)| CLK_000 Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 8 ( 185)| RN_LDS_000 -Mux17| IOPin 6 5 ( 70)| SIZE_0_ -Mux18| IOPin 6 4 ( 69)| A0 -Mux19| Mcel 3 11 ( 190)| SM_AMIGA_5_ -Mux20| Mcel 3 10 ( 188)| cpu_est_0_ +Mux16| Mcel 3 6 ( 182)| SM_AMIGA_0_ +Mux17| IOPin 7 4 ( 81)| DSACK1 +Mux18| Mcel 7 10 ( 284)| inst_BGACK_030_INT_D +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_1_ Mux21| Input Pin ( 86)| RST Mux22| IOPin 2 6 ( 21)| BG_030 -Mux23| Mcel 6 6 ( 254)| SM_AMIGA_6_ -Mux24| Input Pin ( 11)| CLK_000 -Mux25| Mcel 0 3 ( 106)| inst_VPA_D +Mux23| Mcel 6 2 ( 248)| inst_VPA_D +Mux24| Mcel 3 5 ( 181)| RN_AMIGA_BUS_ENABLE +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_D0 Mux26| ... | ... -Mux27| Mcel 3 1 ( 175)| RN_VMA -Mux28| ... | ... -Mux29| ... | ... -Mux30| Mcel 3 6 ( 182)| RN_UDS_000 -Mux31| Mcel 6 2 ( 248)| RN_E -Mux32| IOPin 7 4 ( 81)| DSACK1 +Mux27| Mcel 6 9 ( 259)| cpu_est_1_ +Mux28| Mcel 2 5 ( 157)| inst_UDS_000_INT +Mux29| Mcel 5 4 ( 227)| cpu_est_0_ +Mux30| Mcel 0 8 ( 113)| inst_CLK_000_NE +Mux31| Mcel 1 5 ( 133)| inst_DS_000_ENABLE +Mux32| Mcel 6 5 ( 253)| SM_AMIGA_6_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1127,18 +1160,18 @@ Mux32| IOPin 7 4 ( 81)| DSACK1 | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 0]| 1 XOR free - 1| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| BERR|OUT| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 1|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4| | ? | | S | | 4 free | 1 XOR free - 5| | ? | | S | | 4 free | 1 XOR free + 4| BERR|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_CLK_000_D3|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free +12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -1153,20 +1186,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 13] logic PT(s) - 1| CIIN|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| BERR|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) - 3| | ? | | S | |=> can support up to [ 19] logic PT(s) - 4| | ? | | S | |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 20] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) + 0|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) + 1|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 18] logic PT(s) + 3| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| BERR|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) + 5|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 18] logic PT(s) + 8|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 9|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 19] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -1179,18 +1212,18 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 - 1| CIIN|OUT| | => | 5 ( 6) 7 0 | 46 ( 47) 48 41 - 2| BERR|OUT| | => | 6 7 ( 0) 1 | 47 48 ( 41) 42 + 1|CLK_000_N_SYNC_7_|NOD| | => | 5 6 7 0 | 46 47 48 41 + 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 - 4| | | | => | 7 0 1 2 | 48 41 42 43 - 5| | | | => | 7 0 1 2 | 48 41 42 43 + 4| BERR|OUT| | => | 7 ( 0) 1 2 | 48 ( 41) 42 43 + 5|CLK_000_N_SYNC_2_|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8| | | | => | 1 2 3 4 | 42 43 44 45 - 9| | | | => | 1 2 3 4 | 42 43 44 45 + 8|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|inst_CLK_000_D3|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 -12| | | | => | 3 4 5 6 | 44 45 46 47 +12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) 13| | | | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 @@ -1204,13 +1237,13 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| BERR|OUT|*| 41| => | 0 1 ( 2) 3 4 5 6 7 + 0| BERR|OUT|*| 41| => | 0 1 2 3 ( 4) 5 6 7 1| | | | 42| => | 2 3 4 5 6 7 8 9 2| | | | 43| => | 4 5 6 7 8 9 10 11 3| | | | 44| => | 6 7 8 9 10 11 12 13 4| | | | 45| => | 8 9 10 11 12 13 14 15 5| | | | 46| => | 10 11 12 13 14 15 0 1 - 6| CIIN|OUT|*| 47| => | 12 13 14 15 0 ( 1) 2 3 + 6| CIIN|OUT|*| 47| => | (12) 13 14 15 0 1 2 3 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== @@ -1243,17 +1276,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 41|OUT BERR|*| ] [RegIn 0 |198| -| | ] [MCell 0 |197|OUT AMIGA_BUS_DATA_DIR| | ] - [MCell 1 |199|OUT CIIN| | ] + [MCell 1 |199|NOD CLK_000_N_SYNC_7_| |*] 1 [IOpin 1 | 42| -| | ] [RegIn 1 |201| -| | ] - [MCell 2 |200|OUT BERR| | ] + [MCell 2 |200| -| | ] [MCell 3 |202| -| | ] 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] - [MCell 4 |203| -| | ] - [MCell 5 |205| -| | ] + [MCell 4 |203|OUT BERR| | ] + [MCell 5 |205|NOD CLK_000_N_SYNC_2_| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1262,8 +1295,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209| -| | ] - [MCell 9 |211| -| | ] + [MCell 8 |209|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 9 |211|NOD inst_CLK_000_D3| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1272,7 +1305,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] - [MCell 12 |215| -| | ] + [MCell 12 |215|OUT CIIN| | ] [MCell 13 |217| -| | ] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] @@ -1286,39 +1319,118 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux00| Input Pin ( 86)| RST Mux01| IOPin 1 6 ( 4)| A_31_ Mux02| ... | ... Mux03| IOPin 2 1 ( 16)| A_27_ Mux04| IOPin 1 4 ( 6)| A_29_ -Mux05| IOPin 2 4 ( 19)| A_24_ -Mux06| ... | ... +Mux05| IOPin 0 3 ( 94)| A_21_ +Mux06| IOPin 0 6 ( 97)| A_19_ Mux07| IOPin 2 0 ( 15)| A_28_ -Mux08| IOPin 7 0 ( 85)| A_22_ -Mux09| IOPin 1 5 ( 5)| A_30_ -Mux10| ... | ... +Mux08| IOPin 6 6 ( 71)| RW +Mux09| IOPin 2 2 ( 17)| A_26_ +Mux10| Mcel 0 6 ( 110)| CLK_000_N_SYNC_1_ Mux11| IOPin 7 1 ( 84)| A_23_ Mux12| IOPin 2 3 ( 18)| A_25_ -Mux13| ... | ... -Mux14| Mcel 7 2 ( 272)| RN_FPU_CS -Mux15| IOPin 0 3 ( 94)| A_21_ -Mux16| ... | ... -Mux17| IOPin 2 2 ( 17)| A_26_ -Mux18| ... | ... -Mux19| ... | ... -Mux20| ... | ... +Mux13| IOPin 5 1 ( 59)| A_17_ +Mux14| IOPin 2 4 ( 19)| A_24_ +Mux15| Mcel 5 2 ( 224)| CLK_000_N_SYNC_6_ +Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_50 +Mux17| IOPin 5 3 ( 57)| FC_0_ +Mux18| IOPin 7 0 ( 85)| A_22_ +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| IOPin 5 2 ( 58)| FC_1_ Mux21| Input Pin ( 14)| nEXP_SPACE Mux22| ... | ... Mux23| IOPin 3 2 ( 33)| AS_000 Mux24| ... | ... -Mux25| IOPin 6 6 ( 71)| RW -Mux26| ... | ... -Mux27| ... | ... -Mux28| ... | ... +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D2 +Mux26| IOPin 0 5 ( 96)| A_16_ +Mux27| Mcel 7 5 ( 277)| RN_BGACK_030 +Mux28| IOPin 1 5 ( 5)| A_30_ Mux29| IOPin 0 2 ( 93)| A_20_ Mux30| ... | ... -Mux31| ... | ... -Mux32| ... | ... +Mux31| IOPin 0 4 ( 95)| A_18_ +Mux32| IOPin 3 7 ( 28)| BGACK_000 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| cpu_est_0_|NOD| | S | 2 | 4 to [ 4]| 1 XOR free + 5|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| SM_AMIGA_1_|NOD| | S | 2 | 4 to [ 8]| 1 XOR free + 9|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_3_|NOD| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT +13|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 2|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 5|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 6|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| SM_AMIGA_1_|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 9|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) +13|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|inst_CLK_000_D0|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| SM_AMIGA_2_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2|CLK_000_N_SYNC_6_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4| cpu_est_0_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5|CLK_000_P_SYNC_8_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 6|CLK_000_N_SYNC_0_|NOD| | => | 0 1 2 3 | 60 59 58 57 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| SM_AMIGA_1_|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9|CLK_000_P_SYNC_0_|NOD| | => | 1 2 3 4 | 59 58 57 56 +10| | | | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 57 56 55 54 +13|CLK_000_N_SYNC_9_|NOD| | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping @@ -1367,28 +1479,28 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221| -| | ] - [MCell 1 |223| -| | ] + [MCell 0 |221|NOD inst_CLK_000_D0| |*] + [MCell 1 |223|NOD SM_AMIGA_2_| |*] 1 [IOpin 1 | 59|INP A_17_|*|*] [RegIn 1 |225| -| | ] - [MCell 2 |224| -| | ] + [MCell 2 |224|NOD CLK_000_N_SYNC_6_| |*] [MCell 3 |226| -| | ] 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227| -| | ] - [MCell 5 |229| -| | ] + [MCell 4 |227|NOD cpu_est_0_| |*] + [MCell 5 |229|NOD CLK_000_P_SYNC_8_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] - [MCell 6 |230| -| | ] + [MCell 6 |230|NOD CLK_000_N_SYNC_0_| |*] [MCell 7 |232| -| | ] 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233| -| | ] - [MCell 9 |235| -| | ] + [MCell 8 |233|NOD SM_AMIGA_1_| |*] + [MCell 9 |235|NOD CLK_000_P_SYNC_0_| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] @@ -1397,14 +1509,54 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239| -| | ] - [MCell 13 |241| -| | ] + [MCell 12 |239|NOD SM_AMIGA_3_| |*] + [MCell 13 |241|NOD CLK_000_N_SYNC_9_| |*] 7 [IOpin 7 | 53| -| | ] [RegIn 7 |243| -| | ] [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 5 12 ( 239)| SM_AMIGA_3_ +Mux02| Mcel 4 9 ( 211)| inst_CLK_000_D3 +Mux03| Input Pin ( 11)| CLK_000 +Mux04| Mcel 6 2 ( 248)| inst_VPA_D +Mux05| Mcel 5 0 ( 221)| inst_CLK_000_D0 +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_4_ +Mux07| Mcel 3 9 ( 187)| inst_CLK_000_D2 +Mux08| Mcel 2 10 ( 164)| CLK_000_N_SYNC_8_ +Mux09| Mcel 0 1 ( 103)| CLK_000_P_SYNC_7_ +Mux10| Mcel 5 1 ( 223)| SM_AMIGA_2_ +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 6 9 ( 259)| cpu_est_1_ +Mux13| ... | ... +Mux14| Mcel 5 4 ( 227)| cpu_est_0_ +Mux15| ... | ... +Mux16| ... | ... +Mux17| Mcel 3 1 ( 175)| RN_VMA +Mux18| Mcel 0 8 ( 113)| inst_CLK_000_NE +Mux19| ... | ... +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_1_ +Mux21| ... | ... +Mux22| ... | ... +Mux23| IOPin 3 5 ( 30)| DTACK +Mux24| ... | ... +Mux25| Mcel 0 13 ( 121)| CLK_000_N_SYNC_5_ +Mux26| ... | ... +Mux27| Mcel 7 9 ( 283)| inst_CLK_000_D1 +Mux28| ... | ... +Mux29| Mcel 2 4 ( 155)| RN_AVEC_EXP +Mux30| ... | ... +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -1415,20 +1567,20 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| RW| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| E| IO| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2] - 3| CLK_DIV_OUT|OUT| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig - 4|inst_avec_expreg|NOD| | S | 6 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5|inst_RW_000_INT|NOD| | S |14 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 7| | ? | | S | | 4 to [ 5]| 1 XOR free - 8| A0| IO| | S | 1 | 4 to [ 6]| 1 XOR to [ 8] for 1 PT sig - 9| | ? | | S | | 4 free | 1 XOR free + 0| RW| IO| | S | 4 | 4 to [ 0]| 1 XOR free + 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| E| IO| | S | 4 | 4 to [ 4]| 1 XOR free + 5| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| A0| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| cpu_est_1_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free +12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| cpu_est_2_|NOD| | S | 4 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1442,21 +1594,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| SIZE_0_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 2| E| IO| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) - 3| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) - 4|inst_avec_expreg|NOD| | S | 6 |=> can support up to [ 9] logic PT(s) - 5|inst_RW_000_INT|NOD| | S |14 |=> can support up to [ 15] logic PT(s) - 6| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) - 7| | ? | | S | |=> can support up to [ 6] logic PT(s) - 8| A0| IO| | S | 1 |=> can support up to [ 11] logic PT(s) - 9| | ? | | S | |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) + 0| RW| IO| | S | 4 |=> can support up to [ 13] logic PT(s) + 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4| E| IO| | S | 4 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 6|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| A0| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| cpu_est_1_|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| SIZE_0_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) +13| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1468,19 +1620,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 - 1| SIZE_0_| IO| | => |( 5) 6 7 0 |( 70) 71 72 65 - 2| E| IO| | => | 6 7 0 ( 1)| 71 72 65 ( 66) - 3| CLK_DIV_OUT|OUT| | => | 6 7 ( 0) 1 | 71 72 ( 65) 66 - 4|inst_avec_expreg|NOD| | => | 7 0 1 2 | 72 65 66 67 - 5|inst_RW_000_INT|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| SM_AMIGA_6_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) + 2| inst_VPA_D|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3| | | | => | 6 7 0 1 | 71 72 65 66 + 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 + 5| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|CLK_000_P_SYNC_4_|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9| | | | => | 1 2 3 4 | 66 67 68 69 + 9| cpu_est_1_|NOD| | => | 1 2 3 4 | 66 67 68 69 10| | | | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 -12| | | | => | 3 4 5 6 | 68 69 70 71 -13| | | | => | 3 4 5 6 | 68 69 70 71 +12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 +13| cpu_est_2_|NOD| | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- @@ -1493,12 +1645,12 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| CLK_DIV_OUT|OUT|*| 65| => | 0 1 2 ( 3) 4 5 6 7 - 1| E| IO|*| 66| => | ( 2) 3 4 5 6 7 8 9 + 0| CLK_DIV_OUT|OUT|*| 65| => | 0 ( 1) 2 3 4 5 6 7 + 1| E| IO|*| 66| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 4| A0| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 - 5| SIZE_0_| IO|*| 70| => | 10 11 12 13 14 15 0 ( 1) + 5| SIZE_0_| IO|*| 70| => | 10 11 (12) 13 14 15 0 1 6| RW| IO|*| 71| => | 12 13 14 15 ( 0) 1 2 3 7| | | | 72| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- @@ -1519,6 +1671,7 @@ _|_________________|__|___|_____|__________________________________________ 4| A0| IO|*| 69| => | Input macrocell [ -] 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] 6| RW| IO|*| 71| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RW] 7| | | | 72| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -1532,38 +1685,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] - [MCell 0 |245| IO RW| | ] - [MCell 1 |247| IO SIZE_0_| | ] + [MCell 0 |245|NOD RN_RW| |*] paired w/[ RW] + [MCell 1 |247|OUT CLK_DIV_OUT| | ] 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD RN_E| |*] paired w/[ E] - [MCell 3 |250|OUT CLK_DIV_OUT| | ] + [MCell 2 |248|NOD inst_VPA_D| |*] + [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] - [MCell 4 |251|NOD inst_avec_expreg| |*] - [MCell 5 |253|NOD inst_RW_000_INT| |*] + [MCell 4 |251|NOD RN_E| |*] paired w/[ E] + [MCell 5 |253|NOD SM_AMIGA_6_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD SM_AMIGA_6_| |*] + [MCell 6 |254|NOD CLK_000_P_SYNC_4_| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69| IO A0|*|*] [RegIn 4 |258| -| | ] [MCell 8 |257| IO A0| | ] - [MCell 9 |259| -| | ] + [MCell 9 |259|NOD cpu_est_1_| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] [MCell 10 |260| -| | ] [MCell 11 |262| -| | ] - 6 [IOpin 6 | 71| IO RW|*|*] + 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] [RegIn 6 |264| -| | ] - [MCell 12 |263| -| | ] - [MCell 13 |265| -| | ] + [MCell 12 |263| IO SIZE_0_| | ] + [MCell 13 |265|NOD cpu_est_2_| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] @@ -1576,38 +1729,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 3 4 ( 31)| LDS_000 -Mux01| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25 -Mux02| Mcel 3 10 ( 188)| cpu_est_0_ -Mux03| Mcel 6 5 ( 253)| inst_RW_000_INT +Mux00| Input Pin ( 86)| RST +Mux01| ... | ... +Mux02| Mcel 0 5 ( 109)| CLK_000_P_SYNC_3_ +Mux03| Mcel 3 2 ( 176)| SM_AMIGA_7_ Mux04| Input Pin ( 64)| CLK_030 -Mux05| Mcel 7 9 ( 283)| SM_AMIGA_0_ -Mux06| Mcel 1 9 ( 139)| inst_BGACK_030_INT_D -Mux07| Mcel 3 9 ( 187)| cpu_est_2_ -Mux08| Mcel 3 7 ( 184)| cpu_est_1_ -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D0 -Mux11| Mcel 6 4 ( 251)| inst_avec_expreg -Mux12| IOPin 3 3 ( 32)| UDS_000 -Mux13| Mcel 1 3 ( 130)| SM_AMIGA_1_ -Mux14| ... | ... -Mux15| Input Pin ( 14)| nEXP_SPACE +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| Mcel 2 4 ( 155)| RN_AVEC_EXP +Mux07| Mcel 2 8 ( 161)| inst_CLK_OUT_PRE_D +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 6 13 ( 265)| cpu_est_2_ +Mux10| Input Pin ( 36)| VPA +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 6 9 ( 259)| cpu_est_1_ +Mux13| Mcel 7 5 ( 277)| RN_BGACK_030 +Mux14| Mcel 5 4 ( 227)| cpu_est_0_ +Mux15| ... | ... Mux16| ... | ... -Mux17| ... | ... -Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D2 +Mux17| Mcel 6 0 ( 245)| RN_RW +Mux18| ... | ... Mux19| ... | ... -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 86)| RST -Mux22| ... | ... -Mux23| Mcel 6 6 ( 254)| SM_AMIGA_6_ -Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D1 -Mux25| IOPin 6 6 ( 71)| RW -Mux26| IOPin 3 2 ( 33)| AS_000 -Mux27| Mcel 7 5 ( 277)| SM_AMIGA_7_ +Mux20| Mcel 7 4 ( 275)| inst_AS_030_000_SYNC +Mux21| Mcel 7 6 ( 278)| RN_AS_030 +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_6_ +Mux23| IOPin 3 2 ( 33)| AS_000 +Mux24| IOPin 3 4 ( 31)| LDS_000 +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D2 +Mux26| ... | ... +Mux27| Mcel 7 9 ( 283)| inst_CLK_000_D1 Mux28| IOPin 7 5 ( 80)| RW_000 -Mux29| Mcel 7 7 ( 280)| inst_AS_030_000_SYNC -Mux30| Mcel 7 6 ( 278)| RN_AS_030 -Mux31| Mcel 6 2 ( 248)| RN_E +Mux29| ... | ... +Mux30| ... | ... +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1620,20 +1773,20 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| RW_000| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 0| RW_000| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| SIZE_1_| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| FPU_CS| IO| | S | 2 | 4 to [ 2]| 1 XOR free - 3|inst_CLK_000_D0|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig - 4| BGACK_030| IO| | S | 2 | 4 to [ 5]| 1 XOR free - 5| SM_AMIGA_7_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free - 6| AS_030| IO| | S | 4 | 4 to [ 7]| 1 XOR free - 7|inst_AS_030_000_SYNC|NOD| | S | 8 | 4 to [ 7]| 1 XOR to [ 7] as logic PT - 8| DSACK1| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig -12|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| | ? | | S | | 4 free | 1 XOR free + 2| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4|inst_AS_030_000_SYNC|NOD| | S | 5 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5| BGACK_030| IO| | S | 2 | 4 to [ 5]| 1 XOR free + 6| AS_030| IO| | S | 4 | 4 to [ 6]| 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| | ? | | S | | 4 free | 1 XOR free + 9|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12| DSACK1| IO| | S | 2 | 4 to [12]| 1 XOR free +13|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1647,21 +1800,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW_000| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| SIZE_1_| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 2| FPU_CS| IO| | S | 2 |=> can support up to [ 5] logic PT(s) - 3|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 4] logic PT(s) - 5| SM_AMIGA_7_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 6| AS_030| IO| | S | 4 |=> can support up to [ 5] logic PT(s) - 7|inst_AS_030_000_SYNC|NOD| | S | 8 |=> can support up to [ 10] logic PT(s) - 8| DSACK1| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 9| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) -10|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -11|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) -12|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -13| | ? | | S | |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) + 0| RW_000| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 1| SIZE_1_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) + 2| FPU_CS|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4|inst_AS_030_000_SYNC|NOD| | S | 5 |=> can support up to [ 10] logic PT(s) + 5| BGACK_030| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 6| AS_030| IO| | S | 4 |=> can support up to [ 15] logic PT(s) + 7| | ? | | S | |=> can support up to [ 14] logic PT(s) + 8| | ? | | S | |=> can support up to [ 18] logic PT(s) + 9|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12| DSACK1| IO| | S | 2 |=> can support up to [ 19] logic PT(s) +13|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1674,18 +1827,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 1| SIZE_1_| IO| | => | 5 ( 6) 7 0 | 80 ( 79) 78 85 - 2| FPU_CS| IO| | => | 6 ( 7) 0 1 | 79 ( 78) 85 84 - 3|inst_CLK_000_D0|NOD| | => | 6 7 0 1 | 79 78 85 84 - 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5| SM_AMIGA_7_|NOD| | => | 7 0 1 2 | 78 85 84 83 + 2| FPU_CS|OUT| | => | 6 ( 7) 0 1 | 79 ( 78) 85 84 + 3| | | | => | 6 7 0 1 | 79 78 85 84 + 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 78 85 84 83 + 5| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) 6| AS_030| IO| | => | 0 1 2 ( 3)| 85 84 83 ( 82) - 7|inst_AS_030_000_SYNC|NOD| | => | 0 1 2 3 | 85 84 83 82 - 8| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) - 9| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 84 83 82 81 -10|inst_CLK_000_D2|NOD| | => | 2 3 4 5 | 83 82 81 80 -11|inst_CLK_OUT_PRE_50|NOD| | => | 2 3 4 5 | 83 82 81 80 -12|inst_CLK_OUT_PRE_50_D|NOD| | => | 3 4 5 6 | 82 81 80 79 -13| | | | => | 3 4 5 6 | 82 81 80 79 + 7| | | | => | 0 1 2 3 | 85 84 83 82 + 8| | | | => | 1 2 3 4 | 84 83 82 81 + 9|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 84 83 82 81 +10|inst_BGACK_030_INT_D|NOD| | => | 2 3 4 5 | 83 82 81 80 +11| | | | => | 2 3 4 5 | 83 82 81 80 +12| DSACK1| IO| | => | 3 ( 4) 5 6 | 82 ( 81) 80 79 +13|inst_CLK_OUT_PRE_50_D|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1700,12 +1853,12 @@ _|_________________|__|_____|____________________|________________________ _|_________________|__|___|_____|___________________________________________ 0| A_22_|INP|*| 85| => | 0 1 2 3 4 5 6 7 1| A_23_|INP|*| 84| => | 2 3 4 5 6 7 8 9 - 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 + 2| BGACK_030| IO|*| 83| => | 4 ( 5) 6 7 8 9 10 11 3| AS_030| IO|*| 82| => | ( 6) 7 8 9 10 11 12 13 - 4| DSACK1| IO|*| 81| => | ( 8) 9 10 11 12 13 14 15 + 4| DSACK1| IO|*| 81| => | 8 9 10 11 (12) 13 14 15 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 6| SIZE_1_| IO|*| 79| => | 12 13 14 15 0 ( 1) 2 3 - 7| FPU_CS| IO|*| 78| => | 14 15 0 1 ( 2) 3 4 5 + 7| FPU_CS|OUT|*| 78| => | 14 15 0 1 ( 2) 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table @@ -1725,9 +1878,9 @@ _|_________________|__|___|_____|__________________________________________ 4| DSACK1| IO|*| 81| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_DSACK1] 5| RW_000| IO|*| 80| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RW_000] 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] - 7| FPU_CS| IO|*| 78| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_FPU_CS] + 7| FPU_CS|OUT|*| 78| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Input Multiplexer (IMX) Assignments @@ -1740,40 +1893,40 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 85|INP A_22_|*|*] [RegIn 0 |270| -| | ] - [MCell 0 |269| IO RW_000| | ] + [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] [MCell 1 |271| IO SIZE_1_| | ] 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] - [MCell 3 |274|NOD inst_CLK_000_D0| |*] + [MCell 2 |272|OUT FPU_CS| | ] + [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] - [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD SM_AMIGA_7_| |*] + [MCell 4 |275|NOD inst_AS_030_000_SYNC| |*] + [MCell 5 |277|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] 3 [IOpin 3 | 82| IO AS_030|*|*] paired w/[ RN_AS_030] [RegIn 3 |279| -| | ] [MCell 6 |278|NOD RN_AS_030| |*] paired w/[ AS_030] - [MCell 7 |280|NOD inst_AS_030_000_SYNC| |*] + [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK1|*|*] paired w/[ RN_DSACK1] [RegIn 4 |282| -| | ] - [MCell 8 |281|NOD RN_DSACK1| |*] paired w/[ DSACK1] - [MCell 9 |283|NOD SM_AMIGA_0_| |*] + [MCell 8 |281| -| | ] + [MCell 9 |283|NOD inst_CLK_000_D1| |*] - 5 [IOpin 5 | 80| IO RW_000|*|*] + 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] [RegIn 5 |285| -| | ] - [MCell 10 |284|NOD inst_CLK_000_D2| |*] - [MCell 11 |286|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 10 |284|NOD inst_BGACK_030_INT_D| |*] + [MCell 11 |286| -| | ] 6 [IOpin 6 | 79| IO SIZE_1_|*|*] [RegIn 6 |288| -| | ] - [MCell 12 |287|NOD inst_CLK_OUT_PRE_50_D| |*] - [MCell 13 |289| -| | ] + [MCell 12 |287|NOD RN_DSACK1| |*] paired w/[ DSACK1] + [MCell 13 |289|NOD inst_CLK_OUT_PRE_50_D| |*] - 7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS] + 7 [IOpin 7 | 78|OUT FPU_CS|*| ] [RegIn 7 |291| -| | ] [MCell 14 |290| -| | ] [MCell 15 |292| -| | ] @@ -1784,37 +1937,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 3 4 ( 31)| LDS_000 +Mux00| Mcel 7 4 ( 275)| inst_AS_030_000_SYNC Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| ... | ... -Mux03| Input Pin ( 11)| CLK_000 -Mux04| IOPin 3 7 ( 28)| BGACK_000 -Mux05| Mcel 7 9 ( 283)| SM_AMIGA_0_ +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_1_ +Mux03| Mcel 3 2 ( 176)| SM_AMIGA_7_ +Mux04| IOPin 0 4 ( 95)| A_18_ +Mux05| Mcel 7 9 ( 283)| inst_CLK_000_D1 Mux06| IOPin 0 6 ( 97)| A_19_ Mux07| Mcel 7 6 ( 278)| RN_AS_030 -Mux08| IOPin 5 1 ( 59)| A_17_ +Mux08| IOPin 6 6 ( 71)| RW Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D0 +Mux10| ... | ... Mux11| IOPin 0 5 ( 96)| A_16_ Mux12| IOPin 3 3 ( 32)| UDS_000 -Mux13| Mcel 7 8 ( 281)| RN_DSACK1 -Mux14| Mcel 7 2 ( 272)| RN_FPU_CS +Mux13| Mcel 7 5 ( 277)| RN_BGACK_030 +Mux14| Mcel 2 4 ( 155)| RN_AVEC_EXP Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| ... | ... +Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_50 Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D2 -Mux19| Mcel 1 3 ( 130)| SM_AMIGA_1_ -Mux20| Mcel 7 7 ( 280)| inst_AS_030_000_SYNC +Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux19| ... | ... +Mux20| Input Pin ( 64)| CLK_030 Mux21| Input Pin ( 86)| RST -Mux22| Mcel 7 11 ( 286)| inst_CLK_OUT_PRE_50 -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D1 -Mux25| ... | ... +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_6_ +Mux23| Mcel 2 12 ( 167)| RN_AMIGA_BUS_ENABLE_LOW +Mux24| IOPin 3 4 ( 31)| LDS_000 +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_D0 Mux26| IOPin 3 2 ( 33)| AS_000 -Mux27| Mcel 7 5 ( 277)| SM_AMIGA_7_ -Mux28| Input Pin ( 64)| CLK_030 -Mux29| ... | ... -Mux30| ... | ... -Mux31| IOPin 0 4 ( 95)| A_18_ -Mux32| Mcel 6 5 ( 253)| inst_RW_000_INT +Mux27| IOPin 5 1 ( 59)| A_17_ +Mux28| ... | ... +Mux29| Mcel 7 12 ( 287)| RN_DSACK1 +Mux30| Mcel 7 0 ( 269)| RN_RW_000 +Mux31| ... | ... +Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 796ee6f..9eeebeb 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Sat Jun 07 23:03:24 2014 +Project Fitted on : Mon Jun 09 10:27:29 2014 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 29 Total Output Pins : 18 Total Bidir I/O Pins : 12 - Total Flip-Flops : 44 - Total Product Terms : 146 + Total Flip-Flops : 72 + Total Product Terms : 151 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 54 74 --> 42% +Logic Macrocells 128 80 48 --> 62% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 147 117 --> 55% -Logical Product Terms 640 149 491 --> 23% -Product Term Clusters 128 40 88 --> 31% +CSM Outputs/Total Block Inputs 264 190 74 --> 71% +Logical Product Terms 640 152 488 --> 23% +Product Term Clusters 128 35 93 --> 27%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 23 7 0 6 0 10 18 11 Hi -Block B 22 8 0 10 0 6 23 10 Hi -Block C 1 8 0 2 0 14 2 16 Hi -Block D 29 8 0 12 0 4 41 4 Hi -Block E 17 3 0 3 0 13 4 15 Hi -Block F 0 4 0 0 0 16 0 16 Hi -Block G 27 7 0 8 0 8 30 9 Hi -Block H 28 8 0 13 0 3 31 7 Hi +Block A 19 7 0 11 0 5 21 13 Hi +Block B 21 8 0 11 0 5 21 10 Hi +Block C 18 8 0 11 0 5 15 13 Hi +Block D 31 8 0 10 0 6 23 9 Hi +Block E 29 3 0 7 0 9 8 15 Hi +Block F 21 4 0 10 0 6 18 12 Hi +Block G 23 7 0 10 0 6 24 11 Hi +Block H 28 8 0 10 0 6 22 10 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -110,8 +110,8 @@ Block Reservation : No @Timing_Constraints : No @Global_Project_Optimization : - Balanced Partitioning : No - Spread Placement : No + Balanced Partitioning : Yes + Spread Placement : Yes Note : Pack Design : @@ -287,10 +287,10 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 96 A . I/O -------H Hi Slow A_16_ - 59 F . I/O -------H Hi Slow A_17_ - 95 A . I/O -------H Hi Slow A_18_ - 97 A . I/O -------H Hi Slow A_19_ + 96 A . I/O ----E--H Hi Slow A_16_ + 59 F . I/O ----E--H Hi Slow A_17_ + 95 A . I/O ----E--H Hi Slow A_18_ + 97 A . I/O ----E--H Hi Slow A_19_ 93 A . I/O ----E--- Hi Slow A_20_ 94 A . I/O ----E--- Hi Slow A_21_ 85 H . I/O ----E--- Hi Slow A_22_ @@ -303,19 +303,19 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B . I/O ----E--- Hi Slow A_29_ 5 B . I/O ----E--- Hi Slow A_30_ 4 B . I/O ----E--- Hi Slow A_31_ - 28 D . I/O -------H Hi Slow BGACK_000 + 28 D . I/O ----E--H Hi Slow BGACK_000 21 C . I/O ---D---- Hi Slow BG_030 - 57 F . I/O -------H Hi Slow FC_0_ - 58 F . I/O -------H Hi Slow FC_1_ + 57 F . I/O ----E--H Hi Slow FC_0_ + 58 F . I/O ----E--H Hi Slow FC_1_ 67 G . I/O -B------ Hi Slow IPL_0_ 56 F . I/O -B------ Hi Slow IPL_1_ 68 G . I/O -B------ Hi Slow IPL_2_ - 11 . . Ck/I ---D---H - Slow CLK_000 + 11 . . Ck/I ---D-F-- - Slow CLK_000 14 . . Ck/I A--DE-GH - Slow nEXP_SPACE - 36 . . Ded A------- - Slow VPA - 61 . . Ck/I AB-D--GH - Slow CLK_OSZI - 64 . . Ck/I AB----GH - Slow CLK_030 - 86 . . Ded AB-D--GH - Slow RST + 36 . . Ded ------G- - Slow VPA + 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI + 64 . . Ck/I A-----GH - Slow CLK_030 + 86 . . Ded ABCDEFGH - Slow RST ---------------------------------------------------------------------- Power : Hi = High @@ -332,18 +332,18 @@ Output_Signal_List Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR - 34 D 1 COM -------- Hi Slow AMIGA_BUS_ENABLE - 20 C 1 COM -------- Hi Slow AMIGA_BUS_ENABLE_LOW + 34 D 6 DFF * -------- Hi Slow AMIGA_BUS_ENABLE + 20 C 1 DFF * -------- Hi Slow AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Hi Slow AVEC - 22 C 1 COM -------- Hi Slow AVEC_EXP + 22 C 1 DFF * -------- Hi Slow AVEC_EXP 41 E 1 COM -------- Hi Slow BERR 83 H 2 DFF * -------- Hi Slow BGACK_030 29 D 2 DFF * -------- Hi Slow BG_000 47 E 1 COM -------- Hi Slow CIIN 65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT 10 B 1 DFF * -------- Hi Slow CLK_EXP - 66 G 3 DFF * -------- Hi Slow E - 78 H 2 DFF * -------- Hi Slow FPU_CS + 66 G 4 DFF * -------- Hi Slow E + 78 H 1 COM -------- Hi Slow FPU_CS 8 B 3 DFF * -------- Hi Slow IPL_030_0_ 7 B 3 DFF * -------- Hi Slow IPL_030_1_ 9 B 3 DFF * -------- Hi Slow IPL_030_2_ @@ -364,18 +364,18 @@ Bidir_Signal_List Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 69 G 1 DFF * ---D---- Hi Slow A0 - 33 D 2 DFF * AB--E-GH Hi Slow AS_000 - 82 H 4 DFF * ---D--GH Hi Slow AS_030 + 69 G 1 DFF * --C----- Hi Slow A0 + 33 D 2 DFF * A---E-GH Hi Slow AS_000 + 82 H 4 DFF * -B-DE--H Hi Slow AS_030 81 H 2 DFF * ---D---- Hi Slow DSACK1 - 98 A 7 DFF * ---D---- Hi Slow DS_030 - 30 D 1 COM -B------ Hi Slow DTACK - 31 D 11 DFF * AB----GH Hi Slow LDS_000 - 71 G 1 COM ---DE-G- Hi Slow RW - 80 H 1 COM A-----G- Hi Slow RW_000 - 70 G 1 DFF * ---D---- Hi Slow SIZE_0_ - 79 H 2 DFF * ---D---- Hi Slow SIZE_1_ - 32 D 7 DFF * AB----GH Hi Slow UDS_000 + 98 A 7 DFF * --C----- Hi Slow DS_030 + 30 D 1 COM -----F-- Hi Slow DTACK + 31 D 1 COM A-----GH Hi Slow LDS_000 + 71 G 4 DFF * -B--E--H Hi Slow RW + 80 H 3 DFF * A-----G- Hi Slow RW_000 + 70 G 1 DFF * --C----- Hi Slow SIZE_0_ + 79 H 2 DFF * --C----- Hi Slow SIZE_1_ + 32 D 1 COM A-----GH Hi Slow UDS_000 ---------------------------------------------------------------------- Power : Hi = High @@ -391,44 +391,72 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- + F6 F 1 DFF * A------- Hi Slow CLK_000_N_SYNC_0_ + A9 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_10_ + A10 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_11_ + A6 A 1 DFF * ----E--- Hi Slow CLK_000_N_SYNC_1_ + E5 E 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_2_ + C14 C 1 DFF * A------- Hi Slow CLK_000_N_SYNC_3_ + A2 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_4_ + A13 A 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_5_ + F2 F 1 DFF * ----E--- Hi Slow CLK_000_N_SYNC_6_ + E1 E 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_7_ + C10 C 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_8_ + F13 F 1 DFF * A------- Hi Slow CLK_000_N_SYNC_9_ + F9 F 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_0_ + B2 B 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_1_ + C6 C 1 DFF * A------- Hi Slow CLK_000_P_SYNC_2_ + A5 A 1 DFF * ------G- Hi Slow CLK_000_P_SYNC_3_ + G6 G 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_4_ + C2 C 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_5_ + C13 C 1 DFF * A------- Hi Slow CLK_000_P_SYNC_6_ + A1 A 1 DFF * -----F-- Hi Slow CLK_000_P_SYNC_7_ + F5 F 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_8_ + B6 B 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_9_ + D5 D 6 DFF * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE + C12 C 1 DFF * -------H Hi - RN_AMIGA_BUS_ENABLE_LOW --> AMIGA_BUS_ENABLE_LOW D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000 - H6 H 4 DFF * AB-D--GH Hi - RN_AS_030 --> AS_030 - H4 H 2 DFF * AB-DE-GH Hi - RN_BGACK_030 --> BGACK_030 - D2 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000 - H8 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1 + H6 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030 + C4 C 1 DFF * -B-D-FGH Hi - RN_AVEC_EXP --> AVEC_EXP + H5 H 2 DFF * A--DE-GH Hi - RN_BGACK_030 --> BGACK_030 + D13 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000 + H12 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1 A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030 - G2 G 3 DFF * A--D--G- Hi - RN_E --> E - H2 H 2 DFF * ----E--H Hi - RN_FPU_CS --> FPU_CS - B4 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ - B6 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ - B2 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ - D8 D 11 DFF * ---D---- Hi - RN_LDS_000 --> LDS_000 - D6 D 7 DFF * ---D---- Hi - RN_UDS_000 --> UDS_000 - D1 D 2 DFF * A--D---- Hi - RN_VMA --> VMA - H9 H 2 DFF * ------GH Hi Slow SM_AMIGA_0_ - B3 B 2 DFF * -B----GH Hi Slow SM_AMIGA_1_ - A1 A 3 DFF * AB------ Hi Slow SM_AMIGA_2_ - A4 A 4 DFF * A------- Hi Slow SM_AMIGA_3_ - A5 A 2 DFF * A------- Hi Slow SM_AMIGA_4_ - D11 D 2 DFF * A--D---- Hi Slow SM_AMIGA_5_ - G6 G 2 DFF * ---D--G- Hi Slow SM_AMIGA_6_ - H5 H 4 DFF * ---D--GH Hi Slow SM_AMIGA_7_ - D10 D 3 DFF * ---D--G- Hi Slow cpu_est_0_ - D7 D 4 TFF * A--D--G- Hi Slow cpu_est_1_ - D9 D 3 DFF * ---D--G- Hi Slow cpu_est_2_ - H7 H 8 DFF * ------GH Hi Slow inst_AS_030_000_SYNC - B9 B 1 DFF * ------G- Hi Slow inst_BGACK_030_INT_D - H3 H 1 DFF * AB-D--GH Hi Slow inst_CLK_000_D0 - D5 D 1 DFF * AB-D--GH Hi Slow inst_CLK_000_D1 - H10 H 1 DFF * ------GH Hi Slow inst_CLK_000_D2 - B5 B 5 DFF AB------ Hi Slow inst_CLK_030_H - B7 B 3 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_25 - H11 H 1 DFF * -B-----H Hi Slow inst_CLK_OUT_PRE_50 - H12 H 1 DFF * -B------ Hi Slow inst_CLK_OUT_PRE_50_D - B8 B 1 DFF * A------- Hi Slow inst_DTACK_D0 - G5 G 14 DFF * ------GH Hi Slow inst_RW_000_INT - A3 A 1 DFF * A--D---- Hi Slow inst_VPA_D - G4 G 6 DFF * --CD--G- Hi Slow inst_avec_expreg + G4 G 4 DFF * ---D-FG- Hi - RN_E --> E + B8 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ + B12 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ + B4 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ + G0 G 4 DFF * ------G- Hi - RN_RW --> RW + H0 H 3 DFF * -------H Hi - RN_RW_000 --> RW_000 + D1 D 2 DFF * ---D-F-- Hi - RN_VMA --> VMA + D6 D 2 DFF * ---D---- Hi Slow SM_AMIGA_0_ + F8 F 2 DFF * ---D-F-H Hi Slow SM_AMIGA_1_ + F1 F 3 DFF * -----F-- Hi Slow SM_AMIGA_2_ + F12 F 5 TFF * -----F-- Hi Slow SM_AMIGA_3_ + B9 B 2 DFF * -B---F-- Hi Slow SM_AMIGA_4_ + B13 B 2 DFF * -B------ Hi Slow SM_AMIGA_5_ + G5 G 2 DFF * -B-D--GH Hi Slow SM_AMIGA_6_ + D2 D 4 DFF * ---D--GH Hi Slow SM_AMIGA_7_ + F4 F 2 DFF * ---D-FG- Hi Slow cpu_est_0_ + G9 G 5 DFF * ---D-FG- Hi Slow cpu_est_1_ + G13 G 4 DFF * ---D--G- Hi Slow cpu_est_2_ + H4 H 5 DFF * ---D--GH Hi Slow inst_AS_030_000_SYNC + H10 H 1 DFF * ---D---- Hi Slow inst_BGACK_030_INT_D + F0 F 1 DFF * -B-D-F-H Hi Slow inst_CLK_000_D0 + H9 H 1 DFF * -B-D-FGH Hi Slow inst_CLK_000_D1 + D9 D 1 DFF * ---DEFG- Hi Slow inst_CLK_000_D2 + E9 E 1 DFF * -----F-- Hi Slow inst_CLK_000_D3 + A8 A 1 DFF * -B-D-F-- Hi Slow inst_CLK_000_NE + A12 A 5 DFF A------- Hi Slow inst_CLK_030_H + B10 B 1 DFF * --C----- Hi Slow inst_CLK_OUT_PRE + C1 C 3 DFF * -BC----- Hi Slow inst_CLK_OUT_PRE_25 + E8 E 1 DFF * --C-E--H Hi Slow inst_CLK_OUT_PRE_50 + H13 H 1 DFF * --C----- Hi Slow inst_CLK_OUT_PRE_50_D + C8 C 1 DFF * -BC---G- Hi Slow inst_CLK_OUT_PRE_D + B5 B 3 DFF * -B-D---- Hi Slow inst_DS_000_ENABLE + C9 C 2 DFF * --CD---- Hi Slow inst_LDS_000_INT + C5 C 2 DFF * --CD---- Hi Slow inst_UDS_000_INT + G2 G 1 DFF * ---D-F-- Hi Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -443,141 +471,176 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - A_22_{ I}: CIIN{ E} - A_21_{ B}: CIIN{ E} - A_20_{ B}: CIIN{ E} - A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_31_{ C}: CIIN{ E} - A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} IPL_2_{ H}: IPL_030_2_{ B} - IPL_1_{ G}: IPL_030_1_{ B} - FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - IPL_0_{ H}: IPL_030_0_{ B} - FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - RW_000{ I}: DS_030{ A}inst_RW_000_INT{ G} - nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} - : AS_030{ H} DS_030{ A} A0{ G} - : BG_000{ D} DSACK1{ H} SIZE_0_{ G} - :inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} - : SM_AMIGA_7_{ H} - BG_030{ D}: BG_000{ D} - BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - CLK_030{. }: AS_030{ H} DS_030{ A} FPU_CS{ H} - :inst_AS_030_000_SYNC{ H}inst_RW_000_INT{ G} inst_CLK_030_H{ B} - CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ H} - DTACK{ E}: inst_DTACK_D0{ B} - VPA{. }: inst_VPA_D{ A} - RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B} - : IPL_030_1_{ B} IPL_030_0_{ B} AS_030{ H} - : AS_000{ D} DS_030{ A} UDS_000{ D} - : LDS_000{ D} A0{ G} BG_000{ D} - : BGACK_030{ H} CLK_EXP{ B} FPU_CS{ H} - : DSACK1{ H} E{ G} VMA{ D} - : RESET{ B} SIZE_0_{ G}inst_avec_expreg{ G} - :inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ B} inst_VPA_D{ A} - :inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ H}inst_CLK_000_D1{ D} - : inst_DTACK_D0{ B}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B} - : SM_AMIGA_1_{ B} SM_AMIGA_6_{ G} SM_AMIGA_0_{ H} - : SM_AMIGA_7_{ H}inst_RW_000_INT{ G}inst_CLK_000_D2{ H} - : inst_CLK_030_H{ B} SM_AMIGA_5_{ D} SM_AMIGA_4_{ A} - : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_0_{ D} - : cpu_est_1_{ D} cpu_est_2_{ D} - RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} - :inst_RW_000_INT{ G} + FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} + UDS_000{ E}: SIZE_1_{ H} AS_030{ H} SIZE_0_{ G} + : DS_030{ A} A0{ G} RW{ G} + : inst_CLK_030_H{ A} A_28_{ D}: CIIN{ E} + LDS_000{ E}: SIZE_1_{ H} AS_030{ H} SIZE_0_{ G} + : DS_030{ A} A0{ G} RW{ G} + : inst_CLK_030_H{ A} A_27_{ D}: CIIN{ E} A_26_{ D}: CIIN{ E} + nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} + : AS_030{ H} SIZE_0_{ G} DS_030{ A} + : A0{ G} BG_000{ D} DSACK1{ H} + :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ D} + : SM_AMIGA_6_{ G} A_25_{ D}: CIIN{ E} A_24_{ D}: CIIN{ E} + BG_030{ D}: BG_000{ D} A_23_{ I}: CIIN{ E} - SIZE_1_{ I}: LDS_000{ D} + A_22_{ I}: CIIN{ E} + A_21_{ B}: CIIN{ E} + BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} + :inst_AS_030_000_SYNC{ H} + A_20_{ B}: CIIN{ E} + CLK_030{. }: AS_030{ H} DS_030{ A} RW{ G} + : inst_CLK_030_H{ A} + A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ F} + A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + IPL_1_{ G}: IPL_030_1_{ B} + DTACK{ E}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + IPL_0_{ H}: IPL_030_0_{ B} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + VPA{. }: inst_VPA_D{ G} + RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B} + : AS_030{ H} AS_000{ D} SIZE_0_{ G} + : RW_000{ H} DS_030{ A} A0{ G} + : BG_000{ D} BGACK_030{ H} CLK_EXP{ B} + : IPL_030_1_{ B} IPL_030_0_{ B} DSACK1{ H} + : AVEC_EXP{ C} E{ G} VMA{ D} + : RESET{ B} RW{ G}AMIGA_BUS_ENABLE{ D} + :AMIGA_BUS_ENABLE_LOW{ C}inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ H} + : inst_VPA_D{ G}inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE{ B} + :inst_CLK_000_D0{ F}inst_CLK_000_D1{ H}inst_CLK_OUT_PRE_50{ E} + :inst_CLK_OUT_PRE_25{ C}inst_CLK_000_D2{ D}inst_CLK_000_D3{ E} + :inst_CLK_000_NE{ A}inst_CLK_OUT_PRE_D{ C}CLK_000_P_SYNC_9_{ B} + :CLK_000_N_SYNC_11_{ A} SM_AMIGA_7_{ D} SM_AMIGA_6_{ G} + : SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} SM_AMIGA_4_{ B} + : inst_CLK_030_H{ A}inst_LDS_000_INT{ C}inst_DS_000_ENABLE{ B} + :inst_UDS_000_INT{ C}CLK_000_N_SYNC_0_{ F}CLK_000_N_SYNC_1_{ A} + :CLK_000_N_SYNC_2_{ E}CLK_000_N_SYNC_3_{ C}CLK_000_N_SYNC_4_{ A} + :CLK_000_N_SYNC_5_{ A}CLK_000_N_SYNC_6_{ F}CLK_000_N_SYNC_7_{ E} + :CLK_000_N_SYNC_8_{ C}CLK_000_N_SYNC_9_{ F}CLK_000_N_SYNC_10_{ A} + :CLK_000_P_SYNC_0_{ F}CLK_000_P_SYNC_1_{ B}CLK_000_P_SYNC_2_{ C} + :CLK_000_P_SYNC_3_{ A}CLK_000_P_SYNC_4_{ G}CLK_000_P_SYNC_5_{ C} + :CLK_000_P_SYNC_6_{ C}CLK_000_P_SYNC_7_{ A}CLK_000_P_SYNC_8_{ F} + : SM_AMIGA_5_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : cpu_est_0_{ F} cpu_est_1_{ G} cpu_est_2_{ G} + SIZE_1_{ I}:inst_LDS_000_INT{ C} RN_IPL_030_2_{ C}: IPL_030_2_{ B} + AS_030{ I}: BERR{ E} FPU_CS{ H} AS_000{ D} + : BG_000{ D} DSACK1{ H}AMIGA_BUS_ENABLE{ D} + :inst_AS_030_000_SYNC{ H}inst_DS_000_ENABLE{ B} + RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H} + : SIZE_0_{ G} DS_030{ A} A0{ G} + : inst_CLK_030_H{ A} + AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} + : SIZE_0_{ G} DS_030{ A} A0{ G} + : RW{ G} inst_CLK_030_H{ A} + RN_AS_000{ E}: AS_000{ D} VMA{ D} + SIZE_0_{ H}:inst_LDS_000_INT{ C} + RW_000{ I}: DS_030{ A} RW{ G} + RN_RW_000{ I}: RW_000{ H} + DS_030{ B}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ C} + RN_DS_030{ B}: DS_030{ A} + A0{ H}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ C} + RN_BG_000{ E}: BG_000{ D} +RN_BGACK_030{ I}: UDS_000{ D} LDS_000{ D} DTACK{ D} + :AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} + : AS_000{ D} SIZE_0_{ G} RW_000{ H} + : DS_030{ A} A0{ G} BGACK_030{ H} + : RW{ G}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} + :inst_BGACK_030_INT_D{ H} inst_CLK_030_H{ A} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - AS_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : BG_000{ D} FPU_CS{ H} DSACK1{ H} - :inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} - RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H} - : DS_030{ A} A0{ G} SIZE_0_{ G} - : inst_CLK_030_H{ B} - AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} - : DS_030{ A} A0{ G} SIZE_0_{ G} - :inst_RW_000_INT{ G} inst_CLK_030_H{ B} - RN_AS_000{ E}: AS_000{ D} VMA{ D} - DS_030{ B}: UDS_000{ D} LDS_000{ D} - RN_DS_030{ B}: DS_030{ A} - UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} - : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ G} - : inst_CLK_030_H{ B} - RN_UDS_000{ E}: UDS_000{ D} - LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} - : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ G} - : inst_CLK_030_H{ B} - RN_LDS_000{ E}: LDS_000{ D} - A0{ H}: UDS_000{ D} LDS_000{ D} - RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: RW_000{ H} DTACK{ D} RW{ G} - :AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} - : AS_000{ D} DS_030{ A} UDS_000{ D} - : LDS_000{ D} A0{ G} BGACK_030{ H} - : SIZE_0_{ G}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} - :inst_BGACK_030_INT_D{ B}inst_RW_000_INT{ G} inst_CLK_030_H{ B} - RN_FPU_CS{ I}: BERR{ E} FPU_CS{ H} DSACK1{ I}: DTACK{ D} RN_DSACK1{ I}: DSACK1{ H} - RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} cpu_est_1_{ D} cpu_est_2_{ D} - RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - SIZE_0_{ H}: LDS_000{ D} -inst_avec_expreg{ H}: AVEC_EXP{ C}AMIGA_BUS_ENABLE{ D}inst_avec_expreg{ G} -inst_AS_030_000_SYNC{ I}:inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} - : SM_AMIGA_7_{ H} -inst_BGACK_030_INT_D{ C}:inst_avec_expreg{ G} - inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ B} -inst_CLK_000_D0{ I}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : AS_000{ D} UDS_000{ D} LDS_000{ D} - : BGACK_030{ H} E{ G} VMA{ D} - :inst_avec_expreg{ G}inst_CLK_000_D1{ D} SM_AMIGA_1_{ B} - : SM_AMIGA_6_{ G} SM_AMIGA_0_{ H} SM_AMIGA_7_{ H} - :inst_RW_000_INT{ G} SM_AMIGA_5_{ D} SM_AMIGA_4_{ A} - : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_0_{ D} - : cpu_est_1_{ D} cpu_est_2_{ D} -inst_CLK_000_D1{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : BGACK_030{ H} E{ G}inst_avec_expreg{ G} - :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} - :inst_CLK_000_D2{ H} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : cpu_est_0_{ D} cpu_est_1_{ D} cpu_est_2_{ D} -inst_DTACK_D0{ C}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B} -inst_CLK_OUT_PRE_25{ C}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE_25{ B} -SM_AMIGA_1_{ C}: DSACK1{ H}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} - : SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} -SM_AMIGA_6_{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : SM_AMIGA_6_{ G}inst_RW_000_INT{ G} SM_AMIGA_5_{ D} -SM_AMIGA_0_{ I}:inst_avec_expreg{ G} SM_AMIGA_0_{ H} SM_AMIGA_7_{ H} - :inst_RW_000_INT{ G} -SM_AMIGA_7_{ I}: BG_000{ D}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} - : SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} -inst_RW_000_INT{ H}: RW_000{ H} RW{ G}inst_RW_000_INT{ G} -inst_CLK_000_D2{ I}:inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} - : SM_AMIGA_7_{ H} -inst_CLK_030_H{ C}: DS_030{ A} inst_CLK_030_H{ B} -SM_AMIGA_5_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_5_{ D} - : SM_AMIGA_4_{ A} -SM_AMIGA_4_{ B}: SM_AMIGA_4_{ A} SM_AMIGA_3_{ A} -SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -SM_AMIGA_2_{ B}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ A} - cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} - : cpu_est_1_{ D} cpu_est_2_{ D} - cpu_est_1_{ E}: E{ G} VMA{ D} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} cpu_est_1_{ D} cpu_est_2_{ D} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} +RN_AVEC_EXP{ D}: AS_000{ D} RW_000{ H} E{ G} + : SM_AMIGA_7_{ D} SM_AMIGA_6_{ G} SM_AMIGA_1_{ F} + : SM_AMIGA_0_{ D} SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B} + : SM_AMIGA_5_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : cpu_est_0_{ F} cpu_est_1_{ G} cpu_est_2_{ G} + RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} cpu_est_1_{ G} cpu_est_2_{ G} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + RW{ H}:AMIGA_BUS_DATA_DIR{ E} RW_000{ H}inst_DS_000_ENABLE{ B} + RN_RW{ H}: RW{ G} +RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D} +RN_AMIGA_BUS_ENABLE_LOW{ D}: DSACK1{ H} +inst_AS_030_000_SYNC{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ D} + : SM_AMIGA_6_{ G} +inst_BGACK_030_INT_D{ I}:AMIGA_BUS_ENABLE{ D} + inst_VPA_D{ H}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ C} +inst_CLK_OUT_PRE{ C}:AMIGA_BUS_ENABLE_LOW{ C}inst_CLK_OUT_PRE_D{ C} +inst_CLK_000_D0{ G}: IPL_030_2_{ B} BGACK_030{ H} IPL_030_1_{ B} + : IPL_030_0_{ B} VMA{ D}inst_CLK_000_D1{ H} + :CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F} +inst_CLK_000_D1{ I}: IPL_030_2_{ B} BGACK_030{ H} IPL_030_1_{ B} + : IPL_030_0_{ B} DSACK1{ H}AMIGA_BUS_ENABLE{ D} + :inst_CLK_000_D2{ D} SM_AMIGA_7_{ D} SM_AMIGA_6_{ G} + :CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F} +inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_25{ C} +inst_CLK_OUT_PRE_25{ D}:inst_CLK_OUT_PRE{ B}inst_CLK_OUT_PRE_25{ C} +inst_CLK_000_D2{ E}:AMIGA_BUS_ENABLE{ D}inst_CLK_000_D3{ E} SM_AMIGA_7_{ D} + : SM_AMIGA_6_{ G}CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F} +inst_CLK_000_D3{ F}:CLK_000_N_SYNC_0_{ F}CLK_000_P_SYNC_0_{ F} +inst_CLK_000_NE{ B}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_1_{ F} SM_AMIGA_0_{ D} + : SM_AMIGA_4_{ B} SM_AMIGA_5_{ B} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} +inst_CLK_OUT_PRE_D{ D}: CLK_DIV_OUT{ G} CLK_EXP{ B}AMIGA_BUS_ENABLE_LOW{ C} +CLK_000_P_SYNC_9_{ C}: AVEC_EXP{ C} +CLK_000_N_SYNC_11_{ B}:inst_CLK_000_NE{ A} +SM_AMIGA_7_{ E}: RW_000{ H} BG_000{ D}AMIGA_BUS_ENABLE{ D} + :inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ D} SM_AMIGA_6_{ G} +SM_AMIGA_6_{ H}: AS_000{ D} RW_000{ H} SM_AMIGA_6_{ G} + :inst_DS_000_ENABLE{ B} SM_AMIGA_5_{ B} +SM_AMIGA_1_{ G}: DSACK1{ H}AMIGA_BUS_ENABLE{ D} SM_AMIGA_1_{ F} + : SM_AMIGA_0_{ D} +SM_AMIGA_0_{ E}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ D} SM_AMIGA_0_{ D} +SM_AMIGA_4_{ C}: SM_AMIGA_4_{ B}inst_DS_000_ENABLE{ B} SM_AMIGA_3_{ F} +inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A} +inst_LDS_000_INT{ D}: LDS_000{ D}inst_LDS_000_INT{ C} +inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B} +inst_UDS_000_INT{ D}: UDS_000{ D}inst_UDS_000_INT{ C} +CLK_000_N_SYNC_0_{ G}:CLK_000_N_SYNC_1_{ A} +CLK_000_N_SYNC_1_{ B}:CLK_000_N_SYNC_2_{ E} +CLK_000_N_SYNC_2_{ F}:CLK_000_N_SYNC_3_{ C} +CLK_000_N_SYNC_3_{ D}:CLK_000_N_SYNC_4_{ A} +CLK_000_N_SYNC_4_{ B}:CLK_000_N_SYNC_5_{ A} +CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ F} +CLK_000_N_SYNC_6_{ G}:CLK_000_N_SYNC_7_{ E} +CLK_000_N_SYNC_7_{ F}:CLK_000_N_SYNC_8_{ C} +CLK_000_N_SYNC_8_{ D}:CLK_000_N_SYNC_9_{ F} +CLK_000_N_SYNC_9_{ G}:CLK_000_N_SYNC_10_{ A} +CLK_000_N_SYNC_10_{ B}:CLK_000_N_SYNC_11_{ A} +CLK_000_P_SYNC_0_{ G}:CLK_000_P_SYNC_1_{ B} +CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ C} +CLK_000_P_SYNC_2_{ D}:CLK_000_P_SYNC_3_{ A} +CLK_000_P_SYNC_3_{ B}:CLK_000_P_SYNC_4_{ G} +CLK_000_P_SYNC_4_{ H}:CLK_000_P_SYNC_5_{ C} +CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ C} +CLK_000_P_SYNC_6_{ D}:CLK_000_P_SYNC_7_{ A} +CLK_000_P_SYNC_7_{ B}:CLK_000_P_SYNC_8_{ F} +CLK_000_P_SYNC_8_{ G}:CLK_000_P_SYNC_9_{ B} +SM_AMIGA_5_{ C}: SM_AMIGA_4_{ B} SM_AMIGA_5_{ B} +SM_AMIGA_3_{ G}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +SM_AMIGA_2_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} + cpu_est_0_{ G}: E{ G} VMA{ D} cpu_est_0_{ F} + : cpu_est_1_{ G} cpu_est_2_{ G} + cpu_est_1_{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} cpu_est_1_{ G} cpu_est_2_{ G} + cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ G} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -595,11 +658,16 @@ Equations : +-----+-----+-----+-----+------------------------ | * | S | BS | BR | DS_030 | | | | | AVEC -| * | S | BR | BS | SM_AMIGA_2_ -| * | S | BS | BR | inst_VPA_D +| * | S | BR | BS | inst_CLK_000_NE | * | S | BS | BR | RN_DS_030 -| * | S | BR | BS | SM_AMIGA_3_ -| * | S | BR | BS | SM_AMIGA_4_ +| * | S | BR | BR | inst_CLK_030_H +| * | S | BR | BS | CLK_000_P_SYNC_7_ +| * | S | BR | BS | CLK_000_P_SYNC_3_ +| * | S | BR | BS | CLK_000_N_SYNC_10_ +| * | S | BR | BS | CLK_000_N_SYNC_5_ +| * | S | BR | BS | CLK_000_N_SYNC_4_ +| * | S | BR | BS | CLK_000_N_SYNC_1_ +| * | S | BR | BS | CLK_000_N_SYNC_11_ | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ @@ -619,14 +687,15 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | S | BR | BS | CLK_EXP | * | S | BR | BS | RESET -| * | S | BR | BS | SM_AMIGA_1_ -| * | S | BR | BR | inst_CLK_030_H -| * | S | BR | BS | inst_CLK_OUT_PRE_25 +| * | S | BR | BS | inst_DS_000_ENABLE +| * | S | BR | BS | SM_AMIGA_4_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ -| * | S | BS | BR | inst_DTACK_D0 -| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BR | BS | SM_AMIGA_5_ +| * | S | BR | BS | CLK_000_P_SYNC_1_ +| * | S | BR | BS | CLK_000_P_SYNC_9_ +| * | S | BR | BS | inst_CLK_OUT_PRE | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ @@ -634,13 +703,24 @@ Equations : Block C block level set pt : -block level reset pt : +block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| | | | | AVEC_EXP -| | | | | AMIGA_BUS_ENABLE_LOW +| * | S | BS | BR | AVEC_EXP +| * | S | BS | BR | AMIGA_BUS_ENABLE_LOW +| * | S | BS | BR | RN_AVEC_EXP +| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | inst_CLK_OUT_PRE_25 +| * | S | BR | BS | inst_UDS_000_INT +| * | S | BR | BS | inst_LDS_000_INT +| * | S | BS | BR | RN_AMIGA_BUS_ENABLE_LOW +| * | S | BS | BR | CLK_000_P_SYNC_6_ +| * | S | BS | BR | CLK_000_P_SYNC_5_ +| * | S | BS | BR | CLK_000_P_SYNC_2_ +| * | S | BS | BR | CLK_000_N_SYNC_8_ +| * | S | BS | BR | CLK_000_N_SYNC_3_ | | | | | BG_030 | | | | | A_24_ | | | | | A_25_ @@ -657,28 +737,25 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_000 -| * | S | BS | BR | LDS_000 -| * | S | BS | BR | UDS_000 +| | | | | UDS_000 +| | | | | LDS_000 | | | | | DTACK +| * | S | BS | BR | AMIGA_BUS_ENABLE | * | S | BS | BR | VMA | * | S | BS | BR | BG_000 -| | | | | AMIGA_BUS_ENABLE -| * | S | BS | BR | inst_CLK_000_D1 -| * | S | BR | BS | cpu_est_1_ -| * | S | BR | BS | cpu_est_2_ -| * | S | BR | BS | cpu_est_0_ +| * | S | BS | BR | inst_CLK_000_D2 +| * | S | BS | BR | SM_AMIGA_7_ | * | S | BS | BR | RN_VMA -| * | S | BR | BS | SM_AMIGA_5_ -| * | S | BS | BR | RN_LDS_000 -| * | S | BS | BR | RN_UDS_000 +| * | S | BS | BR | RN_AMIGA_BUS_ENABLE | * | S | BS | BR | RN_BG_000 | * | S | BS | BR | RN_AS_000 +| * | S | BR | BS | SM_AMIGA_0_ | | | | | BGACK_000 Block E block level set pt : -block level reset pt : +block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name @@ -686,15 +763,29 @@ Equations : | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN | | | | | BERR +| * | S | BS | BR | inst_CLK_OUT_PRE_50 +| * | S | BS | BR | CLK_000_N_SYNC_7_ +| * | S | BS | BR | CLK_000_N_SYNC_2_ +| * | S | BR | BS | inst_CLK_000_D3 Block F -block level set pt : +block level set pt : !RST block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_CLK_000_D0 +| * | S | BR | BS | cpu_est_0_ +| * | S | BR | BS | SM_AMIGA_1_ +| * | S | BR | BS | SM_AMIGA_3_ +| * | S | BR | BS | SM_AMIGA_2_ +| * | S | BR | BS | CLK_000_P_SYNC_8_ +| * | S | BR | BS | CLK_000_P_SYNC_0_ +| * | S | BR | BS | CLK_000_N_SYNC_9_ +| * | S | BR | BS | CLK_000_N_SYNC_6_ +| * | S | BR | BS | CLK_000_N_SYNC_0_ | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -702,21 +793,24 @@ Equations : Block G -block level set pt : -block level reset pt : !RST +block level set pt : !RST +block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| | | | | RW -| * | S | BR | BS | SIZE_0_ -| * | S | BR | BS | A0 -| * | S | BS | BR | E -| * | S | BS | BR | CLK_DIV_OUT -| * | S | BR | BS | inst_avec_expreg -| * | S | BS | BR | RN_E -| * | S | BR | BS | inst_RW_000_INT -| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | RW +| * | S | BS | BR | SIZE_0_ +| * | S | BS | BR | A0 +| * | S | BR | BS | E +| * | S | BR | BS | CLK_DIV_OUT +| * | S | BR | BS | SM_AMIGA_6_ +| * | S | BR | BS | cpu_est_1_ +| * | S | BR | BS | RN_E +| * | S | BR | BS | cpu_est_2_ +| * | S | BS | BR | inst_VPA_D +| * | S | BS | BR | RN_RW +| * | S | BR | BS | CLK_000_P_SYNC_4_ | | | | | IPL_2_ | | | | | IPL_0_ @@ -729,22 +823,19 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_030 -| | | | | RW_000 +| * | S | BS | BR | RW_000 | * | S | BS | BR | DSACK1 | * | S | BS | BR | SIZE_1_ | * | S | BS | BR | BGACK_030 -| * | S | BS | BR | FPU_CS +| | | | | FPU_CS | * | S | BS | BR | RN_BGACK_030 +| * | S | BS | BR | inst_CLK_000_D1 | * | S | BS | BR | RN_AS_030 -| * | S | BS | BR | inst_CLK_000_D0 -| * | S | BS | BR | SM_AMIGA_7_ | * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | RN_FPU_CS -| * | S | BR | BS | SM_AMIGA_0_ -| * | S | BS | BR | inst_CLK_000_D2 -| * | S | BR | BS | inst_CLK_OUT_PRE_50 +| * | S | BS | BR | RN_RW_000 | * | S | BS | BR | RN_DSACK1 | * | S | BR | BS | inst_CLK_OUT_PRE_50_D +| * | S | BS | BR | inst_BGACK_030_INT_D | | | | | A_22_ | | | | | A_23_ @@ -763,22 +854,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 RST pin 86 mx A17 RN_VMA mcell D1 -mx A1 SM_AMIGA_3_ mcell A4 mx A18 ... ... -mx A2 SM_AMIGA_4_ mcell A5 mx A19 ... ... -mx A3 SM_AMIGA_5_ mcell D11 mx A20 RN_BGACK_030 mcell H4 +mx A0 RST pin 86 mx A17 ... ... +mx A1CLK_000_N_SYNC_0_ mcell F6 mx A18 ... ... +mx A2CLK_000_N_SYNC_10_ mcell A9 mx A19 ... ... +mx A3 ... ... mx A20 ... ... mx A4 CLK_030 pin 64 mx A21 RN_AS_030 mcell H6 -mx A5 nEXP_SPACE pin 14 mx A22 ... ... -mx A6 RW_000 pin 80 mx A23 RN_E mcell G2 -mx A7 inst_CLK_000_D1 mcell D5 mx A24 LDS_000 pin 31 -mx A8 inst_DTACK_D0 mcell B8 mx A25 inst_VPA_D mcell A3 -mx A9 SM_AMIGA_2_ mcell A1 mx A26 AS_000 pin 33 -mx A10 VPA pin 36 mx A27 ... ... -mx A11 inst_CLK_000_D0 mcell H3 mx A28 inst_CLK_030_H mcell B5 -mx A12 UDS_000 pin 32 mx A29 ... ... -mx A13 cpu_est_1_ mcell D7 mx A30 ... ... +mx A5 nEXP_SPACE pin 14 mx A22CLK_000_N_SYNC_4_ mcell A2 +mx A6CLK_000_N_SYNC_9_ mcell F13 mx A23 AS_000 pin 33 +mx A7CLK_000_N_SYNC_3_ mcell C14 mx A24 LDS_000 pin 31 +mx A8CLK_000_N_SYNC_11_ mcell A10 mx A25 ... ... +mx A9CLK_000_P_SYNC_2_ mcell C6 mx A26 ... ... +mx A10 ... ... mx A27 ... ... +mx A11CLK_000_P_SYNC_6_ mcell C13 mx A28 RW_000 pin 80 +mx A12 UDS_000 pin 32 mx A29 RN_DS_030 mcell A0 +mx A13 RN_BGACK_030 mcell H5 mx A30 ... ... mx A14 ... ... mx A31 ... ... -mx A15 RN_DS_030 mcell A0 mx A32 ... ... +mx A15 inst_CLK_030_H mcell A12 mx A32 ... ... mx A16 ... ... ---------------------------------------------------------------------------- @@ -787,23 +878,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 LDS_000 pin 31 mx B17 ... ... -mx B1inst_CLK_OUT_PRE_50 mcell H11 mx B18 ... ... -mx B2 RN_IPL_030_1_ mcell B6 mx B19 ... ... -mx B3 IPL_1_ pin 56 mx B20 CLK_030 pin 64 +mx B0 IPL_0_ pin 67 mx B17 ... ... +mx B1CLK_000_P_SYNC_0_ mcell F9 mx B18 inst_CLK_000_NE mcell A8 +mx B2 ... ... mx B19 AS_030 pin 82 +mx B3 IPL_1_ pin 56 mx B20 ... ... mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5 SM_AMIGA_1_ mcell B3 mx B22 ... ... -mx B6 ... ... mx B23 RN_BGACK_030 mcell H4 -mx B7 inst_CLK_000_D1 mcell D5 mx B24inst_CLK_OUT_PRE_25 mcell B7 -mx B8inst_CLK_OUT_PRE_50_D mcell H12 mx B25 ... ... -mx B9 SM_AMIGA_2_ mcell A1 mx B26 AS_000 pin 33 -mx B10 RN_IPL_030_2_ mcell B2 mx B27 RN_IPL_030_0_ mcell B4 -mx B11 inst_CLK_000_D0 mcell H3 mx B28 inst_CLK_030_H mcell B5 -mx B12 UDS_000 pin 32 mx B29 ... ... -mx B13 ... ... mx B30 RN_AS_030 mcell H6 -mx B14 DTACK pin 30 mx B31 ... ... -mx B15 ... ... mx B32 ... ... -mx B16 IPL_0_ pin 67 +mx B5 inst_CLK_000_D0 mcell F0 mx B22inst_CLK_OUT_PRE_25 mcell C1 +mx B6 SM_AMIGA_4_ mcell B9 mx B23 ... ... +mx B7inst_CLK_OUT_PRE_D mcell C8 mx B24 ... ... +mx B8 RN_IPL_030_0_ mcell B8 mx B25 RW pin 71 +mx B9CLK_000_P_SYNC_8_ mcell F5 mx B26 ... ... +mx B10 SM_AMIGA_5_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 inst_CLK_000_D1 mcell H9 mx B28inst_DS_000_ENABLE mcell B5 +mx B12 RN_IPL_030_1_ mcell B12 mx B29 ... ... +mx B13 ... ... mx B30 ... ... +mx B14 RN_AVEC_EXP mcell C4 mx B31 ... ... +mx B15 ... ... mx B32 SM_AMIGA_6_ mcell G5 +mx B16 ... ... ---------------------------------------------------------------------------- @@ -811,23 +902,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 ... ... mx C17 ... ... -mx C1 ... ... mx C18 ... ... -mx C2inst_avec_expreg mcell G4 mx C19 ... ... -mx C3 ... ... mx C20 ... ... +mx C0 RST pin 86 mx C17 ... ... +mx C1inst_CLK_OUT_PRE_25 mcell C1 mx C18 A0 pin 69 +mx C2inst_CLK_OUT_PRE mcell B10 mx C19 ... ... +mx C3CLK_000_N_SYNC_2_ mcell E5 mx C20 ... ... mx C4 ... ... mx C21 ... ... -mx C5 ... ... mx C22 ... ... -mx C6 ... ... mx C23 ... ... -mx C7 ... ... mx C24 ... ... -mx C8 ... ... mx C25 ... ... +mx C5CLK_000_N_SYNC_7_ mcell E1 mx C22CLK_000_P_SYNC_5_ mcell C2 +mx C6 SIZE_1_ pin 79 mx C23CLK_000_P_SYNC_4_ mcell G6 +mx C7inst_CLK_OUT_PRE_50_D mcell H13 mx C24 ... ... +mx C8inst_CLK_OUT_PRE_50 mcell E8 mx C25 ... ... mx C9 ... ... mx C26 ... ... -mx C10 ... ... mx C27 ... ... -mx C11 ... ... mx C28 ... ... -mx C12 ... ... mx C29 ... ... -mx C13 ... ... mx C30 ... ... -mx C14 ... ... mx C31 ... ... -mx C15 ... ... mx C32 ... ... -mx C16 ... ... +mx C10CLK_000_P_SYNC_1_ mcell B2 mx C27 ... ... +mx C11CLK_000_P_SYNC_9_ mcell B6 mx C28 ... ... +mx C12 DS_030 pin 98 mx C29 ... ... +mx C13inst_LDS_000_INT mcell C9 mx C30 ... ... +mx C14 SIZE_0_ pin 70 mx C31 ... ... +mx C15inst_UDS_000_INT mcell C5 mx C32 ... ... +mx C16inst_CLK_OUT_PRE_D mcell C8 ---------------------------------------------------------------------------- @@ -835,23 +926,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RN_BGACK_030 mcell H4 mx D17 SIZE_0_ pin 70 -mx D1 ... ... mx D18 A0 pin 69 -mx D2inst_avec_expreg mcell G4 mx D19 SM_AMIGA_5_ mcell D11 -mx D3 RN_BG_000 mcell D2 mx D20 cpu_est_0_ mcell D10 -mx D4 SM_AMIGA_7_ mcell H5 mx D21 RST pin 86 -mx D5 DS_030 pin 98 mx D22 BG_030 pin 21 -mx D6 SIZE_1_ pin 79 mx D23 SM_AMIGA_6_ mcell G6 -mx D7 RN_AS_030 mcell H6 mx D24 CLK_000 pin 11 -mx D8 RW pin 71 mx D25 inst_VPA_D mcell A3 -mx D9 AS_030 pin 82 mx D26 ... ... -mx D10 inst_CLK_000_D0 mcell H3 mx D27 RN_VMA mcell D1 -mx D11 inst_CLK_000_D1 mcell D5 mx D28 ... ... -mx D12 cpu_est_2_ mcell D9 mx D29 ... ... -mx D13 cpu_est_1_ mcell D7 mx D30 RN_UDS_000 mcell D6 -mx D14 RN_AS_000 mcell D4 mx D31 RN_E mcell G2 -mx D15 nEXP_SPACE pin 14 mx D32 DSACK1 pin 81 -mx D16 RN_LDS_000 mcell D8 +mx D0inst_AS_030_000_SYNC mcell H4 mx D17 DSACK1 pin 81 +mx D1 RN_BG_000 mcell D13 mx D18inst_BGACK_030_INT_D mcell H10 +mx D2 RN_VMA mcell D1 mx D19 AS_030 pin 82 +mx D3 SM_AMIGA_7_ mcell D2 mx D20 SM_AMIGA_1_ mcell F8 +mx D4 RN_BGACK_030 mcell H5 mx D21 RST pin 86 +mx D5 inst_CLK_000_D1 mcell H9 mx D22 BG_030 pin 21 +mx D6 RN_AVEC_EXP mcell C4 mx D23 inst_VPA_D mcell G2 +mx D7 RN_AS_030 mcell H6 mx D24RN_AMIGA_BUS_ENABLE mcell D5 +mx D8 ... ... mx D25 inst_CLK_000_D0 mcell F0 +mx D9 cpu_est_2_ mcell G13 mx D26 ... ... +mx D10 RN_AS_000 mcell D4 mx D27 cpu_est_1_ mcell G9 +mx D11 RN_E mcell G4 mx D28inst_UDS_000_INT mcell C5 +mx D12 inst_CLK_000_D2 mcell D9 mx D29 cpu_est_0_ mcell F4 +mx D13inst_LDS_000_INT mcell C9 mx D30 inst_CLK_000_NE mcell A8 +mx D14 CLK_000 pin 11 mx D31inst_DS_000_ENABLE mcell B5 +mx D15 nEXP_SPACE pin 14 mx D32 SM_AMIGA_6_ mcell G5 +mx D16 SM_AMIGA_0_ mcell D6 ---------------------------------------------------------------------------- @@ -859,23 +950,47 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17 -mx E1 A_31_ pin 4 mx E18 ... ... -mx E2 ... ... mx E19 ... ... -mx E3 A_27_ pin 16 mx E20 ... ... +mx E0 RST pin 86 mx E17 FC_0_ pin 57 +mx E1 A_31_ pin 4 mx E18 A_22_ pin 85 +mx E2 ... ... mx E19 AS_030 pin 82 +mx E3 A_27_ pin 16 mx E20 FC_1_ pin 58 mx E4 A_29_ pin 6 mx E21 nEXP_SPACE pin 14 -mx E5 A_24_ pin 19 mx E22 ... ... -mx E6 ... ... mx E23 AS_000 pin 33 +mx E5 A_21_ pin 94 mx E22 ... ... +mx E6 A_19_ pin 97 mx E23 AS_000 pin 33 mx E7 A_28_ pin 15 mx E24 ... ... -mx E8 A_22_ pin 85 mx E25 RW pin 71 -mx E9 A_30_ pin 5 mx E26 ... ... -mx E10 ... ... mx E27 ... ... -mx E11 A_23_ pin 84 mx E28 ... ... +mx E8 RW pin 71 mx E25 inst_CLK_000_D2 mcell D9 +mx E9 A_26_ pin 17 mx E26 A_16_ pin 96 +mx E10CLK_000_N_SYNC_1_ mcell A6 mx E27 RN_BGACK_030 mcell H5 +mx E11 A_23_ pin 84 mx E28 A_30_ pin 5 mx E12 A_25_ pin 18 mx E29 A_20_ pin 93 -mx E13 ... ... mx E30 ... ... -mx E14 RN_FPU_CS mcell H2 mx E31 ... ... -mx E15 A_21_ pin 94 mx E32 ... ... -mx E16 ... ... +mx E13 A_17_ pin 59 mx E30 ... ... +mx E14 A_24_ pin 19 mx E31 A_18_ pin 95 +mx E15CLK_000_N_SYNC_6_ mcell F2 mx E32 BGACK_000 pin 28 +mx E16inst_CLK_OUT_PRE_50 mcell E8 +---------------------------------------------------------------------------- + + +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0 RST pin 86 mx F17 RN_VMA mcell D1 +mx F1 SM_AMIGA_3_ mcell F12 mx F18 inst_CLK_000_NE mcell A8 +mx F2 inst_CLK_000_D3 mcell E9 mx F19 ... ... +mx F3 CLK_000 pin 11 mx F20 SM_AMIGA_1_ mcell F8 +mx F4 inst_VPA_D mcell G2 mx F21 ... ... +mx F5 inst_CLK_000_D0 mcell F0 mx F22 ... ... +mx F6 SM_AMIGA_4_ mcell B9 mx F23 DTACK pin 30 +mx F7 inst_CLK_000_D2 mcell D9 mx F24 ... ... +mx F8CLK_000_N_SYNC_8_ mcell C10 mx F25CLK_000_N_SYNC_5_ mcell A13 +mx F9CLK_000_P_SYNC_7_ mcell A1 mx F26 ... ... +mx F10 SM_AMIGA_2_ mcell F1 mx F27 inst_CLK_000_D1 mcell H9 +mx F11 RN_E mcell G4 mx F28 ... ... +mx F12 cpu_est_1_ mcell G9 mx F29 RN_AVEC_EXP mcell C4 +mx F13 ... ... mx F30 ... ... +mx F14 cpu_est_0_ mcell F4 mx F31 ... ... +mx F15 ... ... mx F32 ... ... +mx F16 ... ... ---------------------------------------------------------------------------- @@ -883,22 +998,22 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 LDS_000 pin 31 mx G17 ... ... -mx G1inst_CLK_OUT_PRE_25 mcell B7 mx G18 inst_CLK_000_D2 mcell H10 -mx G2 cpu_est_0_ mcell D10 mx G19 ... ... -mx G3 inst_RW_000_INT mcell G5 mx G20 RN_BGACK_030 mcell H4 -mx G4 CLK_030 pin 64 mx G21 RST pin 86 -mx G5 SM_AMIGA_0_ mcell H9 mx G22 ... ... -mx G6inst_BGACK_030_INT_D mcell B9 mx G23 SM_AMIGA_6_ mcell G6 -mx G7 cpu_est_2_ mcell D9 mx G24 inst_CLK_000_D1 mcell D5 -mx G8 cpu_est_1_ mcell D7 mx G25 RW pin 71 -mx G9 AS_030 pin 82 mx G26 AS_000 pin 33 -mx G10 inst_CLK_000_D0 mcell H3 mx G27 SM_AMIGA_7_ mcell H5 -mx G11inst_avec_expreg mcell G4 mx G28 RW_000 pin 80 -mx G12 UDS_000 pin 32 mx G29inst_AS_030_000_SYNC mcell H7 -mx G13 SM_AMIGA_1_ mcell B3 mx G30 RN_AS_030 mcell H6 -mx G14 ... ... mx G31 RN_E mcell G2 -mx G15 nEXP_SPACE pin 14 mx G32 ... ... +mx G0 RST pin 86 mx G17 RN_RW mcell G0 +mx G1 ... ... mx G18 ... ... +mx G2CLK_000_P_SYNC_3_ mcell A5 mx G19 ... ... +mx G3 SM_AMIGA_7_ mcell D2 mx G20inst_AS_030_000_SYNC mcell H4 +mx G4 CLK_030 pin 64 mx G21 RN_AS_030 mcell H6 +mx G5 nEXP_SPACE pin 14 mx G22 SM_AMIGA_6_ mcell G5 +mx G6 RN_AVEC_EXP mcell C4 mx G23 AS_000 pin 33 +mx G7inst_CLK_OUT_PRE_D mcell C8 mx G24 LDS_000 pin 31 +mx G8 UDS_000 pin 32 mx G25 inst_CLK_000_D2 mcell D9 +mx G9 cpu_est_2_ mcell G13 mx G26 ... ... +mx G10 VPA pin 36 mx G27 inst_CLK_000_D1 mcell H9 +mx G11 RN_E mcell G4 mx G28 RW_000 pin 80 +mx G12 cpu_est_1_ mcell G9 mx G29 ... ... +mx G13 RN_BGACK_030 mcell H5 mx G30 ... ... +mx G14 cpu_est_0_ mcell F4 mx G31 ... ... +mx G15 ... ... mx G32 ... ... mx G16 ... ... ---------------------------------------------------------------------------- @@ -907,23 +1022,23 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 LDS_000 pin 31 mx H17 FC_0_ pin 57 -mx H1 FC_1_ pin 58 mx H18 inst_CLK_000_D2 mcell H10 -mx H2 ... ... mx H19 SM_AMIGA_1_ mcell B3 -mx H3 CLK_000 pin 11 mx H20inst_AS_030_000_SYNC mcell H7 -mx H4 BGACK_000 pin 28 mx H21 RST pin 86 -mx H5 SM_AMIGA_0_ mcell H9 mx H22inst_CLK_OUT_PRE_50 mcell H11 -mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4 -mx H7 RN_AS_030 mcell H6 mx H24 inst_CLK_000_D1 mcell D5 -mx H8 A_17_ pin 59 mx H25 ... ... +mx H0inst_AS_030_000_SYNC mcell H4 mx H17 FC_0_ pin 57 +mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 +mx H2 SM_AMIGA_1_ mcell F8 mx H19 ... ... +mx H3 SM_AMIGA_7_ mcell D2 mx H20 CLK_030 pin 64 +mx H4 A_18_ pin 95 mx H21 RST pin 86 +mx H5 inst_CLK_000_D1 mcell H9 mx H22 SM_AMIGA_6_ mcell G5 +mx H6 A_19_ pin 97 mx H23RN_AMIGA_BUS_ENABLE_LOW mcell C12 +mx H7 RN_AS_030 mcell H6 mx H24 LDS_000 pin 31 +mx H8 RW pin 71 mx H25 inst_CLK_000_D0 mcell F0 mx H9 AS_030 pin 82 mx H26 AS_000 pin 33 -mx H10 inst_CLK_000_D0 mcell H3 mx H27 SM_AMIGA_7_ mcell H5 -mx H11 A_16_ pin 96 mx H28 CLK_030 pin 64 -mx H12 UDS_000 pin 32 mx H29 ... ... -mx H13 RN_DSACK1 mcell H8 mx H30 ... ... -mx H14 RN_FPU_CS mcell H2 mx H31 A_18_ pin 95 -mx H15 nEXP_SPACE pin 14 mx H32 inst_RW_000_INT mcell G5 -mx H16 ... ... +mx H10 ... ... mx H27 A_17_ pin 59 +mx H11 A_16_ pin 96 mx H28 ... ... +mx H12 UDS_000 pin 32 mx H29 RN_DSACK1 mcell H12 +mx H13 RN_BGACK_030 mcell H5 mx H30 RN_RW_000 mcell H0 +mx H14 RN_AVEC_EXP mcell C4 mx H31 ... ... +mx H15 nEXP_SPACE pin 14 mx H32 ... ... +mx H16inst_CLK_OUT_PRE_50 mcell E8 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -938,22 +1053,20 @@ PostFit_Equations P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- - 1 1 1 Pin RW_000 - 1 1 1 Pin RW_000.OE + 1 2 1 Pin UDS_000- + 1 1 1 Pin UDS_000.OE + 1 2 1 Pin LDS_000- + 1 1 1 Pin LDS_000.OE 0 0 1 Pin BERR - 1 1 1 Pin BERR.OE + 1 8 1 Pin BERR.OE 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C + 1 8 1 Pin FPU_CS- 1 1 1 Pin DTACK 1 3 1 Pin DTACK.OE 1 0 1 Pin AVEC - 1 1 1 Pin AVEC_EXP - 1 1 1 Pin RW - 1 1 1 Pin RW.OE - 1 1 1 Pin AMIGA_BUS_ENABLE 2 4 1 Pin AMIGA_BUS_DATA_DIR - 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE 1 3 1 Pin SIZE_1_.OE @@ -963,12 +1076,6 @@ PostFit_Equations 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C - 3 4 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C - 3 4 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin AS_030.OE 4 6 1 Pin AS_030.D 1 1 1 Pin AS_030.AP @@ -977,18 +1084,18 @@ PostFit_Equations 2 4 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C + 1 3 1 Pin SIZE_0_.OE + 1 4 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.AP + 1 1 1 Pin SIZE_0_.C + 1 1 1 Pin RW_000.OE + 3 5 1 Pin RW_000.D- + 1 1 1 Pin RW_000.AP + 1 1 1 Pin RW_000.C 1 3 1 Pin DS_030.OE 7 9 1 Pin DS_030.D 1 1 1 Pin DS_030.AP 1 1 1 Pin DS_030.C - 1 1 1 Pin UDS_000.OE - 7 8 1 Pin UDS_000.D- - 1 1 1 Pin UDS_000.AP - 1 1 1 Pin UDS_000.C - 1 1 1 Pin LDS_000.OE - 11 10 1 Pin LDS_000.D- - 1 1 1 Pin LDS_000.AP - 1 1 1 Pin LDS_000.C 1 3 1 Pin A0.OE 1 4 1 Pin A0.D 1 1 1 Pin A0.AP @@ -1002,16 +1109,21 @@ PostFit_Equations 1 1 1 Pin CLK_EXP.AR 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C - 2 10 1 Pin FPU_CS.D- - 1 1 1 Pin FPU_CS.AP - 1 1 1 Pin FPU_CS.C + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C 1 1 1 Pin DSACK1.OE - 2 3 1 Pin DSACK1.D + 2 5 1 Pin DSACK1.D- 1 1 1 Pin DSACK1.AP 1 1 1 Pin DSACK1.C - 3 6 1 PinX1 E.D.X1 - 1 1 1 PinX2 E.D.X2 + 1 1 1 Pin AVEC_EXP.AR + 1 1 1 Pin AVEC_EXP.D + 1 1 1 Pin AVEC_EXP.C 1 1 1 Pin E.AR + 4 5 1 Pin E.D- 1 1 1 Pin E.C 2 7 1 PinX1 VMA.D.X1 1 5 1 PinX2 VMA.D.X2 @@ -1020,14 +1132,17 @@ PostFit_Equations 1 1 1 Pin RESET.AR 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C - 1 3 1 Pin SIZE_0_.OE - 1 4 1 Pin SIZE_0_.D- - 1 1 1 Pin SIZE_0_.AP - 1 1 1 Pin SIZE_0_.C - 6 12 1 Node inst_avec_expreg.D- - 1 1 1 Node inst_avec_expreg.AP - 1 1 1 Node inst_avec_expreg.C - 8 16 1 Node inst_AS_030_000_SYNC.D + 1 1 1 Pin RW.OE + 4 7 1 Pin RW.D- + 1 1 1 Pin RW.AP + 1 1 1 Pin RW.C + 6 12 1 Pin AMIGA_BUS_ENABLE.D- + 1 1 1 Pin AMIGA_BUS_ENABLE.AP + 1 1 1 Pin AMIGA_BUS_ENABLE.C + 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.AR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW.D + 1 1 1 Pin AMIGA_BUS_ENABLE_LOW.C + 5 12 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C 1 1 1 Node inst_BGACK_030_INT_D.D @@ -1039,105 +1154,181 @@ PostFit_Equations 1 1 1 Node inst_CLK_OUT_PRE_50_D.AR 1 1 1 Node inst_CLK_OUT_PRE_50_D.D 1 1 1 Node inst_CLK_OUT_PRE_50_D.C + 1 1 1 Node inst_CLK_OUT_PRE.AR + 1 1 1 Node inst_CLK_OUT_PRE.D + 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node inst_CLK_000_D0.D 1 1 1 Node inst_CLK_000_D0.AP 1 1 1 Node inst_CLK_000_D0.C 1 1 1 Node inst_CLK_000_D1.D 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C - 1 1 1 Node inst_DTACK_D0.D - 1 1 1 Node inst_DTACK_D0.AP - 1 1 1 Node inst_DTACK_D0.C 1 1 1 Node inst_CLK_OUT_PRE_50.AR 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C 1 1 1 Node inst_CLK_OUT_PRE_25.AR 3 3 1 Node inst_CLK_OUT_PRE_25.D 1 1 1 Node inst_CLK_OUT_PRE_25.C - 1 1 1 Node SM_AMIGA_1_.AR - 2 3 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C - 1 1 1 Node SM_AMIGA_6_.AR - 2 7 1 Node SM_AMIGA_6_.D - 1 1 1 Node SM_AMIGA_6_.C - 1 1 1 Node SM_AMIGA_0_.AR - 2 3 1 Node SM_AMIGA_0_.D - 1 1 1 Node SM_AMIGA_0_.C - 4 7 1 Node SM_AMIGA_7_.D- - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C - 14 11 1 Node inst_RW_000_INT.D- - 1 1 1 Node inst_RW_000_INT.AP - 1 1 1 Node inst_RW_000_INT.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.AP 1 1 1 Node inst_CLK_000_D2.C + 1 1 1 Node inst_CLK_000_D3.D + 1 1 1 Node inst_CLK_000_D3.AP + 1 1 1 Node inst_CLK_000_D3.C + 1 1 1 Node inst_CLK_000_NE.AR + 1 1 1 Node inst_CLK_000_NE.D + 1 1 1 Node inst_CLK_000_NE.C + 1 1 1 Node inst_CLK_OUT_PRE_D.AR + 1 1 1 Node inst_CLK_OUT_PRE_D.D + 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 1 1 Node CLK_000_P_SYNC_9_.AR + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_11_.AR + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 4 7 1 Node SM_AMIGA_7_.D- + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_6_.AR + 2 7 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C + 1 1 1 Node SM_AMIGA_1_.AR + 2 4 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node SM_AMIGA_0_.AR + 2 4 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 1 1 1 Node SM_AMIGA_4_.AR + 2 4 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C 5 8 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C + 2 5 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.AP + 1 1 1 Node inst_LDS_000_INT.C + 1 1 1 Node inst_DS_000_ENABLE.AR + 3 6 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 2 3 1 Node inst_UDS_000_INT.D + 1 1 1 Node inst_UDS_000_INT.AP + 1 1 1 Node inst_UDS_000_INT.C + 1 1 1 Node CLK_000_N_SYNC_0_.AR + 1 4 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_N_SYNC_1_.AR + 1 1 1 Node CLK_000_N_SYNC_1_.D + 1 1 1 Node CLK_000_N_SYNC_1_.C + 1 1 1 Node CLK_000_N_SYNC_2_.AR + 1 1 1 Node CLK_000_N_SYNC_2_.D + 1 1 1 Node CLK_000_N_SYNC_2_.C + 1 1 1 Node CLK_000_N_SYNC_3_.AR + 1 1 1 Node CLK_000_N_SYNC_3_.D + 1 1 1 Node CLK_000_N_SYNC_3_.C + 1 1 1 Node CLK_000_N_SYNC_4_.AR + 1 1 1 Node CLK_000_N_SYNC_4_.D + 1 1 1 Node CLK_000_N_SYNC_4_.C + 1 1 1 Node CLK_000_N_SYNC_5_.AR + 1 1 1 Node CLK_000_N_SYNC_5_.D + 1 1 1 Node CLK_000_N_SYNC_5_.C + 1 1 1 Node CLK_000_N_SYNC_6_.AR + 1 1 1 Node CLK_000_N_SYNC_6_.D + 1 1 1 Node CLK_000_N_SYNC_6_.C + 1 1 1 Node CLK_000_N_SYNC_7_.AR + 1 1 1 Node CLK_000_N_SYNC_7_.D + 1 1 1 Node CLK_000_N_SYNC_7_.C + 1 1 1 Node CLK_000_N_SYNC_8_.AR + 1 1 1 Node CLK_000_N_SYNC_8_.D + 1 1 1 Node CLK_000_N_SYNC_8_.C + 1 1 1 Node CLK_000_N_SYNC_9_.AR + 1 1 1 Node CLK_000_N_SYNC_9_.D + 1 1 1 Node CLK_000_N_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_10_.AR + 1 1 1 Node CLK_000_N_SYNC_10_.D + 1 1 1 Node CLK_000_N_SYNC_10_.C + 1 1 1 Node CLK_000_P_SYNC_0_.AR + 1 4 1 Node CLK_000_P_SYNC_0_.D + 1 1 1 Node CLK_000_P_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_1_.AR + 1 1 1 Node CLK_000_P_SYNC_1_.D + 1 1 1 Node CLK_000_P_SYNC_1_.C + 1 1 1 Node CLK_000_P_SYNC_2_.AR + 1 1 1 Node CLK_000_P_SYNC_2_.D + 1 1 1 Node CLK_000_P_SYNC_2_.C + 1 1 1 Node CLK_000_P_SYNC_3_.AR + 1 1 1 Node CLK_000_P_SYNC_3_.D + 1 1 1 Node CLK_000_P_SYNC_3_.C + 1 1 1 Node CLK_000_P_SYNC_4_.AR + 1 1 1 Node CLK_000_P_SYNC_4_.D + 1 1 1 Node CLK_000_P_SYNC_4_.C + 1 1 1 Node CLK_000_P_SYNC_5_.AR + 1 1 1 Node CLK_000_P_SYNC_5_.D + 1 1 1 Node CLK_000_P_SYNC_5_.C + 1 1 1 Node CLK_000_P_SYNC_6_.AR + 1 1 1 Node CLK_000_P_SYNC_6_.D + 1 1 1 Node CLK_000_P_SYNC_6_.C + 1 1 1 Node CLK_000_P_SYNC_7_.AR + 1 1 1 Node CLK_000_P_SYNC_7_.D + 1 1 1 Node CLK_000_P_SYNC_7_.C + 1 1 1 Node CLK_000_P_SYNC_8_.AR + 1 1 1 Node CLK_000_P_SYNC_8_.D + 1 1 1 Node CLK_000_P_SYNC_8_.C 1 1 1 Node SM_AMIGA_5_.AR - 2 3 1 Node SM_AMIGA_5_.D + 2 4 1 Node SM_AMIGA_5_.D 1 1 1 Node SM_AMIGA_5_.C - 1 1 1 Node SM_AMIGA_4_.AR - 2 3 1 Node SM_AMIGA_4_.D - 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node SM_AMIGA_3_.AR - 4 9 1 Node SM_AMIGA_3_.D- + 5 9 1 Node SM_AMIGA_3_.T 1 1 1 Node SM_AMIGA_3_.C 1 1 1 Node SM_AMIGA_2_.AR 3 9 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR - 3 3 1 Node cpu_est_0_.D + 2 2 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 1 1 1 Node cpu_est_1_.AR - 4 6 1 Node cpu_est_1_.T + 5 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 3 6 1 NodeX1 cpu_est_2_.D.X1 - 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.AR + 4 5 1 Node cpu_est_2_.D 1 1 1 Node cpu_est_2_.C ========= - 249 P-Term Total: 249 + 308 P-Term Total: 308 Total Pins: 59 - Total Nodes: 24 - Average P-Term/Output: 2 + Total Nodes: 50 + Average P-Term/Output: 1 Equations: -RW_000 = (inst_RW_000_INT.Q); +!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); -RW_000.OE = (BGACK_030.Q); +UDS_000.OE = (BGACK_030.Q); + +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); + +LDS_000.OE = (BGACK_030.Q); BERR = (0); -BERR.OE = (!FPU_CS.Q); +BERR.OE = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); CLK_DIV_OUT.AR = (!RST); -CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_25.Q); +CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); CLK_DIV_OUT.C = (CLK_OSZI); +!FPU_CS = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + DTACK = (DSACK1.PIN); DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AVEC = (1); -AVEC_EXP = (inst_avec_expreg.Q); - -RW = (inst_RW_000_INT.Q); - -RW.OE = (!BGACK_030.Q); - -AMIGA_BUS_ENABLE = (inst_avec_expreg.Q); - AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN); -AMIGA_BUS_ENABLE_LOW = (1); - CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); @@ -1159,22 +1350,6 @@ IPL_030_2_.AP = (!RST); IPL_030_2_.C = (CLK_OSZI); -IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q - # inst_CLK_000_D1.Q & IPL_030_1_.Q - # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - -IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q - # inst_CLK_000_D1.Q & IPL_030_0_.Q - # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AS_030.D = (BGACK_030.Q @@ -1188,13 +1363,31 @@ AS_030.C = (CLK_OSZI); AS_000.OE = (BGACK_030.Q); -!AS_000.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q +!AS_000.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q # !AS_000.Q & !AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); + +!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_0_.AP = (!RST); + +SIZE_0_.C = (CLK_OSZI); + +RW_000.OE = (BGACK_030.Q); + +!RW_000.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & !RW_000.Q + # !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !RW_000.Q + # AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q & !RW.PIN); + +RW_000.AP = (!RST); + +RW_000.C = (CLK_OSZI); + DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); DS_030.D = (BGACK_030.Q @@ -1209,38 +1402,6 @@ DS_030.AP = (!RST); DS_030.C = (CLK_OSZI); -UDS_000.OE = (BGACK_030.Q); - -!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_6_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN - # !UDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !A0.PIN & RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); - -UDS_000.AP = (!RST); - -UDS_000.C = (CLK_OSZI); - -LDS_000.OE = (BGACK_030.Q); - -!LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D0.Q & !LDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN - # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_6_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & A0.PIN & RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN - # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); - -LDS_000.AP = (!RST); - -LDS_000.C = (CLK_OSZI); - A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); @@ -1265,34 +1426,48 @@ BGACK_030.C = (CLK_OSZI); CLK_EXP.AR = (!RST); -CLK_EXP.D = (inst_CLK_OUT_PRE_25.Q); +CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); -!FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN - # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); +IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q + # inst_CLK_000_D1.Q & IPL_030_1_.Q + # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); -FPU_CS.AP = (!RST); +IPL_030_1_.AP = (!RST); -FPU_CS.C = (CLK_OSZI); +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q + # inst_CLK_000_D1.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); DSACK1.OE = (nEXP_SPACE); -DSACK1.D = (!SM_AMIGA_1_.Q & DSACK1.Q - # !SM_AMIGA_1_.Q & AS_030.PIN); +!DSACK1.D = (!DSACK1.Q & !AS_030.PIN + # !AMIGA_BUS_ENABLE_LOW.Q & inst_CLK_000_D1.Q & SM_AMIGA_1_.Q); DSACK1.AP = (!RST); DSACK1.C = (CLK_OSZI); -E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); +AVEC_EXP.AR = (!RST); -E.D.X2 = (E.Q); +AVEC_EXP.D = (CLK_000_P_SYNC_9_.Q); + +AVEC_EXP.C = (CLK_OSZI); E.AR = (!RST); +!E.D = (!AVEC_EXP.Q & !E.Q + # cpu_est_2_.Q & !E.Q + # AVEC_EXP.Q & cpu_est_1_.Q & cpu_est_2_.Q + # !cpu_est_0_.Q & cpu_est_1_.Q & !E.Q); + E.C = (CLK_OSZI); VMA.D.X1 = (VMA.Q @@ -1310,32 +1485,38 @@ RESET.D = (1); RESET.C = (CLK_OSZI); -SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); +RW.OE = (!BGACK_030.Q); -!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); +!RW.D = (CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN + # CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN); -SIZE_0_.AP = (!RST); +RW.AP = (!RST); -SIZE_0_.C = (CLK_OSZI); +RW.C = (CLK_OSZI); -!inst_avec_expreg.D = (!BGACK_030.Q - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q - # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); +!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_NE.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q + # !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); -inst_avec_expreg.AP = (!RST); +AMIGA_BUS_ENABLE.AP = (!RST); -inst_avec_expreg.C = (CLK_OSZI); +AMIGA_BUS_ENABLE.C = (CLK_OSZI); -inst_AS_030_000_SYNC.D = (SM_AMIGA_1_.Q - # AS_030.PIN +AMIGA_BUS_ENABLE_LOW.AR = (!RST); + +AMIGA_BUS_ENABLE_LOW.D = (!inst_CLK_OUT_PRE.Q & inst_CLK_OUT_PRE_D.Q); + +AMIGA_BUS_ENABLE_LOW.C = (CLK_OSZI); + +inst_AS_030_000_SYNC.D = (AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q - # !CLK_030 & inst_AS_030_000_SYNC.Q # !BGACK_030.Q & inst_AS_030_000_SYNC.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q - # !nEXP_SPACE & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); @@ -1360,6 +1541,12 @@ inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI); +inst_CLK_OUT_PRE.AR = (!RST); + +inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_25.Q); + +inst_CLK_OUT_PRE.C = (CLK_OSZI); + inst_CLK_000_D0.D = (CLK_000); inst_CLK_000_D0.AP = (!RST); @@ -1372,12 +1559,6 @@ inst_CLK_000_D1.AP = (!RST); inst_CLK_000_D1.C = (CLK_OSZI); -inst_DTACK_D0.D = (DTACK.PIN); - -inst_DTACK_D0.AP = (!RST); - -inst_DTACK_D0.C = (CLK_OSZI); - inst_CLK_OUT_PRE_50.AR = (!RST); inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); @@ -1392,61 +1573,79 @@ inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_25.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); - -SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q); - -SM_AMIGA_1_.C = (CLK_OSZI); - -SM_AMIGA_6_.AR = (!RST); - -SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); - -SM_AMIGA_6_.C = (CLK_OSZI); - -SM_AMIGA_0_.AR = (!RST); - -SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_1_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); - -SM_AMIGA_0_.C = (CLK_OSZI); - -!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q - # !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D2.Q); - -SM_AMIGA_7_.AP = (!RST); - -SM_AMIGA_7_.C = (CLK_OSZI); - -!inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q - # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q - # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & AS_000.PIN - # CLK_030 & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q - # BGACK_030.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q - # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & AS_000.PIN - # !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN - # CLK_030 & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN - # BGACK_030.Q & inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & AS_000.PIN & !RW.PIN - # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN - # !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !inst_RW_000_INT.Q & UDS_000.PIN & LDS_000.PIN - # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & UDS_000.PIN & LDS_000.PIN & !RW.PIN); - -inst_RW_000_INT.AP = (!RST); - -inst_RW_000_INT.C = (CLK_OSZI); - inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.AP = (!RST); inst_CLK_000_D2.C = (CLK_OSZI); +inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); + +inst_CLK_000_D3.AP = (!RST); + +inst_CLK_000_D3.C = (CLK_OSZI); + +inst_CLK_000_NE.AR = (!RST); + +inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); + +inst_CLK_000_NE.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_D.AR = (!RST); + +inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE.Q); + +inst_CLK_OUT_PRE_D.C = (CLK_OSZI); + +CLK_000_P_SYNC_9_.AR = (!RST); + +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); + +CLK_000_P_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_11_.AR = (!RST); + +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +!SM_AMIGA_7_.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q + # !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q + # nEXP_SPACE & !AVEC_EXP.Q & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q); + +SM_AMIGA_7_.AP = (!RST); + +SM_AMIGA_7_.C = (CLK_OSZI); + +SM_AMIGA_6_.AR = (!RST); + +SM_AMIGA_6_.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & SM_AMIGA_7_.Q); + +SM_AMIGA_6_.C = (CLK_OSZI); + +SM_AMIGA_1_.AR = (!RST); + +SM_AMIGA_1_.D = (!inst_CLK_000_NE.Q & SM_AMIGA_1_.Q + # AVEC_EXP.Q & SM_AMIGA_2_.Q); + +SM_AMIGA_1_.C = (CLK_OSZI); + +SM_AMIGA_0_.AR = (!RST); + +SM_AMIGA_0_.D = (!AVEC_EXP.Q & SM_AMIGA_0_.Q + # inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q); + +SM_AMIGA_0_.C = (CLK_OSZI); + +SM_AMIGA_4_.AR = (!RST); + +SM_AMIGA_4_.D = (!AVEC_EXP.Q & SM_AMIGA_4_.Q + # inst_CLK_000_NE.Q & SM_AMIGA_5_.Q); + +SM_AMIGA_4_.C = (CLK_OSZI); + inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN @@ -1455,62 +1654,197 @@ inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q inst_CLK_030_H.C = (CLK_OSZI); +inst_LDS_000_INT.D = (inst_LDS_000_INT.Q & DS_030.PIN + # !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + +inst_LDS_000_INT.AP = (!RST); + +inst_LDS_000_INT.C = (CLK_OSZI); + +inst_DS_000_ENABLE.AR = (!RST); + +inst_DS_000_ENABLE.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q + # inst_DS_000_ENABLE.Q & !AS_030.PIN + # AVEC_EXP.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +inst_UDS_000_INT.D = (inst_UDS_000_INT.Q & DS_030.PIN + # !DS_030.PIN & A0.PIN); + +inst_UDS_000_INT.AP = (!RST); + +inst_UDS_000_INT.C = (CLK_OSZI); + +CLK_000_N_SYNC_0_.AR = (!RST); + +CLK_000_N_SYNC_0_.D = (!inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & inst_CLK_000_D3.Q); + +CLK_000_N_SYNC_0_.C = (CLK_OSZI); + +CLK_000_N_SYNC_1_.AR = (!RST); + +CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); + +CLK_000_N_SYNC_1_.C = (CLK_OSZI); + +CLK_000_N_SYNC_2_.AR = (!RST); + +CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); + +CLK_000_N_SYNC_2_.C = (CLK_OSZI); + +CLK_000_N_SYNC_3_.AR = (!RST); + +CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); + +CLK_000_N_SYNC_3_.C = (CLK_OSZI); + +CLK_000_N_SYNC_4_.AR = (!RST); + +CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); + +CLK_000_N_SYNC_4_.C = (CLK_OSZI); + +CLK_000_N_SYNC_5_.AR = (!RST); + +CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); + +CLK_000_N_SYNC_5_.C = (CLK_OSZI); + +CLK_000_N_SYNC_6_.AR = (!RST); + +CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); + +CLK_000_N_SYNC_6_.C = (CLK_OSZI); + +CLK_000_N_SYNC_7_.AR = (!RST); + +CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); + +CLK_000_N_SYNC_7_.C = (CLK_OSZI); + +CLK_000_N_SYNC_8_.AR = (!RST); + +CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); + +CLK_000_N_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_9_.AR = (!RST); + +CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); + +CLK_000_N_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_10_.AR = (!RST); + +CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); + +CLK_000_N_SYNC_10_.C = (CLK_OSZI); + +CLK_000_P_SYNC_0_.AR = (!RST); + +CLK_000_P_SYNC_0_.D = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & !inst_CLK_000_D3.Q); + +CLK_000_P_SYNC_0_.C = (CLK_OSZI); + +CLK_000_P_SYNC_1_.AR = (!RST); + +CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); + +CLK_000_P_SYNC_1_.C = (CLK_OSZI); + +CLK_000_P_SYNC_2_.AR = (!RST); + +CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); + +CLK_000_P_SYNC_2_.C = (CLK_OSZI); + +CLK_000_P_SYNC_3_.AR = (!RST); + +CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); + +CLK_000_P_SYNC_3_.C = (CLK_OSZI); + +CLK_000_P_SYNC_4_.AR = (!RST); + +CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); + +CLK_000_P_SYNC_4_.C = (CLK_OSZI); + +CLK_000_P_SYNC_5_.AR = (!RST); + +CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); + +CLK_000_P_SYNC_5_.C = (CLK_OSZI); + +CLK_000_P_SYNC_6_.AR = (!RST); + +CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); + +CLK_000_P_SYNC_6_.C = (CLK_OSZI); + +CLK_000_P_SYNC_7_.AR = (!RST); + +CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); + +CLK_000_P_SYNC_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_8_.AR = (!RST); + +CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); + +CLK_000_P_SYNC_8_.C = (CLK_OSZI); + SM_AMIGA_5_.AR = (!RST); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_5_.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q + # !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q); SM_AMIGA_5_.C = (CLK_OSZI); -SM_AMIGA_4_.AR = (!RST); - -SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); - -SM_AMIGA_4_.C = (CLK_OSZI); - SM_AMIGA_3_.AR = (!RST); -!SM_AMIGA_3_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q - # !SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q - # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !cpu_est_1_.Q & E.Q); +SM_AMIGA_3_.T = (AVEC_EXP.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # !AVEC_EXP.Q & inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN + # inst_VPA_D.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !DTACK.PIN + # !AVEC_EXP.Q & !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q + # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.AR = (!RST); -SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q - # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); +SM_AMIGA_2_.D = (!AVEC_EXP.Q & SM_AMIGA_2_.Q + # inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN + # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); SM_AMIGA_2_.C = (CLK_OSZI); cpu_est_0_.AR = (!RST); -cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q - # inst_CLK_000_D1.Q & cpu_est_0_.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q); +cpu_est_0_.D = (!AVEC_EXP.Q & cpu_est_0_.Q + # AVEC_EXP.Q & !cpu_est_0_.Q); cpu_est_0_.C = (CLK_OSZI); cpu_est_1_.AR = (!RST); -cpu_est_1_.T = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & cpu_est_2_.Q & !E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); +cpu_est_1_.D = (!AVEC_EXP.Q & cpu_est_1_.Q + # !cpu_est_0_.Q & cpu_est_1_.Q + # AVEC_EXP.Q & cpu_est_0_.Q & !cpu_est_1_.Q + # AVEC_EXP.Q & cpu_est_2_.Q & E.Q + # AVEC_EXP.Q & !cpu_est_2_.Q & !E.Q); cpu_est_1_.C = (CLK_OSZI); -cpu_est_2_.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & E.Q - # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); - -cpu_est_2_.D.X2 = (cpu_est_2_.Q); - cpu_est_2_.AR = (!RST); +cpu_est_2_.D = (!AVEC_EXP.Q & cpu_est_2_.Q + # cpu_est_1_.Q & cpu_est_2_.Q + # AVEC_EXP.Q & !cpu_est_0_.Q & !cpu_est_1_.Q + # AVEC_EXP.Q & cpu_est_0_.Q & E.Q); + cpu_est_2_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index f60aec6..dd9f34d 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -32,61 +32,92 @@ TCR, Clocked Output-to-Register Time, TSU TCO TPD TCR #passes #passes #passes #passes SIGNAL NAME min max min max min max min max - inst_DTACK_D0 1 2 .. .. .. .. 1 1 - inst_RW_000_INT 1 1 1 2 .. .. 2 2 +inst_LDS_000_INT 1 1 1 1 .. .. 2 2 +inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 +inst_UDS_000_INT 1 1 1 1 .. .. 2 2 + SM_AMIGA_3_ 1 2 .. .. .. .. 1 1 + SM_AMIGA_2_ 1 2 .. .. .. .. 1 1 + FPU_CS .. .. .. .. 1 1 .. .. DTACK .. .. .. .. 1 1 .. .. AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. SIZE_1_ 1 1 0 0 .. .. .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 - IPL_030_1_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 - IPL_030_0_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 AS_030 1 1 0 0 .. .. 1 1 RN_AS_030 1 1 0 0 .. .. 1 1 AS_000 1 1 0 0 .. .. 1 1 RN_AS_000 1 1 0 0 .. .. 1 1 + SIZE_0_ 1 1 0 0 .. .. .. .. + RW_000 1 1 0 0 .. .. 1 1 + RN_RW_000 1 1 0 0 .. .. 1 1 DS_030 1 1 0 0 .. .. 1 1 RN_DS_030 1 1 0 0 .. .. 1 1 - UDS_000 1 1 0 0 .. .. 1 1 - RN_UDS_000 1 1 0 0 .. .. 1 1 - LDS_000 1 1 0 0 .. .. 1 1 - RN_LDS_000 1 1 0 0 .. .. 1 1 A0 1 1 0 0 .. .. .. .. BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 BGACK_030 1 1 0 1 .. .. 1 1 RN_BGACK_030 1 1 0 1 .. .. 1 1 - FPU_CS 1 1 0 0 .. .. 1 1 - RN_FPU_CS 1 1 0 0 .. .. 1 1 + IPL_030_1_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 + IPL_030_0_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 DSACK1 1 1 0 0 .. .. 1 1 RN_DSACK1 1 1 0 0 .. .. 1 1 + AVEC_EXP .. .. 0 0 .. .. 1 1 + RN_AVEC_EXP .. .. 0 0 .. .. 1 1 E .. .. 0 0 .. .. 1 1 RN_E .. .. 0 0 .. .. 1 1 VMA .. .. 0 0 .. .. 1 1 RN_VMA .. .. 0 0 .. .. 1 1 - SIZE_0_ 1 1 0 0 .. .. .. .. -inst_avec_expreg 1 1 1 1 .. .. .. .. + RW 1 1 0 0 .. .. 1 1 + RN_RW 1 1 0 0 .. .. 1 1 +AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 +RN_AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 +AMIGA_BUS_ENABLE_LOW .. .. 0 0 .. .. 1 1 +RN_AMIGA_BUS_ENABLE_LOW .. .. 0 0 .. .. 1 1 inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_50_D .. .. .. .. .. .. 1 1 +inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 inst_CLK_000_D0 1 1 .. .. .. .. 1 1 inst_CLK_000_D1 .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1 - SM_AMIGA_1_ .. .. .. .. .. .. 1 1 - SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 - SM_AMIGA_0_ .. .. .. .. .. .. 1 1 - SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 inst_CLK_000_D2 .. .. .. .. .. .. 1 1 - inst_CLK_030_H 1 1 .. .. .. .. 1 1 - SM_AMIGA_5_ .. .. .. .. .. .. 1 1 + inst_CLK_000_D3 .. .. .. .. .. .. 1 1 + inst_CLK_000_NE .. .. .. .. .. .. 1 1 +inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 + SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_1_ .. .. .. .. .. .. 1 1 + SM_AMIGA_0_ .. .. .. .. .. .. 1 1 SM_AMIGA_4_ .. .. .. .. .. .. 1 1 - SM_AMIGA_3_ .. .. .. .. .. .. 1 1 - SM_AMIGA_2_ .. .. .. .. .. .. 1 1 + inst_CLK_030_H 1 1 .. .. .. .. 1 1 +CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1 + SM_AMIGA_5_ .. .. .. .. .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index a6027aa..492138c 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,370 +1,402 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE 68030_tk -#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 A_31_ IPL_2_ FC_1_ A_30_ A_29_ UDS_000 A_28_ LDS_000 A_27_ A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ A_22_ A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ CLK_DIV_OUT A_16_ FPU_CS IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_BUS_DATA_DIR CIIN SIZE_1_ IPL_030_2_ AS_030 AS_000 SIZE_0_ RW_000 DS_030 A0 BG_000 BGACK_030 CLK_EXP IPL_030_1_ IPL_030_0_ DSACK1 AVEC_EXP E VMA RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_ENABLE_LOW +#$ NODES 50 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_OUT_PRE inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_000_D2 inst_CLK_000_D3 inst_CLK_000_NE inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ CLK_000_N_SYNC_11_ SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ inst_CLK_030_H inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr -.i 79 -.o 155 -.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q BG_000.Q inst_CLK_000_D1.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q SM_AMIGA_1_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_7_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q IPL_030_0_.Q inst_CLK_000_D2.Q IPL_030_1_.Q inst_CLK_030_H.Q DS_030.Q IPL_030_2_.Q SM_AMIGA_5_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP DSACK1.C DSACK1.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D BG_000.D inst_CLK_000_D1.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D SM_AMIGA_1_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_7_.D inst_RW_000_INT.D CLK_EXP.D UDS_000.D LDS_000.D DSACK1.D IPL_030_0_.D inst_CLK_000_D2.D IPL_030_1_.D inst_CLK_030_H.D DS_030.D IPL_030_2_.D SIZE_0_.D SIZE_1_.D A0.D SM_AMIGA_5_.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_2_.D RESET.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D -.p 358 -------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ ----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1---------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0-------------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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-------1-------------------------------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------1---------------------------------------00-0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1----------------00-0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -----------------------------------------1------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----1-----------------------------0----0-0-------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ----1-----------------------------0------0------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ----1-----------------------------01-----0---0--01-----1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1-----0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0----------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------1--------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -------0-------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----------0---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ------------------------------------1--------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------0-------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----------------------------------------1-----------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----------------------------------------------0------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------------00------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---------------------------------------0----------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -------------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------1---0-------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------0---------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------1----1--------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------0-----------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------00---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-0----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------1----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -------------------------------------0-------------------------0-1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------0-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0-0------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-0-----------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ---------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------1------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ----------------------------------------------------------------010------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------0---------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0---0-0-1-----------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------------------------------------------------------------111------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------0-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ---------------------------------------0---------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------1-------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------0-------------------------0---0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------01-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ---------------------------------------1-0----------------------10-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ----------------------------------------------------------------0-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------1-00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------------100------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----10--1----------------------------------------1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---1--11---------------0010--1--------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------0------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------0--1---------1----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1-----------------------------0----------0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0------1---0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0---------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------0--1------------1-------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---01--1----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1-01----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------1------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1----------------1-----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1-----------------0----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1------------------1---1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------------01--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0----------0---0------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------0----------0---------0------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0------------0-------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1---------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------0----------0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------00-0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0----------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0---------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------0----------------------0--------------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0----------------------0-----0--------------------1-----------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------0----------------------0--------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------1----------------------0---------------------------0----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0--------------------------00----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------0----------0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------00-0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0--------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -------0----------------------0--------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0----------------------0-----0--------------------1-----------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------0----------------------0--------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------1----------------------0---------------------------0----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0--------------------------00----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------------------------------0--------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------------------------------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----------0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0---0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0------------0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0----0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ------------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1-------------------------------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-----------0----------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1------------0---------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0--------0-------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1---------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1------------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +.i 107 +.o 237 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q AVEC_EXP.Q VMA.Q AMIGA_BUS_ENABLE.Q AMIGA_BUS_ENABLE_LOW.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_OUT_PRE.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_000_D2.Q inst_CLK_000_D3.Q inst_CLK_000_NE.Q inst_CLK_OUT_PRE_D.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_11_.Q AS_000.Q SM_AMIGA_7_.Q SM_AMIGA_6_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q DSACK1.Q inst_CLK_030_H.Q RW.Q BG_000.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q DS_030.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q IPL_030_0_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q IPL_030_1_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q IPL_030_2_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN +.ob BERR FPU_CS AVEC AMIGA_BUS_DATA_DIR CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP BG_000.C BG_000.AP inst_LDS_000_INT.C inst_LDS_000_INT.AP AS_000.C AS_000.AP inst_DS_000_ENABLE.C inst_DS_000_ENABLE.AR DSACK1.C DSACK1.AP inst_UDS_000_INT.C inst_UDS_000_INT.AP RW_000.C RW_000.AP A0.C A0.AP inst_CLK_030_H.C RW.C RW.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP AMIGA_BUS_ENABLE_LOW.C AMIGA_BUS_ENABLE_LOW.AR inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP AVEC_EXP.C AVEC_EXP.AR inst_CLK_000_NE.C inst_CLK_000_NE.AR inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR UDS_000 LDS_000 DTACK AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D AVEC_EXP.D VMA.D AMIGA_BUS_ENABLE.D AMIGA_BUS_ENABLE_LOW.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D inst_CLK_000_D2.D inst_CLK_000_D3.D inst_CLK_000_NE.D inst_CLK_OUT_PRE_D.D CLK_000_P_SYNC_9_.D CLK_000_N_SYNC_11_.D AS_000.D SM_AMIGA_7_.D SM_AMIGA_6_.D SM_AMIGA_1_.D SM_AMIGA_0_.D SM_AMIGA_4_.D RW_000.D DSACK1.D inst_CLK_030_H.D RW.D BG_000.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D CLK_000_N_SYNC_0_.D CLK_EXP.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D IPL_030_0_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D IPL_030_1_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D IPL_030_2_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D RESET.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D E.D +.p 390 +----------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +--0-------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0----------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1-------------------------------------------------------------------------------------------------- ~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0------------------------------------------------------------------------------------------------ ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0----------0000000----------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1111------------------------------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1----------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0---------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1--------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------0------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-----------------------1----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0------------------------------1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1--1----------------0010--1-----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-----0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-----------------------------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------0------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1-----1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1--------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1--------------------------------------10----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +-----1----------------------------------10----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-------------10----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1------------10----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---10--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------01--11------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------10--00------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-----------------------------------------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------0-------------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----------------------------------------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------1----------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1---------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1------------------------------0------0--1------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--1------------------0------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------1----------------0------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1---------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +------------------------------0--------------------01------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1-0------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--1--------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1-----------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------0-----------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--1---------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------1------10---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------1---------------------1-00---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----1----------------1-00---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-----------1---------1-00---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------0-------------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0---1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+-----------------------------0------0-----------------------------------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0------------------------------------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0----------------------------------0-------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----------------------------0-----0-------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1----------------------------------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0------------------------------------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------0-----------------------------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0------0---------------------1-------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0-----------------------------0------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------0-----------------------------------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0------------------------------------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0----------------------------------0-------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----------------------------0-----0-------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0---1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0----1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------1-------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-------------------------------------1---------------------------------------------------1---------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-------------------------------------1----------------------------------------------------0--------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---1------------------------------------------------------------------------------------------------------1 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------------------------------------------------------------------1 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------------------------1---------1 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----------------------------------------------------------------------------0 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1--------------------01-----------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0------0-------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0---------------------------------------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 3170b16..e314d33 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,370 +1,402 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE 68030_tk -#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 A_31_ IPL_2_ FC_1_ A_30_ A_29_ UDS_000 A_28_ LDS_000 A_27_ A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ A_22_ A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ CLK_DIV_OUT A_16_ FPU_CS IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_BUS_DATA_DIR CIIN SIZE_1_ IPL_030_2_ AS_030 AS_000 SIZE_0_ RW_000 DS_030 A0 BG_000 BGACK_030 CLK_EXP IPL_030_1_ IPL_030_0_ DSACK1 AVEC_EXP E VMA RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_ENABLE_LOW +#$ NODES 50 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_OUT_PRE inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_000_D2 inst_CLK_000_D3 inst_CLK_000_NE inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ CLK_000_N_SYNC_11_ SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ inst_CLK_030_H inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr -.i 79 -.o 155 -.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q BG_000.Q inst_CLK_000_D1.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q SM_AMIGA_1_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_7_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q IPL_030_0_.Q inst_CLK_000_D2.Q IPL_030_1_.Q inst_CLK_030_H.Q DS_030.Q IPL_030_2_.Q SM_AMIGA_5_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP DSACK1.C DSACK1.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D BG_000.D inst_CLK_000_D1.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D SM_AMIGA_1_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_7_.D inst_RW_000_INT.D CLK_EXP.D UDS_000.D LDS_000.D DSACK1.D IPL_030_0_.D inst_CLK_000_D2.D IPL_030_1_.D inst_CLK_030_H.D DS_030.D IPL_030_2_.D SIZE_0_.D SIZE_1_.D A0.D SM_AMIGA_5_.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_2_.D RESET.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D -.p 358 -------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ ----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1---------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------0-------------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -0----------0000000------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------1111--------------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~ ------1-----------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0---------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0-----------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1-------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------1------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------0-----1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------1----1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------0-1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------0------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------1----------------------------------------------- ~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-----------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0--------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---1--1----------------0010--1----1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0---1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1----0-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1----------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------0-----0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------1---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------1-----1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0-----------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------0-------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ --1------------------------------------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ------1--------------------------------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------1-----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ ----------------------------1----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ -------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-----1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------01----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0----10----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1-1------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-----1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ ----------------------------------------------10-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1-1---------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1--------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ -------1-------------------------------1-------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------1-------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------1--------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------1--------------0--01------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1---1----------0--01------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1----------1---0--01------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1-1----------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------1--------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------1--------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-------1-0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1-------------------------------0----------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------0----------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ -------1---------------------------------------0--1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1----------------0--1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ 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-----------------------------------------1--------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ -----------0---------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ -------0----------------------------1--------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------------------------------0-------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ -----------------------------------------1-----------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ ---------------------------------------1--------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ ---------------------------------------0--------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ---------------------------------------0------------1-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ---------------------------------------1---------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ---------------------------------------0---------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ---------------------------------1---0------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ---------------------------------------1----------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ -----------------------------------------0--------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ -------------------------------------1----1-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ -------------------------------------1-0-10-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ ---------------------------------------1-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ ---------------------------------------0------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ -----------------------------------------1----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ---------------------------------1------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-0----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ ---------------------------------1-------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------1--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ---------------------------------------1-0----------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ ---------------------------------------0--------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -----------------------------------------1------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -----------------------------------------------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ ---------------------------------------1-0----------------------1-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ---------------------------------------1-0-----------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ---------------------------------------0---------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -----------------------------------------1-------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ---------------------------------------1-0----------------------1--1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ -----------------------------------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ---------------------------------0---0-0-1--------------------1--0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ ---------------------------------------1-0-----------------------011------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ------------------------------------------------------------------01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ---------------------------------------1-0----------------------1-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ -------------------------------------0------------------------1----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ ---------------------------------------1-0----------------------1-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ ---------------------------------------1------1-----------------0110------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-0-----------------------000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ --------------------------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0----------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------0-----1----------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------0----------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ -----------------------------------------------0--------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1-----------------1-------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------------1---1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ----------------------------------------1---------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~ ---------------------------------------1-------01--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0----------1------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0--1------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1---------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ -------1--------------------------------------------------1-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------------------------------------------------01-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ ---------------------------------------------------1-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------1------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------1--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ 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---------------------------------------1-------1---------------------1---------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ----0-------------------------0--------------------------------------0---------1 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1------------------------11-----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0--100--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ ------------------------------1------------------------------------------------0 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-----------1---------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1------------1--------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ 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---------------------------------------0--------------------1----------0--100--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------- 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------0------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------0---------------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1-------------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------0------------------------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------0----------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------0---------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------0--------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ------------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~00~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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-------------------------------------------00----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ---------------------------------0------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------0--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------1--------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ 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--------------------------------0--1---1--------00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------0--1---------0--00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1-------------------------------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ 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-----------------------------------------1------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----1-----------------------------0----0-0-------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ----1-----------------------------0------0------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ----1-----------------------------01-----0---0--01-----1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1-----0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0----------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------1--------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -------0-------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----------0---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ------------------------------------1--------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------0-------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----------------------------------------1-----------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -----------------------------------------------0------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------------00------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---------------------------------------0----------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -------------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------------1---0-------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------0---------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------1----1--------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------0-----------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------00---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-0----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ---------------------------------------0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------1----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -------------------------------------0-------------------------0-1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------0-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0-0------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-0-----------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ---------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------1------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ----------------------------------------------------------------010------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------0---------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------0---0-0-1-----------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------------------------------------------------------------111------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------0-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ---------------------------------------0---------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------1-------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------0-------------------------0---0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------01-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ---------------------------------------1-0----------------------10-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ----------------------------------------------------------------0-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------------------------------1-00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------------100------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----10--1----------------------------------------1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---1--11---------------0010--1--------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------0------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------0--1---------1----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1-----------------------------0----------0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0------1---0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------0---------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------0--1------------1-------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---01--1----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1-01----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------1------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1----------------1-----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1-----------------0----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1------------------1---1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------------01--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0----------0---0------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------0----------0---------0------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0------------0-------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1---------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------0----------0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------00-0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0----------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0---------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------0----------------------0--------------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0----------------------0-----0--------------------1-----------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------0----------------------0--------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------1----------------------0---------------------------0----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0--------------------------00----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------0----------0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------00-0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0--------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -------0----------------------0--------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0----------------------0-----0--------------------1-----------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0-----0--------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -------0----------------------0--------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -------1----------------------0---------------------------0----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0--------------------------00----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------------------------------0--------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--------------------------------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----------0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0---0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0------------0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0----0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1-----------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ------------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1-------------------------------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ------------------------------1--------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-----------0----------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1------------0---------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0--------0-------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1---------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------1-------1------------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------0--------------------1----------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +.i 107 +.o 237 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q AVEC_EXP.Q VMA.Q AMIGA_BUS_ENABLE.Q AMIGA_BUS_ENABLE_LOW.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_OUT_PRE.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q inst_CLK_000_D2.Q inst_CLK_000_D3.Q inst_CLK_000_NE.Q inst_CLK_OUT_PRE_D.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_11_.Q AS_000.Q SM_AMIGA_7_.Q SM_AMIGA_6_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q DSACK1.Q inst_CLK_030_H.Q RW.Q BG_000.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q DS_030.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q IPL_030_0_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q IPL_030_1_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q IPL_030_2_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN +.ob BERR FPU_CS AVEC AMIGA_BUS_DATA_DIR CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP BG_000.C BG_000.AP inst_LDS_000_INT.C inst_LDS_000_INT.AP AS_000.C AS_000.AP inst_DS_000_ENABLE.C inst_DS_000_ENABLE.AR DSACK1.C DSACK1.AP inst_UDS_000_INT.C inst_UDS_000_INT.AP RW_000.C RW_000.AP A0.C A0.AP inst_CLK_030_H.C RW.C RW.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP AMIGA_BUS_ENABLE_LOW.C AMIGA_BUS_ENABLE_LOW.AR inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP AVEC_EXP.C AVEC_EXP.AR inst_CLK_000_NE.C inst_CLK_000_NE.AR inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR UDS_000 LDS_000 DTACK AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D AVEC_EXP.D VMA.D AMIGA_BUS_ENABLE.D AMIGA_BUS_ENABLE_LOW.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D inst_CLK_000_D2.D inst_CLK_000_D3.D inst_CLK_000_NE.D inst_CLK_OUT_PRE_D.D CLK_000_P_SYNC_9_.D CLK_000_N_SYNC_11_.D AS_000.D SM_AMIGA_7_.D SM_AMIGA_6_.D SM_AMIGA_1_.D SM_AMIGA_0_.D SM_AMIGA_4_.D RW_000.D DSACK1.D inst_CLK_030_H.D RW.D BG_000.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D CLK_000_N_SYNC_0_.D CLK_EXP.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D IPL_030_0_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D IPL_030_1_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D IPL_030_2_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D RESET.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D E.D +.p 390 +----------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +--0-------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0----------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1-------------------------------------------------------------------------------------------------- ~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0------------------------------------------------------------------------------------------------ ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0----------0000000----------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1111------------------------------------------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1----------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0---------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1--------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------0------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-----------------------1----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0------------------------------1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1--1----------------0010--1-----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-----0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-----------------------------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------0------0---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1-----1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+-----------------------------0------------------------------------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0---1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0----1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------0----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------1-------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-------------------------------------1---------------------------------------------------1---------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-------------------------------------1----------------------------------------------------0--------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---1------------------------------------------------------------------------------------------------------1 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------------------------------------------------------------------1 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------------------------1---------1 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0----------------------------------------------------------------------------0 ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1--------------------01-----------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0------0-------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0---------------------------------------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index e08dda8..d970b72 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,202 +1,249 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE BUS68030 -#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ - IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ - SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 - BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D - inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 - inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ - SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ - SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 A_31_ IPL_2_ FC_1_ A_30_ A_29_ UDS_000 A_28_ LDS_000 A_27_ A_26_ + nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ A_22_ A_21_ BGACK_000 A_20_ CLK_030 + A_19_ CLK_000 A_18_ CLK_OSZI A_17_ CLK_DIV_OUT A_16_ FPU_CS IPL_1_ DTACK IPL_0_ + AVEC FC_0_ VPA RST AMIGA_BUS_DATA_DIR CIIN SIZE_1_ IPL_030_2_ AS_030 AS_000 + SIZE_0_ RW_000 DS_030 A0 BG_000 BGACK_030 CLK_EXP IPL_030_1_ IPL_030_0_ DSACK1 + AVEC_EXP E VMA RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_ENABLE_LOW +#$ NODES 50 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D + inst_CLK_OUT_PRE_50_D inst_CLK_OUT_PRE inst_CLK_000_D0 inst_CLK_000_D1 + inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 inst_CLK_000_D2 inst_CLK_000_D3 + inst_CLK_000_NE inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ CLK_000_N_SYNC_11_ + SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ inst_CLK_030_H + inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT CLK_000_N_SYNC_0_ + CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ + CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ + CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ + CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ + CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ SM_AMIGA_5_ SM_AMIGA_3_ + SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type f -.i 79 -.o 158 +.i 107 +.o 238 .ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ - A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q - VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q - inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q BG_000.Q inst_CLK_000_D1.Q - inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q SM_AMIGA_1_.Q - AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_7_.Q inst_RW_000_INT.Q UDS_000.Q - LDS_000.Q DSACK1.Q IPL_030_0_.Q inst_CLK_000_D2.Q IPL_030_1_.Q inst_CLK_030_H.Q - DS_030.Q IPL_030_2_.Q SM_AMIGA_5_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q - cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN - DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN - DTACK.PIN RW.PIN -.ob RW_000 RW_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR - DTACK DTACK.OE AVEC AVEC_EXP RW RW.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE SIZE_1_.D% SIZE_1_.C SIZE_1_.AP SIZE_1_.OE - IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP - IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP AS_030.D AS_030.C AS_030.AP AS_030.OE - AS_000.D% AS_000.C AS_000.AP AS_000.OE DS_030.D DS_030.C DS_030.AP DS_030.OE - UDS_000.D% UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D% LDS_000.C LDS_000.AP - LDS_000.OE A0.D A0.C A0.AP A0.OE BG_000.D% BG_000.C BG_000.AP BGACK_030.D - BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C CLK_EXP.AR FPU_CS.D% FPU_CS.C - FPU_CS.AP DSACK1.D DSACK1.C DSACK1.AP DSACK1.OE E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 - VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C RESET.AR SIZE_0_.D% SIZE_0_.C SIZE_0_.AP - SIZE_0_.OE inst_avec_expreg.D% inst_avec_expreg.C inst_avec_expreg.AP - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP - inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP - inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50_D.D - inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D + A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q AVEC_EXP.Q VMA.Q + AMIGA_BUS_ENABLE.Q AMIGA_BUS_ENABLE_LOW.Q inst_AS_030_000_SYNC.Q + inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q + inst_CLK_OUT_PRE.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE_50.Q + inst_CLK_OUT_PRE_25.Q inst_CLK_000_D2.Q inst_CLK_000_D3.Q inst_CLK_000_NE.Q + inst_CLK_OUT_PRE_D.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_11_.Q AS_000.Q + SM_AMIGA_7_.Q SM_AMIGA_6_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SM_AMIGA_4_.Q RW_000.Q + DSACK1.Q inst_CLK_030_H.Q RW.Q BG_000.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q + inst_UDS_000_INT.Q DS_030.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q + CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q IPL_030_0_.Q CLK_000_N_SYNC_4_.Q + CLK_000_N_SYNC_5_.Q IPL_030_1_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q + IPL_030_2_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q + CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q + CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q + CLK_000_P_SYNC_8_.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q + cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN + RW.PIN +.ob UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D + CLK_DIV_OUT.C CLK_DIV_OUT.AR FPU_CS% DTACK DTACK.OE AVEC AMIGA_BUS_DATA_DIR CIIN + CIIN.OE SIZE_1_.D% SIZE_1_.C SIZE_1_.AP SIZE_1_.OE IPL_030_2_.D IPL_030_2_.C + IPL_030_2_.AP AS_030.D AS_030.C AS_030.AP AS_030.OE AS_000.D% AS_000.C AS_000.AP + AS_000.OE SIZE_0_.D% SIZE_0_.C SIZE_0_.AP SIZE_0_.OE RW_000.D% RW_000.C + RW_000.AP RW_000.OE DS_030.D DS_030.C DS_030.AP DS_030.OE A0.D A0.C A0.AP A0.OE + BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D + CLK_EXP.C CLK_EXP.AR IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D + IPL_030_0_.C IPL_030_0_.AP DSACK1.D% DSACK1.C DSACK1.AP DSACK1.OE AVEC_EXP.D + AVEC_EXP.C AVEC_EXP.AR E.D% E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D + RESET.C RESET.AR RW.D% RW.C RW.AP RW.OE AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C + AMIGA_BUS_ENABLE.AP AMIGA_BUS_ENABLE_LOW.D AMIGA_BUS_ENABLE_LOW.C + AMIGA_BUS_ENABLE_LOW.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C + inst_AS_030_000_SYNC.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C + inst_BGACK_030_INT_D.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP + inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR + inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C - inst_CLK_000_D1.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP - inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR - inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SM_AMIGA_1_.D - SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR - SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR SM_AMIGA_7_.D% SM_AMIGA_7_.C - SM_AMIGA_7_.AP inst_RW_000_INT.D% inst_RW_000_INT.C inst_RW_000_INT.AP - inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_030_H.D - inst_CLK_030_H.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D - SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D% SM_AMIGA_3_.C SM_AMIGA_3_.AR - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR cpu_est_0_.D cpu_est_0_.C - cpu_est_0_.AR cpu_est_1_.T cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D.X1 - cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_2_.AR -.phase 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+------------------------------1------------------------------------------------------------1--1------------ 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 5503d92..6297a9f 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,202 +1,249 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE BUS68030 -#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ - IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR - AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ - SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 - BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D - inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 - inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ - SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ - SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 A_31_ IPL_2_ FC_1_ A_30_ A_29_ UDS_000 A_28_ LDS_000 A_27_ A_26_ + nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ A_22_ A_21_ BGACK_000 A_20_ CLK_030 + A_19_ CLK_000 A_18_ CLK_OSZI A_17_ CLK_DIV_OUT A_16_ FPU_CS IPL_1_ DTACK IPL_0_ + AVEC FC_0_ VPA RST AMIGA_BUS_DATA_DIR CIIN SIZE_1_ IPL_030_2_ AS_030 AS_000 + SIZE_0_ RW_000 DS_030 A0 BG_000 BGACK_030 CLK_EXP IPL_030_1_ IPL_030_0_ DSACK1 + AVEC_EXP E VMA RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_ENABLE_LOW +#$ NODES 50 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D + 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+--------------------------------------------------------------------------------------------11------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +------------------------------1------------------------------------------------------------1--1------------ 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 3e99f94..5cc5dc3 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 6/7/14; -TIME = 23:03:24; +DATE = 6/9/14; +TIME = 10:27:29; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -73,8 +73,8 @@ Routing = NO; [GLOBAL PROJECT OPTIMIZATION] -Balanced_Partitioning = NO; -Spread_Placement = NO; +Balanced_Partitioning = YES; +Spread_Placement = YES; Max_Pin_Percent = 100; Max_Macrocell_Percent = 100; Max_Inter_Seg_Percent = 100; @@ -134,72 +134,100 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF -AS_000 = BIDIR,33,3,-; -LDS_000 = BIDIR,31,3,-; -UDS_000 = BIDIR,32,3,-; AS_030 = BIDIR,82,7,-; -RW = OUTPUT,71,6,-; -RW_000 = OUTPUT,80,7,-; +AS_000 = BIDIR,33,3,-; +RW = BIDIR,71,6,-; +UDS_000 = OUTPUT,32,3,-; +LDS_000 = OUTPUT,31,3,-; +RW_000 = BIDIR,80,7,-; DS_030 = BIDIR,98,0,-; DSACK1 = BIDIR,81,7,-; SIZE_1_ = OUTPUT,79,7,-; SIZE_0_ = OUTPUT,70,6,-; A0 = OUTPUT,69,6,-; DTACK = OUTPUT,30,3,-; +AMIGA_BUS_ENABLE = OUTPUT,34,3,-; E = OUTPUT,66,6,-; IPL_030_2_ = OUTPUT,9,1,-; IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; BGACK_030 = OUTPUT,83,7,-; -FPU_CS = OUTPUT,78,7,-; AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; VMA = OUTPUT,35,3,-; BG_000 = OUTPUT,29,3,-; AVEC = OUTPUT,92,0,-; +FPU_CS = OUTPUT,78,7,-; CLK_DIV_OUT = OUTPUT,65,6,-; CIIN = OUTPUT,47,4,-; BERR = OUTPUT,41,4,-; -AMIGA_BUS_ENABLE = OUTPUT,34,3,-; AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; RN_BGACK_030 = NODE,-1,7,-; +RN_AVEC_EXP = NODE,-1,2,-; +inst_CLK_000_D1 = NODE,*,7,-; RN_AS_030 = NODE,-1,7,-; -inst_CLK_000_D1 = NODE,*,3,-; -inst_CLK_000_D0 = NODE,*,7,-; -inst_avec_expreg = NODE,*,6,-; -cpu_est_1_ = NODE,*,3,-; -SM_AMIGA_7_ = NODE,*,7,-; -RN_E = NODE,-1,6,-; -SM_AMIGA_1_ = NODE,*,1,-; -inst_RW_000_INT = NODE,*,6,-; -inst_AS_030_000_SYNC = NODE,*,7,-; -inst_CLK_030_H = NODE,*,1,-; -cpu_est_2_ = NODE,*,3,-; -cpu_est_0_ = NODE,*,3,-; -SM_AMIGA_2_ = NODE,*,0,-; -inst_CLK_OUT_PRE_25 = NODE,*,1,-; -RN_VMA = NODE,-1,3,-; -RN_FPU_CS = NODE,-1,7,-; -SM_AMIGA_5_ = NODE,*,3,-; -SM_AMIGA_0_ = NODE,*,7,-; SM_AMIGA_6_ = NODE,*,6,-; -inst_CLK_000_D2 = NODE,*,7,-; -inst_CLK_OUT_PRE_50 = NODE,*,7,-; -inst_VPA_D = NODE,*,0,-; -RN_LDS_000 = NODE,-1,3,-; -RN_UDS_000 = NODE,-1,3,-; +inst_CLK_000_D2 = NODE,*,3,-; +inst_CLK_000_D0 = NODE,*,5,-; +cpu_est_1_ = NODE,*,6,-; +inst_AS_030_000_SYNC = NODE,*,7,-; +RN_E = NODE,-1,6,-; +SM_AMIGA_7_ = NODE,*,3,-; +cpu_est_0_ = NODE,*,5,-; +SM_AMIGA_1_ = NODE,*,5,-; +inst_CLK_OUT_PRE_D = NODE,*,2,-; +inst_CLK_000_NE = NODE,*,0,-; +inst_CLK_OUT_PRE_50 = NODE,*,4,-; +cpu_est_2_ = NODE,*,6,-; +inst_DS_000_ENABLE = NODE,*,1,-; +inst_CLK_OUT_PRE_25 = NODE,*,2,-; +RN_VMA = NODE,-1,3,-; +inst_UDS_000_INT = NODE,*,2,-; +inst_LDS_000_INT = NODE,*,2,-; +SM_AMIGA_4_ = NODE,*,1,-; +inst_VPA_D = NODE,*,6,-; RN_DS_030 = NODE,-1,0,-; -SM_AMIGA_3_ = NODE,*,0,-; +RN_AMIGA_BUS_ENABLE = NODE,-1,3,-; +SM_AMIGA_3_ = NODE,*,5,-; +inst_CLK_030_H = NODE,*,0,-; +RN_RW = NODE,-1,6,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; +RN_RW_000 = NODE,-1,7,-; RN_IPL_030_2_ = NODE,-1,1,-; +SM_AMIGA_2_ = NODE,*,5,-; RN_DSACK1 = NODE,-1,7,-; RN_BG_000 = NODE,-1,3,-; RN_AS_000 = NODE,-1,3,-; -SM_AMIGA_4_ = NODE,*,0,-; -inst_DTACK_D0 = NODE,*,1,-; +SM_AMIGA_5_ = NODE,*,1,-; +SM_AMIGA_0_ = NODE,*,3,-; +RN_AMIGA_BUS_ENABLE_LOW = NODE,-1,2,-; +CLK_000_P_SYNC_8_ = NODE,*,5,-; +CLK_000_P_SYNC_7_ = NODE,*,0,-; +CLK_000_P_SYNC_6_ = NODE,*,2,-; +CLK_000_P_SYNC_5_ = NODE,*,2,-; +CLK_000_P_SYNC_4_ = NODE,*,6,-; +CLK_000_P_SYNC_3_ = NODE,*,0,-; +CLK_000_P_SYNC_2_ = NODE,*,2,-; +CLK_000_P_SYNC_1_ = NODE,*,1,-; +CLK_000_P_SYNC_0_ = NODE,*,5,-; +CLK_000_N_SYNC_10_ = NODE,*,0,-; +CLK_000_N_SYNC_9_ = NODE,*,5,-; +CLK_000_N_SYNC_8_ = NODE,*,2,-; +CLK_000_N_SYNC_7_ = NODE,*,4,-; +CLK_000_N_SYNC_6_ = NODE,*,5,-; +CLK_000_N_SYNC_5_ = NODE,*,0,-; +CLK_000_N_SYNC_4_ = NODE,*,0,-; +CLK_000_N_SYNC_3_ = NODE,*,2,-; +CLK_000_N_SYNC_2_ = NODE,*,4,-; +CLK_000_N_SYNC_1_ = NODE,*,0,-; +CLK_000_N_SYNC_0_ = NODE,*,5,-; +CLK_000_N_SYNC_11_ = NODE,*,0,-; +CLK_000_P_SYNC_9_ = NODE,*,1,-; +inst_CLK_000_D3 = NODE,*,4,-; +inst_CLK_OUT_PRE = NODE,*,1,-; inst_CLK_OUT_PRE_50_D = NODE,*,7,-; -inst_BGACK_030_INT_D = NODE,*,1,-; +inst_BGACK_030_INT_D = NODE,*,7,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index f793977..6e05f31 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 6/7/14; -TIME = 23:03:24; +DATE = 6/9/14; +TIME = 10:27:29; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -73,8 +73,8 @@ Routing = NO; [GLOBAL PROJECT OPTIMIZATION] -Balanced_Partitioning = NO; -Spread_Placement = NO; +Balanced_Partitioning = YES; +Spread_Placement = YES; Max_Pin_Percent = 100; Max_Macrocell_Percent = 100; Max_Inter_Seg_Percent = 100; @@ -134,86 +134,112 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; -A_22_ = INPUT,85, H,-; -A_21_ = INPUT,94, A,-; -A_20_ = INPUT,93, A,-; -A_19_ = INPUT,97, A,-; A_31_ = INPUT,4, B,-; -A_18_ = INPUT,95, A,-; -A_17_ = INPUT,59, F,-; -A_16_ = INPUT,96, A,-; IPL_2_ = INPUT,68, G,-; -IPL_1_ = INPUT,56, F,-; FC_1_ = INPUT,58, F,-; -IPL_0_ = INPUT,67, G,-; -FC_0_ = INPUT,57, F,-; -RW_000 = BIDIR,80, H,-; -nEXP_SPACE = INPUT,14,-,-; -BERR = OUTPUT,41, E,-; -BG_030 = INPUT,21, C,-; -BGACK_000 = INPUT,28, D,-; -CLK_030 = INPUT,64,-,-; -CLK_000 = INPUT,11,-,-; -CLK_OSZI = INPUT,61,-,-; -CLK_DIV_OUT = OUTPUT,65, G,-; -DTACK = BIDIR,30, D,-; -AVEC = OUTPUT,92, A,-; -AVEC_EXP = OUTPUT,22, C,-; -VPA = INPUT,36,-,-; -RST = INPUT,86,-,-; -RW = BIDIR,71, G,-; -AMIGA_BUS_ENABLE = OUTPUT,34, D,-; -AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; -AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; -CIIN = OUTPUT,47, E,-; A_30_ = INPUT,5, B,-; A_29_ = INPUT,6, B,-; +UDS_000 = BIDIR,32, D,-; A_28_ = INPUT,15, C,-; +LDS_000 = BIDIR,31, D,-; A_27_ = INPUT,16, C,-; A_26_ = INPUT,17, C,-; +nEXP_SPACE = INPUT,14,-,-; A_25_ = INPUT,18, C,-; +BERR = OUTPUT,41, E,-; A_24_ = INPUT,19, C,-; +BG_030 = INPUT,21, C,-; A_23_ = INPUT,84, H,-; +A_22_ = INPUT,85, H,-; +A_21_ = INPUT,94, A,-; +BGACK_000 = INPUT,28, D,-; +A_20_ = INPUT,93, A,-; +CLK_030 = INPUT,64,-,-; +A_19_ = INPUT,97, A,-; +CLK_000 = INPUT,11,-,-; +A_18_ = INPUT,95, A,-; +CLK_OSZI = INPUT,61,-,-; +A_17_ = INPUT,59, F,-; +CLK_DIV_OUT = OUTPUT,65, G,-; +A_16_ = INPUT,96, A,-; +FPU_CS = OUTPUT,78, H,-; +IPL_1_ = INPUT,56, F,-; +DTACK = BIDIR,30, D,-; +IPL_0_ = INPUT,67, G,-; +AVEC = OUTPUT,92, A,-; +FC_0_ = INPUT,57, F,-; +VPA = INPUT,36,-,-; +RST = INPUT,86,-,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +CIIN = OUTPUT,47, E,-; SIZE_1_ = BIDIR,79, H,-; IPL_030_2_ = OUTPUT,9, B,-; -IPL_030_1_ = OUTPUT,7, B,-; -IPL_030_0_ = OUTPUT,8, B,-; AS_030 = BIDIR,82, H,-; AS_000 = BIDIR,33, D,-; +SIZE_0_ = BIDIR,70, G,-; +RW_000 = BIDIR,80, H,-; DS_030 = BIDIR,98, A,-; -UDS_000 = BIDIR,32, D,-; -LDS_000 = BIDIR,31, D,-; A0 = BIDIR,69, G,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; CLK_EXP = OUTPUT,10, B,-; -FPU_CS = OUTPUT,78, H,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; DSACK1 = BIDIR,81, H,-; +AVEC_EXP = OUTPUT,22, C,-; E = OUTPUT,66, G,-; VMA = OUTPUT,35, D,-; RESET = OUTPUT,3, B,-; -SIZE_0_ = BIDIR,70, G,-; -inst_avec_expreg = NODE,4, G,-; -inst_AS_030_000_SYNC = NODE,7, H,-; -inst_BGACK_030_INT_D = NODE,9, B,-; -inst_VPA_D = NODE,3, A,-; -inst_CLK_OUT_PRE_50_D = NODE,12, H,-; -inst_CLK_000_D0 = NODE,3, H,-; -inst_CLK_000_D1 = NODE,5, D,-; -inst_DTACK_D0 = NODE,8, B,-; -inst_CLK_OUT_PRE_50 = NODE,11, H,-; -inst_CLK_OUT_PRE_25 = NODE,7, B,-; -SM_AMIGA_1_ = NODE,3, B,-; -SM_AMIGA_6_ = NODE,6, G,-; -SM_AMIGA_0_ = NODE,9, H,-; -SM_AMIGA_7_ = NODE,5, H,-; -inst_RW_000_INT = NODE,5, G,-; -inst_CLK_000_D2 = NODE,10, H,-; -inst_CLK_030_H = NODE,5, B,-; -SM_AMIGA_5_ = NODE,11, D,-; -SM_AMIGA_4_ = NODE,5, A,-; -SM_AMIGA_3_ = NODE,4, A,-; -SM_AMIGA_2_ = NODE,1, A,-; -cpu_est_0_ = NODE,10, D,-; -cpu_est_1_ = NODE,7, D,-; -cpu_est_2_ = NODE,9, D,-; +RW = BIDIR,71, G,-; +AMIGA_BUS_ENABLE = OUTPUT,34, D,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; +inst_AS_030_000_SYNC = NODE,4, H,-; +inst_BGACK_030_INT_D = NODE,10, H,-; +inst_VPA_D = NODE,2, G,-; +inst_CLK_OUT_PRE_50_D = NODE,13, H,-; +inst_CLK_OUT_PRE = NODE,10, B,-; +inst_CLK_000_D0 = NODE,0, F,-; +inst_CLK_000_D1 = NODE,9, H,-; +inst_CLK_OUT_PRE_50 = NODE,8, E,-; +inst_CLK_OUT_PRE_25 = NODE,1, C,-; +inst_CLK_000_D2 = NODE,9, D,-; +inst_CLK_000_D3 = NODE,9, E,-; +inst_CLK_000_NE = NODE,8, A,-; +inst_CLK_OUT_PRE_D = NODE,8, C,-; +CLK_000_P_SYNC_9_ = NODE,6, B,-; +CLK_000_N_SYNC_11_ = NODE,10, A,-; +SM_AMIGA_7_ = NODE,2, D,-; +SM_AMIGA_6_ = NODE,5, G,-; +SM_AMIGA_1_ = NODE,8, F,-; +SM_AMIGA_0_ = NODE,6, D,-; +SM_AMIGA_4_ = NODE,9, B,-; +inst_CLK_030_H = NODE,12, A,-; +inst_LDS_000_INT = NODE,9, C,-; +inst_DS_000_ENABLE = NODE,5, B,-; +inst_UDS_000_INT = NODE,5, C,-; +CLK_000_N_SYNC_0_ = NODE,6, F,-; +CLK_000_N_SYNC_1_ = NODE,6, A,-; +CLK_000_N_SYNC_2_ = NODE,5, E,-; +CLK_000_N_SYNC_3_ = NODE,14, C,-; +CLK_000_N_SYNC_4_ = NODE,2, A,-; +CLK_000_N_SYNC_5_ = NODE,13, A,-; +CLK_000_N_SYNC_6_ = NODE,2, F,-; +CLK_000_N_SYNC_7_ = NODE,1, E,-; +CLK_000_N_SYNC_8_ = NODE,10, C,-; +CLK_000_N_SYNC_9_ = NODE,13, F,-; +CLK_000_N_SYNC_10_ = NODE,9, A,-; +CLK_000_P_SYNC_0_ = NODE,9, F,-; +CLK_000_P_SYNC_1_ = NODE,2, B,-; +CLK_000_P_SYNC_2_ = NODE,6, C,-; +CLK_000_P_SYNC_3_ = NODE,5, A,-; +CLK_000_P_SYNC_4_ = NODE,6, G,-; +CLK_000_P_SYNC_5_ = NODE,2, C,-; +CLK_000_P_SYNC_6_ = NODE,13, C,-; +CLK_000_P_SYNC_7_ = NODE,1, A,-; +CLK_000_P_SYNC_8_ = NODE,5, F,-; +SM_AMIGA_5_ = NODE,13, B,-; +SM_AMIGA_3_ = NODE,12, F,-; +SM_AMIGA_2_ = NODE,1, F,-; +cpu_est_0_ = NODE,4, F,-; +cpu_est_1_ = NODE,9, G,-; +cpu_est_2_ = NODE,13, G,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct index 5cb097f..110ae2a 100644 --- a/Logic/68030_tk.vct +++ b/Logic/68030_tk.vct @@ -15,8 +15,8 @@ Voltage = 5.0; RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; -DATE = 06/01/2014; -TIME = 00:00:40; +DATE = 06/08/2014; +TIME = 11:30:13; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -53,8 +53,8 @@ Pin_Macrocell_Block = No; Routing = No; [GLOBAL PROJECT OPTIMIZATION] -Balanced_Partitioning = No; -Spread_Placement = No; +Balanced_Partitioning = Yes; +Spread_Placement = Yes; Max_Pin_Percent = 100; Max_Macrocell_Percent = 100; Max_Blk_In_Percent = 100; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index a267e73..c4e34de 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Sat Jun 07 23:03:19 2014 +Design '68030_tk' created Mon Jun 09 10:27:24 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 4a32b0f..fe3cef7 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,148 +1,158 @@ -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ -#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \ -# nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \ -# inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ \ -# CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n \ -# inst_CLK_000_D2 IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ \ -# ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n \ -# CLK_OUT_PRE_25_0 fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n cpu_est_3_reg \ -# N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n N_160_i \ -# N_92 N_154_i state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n \ -# AS_000_DMA_1_sqmuxa state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ -# state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 state_machine_un51_clk_000_d0_i_n \ -# N_90 state_machine_un53_clk_000_d0_0_n N_164_1 state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \ -# state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i \ -# N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n \ -# N_89_i state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d \ -# BG_030_c_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 \ -# state_machine_un10_bgack_030_int_0_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n AMIGA_BUS_ENABLE_INT_2_sqmuxa \ -# state_machine_size_dma_4_0_0__n N_89 state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \ -# state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i un1_as_030_000_sync8_1 RW_li_m_i \ -# AS_000_INT_1_sqmuxa state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n state_machine_un53_clk_000_d0_n \ -# N_94_i state_machine_un57_clk_000_d0_n N_93_i AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ -# CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ -# cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \ -# N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \ -# cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \ -# cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 \ -# state_machine_un28_clk_030_i_n N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n state_machine_un57_clk_000_d0_1_n \ -# DTACK_D0_i state_machine_un49_clk_000_d0_1_n a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n state_machine_un28_clk_030_2_n \ -# nEXP_SPACE_i state_machine_un28_clk_030_3_n sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n \ -# BGACK_030_INT_i state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i cpu_est_ns_0_2_1__n \ -# AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n \ -# RW_000_i cpu_estse_1_un1_n UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ -# state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n \ -# a_i_30__n ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n \ -# a_i_27__n bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i \ -# fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \ -# dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \ -# avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -# a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ -# rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \ -# clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n a_c_26__n a_c_27__n +#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 SIZE_0_ RW_000 A_30_ DS_030 A_29_ UDS_000 A_28_ LDS_000 A_27_ A0 A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ BG_000 A_22_ BGACK_030 A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ CLK_DIV_OUT A_16_ CLK_EXP IPL_030_1_ FPU_CS IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN +#$ NODES 425 amiga_bus_enable_int_0_un3_n a_c_16__n amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_17__n bg_000_0_un3_n bg_000_0_un1_n a_c_18__n bg_000_0_un0_n inst_BGACK_030_INTreg \ +# lds_000_int_0_un3_n vcc_n_n a_c_19__n lds_000_int_0_un1_n inst_avec_expreg lds_000_int_0_un0_n inst_VMA_INTreg a_c_20__n ds_000_enable_0_un3_n inst_AMIGA_BUS_ENABLE_INTreg \ +# ds_000_enable_0_un1_n inst_CLK_OUT_NEreg a_c_21__n ds_000_enable_0_un0_n inst_AS_030_000_SYNC uds_000_int_0_un3_n inst_BGACK_030_INT_D a_c_22__n uds_000_int_0_un1_n inst_AS_000_DMA \ +# uds_000_int_0_un0_n inst_VPA_D a_c_23__n inst_CLK_OUT_PRE_50_D inst_CLK_OUT_PRE a_c_24__n inst_CLK_000_D0 inst_CLK_000_D1 a_c_25__n inst_CLK_OUT_PRE_50 \ +# inst_CLK_OUT_PRE_25 a_c_26__n inst_CLK_000_D2 inst_CLK_000_D3 a_c_27__n inst_CLK_000_NE gnd_n_n a_c_28__n inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ \ +# a_c_29__n CLK_000_N_SYNC_11_ inst_AS_000_INT a_c_30__n SM_AMIGA_7_ SM_AMIGA_6_ a_c_31__n SM_AMIGA_1_ SM_AMIGA_0_ A0_c \ +# SM_AMIGA_4_ inst_RW_000_INT nEXP_SPACE_c inst_DSACK1_INT state_machine_un3_clk_out_pre_50_n BG_030_c inst_CLK_030_H inst_RW_000_DMA BG_000DFFSHreg un1_LDS_000_INT \ +# inst_LDS_000_INT inst_DS_000_ENABLE BGACK_000_c un1_UDS_000_INT inst_UDS_000_INT CLK_030_c CLK_000_c inst_DS_000_DMA SIZE_DMA_0_ CLK_OSZI_c \ +# SIZE_DMA_1_ inst_A0_DMA CLK_000_N_SYNC_0_ CLK_OUT_INTreg CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ IPL_030DFFSH_0_reg CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ \ +# IPL_030DFFSH_1_reg CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ IPL_030DFFSH_2_reg CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ ipl_c_0__n CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ ipl_c_1__n \ +# CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ ipl_c_2__n CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ DSACK1_c CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ DTACK_c CLK_000_P_SYNC_7_ \ +# CLK_000_P_SYNC_8_ un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n SM_AMIGA_5_ SM_AMIGA_3_ RST_c SM_AMIGA_2_ RESETDFFRHreg \ +# RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i DS_000_ENABLE_0_sqmuxa_i un1_SM_AMIGA_0_sqmuxa_1_i state_machine_un10_clk_000_ne_i_n state_machine_un4_clk_000_ne_i_n CLK_OUT_PRE_25_0 \ +# state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n state_machine_un6_bgack_000_0_n N_167_i \ +# cpu_est_0_ N_166_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_162_i cpu_est_3_reg N_161_i cpu_estse N_152_i \ +# state_machine_un10_clk_000_d0_i_n state_machine_un5_clk_000_d0_i_n state_machine_un12_clk_000_d0_0_n N_198 cpu_est_ns_0_1__n N_207 N_156_i SM_AMIGA_0_sqmuxa N_155_i N_89 \ +# N_163_i N_90 state_machine_un5_clk_000_d0_1_i_n state_machine_un8_bg_030_n state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 N_160_i N_87 \ +# cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 state_machine_size_dma_4_0_1__n N_101 \ +# CLK_030_H_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_030_H_1_sqmuxa_i N_85 state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa un3_dtack_i AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n un1_bgack_030_int_d \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 AMIGA_BUS_ENABLE_INT_2_sqmuxa \ +# N_91_i N_93 N_93_i N_66 state_machine_rw_000_int_3_n AS_030_000_SYNC_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ +# AS_030_000_SYNC_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \ +# CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa N_92_i DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \ +# sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 \ +# sm_amiga_ns_0_2__n N_159 sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 state_machine_un10_bg_030_0_n N_155 \ +# LDS_000_INT_i N_156 un1_LDS_000_INT_0 cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n un1_UDS_000_INT_0 state_machine_un6_clk_000_p_sync_n state_machine_un7_ds_030_i_n state_machine_un10_clk_000_d0_n \ +# A0_c_i state_machine_un5_clk_000_d0_n size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 state_machine_un10_clk_000_ne_1_n N_84_0_1 N_162 N_84_0_2 state_machine_un5_clk_000_d0_2_n \ +# un3_dtack_i_1 N_166 cpu_est_ns_0_1_2__n N_167 N_198_1 DSACK1_INT_1_sqmuxa N_198_2 state_machine_un6_bgack_000_n N_207_1 DS_000_ENABLE_0_sqmuxa \ +# N_207_2 state_machine_un10_clk_000_ne_n N_207_3 N_86 N_207_4 state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \ +# state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \ +# AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 VPA_D_i cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i state_machine_un10_clk_000_d0_1_n a_i_19__n \ +# state_machine_un10_clk_000_d0_2_0_n DSACK1_INT_0_sqmuxa_i state_machine_un10_clk_000_d0_3_n a_i_16__n state_machine_clk_000_n_sync_2_1_0__n a_i_18__n state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i state_machine_clk_000_p_sync_3_1_0__n RW_i \ +# N_167_1_0 CLK_000_D3_i un19_fpu_cs_1 CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 cpu_est_i_3__n un19_fpu_cs_4 cpu_est_i_0__n \ +# un19_fpu_cs_5 cpu_est_i_1__n un19_fpu_cs_6 state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 CLK_000_D1_i state_machine_un10_clk_000_ne_1_0_n state_machine_un5_clk_000_d0_2_i_0_n dsack1_int_0_un3_n cpu_est_i_2__n \ +# dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i dsack1_int_0_un0_n state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n CLK_030_i bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \ +# cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n RW_000_i cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n vma_int_0_un3_n AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i \ +# vma_int_0_un0_n AS_000_i ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i ipl_030_0_0__un0_n N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i \ +# ipl_030_0_1__un1_n sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i ipl_030_0_2__un3_n sm_amiga_i_0__n ipl_030_0_2__un1_n sm_amiga_i_1__n ipl_030_0_2__un0_n a_i_30__n \ +# cpu_estse_2_un3_n a_i_31__n cpu_estse_2_un1_n a_i_28__n cpu_estse_2_un0_n a_i_29__n as_000_dma_0_un3_n a_i_26__n as_000_dma_0_un1_n a_i_27__n \ +# as_000_dma_0_un0_n a_i_24__n ds_000_dma_0_un3_n a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n rw_000_dma_0_un3_n CLK_OUT_PRE_i rw_000_dma_0_un1_n \ +# CLK_OUT_PRE_50_D_i rw_000_dma_0_un0_n AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c clk_030_h_0_un0_n cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n \ +# cpu_estse_1_un0_n DS_030_c rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n \ +# size_c_0__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n as_030_000_sync_0_un0_n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF \ - IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF \ - A0_c.BLIF inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ - inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF \ - vcc_n_n.BLIF gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \ - CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF \ - inst_DS_000_DMA.BLIF IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \ - SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \ - fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF cpu_est_3_reg.BLIF \ - N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ - N_160_i.BLIF N_92.BLIF N_154_i.BLIF state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF \ - CLK_030_H_1_sqmuxa.BLIF cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \ - un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF state_machine_un3_clk_030_i_n.BLIF \ - N_94.BLIF state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF state_machine_un10_bgack_030_int_n.BLIF \ - un1_bgack_030_int_d_0.BLIF UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \ - RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF \ - N_100.BLIF N_95_i.BLIF N_91.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF state_machine_uds_000_int_7_n.BLIF \ - sm_amiga_ns_0_0__n.BLIF RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF BG_030_c_i.BLIF \ - un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF N_59_0.BLIF N_86.BLIF \ - state_machine_un10_bgack_030_int_0_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \ - AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF N_97.BLIF N_100_i.BLIF \ - N_99.BLIF un1_SM_AMIGA_8_0.BLIF state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ - RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \ - state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \ - AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF un1_as_030_000_sync8.BLIF \ - state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF N_157.BLIF \ - state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF \ - N_152.BLIF N_220_2.BLIF N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF cpu_est_ns_1__n.BLIF \ - N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF \ - cpu_est_i_2__n.BLIF UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \ - AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF state_machine_un8_bg_030_2_n.BLIF \ - sm_amiga_i_1__n.BLIF state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \ - state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF state_machine_un28_clk_030_5_n.BLIF \ - N_99_i.BLIF state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \ - state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF state_machine_un28_clk_000_d1_1_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \ - state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ - cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF \ - CLK_030_i.BLIF ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \ - ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF bgack_030_int_0_un3_n.BLIF \ - a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ - FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF as_000_int_0_un1_n.BLIF \ - as_000_int_0_un0_n.BLIF RW_000_c.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF vma_int_0_un1_n.BLIF \ - vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF \ - bg_000_0_un0_n.BLIF a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF \ - uds_000_int_0_un0_n.BLIF a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF as_000_dma_0_un1_n.BLIF \ - as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF clk_030_h_0_un1_n.BLIF \ - clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN \ + IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF amiga_bus_enable_int_0_un3_n.BLIF a_c_16__n.BLIF amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF a_c_17__n.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \ + a_c_18__n.BLIF bg_000_0_un0_n.BLIF inst_BGACK_030_INTreg.BLIF lds_000_int_0_un3_n.BLIF vcc_n_n.BLIF a_c_19__n.BLIF lds_000_int_0_un1_n.BLIF inst_avec_expreg.BLIF lds_000_int_0_un0_n.BLIF \ + inst_VMA_INTreg.BLIF a_c_20__n.BLIF ds_000_enable_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF ds_000_enable_0_un1_n.BLIF inst_CLK_OUT_NEreg.BLIF a_c_21__n.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ + uds_000_int_0_un3_n.BLIF inst_BGACK_030_INT_D.BLIF a_c_22__n.BLIF uds_000_int_0_un1_n.BLIF inst_AS_000_DMA.BLIF uds_000_int_0_un0_n.BLIF inst_VPA_D.BLIF a_c_23__n.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ + inst_CLK_OUT_PRE.BLIF a_c_24__n.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF a_c_25__n.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF a_c_26__n.BLIF inst_CLK_000_D2.BLIF \ + inst_CLK_000_D3.BLIF a_c_27__n.BLIF inst_CLK_000_NE.BLIF gnd_n_n.BLIF a_c_28__n.BLIF inst_CLK_OUT_PRE_D.BLIF CLK_000_P_SYNC_9_.BLIF a_c_29__n.BLIF CLK_000_N_SYNC_11_.BLIF \ + inst_AS_000_INT.BLIF a_c_30__n.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF a_c_31__n.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF A0_c.BLIF SM_AMIGA_4_.BLIF \ + inst_RW_000_INT.BLIF nEXP_SPACE_c.BLIF inst_DSACK1_INT.BLIF state_machine_un3_clk_out_pre_50_n.BLIF BG_030_c.BLIF inst_CLK_030_H.BLIF inst_RW_000_DMA.BLIF BG_000DFFSHreg.BLIF un1_LDS_000_INT.BLIF \ + inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF BGACK_000_c.BLIF un1_UDS_000_INT.BLIF inst_UDS_000_INT.BLIF CLK_030_c.BLIF CLK_000_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF \ + CLK_OSZI_c.BLIF SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF CLK_000_N_SYNC_0_.BLIF CLK_OUT_INTreg.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF IPL_030DFFSH_0_reg.BLIF \ + CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF IPL_030DFFSH_1_reg.BLIF CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF IPL_030DFFSH_2_reg.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF ipl_c_0__n.BLIF \ + CLK_000_N_SYNC_10_.BLIF CLK_000_P_SYNC_0_.BLIF ipl_c_1__n.BLIF CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF ipl_c_2__n.BLIF CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF DSACK1_c.BLIF \ + CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF DTACK_c.BLIF CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF un1_as_030.BLIF un19_fpu_cs.BLIF state_machine_un10_bg_030_n.BLIF \ + SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF RST_c.BLIF SM_AMIGA_2_.BLIF RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ + SM_AMIGA_0_sqmuxa_i.BLIF DS_000_ENABLE_0_sqmuxa_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un4_clk_000_ne_i_n.BLIF CLK_OUT_PRE_25_0.BLIF state_machine_un6_clk_000_ne_i_n.BLIF N_97_i.BLIF sm_amiga_ns_0_4__n.BLIF \ + N_99_i.BLIF N_98_i.BLIF sm_amiga_ns_0_5__n.BLIF N_86_i.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF state_machine_un6_bgack_000_0_n.BLIF N_167_i.BLIF cpu_est_0_.BLIF N_166_i.BLIF \ + cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_162_i.BLIF cpu_est_3_reg.BLIF N_161_i.BLIF cpu_estse.BLIF N_152_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF \ + state_machine_un5_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n.BLIF N_198.BLIF cpu_est_ns_0_1__n.BLIF N_207.BLIF N_156_i.BLIF SM_AMIGA_0_sqmuxa.BLIF N_155_i.BLIF N_89.BLIF \ + N_163_i.BLIF N_90.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF state_machine_un8_bg_030_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF N_91.BLIF N_159_i.BLIF N_92.BLIF N_160_i.BLIF \ + N_87.BLIF cpu_est_ns_0_2__n.BLIF N_94.BLIF state_machine_un10_bgack_030_int_0_n.BLIF N_95.BLIF state_machine_ds_000_dma_3_0_n.BLIF N_96.BLIF state_machine_size_dma_4_0_0__n.BLIF N_100.BLIF \ + state_machine_size_dma_4_0_1__n.BLIF N_101.BLIF CLK_030_H_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_030_H_1_sqmuxa_i.BLIF N_85.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF DSACK1_INT_0_sqmuxa.BLIF un3_dtack_i.BLIF \ + AS_030_000_SYNC_0_sqmuxa.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF un1_bgack_030_int_d.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF state_machine_un3_bgack_030_int_d_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF \ + state_machine_rw_000_int_3_0_n.BLIF N_84.BLIF N_66_0.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_91_i.BLIF N_93.BLIF N_93_i.BLIF N_66.BLIF state_machine_rw_000_int_3_n.BLIF \ + AS_030_000_SYNC_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_84_0.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF \ + state_machine_un8_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF N_167_1.BLIF N_87_0.BLIF state_machine_un10_bgack_030_int_n.BLIF N_85_0.BLIF CLK_030_H_1_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF AS_000_DMA_1_sqmuxa.BLIF \ + N_92_i.BLIF DS_000_DMA_1_sqmuxa.BLIF DS_000_DMA_1_sqmuxa_1.BLIF N_100_i.BLIF state_machine_un24_bgack_030_int_n.BLIF N_101_i.BLIF state_machine_clk_030_h_2_n.BLIF sm_amiga_ns_0_6__n.BLIF state_machine_clk_030_h_2_f1_n.BLIF \ + N_95_i.BLIF state_machine_un31_bgack_030_int_n.BLIF N_96_i.BLIF state_machine_ds_000_dma_3_n.BLIF sm_amiga_ns_0_3__n.BLIF cpu_est_ns_2__n.BLIF N_94_i.BLIF N_160.BLIF sm_amiga_ns_0_2__n.BLIF \ + N_159.BLIF sm_amiga_ns_0_0__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BG_030_c_i.BLIF state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un8_bg_030_i_n.BLIF N_163.BLIF state_machine_un10_bg_030_0_n.BLIF N_155.BLIF \ + LDS_000_INT_i.BLIF N_156.BLIF un1_LDS_000_INT_0.BLIF cpu_est_ns_1__n.BLIF UDS_000_INT_i.BLIF state_machine_un12_clk_000_d0_n.BLIF un1_UDS_000_INT_0.BLIF state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un7_ds_030_i_n.BLIF \ + state_machine_un10_clk_000_d0_n.BLIF A0_c_i.BLIF state_machine_un5_clk_000_d0_n.BLIF size_c_i_1__n.BLIF N_161.BLIF un1_bgack_030_int_d_0_1.BLIF state_machine_un10_clk_000_ne_1_n.BLIF N_84_0_1.BLIF N_162.BLIF \ + N_84_0_2.BLIF state_machine_un5_clk_000_d0_2_n.BLIF un3_dtack_i_1.BLIF N_166.BLIF cpu_est_ns_0_1_2__n.BLIF N_167.BLIF N_198_1.BLIF DSACK1_INT_1_sqmuxa.BLIF N_198_2.BLIF \ + state_machine_un6_bgack_000_n.BLIF N_207_1.BLIF DS_000_ENABLE_0_sqmuxa.BLIF N_207_2.BLIF state_machine_un10_clk_000_ne_n.BLIF N_207_3.BLIF N_86.BLIF N_207_4.BLIF state_machine_un6_clk_000_ne_n.BLIF \ + N_207_5.BLIF N_98.BLIF N_207_6.BLIF N_99.BLIF state_machine_un7_ds_030_i_1_n.BLIF N_97.BLIF state_machine_un8_bg_030_1_n.BLIF state_machine_un4_clk_000_ne_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ + un19_fpu_cs_i.BLIF DSACK1_INT_0_sqmuxa_1.BLIF DTACK_i.BLIF AS_030_000_SYNC_0_sqmuxa_1_0.BLIF avec_exp_i.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF CLK_000_NE_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF VPA_D_i.BLIF \ + cpu_est_ns_0_1_1__n.BLIF VMA_INT_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF a_i_19__n.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF DSACK1_INT_0_sqmuxa_i.BLIF state_machine_un10_clk_000_d0_3_n.BLIF \ + a_i_16__n.BLIF state_machine_clk_000_n_sync_2_1_0__n.BLIF a_i_18__n.BLIF state_machine_clk_000_n_sync_2_2_0__n.BLIF nEXP_SPACE_i.BLIF state_machine_clk_000_p_sync_3_1_0__n.BLIF RW_i.BLIF N_167_1_0.BLIF CLK_000_D3_i.BLIF \ + un19_fpu_cs_1.BLIF CLK_000_D2_i.BLIF un19_fpu_cs_2.BLIF CLK_000_D0_i.BLIF un19_fpu_cs_3.BLIF cpu_est_i_3__n.BLIF un19_fpu_cs_4.BLIF cpu_est_i_0__n.BLIF un19_fpu_cs_5.BLIF \ + cpu_est_i_1__n.BLIF un19_fpu_cs_6.BLIF state_machine_un10_clk_000_ne_1_i_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF CLK_000_D1_i.BLIF state_machine_un10_clk_000_ne_1_0_n.BLIF state_machine_un5_clk_000_d0_2_i_0_n.BLIF dsack1_int_0_un3_n.BLIF cpu_est_i_2__n.BLIF \ + dsack1_int_0_un1_n.BLIF DS_000_DMA_1_sqmuxa_1_i.BLIF dsack1_int_0_un0_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF bgack_030_int_0_un3_n.BLIF CLK_030_i.BLIF bgack_030_int_0_un1_n.BLIF UDS_000_i.BLIF bgack_030_int_0_un0_n.BLIF \ + LDS_000_i.BLIF cpu_estse_0_un3_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_0_un1_n.BLIF RW_000_i.BLIF cpu_estse_0_un0_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF vma_int_0_un3_n.BLIF AS_000_DMA_i.BLIF \ + vma_int_0_un1_n.BLIF BGACK_030_INT_i.BLIF vma_int_0_un0_n.BLIF AS_000_i.BLIF ipl_030_0_0__un3_n.BLIF N_90_i.BLIF ipl_030_0_0__un1_n.BLIF BGACK_030_INT_D_i.BLIF ipl_030_0_0__un0_n.BLIF \ + N_89_i.BLIF ipl_030_0_1__un3_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF ipl_030_0_1__un1_n.BLIF sm_amiga_i_7__n.BLIF ipl_030_0_1__un0_n.BLIF CLK_OUT_NE_i.BLIF ipl_030_0_2__un3_n.BLIF sm_amiga_i_0__n.BLIF \ + ipl_030_0_2__un1_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_30__n.BLIF cpu_estse_2_un3_n.BLIF a_i_31__n.BLIF cpu_estse_2_un1_n.BLIF a_i_28__n.BLIF cpu_estse_2_un0_n.BLIF \ + a_i_29__n.BLIF as_000_dma_0_un3_n.BLIF a_i_26__n.BLIF as_000_dma_0_un1_n.BLIF a_i_27__n.BLIF as_000_dma_0_un0_n.BLIF a_i_24__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_25__n.BLIF \ + ds_000_dma_0_un1_n.BLIF RST_i.BLIF ds_000_dma_0_un0_n.BLIF rw_000_dma_0_un3_n.BLIF CLK_OUT_PRE_i.BLIF rw_000_dma_0_un1_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_dma_0_un0_n.BLIF AS_030_c.BLIF \ + clk_030_h_0_un3_n.BLIF clk_030_h_0_un1_n.BLIF AS_000_c.BLIF clk_030_h_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF RW_000_c.BLIF cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF DS_030_c.BLIF \ + rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF UDS_000_c.BLIF rw_000_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF LDS_000_c.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF size_c_0__n.BLIF \ + as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un0_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN \ LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC AVEC_EXP E VMA \ - RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D \ - cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ - IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C \ - SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ - SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ - inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C \ - SIZE_DMA_1_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \ - BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP \ - inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C \ - inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ - inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \ - inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ - RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR cpu_estse.X1 cpu_estse.X2 CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n a_c_30__n a_c_31__n \ - A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \ - ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n \ - N_159_i N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \ - state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ - state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \ - N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \ - un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i \ - N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \ - state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \ - un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 \ - N_86 state_machine_un10_bgack_030_int_0_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n AMIGA_BUS_ENABLE_INT_2_sqmuxa \ - state_machine_size_dma_4_0_0__n N_89 state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n \ - N_164_i N_101 N_163_i un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa state_machine_rw_000_int_7_iv_i_n \ - DSACK1_INT_1_sqmuxa size_c_i_1__n state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ - AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i un1_as_030_000_sync8 \ - state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ - cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 \ - N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \ - UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ - CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ - state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n state_machine_un28_clk_030_2_n \ - nEXP_SPACE_i state_machine_un28_clk_030_3_n sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ - state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ - state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n UDS_000_INT_0_sqmuxa_i \ - cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \ - state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n \ - ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n \ - RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c \ - as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \ - LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n \ - lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ - rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n clk_030_h_0_un3_n \ - a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE \ - DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE \ - BERR.OE CIIN.OE + RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D \ + cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP \ + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C \ + SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.D \ + CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR \ + CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \ + CLK_000_P_SYNC_9_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ + IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR \ + CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C \ + CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D \ + CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR \ + CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \ + inst_CLK_OUT_PRE_25.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_AS_000_INT.D \ + inst_AS_000_INT.C inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_DS_000_ENABLE.AR inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \ + inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_DMA.AP \ + inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C inst_AMIGA_BUS_ENABLE_INTreg.AP inst_CLK_OUT_NEreg.D inst_CLK_OUT_NEreg.C \ + inst_CLK_OUT_NEreg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_OUT_INTreg.D \ + CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \ + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C \ + inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_000_NE.AR inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR cpu_estse.X1 \ + cpu_estse.X2 CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ amiga_bus_enable_int_0_un3_n a_c_16__n amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_17__n bg_000_0_un3_n bg_000_0_un1_n a_c_18__n \ + bg_000_0_un0_n lds_000_int_0_un3_n vcc_n_n a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n ds_000_enable_0_un3_n ds_000_enable_0_un1_n a_c_21__n ds_000_enable_0_un0_n \ + uds_000_int_0_un3_n a_c_22__n uds_000_int_0_un1_n uds_000_int_0_un0_n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n gnd_n_n a_c_28__n \ + a_c_29__n a_c_30__n a_c_31__n A0_c nEXP_SPACE_c state_machine_un3_clk_out_pre_50_n BG_030_c un1_LDS_000_INT BGACK_000_c un1_UDS_000_INT CLK_030_c \ + CLK_000_c CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c DTACK_c un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \ + RST_c RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i DS_000_ENABLE_0_sqmuxa_i un1_SM_AMIGA_0_sqmuxa_1_i state_machine_un10_clk_000_ne_i_n state_machine_un4_clk_000_ne_i_n state_machine_un6_clk_000_ne_i_n \ + N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n state_machine_un6_bgack_000_0_n N_167_i N_166_i AMIGA_BUS_DATA_DIR_c_0 \ + N_162_i N_161_i N_152_i state_machine_un10_clk_000_d0_i_n state_machine_un5_clk_000_d0_i_n state_machine_un12_clk_000_d0_0_n N_198 cpu_est_ns_0_1__n N_207 N_156_i SM_AMIGA_0_sqmuxa \ + N_155_i N_89 N_163_i N_90 state_machine_un5_clk_000_d0_1_i_n state_machine_un8_bg_030_n state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 N_160_i \ + N_87 cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 state_machine_size_dma_4_0_1__n N_101 \ + CLK_030_H_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_030_H_1_sqmuxa_i N_85 state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa un3_dtack_i AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ + state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 \ + N_93_i N_66 state_machine_rw_000_int_3_n AS_030_000_SYNC_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i AS_030_000_SYNC_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \ + state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa N_92_i \ + DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i state_machine_un31_bgack_030_int_n N_96_i \ + state_machine_ds_000_dma_3_n sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i state_machine_un5_clk_000_d0_1_n \ + state_machine_un8_bg_030_i_n N_163 state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n un1_UDS_000_INT_0 \ + state_machine_un6_clk_000_p_sync_n state_machine_un7_ds_030_i_n state_machine_un10_clk_000_d0_n A0_c_i state_machine_un5_clk_000_d0_n size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 state_machine_un10_clk_000_ne_1_n N_84_0_1 N_162 \ + N_84_0_2 state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 cpu_est_ns_0_1_2__n N_167 N_198_1 DSACK1_INT_1_sqmuxa N_198_2 state_machine_un6_bgack_000_n N_207_1 \ + DS_000_ENABLE_0_sqmuxa N_207_2 state_machine_un10_clk_000_ne_n N_207_3 N_86 N_207_4 state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \ + state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i AS_030_000_SYNC_0_sqmuxa_2 \ + CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 VPA_D_i cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i state_machine_un10_clk_000_d0_1_n a_i_19__n state_machine_un10_clk_000_d0_2_0_n DSACK1_INT_0_sqmuxa_i \ + state_machine_un10_clk_000_d0_3_n a_i_16__n state_machine_clk_000_n_sync_2_1_0__n a_i_18__n state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i un19_fpu_cs_1 \ + CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 cpu_est_i_3__n un19_fpu_cs_4 cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n un19_fpu_cs_6 state_machine_un10_clk_000_ne_1_i_n \ + DS_000_ENABLE_0_sqmuxa_1 CLK_000_D1_i state_machine_un10_clk_000_ne_1_0_n state_machine_un5_clk_000_d0_2_i_0_n dsack1_int_0_un3_n cpu_est_i_2__n dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i dsack1_int_0_un0_n state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n \ + CLK_030_i bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n RW_000_i cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n \ + vma_int_0_un3_n AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n AS_000_i ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i ipl_030_0_0__un0_n \ + N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i ipl_030_0_1__un1_n sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i ipl_030_0_2__un3_n sm_amiga_i_0__n ipl_030_0_2__un1_n sm_amiga_i_1__n \ + ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n a_i_31__n cpu_estse_2_un1_n a_i_28__n cpu_estse_2_un0_n a_i_29__n as_000_dma_0_un3_n a_i_26__n as_000_dma_0_un1_n \ + a_i_27__n as_000_dma_0_un0_n a_i_24__n ds_000_dma_0_un3_n a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n rw_000_dma_0_un3_n CLK_OUT_PRE_i rw_000_dma_0_un1_n \ + CLK_OUT_PRE_50_D_i rw_000_dma_0_un0_n AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c clk_030_h_0_un0_n cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n \ + DS_030_c rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n as_030_000_sync_0_un3_n \ + as_030_000_sync_0_un1_n size_c_1__n as_030_000_sync_0_un0_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE \ + SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE .names inst_AS_000_DMA.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c @@ -167,13 +177,13 @@ 1 1 .names un3_dtack_i.BLIF DS_030.OE 1 1 -.names inst_UDS_000_INT.BLIF UDS_000 +.names un1_UDS_000_INT.BLIF UDS_000 1 1 .names UDS_000.PIN UDS_000_c 1 1 .names inst_BGACK_030_INTreg.BLIF UDS_000.OE 1 1 -.names inst_LDS_000_INT.BLIF LDS_000 +.names un1_LDS_000_INT.BLIF LDS_000 1 1 .names LDS_000.PIN LDS_000_c 1 1 @@ -205,11 +215,11 @@ 1 1 .names DSACK1_c.BLIF DTACK 1 1 -.names DTACK.PIN inst_DTACK_D0.D +.names DTACK.PIN DTACK_c 1 1 .names un3_dtack_i.BLIF DTACK.OE 1 1 -.names inst_RW_000_INT.BLIF RW +.names inst_RW_000_DMA.BLIF RW 1 1 .names RW.PIN RW_c 1 1 @@ -217,1025 +227,1174 @@ 1 1 .names gnd_n_n.BLIF BERR 1 1 -.names FPU_CS_INT_i.BLIF BERR.OE +.names un19_fpu_cs.BLIF BERR.OE 1 1 -.names N_210.BLIF CIIN +.names N_198.BLIF CIIN 1 1 -.names N_220.BLIF CIIN.OE +.names N_207.BLIF CIIN.OE 1 1 -.names N_86_0.BLIF N_86 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i 0 1 -.names N_101.BLIF N_101_i -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C +.names state_machine_un7_ds_030_i_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 -.names N_84_0.BLIF N_84 +.names state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un3_bgack_030_int_d_i_n 0 1 -.names N_97.BLIF N_97_i +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D +1- 1 +-1 1 +.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d 0 1 -.names RST_i.BLIF inst_VPA_D.AP +.names un1_as_030.BLIF ds_000_enable_0_un3_n +0 1 +.names RST_i.BLIF CLK_000_P_SYNC_0_.AR 1 1 -.names N_96.BLIF N_96_i +.names N_87_0.BLIF N_87 0 1 -.names N_95.BLIF N_95_i +.names inst_DS_000_ENABLE.BLIF un1_as_030.BLIF ds_000_enable_0_un1_n +11 1 +.names N_85_0.BLIF N_85 0 1 -.names N_150_i.BLIF N_150 +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i 0 1 -.names N_153.BLIF N_153_i +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF inst_DS_000_ENABLE.D +1- 1 +-1 1 +.names N_92.BLIF N_92_i 0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +.names DS_030_c.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C 1 1 -.names N_152.BLIF N_152_i +.names N_163.BLIF N_163_i 0 1 -.names N_160.BLIF N_160_i +.names inst_UDS_000_INT.BLIF DS_030_c.BLIF uds_000_int_0_un1_n +11 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un5_clk_000_d0_1_i_n 0 1 -.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR +.names A0_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names RST_i.BLIF CLK_000_P_SYNC_1_.AR 1 1 -.names N_154.BLIF N_154_i -0 1 .names state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_2_i_n 0 1 -.names N_156.BLIF N_156_i +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names N_159.BLIF N_159_i 0 1 -.names vcc_n_n.BLIF RESETDFFRHreg.D -1 1 -.names N_157.BLIF N_157_i +.names vcc_n_n +1 +.names N_160.BLIF N_160_i 0 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 +.names gnd_n_n .names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n 0 1 -.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 -.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n +.names state_machine_un10_bgack_030_int_0_n.BLIF state_machine_un10_bgack_030_int_n 0 1 -.names RST_i.BLIF cpu_est_1_.AR +.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n +0 1 +.names RST_i.BLIF inst_VMA_INTreg.AP 1 1 -.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n +.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D 0 1 -.names RST_i.BLIF RESETDFFRHreg.AR +.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 -.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i +.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n 0 1 -.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i 0 1 -.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i -0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names RST_i.BLIF inst_BGACK_030_INTreg.AP 1 1 -.names cpu_est_0_.BLIF cpu_estse.X1 -1 1 -.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i 0 1 -.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names RST_i.BLIF cpu_est_2_.AR -1 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse.X2 +.names N_86_i.BLIF N_86 +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un6_clk_000_p_sync_i_n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C 1 1 .names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 +.names N_167.BLIF N_167_i +0 1 +.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR +1 1 +.names N_166.BLIF N_166_i +0 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names N_162.BLIF N_162_i +0 1 +.names N_161.BLIF N_161_i +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n +0 1 +.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_n +0 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n +0 1 .names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n 0 1 -.names N_159.BLIF N_159_i -0 1 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 -.names N_158.BLIF N_158_i +.names N_156.BLIF N_156_i +0 1 +.names N_155.BLIF N_155_i +0 1 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +.names SM_AMIGA_0_sqmuxa.BLIF SM_AMIGA_0_sqmuxa_i +0 1 +.names DS_000_ENABLE_0_sqmuxa.BLIF DS_000_ENABLE_0_sqmuxa_i +0 1 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +.names un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names state_machine_un10_clk_000_ne_n.BLIF state_machine_un10_clk_000_ne_i_n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names state_machine_un4_clk_000_ne_n.BLIF state_machine_un4_clk_000_ne_i_n +0 1 +.names state_machine_un6_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_n +0 1 +.names RST_i.BLIF cpu_est_1_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_97.BLIF N_97_i +0 1 +.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names RST_i.BLIF inst_LDS_000_INT.AP +1 1 +.names N_99.BLIF N_99_i +0 1 +.names N_98.BLIF N_98_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names N_86.BLIF SM_AMIGA_3_.BLIF N_97 +11 1 +.names state_machine_un4_clk_000_ne_i_n.BLIF state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_i_n +11 1 +.names RST_i.BLIF cpu_est_2_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF state_machine_un4_clk_000_ne_n +11 1 +.names RST_i.BLIF inst_AS_000_INT.AP +1 1 +.names DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i +11 1 +.names un19_fpu_cs.BLIF un19_fpu_cs_i 0 1 .names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152 -11 1 -.names state_machine_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2 -1 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names a_c_18__n.BLIF a_i_18__n 0 1 +.names BGACK_000_c.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF state_machine_un6_bgack_000_0_n +11 1 .names RST_i.BLIF cpu_est_3_reg.AR 1 1 -.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_0_n -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i 0 1 -.names cpu_estse.BLIF cpu_est_0_.D +.names AS_030_i.BLIF DSACK1_INT_0_sqmuxa_i.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names RST_i.BLIF inst_DS_000_ENABLE.AR 1 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n +.names AS_030_c.BLIF AS_030_i 0 1 -.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 -.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 -.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names inst_CLK_000_NE.BLIF state_machine_un6_clk_000_ne_n.BLIF N_86_i 11 1 -.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names N_97_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF sm_amiga_ns_0_4__n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names N_86_i.BLIF SM_AMIGA_3_.BLIF N_99 +11 1 +.names inst_avec_expreg.BLIF avec_exp_i +0 1 +.names RST_i.BLIF SM_AMIGA_6_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names SM_AMIGA_2_.BLIF avec_exp_i.BLIF N_98 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF state_machine_un10_clk_000_ne_1_n +11 1 +.names RST_i.BLIF inst_UDS_000_INT.AP +1 1 +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_2_n +11 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names RST_i.BLIF SM_AMIGA_5_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names RST_i.BLIF inst_RW_000_INT.AP +1 1 +.names inst_CLK_000_D3.BLIF CLK_000_D3_i +0 1 +.names RW_c.BLIF RW_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_166 +11 1 +.names N_166_i.BLIF N_167_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names RST_i.BLIF SM_AMIGA_4_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n +0 1 +.names RST_i.BLIF inst_A0_DMA.AP +1 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +11 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D 1- 1 -1 1 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un1_n +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 -.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n +.names a_c_16__n.BLIF a_i_16__n 0 1 -.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un1_n +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names inst_avec_expreg.BLIF cpu_estse_0_un3_n +0 1 +.names cpu_est_ns_1__n.BLIF inst_avec_expreg.BLIF cpu_estse_0_un1_n 11 1 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +.names RST_i.BLIF inst_RW_000_DMA.AP 1 1 .names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n 11 1 .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n +.names state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_2_i_0_n 0 1 -.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C 1 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names state_machine_un5_clk_000_d0_2_i_0_n.BLIF state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +.names RST_i.BLIF inst_DS_000_DMA.AP +1 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un3_n 0 1 -.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +.names ipl_c_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un1_n +11 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un3_n +0 1 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 +.names RST_i.BLIF inst_AS_000_DMA.AP +1 1 +.names ipl_c_1__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un1_n 11 1 .names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un3_n 0 1 -.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C 1 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C +1 1 +.names ipl_c_2__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un1_n 11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names RST_i.BLIF CLK_000_P_SYNC_2_.AR +1 1 +.names RST_i.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP +1 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names inst_avec_expreg.BLIF cpu_estse_2_un3_n 0 1 -.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +.names N_152_i.BLIF inst_avec_expreg.BLIF cpu_estse_2_un1_n 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C +.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C 1 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D +.names CLK_OSZI_c.BLIF inst_CLK_OUT_NEreg.C +1 1 +.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i -11 1 -.names N_158_i.BLIF N_159_i.BLIF N_149_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names N_160.BLIF cpu_est_i_3__n.BLIF N_159 -11 1 -.names N_150.BLIF cpu_est_2_.BLIF N_158 -11 1 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n +.names inst_CLK_000_D1.BLIF CLK_000_D1_i 0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157 +.names RST_i.BLIF CLK_000_P_SYNC_3_.AR +1 1 +.names RST_i.BLIF inst_CLK_OUT_NEreg.AR +1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un6_clk_000_p_sync_n 11 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156 +.names state_machine_un5_clk_000_d0_i_n.BLIF state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n +.names state_machine_un10_clk_000_ne_1_n.BLIF state_machine_un10_clk_000_ne_1_i_n +0 1 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +1 1 +.names cpu_est_2_.BLIF state_machine_un10_clk_000_ne_1_i_n.BLIF N_161 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +.names N_163.BLIF cpu_est_i_3__n.BLIF N_162 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +1 1 +.names N_161_i.BLIF N_162_i.BLIF N_152_i +11 1 +.names RST_i.BLIF CLK_000_P_SYNC_4_.AR 1 1 .names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154 -11 1 -.names RST_i.BLIF SM_AMIGA_5_.AR +.names RST_i.BLIF inst_CLK_000_D2.AP 1 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n 0 1 +.names A_16_.BLIF a_c_16__n +1 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n +11 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D +1 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D +1- 1 +-1 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 +.names RST_i.BLIF CLK_000_P_SYNC_5_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n +11 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR +1 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D +1- 1 +-1 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names DS_000_DMA_1_sqmuxa_1.BLIF DS_000_DMA_1_sqmuxa_1_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names inst_RW_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un1_n +11 1 +.names RST_i.BLIF CLK_000_P_SYNC_6_.AR +1 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names DS_000_DMA_1_sqmuxa_1_i.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF inst_RW_000_DMA.D +1- 1 +-1 1 +.names A_28_.BLIF a_c_28__n +1 1 +.names RST_c.BLIF clk_030_h_0_un3_n +0 1 +.names RST_i.BLIF inst_CLK_000_D3.AP +1 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n +11 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D +1- 1 +-1 1 +.names RST_i.BLIF CLK_000_P_SYNC_7_.AR +1 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D +1 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_163 +11 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_160 +11 1 +.names BG_030.BLIF BG_030_c +1 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_159 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +.names RST_i.BLIF CLK_OUT_INTreg.AR +1 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_1_n +11 1 +.names RST_i.BLIF CLK_000_P_SYNC_8_.AR +1 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_156 +11 1 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names CLK_030.BLIF CLK_030_c +1 1 .names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +.names CLK_000.BLIF CLK_000_c 1 1 -.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF AS_030_000_SYNC_0_sqmuxa_2 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_155 11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n -11 1 -.names RST_i.BLIF SM_AMIGA_4_.AR +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa -11 1 -.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0 -11 1 -.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF un1_as_030_000_sync8_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +.names CLK_OSZI.BLIF CLK_OSZI_c 1 1 -.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF un1_as_030_000_sync8_1_0 -11 1 -.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa -11 1 -.names RST_i.BLIF SM_AMIGA_3_.AR +.names inst_avec_expreg.BLIF cpu_estse_1_un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C 1 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n -0 1 -.names state_machine_un5_clk_000_d0_i_0_n.BLIF state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT 1 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n +.names cpu_est_ns_2__n.BLIF inst_avec_expreg.BLIF cpu_estse_1_un1_n 11 1 -.names RST_i.BLIF SM_AMIGA_2_.AR +.names RST_i.BLIF inst_CLK_000_D1.AP 1 1 -.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un1_n +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n 11 1 -.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +.names RST_i.BLIF CLK_000_P_SYNC_9_.AR +1 1 +.names un19_fpu_cs_i.BLIF FPU_CS +1 1 +.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ +1 1 +.names state_machine_clk_030_h_2_f1_n.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D +1 1 +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +1 1 +.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF state_machine_clk_030_h_2_f1_0_n +11 1 +.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ +1 1 +.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names state_machine_un31_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n +0 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n +11 1 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +.names RST_i.BLIF inst_BGACK_030_INT_D.AP +1 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_ds_000_dma_3_0_n +11 1 +.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +11 1 +.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa +11 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D +1 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names inst_avec_expreg.BLIF AVEC_EXP +1 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C +1 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +.names VPA.BLIF inst_VPA_D.D +1 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n +11 1 +.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR +1 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names RST.BLIF RST_c +1 1 +.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n +11 1 +.names RESETDFFRHreg.BLIF RESET +1 1 +.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_i_n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names N_66.BLIF rw_000_int_0_un3_n +0 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names state_machine_rw_000_int_3_n.BLIF N_66.BLIF rw_000_int_0_un1_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE +1 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D +1- 1 +-1 1 +.names RST_i.BLIF inst_CLK_OUT_PRE_D.AR +1 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names N_90.BLIF N_90_i +0 1 +.names inst_CLK_OUT_NEreg.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names CLK_000_c.BLIF inst_CLK_000_D0.D +1 1 +.names state_machine_clk_000_p_sync_3_1_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF CLK_000_P_SYNC_0_.D +11 1 +.names N_90_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +.names N_167_1.BLIF RW_c.BLIF N_167_1_0 +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +.names N_167_1_0.BLIF nEXP_SPACE_i.BLIF N_167 +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un3_n +0 1 +.names AS_030_i.BLIF a_c_17__n.BLIF un19_fpu_cs_1 +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un1_n +11 1 +.names RST_i.BLIF inst_CLK_000_D0.AP +1 1 +.names a_i_16__n.BLIF a_i_18__n.BLIF un19_fpu_cs_2 +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +.names a_i_19__n.BLIF BGACK_000_c.BLIF un19_fpu_cs_3 11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n +.names fc_c_0__n.BLIF fc_c_1__n.BLIF un19_fpu_cs_4 +11 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un3_n 0 1 -.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n -11 1 -.names RST_i.BLIF SM_AMIGA_1_.AR +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP 1 1 -.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +.names un19_fpu_cs_1.BLIF un19_fpu_cs_2.BLIF un19_fpu_cs_5 11 1 -.names A_16_.BLIF a_c_16__n +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +.names un19_fpu_cs_3.BLIF un19_fpu_cs_4.BLIF un19_fpu_cs_6 +11 1 +.names un1_bgack_030_int_d.BLIF amiga_bus_enable_int_0_un3_n.BLIF amiga_bus_enable_int_0_un0_n +11 1 +.names un19_fpu_cs_5.BLIF un19_fpu_cs_6.BLIF un19_fpu_cs +11 1 +.names amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.D 1- 1 -1 1 -.names A_17_.BLIF a_c_17__n +.names RST_i.BLIF inst_VPA_D.AP 1 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names RW_c.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa_1 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names N_167_1.BLIF state_machine_un10_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_n 11 1 -.names A_20_.BLIF a_c_20__n +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C 1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D -1- 1 --1 1 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n -0 1 -.names A_22_.BLIF a_c_22__n -1 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +.names DS_000_ENABLE_0_sqmuxa_1.BLIF inst_avec_expreg.BLIF DS_000_ENABLE_0_sqmuxa 11 1 -.names A_23_.BLIF a_c_23__n -1 1 -.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n -0 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names state_machine_un5_clk_000_d0_i_0_n.BLIF state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n -11 1 -.names BG_030.BLIF BG_030_c -1 1 -.names state_machine_un51_clk_000_d0_i_n.BLIF state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n -11 1 -.names BG_000DFFSHreg.BLIF BG_000 -1 1 -.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa -11 1 -.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR -1 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96 -11 1 -.names CLK_000.BLIF CLK_000_c -1 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97 -11 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99 -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names RST_i.BLIF SIZE_DMA_0_.AP -1 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 -.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ -1 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D -11 1 -.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ -1 1 -.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0 -11 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0 -11 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names RST_i.BLIF SIZE_DMA_1_.AP -1 1 -.names N_99.BLIF N_99_i -0 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names inst_avec_expreg.BLIF AVEC_EXP -1 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0 -11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names cpu_est_3_reg.BLIF E -1 1 -.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n -0 1 -.names VPA.BLIF inst_VPA_D.D -1 1 -.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un1_n -11 1 -.names RST_i.BLIF inst_LDS_000_INT.AP -1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n -11 1 -.names RST.BLIF RST_c -1 1 -.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D -1- 1 --1 1 -.names RESETDFFRHreg.BLIF RESET -1 1 -.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF state_machine_un3_bgack_030_int_d_n -11 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF state_machine_un5_bgack_030_int_d_i_n -11 1 -.names CLK_OSZI_c.BLIF inst_avec_expreg.C -1 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n -11 1 -.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa -11 1 -.names state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 -11 1 -.names RST_i.BLIF inst_avec_expreg.AP -1 1 -.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF state_machine_un10_clk_000_d0_1_n -11 1 -.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 -11 1 -.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF state_machine_un10_clk_000_d0_2_0_n -11 1 -.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_0_n -11 1 -.names state_machine_un10_clk_000_d0_1_n.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n -11 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 -11 1 -.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF state_machine_un10_clk_000_d0_n -11 1 -.names N_84.BLIF SM_AMIGA_7_.BLIF N_88 -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89 -11 1 -.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 -11 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names state_machine_un31_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n -0 1 -.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF state_machine_un28_clk_000_d1_1_n -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n -11 1 -.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF state_machine_un28_clk_000_d1_n -11 1 -.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF state_machine_lds_000_int_7_0_n -11 1 -.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF state_machine_un8_bg_030_n -11 1 -.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n -11 1 -.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i -0 1 -.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF state_machine_un57_clk_000_d0_n -11 1 -.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1 -11 1 -.names RST_i.BLIF inst_DS_000_DMA.AP -1 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF state_machine_un49_clk_000_d0_1_n -11 1 -.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2 -11 1 -.names state_machine_un49_clk_000_d0_1_n.BLIF state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n -11 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n -11 1 -.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1 -11 1 -.names UDS_000_c.BLIF UDS_000_i -0 1 -.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF AS_030_000_SYNC_0_sqmuxa_2_0 -11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF AS_030_000_SYNC_0_sqmuxa -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n -11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n -11 1 -.names un1_AS_030_2.BLIF lds_000_int_0_un3_n -0 1 -.names RST_i.BLIF inst_AS_000_DMA.AP -1 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n -11 1 -.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n -11 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n -11 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF state_machine_un28_clk_030_4_n -11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D -1- 1 --1 1 -.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un28_clk_030_5_n -11 1 -.names un1_AS_030_2.BLIF uds_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF state_machine_un28_clk_030_n -11 1 -.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n -11 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n -11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names RST_i.BLIF inst_AS_000_INT.AP -1 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2 -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D -1- 1 --1 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa -11 1 -.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n -0 1 -.names N_164_1.BLIF RW_c.BLIF N_164_1_0 -11 1 -.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n -11 1 -.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164 -11 1 -.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1 -11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D -1- 1 --1 1 -.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names RST_i.BLIF inst_DSACK1_INT.AP -1 1 -.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181 -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa -11 1 -.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1 -11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101 -11 1 -.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m -11 1 -.names state_machine_un3_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 -11 1 -.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names RST_i.BLIF inst_RW_000_INT.AP -1 1 -.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF un1_bgack_030_int_d_0 -11 1 -.names RW_c.BLIF RW_i -0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163 -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n -11 1 -.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2 -11 1 -.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_210_1.BLIF N_210_2.BLIF N_210 -11 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2 -11 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3 -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4 -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_i_n -0 1 -.names N_220_1.BLIF N_220_2.BLIF N_220_5 -11 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names N_220_3.BLIF N_220_4.BLIF N_220_6 -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names N_220_5.BLIF N_220_6.BLIF N_220 -11 1 -.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF DS_000_DMA_1_sqmuxa_1 -11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D -1- 1 --1 1 -.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF DS_000_DMA_1_sqmuxa -11 1 -.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n -11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2 -11 1 -.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names RST_i.BLIF inst_UDS_000_INT.AP -1 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1 -11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D -1- 1 --1 1 -.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names RST_c.BLIF clk_030_h_0_un3_n -0 1 -.names N_93.BLIF N_93_i -0 1 -.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n -11 1 -.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D -0 1 -.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names N_87_0.BLIF N_87 -0 1 -.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D -1- 1 --1 1 -.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0 -11 1 -.names RST_i.BLIF inst_A0_DMA.AP -1 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n -11 1 -.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i -0 1 -.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D -11 1 -.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n -0 1 -.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n -0 1 -.names N_92.BLIF N_92_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94 -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93 -11 1 -.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i -11 1 -.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90 -11 1 -.names RST_i.BLIF inst_DTACK_D0.AP -1 1 -.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n -11 1 -.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_n -11 1 -.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un25_clk_000_d0_i_n -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n +.names state_machine_un10_clk_000_ne_1_n.BLIF VMA_INT_i.BLIF state_machine_un10_clk_000_ne_1_0_n 11 1 .names AS_000_c.BLIF AS_000_i 0 1 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +.names RST_i.BLIF CLK_000_N_SYNC_0_.AR 1 1 -.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF cpu_est_ns_0_2__n +.names state_machine_un10_clk_000_ne_1_0_n.BLIF VPA_D_i.BLIF state_machine_un10_clk_000_ne_n 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_167_1 11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1 -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +.names CLK_OSZI_c.BLIF inst_avec_expreg.C 1 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names RST_i.BLIF inst_CLK_000_D2.AP -1 1 -.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92 +.names nEXP_SPACE_c.BLIF un19_fpu_cs_i.BLIF AS_030_000_SYNC_0_sqmuxa_2 11 1 -.names N_91.BLIF N_91_i -0 1 -.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_100.BLIF N_100_i -0 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D -1 1 -.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8 -0 1 +.names AS_030_000_SYNC_0_sqmuxa_1_0.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa +11 1 .names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa 11 1 -.names N_164.BLIF N_164_i -0 1 +.names RST_i.BLIF inst_avec_expreg.AR +1 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 +11 1 .names state_machine_un24_bgack_030_int_n.BLIF state_machine_un24_bgack_030_int_i_n 0 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C 1 1 -.names N_163.BLIF N_163_i -0 1 -.names state_machine_clk_030_h_2_f1_n.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa 11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF state_machine_clk_030_h_2_f1_0_n +.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF DS_000_DMA_1_sqmuxa 11 1 -.names RST_i.BLIF CLK_OUT_INTreg.AR +.names N_155_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_1__n +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names RST_i.BLIF CLK_000_N_SYNC_1_.AR 1 1 -.names RW_000_i_m.BLIF RW_000_i_m_i -0 1 -.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_ds_000_dma_3_0_n +.names N_163_i.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF cpu_est_ns_0_2_1__n 11 1 -.names RW_li_m.BLIF RW_li_m_i -0 1 -.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF DS_000_DMA_1_sqmuxa_1 11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa -11 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C 1 1 -.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n -0 1 -.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF AS_000_DMA_0_sqmuxa +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n 11 1 -.names N_90.BLIF N_90_i +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n 0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -.names N_94.BLIF N_94_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n +.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF state_machine_un10_clk_000_d0_1_n 11 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D -0 1 -.names RST_i.BLIF inst_CLK_000_D1.AP +.names N_87.BLIF sm_amiga_i_7__n.BLIF N_93 +11 1 +.names RST_i.BLIF inst_CLK_000_NE.AR 1 1 -.names N_88.BLIF N_88_i -0 1 -.names RST_c.BLIF RST_i +.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF state_machine_un10_clk_000_d0_2_0_n +11 1 +.names N_84.BLIF SM_AMIGA_7_.BLIF N_91 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +.names state_machine_un10_clk_000_d0_1_n.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n +11 1 +.names RW_i.BLIF sm_amiga_i_7__n.BLIF state_machine_rw_000_int_3_0_n +11 1 +.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF state_machine_un10_clk_000_d0_n +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_2_.AR +1 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF state_machine_clk_000_n_sync_2_1_0__n +11 1 +.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i 0 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF state_machine_clk_000_n_sync_2_2_0__n +11 1 +.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF AS_030_000_SYNC_0_sqmuxa_1 +11 1 +.names state_machine_clk_000_n_sync_2_1_0__n.BLIF state_machine_clk_000_n_sync_2_2_0__n.BLIF CLK_000_N_SYNC_0_.D +11 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 +11 1 +.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR +1 1 +.names CLK_000_D2_i.BLIF CLK_000_D3_i.BLIF state_machine_clk_000_p_sync_3_1_0__n +11 1 +.names AS_030_i.BLIF N_90_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_207_1 +11 1 .names N_89.BLIF N_89_i 0 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D -0 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D -1 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i -0 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 -.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names RST_i.BLIF inst_BGACK_030_INT_D.AP -1 1 -.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n -0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_59_0.BLIF N_59 -0 1 -.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i -0 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D -1 1 -.names state_machine_un10_bgack_030_int_0_n.BLIF state_machine_un10_bgack_030_int_n -0 1 -.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF state_machine_un3_clk_out_pre_50_n +.names a_i_26__n.BLIF a_i_27__n.BLIF N_207_2 11 1 -.names N_181.BLIF N_181_i +.names N_89_i.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_3_.AR +1 1 +.names vcc_n_n.BLIF RESETDFFRHreg.D +1 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_207_3 +11 1 +.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_207_4 +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF state_machine_un5_bgack_030_int_d_i_n +11 1 +.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +1 1 +.names N_207_1.BLIF N_207_2.BLIF N_207_5 +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i 0 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +.names N_207_3.BLIF N_207_4.BLIF N_207_6 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF state_machine_un3_bgack_030_int_d_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +.names RST_i.BLIF RESETDFFRHreg.AR +1 1 +.names N_207_5.BLIF N_207_6.BLIF N_207 +11 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_101 +11 1 +.names size_c_i_1__n.BLIF A0_c_i.BLIF state_machine_un7_ds_030_i_1_n +11 1 +.names N_91_i.BLIF N_92_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_4_.AR +1 1 +.names state_machine_un7_ds_030_i_1_n.BLIF size_c_0__n.BLIF state_machine_un7_ds_030_i_n +11 1 +.names N_90_i.BLIF N_94_i.BLIF sm_amiga_ns_0_2__n +11 1 +.names inst_avec_expreg.BLIF cpu_estse.X1 +1 1 +.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n +11 1 +.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_3__n +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n +11 1 +.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_6__n +11 1 +.names cpu_est_0_.BLIF cpu_estse.X2 +1 1 +.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF state_machine_un8_bg_030_n +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF N_92_i.BLIF SM_AMIGA_0_.D +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +.names inst_CLK_000_D1.BLIF CLK_OUT_NE_i.BLIF DSACK1_INT_0_sqmuxa_1 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C +.names DSACK1_INT_0_sqmuxa_1.BLIF SM_AMIGA_1_.BLIF DSACK1_INT_0_sqmuxa +11 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_85_0 +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_5_.AR +1 1 +.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1 +1 1 +.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1_0 +11 1 +.names SM_AMIGA_6_.BLIF avec_exp_i.BLIF N_87_0 +11 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names state_machine_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2 1 1 .names A0_c.BLIF A0_c_i 0 1 -.names vcc_n_n -1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +.names N_85.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n 0 1 -.names gnd_n_n -.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR +.names AS_030_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_as_030 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C 1 1 -.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12 +.names state_machine_un3_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 +11 1 +.names inst_CLK_OUT_NEreg.BLIF CLK_OUT_NE_i 0 1 -.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n -0 1 -.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D0.D +.names cpu_estse.BLIF cpu_est_0_.D 1 1 -.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n -0 1 -.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF un1_bgack_030_int_d_0 +11 1 +.names N_91_i.BLIF N_93_i.BLIF SM_AMIGA_6_.D +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_6_.AR 1 1 -.names state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un3_bgack_030_int_d_i_n -0 1 -.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d -0 1 -.names RST_i.BLIF inst_CLK_000_D0.AP +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D 1 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_D1_i.BLIF N_84_0_1 +11 1 +.names N_90_i.BLIF sm_amiga_i_7__n.BLIF N_66_0 +11 1 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +.names inst_CLK_000_D2.BLIF nEXP_SPACE_c.BLIF N_84_0_2 +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0 +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i +11 1 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +.names N_160_i.BLIF N_159_i.BLIF cpu_est_ns_0_1_2__n +11 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_7_.AR +1 1 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF cpu_est_ns_0_2__n +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +11 1 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_198_1 +11 1 +.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_0_n +11 1 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_198_2 +11 1 +.names SM_AMIGA_4_.BLIF inst_avec_expreg.BLIF SM_AMIGA_0_sqmuxa +11 1 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +.names N_198_1.BLIF N_198_2.BLIF N_198 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_89 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +.names N_100.BLIF N_100_i +0 1 +.names SM_AMIGA_6_.BLIF inst_avec_expreg.BLIF N_90 +11 1 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +.names N_101.BLIF N_101_i +0 1 +.names SM_AMIGA_0_.BLIF inst_avec_expreg.BLIF N_92 +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_8_.AR +1 1 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D +0 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_94 +11 1 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +.names N_95.BLIF N_95_i +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_5_.BLIF N_95 +11 1 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +.names N_96.BLIF N_96_i +0 1 +.names SM_AMIGA_4_.BLIF avec_exp_i.BLIF N_96 +11 1 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +.names sm_amiga_ns_0_3__n.BLIF SM_AMIGA_4_.D +0 1 +.names SM_AMIGA_2_.BLIF inst_avec_expreg.BLIF N_100 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +.names N_94.BLIF N_94_i +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names RST_c.BLIF RST_i +0 1 +.names RST_i.BLIF CLK_000_N_SYNC_9_.AR +1 1 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D +1 1 +.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n +0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D +1 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT +0 1 +.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i +0 1 +.names RST_i.BLIF CLK_000_N_SYNC_10_.AR +1 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF state_machine_un3_clk_out_pre_50_n +11 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i +0 1 +.names state_machine_rw_000_int_3_0_n.BLIF state_machine_rw_000_int_3_n +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_i.BLIF inst_CLK_OUT_NEreg.D +11 1 +.names N_66_0.BLIF N_66 +0 1 +.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +.names N_91.BLIF N_91_i +0 1 +.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names N_93.BLIF N_93_i +0 1 +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names RST_i.BLIF CLK_000_N_SYNC_11_.AR +1 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names N_84_0.BLIF N_84 +0 1 +.names DS_030_c.BLIF lds_000_int_0_un3_n +0 1 .names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i 0 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i -0 1 +.names inst_LDS_000_INT.BLIF DS_030_c.BLIF lds_000_int_0_un1_n +11 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index cce867e..9021127 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,111 +1,115 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat Jun 07 23:03:19 2014 +#$ DATE Mon Jun 09 10:27:24 2014 #$ MODULE bus68030 -#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \ -# IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ -# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \ -# A_25_ A_24_ A_23_ -#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n \ -# inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \ -# nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c \ -# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \ -# inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n \ -# gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ \ -# inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ -# IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n inst_CLK_000_D2 \ -# IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \ -# SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ \ -# ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n CLK_OUT_PRE_25_0 \ -# fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n \ -# cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n \ -# cpu_est_3_reg N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa \ -# N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \ -# state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i \ -# N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ -# state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ -# state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ -# FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ -# state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ -# state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 \ -# state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ -# state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 \ -# state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \ -# un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ -# UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \ -# state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 \ -# RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \ -# state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i \ -# state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 \ -# AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ -# N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ -# un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ -# state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ -# state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ -# AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ -# AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ -# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ -# state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ -# AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ -# state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \ -# state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 \ -# AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ -# un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ -# state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ -# state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ -# state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ -# state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ -# AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ -# state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ -# CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ -# un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ -# state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ -# cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ -# cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 \ -# N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 \ -# state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i \ -# UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n \ -# UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n \ -# N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ -# CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n \ -# N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ -# AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ -# state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ -# a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ -# a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ -# state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ -# sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ -# state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ -# sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ -# state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ -# state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ -# state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ -# cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ -# state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ -# state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ -# cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ -# UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ -# cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ -# state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \ -# state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i \ -# ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n \ -# a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \ -# ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n \ -# a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n \ -# CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n \ -# as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \ -# dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n \ -# UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \ -# avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n \ -# bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -# a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ -# rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n \ -# as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n \ -# ds_000_dma_0_un0_n clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n \ -# a_c_25__n a_c_26__n a_c_27__n +#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 SIZE_0_ RW_000 A_30_ \ +# DS_030 A_29_ UDS_000 A_28_ LDS_000 A_27_ A0 A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ \ +# BG_000 A_22_ BGACK_030 A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ \ +# CLK_DIV_OUT A_16_ CLK_EXP IPL_030_1_ FPU_CS IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC \ +# FC_0_ AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW CIIN +#$ NODES 425 amiga_bus_enable_int_0_un3_n a_c_16__n amiga_bus_enable_int_0_un1_n \ +# amiga_bus_enable_int_0_un0_n a_c_17__n bg_000_0_un3_n bg_000_0_un1_n a_c_18__n \ +# bg_000_0_un0_n inst_BGACK_030_INTreg lds_000_int_0_un3_n vcc_n_n a_c_19__n \ +# lds_000_int_0_un1_n inst_avec_expreg lds_000_int_0_un0_n inst_VMA_INTreg a_c_20__n \ +# ds_000_enable_0_un3_n inst_AMIGA_BUS_ENABLE_INTreg ds_000_enable_0_un1_n \ +# inst_CLK_OUT_NEreg a_c_21__n ds_000_enable_0_un0_n inst_AS_030_000_SYNC \ +# uds_000_int_0_un3_n inst_BGACK_030_INT_D a_c_22__n uds_000_int_0_un1_n \ +# inst_AS_000_DMA uds_000_int_0_un0_n inst_VPA_D a_c_23__n inst_CLK_OUT_PRE_50_D \ +# inst_CLK_OUT_PRE a_c_24__n inst_CLK_000_D0 inst_CLK_000_D1 a_c_25__n \ +# inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 a_c_26__n inst_CLK_000_D2 inst_CLK_000_D3 \ +# a_c_27__n inst_CLK_000_NE gnd_n_n a_c_28__n inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ \ +# a_c_29__n CLK_000_N_SYNC_11_ inst_AS_000_INT a_c_30__n SM_AMIGA_7_ SM_AMIGA_6_ \ +# a_c_31__n SM_AMIGA_1_ SM_AMIGA_0_ A0_c SM_AMIGA_4_ inst_RW_000_INT nEXP_SPACE_c \ +# inst_DSACK1_INT state_machine_un3_clk_out_pre_50_n BG_030_c inst_CLK_030_H \ +# inst_RW_000_DMA BG_000DFFSHreg un1_LDS_000_INT inst_LDS_000_INT inst_DS_000_ENABLE \ +# BGACK_000_c un1_UDS_000_INT inst_UDS_000_INT CLK_030_c CLK_000_c inst_DS_000_DMA \ +# SIZE_DMA_0_ CLK_OSZI_c SIZE_DMA_1_ inst_A0_DMA CLK_000_N_SYNC_0_ CLK_OUT_INTreg \ +# CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ IPL_030DFFSH_0_reg \ +# CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ IPL_030DFFSH_1_reg CLK_000_N_SYNC_6_ \ +# CLK_000_N_SYNC_7_ IPL_030DFFSH_2_reg CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ \ +# ipl_c_0__n CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ ipl_c_1__n CLK_000_P_SYNC_1_ \ +# CLK_000_P_SYNC_2_ ipl_c_2__n CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ DSACK1_c \ +# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ DTACK_c CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \ +# un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \ +# SM_AMIGA_5_ SM_AMIGA_3_ RST_c SM_AMIGA_2_ RESETDFFRHreg RW_c fc_c_0__n fc_c_1__n \ +# AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i DS_000_ENABLE_0_sqmuxa_i \ +# un1_SM_AMIGA_0_sqmuxa_1_i state_machine_un10_clk_000_ne_i_n \ +# state_machine_un4_clk_000_ne_i_n CLK_OUT_PRE_25_0 \ +# state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i \ +# sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n \ +# state_machine_un6_bgack_000_0_n N_167_i cpu_est_0_ N_166_i cpu_est_1_ \ +# AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_162_i cpu_est_3_reg N_161_i cpu_estse N_152_i \ +# state_machine_un10_clk_000_d0_i_n state_machine_un5_clk_000_d0_i_n \ +# state_machine_un12_clk_000_d0_0_n N_198 cpu_est_ns_0_1__n N_207 N_156_i \ +# SM_AMIGA_0_sqmuxa N_155_i N_89 N_163_i N_90 state_machine_un5_clk_000_d0_1_i_n \ +# state_machine_un8_bg_030_n state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 \ +# N_160_i N_87 cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 \ +# state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 \ +# state_machine_size_dma_4_0_1__n N_101 CLK_030_H_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ +# CLK_030_H_1_sqmuxa_i N_85 state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa \ +# un3_dtack_i AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n \ +# un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ +# state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \ +# AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 \ +# AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 N_93_i N_66 state_machine_rw_000_int_3_n \ +# AS_030_000_SYNC_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ +# AS_030_000_SYNC_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \ +# state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n \ +# un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \ +# CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa N_92_i \ +# DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i \ +# state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \ +# sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i \ +# state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n \ +# sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 \ +# sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i \ +# state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 \ +# state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 \ +# cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n un1_UDS_000_INT_0 \ +# state_machine_un6_clk_000_p_sync_n state_machine_un7_ds_030_i_n \ +# state_machine_un10_clk_000_d0_n A0_c_i state_machine_un5_clk_000_d0_n \ +# size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 state_machine_un10_clk_000_ne_1_n \ +# N_84_0_1 N_162 N_84_0_2 state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 \ +# cpu_est_ns_0_1_2__n N_167 N_198_1 DSACK1_INT_1_sqmuxa N_198_2 \ +# state_machine_un6_bgack_000_n N_207_1 DS_000_ENABLE_0_sqmuxa N_207_2 \ +# state_machine_un10_clk_000_ne_n N_207_3 N_86 N_207_4 \ +# state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \ +# state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n \ +# state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i \ +# DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \ +# AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 VPA_D_i \ +# cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i \ +# state_machine_un10_clk_000_d0_1_n a_i_19__n state_machine_un10_clk_000_d0_2_0_n \ +# DSACK1_INT_0_sqmuxa_i state_machine_un10_clk_000_d0_3_n a_i_16__n \ +# state_machine_clk_000_n_sync_2_1_0__n a_i_18__n \ +# state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i \ +# state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i un19_fpu_cs_1 \ +# CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 cpu_est_i_3__n un19_fpu_cs_4 \ +# cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n un19_fpu_cs_6 \ +# state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 CLK_000_D1_i \ +# state_machine_un10_clk_000_ne_1_0_n state_machine_un5_clk_000_d0_2_i_0_n \ +# dsack1_int_0_un3_n cpu_est_i_2__n dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i \ +# dsack1_int_0_un0_n state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n \ +# CLK_030_i bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \ +# cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n RW_000_i \ +# cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n vma_int_0_un3_n \ +# AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n AS_000_i \ +# ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i ipl_030_0_0__un0_n \ +# N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i ipl_030_0_1__un1_n \ +# sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i ipl_030_0_2__un3_n sm_amiga_i_0__n \ +# ipl_030_0_2__un1_n sm_amiga_i_1__n ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n \ +# a_i_31__n cpu_estse_2_un1_n a_i_28__n cpu_estse_2_un0_n a_i_29__n \ +# as_000_dma_0_un3_n a_i_26__n as_000_dma_0_un1_n a_i_27__n as_000_dma_0_un0_n \ +# a_i_24__n ds_000_dma_0_un3_n a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n \ +# rw_000_dma_0_un3_n CLK_OUT_PRE_i rw_000_dma_0_un1_n CLK_OUT_PRE_50_D_i \ +# rw_000_dma_0_un0_n AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c \ +# clk_030_h_0_un0_n cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n \ +# DS_030_c rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n \ +# as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n \ +# as_030_000_sync_0_un0_n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ @@ -113,280 +117,308 @@ A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \ AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \ -DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \ -a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF \ -inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF A0_c.BLIF inst_VMA_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ -inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF \ -inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF \ -inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF vcc_n_n.BLIF \ -gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ -CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \ -CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ -inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \ -state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF \ -IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF \ -IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF \ -inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF \ -RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \ -fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF \ -state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF \ -state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF \ -cpu_est_3_reg.BLIF N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF \ -N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF \ -state_machine_un8_bgack_030_int_n.BLIF N_160_i.BLIF N_92.BLIF N_154_i.BLIF \ -state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ -N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF CLK_030_H_1_sqmuxa.BLIF \ -cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF \ -state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \ -state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF \ -FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \ -un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF \ -un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF \ -state_machine_un3_clk_030_i_n.BLIF N_94.BLIF \ -state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF \ -state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF \ -state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF \ -state_machine_un3_bgack_030_int_d_i_n.BLIF \ -state_machine_un10_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF \ -UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ -UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \ -state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \ -RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF \ -N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF N_100.BLIF N_95_i.BLIF N_91.BLIF \ -sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF \ -state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF \ -state_machine_uds_000_int_7_n.BLIF sm_amiga_ns_0_0__n.BLIF \ -RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \ -un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF \ -BG_030_c_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ -state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF \ -state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF \ -state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF \ -N_59_0.BLIF N_86.BLIF state_machine_un10_bgack_030_int_0_n.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF \ -state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF \ -N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF \ -N_97.BLIF N_100_i.BLIF N_99.BLIF un1_SM_AMIGA_8_0.BLIF \ -state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF \ -un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ -RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF \ -AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF \ -DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF \ -state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \ -state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF \ -state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF \ -N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \ -AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF \ -state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF \ -state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF \ -un1_as_030_000_sync8.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF \ -un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF \ -state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF \ -N_157.BLIF state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF \ -cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF \ -N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF N_152.BLIF N_220_2.BLIF \ -N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF \ -cpu_est_ns_1__n.BLIF N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF \ -DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF \ -UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF cpu_est_i_2__n.BLIF \ -UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF \ -cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF \ -N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF \ -state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \ -state_machine_un8_bg_030_2_n.BLIF sm_amiga_i_1__n.BLIF \ -state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF \ -state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \ -state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF \ -state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF \ -state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF \ -state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF \ -state_machine_un28_clk_030_5_n.BLIF N_99_i.BLIF \ -state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF \ -state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \ -state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF \ -state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \ -state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF \ -LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF \ -state_machine_un28_clk_000_d1_1_n.BLIF \ -state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \ -state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF \ -sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF \ -RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ -cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF \ -AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF \ -state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF CLK_030_i.BLIF \ -ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ -ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF \ -sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \ -ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \ -ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \ -bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF \ -as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF \ -as_030_000_sync_0_un0_n.BLIF FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF \ -CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF \ -fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF \ -as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF RW_000_c.BLIF \ -dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF \ -dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF \ -vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF \ -avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF \ -bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ -a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF \ -a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ -a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ -a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF \ -rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF \ -as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF \ -ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF \ -ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF \ -clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF \ -a_c_27__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \ -UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ -A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF +DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF amiga_bus_enable_int_0_un3_n.BLIF \ +a_c_16__n.BLIF amiga_bus_enable_int_0_un1_n.BLIF \ +amiga_bus_enable_int_0_un0_n.BLIF a_c_17__n.BLIF bg_000_0_un3_n.BLIF \ +bg_000_0_un1_n.BLIF a_c_18__n.BLIF bg_000_0_un0_n.BLIF \ +inst_BGACK_030_INTreg.BLIF lds_000_int_0_un3_n.BLIF vcc_n_n.BLIF \ +a_c_19__n.BLIF lds_000_int_0_un1_n.BLIF inst_avec_expreg.BLIF \ +lds_000_int_0_un0_n.BLIF inst_VMA_INTreg.BLIF a_c_20__n.BLIF \ +ds_000_enable_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF \ +ds_000_enable_0_un1_n.BLIF inst_CLK_OUT_NEreg.BLIF a_c_21__n.BLIF \ +ds_000_enable_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF uds_000_int_0_un3_n.BLIF \ +inst_BGACK_030_INT_D.BLIF a_c_22__n.BLIF uds_000_int_0_un1_n.BLIF \ +inst_AS_000_DMA.BLIF uds_000_int_0_un0_n.BLIF inst_VPA_D.BLIF a_c_23__n.BLIF \ +inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_OUT_PRE.BLIF a_c_24__n.BLIF \ +inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF a_c_25__n.BLIF \ +inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF a_c_26__n.BLIF \ +inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF a_c_27__n.BLIF inst_CLK_000_NE.BLIF \ +gnd_n_n.BLIF a_c_28__n.BLIF inst_CLK_OUT_PRE_D.BLIF CLK_000_P_SYNC_9_.BLIF \ +a_c_29__n.BLIF CLK_000_N_SYNC_11_.BLIF inst_AS_000_INT.BLIF a_c_30__n.BLIF \ +SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF a_c_31__n.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_0_.BLIF A0_c.BLIF SM_AMIGA_4_.BLIF inst_RW_000_INT.BLIF \ +nEXP_SPACE_c.BLIF inst_DSACK1_INT.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ +BG_030_c.BLIF inst_CLK_030_H.BLIF inst_RW_000_DMA.BLIF BG_000DFFSHreg.BLIF \ +un1_LDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \ +BGACK_000_c.BLIF un1_UDS_000_INT.BLIF inst_UDS_000_INT.BLIF CLK_030_c.BLIF \ +CLK_000_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF CLK_OSZI_c.BLIF \ +SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF CLK_000_N_SYNC_0_.BLIF CLK_OUT_INTreg.BLIF \ +CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \ +IPL_030DFFSH_0_reg.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \ +IPL_030DFFSH_1_reg.BLIF CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF \ +IPL_030DFFSH_2_reg.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \ +ipl_c_0__n.BLIF CLK_000_N_SYNC_10_.BLIF CLK_000_P_SYNC_0_.BLIF ipl_c_1__n.BLIF \ +CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF ipl_c_2__n.BLIF \ +CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF DSACK1_c.BLIF \ +CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF DTACK_c.BLIF \ +CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +un1_as_030.BLIF un19_fpu_cs.BLIF state_machine_un10_bg_030_n.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF RST_c.BLIF SM_AMIGA_2_.BLIF \ +RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \ +DS_000_ENABLE_0_sqmuxa_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF \ +state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un4_clk_000_ne_i_n.BLIF \ +CLK_OUT_PRE_25_0.BLIF state_machine_un6_clk_000_ne_i_n.BLIF N_97_i.BLIF \ +sm_amiga_ns_0_4__n.BLIF N_99_i.BLIF N_98_i.BLIF sm_amiga_ns_0_5__n.BLIF \ +N_86_i.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_167_i.BLIF cpu_est_0_.BLIF N_166_i.BLIF \ +cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_162_i.BLIF \ +cpu_est_3_reg.BLIF N_161_i.BLIF cpu_estse.BLIF N_152_i.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un5_clk_000_d0_i_n.BLIF \ +state_machine_un12_clk_000_d0_0_n.BLIF N_198.BLIF cpu_est_ns_0_1__n.BLIF \ +N_207.BLIF N_156_i.BLIF SM_AMIGA_0_sqmuxa.BLIF N_155_i.BLIF N_89.BLIF \ +N_163_i.BLIF N_90.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF \ +state_machine_un8_bg_030_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +N_91.BLIF N_159_i.BLIF N_92.BLIF N_160_i.BLIF N_87.BLIF cpu_est_ns_0_2__n.BLIF \ +N_94.BLIF state_machine_un10_bgack_030_int_0_n.BLIF N_95.BLIF \ +state_machine_ds_000_dma_3_0_n.BLIF N_96.BLIF \ +state_machine_size_dma_4_0_0__n.BLIF N_100.BLIF \ +state_machine_size_dma_4_0_1__n.BLIF N_101.BLIF CLK_030_H_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_030_H_1_sqmuxa_i.BLIF N_85.BLIF \ +state_machine_clk_030_h_2_f1_0_n.BLIF DSACK1_INT_0_sqmuxa.BLIF \ +un3_dtack_i.BLIF AS_030_000_SYNC_0_sqmuxa.BLIF \ +state_machine_un5_bgack_030_int_d_i_n.BLIF un1_bgack_030_int_d.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ +state_machine_un3_bgack_030_int_d_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF state_machine_rw_000_int_3_0_n.BLIF \ +N_84.BLIF N_66_0.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_91_i.BLIF N_93.BLIF \ +N_93_i.BLIF N_66.BLIF state_machine_rw_000_int_3_n.BLIF AS_030_000_SYNC_i.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_84_0.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF N_167_1.BLIF \ +N_87_0.BLIF state_machine_un10_bgack_030_int_n.BLIF N_85_0.BLIF \ +CLK_030_H_1_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF \ +AS_000_DMA_1_sqmuxa.BLIF N_92_i.BLIF DS_000_DMA_1_sqmuxa.BLIF \ +DS_000_DMA_1_sqmuxa_1.BLIF N_100_i.BLIF \ +state_machine_un24_bgack_030_int_n.BLIF N_101_i.BLIF \ +state_machine_clk_030_h_2_n.BLIF sm_amiga_ns_0_6__n.BLIF \ +state_machine_clk_030_h_2_f1_n.BLIF N_95_i.BLIF \ +state_machine_un31_bgack_030_int_n.BLIF N_96_i.BLIF \ +state_machine_ds_000_dma_3_n.BLIF sm_amiga_ns_0_3__n.BLIF cpu_est_ns_2__n.BLIF \ +N_94_i.BLIF N_160.BLIF sm_amiga_ns_0_2__n.BLIF N_159.BLIF \ +sm_amiga_ns_0_0__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BG_030_c_i.BLIF \ +state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un8_bg_030_i_n.BLIF \ +N_163.BLIF state_machine_un10_bg_030_0_n.BLIF N_155.BLIF LDS_000_INT_i.BLIF \ +N_156.BLIF un1_LDS_000_INT_0.BLIF cpu_est_ns_1__n.BLIF UDS_000_INT_i.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF un1_UDS_000_INT_0.BLIF \ +state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un7_ds_030_i_n.BLIF \ +state_machine_un10_clk_000_d0_n.BLIF A0_c_i.BLIF \ +state_machine_un5_clk_000_d0_n.BLIF size_c_i_1__n.BLIF N_161.BLIF \ +un1_bgack_030_int_d_0_1.BLIF state_machine_un10_clk_000_ne_1_n.BLIF \ +N_84_0_1.BLIF N_162.BLIF N_84_0_2.BLIF state_machine_un5_clk_000_d0_2_n.BLIF \ +un3_dtack_i_1.BLIF N_166.BLIF cpu_est_ns_0_1_2__n.BLIF N_167.BLIF N_198_1.BLIF \ +DSACK1_INT_1_sqmuxa.BLIF N_198_2.BLIF state_machine_un6_bgack_000_n.BLIF \ +N_207_1.BLIF DS_000_ENABLE_0_sqmuxa.BLIF N_207_2.BLIF \ +state_machine_un10_clk_000_ne_n.BLIF N_207_3.BLIF N_86.BLIF N_207_4.BLIF \ +state_machine_un6_clk_000_ne_n.BLIF N_207_5.BLIF N_98.BLIF N_207_6.BLIF \ +N_99.BLIF state_machine_un7_ds_030_i_1_n.BLIF N_97.BLIF \ +state_machine_un8_bg_030_1_n.BLIF state_machine_un4_clk_000_ne_n.BLIF \ +state_machine_un8_bg_030_2_n.BLIF un19_fpu_cs_i.BLIF \ +DSACK1_INT_0_sqmuxa_1.BLIF DTACK_i.BLIF AS_030_000_SYNC_0_sqmuxa_1_0.BLIF \ +avec_exp_i.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF CLK_000_NE_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF VPA_D_i.BLIF cpu_est_ns_0_1_1__n.BLIF \ +VMA_INT_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_030_i.BLIF \ +state_machine_un10_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF DSACK1_INT_0_sqmuxa_i.BLIF \ +state_machine_un10_clk_000_d0_3_n.BLIF a_i_16__n.BLIF \ +state_machine_clk_000_n_sync_2_1_0__n.BLIF a_i_18__n.BLIF \ +state_machine_clk_000_n_sync_2_2_0__n.BLIF nEXP_SPACE_i.BLIF \ +state_machine_clk_000_p_sync_3_1_0__n.BLIF RW_i.BLIF N_167_1_0.BLIF \ +CLK_000_D3_i.BLIF un19_fpu_cs_1.BLIF CLK_000_D2_i.BLIF un19_fpu_cs_2.BLIF \ +CLK_000_D0_i.BLIF un19_fpu_cs_3.BLIF cpu_est_i_3__n.BLIF un19_fpu_cs_4.BLIF \ +cpu_est_i_0__n.BLIF un19_fpu_cs_5.BLIF cpu_est_i_1__n.BLIF un19_fpu_cs_6.BLIF \ +state_machine_un10_clk_000_ne_1_i_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF \ +CLK_000_D1_i.BLIF state_machine_un10_clk_000_ne_1_0_n.BLIF \ +state_machine_un5_clk_000_d0_2_i_0_n.BLIF dsack1_int_0_un3_n.BLIF \ +cpu_est_i_2__n.BLIF dsack1_int_0_un1_n.BLIF DS_000_DMA_1_sqmuxa_1_i.BLIF \ +dsack1_int_0_un0_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF \ +bgack_030_int_0_un3_n.BLIF CLK_030_i.BLIF bgack_030_int_0_un1_n.BLIF \ +UDS_000_i.BLIF bgack_030_int_0_un0_n.BLIF LDS_000_i.BLIF \ +cpu_estse_0_un3_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF \ +cpu_estse_0_un1_n.BLIF RW_000_i.BLIF cpu_estse_0_un0_n.BLIF \ +state_machine_un24_bgack_030_int_i_n.BLIF vma_int_0_un3_n.BLIF \ +AS_000_DMA_i.BLIF vma_int_0_un1_n.BLIF BGACK_030_INT_i.BLIF \ +vma_int_0_un0_n.BLIF AS_000_i.BLIF ipl_030_0_0__un3_n.BLIF N_90_i.BLIF \ +ipl_030_0_0__un1_n.BLIF BGACK_030_INT_D_i.BLIF ipl_030_0_0__un0_n.BLIF \ +N_89_i.BLIF ipl_030_0_1__un3_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \ +ipl_030_0_1__un1_n.BLIF sm_amiga_i_7__n.BLIF ipl_030_0_1__un0_n.BLIF \ +CLK_OUT_NE_i.BLIF ipl_030_0_2__un3_n.BLIF sm_amiga_i_0__n.BLIF \ +ipl_030_0_2__un1_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF \ +a_i_30__n.BLIF cpu_estse_2_un3_n.BLIF a_i_31__n.BLIF cpu_estse_2_un1_n.BLIF \ +a_i_28__n.BLIF cpu_estse_2_un0_n.BLIF a_i_29__n.BLIF as_000_dma_0_un3_n.BLIF \ +a_i_26__n.BLIF as_000_dma_0_un1_n.BLIF a_i_27__n.BLIF as_000_dma_0_un0_n.BLIF \ +a_i_24__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un1_n.BLIF \ +RST_i.BLIF ds_000_dma_0_un0_n.BLIF rw_000_dma_0_un3_n.BLIF CLK_OUT_PRE_i.BLIF \ +rw_000_dma_0_un1_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_dma_0_un0_n.BLIF \ +AS_030_c.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un1_n.BLIF AS_000_c.BLIF \ +clk_030_h_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF RW_000_c.BLIF \ +cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF DS_030_c.BLIF \ +rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF UDS_000_c.BLIF \ +rw_000_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF LDS_000_c.BLIF \ +as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF size_c_0__n.BLIF \ +as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF size_c_1__n.BLIF \ +as_030_000_sync_0_un0_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ -cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \ -cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ +cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \ +cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ +SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ +SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D \ +CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D \ +CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D \ +CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D \ +CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D \ +CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \ +SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ -IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP CLK_000_N_SYNC_0_.D \ +CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.D \ +CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.D \ +CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.D \ +CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.D \ +CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D \ +CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D \ +CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D \ +CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.D \ +CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.D \ +CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \ inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \ -inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \ -SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \ -inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \ -inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D inst_DSACK1_INT.C \ -inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ -inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ -inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \ -inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D \ -inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +inst_CLK_OUT_PRE_25.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +inst_DS_000_ENABLE.AR inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_RW_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \ +inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_RW_000_DMA.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ +inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C \ +inst_AMIGA_BUS_ENABLE_INTreg.AP inst_CLK_OUT_NEreg.D inst_CLK_OUT_NEreg.C \ +inst_CLK_OUT_NEreg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ +inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D \ +inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \ +inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR \ +inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \ +inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C \ +inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_000_NE.AR \ inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \ -DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n \ -a_c_30__n a_c_31__n A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n \ -gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \ -ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n \ -AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n \ -state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n N_159_i N_158_i N_149_i \ -N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n \ -N_160_i N_92 N_154_i state_machine_un49_clk_000_d0_n \ -state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i \ -CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ -state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ -state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ -FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ -state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ -state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \ -N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ -state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n \ -N_164_1 state_machine_un3_bgack_030_int_d_i_n \ -state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 \ -UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 \ -N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 \ -N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n \ -N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n \ -sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ -un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ -state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ -state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ -AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ -state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ -state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 \ -un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i \ -un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ -un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ -state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ -state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ -state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ -state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ -AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ -state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ -CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ -un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ -state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ -cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ -cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \ -N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \ -cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 \ -AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \ -UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \ -cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n \ -RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 \ -VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ -AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ -state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ -a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ -a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ -state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ -sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ -state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ -sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ -state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ -state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ -state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ -cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ -state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ -state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ -cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ -UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ -cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ -state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i \ -ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n \ -AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n \ -ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n \ -a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \ -bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n \ -as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ -FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c \ -fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n \ -as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c \ -dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \ -LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n \ -bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n \ -lds_000_int_0_un3_n lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n \ -uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n \ -a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n rw_000_int_0_un0_n \ -as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n \ -ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \ -clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n \ -a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \ +DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ amiga_bus_enable_int_0_un3_n \ +a_c_16__n amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_17__n \ +bg_000_0_un3_n bg_000_0_un1_n a_c_18__n bg_000_0_un0_n lds_000_int_0_un3_n \ +vcc_n_n a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n \ +ds_000_enable_0_un3_n ds_000_enable_0_un1_n a_c_21__n ds_000_enable_0_un0_n \ +uds_000_int_0_un3_n a_c_22__n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n gnd_n_n a_c_28__n a_c_29__n \ +a_c_30__n a_c_31__n A0_c nEXP_SPACE_c state_machine_un3_clk_out_pre_50_n \ +BG_030_c un1_LDS_000_INT BGACK_000_c un1_UDS_000_INT CLK_030_c CLK_000_c \ +CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c DTACK_c \ +un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \ +RST_c RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i \ +DS_000_ENABLE_0_sqmuxa_i un1_SM_AMIGA_0_sqmuxa_1_i \ +state_machine_un10_clk_000_ne_i_n state_machine_un4_clk_000_ne_i_n \ +state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i \ +sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n \ +state_machine_un6_bgack_000_0_n N_167_i N_166_i AMIGA_BUS_DATA_DIR_c_0 N_162_i \ +N_161_i N_152_i state_machine_un10_clk_000_d0_i_n \ +state_machine_un5_clk_000_d0_i_n state_machine_un12_clk_000_d0_0_n N_198 \ +cpu_est_ns_0_1__n N_207 N_156_i SM_AMIGA_0_sqmuxa N_155_i N_89 N_163_i N_90 \ +state_machine_un5_clk_000_d0_1_i_n state_machine_un8_bg_030_n \ +state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 N_160_i N_87 \ +cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 \ +state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 \ +state_machine_size_dma_4_0_1__n N_101 CLK_030_H_i \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_030_H_1_sqmuxa_i N_85 \ +state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa un3_dtack_i \ +AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n \ +un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ +state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 N_93_i N_66 \ +state_machine_rw_000_int_3_n AS_030_000_SYNC_i \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa_i AS_030_000_SYNC_0_sqmuxa_1 \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \ +state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n \ +un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \ +CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa \ +N_92_i DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i \ +state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \ +sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i \ +state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n \ +sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 \ +sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i \ +state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 \ +state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 \ +cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n \ +un1_UDS_000_INT_0 state_machine_un6_clk_000_p_sync_n \ +state_machine_un7_ds_030_i_n state_machine_un10_clk_000_d0_n A0_c_i \ +state_machine_un5_clk_000_d0_n size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 \ +state_machine_un10_clk_000_ne_1_n N_84_0_1 N_162 N_84_0_2 \ +state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 cpu_est_ns_0_1_2__n N_167 \ +N_198_1 DSACK1_INT_1_sqmuxa N_198_2 state_machine_un6_bgack_000_n N_207_1 \ +DS_000_ENABLE_0_sqmuxa N_207_2 state_machine_un10_clk_000_ne_n N_207_3 N_86 \ +N_207_4 state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \ +state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n \ +state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i \ +DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \ +AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 \ +VPA_D_i cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i \ +state_machine_un10_clk_000_d0_1_n a_i_19__n \ +state_machine_un10_clk_000_d0_2_0_n DSACK1_INT_0_sqmuxa_i \ +state_machine_un10_clk_000_d0_3_n a_i_16__n \ +state_machine_clk_000_n_sync_2_1_0__n a_i_18__n \ +state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i \ +state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i \ +un19_fpu_cs_1 CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 \ +cpu_est_i_3__n un19_fpu_cs_4 cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n \ +un19_fpu_cs_6 state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 \ +CLK_000_D1_i state_machine_un10_clk_000_ne_1_0_n \ +state_machine_un5_clk_000_d0_2_i_0_n dsack1_int_0_un3_n cpu_est_i_2__n \ +dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i dsack1_int_0_un0_n \ +state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n CLK_030_i \ +bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \ +cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n \ +RW_000_i cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n \ +vma_int_0_un3_n AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n \ +AS_000_i ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i \ +ipl_030_0_0__un0_n N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i \ +ipl_030_0_1__un1_n sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i \ +ipl_030_0_2__un3_n sm_amiga_i_0__n ipl_030_0_2__un1_n sm_amiga_i_1__n \ +ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n a_i_31__n cpu_estse_2_un1_n \ +a_i_28__n cpu_estse_2_un0_n a_i_29__n as_000_dma_0_un3_n a_i_26__n \ +as_000_dma_0_un1_n a_i_27__n as_000_dma_0_un0_n a_i_24__n ds_000_dma_0_un3_n \ +a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n rw_000_dma_0_un3_n \ +CLK_OUT_PRE_i rw_000_dma_0_un1_n CLK_OUT_PRE_50_D_i rw_000_dma_0_un0_n \ +AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c clk_030_h_0_un0_n \ +cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n DS_030_c \ +rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n \ +as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n \ +as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n \ +as_030_000_sync_0_un0_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \ LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE \ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D @@ -398,6 +430,26 @@ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D +0 1 +.names N_91_i.BLIF N_93_i.BLIF SM_AMIGA_6_.D +11 1 +.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D +0 1 +.names sm_amiga_ns_0_3__n.BLIF SM_AMIGA_4_.D +0 1 +.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D +0 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF N_92_i.BLIF SM_AMIGA_0_.D +11 1 +.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D +0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -407,21 +459,11 @@ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D -0 1 -.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D +.names state_machine_clk_000_n_sync_2_1_0__n.BLIF \ +state_machine_clk_000_n_sync_2_2_0__n.BLIF CLK_000_N_SYNC_0_.D 11 1 -.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D -11 1 -.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D -11 1 -.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D -0 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D -11 1 -.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D +.names state_machine_clk_000_p_sync_3_1_0__n.BLIF \ +state_machine_un6_clk_000_p_sync_n.BLIF CLK_000_P_SYNC_0_.D 11 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 @@ -430,716 +472,61 @@ CIIN.OE CLK_OUT_PRE_25_0 cpu_estse inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D -0 1 -.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D -0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D -1- 1 --1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D 1- 1 -1 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D 1- 1 -1 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D +1- 1 +-1 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +1- 1 +-1 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF \ +inst_DS_000_ENABLE.D +1- 1 +-1 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D +1- 1 +-1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D +1- 1 +-1 1 +.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +11 1 +.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D +1- 1 +-1 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF inst_RW_000_DMA.D +1- 1 +-1 1 .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D 1- 1 -1 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D 1- 1 -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +.names amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF \ +inst_AMIGA_BUS_ENABLE_INTreg.D 1- 1 -1 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D -1- 1 --1 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D -1- 1 --1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D -1- 1 --1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D -1- 1 --1 1 -.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_i.BLIF inst_CLK_OUT_NEreg.D 11 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names vcc_n_n - 1 -.names gnd_n_n -.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \ -state_machine_un3_clk_out_pre_50_n -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n -0 1 -.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF \ -state_machine_un6_bgack_000_0_n -11 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names N_159.BLIF N_159_i -0 1 -.names N_158.BLIF N_158_i -0 1 -.names N_158_i.BLIF N_159_i.BLIF N_149_i -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i -11 1 -.names N_153.BLIF N_153_i -0 1 -.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -AS_000_DMA_0_sqmuxa -11 1 -.names N_152.BLIF N_152_i -0 1 -.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \ -state_machine_un8_bgack_030_int_n -11 1 -.names N_160.BLIF N_160_i -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92 -11 1 -.names N_154.BLIF N_154_i -0 1 -.names state_machine_un49_clk_000_d0_1_n.BLIF \ -state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n -11 1 -.names state_machine_un10_clk_000_d0_2_n.BLIF \ -state_machine_un10_clk_000_d0_2_i_n -0 1 -.names N_210_1.BLIF N_210_2.BLIF N_210 -11 1 -.names N_156.BLIF N_156_i -0 1 -.names N_220_5.BLIF N_220_6.BLIF N_220 -11 1 -.names N_157.BLIF N_157_i -0 1 -.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa -11 1 -.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ -cpu_est_ns_0_2__n -11 1 -.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -AS_000_DMA_1_sqmuxa -11 1 -.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n -0 1 -.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ -DS_000_DMA_1_sqmuxa -11 1 -.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ -state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n -11 1 -.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n -11 1 -.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i -0 1 -.names state_machine_clk_030_h_2_f1_n.BLIF \ -state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n -11 1 -.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF \ -un1_as_030_000_sync8_1_0 -11 1 -.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n -0 1 -.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i -0 1 -.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n -0 1 -.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF \ -un1_as_030_000_sync8_0 -11 1 -.names N_87_0.BLIF N_87 -0 1 -.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0 -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93 -11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n -11 1 -.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94 -11 1 -.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n -0 1 -.names N_84.BLIF SM_AMIGA_7_.BLIF N_88 -11 1 -.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n -0 1 -.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90 -11 1 -.names state_machine_un51_clk_000_d0_i_n.BLIF \ -state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1 -11 1 -.names state_machine_un3_bgack_030_int_d_n.BLIF \ -state_machine_un3_bgack_030_int_d_i_n -0 1 -.names state_machine_un10_bgack_030_int_0_n.BLIF \ -state_machine_un10_bgack_030_int_n -0 1 -.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ -un1_bgack_030_int_d_0 -11 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ -UDS_000_INT_0_sqmuxa_1 -11 1 -.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i -0 1 -.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ -UDS_000_INT_0_sqmuxa -11 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i -0 1 -.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0 -11 1 -.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164 -11 1 -.names N_101.BLIF N_101_i -0 1 -.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m -11 1 -.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181 -11 1 -.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0 -11 1 -.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m -11 1 -.names N_97.BLIF N_97_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163 -11 1 -.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8 -0 1 -.names N_96.BLIF N_96_i -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100 -11 1 -.names N_95.BLIF N_95_i -0 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91 -11 1 -.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n -11 1 -.names N_88.BLIF N_88_i -0 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names N_89.BLIF N_89_i -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 -.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1 -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i -0 1 -.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2 -11 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i -0 1 -.names N_59_0.BLIF N_59 -0 1 -.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 -11 1 -.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ -un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa -0 1 -.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \ -state_machine_un10_bg_030_0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \ -state_machine_un3_bgack_030_int_d_n -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -state_machine_un5_bgack_030_int_d_i_n -11 1 -.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ -AMIGA_BUS_ENABLE_INT_3_sqmuxa -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0 -11 1 -.names N_86_0.BLIF N_86 -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 -11 1 -.names N_181.BLIF N_181_i -0 1 -.names N_84_0.BLIF N_84 -0 1 -.names A0_c.BLIF A0_c_i -0 1 -.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 -11 1 -.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n -11 1 -.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ -state_machine_un8_bg_030_n -11 1 -.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF \ -state_machine_lds_000_int_7_0_n -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89 -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 -11 1 -.names N_91.BLIF N_91_i -0 1 -.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97 -11 1 -.names N_100.BLIF N_100_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99 -11 1 -.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0 -11 1 -.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF \ -state_machine_un28_clk_000_d1_n -11 1 -.names N_164.BLIF N_164_i -0 1 -.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101 -11 1 -.names N_163.BLIF N_163_i -0 1 -.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12 -0 1 -.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa -11 1 -.names RW_000_i_m.BLIF RW_000_i_m_i -0 1 -.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1 -0 1 -.names RW_li_m.BLIF RW_li_m_i -0 1 -.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa -11 1 -.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n -11 1 -.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \ -state_machine_un10_clk_000_d0_n -11 1 -.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF \ -state_machine_un25_clk_000_d0_i_n -11 1 -.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n -0 1 -.names N_90.BLIF N_90_i -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n -11 1 -.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF \ -state_machine_un57_clk_000_d0_n -11 1 -.names N_93.BLIF N_93_i -0 1 -.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2 -11 1 -.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n -11 1 -.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF \ -AS_030_000_SYNC_0_sqmuxa -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0 -11 1 -.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n -0 1 -.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_ds_000_dma_3_0_n -11 1 -.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa -11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF \ -state_machine_un28_clk_030_n -11 1 -.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i -0 1 -.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8 -0 1 -.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \ -state_machine_clk_030_h_2_f1_0_n -11 1 -.names N_150_i.BLIF N_150 -0 1 -.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i -11 1 -.names state_machine_un5_clk_000_d0_1_n.BLIF \ -state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n -11 1 -.names N_92.BLIF N_92_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n -11 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157 -11 1 -.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n -11 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156 -11 1 -.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152 -11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2 -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3 -11 1 -.names N_150.BLIF cpu_est_2_.BLIF N_158 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4 -11 1 -.names N_160.BLIF cpu_est_i_3__n.BLIF N_159 -11 1 -.names N_220_1.BLIF N_220_2.BLIF N_220_5 -11 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n -0 1 -.names N_220_3.BLIF N_220_4.BLIF N_220_6 -11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ -DS_000_DMA_1_sqmuxa_1 -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_164_1.BLIF RW_c.BLIF N_164_1_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 -11 1 -.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names state_machine_un3_bgack_030_int_d_i_n.BLIF \ -AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n -11 1 -.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \ -state_machine_un49_clk_000_d0_1_n -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1 -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF \ -AS_030_000_SYNC_0_sqmuxa_2_0 -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n -11 1 -.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n -0 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF \ -state_machine_un28_clk_030_4_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF \ -state_machine_un28_clk_030_5_n -11 1 -.names N_99.BLIF N_99_i -0 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \ -state_machine_un10_clk_000_d0_1_n -11 1 -.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i -0 1 -.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \ -state_machine_un10_clk_000_d0_2_0_n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names state_machine_un10_clk_000_d0_1_n.BLIF \ -state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n -11 1 -.names UDS_000_c.BLIF UDS_000_i -0 1 -.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i -0 1 -.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF \ -state_machine_un28_clk_000_d1_1_n -11 1 -.names state_machine_un8_bgack_030_int_n.BLIF \ -state_machine_un8_bgack_030_int_i_n -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n -0 1 -.names state_machine_un31_bgack_030_int_n.BLIF \ -state_machine_un31_bgack_030_int_i_n -0 1 -.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ -cpu_estse_1_un1_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ -cpu_estse_0_un1_n -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n -11 1 -.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n -11 1 -.names state_machine_un24_bgack_030_int_n.BLIF \ -state_machine_un24_bgack_030_int_i_n -0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ -bgack_030_int_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n -0 1 -.names RST_c.BLIF RST_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ -as_030_000_sync_0_un1_n -11 1 -.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n -0 1 -.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i -0 1 -.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n -11 1 -.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n -11 1 -.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n -0 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n -11 1 -.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ -state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un3_n 0 1 -.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ -avec_exp_0_un1_n +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un1_n 11 1 -.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n +.names un1_bgack_030_int_d.BLIF amiga_bus_enable_int_0_un3_n.BLIF \ +amiga_bus_enable_int_0_un0_n 11 1 .names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n 0 1 @@ -1147,47 +534,683 @@ avec_exp_0_un1_n 11 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names un1_AS_030_2.BLIF lds_000_int_0_un3_n +.names DS_030_c.BLIF lds_000_int_0_un3_n 0 1 -.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n +.names vcc_n_n + 1 +.names inst_LDS_000_INT.BLIF DS_030_c.BLIF lds_000_int_0_un1_n 11 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \ +.names state_machine_un7_ds_030_i_n.BLIF lds_000_int_0_un3_n.BLIF \ lds_000_int_0_un0_n 11 1 -.names un1_AS_030_2.BLIF uds_000_int_0_un3_n +.names un1_as_030.BLIF ds_000_enable_0_un3_n 0 1 -.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n +.names inst_DS_000_ENABLE.BLIF un1_as_030.BLIF ds_000_enable_0_un1_n 11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n 11 1 -.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +.names DS_030_c.BLIF uds_000_int_0_un3_n 0 1 -.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +.names inst_UDS_000_INT.BLIF DS_030_c.BLIF uds_000_int_0_un1_n 11 1 -.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF \ -rw_000_int_0_un0_n +.names A0_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 +.names gnd_n_n +.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \ +state_machine_un3_clk_out_pre_50_n +11 1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT +0 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names AS_030_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_as_030 +11 1 +.names un19_fpu_cs_5.BLIF un19_fpu_cs_6.BLIF un19_fpu_cs +11 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names SM_AMIGA_0_sqmuxa.BLIF SM_AMIGA_0_sqmuxa_i +0 1 +.names DS_000_ENABLE_0_sqmuxa.BLIF DS_000_ENABLE_0_sqmuxa_i +0 1 +.names DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1_i +11 1 +.names state_machine_un10_clk_000_ne_n.BLIF state_machine_un10_clk_000_ne_i_n +0 1 +.names state_machine_un4_clk_000_ne_n.BLIF state_machine_un4_clk_000_ne_i_n +0 1 +.names state_machine_un4_clk_000_ne_i_n.BLIF \ +state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_i_n +11 1 +.names N_97.BLIF N_97_i +0 1 +.names N_97_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF sm_amiga_ns_0_4__n +11 1 +.names N_99.BLIF N_99_i +0 1 +.names N_98.BLIF N_98_i +0 1 +.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names inst_CLK_000_NE.BLIF state_machine_un6_clk_000_ne_n.BLIF N_86_i +11 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF \ +state_machine_un6_clk_000_p_sync_i_n +0 1 +.names BGACK_000_c.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF \ +state_machine_un6_bgack_000_0_n +11 1 +.names N_167.BLIF N_167_i +0 1 +.names N_166.BLIF N_166_i +0 1 +.names N_166_i.BLIF N_167_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_162.BLIF N_162_i +0 1 +.names N_161.BLIF N_161_i +0 1 +.names N_161_i.BLIF N_162_i.BLIF N_152_i +11 1 +.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n +0 1 +.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_n +0 1 +.names state_machine_un5_clk_000_d0_i_n.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n +11 1 +.names N_198_1.BLIF N_198_2.BLIF N_198 +11 1 +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n +11 1 +.names N_207_5.BLIF N_207_6.BLIF N_207 +11 1 +.names N_156.BLIF N_156_i +0 1 +.names SM_AMIGA_4_.BLIF inst_avec_expreg.BLIF SM_AMIGA_0_sqmuxa +11 1 +.names N_155.BLIF N_155_i +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_89 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names SM_AMIGA_6_.BLIF inst_avec_expreg.BLIF N_90 +11 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF \ +state_machine_un5_clk_000_d0_1_i_n +0 1 +.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ +state_machine_un8_bg_030_n +11 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF \ +state_machine_un10_clk_000_d0_2_i_n +0 1 +.names N_84.BLIF SM_AMIGA_7_.BLIF N_91 +11 1 +.names N_159.BLIF N_159_i +0 1 +.names SM_AMIGA_0_.BLIF inst_avec_expreg.BLIF N_92 +11 1 +.names N_160.BLIF N_160_i +0 1 +.names N_87_0.BLIF N_87 +0 1 +.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +cpu_est_ns_0_2__n +11 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_94 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n +11 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_5_.BLIF N_95 +11 1 +.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_ds_000_dma_3_0_n +11 1 +.names SM_AMIGA_4_.BLIF avec_exp_i.BLIF N_96 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n +11 1 +.names SM_AMIGA_2_.BLIF inst_avec_expreg.BLIF N_100 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n +11 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_101 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_85.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +11 1 +.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i +0 1 +.names N_85_0.BLIF N_85 +0 1 +.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \ +state_machine_clk_030_h_2_f1_0_n +11 1 +.names DSACK1_INT_0_sqmuxa_1.BLIF SM_AMIGA_1_.BLIF DSACK1_INT_0_sqmuxa +11 1 +.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1_0.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF \ +AS_030_000_SYNC_0_sqmuxa +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +state_machine_un5_bgack_030_int_d_i_n +11 1 +.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d +0 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \ +state_machine_un3_bgack_030_int_d_n +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i +0 1 +.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 +11 1 +.names N_89_i.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa +11 1 +.names RW_i.BLIF sm_amiga_i_7__n.BLIF state_machine_rw_000_int_3_0_n +11 1 +.names N_84_0.BLIF N_84 +0 1 +.names N_90_i.BLIF sm_amiga_i_7__n.BLIF N_66_0 +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF \ +state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa +11 1 +.names N_91.BLIF N_91_i +0 1 +.names N_87.BLIF sm_amiga_i_7__n.BLIF N_93 +11 1 +.names N_93.BLIF N_93_i +0 1 +.names N_66_0.BLIF N_66 +0 1 +.names state_machine_rw_000_int_3_0_n.BLIF state_machine_rw_000_int_3_n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa +0 1 +.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0 +11 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 +11 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i +0 1 +.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1 +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i +0 1 +.names AS_030_i.BLIF N_90_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names state_machine_un3_bgack_030_int_d_n.BLIF \ +state_machine_un3_bgack_030_int_d_i_n +0 1 +.names N_167_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_n +11 1 +.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +un1_bgack_030_int_d_0 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_167_1 +11 1 +.names SM_AMIGA_6_.BLIF avec_exp_i.BLIF N_87_0 +11 1 +.names state_machine_un10_bgack_030_int_0_n.BLIF \ +state_machine_un10_bgack_030_int_n +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_85_0 +11 1 +.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i +0 1 +.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +AS_000_DMA_1_sqmuxa +11 1 +.names N_92.BLIF N_92_i +0 1 +.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ +DS_000_DMA_1_sqmuxa +11 1 +.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +DS_000_DMA_1_sqmuxa_1 +11 1 +.names N_100.BLIF N_100_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n +11 1 +.names N_101.BLIF N_101_i +0 1 +.names state_machine_clk_030_h_2_f1_n.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n +11 1 +.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_6__n +11 1 +.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n +0 1 +.names N_95.BLIF N_95_i +0 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n +11 1 +.names N_96.BLIF N_96_i +0 1 +.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n +0 1 +.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_3__n +11 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_160 +11 1 +.names N_90_i.BLIF N_94_i.BLIF sm_amiga_ns_0_2__n +11 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_159 +11 1 +.names N_91_i.BLIF N_92_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_1_n +11 1 +.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_163 +11 1 +.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \ +state_machine_un10_bg_030_0_n +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_155 +11 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_156 +11 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +11 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n +0 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF \ +state_machine_un6_clk_000_p_sync_n +11 1 +.names state_machine_un7_ds_030_i_1_n.BLIF size_c_0__n.BLIF \ +state_machine_un7_ds_030_i_n +11 1 +.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un10_clk_000_d0_n +11 1 +.names A0_c.BLIF A0_c_i +0 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF \ +state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names cpu_est_2_.BLIF state_machine_un10_clk_000_ne_1_i_n.BLIF N_161 +11 1 +.names state_machine_un3_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF \ +state_machine_un10_clk_000_ne_1_n +11 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_D1_i.BLIF N_84_0_1 +11 1 +.names N_163.BLIF cpu_est_i_3__n.BLIF N_162 +11 1 +.names inst_CLK_000_D2.BLIF nEXP_SPACE_c.BLIF N_84_0_2 +11 1 +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_2_n +11 1 +.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_166 +11 1 +.names N_160_i.BLIF N_159_i.BLIF cpu_est_ns_0_1_2__n +11 1 +.names N_167_1_0.BLIF nEXP_SPACE_i.BLIF N_167 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_198_1 +11 1 +.names AS_030_i.BLIF DSACK1_INT_0_sqmuxa_i.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_198_2 +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_207_1 +11 1 +.names DS_000_ENABLE_0_sqmuxa_1.BLIF inst_avec_expreg.BLIF \ +DS_000_ENABLE_0_sqmuxa +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_207_2 +11 1 +.names state_machine_un10_clk_000_ne_1_0_n.BLIF VPA_D_i.BLIF \ +state_machine_un10_clk_000_ne_n +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_207_3 +11 1 +.names N_86_i.BLIF N_86 +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_207_4 +11 1 +.names state_machine_un6_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_n +0 1 +.names N_207_1.BLIF N_207_2.BLIF N_207_5 +11 1 +.names SM_AMIGA_2_.BLIF avec_exp_i.BLIF N_98 +11 1 +.names N_207_3.BLIF N_207_4.BLIF N_207_6 +11 1 +.names N_86_i.BLIF SM_AMIGA_3_.BLIF N_99 +11 1 +.names size_c_i_1__n.BLIF A0_c_i.BLIF state_machine_un7_ds_030_i_1_n +11 1 +.names N_86.BLIF SM_AMIGA_3_.BLIF N_97 +11 1 +.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n +11 1 +.names DTACK_i.BLIF inst_VPA_D.BLIF state_machine_un4_clk_000_ne_n +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n +11 1 +.names un19_fpu_cs.BLIF un19_fpu_cs_i +0 1 +.names inst_CLK_000_D1.BLIF CLK_OUT_NE_i.BLIF DSACK1_INT_0_sqmuxa_1 +11 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1_0 +11 1 +.names inst_avec_expreg.BLIF avec_exp_i +0 1 +.names nEXP_SPACE_c.BLIF un19_fpu_cs_i.BLIF AS_030_000_SYNC_0_sqmuxa_2 +11 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_155_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_1__n +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_163_i.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF \ +cpu_est_ns_0_2_1__n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \ +state_machine_un10_clk_000_d0_1_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n +11 1 +.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i +0 1 +.names state_machine_un10_clk_000_d0_1_n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \ +state_machine_clk_000_n_sync_2_1_0__n +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF \ +state_machine_clk_000_n_sync_2_2_0__n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names CLK_000_D2_i.BLIF CLK_000_D3_i.BLIF \ +state_machine_clk_000_p_sync_3_1_0__n +11 1 +.names RW_c.BLIF RW_i +0 1 +.names N_167_1.BLIF RW_c.BLIF N_167_1_0 +11 1 +.names inst_CLK_000_D3.BLIF CLK_000_D3_i +0 1 +.names AS_030_i.BLIF a_c_17__n.BLIF un19_fpu_cs_1 +11 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names a_i_16__n.BLIF a_i_18__n.BLIF un19_fpu_cs_2 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names a_i_19__n.BLIF BGACK_000_c.BLIF un19_fpu_cs_3 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF un19_fpu_cs_4 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names un19_fpu_cs_1.BLIF un19_fpu_cs_2.BLIF un19_fpu_cs_5 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names un19_fpu_cs_3.BLIF un19_fpu_cs_4.BLIF un19_fpu_cs_6 +11 1 +.names state_machine_un10_clk_000_ne_1_n.BLIF \ +state_machine_un10_clk_000_ne_1_i_n +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa_1 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names state_machine_un10_clk_000_ne_1_n.BLIF VMA_INT_i.BLIF \ +state_machine_un10_clk_000_ne_1_0_n +11 1 +.names state_machine_un5_clk_000_d0_2_n.BLIF \ +state_machine_un5_clk_000_d0_2_i_0_n +0 1 +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +11 1 +.names DS_000_DMA_1_sqmuxa_1.BLIF DS_000_DMA_1_sqmuxa_1_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_i_n +0 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ +bgack_030_int_0_un1_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names inst_avec_expreg.BLIF cpu_estse_0_un3_n +0 1 +.names state_machine_un31_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n +0 1 +.names cpu_est_ns_1__n.BLIF inst_avec_expreg.BLIF cpu_estse_0_un1_n +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names state_machine_un24_bgack_030_int_n.BLIF \ +state_machine_un24_bgack_030_int_i_n +0 1 +.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names state_machine_un5_clk_000_d0_2_i_0_n.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_90.BLIF N_90_i +0 1 +.names ipl_c_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \ +ipl_030_0_0__un1_n +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_89.BLIF N_89_i +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un3_n +0 1 +.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i +0 1 +.names ipl_c_1__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \ +ipl_030_0_1__un1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names inst_CLK_OUT_NEreg.BLIF CLK_OUT_NE_i +0 1 +.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un3_n +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names ipl_c_2__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \ +ipl_030_0_2__un1_n +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names inst_avec_expreg.BLIF cpu_estse_2_un3_n +0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names N_152_i.BLIF inst_avec_expreg.BLIF cpu_estse_2_un1_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 .names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n 0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \ as_000_dma_0_un0_n 11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 .names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n 0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 .names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 +.names RST_c.BLIF RST_i +0 1 .names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \ ds_000_dma_0_un0_n 11 1 +.names AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i +0 1 +.names inst_RW_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un1_n +11 1 +.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i +0 1 +.names DS_000_DMA_1_sqmuxa_1_i.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 .names RST_c.BLIF clk_030_h_0_un3_n 0 1 .names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n 11 1 .names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n 11 1 +.names inst_avec_expreg.BLIF cpu_estse_1_un3_n +0 1 +.names cpu_est_ns_2__n.BLIF inst_avec_expreg.BLIF cpu_estse_1_un1_n +11 1 +.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names N_66.BLIF rw_000_int_0_un3_n +0 1 +.names state_machine_rw_000_int_3_n.BLIF N_66.BLIF rw_000_int_0_un1_n +11 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names N_90_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un3_n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF \ +as_030_000_sync_0_un1_n +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -1206,7 +1229,7 @@ ds_000_dma_0_un0_n .names CLK_OUT_INTreg.BLIF CLK_EXP 1 1 0 0 -.names inst_FPU_CS_INTreg.BLIF FPU_CS +.names un19_fpu_cs_i.BLIF FPU_CS 1 1 0 0 .names vcc_n_n.BLIF AVEC @@ -1224,16 +1247,16 @@ ds_000_dma_0_un0_n .names RESETDFFRHreg.BLIF RESET 1 1 0 0 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE +.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE 1 1 0 0 .names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR 1 1 0 0 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +.names inst_CLK_OUT_NEreg.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_210.BLIF CIIN +.names N_198.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1242,6 +1265,15 @@ ds_000_dma_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names cpu_estse.BLIF cpu_est_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +0 0 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 @@ -1260,33 +1292,6 @@ ds_000_dma_0_un0_n .names RST_i.BLIF cpu_est_3_reg.AR 1 1 0 0 -.names cpu_estse.BLIF cpu_est_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -0 0 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 0 0 @@ -1335,6 +1340,228 @@ ds_000_dma_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_2_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_3_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_4_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_5_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_6_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_7_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_8_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_9_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +0 0 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_0_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_1_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_2_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_3_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_4_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_5_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_6_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_7_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_8_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_9_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_10_.AR +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_N_SYNC_11_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_0_.AR +1 1 +0 0 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_000_P_SYNC_1_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 @@ -1356,16 +1583,16 @@ ds_000_dma_0_un0_n .names RST_i.BLIF inst_CLK_OUT_PRE_25.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names RST_i.BLIF SIZE_DMA_0_.AP +.names RST_i.BLIF inst_AS_030_000_SYNC.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C 1 1 0 0 -.names RST_i.BLIF SIZE_DMA_1_.AP +.names RST_i.BLIF BG_000DFFSHreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INT.C @@ -1374,22 +1601,49 @@ ds_000_dma_0_un0_n .names RST_i.BLIF inst_LDS_000_INT.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP +.names RST_i.BLIF inst_AS_000_INT.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_avec_expreg.C +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names RST_i.BLIF inst_avec_expreg.AP +.names RST_i.BLIF inst_DS_000_ENABLE.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C 1 1 0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_UDS_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_RW_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_A0_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_RW_000_DMA.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C @@ -1404,52 +1658,16 @@ ds_000_dma_0_un0_n .names RST_i.BLIF inst_AS_000_DMA.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C 1 1 0 0 -.names RST_i.BLIF inst_AS_000_INT.AP +.names RST_i.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +.names CLK_OSZI_c.BLIF inst_CLK_OUT_NEreg.C 1 1 0 0 -.names RST_i.BLIF inst_DSACK1_INT.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 -.names RST_i.BLIF inst_RW_000_INT.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -0 0 -.names RST_i.BLIF inst_UDS_000_INT.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -0 0 -.names RST_i.BLIF inst_A0_DMA.AP -1 1 -0 0 -.names DTACK.PIN.BLIF inst_DTACK_D0.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_D0.AP +.names RST_i.BLIF inst_CLK_OUT_NEreg.AR 1 1 0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D @@ -1461,7 +1679,25 @@ ds_000_dma_0_un0_n .names RST_i.BLIF inst_CLK_000_D2.AP 1 1 0 0 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D +.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR +1 1 +0 0 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_000_D3.AP +1 1 +0 0 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C @@ -1497,6 +1733,15 @@ ds_000_dma_0_un0_n .names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR 1 1 0 0 +.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_OUT_PRE_D.AR +1 1 +0 0 .names CLK_000_c.BLIF inst_CLK_000_D0.D 1 1 0 0 @@ -1515,6 +1760,24 @@ ds_000_dma_0_un0_n .names RST_i.BLIF inst_VPA_D.AP 1 1 0 0 +.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_avec_expreg.C +1 1 +0 0 +.names RST_i.BLIF inst_avec_expreg.AR +1 1 +0 0 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +1 1 +0 0 +.names RST_i.BLIF inst_CLK_000_NE.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 0 0 @@ -1545,10 +1808,10 @@ ds_000_dma_0_un0_n .names inst_DS_000_DMA.BLIF DS_030 1 1 0 0 -.names inst_UDS_000_INT.BLIF UDS_000 +.names un1_UDS_000_INT.BLIF UDS_000 1 1 0 0 -.names inst_LDS_000_INT.BLIF LDS_000 +.names un1_LDS_000_INT.BLIF LDS_000 1 1 0 0 .names inst_A0_DMA.BLIF A0 @@ -1560,12 +1823,48 @@ ds_000_dma_0_un0_n .names DSACK1_c.BLIF DTACK 1 1 0 0 -.names inst_RW_000_INT.BLIF RW +.names inst_RW_000_DMA.BLIF RW 1 1 0 0 .names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 +.names A_16_.BLIF a_c_16__n +1 1 +0 0 +.names A_17_.BLIF a_c_17__n +1 1 +0 0 +.names A_18_.BLIF a_c_18__n +1 1 +0 0 +.names A_19_.BLIF a_c_19__n +1 1 +0 0 +.names A_20_.BLIF a_c_20__n +1 1 +0 0 +.names A_21_.BLIF a_c_21__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 +.names A_24_.BLIF a_c_24__n +1 1 +0 0 +.names A_25_.BLIF a_c_25__n +1 1 +0 0 +.names A_26_.BLIF a_c_26__n +1 1 +0 0 +.names A_27_.BLIF a_c_27__n +1 1 +0 0 .names A_28_.BLIF a_c_28__n 1 1 0 0 @@ -1611,6 +1910,9 @@ ds_000_dma_0_un0_n .names DSACK1.PIN.BLIF DSACK1_c 1 1 0 0 +.names DTACK.PIN.BLIF DTACK_c +1 1 +0 0 .names RST.BLIF RST_c 1 1 0 0 @@ -1647,42 +1949,6 @@ ds_000_dma_0_un0_n .names SIZE_1_.PIN.BLIF size_c_1__n 1 1 0 0 -.names A_16_.BLIF a_c_16__n -1 1 -0 0 -.names A_17_.BLIF a_c_17__n -1 1 -0 0 -.names A_18_.BLIF a_c_18__n -1 1 -0 0 -.names A_19_.BLIF a_c_19__n -1 1 -0 0 -.names A_20_.BLIF a_c_20__n -1 1 -0 0 -.names A_21_.BLIF a_c_21__n -1 1 -0 0 -.names A_22_.BLIF a_c_22__n -1 1 -0 0 -.names A_23_.BLIF a_c_23__n -1 1 -0 0 -.names A_24_.BLIF a_c_24__n -1 1 -0 0 -.names A_25_.BLIF a_c_25__n -1 1 -0 0 -.names A_26_.BLIF a_c_26__n -1 1 -0 0 -.names A_27_.BLIF a_c_27__n -1 1 -0 0 .names un3_dtack_i.BLIF AS_030.OE 1 1 0 0 @@ -1719,10 +1985,10 @@ ds_000_dma_0_un0_n .names BGACK_030_INT_i.BLIF RW.OE 1 1 0 0 -.names FPU_CS_INT_i.BLIF BERR.OE +.names un19_fpu_cs.BLIF BERR.OE 1 1 0 0 -.names N_220.BLIF CIIN.OE +.names N_207.BLIF CIIN.OE 1 1 0 0 .names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ @@ -1731,7 +1997,7 @@ CLK_OUT_PRE_25_0 10 1 11 0 00 0 -.names cpu_est_0_.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse +.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_estse 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index db3576b..23f2ffb 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 6 7 23 3 15) + (timeStamp 2014 6 9 10 27 20) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -158,20 +158,14 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) @@ -188,46 +182,102 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) + (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance CLK_OUT_PRE_25 (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance avec_exp (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance DS_000_ENABLE (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance DSACK1_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance RW_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance A0_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance DS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance AS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance AMIGA_BUS_ENABLE_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance DSACK1_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance RW_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance A0_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance DTACK_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance CLK_OUT_NE (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance CLK_000_D2 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance CLK_000_D3 (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance CLK_OUT_INT (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance CLK_000_D1 (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -236,10 +286,16 @@ ) (instance CLK_OUT_PRE_50_D (viewRef prim (cellRef DFFRH (libraryRef mach))) ) + (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance CLK_000_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance VPA_D (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance avec_exp (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance CLK_000_NE (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance RESETDFFRH (viewRef prim (cellRef DFFRH (libraryRef mach))) @@ -303,49 +359,35 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_000_d0_2 "state_machine.un5_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_000_d0 "state_machine.un5_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_CLK_000_P_SYNC_3_0 "state_machine.CLK_000_P_SYNC_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3_0_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_ne_1_0 "state_machine.un10_clk_000_ne_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_ne "state_machine.un10_clk_000_ne") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un10_clk_000_d0_1 "state_machine.un10_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un10_clk_000_d0_2 "state_machine.un10_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un10_clk_000_d0_3 "state_machine.un10_clk_000_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_000_d1_1 "state_machine.un28_clk_000_d1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_000_d1 "state_machine.un28_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un57_clk_000_d0_1 "state_machine.un57_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un57_clk_000_d0 "state_machine.un57_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un49_clk_000_d0_1 "state_machine.un49_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un49_clk_000_d0 "state_machine.un49_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_0_sqmuxa_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030_1 "state_machine.un28_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030_2 "state_machine.un28_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030_3 "state_machine.un28_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030_4 "state_machine.un28_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030_5 "state_machine.un28_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030 "state_machine.un28_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_000_d0_1 "state_machine.un5_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3_0_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_li_m_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_li_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_10_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_10_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_bg_030_1 "state_machine.un8_bg_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_bg_030_2 "state_machine.un8_bg_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_CLK_000_N_SYNC_2_1_0 "state_machine.CLK_000_N_SYNC_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_CLK_000_N_SYNC_2_2_0 "state_machine.CLK_000_N_SYNC_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_CLK_000_N_SYNC_2_0 "state_machine.CLK_000_N_SYNC_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_CLK_000_P_SYNC_3_1_0 "state_machine.CLK_000_P_SYNC_3_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -353,259 +395,174 @@ (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_i_1 "SM_AMIGA_ns_i_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_DS_000_DMA_3_i "state_machine.DS_000_DMA_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_CLK_030_H_2_f1_i "state_machine.CLK_030_H_2_f1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_92_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un7_ds_030_1 "state_machine.un7_ds_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un7_ds_030 "state_machine.un7_ds_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_1 "state_machine.un8_bg_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_2 "state_machine.un8_bg_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_bgack_030_int_d_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bgack_030_int_d (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_int5_0_o4_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_int5_0_o4_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_int5_0_o4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un3_dtack_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un3_dtack (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un25_clk_000_d0_1 "state_machine.un25_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un25_clk_000_d0 "state_machine.un25_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_i "state_machine.LDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_i_0 "state_machine.SIZE_DMA_4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_i_1 "state_machine.SIZE_DMA_4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_8_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_i_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_li_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un25_clk_000_d0_i_0 "state_machine.un25_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un8_bg_030_i "state_machine.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un10_bg_030_i "state_machine.un10_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un10_bgack_030_int_i "state_machine.un10_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_181_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_i "state_machine.UDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un3_clk_030_i_0 "state_machine.un3_clk_030_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un57_clk_000_d0_i "state_machine.un57_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un51_clk_000_d0_i "state_machine.un51_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un53_clk_000_d0_i "state_machine.un53_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un3_bgack_030_int_d_i "state_machine.un3_bgack_030_int_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_RW_000_INT_3_i "state_machine.RW_000_INT_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_6_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_int5_0_o4_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_INT_3_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_4_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_amiga_bus_enable_int5_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_o2_i_3 "cpu_est_ns_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_152_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_160_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_bgack_030_int_d_i "state_machine.un3_bgack_030_int_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_bgack_030_int_d_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_i_1 "SM_AMIGA_ns_i_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_i_7 "SM_AMIGA_ns_i_o3_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_92_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_1_i "state_machine.un5_clk_000_d0_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un10_clk_000_d0_2_i "state_machine.un10_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_157_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_i_2 "cpu_est_ns_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_i "state_machine.un12_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance FPU_CS_INT_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_000_sync8_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_0_sqmuxa_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_000_sync8_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un3_clk_000_d1_i "state_machine.un3_clk_000_d1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_i_1 "cpu_est_ns_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_159_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_158_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a3_1 "cpu_est_ns_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_160_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_i_2 "cpu_est_ns_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_bgack_030_int_i "state_machine.un10_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_3_i "state_machine.DS_000_DMA_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_i_0 "state_machine.SIZE_DMA_4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_i_1 "state_machine.SIZE_DMA_4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_CLK_030_H_2_f1_i "state_machine.CLK_030_H_2_f1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_o3_i_4 "SM_AMIGA_ns_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_p_sync_i "state_machine.un6_clk_000_p_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_166_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_162_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_i "state_machine.un5_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un12_clk_000_d0_i "state_machine.un12_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_i_1 "cpu_est_ns_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SM_AMIGA_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_i_0 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_ne_i "state_machine.un10_clk_000_ne_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un4_clk_000_ne_i "state_machine.un4_clk_000_ne_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_ne_i_0 "state_machine.un6_clk_000_ne_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_4 "SM_AMIGA_ns_a4[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_ne "state_machine.un6_clk_000_ne") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_143 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un4_clk_000_ne "state_machine.un4_clk_000_ne") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un19_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_2_r "cpu_estse_2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_2_m "cpu_estse_2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_estse_1_r "cpu_estse_1.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_1_m "cpu_estse_1.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_1_n "cpu_estse_1.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_1_p "cpu_estse_1.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_estse_0_r "cpu_estse_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_0_m "cpu_estse_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_0_n "cpu_estse_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_0_p "cpu_estse_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance cpu_estse (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_o2_3 "cpu_est_ns_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_3 "cpu_est_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a2_1 "cpu_est_ns_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_a3_0_3 "cpu_est_ns_i_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_a3_3 "cpu_est_ns_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a3_1_2 "cpu_est_ns_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a3_0_2 "cpu_est_ns_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a3_2 "cpu_est_ns_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a3_1_1 "cpu_est_ns_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_a3_0_1 "cpu_est_ns_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un3_clk_030 "state_machine.un3_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_151 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance FPU_CS_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_12 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_000_sync8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_000_sync8_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un28_clk_030_i "state_machine.un28_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_144 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un3_clk_000_d1 "state_machine.un3_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_o3_4 "SM_AMIGA_ns_o3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_0_5 "SM_AMIGA_ns_a4_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance avec_exp_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_5 "SM_AMIGA_ns_a4[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_ne_1 "state_machine.un10_clk_000_ne_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_2 "state_machine.un5_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0 "state_machine.un5_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_D3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_145 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un5_clk_000_d0_i "state_machine.un5_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_0_r "cpu_estse_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_0_m "cpu_estse_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_n "cpu_estse_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_p "cpu_estse_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_2_i "state_machine.un5_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un51_clk_000_d0 "state_machine.un51_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un53_clk_000_d0 "state_machine.un53_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_5 "SM_AMIGA_ns_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_9_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_amiga_bus_enable_int5_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_10_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_4_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename avec_exp_0_r "avec_exp_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename avec_exp_0_m "avec_exp_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename avec_exp_0_n "avec_exp_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename avec_exp_0_p "avec_exp_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un3_bgack_030_int_d "state_machine.un3_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un5_bgack_030_int_d "state_machine.un5_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_3_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0 "SM_AMIGA_ns_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_0 "SM_AMIGA_ns_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un31_bgack_030_int_i "state_machine.un31_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_0 "state_machine.SIZE_DMA_4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un31_bgack_030_int "state_machine.un31_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_152 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_153 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un10_bgack_030_int "state_machine.un10_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_AS_030_2_94 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv "state_machine.RW_000_INT_7_iv") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_155 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_i_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_154 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_8_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_8_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_2 "SM_AMIGA_ns_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_1 "state_machine.SIZE_DMA_4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_bgack_030_int_i "state_machine.un8_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_r "cpu_estse_2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_2_m "cpu_estse_2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_p_sync "state_machine.un6_clk_000_p_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_ne_1_i "state_machine.un10_clk_000_ne_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_a3_3 "cpu_est_ns_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_a3_0_3 "cpu_est_ns_i_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_3 "cpu_est_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -614,37 +571,115 @@ (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename CLK_030_H_0_r "CLK_030_H_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename CLK_030_H_0_m "CLK_030_H_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename CLK_030_H_0_n "CLK_030_H_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename CLK_030_H_0_p "CLK_030_H_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_1 "SM_AMIGA_ns_i_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un49_clk_000_d0_i "state_machine.un49_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_4 "SM_AMIGA_ns_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_4 "SM_AMIGA_ns_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_bgack_030_int "state_machine.un8_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_158 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_156 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un24_bgack_030_int_i "state_machine.un24_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance cpu_estse (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a2_1 "cpu_est_ns_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_1_2 "cpu_est_ns_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_0_2 "cpu_est_ns_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_2 "cpu_est_ns_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_1_1 "cpu_est_ns_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_0_1 "cpu_est_ns_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_1 "cpu_est_ns_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_r "cpu_estse_1.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_1_m "cpu_estse_1.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_n "cpu_estse_1.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_p "cpu_estse_1.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename state_machine_CLK_030_H_2_f0 "state_machine.CLK_030_H_2_f0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_CLK_030_H_2_f1 "state_machine.CLK_030_H_2_f1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_1 "state_machine.SIZE_DMA_4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un31_bgack_030_int_i "state_machine.un31_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_0 "state_machine.SIZE_DMA_4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un31_bgack_030_int "state_machine.un31_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_146 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_147 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_bgack_030_int "state_machine.un10_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un24_bgack_030_int "state_machine.un24_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bgack_030_int_i "state_machine.un8_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_r "AMIGA_BUS_ENABLE_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_m "AMIGA_BUS_ENABLE_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_n "AMIGA_BUS_ENABLE_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_p "AMIGA_BUS_ENABLE_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bgack_030_int "state_machine.un8_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_149 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un24_bgack_030_int_i "state_machine.un24_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_148 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a4_1 "SM_AMIGA_ns_i_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_0 "SM_AMIGA_ns_a4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_RW_000_INT_3 "state_machine.RW_000_INT_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_3_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_bgack_030_int_d "state_machine.un5_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_bgack_030_int_d "state_machine.un3_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_0_6 "SM_AMIGA_ns_a4_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_3 "SM_AMIGA_ns[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_7 "SM_AMIGA_ns_i_o3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_1 "SM_AMIGA_ns_i_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_OUT_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_6_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance un1_UDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SM_AMIGA_0_sqmuxa_0_a4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_2_i_a4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_6_i_a4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_0_0 "SM_AMIGA_ns_a4_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_2 "SM_AMIGA_ns_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_3 "SM_AMIGA_ns_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_0_3 "SM_AMIGA_ns_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a4_6 "SM_AMIGA_ns_a4[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -652,21 +687,35 @@ (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_OUT_PRE_50_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un3_clk_out_pre_50 "state_machine.un3_clk_out_pre_50") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_clk_out_pre_d "state_machine.un3_clk_out_pre_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) - (portRef I0 (instanceRef state_machine_un5_bgack_030_int_d)) - (portRef I0 (instanceRef BGACK_030_INT_i)) (portRef I0 (instanceRef state_machine_un3_bgack_030_int_d)) + (portRef I0 (instanceRef state_machine_un5_bgack_030_int_d)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) + (portRef I0 (instanceRef BGACK_030_INT_i)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_1_0)) (portRef OE (instanceRef AS_000)) (portRef I0 (instanceRef BGACK_030)) (portRef D (instanceRef BGACK_030_INT_D)) @@ -674,16 +723,25 @@ (portRef OE (instanceRef RW_000)) (portRef OE (instanceRef UDS_000)) )) - (net FPU_CS_INT (joined - (portRef Q (instanceRef FPU_CS_INT)) - (portRef I0 (instanceRef FPU_CS_INT_i)) - (portRef I0 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS)) + (net VCC (joined + (portRef I0 (instanceRef AVEC)) + (portRef D (instanceRef RESETDFFRH)) )) (net (rename avec_expZ0 "avec_exp") (joined (portRef Q (instanceRef avec_exp)) - (portRef I0 (instanceRef avec_exp_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_0_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_6_i_a4)) + (portRef I1 (instanceRef SM_AMIGA_0_sqmuxa_0_a4)) + (portRef I1 (instanceRef cpu_estse_1_m)) + (portRef I0 (instanceRef cpu_estse_1_r)) + (portRef I0 (instanceRef cpu_estse)) + (portRef I1 (instanceRef cpu_estse_2_m)) + (portRef I0 (instanceRef cpu_estse_2_r)) + (portRef I1 (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_estse_0_r)) + (portRef I0 (instanceRef avec_exp_i)) + (portRef I1 (instanceRef DS_000_ENABLE_0_sqmuxa)) (portRef I0 (instanceRef AVEC_EXPZ0)) )) (net VMA_INT (joined @@ -692,6 +750,16 @@ (portRef I0 (instanceRef VMA_INT_i)) (portRef I0 (instanceRef VMA)) )) + (net AMIGA_BUS_ENABLE_INT (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_INT)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE)) + )) + (net CLK_OUT_NE (joined + (portRef Q (instanceRef CLK_OUT_NE)) + (portRef I0 (instanceRef CLK_OUT_NE_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) + )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) @@ -699,8 +767,8 @@ )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef state_machine_un5_bgack_030_int_d)) (portRef I0 (instanceRef BGACK_030_INT_D_i)) + (portRef I1 (instanceRef state_machine_un5_bgack_030_int_d)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) @@ -710,37 +778,32 @@ )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) - (portRef I1 (instanceRef state_machine_un51_clk_000_d0)) (portRef I0 (instanceRef VPA_D_i)) + (portRef I1 (instanceRef state_machine_un4_clk_000_ne)) )) (net CLK_OUT_PRE_50_D (joined (portRef Q (instanceRef CLK_OUT_PRE_50_D)) (portRef I0 (instanceRef CLK_OUT_PRE_50_D_i)) )) + (net CLK_OUT_PRE (joined + (portRef Q (instanceRef CLK_OUT_PRE)) + (portRef I0 (instanceRef CLK_OUT_PRE_i)) + (portRef D (instanceRef CLK_OUT_PRE_D)) + )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) - (portRef I0 (instanceRef un1_SM_AMIGA_8_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_0)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) - (portRef I0 (instanceRef state_machine_un3_clk_000_d1)) + (portRef I0 (instanceRef state_machine_un6_clk_000_p_sync)) (portRef I0 (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) (portRef I0 (instanceRef state_machine_un10_clk_000_d0_2)) (portRef D (instanceRef CLK_000_D1)) )) (net CLK_000_D1 (joined (portRef Q (instanceRef CLK_000_D1)) (portRef I0 (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef state_machine_un49_clk_000_d0_1)) + (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_1)) + (portRef I1 (instanceRef state_machine_CLK_000_N_SYNC_2_1_0)) (portRef D (instanceRef CLK_000_D2)) )) - (net DTACK_D0 (joined - (portRef Q (instanceRef DTACK_D0)) - (portRef I0 (instanceRef DTACK_D0_i)) - )) (net CLK_OUT_PRE_50 (joined (portRef Q (instanceRef CLK_OUT_PRE_50)) (portRef I0 (instanceRef state_machine_un3_clk_out_pre_50)) @@ -750,64 +813,84 @@ (net CLK_OUT_PRE_25 (joined (portRef Q (instanceRef CLK_OUT_PRE_25)) (portRef I0 (instanceRef CLK_OUT_PRE_25_0)) - (portRef D (instanceRef CLK_OUT_INT)) + (portRef D (instanceRef CLK_OUT_PRE)) )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef un1_SM_AMIGA_9_i_a2)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) + (net CLK_000_D2 (joined + (portRef Q (instanceRef CLK_000_D2)) + (portRef I0 (instanceRef CLK_000_D2_i)) + (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o4_2)) + (portRef I0 (instanceRef state_machine_CLK_000_N_SYNC_2_2_0)) + (portRef D (instanceRef CLK_000_D3)) )) - (net VCC (joined - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) - (portRef I0 (instanceRef AVEC)) - (portRef D (instanceRef RESETDFFRH)) + (net CLK_000_D3 (joined + (portRef Q (instanceRef CLK_000_D3)) + (portRef I0 (instanceRef CLK_000_D3_i)) + (portRef I1 (instanceRef state_machine_CLK_000_N_SYNC_2_2_0)) + )) + (net CLK_000_NE (joined + (portRef Q (instanceRef CLK_000_NE)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_o3_4)) + (portRef I0 (instanceRef CLK_000_NE_i)) )) (net GND (joined (portRef I0 (instanceRef BERR)) )) + (net CLK_OUT_PRE_D (joined + (portRef Q (instanceRef CLK_OUT_PRE_D)) + (portRef I0 (instanceRef state_machine_un3_clk_out_pre_d)) + (portRef D (instanceRef CLK_OUT_INT)) + )) + (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_9)) + (portRef D (instanceRef avec_exp)) + )) + (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_11)) + (portRef D (instanceRef CLK_000_NE)) + )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) (portRef I0 (instanceRef AS_000_INT_0_m)) (portRef I1 (instanceRef state_machine_un10_clk_000_d0_1)) (portRef I0 (instanceRef AS_000)) )) + (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined + (portRef Q (instanceRef SM_AMIGA_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_0)) + (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_1_0)) + (portRef I0 (instanceRef state_machine_un8_bg_030_2)) + )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_1)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i)) - (portRef I1 (instanceRef RW_li_m)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_2)) + (portRef I0 (instanceRef un1_SM_AMIGA_6_i_a4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_1)) + (portRef I1 (instanceRef DS_000_ENABLE_0_sqmuxa_1)) + )) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_7)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_0_6)) + (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) )) - (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined - (portRef Q (instanceRef SM_AMIGA_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0)) - (portRef I0 (instanceRef SM_AMIGA_i_7)) - (portRef I0 (instanceRef state_machine_un8_bg_030_2)) - (portRef I0 (instanceRef un1_SM_AMIGA_10_i_a3_1)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined + (portRef Q (instanceRef SM_AMIGA_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_0_3)) + (portRef I0 (instanceRef SM_AMIGA_0_sqmuxa_0_a4)) )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW)) + (portRef I0 (instanceRef RW_000_INT_0_n)) (portRef I0 (instanceRef RW_000)) )) - (net UDS_000_INT (joined - (portRef Q (instanceRef UDS_000_INT)) - (portRef I0 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000)) - )) - (net LDS_000_INT (joined - (portRef Q (instanceRef LDS_000_INT)) - (portRef I0 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000)) - )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) (portRef I0 (instanceRef DSACK1_INT_0_m)) @@ -817,9 +900,9 @@ (portRef O (instanceRef state_machine_un3_clk_out_pre_50)) (portRef I1 (instanceRef CLK_OUT_PRE_25_0)) )) - (net CLK_000_D2 (joined - (portRef Q (instanceRef CLK_000_D2)) - (portRef I0 (instanceRef state_machine_un28_clk_000_d1_1)) + (net (rename state_machine_un3_clk_out_pre_d "state_machine.un3_clk_out_pre_d") (joined + (portRef O (instanceRef state_machine_un3_clk_out_pre_d)) + (portRef D (instanceRef CLK_OUT_NE)) )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) @@ -827,6 +910,43 @@ (portRef I0 (instanceRef CLK_030_H_0_n)) (portRef I0 (instanceRef CLK_030_H_i)) )) + (net RW_000_DMA (joined + (portRef Q (instanceRef RW_000_DMA)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW)) + )) + (net un1_LDS_000_INT (joined + (portRef O (instanceRef un1_LDS_000_INT_i)) + (portRef I0 (instanceRef LDS_000)) + )) + (net LDS_000_INT (joined + (portRef Q (instanceRef LDS_000_INT)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_i)) + )) + (net DS_000_ENABLE (joined + (portRef Q (instanceRef DS_000_ENABLE)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef un1_LDS_000_INT)) + (portRef I0 (instanceRef un1_UDS_000_INT)) + )) + (net un1_UDS_000_INT (joined + (portRef O (instanceRef un1_UDS_000_INT_i)) + (portRef I0 (instanceRef UDS_000)) + )) + (net UDS_000_INT (joined + (portRef Q (instanceRef UDS_000_INT)) + (portRef I0 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_i)) + )) + (net (rename state_machine_CLK_000_N_SYNC_2_0 "state_machine.CLK_000_N_SYNC_2[0]") (joined + (portRef O (instanceRef state_machine_CLK_000_N_SYNC_2_0)) + (portRef D (instanceRef CLK_000_N_SYNC_0)) + )) + (net (rename state_machine_CLK_000_P_SYNC_3_0 "state_machine.CLK_000_P_SYNC_3[0]") (joined + (portRef O (instanceRef state_machine_CLK_000_P_SYNC_3_0)) + (portRef D (instanceRef CLK_000_P_SYNC_0)) + )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) (portRef I0 (instanceRef DS_000_DMA_0_m)) @@ -844,25 +964,119 @@ (portRef Q (instanceRef A0_DMA)) (portRef I0 (instanceRef A0)) )) + (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_0)) + (portRef D (instanceRef CLK_000_N_SYNC_1)) + )) + (net (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_1)) + (portRef D (instanceRef CLK_000_N_SYNC_2)) + )) + (net (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_2)) + (portRef D (instanceRef CLK_000_N_SYNC_3)) + )) + (net (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_3)) + (portRef D (instanceRef CLK_000_N_SYNC_4)) + )) + (net (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_4)) + (portRef D (instanceRef CLK_000_N_SYNC_5)) + )) + (net (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_5)) + (portRef D (instanceRef CLK_000_N_SYNC_6)) + )) + (net (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_6)) + (portRef D (instanceRef CLK_000_N_SYNC_7)) + )) + (net (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_7)) + (portRef D (instanceRef CLK_000_N_SYNC_8)) + )) + (net (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_8)) + (portRef D (instanceRef CLK_000_N_SYNC_9)) + )) + (net (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_9)) + (portRef D (instanceRef CLK_000_N_SYNC_10)) + )) + (net (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_10)) + (portRef D (instanceRef CLK_000_N_SYNC_11)) + )) + (net (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_0)) + (portRef D (instanceRef CLK_000_P_SYNC_1)) + )) + (net (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_1)) + (portRef D (instanceRef CLK_000_P_SYNC_2)) + )) + (net (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_2)) + (portRef D (instanceRef CLK_000_P_SYNC_3)) + )) + (net (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_3)) + (portRef D (instanceRef CLK_000_P_SYNC_4)) + )) + (net (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_4)) + (portRef D (instanceRef CLK_000_P_SYNC_5)) + )) + (net (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_5)) + (portRef D (instanceRef CLK_000_P_SYNC_6)) + )) + (net (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_6)) + (portRef D (instanceRef CLK_000_P_SYNC_7)) + )) + (net (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_7)) + (portRef D (instanceRef CLK_000_P_SYNC_8)) + )) + (net (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_8)) + (portRef D (instanceRef CLK_000_P_SYNC_9)) + )) + (net un1_SM_AMIGA_0_sqmuxa_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_i_0)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) + )) + (net un1_as_030 (joined + (portRef O (instanceRef un1_as_030)) + (portRef I1 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_r)) + )) + (net un19_fpu_cs (joined + (portRef O (instanceRef un19_fpu_cs)) + (portRef I0 (instanceRef un19_fpu_cs_i)) + (portRef OE (instanceRef BERR)) + )) + (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined + (portRef O (instanceRef state_machine_un10_bg_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) - )) - (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined - (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I0 (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_2)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_0_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_4)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_5)) - (portRef I0 (instanceRef SM_AMIGA_i_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_5)) )) (net (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (joined (portRef O (instanceRef state_machine_A0_DMA_2)) @@ -877,74 +1091,78 @@ (portRef D (instanceRef SIZE_DMA_1)) )) (net N_1 (joined - (portRef O (instanceRef RW_000_INT_0_p)) - (portRef D (instanceRef RW_000_INT)) - )) - (net N_2 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_p)) - (portRef D (instanceRef AS_030_000_SYNC)) - )) - (net N_3 (joined (portRef O (instanceRef CLK_030_H_0_p)) (portRef D (instanceRef CLK_030_H)) )) - (net N_4 (joined - (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef D (instanceRef UDS_000_INT)) + (net N_2 (joined + (portRef O (instanceRef RW_000_DMA_0_p)) + (portRef D (instanceRef RW_000_DMA)) )) - (net N_5 (joined - (portRef O (instanceRef LDS_000_INT_0_p)) - (portRef D (instanceRef LDS_000_INT)) - )) - (net N_6 (joined - (portRef O (instanceRef FPU_CS_INT_0_p)) - (portRef D (instanceRef FPU_CS_INT)) - )) - (net N_7 (joined - (portRef O (instanceRef avec_exp_0_p)) - (portRef D (instanceRef avec_exp)) - )) - (net N_8 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef D (instanceRef BG_000DFFSH)) - )) - (net N_9 (joined + (net N_3 (joined (portRef O (instanceRef DS_000_DMA_0_p)) (portRef D (instanceRef DS_000_DMA)) )) - (net N_10 (joined + (net N_4 (joined (portRef O (instanceRef AS_000_DMA_0_p)) (portRef D (instanceRef AS_000_DMA)) )) - (net N_11 (joined + (net N_5 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_p)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_INT)) + )) + (net N_6 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_p)) + (portRef D (instanceRef AS_030_000_SYNC)) + )) + (net N_7 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef D (instanceRef BG_000DFFSH)) + )) + (net N_8 (joined + (portRef O (instanceRef LDS_000_INT_0_p)) + (portRef D (instanceRef LDS_000_INT)) + )) + (net N_9 (joined (portRef O (instanceRef AS_000_INT_0_p)) (portRef D (instanceRef AS_000_INT)) )) - (net N_12 (joined + (net N_10 (joined + (portRef O (instanceRef DS_000_ENABLE_0_p)) + (portRef D (instanceRef DS_000_ENABLE)) + )) + (net N_11 (joined (portRef O (instanceRef DSACK1_INT_0_p)) (portRef D (instanceRef DSACK1_INT)) )) + (net N_12 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef D (instanceRef UDS_000_INT)) + )) (net N_13 (joined + (portRef O (instanceRef RW_000_INT_0_p)) + (portRef D (instanceRef RW_000_INT)) + )) + (net N_14 (joined (portRef O (instanceRef VMA_INT_0_p)) (portRef D (instanceRef VMA_INT)) )) - (net N_14 (joined + (net N_15 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) (portRef D (instanceRef BGACK_030_INT)) )) - (net N_15 (joined + (net N_16 (joined (portRef O (instanceRef CLK_OUT_PRE_25_0)) (portRef D (instanceRef CLK_OUT_PRE_25)) )) - (net N_16 (joined + (net N_17 (joined (portRef O (instanceRef IPL_030_0_0__p)) (portRef D (instanceRef IPL_030DFFSH_0)) )) - (net N_17 (joined + (net N_18 (joined (portRef O (instanceRef IPL_030_0_1__p)) (portRef D (instanceRef IPL_030DFFSH_1)) )) - (net N_18 (joined + (net N_19 (joined (portRef O (instanceRef IPL_030_0_2__p)) (portRef D (instanceRef IPL_030DFFSH_2)) )) @@ -952,6 +1170,14 @@ (portRef O (instanceRef SM_AMIGA_ns_i_0)) (portRef D (instanceRef SM_AMIGA_7)) )) + (net (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (joined + (portRef O (instanceRef SM_AMIGA_ns_i_2)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net (rename SM_AMIGA_ns_3 "SM_AMIGA_ns[3]") (joined + (portRef O (instanceRef SM_AMIGA_ns_i_3)) + (portRef D (instanceRef SM_AMIGA_4)) + )) (net (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (joined (portRef O (instanceRef SM_AMIGA_ns_i_4)) (portRef D (instanceRef SM_AMIGA_3)) @@ -960,40 +1186,39 @@ (portRef O (instanceRef SM_AMIGA_ns_i_5)) (portRef D (instanceRef SM_AMIGA_2)) )) - (net (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_7)) - (portRef D (instanceRef SM_AMIGA_0)) + (net (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (joined + (portRef O (instanceRef SM_AMIGA_ns_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) (portRef I0 (instanceRef cpu_est_ns_0_a3_1_1)) (portRef I0 (instanceRef cpu_est_ns_0_a3_0_2)) + (portRef I1 (instanceRef cpu_estse)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I0 (instanceRef cpu_estse)) - (portRef I0 (instanceRef state_machine_un5_clk_000_d0_2)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef cpu_est_ns_0_a3_2)) (portRef I0 (instanceRef cpu_est_ns_0_a2_1)) + (portRef I0 (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef cpu_estse_0_n)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) + (portRef I0 (instanceRef cpu_estse_1_n)) (portRef I0 (instanceRef cpu_est_i_2)) (portRef I0 (instanceRef cpu_est_ns_0_a3_0_1)) (portRef I1 (instanceRef cpu_est_ns_0_a3_2)) - (portRef I1 (instanceRef cpu_est_ns_i_a3_3)) - (portRef I0 (instanceRef cpu_estse_1_n)) + (portRef I0 (instanceRef cpu_est_ns_i_a3_3)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef cpu_est_i_3)) (portRef I1 (instanceRef cpu_est_ns_0_a3_0_1)) (portRef I1 (instanceRef cpu_est_ns_0_a3_0_2)) - (portRef I0 (instanceRef cpu_est_ns_i_o2_3)) (portRef I0 (instanceRef cpu_estse_2_n)) + (portRef I0 (instanceRef cpu_est_i_3)) + (portRef I0 (instanceRef state_machine_un10_clk_000_ne_1)) (portRef I0 (instanceRef E)) )) (net (rename cpu_est_ns_e_0 "cpu_est_ns_e[0]") (joined @@ -1012,46 +1237,165 @@ (portRef O (instanceRef cpu_estse_2_p)) (portRef D (instanceRef cpu_est_3)) )) - (net AS_000_DMA_0_sqmuxa (joined - (portRef O (instanceRef AS_000_DMA_0_sqmuxa)) - (portRef I0 (instanceRef RW_000_i_m)) - (portRef I0 (instanceRef AS_000_DMA_0_sqmuxa_i)) - )) - (net (rename state_machine_un8_bgack_030_int "state_machine.un8_bgack_030_int") (joined - (portRef O (instanceRef state_machine_un8_bgack_030_int)) - (portRef I1 (instanceRef AS_000_DMA_0_sqmuxa)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I1 (instanceRef state_machine_A0_DMA_2)) - (portRef I1 (instanceRef state_machine_DS_000_DMA_3)) - (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0)) - (portRef I0 (instanceRef state_machine_un8_bgack_030_int_i)) - (portRef I0 (instanceRef state_machine_SIZE_DMA_4_1)) - (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0)) - (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_1)) - )) - (net N_92 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_3)) - (portRef I0 (instanceRef N_92_i)) - )) - (net (rename state_machine_un49_clk_000_d0 "state_machine.un49_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un49_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un49_clk_000_d0_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_5)) - )) - (net N_210 (joined + (net N_198 (joined (portRef O (instanceRef un4_ciin)) (portRef I0 (instanceRef CIIN)) )) - (net N_220 (joined + (net N_207 (joined (portRef O (instanceRef un8_ciin)) (portRef OE (instanceRef CIIN)) )) + (net SM_AMIGA_0_sqmuxa (joined + (portRef O (instanceRef SM_AMIGA_0_sqmuxa_0_a4)) + (portRef I0 (instanceRef SM_AMIGA_0_sqmuxa_i)) + )) + (net N_89 (joined + (portRef O (instanceRef un1_SM_AMIGA_2_i_a4)) + (portRef I0 (instanceRef N_89_i)) + )) + (net N_90 (joined + (portRef O (instanceRef un1_SM_AMIGA_6_i_a4)) + (portRef I0 (instanceRef N_90_i)) + )) + (net (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (joined + (portRef O (instanceRef state_machine_un8_bg_030)) + (portRef I0 (instanceRef state_machine_un8_bg_030_i)) + )) + (net N_91 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_0)) + (portRef I0 (instanceRef N_91_i)) + )) + (net N_92 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_0_0)) + (portRef I0 (instanceRef N_92_i)) + )) + (net N_87 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o3_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a4_1)) + )) + (net N_94 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_2)) + (portRef I0 (instanceRef N_94_i)) + )) + (net N_95 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_3)) + (portRef I0 (instanceRef N_95_i)) + )) + (net N_96 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_0_3)) + (portRef I0 (instanceRef N_96_i)) + )) + (net N_100 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_6)) + (portRef I0 (instanceRef N_100_i)) + )) + (net N_101 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_0_6)) + (portRef I0 (instanceRef N_101_i)) + )) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0)) + )) + (net N_85 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o3_i_7)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) + )) + (net DSACK1_INT_0_sqmuxa (joined + (portRef O (instanceRef DSACK1_INT_0_sqmuxa)) + (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i)) + )) + (net AS_030_000_SYNC_0_sqmuxa (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_i)) + )) + (net un1_bgack_030_int_d (joined + (portRef O (instanceRef un1_bgack_030_int_d_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_n)) + )) + (net (rename state_machine_un3_bgack_030_int_d "state_machine.un3_bgack_030_int_d") (joined + (portRef O (instanceRef state_machine_un3_bgack_030_int_d)) + (portRef I0 (instanceRef state_machine_un3_bgack_030_int_d_i)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i)) + )) + (net AMIGA_BUS_ENABLE_INT_3_sqmuxa (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa_i)) + )) + (net N_84 (joined + (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o4_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_0)) + )) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + )) + (net N_93 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a4_1)) + (portRef I0 (instanceRef N_93_i)) + )) + (net N_66 (joined + (portRef O (instanceRef un1_SM_AMIGA_6_i_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) + )) + (net (rename state_machine_RW_000_INT_3 "state_machine.RW_000_INT_3") (joined + (portRef O (instanceRef state_machine_RW_000_INT_3_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + )) + (net un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_r)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i)) + )) + (net AS_030_000_SYNC_0_sqmuxa_1 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) + (net (rename state_machine_un8_bgack_030_int "state_machine.un8_bgack_030_int") (joined + (portRef O (instanceRef state_machine_un8_bgack_030_int)) + (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_1)) + (portRef I0 (instanceRef state_machine_un8_bgack_030_int_i)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) + (portRef I1 (instanceRef state_machine_A0_DMA_2)) + (portRef I1 (instanceRef state_machine_DS_000_DMA_3)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_4_1)) + (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0)) + )) + (net N_167_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) + (portRef I0 (instanceRef state_machine_un8_bgack_030_int)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) + )) + (net (rename state_machine_un10_bgack_030_int "state_machine.un10_bgack_030_int") (joined + (portRef O (instanceRef state_machine_un10_bgack_030_int_i)) + (portRef I1 (instanceRef state_machine_un8_bgack_030_int)) + )) (net CLK_030_H_1_sqmuxa (joined (portRef O (instanceRef CLK_030_H_1_sqmuxa)) (portRef I0 (instanceRef CLK_030_H_1_sqmuxa_i)) )) (net AS_000_DMA_1_sqmuxa (joined (portRef O (instanceRef AS_000_DMA_1_sqmuxa)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) (portRef I1 (instanceRef AS_000_DMA_0_m)) (portRef I0 (instanceRef AS_000_DMA_0_r)) )) @@ -1060,6 +1404,11 @@ (portRef I1 (instanceRef DS_000_DMA_0_m)) (portRef I0 (instanceRef DS_000_DMA_0_r)) )) + (net DS_000_DMA_1_sqmuxa_1 (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_1_i)) + )) (net (rename state_machine_un24_bgack_030_int "state_machine.un24_bgack_030_int") (joined (portRef O (instanceRef state_machine_un24_bgack_030_int)) (portRef I0 (instanceRef state_machine_un24_bgack_030_int_i)) @@ -1072,556 +1421,345 @@ (portRef O (instanceRef state_machine_CLK_030_H_2_f1_i)) (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0)) )) - (net (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (joined - (portRef O (instanceRef state_machine_DS_000_DMA_3_i)) - (portRef I0 (instanceRef DS_000_DMA_0_n)) - )) - (net N_87 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1)) - )) - (net N_93 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_4)) - (portRef I0 (instanceRef N_93_i)) - )) - (net N_94 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_4)) - (portRef I0 (instanceRef N_94_i)) - )) - (net N_88 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0)) - (portRef I0 (instanceRef N_88_i)) - )) - (net N_90 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_1)) - (portRef I0 (instanceRef N_90_i)) - )) - (net N_164_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) - (portRef I0 (instanceRef state_machine_un8_bgack_030_int)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) - )) - (net (rename state_machine_un10_bgack_030_int "state_machine.un10_bgack_030_int") (joined - (portRef O (instanceRef state_machine_un10_bgack_030_int_i)) - (portRef I1 (instanceRef state_machine_un8_bgack_030_int)) - )) - (net UDS_000_INT_0_sqmuxa_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - )) - (net UDS_000_INT_0_sqmuxa (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) - )) - (net (rename state_machine_un25_clk_000_d0 "state_machine.un25_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un25_clk_000_d0_i_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7)) - )) - (net N_164 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) - (portRef I0 (instanceRef N_164_i)) - )) - (net RW_li_m (joined - (portRef O (instanceRef RW_li_m)) - (portRef I0 (instanceRef RW_li_m_i)) - )) - (net N_181 (joined - (portRef O (instanceRef un1_AS_030_2_94)) - (portRef I1 (instanceRef un1_AS_030_2)) - (portRef I0 (instanceRef N_181_i)) - )) - (net RW_000_i_m (joined - (portRef O (instanceRef RW_000_i_m)) - (portRef I0 (instanceRef RW_000_i_m_i)) - )) - (net N_163 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) - (portRef I0 (instanceRef N_163_i)) - )) - (net un1_SM_AMIGA_8 (joined - (portRef O (instanceRef un1_SM_AMIGA_8_0_i)) - (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_1)) - )) - (net N_100 (joined - (portRef O (instanceRef un1_SM_AMIGA_8_0_a2)) - (portRef I0 (instanceRef N_100_i)) - )) - (net N_91 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_2)) - (portRef I0 (instanceRef N_91_i)) - )) (net (rename state_machine_un31_bgack_030_int "state_machine.un31_bgack_030_int") (joined (portRef O (instanceRef state_machine_un31_bgack_030_int)) (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0)) (portRef I0 (instanceRef state_machine_un31_bgack_030_int_i)) )) - (net (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_i)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_i)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) - )) - (net RW_000_INT_0_sqmuxa_1 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_1)) - (portRef I1 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_r)) - )) - (net un1_AS_030_2 (joined - (portRef O (instanceRef un1_AS_030_2)) - (portRef I1 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) - )) - (net N_59 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_i)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef AS_000_INT_0_n)) - )) - (net un1_bgack_030_int_d (joined - (portRef O (instanceRef un1_bgack_030_int_d_i)) - (portRef I0 (instanceRef avec_exp_0_n)) - )) - (net un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) - (portRef I1 (instanceRef avec_exp_0_m)) - (portRef I0 (instanceRef avec_exp_0_r)) - )) - (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined - (portRef O (instanceRef state_machine_un10_bg_030_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) - )) - (net (rename state_machine_un3_bgack_030_int_d "state_machine.un3_bgack_030_int_d") (joined - (portRef O (instanceRef state_machine_un3_bgack_030_int_d)) - (portRef I0 (instanceRef state_machine_un3_bgack_030_int_d_i)) - )) - (net AMIGA_BUS_ENABLE_INT_3_sqmuxa (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa_i)) - )) - (net N_86 (joined - (portRef O (instanceRef un1_SM_AMIGA_4_0_o2_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_7)) - )) - (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i)) - )) - (net N_84 (joined - (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o2_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) - )) - (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i)) - )) - (net (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (joined - (portRef O (instanceRef state_machine_un8_bg_030)) - (portRef I0 (instanceRef state_machine_un8_bg_030_i)) - )) - (net AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) - )) - (net N_89 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_0)) - (portRef I0 (instanceRef N_89_i)) - )) - (net N_95 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_5)) - (portRef I0 (instanceRef N_95_i)) - )) - (net N_96 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_5)) - (portRef I0 (instanceRef N_96_i)) - )) - (net N_97 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I0 (instanceRef N_97_i)) - )) - (net N_99 (joined - (portRef O (instanceRef un1_SM_AMIGA_9_i_a2)) - (portRef I0 (instanceRef N_99_i)) - )) - (net (rename state_machine_un28_clk_000_d1 "state_machine.un28_clk_000_d1") (joined - (portRef O (instanceRef state_machine_un28_clk_000_d1)) - (portRef I1 (instanceRef un1_amiga_bus_enable_int5_0_o2)) - (portRef I1 (instanceRef un1_SM_AMIGA_10_i_a3)) - )) - (net N_101 (joined - (portRef O (instanceRef un1_SM_AMIGA_10_i_a3)) - (portRef I0 (instanceRef N_101_i)) - )) - (net un1_SM_AMIGA_12 (joined - (portRef O (instanceRef un1_SM_AMIGA_12_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) - )) - (net AS_030_000_SYNC_1_sqmuxa (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) - )) - (net un1_as_030_000_sync8_1 (joined - (portRef O (instanceRef un1_as_030_000_sync8_1_i)) - (portRef I1 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_r)) - )) - (net AS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) - )) - (net DSACK1_INT_1_sqmuxa (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa)) - (portRef I1 (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_r)) - )) - (net (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un10_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un10_clk_000_d0_i)) - )) - (net (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) - )) - (net (rename state_machine_un51_clk_000_d0 "state_machine.un51_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un51_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un51_clk_000_d0_i)) - )) - (net (rename state_machine_un53_clk_000_d0 "state_machine.un53_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un53_clk_000_d0_i)) - (portRef I1 (instanceRef state_machine_un49_clk_000_d0)) - )) - (net (rename state_machine_un57_clk_000_d0 "state_machine.un57_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un57_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un57_clk_000_d0_i)) - )) - (net AS_030_000_SYNC_0_sqmuxa_2 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2_i)) - )) - (net AS_030_000_SYNC_0_sqmuxa (joined - (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_i)) - )) - (net (rename state_machine_un3_clk_030 "state_machine.un3_clk_030") (joined - (portRef O (instanceRef state_machine_un3_clk_030_i_0)) - (portRef I1 (instanceRef un1_as_030_000_sync8_1)) - (portRef I1 (instanceRef un1_as_030_000_sync8)) - )) - (net FPU_CS_INT_1_sqmuxa (joined - (portRef O (instanceRef FPU_CS_INT_1_sqmuxa)) - (portRef I0 (instanceRef FPU_CS_INT_1_sqmuxa_i)) - )) - (net (rename state_machine_un28_clk_030 "state_machine.un28_clk_030") (joined - (portRef O (instanceRef state_machine_un28_clk_030)) - (portRef I0 (instanceRef state_machine_un28_clk_030_i)) - )) - (net un1_as_030_000_sync8 (joined - (portRef O (instanceRef un1_as_030_000_sync8_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa)) - )) - (net N_150 (joined - (portRef O (instanceRef cpu_est_ns_i_o2_i_3)) - (portRef I0 (instanceRef cpu_est_ns_i_a3_3)) - )) - (net (rename state_machine_un5_clk_000_d0 "state_machine.un5_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un5_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un5_clk_000_d0_i)) - )) - (net (rename state_machine_un3_clk_000_d1 "state_machine.un3_clk_000_d1") (joined - (portRef O (instanceRef state_machine_un3_clk_000_d1)) - (portRef I1 (instanceRef cpu_estse)) - (portRef I1 (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef cpu_estse_0_m)) - (portRef I0 (instanceRef cpu_estse_0_r)) - (portRef I1 (instanceRef cpu_estse_1_m)) - (portRef I0 (instanceRef cpu_estse_1_r)) - (portRef I1 (instanceRef cpu_estse_2_m)) - (portRef I0 (instanceRef cpu_estse_2_r)) - (portRef I0 (instanceRef state_machine_un3_clk_000_d1_i)) + (net (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (joined + (portRef O (instanceRef state_machine_DS_000_DMA_3_i)) + (portRef I0 (instanceRef DS_000_DMA_0_n)) )) (net (rename cpu_est_ns_2 "cpu_est_ns[2]") (joined (portRef O (instanceRef cpu_est_ns_0_i_2)) (portRef I0 (instanceRef cpu_estse_1_m)) )) - (net N_157 (joined + (net N_160 (joined (portRef O (instanceRef cpu_est_ns_0_a3_1_2)) - (portRef I0 (instanceRef N_157_i)) + (portRef I0 (instanceRef N_160_i)) )) - (net N_156 (joined + (net N_159 (joined (portRef O (instanceRef cpu_est_ns_0_a3_0_2)) - (portRef I0 (instanceRef N_156_i)) + (portRef I0 (instanceRef N_159_i)) )) (net (rename state_machine_un10_clk_000_d0_2 "state_machine.un10_clk_000_d0_2") (joined (portRef O (instanceRef cpu_est_ns_0_a3_2)) (portRef I0 (instanceRef state_machine_un10_clk_000_d0_2_i)) (portRef I0 (instanceRef state_machine_un10_clk_000_d0_1)) )) - (net N_154 (joined + (net (rename state_machine_un5_clk_000_d0_1 "state_machine.un5_clk_000_d0_1") (joined (portRef O (instanceRef cpu_est_ns_0_a3_1_1)) - (portRef I0 (instanceRef N_154_i)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_1_i)) )) - (net N_160 (joined + (net N_163 (joined (portRef O (instanceRef cpu_est_ns_0_a2_1)) (portRef I0 (instanceRef cpu_est_ns_i_a3_0_3)) - (portRef I0 (instanceRef N_160_i)) + (portRef I0 (instanceRef N_163_i)) )) - (net N_152 (joined + (net N_155 (joined (portRef O (instanceRef cpu_est_ns_0_a3_1)) - (portRef I0 (instanceRef N_152_i)) + (portRef I0 (instanceRef N_155_i)) )) - (net N_153 (joined + (net N_156 (joined (portRef O (instanceRef cpu_est_ns_0_a3_0_1)) - (portRef I0 (instanceRef N_153_i)) - )) - (net N_158 (joined - (portRef O (instanceRef cpu_est_ns_i_a3_3)) - (portRef I0 (instanceRef N_158_i)) - )) - (net N_159 (joined - (portRef O (instanceRef cpu_est_ns_i_a3_0_3)) - (portRef I0 (instanceRef N_159_i)) + (portRef I0 (instanceRef N_156_i)) )) (net (rename cpu_est_ns_1 "cpu_est_ns[1]") (joined (portRef O (instanceRef cpu_est_ns_0_i_1)) (portRef I0 (instanceRef cpu_estse_0_m)) )) + (net (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un12_clk_000_d0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) + (net (rename state_machine_un6_clk_000_p_sync "state_machine.un6_clk_000_p_sync") (joined + (portRef O (instanceRef state_machine_un6_clk_000_p_sync)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + (portRef I0 (instanceRef state_machine_un6_clk_000_p_sync_i)) + (portRef I1 (instanceRef state_machine_CLK_000_P_SYNC_3_0)) + )) + (net (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0_i)) + )) + (net (rename state_machine_un5_clk_000_d0 "state_machine.un5_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_i)) + )) + (net N_161 (joined + (portRef O (instanceRef cpu_est_ns_i_a3_3)) + (portRef I0 (instanceRef N_161_i)) + )) + (net (rename state_machine_un10_clk_000_ne_1 "state_machine.un10_clk_000_ne_1") (joined + (portRef O (instanceRef state_machine_un10_clk_000_ne_1)) + (portRef I0 (instanceRef state_machine_un10_clk_000_ne_1_i)) + (portRef I0 (instanceRef state_machine_un10_clk_000_ne_1_0)) + )) + (net N_162 (joined + (portRef O (instanceRef cpu_est_ns_i_a3_0_3)) + (portRef I0 (instanceRef N_162_i)) + )) + (net (rename state_machine_un5_clk_000_d0_2 "state_machine.un5_clk_000_d0_2") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_2)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_2_i)) + (portRef I1 (instanceRef state_machine_un5_clk_000_d0)) + )) + (net N_166 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) + (portRef I0 (instanceRef N_166_i)) + )) + (net N_167 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) + (portRef I0 (instanceRef N_167_i)) + )) + (net DSACK1_INT_1_sqmuxa (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) + )) (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined (portRef O (instanceRef state_machine_un6_bgack_000_i)) (portRef I1 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I1 (instanceRef state_machine_un28_clk_000_d1_1)) + (net DS_000_ENABLE_0_sqmuxa (joined + (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa)) + (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_i)) )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef state_machine_un3_clk_000_d1)) - (portRef I1 (instanceRef state_machine_un28_clk_000_d1)) + (net (rename state_machine_un10_clk_000_ne "state_machine.un10_clk_000_ne") (joined + (portRef O (instanceRef state_machine_un10_clk_000_ne)) + (portRef I0 (instanceRef state_machine_un10_clk_000_ne_i)) + )) + (net N_86 (joined + (portRef O (instanceRef SM_AMIGA_ns_o3_i_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_4)) + )) + (net (rename state_machine_un6_clk_000_ne "state_machine.un6_clk_000_ne") (joined + (portRef O (instanceRef state_machine_un6_clk_000_ne_i_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_o3_4)) + )) + (net N_98 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_5)) + (portRef I0 (instanceRef N_98_i)) + )) + (net N_99 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_0_5)) + (portRef I0 (instanceRef N_99_i)) + )) + (net N_97 (joined + (portRef O (instanceRef SM_AMIGA_ns_a4_4)) + (portRef I0 (instanceRef N_97_i)) + )) + (net (rename state_machine_un4_clk_000_ne "state_machine.un4_clk_000_ne") (joined + (portRef O (instanceRef state_machine_un4_clk_000_ne)) + (portRef I0 (instanceRef state_machine_un4_clk_000_ne_i)) + )) + (net un19_fpu_cs_i (joined + (portRef O (instanceRef un19_fpu_cs_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) + (portRef I0 (instanceRef FPU_CS)) + )) + (net DTACK_i (joined + (portRef O (instanceRef I_143)) + (portRef I0 (instanceRef state_machine_un4_clk_000_ne)) + )) + (net avec_exp_i (joined + (portRef O (instanceRef avec_exp_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_0_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_a4_5)) + )) + (net CLK_000_NE_i (joined + (portRef O (instanceRef CLK_000_NE_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_0_6)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef state_machine_un5_clk_000_d0_2)) + (portRef I1 (instanceRef state_machine_un10_clk_000_ne)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I1 (instanceRef state_machine_un10_clk_000_ne_1_0)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_144)) + (portRef I0 (instanceRef un1_as_030)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I0 (instanceRef un19_fpu_cs_1)) + )) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I0 (instanceRef un19_fpu_cs_3)) + )) + (net DSACK1_INT_0_sqmuxa_i (joined + (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i)) + (portRef I0 (instanceRef DSACK1_INT_0_n)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa)) + )) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I0 (instanceRef un19_fpu_cs_2)) + )) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I1 (instanceRef un19_fpu_cs_2)) + )) + (net nEXP_SPACE_i (joined + (portRef O (instanceRef nEXP_SPACE_i)) + (portRef I0 (instanceRef un3_dtack_1)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) + )) + (net RW_i (joined + (portRef O (instanceRef I_145)) + (portRef I0 (instanceRef state_machine_RW_000_INT_3)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) + )) + (net CLK_000_D3_i (joined + (portRef O (instanceRef CLK_000_D3_i)) + (portRef I1 (instanceRef state_machine_CLK_000_P_SYNC_3_1_0)) + )) + (net CLK_000_D2_i (joined + (portRef O (instanceRef CLK_000_D2_i)) + (portRef I0 (instanceRef state_machine_CLK_000_P_SYNC_3_1_0)) + )) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_2)) + (portRef I0 (instanceRef state_machine_CLK_000_N_SYNC_2_1_0)) )) (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef cpu_est_ns_i_a3_0_3)) (portRef I1 (instanceRef cpu_est_ns_0_a3_1)) + (portRef I1 (instanceRef cpu_est_ns_i_a3_0_3)) (portRef I1 (instanceRef state_machine_un10_clk_000_d0)) )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_ns_0_a3_1)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef cpu_est_ns_0_a3_1_1)) - (portRef I1 (instanceRef cpu_est_ns_0_a3_1_2)) - (portRef I1 (instanceRef cpu_est_ns_i_o2_3)) - (portRef I1 (instanceRef state_machine_un5_clk_000_d0_2)) - )) (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined (portRef O (instanceRef cpu_est_i_0)) (portRef I0 (instanceRef cpu_est_ns_0_a3_1_2)) (portRef I1 (instanceRef cpu_est_ns_0_a2_1)) (portRef I1 (instanceRef state_machine_un10_clk_000_d0_2)) )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef state_machine_un5_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un57_clk_000_d0_1)) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_1_1)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_1_2)) + (portRef I1 (instanceRef state_machine_un10_clk_000_ne_1)) )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_5)) - (portRef I0 (instanceRef un1_SM_AMIGA_9_i_a2)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_7)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - (portRef I0 (instanceRef state_machine_un5_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un49_clk_000_d0_1)) + (net (rename state_machine_un10_clk_000_ne_1_i "state_machine.un10_clk_000_ne_1_i") (joined + (portRef O (instanceRef state_machine_un10_clk_000_ne_1_i)) + (portRef I1 (instanceRef cpu_est_ns_i_a3_3)) )) - (net (rename state_machine_un28_clk_030_i "state_machine.un28_clk_030_i") (joined - (portRef O (instanceRef state_machine_un28_clk_030_i)) - (portRef I1 (instanceRef FPU_CS_INT_1_sqmuxa)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_2_0)) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef state_machine_un6_clk_000_p_sync)) + (portRef I1 (instanceRef un1_amiga_bus_enable_int5_0_o4_1)) )) - (net VMA_INT_i (joined - (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef state_machine_un57_clk_000_d0)) - )) - (net AS_030_i (joined - (portRef O (instanceRef I_151)) - (portRef I0 (instanceRef un1_AS_030_2)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef un1_SM_AMIGA_12)) - (portRef I0 (instanceRef FPU_CS_INT_1_sqmuxa)) - (portRef I0 (instanceRef state_machine_un3_clk_030)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) - )) - (net AS_030_000_SYNC_0_sqmuxa_i (joined - (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I1 (instanceRef un1_SM_AMIGA_4_0_o2)) - (portRef I1 (instanceRef un1_SM_AMIGA_10_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa)) - (portRef I0 (instanceRef DSACK1_INT_0_n)) - )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef state_machine_un51_clk_000_d0)) - )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I1 (instanceRef state_machine_un28_clk_030_2)) - )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I1 (instanceRef state_machine_un28_clk_030_1)) - )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I0 (instanceRef state_machine_un28_clk_030_2)) - )) - (net (rename state_machine_un5_clk_000_d0_i_0 "state_machine.un5_clk_000_d0_i_0") (joined - (portRef O (instanceRef state_machine_un5_clk_000_d0_i)) + (net (rename state_machine_un5_clk_000_d0_2_i_0 "state_machine.un5_clk_000_d0_2_i_0") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_2_i)) (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0)) )) - (net nEXP_SPACE_i (joined - (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef un3_dtack_1)) - (portRef I1 (instanceRef un1_SM_AMIGA_10_i_a3_1)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_1)) )) - (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_2)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_8_0_a2)) - (portRef I0 (instanceRef un1_SM_AMIGA_4_0_o2)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) - )) - (net N_99_i (joined - (portRef O (instanceRef N_99_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6)) - )) - (net BGACK_030_INT_i (joined - (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) - (portRef I1 (instanceRef un3_dtack)) - (portRef OE (instanceRef RW)) - )) - (net BGACK_030_INT_D_i (joined - (portRef O (instanceRef BGACK_030_INT_D_i)) - (portRef I1 (instanceRef state_machine_un3_bgack_030_int_d)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_2)) - (portRef I1 (instanceRef un1_SM_AMIGA_8_0_a2)) - )) - (net UDS_000_i (joined - (portRef O (instanceRef I_152)) - (portRef I1 (instanceRef state_machine_un31_bgack_030_int)) - )) - (net LDS_000_i (joined - (portRef O (instanceRef I_153)) - (portRef I0 (instanceRef state_machine_un31_bgack_030_int)) - )) - (net AS_000_DMA_0_sqmuxa_i (joined - (portRef O (instanceRef AS_000_DMA_0_sqmuxa_i)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_1)) - (portRef I0 (instanceRef RW_li_m_1)) + (net DS_000_DMA_1_sqmuxa_1_i (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1_i)) + (portRef I0 (instanceRef RW_000_DMA_0_n)) )) (net (rename state_machine_un8_bgack_030_int_i "state_machine.un8_bgack_030_int_i") (joined (portRef O (instanceRef state_machine_un8_bgack_030_int_i)) (portRef I0 (instanceRef AS_000_DMA_0_n)) )) + (net CLK_030_i (joined + (portRef O (instanceRef CLK_030_i)) + (portRef I1 (instanceRef state_machine_un24_bgack_030_int)) + )) + (net UDS_000_i (joined + (portRef O (instanceRef I_146)) + (portRef I1 (instanceRef state_machine_un31_bgack_030_int)) + )) + (net LDS_000_i (joined + (portRef O (instanceRef I_147)) + (portRef I0 (instanceRef state_machine_un31_bgack_030_int)) + )) (net (rename state_machine_un31_bgack_030_int_i "state_machine.un31_bgack_030_int_i") (joined (portRef O (instanceRef state_machine_un31_bgack_030_int_i)) (portRef I1 (instanceRef state_machine_SIZE_DMA_4_1)) )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_2)) - )) - (net RW_i (joined - (portRef O (instanceRef I_154)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) - (portRef I1 (instanceRef RW_li_m_1)) - )) (net RW_000_i (joined - (portRef O (instanceRef I_155)) - (portRef I1 (instanceRef RW_000_i_m)) + (portRef O (instanceRef I_148)) (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_1)) )) - (net UDS_000_INT_0_sqmuxa_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) - (portRef I1 (instanceRef un1_AS_030_2_94)) - )) - (net UDS_000_INT_0_sqmuxa_1_i (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_AS_030_2_94)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_156)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) - )) - (net DS_030_i (joined - (portRef O (instanceRef I_158)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - )) - (net (rename state_machine_un49_clk_000_d0_i "state_machine.un49_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un49_clk_000_d0_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_4)) - )) - (net CLK_030_i (joined - (portRef O (instanceRef CLK_030_i)) - (portRef I1 (instanceRef state_machine_un24_bgack_030_int)) - (portRef I0 (instanceRef AS_000_DMA_0_sqmuxa)) - (portRef I1 (instanceRef state_machine_un3_clk_030)) - )) (net (rename state_machine_un24_bgack_030_int_i "state_machine.un24_bgack_030_int_i") (joined (portRef O (instanceRef state_machine_un24_bgack_030_int_i)) (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa)) )) (net AS_000_DMA_i (joined (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef state_machine_DS_000_DMA_3)) (portRef I0 (instanceRef CLK_030_H_1_sqmuxa)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_3)) (portRef I1 (instanceRef un3_dtack_1)) )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_3)) + (net BGACK_030_INT_i (joined + (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) + (portRef I1 (instanceRef un3_dtack)) + (portRef OE (instanceRef RW)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_149)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) + )) + (net N_90_i (joined + (portRef O (instanceRef N_90_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_6_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_2)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + )) + (net BGACK_030_INT_D_i (joined + (portRef O (instanceRef BGACK_030_INT_D_i)) + (portRef I1 (instanceRef state_machine_un3_bgack_030_int_d)) + )) + (net N_89_i (joined + (portRef O (instanceRef N_89_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) + )) + (net AS_030_000_SYNC_0_sqmuxa_i (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef un1_SM_AMIGA_6_i)) + (portRef I1 (instanceRef state_machine_RW_000_INT_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a4_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0)) + )) + (net CLK_OUT_NE_i (joined + (portRef O (instanceRef CLK_OUT_NE_i)) + (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_1)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_2_i_a4)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef un1_SM_AMIGA_2_i_a4)) )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) @@ -1658,6 +1796,7 @@ (net RST_i (joined (portRef O (instanceRef RST_i)) (portRef S (instanceRef A0_DMA)) + (portRef S (instanceRef AMIGA_BUS_ENABLE_INT)) (portRef S (instanceRef AS_000_DMA)) (portRef S (instanceRef AS_000_INT)) (portRef S (instanceRef AS_030_000_SYNC)) @@ -1667,19 +1806,46 @@ (portRef S (instanceRef CLK_000_D0)) (portRef S (instanceRef CLK_000_D1)) (portRef S (instanceRef CLK_000_D2)) + (portRef S (instanceRef CLK_000_D3)) + (portRef R (instanceRef CLK_000_NE)) + (portRef R (instanceRef CLK_000_N_SYNC_0)) + (portRef R (instanceRef CLK_000_N_SYNC_1)) + (portRef R (instanceRef CLK_000_N_SYNC_2)) + (portRef R (instanceRef CLK_000_N_SYNC_3)) + (portRef R (instanceRef CLK_000_N_SYNC_4)) + (portRef R (instanceRef CLK_000_N_SYNC_5)) + (portRef R (instanceRef CLK_000_N_SYNC_6)) + (portRef R (instanceRef CLK_000_N_SYNC_7)) + (portRef R (instanceRef CLK_000_N_SYNC_8)) + (portRef R (instanceRef CLK_000_N_SYNC_9)) + (portRef R (instanceRef CLK_000_N_SYNC_10)) + (portRef R (instanceRef CLK_000_N_SYNC_11)) + (portRef R (instanceRef CLK_000_P_SYNC_0)) + (portRef R (instanceRef CLK_000_P_SYNC_1)) + (portRef R (instanceRef CLK_000_P_SYNC_2)) + (portRef R (instanceRef CLK_000_P_SYNC_3)) + (portRef R (instanceRef CLK_000_P_SYNC_4)) + (portRef R (instanceRef CLK_000_P_SYNC_5)) + (portRef R (instanceRef CLK_000_P_SYNC_6)) + (portRef R (instanceRef CLK_000_P_SYNC_7)) + (portRef R (instanceRef CLK_000_P_SYNC_8)) + (portRef R (instanceRef CLK_000_P_SYNC_9)) (portRef R (instanceRef CLK_OUT_INT)) + (portRef R (instanceRef CLK_OUT_NE)) + (portRef R (instanceRef CLK_OUT_PRE)) (portRef R (instanceRef CLK_OUT_PRE_25)) (portRef R (instanceRef CLK_OUT_PRE_50)) (portRef R (instanceRef CLK_OUT_PRE_50_D)) + (portRef R (instanceRef CLK_OUT_PRE_D)) (portRef S (instanceRef DSACK1_INT)) (portRef S (instanceRef DS_000_DMA)) - (portRef S (instanceRef DTACK_D0)) - (portRef S (instanceRef FPU_CS_INT)) + (portRef R (instanceRef DS_000_ENABLE)) (portRef S (instanceRef IPL_030DFFSH_0)) (portRef S (instanceRef IPL_030DFFSH_1)) (portRef S (instanceRef IPL_030DFFSH_2)) (portRef S (instanceRef LDS_000_INT)) (portRef R (instanceRef RESETDFFRH)) + (portRef S (instanceRef RW_000_DMA)) (portRef S (instanceRef RW_000_INT)) (portRef S (instanceRef SIZE_DMA_0)) (portRef S (instanceRef SIZE_DMA_1)) @@ -1694,7 +1860,7 @@ (portRef S (instanceRef UDS_000_INT)) (portRef S (instanceRef VMA_INT)) (portRef S (instanceRef VPA_D)) - (portRef S (instanceRef avec_exp)) + (portRef R (instanceRef avec_exp)) (portRef R (instanceRef cpu_est_0)) (portRef R (instanceRef cpu_est_1)) (portRef R (instanceRef cpu_est_2)) @@ -1704,9 +1870,9 @@ (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net FPU_CS_INT_i (joined - (portRef O (instanceRef FPU_CS_INT_i)) - (portRef OE (instanceRef BERR)) + (net CLK_OUT_PRE_i (joined + (portRef O (instanceRef CLK_OUT_PRE_i)) + (portRef I1 (instanceRef state_machine_un3_clk_out_pre_d)) )) (net CLK_OUT_PRE_50_D_i (joined (portRef O (instanceRef CLK_OUT_PRE_50_D_i)) @@ -1714,8 +1880,8 @@ )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef FPU_CS_INT_0_n)) - (portRef I0 (instanceRef I_151)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef I_144)) (portRef I0 (instanceRef state_machine_un8_bg_030_1)) )) (net AS_030 (joined @@ -1724,7 +1890,7 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef I_156)) + (portRef I0 (instanceRef I_149)) )) (net AS_000 (joined (portRef IO (instanceRef AS_000)) @@ -1732,7 +1898,7 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_155)) + (portRef I0 (instanceRef I_148)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -1740,7 +1906,10 @@ )) (net DS_030_c (joined (portRef O (instanceRef DS_030)) - (portRef I0 (instanceRef I_158)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) )) (net DS_030 (joined (portRef IO (instanceRef DS_030)) @@ -1748,9 +1917,9 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I0 (instanceRef state_machine_A0_DMA_2)) (portRef I1 (instanceRef state_machine_un10_bgack_030_int)) - (portRef I0 (instanceRef I_152)) + (portRef I0 (instanceRef I_146)) + (portRef I0 (instanceRef state_machine_A0_DMA_2)) )) (net UDS_000 (joined (portRef IO (instanceRef UDS_000)) @@ -1759,7 +1928,7 @@ (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) (portRef I0 (instanceRef state_machine_un10_bgack_030_int)) - (portRef I0 (instanceRef I_153)) + (portRef I0 (instanceRef I_147)) )) (net LDS_000 (joined (portRef IO (instanceRef LDS_000)) @@ -1767,7 +1936,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I0 (instanceRef state_machine_un25_clk_000_d0_1)) + (portRef I1 (instanceRef state_machine_un7_ds_030)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef IO (instanceRef SIZE_0)) @@ -1791,7 +1960,7 @@ )) (net (rename A_c_17 "A_c[17]") (joined (portRef O (instanceRef A_17)) - (portRef I0 (instanceRef state_machine_un28_clk_030_1)) + (portRef I1 (instanceRef un19_fpu_cs_1)) )) (net (rename A_17 "A[17]") (joined (portRef (member a 14)) @@ -1911,6 +2080,7 @@ )) (net A0_c (joined (portRef O (instanceRef A0)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) (portRef I0 (instanceRef A0_c_i)) )) (net A0 (joined @@ -1920,9 +2090,9 @@ (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o2)) + (portRef I1 (instanceRef un1_amiga_bus_enable_int5_0_o4_2)) (portRef I1 (instanceRef state_machine_un8_bg_030_2)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2_0)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) (portRef OE (instanceRef DSACK1)) )) (net nEXP_SPACE (joined @@ -1959,7 +2129,7 @@ (portRef O (instanceRef BGACK_000)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef state_machine_un6_bgack_000)) - (portRef I1 (instanceRef state_machine_un28_clk_030_3)) + (portRef I1 (instanceRef un19_fpu_cs_3)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -1967,9 +2137,9 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) + (portRef I1 (instanceRef CLK_030_H_1_sqmuxa)) (portRef I0 (instanceRef CLK_030_i)) (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I1 (instanceRef CLK_030_H_1_sqmuxa)) )) (net CLK_030 (joined (portRef CLK_030) @@ -1987,6 +2157,7 @@ (net CLK_OSZI_c (joined (portRef O (instanceRef CLK_OSZI)) (portRef CLK (instanceRef A0_DMA)) + (portRef CLK (instanceRef AMIGA_BUS_ENABLE_INT)) (portRef CLK (instanceRef AS_000_DMA)) (portRef CLK (instanceRef AS_000_INT)) (portRef CLK (instanceRef AS_030_000_SYNC)) @@ -1996,20 +2167,47 @@ (portRef CLK (instanceRef CLK_000_D0)) (portRef CLK (instanceRef CLK_000_D1)) (portRef CLK (instanceRef CLK_000_D2)) + (portRef CLK (instanceRef CLK_000_D3)) + (portRef CLK (instanceRef CLK_000_NE)) + (portRef CLK (instanceRef CLK_000_N_SYNC_0)) + (portRef CLK (instanceRef CLK_000_N_SYNC_1)) + (portRef CLK (instanceRef CLK_000_N_SYNC_2)) + (portRef CLK (instanceRef CLK_000_N_SYNC_3)) + (portRef CLK (instanceRef CLK_000_N_SYNC_4)) + (portRef CLK (instanceRef CLK_000_N_SYNC_5)) + (portRef CLK (instanceRef CLK_000_N_SYNC_6)) + (portRef CLK (instanceRef CLK_000_N_SYNC_7)) + (portRef CLK (instanceRef CLK_000_N_SYNC_8)) + (portRef CLK (instanceRef CLK_000_N_SYNC_9)) + (portRef CLK (instanceRef CLK_000_N_SYNC_10)) + (portRef CLK (instanceRef CLK_000_N_SYNC_11)) + (portRef CLK (instanceRef CLK_000_P_SYNC_0)) + (portRef CLK (instanceRef CLK_000_P_SYNC_1)) + (portRef CLK (instanceRef CLK_000_P_SYNC_2)) + (portRef CLK (instanceRef CLK_000_P_SYNC_3)) + (portRef CLK (instanceRef CLK_000_P_SYNC_4)) + (portRef CLK (instanceRef CLK_000_P_SYNC_5)) + (portRef CLK (instanceRef CLK_000_P_SYNC_6)) + (portRef CLK (instanceRef CLK_000_P_SYNC_7)) + (portRef CLK (instanceRef CLK_000_P_SYNC_8)) + (portRef CLK (instanceRef CLK_000_P_SYNC_9)) (portRef CLK (instanceRef CLK_030_H)) (portRef CLK (instanceRef CLK_OUT_INT)) + (portRef CLK (instanceRef CLK_OUT_NE)) + (portRef CLK (instanceRef CLK_OUT_PRE)) (portRef CLK (instanceRef CLK_OUT_PRE_25)) (portRef CLK (instanceRef CLK_OUT_PRE_50)) (portRef CLK (instanceRef CLK_OUT_PRE_50_D)) + (portRef CLK (instanceRef CLK_OUT_PRE_D)) (portRef CLK (instanceRef DSACK1_INT)) (portRef CLK (instanceRef DS_000_DMA)) - (portRef CLK (instanceRef DTACK_D0)) - (portRef CLK (instanceRef FPU_CS_INT)) + (portRef CLK (instanceRef DS_000_ENABLE)) (portRef CLK (instanceRef IPL_030DFFSH_0)) (portRef CLK (instanceRef IPL_030DFFSH_1)) (portRef CLK (instanceRef IPL_030DFFSH_2)) (portRef CLK (instanceRef LDS_000_INT)) (portRef CLK (instanceRef RESETDFFRH)) + (portRef CLK (instanceRef RW_000_DMA)) (portRef CLK (instanceRef RW_000_INT)) (portRef CLK (instanceRef SIZE_DMA_0)) (portRef CLK (instanceRef SIZE_DMA_1)) @@ -2112,7 +2310,7 @@ )) (net DTACK_c (joined (portRef O (instanceRef DTACK)) - (portRef D (instanceRef DTACK_D0)) + (portRef I0 (instanceRef I_143)) )) (net DTACK (joined (portRef IO (instanceRef DTACK)) @@ -2162,9 +2360,9 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I0 (instanceRef I_154)) + (portRef I0 (instanceRef I_145)) + (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_1)) (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_2)) )) (net RW (joined (portRef IO (instanceRef RW)) @@ -2172,7 +2370,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I1 (instanceRef state_machine_un28_clk_030_5)) + (portRef I0 (instanceRef un19_fpu_cs_4)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -2180,7 +2378,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I0 (instanceRef state_machine_un28_clk_030_3)) + (portRef I1 (instanceRef un19_fpu_cs_4)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -2206,231 +2404,144 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net (rename state_machine_un3_clk_000_d1_i "state_machine.un3_clk_000_d1_i") (joined - (portRef O (instanceRef state_machine_un3_clk_000_d1_i)) - (portRef I1 (instanceRef state_machine_un6_bgack_000)) + (net SM_AMIGA_0_sqmuxa_i (joined + (portRef O (instanceRef SM_AMIGA_0_sqmuxa_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_4)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1)) )) - (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined - (portRef O (instanceRef state_machine_un6_bgack_000)) - (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) + (net DS_000_ENABLE_0_sqmuxa_i (joined + (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1)) )) - (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_1)) - (portRef I0 (instanceRef cpu_est_ns_0_i_1)) + (net un1_SM_AMIGA_0_sqmuxa_1_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1)) + (portRef I1 (instanceRef un1_as_030)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_i_0)) )) - (net N_159_i (joined - (portRef O (instanceRef N_159_i)) - (portRef I1 (instanceRef cpu_est_ns_i_3)) + (net (rename state_machine_un10_clk_000_ne_i "state_machine.un10_clk_000_ne_i") (joined + (portRef O (instanceRef state_machine_un10_clk_000_ne_i)) + (portRef I1 (instanceRef state_machine_un6_clk_000_ne)) )) - (net N_158_i (joined - (portRef O (instanceRef N_158_i)) - (portRef I0 (instanceRef cpu_est_ns_i_3)) + (net (rename state_machine_un4_clk_000_ne_i "state_machine.un4_clk_000_ne_i") (joined + (portRef O (instanceRef state_machine_un4_clk_000_ne_i)) + (portRef I0 (instanceRef state_machine_un6_clk_000_ne)) )) - (net N_149_i (joined - (portRef O (instanceRef cpu_est_ns_i_3)) - (portRef I0 (instanceRef cpu_estse_2_m)) - )) - (net N_150_i (joined - (portRef O (instanceRef cpu_est_ns_i_o2_3)) - (portRef I0 (instanceRef cpu_est_ns_i_o2_i_3)) - (portRef I1 (instanceRef state_machine_un57_clk_000_d0_1)) - )) - (net N_153_i (joined - (portRef O (instanceRef N_153_i)) - (portRef I1 (instanceRef cpu_est_ns_0_1_1)) - )) - (net N_152_i (joined - (portRef O (instanceRef N_152_i)) - (portRef I0 (instanceRef cpu_est_ns_0_1_1)) - )) - (net N_160_i (joined - (portRef O (instanceRef N_160_i)) - (portRef I1 (instanceRef cpu_est_ns_0_2_1)) - )) - (net N_154_i (joined - (portRef O (instanceRef N_154_i)) - (portRef I0 (instanceRef cpu_est_ns_0_2_1)) - )) - (net (rename state_machine_un10_clk_000_d0_2_i "state_machine.un10_clk_000_d0_2_i") (joined - (portRef O (instanceRef state_machine_un10_clk_000_d0_2_i)) - (portRef I1 (instanceRef cpu_est_ns_0_2)) - )) - (net N_156_i (joined - (portRef O (instanceRef N_156_i)) - (portRef I1 (instanceRef cpu_est_ns_0_1_2)) - )) - (net N_157_i (joined - (portRef O (instanceRef N_157_i)) - (portRef I0 (instanceRef cpu_est_ns_0_1_2)) - )) - (net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined - (portRef O (instanceRef cpu_est_ns_0_2)) - (portRef I0 (instanceRef cpu_est_ns_0_i_2)) - )) - (net (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un10_clk_000_d0_i)) - (portRef I1 (instanceRef state_machine_un12_clk_000_d0)) - )) - (net (rename state_machine_un12_clk_000_d0_0 "state_machine.un12_clk_000_d0_0") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_i)) - )) - (net FPU_CS_INT_1_sqmuxa_i (joined - (portRef O (instanceRef FPU_CS_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef un1_as_030_000_sync8_1)) - )) - (net un1_as_030_000_sync8_1_0 (joined - (portRef O (instanceRef un1_as_030_000_sync8_1)) - (portRef I0 (instanceRef un1_as_030_000_sync8_1_i)) - )) - (net AS_030_000_SYNC_0_sqmuxa_2_i (joined - (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2_i)) - (portRef I0 (instanceRef un1_as_030_000_sync8)) - )) - (net un1_as_030_000_sync8_0 (joined - (portRef O (instanceRef un1_as_030_000_sync8)) - (portRef I0 (instanceRef un1_as_030_000_sync8_i)) - )) - (net un1_SM_AMIGA_12_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_12)) - (portRef I0 (instanceRef un1_SM_AMIGA_12_i)) - )) - (net (rename state_machine_un3_clk_030_i "state_machine.un3_clk_030_i") (joined - (portRef O (instanceRef state_machine_un3_clk_030)) - (portRef I0 (instanceRef state_machine_un3_clk_030_i_0)) - )) - (net (rename state_machine_un57_clk_000_d0_i "state_machine.un57_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un57_clk_000_d0_i)) - (portRef I1 (instanceRef state_machine_un53_clk_000_d0)) - )) - (net (rename state_machine_un51_clk_000_d0_i "state_machine.un51_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un51_clk_000_d0_i)) - (portRef I0 (instanceRef state_machine_un53_clk_000_d0)) - )) - (net (rename state_machine_un53_clk_000_d0_0 "state_machine.un53_clk_000_d0_0") (joined - (portRef O (instanceRef state_machine_un53_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un53_clk_000_d0_i)) - )) - (net (rename state_machine_un3_bgack_030_int_d_i "state_machine.un3_bgack_030_int_d_i") (joined - (portRef O (instanceRef state_machine_un3_bgack_030_int_d_i)) - (portRef I0 (instanceRef un1_bgack_030_int_d_1)) - )) - (net un1_bgack_030_int_d_0 (joined - (portRef O (instanceRef un1_bgack_030_int_d)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i)) - )) - (net AMIGA_BUS_ENABLE_INT_3_sqmuxa_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa_i)) - (portRef I1 (instanceRef un1_bgack_030_int_d)) - )) - (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i)) - (portRef I1 (instanceRef un1_bgack_030_int_d_1)) - )) - (net N_86_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_4_0_o2)) - (portRef I0 (instanceRef un1_SM_AMIGA_4_0_o2_i)) - )) - (net N_101_i (joined - (portRef O (instanceRef N_101_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_10_i_o2)) - )) - (net N_85_i (joined - (portRef O (instanceRef un1_SM_AMIGA_10_i_o2)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa)) - (portRef I1 (instanceRef un1_SM_AMIGA_12)) - )) - (net N_84_0 (joined - (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o2)) - (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o2_i)) + (net (rename state_machine_un6_clk_000_ne_i "state_machine.un6_clk_000_ne_i") (joined + (portRef O (instanceRef state_machine_un6_clk_000_ne)) + (portRef I0 (instanceRef state_machine_un6_clk_000_ne_i_0)) )) (net N_97_i (joined (portRef O (instanceRef N_97_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_4)) )) - (net N_74_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_6)) - (portRef D (instanceRef SM_AMIGA_1)) + (net (rename SM_AMIGA_ns_0_4 "SM_AMIGA_ns_0[4]") (joined + (portRef O (instanceRef SM_AMIGA_ns_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) )) - (net N_96_i (joined - (portRef O (instanceRef N_96_i)) + (net N_99_i (joined + (portRef O (instanceRef N_99_i)) (portRef I1 (instanceRef SM_AMIGA_ns_5)) )) - (net N_95_i (joined - (portRef O (instanceRef N_95_i)) + (net N_98_i (joined + (portRef O (instanceRef N_98_i)) (portRef I0 (instanceRef SM_AMIGA_ns_5)) )) (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined (portRef O (instanceRef SM_AMIGA_ns_5)) (portRef I0 (instanceRef SM_AMIGA_ns_i_5)) )) - (net N_88_i (joined - (portRef O (instanceRef N_88_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_0)) + (net N_86_i (joined + (portRef O (instanceRef SM_AMIGA_ns_o3_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_a4_0_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_o3_i_4)) )) - (net N_89_i (joined - (portRef O (instanceRef N_89_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_0)) + (net (rename state_machine_un6_clk_000_p_sync_i "state_machine.un6_clk_000_p_sync_i") (joined + (portRef O (instanceRef state_machine_un6_clk_000_p_sync_i)) + (portRef I1 (instanceRef state_machine_un6_bgack_000)) )) - (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined - (portRef O (instanceRef SM_AMIGA_ns_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) + (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined + (portRef O (instanceRef state_machine_un6_bgack_000)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) )) - (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + (net N_167_i (joined + (portRef O (instanceRef N_167_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0)) )) - (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + (net N_166_i (joined + (portRef O (instanceRef N_166_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0)) )) - (net un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_i)) )) - (net BG_030_c_i (joined - (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef state_machine_un10_bg_030)) + (net N_162_i (joined + (portRef O (instanceRef N_162_i)) + (portRef I1 (instanceRef cpu_est_ns_i_3)) )) - (net (rename state_machine_un8_bg_030_i "state_machine.un8_bg_030_i") (joined - (portRef O (instanceRef state_machine_un8_bg_030_i)) - (portRef I1 (instanceRef state_machine_un10_bg_030)) + (net N_161_i (joined + (portRef O (instanceRef N_161_i)) + (portRef I0 (instanceRef cpu_est_ns_i_3)) )) - (net (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (joined - (portRef O (instanceRef state_machine_un10_bg_030)) - (portRef I0 (instanceRef state_machine_un10_bg_030_i)) + (net N_152_i (joined + (portRef O (instanceRef cpu_est_ns_i_3)) + (portRef I0 (instanceRef cpu_estse_2_m)) )) - (net (rename state_machine_un5_bgack_030_int_d_i "state_machine.un5_bgack_030_int_d_i") (joined - (portRef O (instanceRef state_machine_un5_bgack_030_int_d)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_2)) + (net (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0_i)) + (portRef I1 (instanceRef state_machine_un12_clk_000_d0)) )) - (net N_59_0 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_i)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_i)) + (net (rename state_machine_un5_clk_000_d0_i "state_machine.un5_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_i)) + (portRef I0 (instanceRef state_machine_un12_clk_000_d0)) + )) + (net (rename state_machine_un12_clk_000_d0_0 "state_machine.un12_clk_000_d0_0") (joined + (portRef O (instanceRef state_machine_un12_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un12_clk_000_d0_i)) + )) + (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_1)) + (portRef I0 (instanceRef cpu_est_ns_0_i_1)) + )) + (net N_156_i (joined + (portRef O (instanceRef N_156_i)) + (portRef I1 (instanceRef cpu_est_ns_0_1_1)) + )) + (net N_155_i (joined + (portRef O (instanceRef N_155_i)) + (portRef I0 (instanceRef cpu_est_ns_0_1_1)) + )) + (net N_163_i (joined + (portRef O (instanceRef N_163_i)) + (portRef I0 (instanceRef cpu_est_ns_0_2_1)) + )) + (net (rename state_machine_un5_clk_000_d0_1_i "state_machine.un5_clk_000_d0_1_i") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_1_i)) + (portRef I1 (instanceRef cpu_est_ns_0_2_1)) + )) + (net (rename state_machine_un10_clk_000_d0_2_i "state_machine.un10_clk_000_d0_2_i") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0_2_i)) + (portRef I1 (instanceRef cpu_est_ns_0_2)) + )) + (net N_159_i (joined + (portRef O (instanceRef N_159_i)) + (portRef I1 (instanceRef cpu_est_ns_0_1_2)) + )) + (net N_160_i (joined + (portRef O (instanceRef N_160_i)) + (portRef I0 (instanceRef cpu_est_ns_0_1_2)) + )) + (net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_2)) + (portRef I0 (instanceRef cpu_est_ns_0_i_2)) )) (net (rename state_machine_un10_bgack_030_int_0 "state_machine.un10_bgack_030_int_0") (joined (portRef O (instanceRef state_machine_un10_bgack_030_int)) (portRef I0 (instanceRef state_machine_un10_bgack_030_int_i)) )) - (net N_181_i (joined - (portRef O (instanceRef N_181_i)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7)) - )) - (net A0_c_i (joined - (portRef O (instanceRef A0_c_i)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7)) - (portRef I1 (instanceRef state_machine_un25_clk_000_d0_1)) - )) - (net (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_i)) - )) - (net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_i)) + (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined + (portRef O (instanceRef state_machine_DS_000_DMA_3)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_3_i)) )) (net (rename state_machine_SIZE_DMA_4_0_0 "state_machine.SIZE_DMA_4_0[0]") (joined (portRef O (instanceRef state_machine_SIZE_DMA_4_0)) @@ -2440,82 +2551,6 @@ (portRef O (instanceRef state_machine_SIZE_DMA_4_1)) (portRef I0 (instanceRef state_machine_SIZE_DMA_4_i_1)) )) - (net N_91_i (joined - (portRef O (instanceRef N_91_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_2)) - )) - (net N_68_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_2)) - (portRef D (instanceRef SM_AMIGA_5)) - )) - (net N_100_i (joined - (portRef O (instanceRef N_100_i)) - (portRef I1 (instanceRef un1_SM_AMIGA_8_0)) - )) - (net un1_SM_AMIGA_8_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_8_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_8_0_i)) - )) - (net N_164_i (joined - (portRef O (instanceRef N_164_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0)) - )) - (net N_163_i (joined - (portRef O (instanceRef N_163_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0)) - )) - (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_i)) - )) - (net RW_000_i_m_i (joined - (portRef O (instanceRef RW_000_i_m_i)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv)) - )) - (net RW_li_m_i (joined - (portRef O (instanceRef RW_li_m_i)) - (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv)) - )) - (net (rename state_machine_RW_000_INT_7_iv_i "state_machine.RW_000_INT_7_iv_i") (joined - (portRef O (instanceRef state_machine_RW_000_INT_7_iv)) - (portRef I0 (instanceRef RW_000_INT_0_n)) - )) - (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined - (portRef O (instanceRef SIZE_c_i_1)) - (portRef I1 (instanceRef state_machine_un25_clk_000_d0)) - )) - (net (rename state_machine_un25_clk_000_d0_i "state_machine.un25_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un25_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un25_clk_000_d0_i_0)) - )) - (net N_90_i (joined - (portRef O (instanceRef N_90_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) - )) - (net N_66_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_1)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net N_94_i (joined - (portRef O (instanceRef N_94_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_4)) - )) - (net N_93_i (joined - (portRef O (instanceRef N_93_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_4)) - )) - (net (rename SM_AMIGA_ns_0_4 "SM_AMIGA_ns_0[4]") (joined - (portRef O (instanceRef SM_AMIGA_ns_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) - )) - (net N_87_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_1)) - )) - (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined - (portRef O (instanceRef state_machine_DS_000_DMA_3)) - (portRef I0 (instanceRef state_machine_DS_000_DMA_3_i)) - )) (net CLK_030_H_i (joined (portRef O (instanceRef CLK_030_H_i)) (portRef I1 (instanceRef state_machine_CLK_030_H_2_f1)) @@ -2537,101 +2572,220 @@ (portRef OE (instanceRef SIZE_0)) (portRef OE (instanceRef SIZE_1)) )) + (net (rename state_machine_un5_bgack_030_int_d_i "state_machine.un5_bgack_030_int_d_i") (joined + (portRef O (instanceRef state_machine_un5_bgack_030_int_d)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + )) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + )) + (net un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + )) + (net (rename state_machine_RW_000_INT_3_0 "state_machine.RW_000_INT_3_0") (joined + (portRef O (instanceRef state_machine_RW_000_INT_3)) + (portRef I0 (instanceRef state_machine_RW_000_INT_3_i)) + )) + (net N_66_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_6_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_6_i_i)) + )) + (net N_91_i (joined + (portRef O (instanceRef N_91_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0)) + )) + (net N_93_i (joined + (portRef O (instanceRef N_93_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) + )) + (net N_69_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_1)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o4_1)) + )) + (net N_84_0 (joined + (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o4)) + (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o4_i)) + )) + (net AMIGA_BUS_ENABLE_INT_3_sqmuxa_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa_i)) + (portRef I1 (instanceRef un1_bgack_030_int_d)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i)) + (portRef I1 (instanceRef un1_bgack_030_int_d_1)) + )) + (net (rename state_machine_un3_bgack_030_int_d_i "state_machine.un3_bgack_030_int_d_i") (joined + (portRef O (instanceRef state_machine_un3_bgack_030_int_d_i)) + (portRef I0 (instanceRef un1_bgack_030_int_d_1)) + )) + (net un1_bgack_030_int_d_0 (joined + (portRef O (instanceRef un1_bgack_030_int_d)) + (portRef I0 (instanceRef un1_bgack_030_int_d_i)) + )) + (net N_87_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_1)) + )) + (net N_85_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o3_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_7)) + )) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_7)) + )) (net N_92_i (joined (portRef O (instanceRef N_92_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_0)) )) - (net N_70_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_3)) - (portRef D (instanceRef SM_AMIGA_4)) + (net N_76_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_7)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_100_i (joined + (portRef O (instanceRef N_100_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_6)) + )) + (net N_101_i (joined + (portRef O (instanceRef N_101_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_6)) + )) + (net (rename SM_AMIGA_ns_0_6 "SM_AMIGA_ns_0[6]") (joined + (portRef O (instanceRef SM_AMIGA_ns_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) + )) + (net N_95_i (joined + (portRef O (instanceRef N_95_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_3)) + )) + (net N_96_i (joined + (portRef O (instanceRef N_96_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_3)) + )) + (net (rename SM_AMIGA_ns_0_3 "SM_AMIGA_ns_0[3]") (joined + (portRef O (instanceRef SM_AMIGA_ns_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) + )) + (net N_94_i (joined + (portRef O (instanceRef N_94_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_2)) + )) + (net (rename SM_AMIGA_ns_0_2 "SM_AMIGA_ns_0[2]") (joined + (portRef O (instanceRef SM_AMIGA_ns_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) + )) + (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) + )) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef state_machine_un10_bg_030)) + )) + (net (rename state_machine_un8_bg_030_i "state_machine.un8_bg_030_i") (joined + (portRef O (instanceRef state_machine_un8_bg_030_i)) + (portRef I1 (instanceRef state_machine_un10_bg_030)) + )) + (net (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (joined + (portRef O (instanceRef state_machine_un10_bg_030)) + (portRef I0 (instanceRef state_machine_un10_bg_030_i)) + )) + (net LDS_000_INT_i (joined + (portRef O (instanceRef LDS_000_INT_i)) + (portRef I1 (instanceRef un1_LDS_000_INT)) + )) + (net un1_LDS_000_INT_0 (joined + (portRef O (instanceRef un1_LDS_000_INT)) + (portRef I0 (instanceRef un1_LDS_000_INT_i)) + )) + (net UDS_000_INT_i (joined + (portRef O (instanceRef UDS_000_INT_i)) + (portRef I1 (instanceRef un1_UDS_000_INT)) + )) + (net un1_UDS_000_INT_0 (joined + (portRef O (instanceRef un1_UDS_000_INT)) + (portRef I0 (instanceRef un1_UDS_000_INT_i)) + )) + (net (rename state_machine_un7_ds_030_i "state_machine.un7_ds_030_i") (joined + (portRef O (instanceRef state_machine_un7_ds_030)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + )) + (net A0_c_i (joined + (portRef O (instanceRef A0_c_i)) + (portRef I1 (instanceRef state_machine_un7_ds_030_1)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I0 (instanceRef state_machine_un7_ds_030_1)) + )) + (net un1_bgack_030_int_d_0_1 (joined + (portRef O (instanceRef un1_bgack_030_int_d_1)) + (portRef I0 (instanceRef un1_bgack_030_int_d)) + )) + (net N_84_0_1 (joined + (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o4_1)) + (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o4)) + )) + (net N_84_0_2 (joined + (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o4_2)) + (portRef I1 (instanceRef un1_amiga_bus_enable_int5_0_o4)) )) (net un3_dtack_i_1 (joined (portRef O (instanceRef un3_dtack_1)) (portRef I0 (instanceRef un3_dtack)) )) - (net (rename state_machine_un25_clk_000_d0_i_1 "state_machine.un25_clk_000_d0_i_1") (joined - (portRef O (instanceRef state_machine_un25_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un25_clk_000_d0)) - )) (net (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (joined (portRef O (instanceRef cpu_est_ns_0_1_2)) (portRef I0 (instanceRef cpu_est_ns_0_2)) )) - (net N_210_1 (joined + (net N_198_1 (joined (portRef O (instanceRef un4_ciin_1)) (portRef I0 (instanceRef un4_ciin)) )) - (net N_210_2 (joined + (net N_198_2 (joined (portRef O (instanceRef un4_ciin_2)) (portRef I1 (instanceRef un4_ciin)) )) - (net N_220_1 (joined + (net N_207_1 (joined (portRef O (instanceRef un8_ciin_1)) (portRef I0 (instanceRef un8_ciin_5)) )) - (net N_220_2 (joined + (net N_207_2 (joined (portRef O (instanceRef un8_ciin_2)) (portRef I1 (instanceRef un8_ciin_5)) )) - (net N_220_3 (joined + (net N_207_3 (joined (portRef O (instanceRef un8_ciin_3)) (portRef I0 (instanceRef un8_ciin_6)) )) - (net N_220_4 (joined + (net N_207_4 (joined (portRef O (instanceRef un8_ciin_4)) (portRef I1 (instanceRef un8_ciin_6)) )) - (net N_220_5 (joined + (net N_207_5 (joined (portRef O (instanceRef un8_ciin_5)) (portRef I0 (instanceRef un8_ciin)) )) - (net N_220_6 (joined + (net N_207_6 (joined (portRef O (instanceRef un8_ciin_6)) (portRef I1 (instanceRef un8_ciin)) )) - (net DS_000_DMA_1_sqmuxa_1 (joined - (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1)) - (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa)) - )) - (net UDS_000_INT_0_sqmuxa_1_1 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) - )) - (net UDS_000_INT_0_sqmuxa_1_2 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) - )) - (net UDS_000_INT_0_sqmuxa_1_0 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) - (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) - )) - (net UDS_000_INT_0_sqmuxa_2 (joined - (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) - )) - (net N_164_1_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) - )) - (net RW_li_m_1 (joined - (portRef O (instanceRef RW_li_m_1)) - (portRef I0 (instanceRef RW_li_m)) - )) - (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) - )) - (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_2)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) - )) - (net N_101_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_10_i_a3_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_10_i_a3)) - )) - (net un1_bgack_030_int_d_0_1 (joined - (portRef O (instanceRef un1_bgack_030_int_d_1)) - (portRef I0 (instanceRef un1_bgack_030_int_d)) + (net (rename state_machine_un7_ds_030_i_1 "state_machine.un7_ds_030_i_1") (joined + (portRef O (instanceRef state_machine_un7_ds_030_1)) + (portRef I0 (instanceRef state_machine_un7_ds_030)) )) (net (rename state_machine_un8_bg_030_1 "state_machine.un8_bg_030_1") (joined (portRef O (instanceRef state_machine_un8_bg_030_1)) @@ -2641,49 +2795,29 @@ (portRef O (instanceRef state_machine_un8_bg_030_2)) (portRef I1 (instanceRef state_machine_un8_bg_030)) )) - (net (rename state_machine_un57_clk_000_d0_1 "state_machine.un57_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un57_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un57_clk_000_d0)) + (net DSACK1_INT_0_sqmuxa_1 (joined + (portRef O (instanceRef DSACK1_INT_0_sqmuxa_1)) + (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa)) )) - (net (rename state_machine_un49_clk_000_d0_1 "state_machine.un49_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un49_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un49_clk_000_d0)) - )) - (net AS_030_000_SYNC_0_sqmuxa_1 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + (net AS_030_000_SYNC_0_sqmuxa_1_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_1_0)) (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa)) )) - (net AS_030_000_SYNC_0_sqmuxa_2_0 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2_0)) + (net AS_030_000_SYNC_0_sqmuxa_2 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa)) )) - (net (rename state_machine_un28_clk_030_1 "state_machine.un28_clk_030_1") (joined - (portRef O (instanceRef state_machine_un28_clk_030_1)) - (portRef I0 (instanceRef state_machine_un28_clk_030_4)) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) )) - (net (rename state_machine_un28_clk_030_2 "state_machine.un28_clk_030_2") (joined - (portRef O (instanceRef state_machine_un28_clk_030_2)) - (portRef I1 (instanceRef state_machine_un28_clk_030_4)) + (net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_1_1)) + (portRef I0 (instanceRef cpu_est_ns_0_1)) )) - (net (rename state_machine_un28_clk_030_3 "state_machine.un28_clk_030_3") (joined - (portRef O (instanceRef state_machine_un28_clk_030_3)) - (portRef I0 (instanceRef state_machine_un28_clk_030_5)) - )) - (net (rename state_machine_un28_clk_030_4 "state_machine.un28_clk_030_4") (joined - (portRef O (instanceRef state_machine_un28_clk_030_4)) - (portRef I0 (instanceRef state_machine_un28_clk_030)) - )) - (net (rename state_machine_un28_clk_030_5 "state_machine.un28_clk_030_5") (joined - (portRef O (instanceRef state_machine_un28_clk_030_5)) - (portRef I1 (instanceRef state_machine_un28_clk_030)) - )) - (net (rename state_machine_un5_clk_000_d0_1 "state_machine.un5_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un5_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un5_clk_000_d0)) - )) - (net (rename state_machine_un5_clk_000_d0_2 "state_machine.un5_clk_000_d0_2") (joined - (portRef O (instanceRef state_machine_un5_clk_000_d0_2)) - (portRef I1 (instanceRef state_machine_un5_clk_000_d0)) + (net (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_2_1)) + (portRef I1 (instanceRef cpu_est_ns_0_1)) )) (net (rename state_machine_un10_clk_000_d0_1 "state_machine.un10_clk_000_d0_1") (joined (portRef O (instanceRef state_machine_un10_clk_000_d0_1)) @@ -2697,137 +2831,53 @@ (portRef O (instanceRef state_machine_un10_clk_000_d0_3)) (portRef I0 (instanceRef state_machine_un10_clk_000_d0)) )) - (net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_1_1)) - (portRef I0 (instanceRef cpu_est_ns_0_1)) + (net (rename state_machine_CLK_000_N_SYNC_2_1_0 "state_machine.CLK_000_N_SYNC_2_1[0]") (joined + (portRef O (instanceRef state_machine_CLK_000_N_SYNC_2_1_0)) + (portRef I0 (instanceRef state_machine_CLK_000_N_SYNC_2_0)) )) - (net (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_2_1)) - (portRef I1 (instanceRef cpu_est_ns_0_1)) + (net (rename state_machine_CLK_000_N_SYNC_2_2_0 "state_machine.CLK_000_N_SYNC_2_2[0]") (joined + (portRef O (instanceRef state_machine_CLK_000_N_SYNC_2_2_0)) + (portRef I1 (instanceRef state_machine_CLK_000_N_SYNC_2_0)) )) - (net (rename state_machine_un28_clk_000_d1_1 "state_machine.un28_clk_000_d1_1") (joined - (portRef O (instanceRef state_machine_un28_clk_000_d1_1)) - (portRef I0 (instanceRef state_machine_un28_clk_000_d1)) + (net (rename state_machine_CLK_000_P_SYNC_3_1_0 "state_machine.CLK_000_P_SYNC_3_1[0]") (joined + (portRef O (instanceRef state_machine_CLK_000_P_SYNC_3_1_0)) + (portRef I0 (instanceRef state_machine_CLK_000_P_SYNC_3_0)) )) - (net (rename cpu_estse_2_un3 "cpu_estse_2.un3") (joined - (portRef O (instanceRef cpu_estse_2_r)) - (portRef I1 (instanceRef cpu_estse_2_n)) + (net N_167_1_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) )) - (net (rename cpu_estse_2_un1 "cpu_estse_2.un1") (joined - (portRef O (instanceRef cpu_estse_2_m)) - (portRef I0 (instanceRef cpu_estse_2_p)) + (net un19_fpu_cs_1 (joined + (portRef O (instanceRef un19_fpu_cs_1)) + (portRef I0 (instanceRef un19_fpu_cs_5)) )) - (net (rename cpu_estse_2_un0 "cpu_estse_2.un0") (joined - (portRef O (instanceRef cpu_estse_2_n)) - (portRef I1 (instanceRef cpu_estse_2_p)) + (net un19_fpu_cs_2 (joined + (portRef O (instanceRef un19_fpu_cs_2)) + (portRef I1 (instanceRef un19_fpu_cs_5)) )) - (net (rename cpu_estse_1_un3 "cpu_estse_1.un3") (joined - (portRef O (instanceRef cpu_estse_1_r)) - (portRef I1 (instanceRef cpu_estse_1_n)) + (net un19_fpu_cs_3 (joined + (portRef O (instanceRef un19_fpu_cs_3)) + (portRef I0 (instanceRef un19_fpu_cs_6)) )) - (net (rename cpu_estse_1_un1 "cpu_estse_1.un1") (joined - (portRef O (instanceRef cpu_estse_1_m)) - (portRef I0 (instanceRef cpu_estse_1_p)) + (net un19_fpu_cs_4 (joined + (portRef O (instanceRef un19_fpu_cs_4)) + (portRef I1 (instanceRef un19_fpu_cs_6)) )) - (net (rename cpu_estse_1_un0 "cpu_estse_1.un0") (joined - (portRef O (instanceRef cpu_estse_1_n)) - (portRef I1 (instanceRef cpu_estse_1_p)) + (net un19_fpu_cs_5 (joined + (portRef O (instanceRef un19_fpu_cs_5)) + (portRef I0 (instanceRef un19_fpu_cs)) )) - (net (rename cpu_estse_0_un3 "cpu_estse_0.un3") (joined - (portRef O (instanceRef cpu_estse_0_r)) - (portRef I1 (instanceRef cpu_estse_0_n)) + (net un19_fpu_cs_6 (joined + (portRef O (instanceRef un19_fpu_cs_6)) + (portRef I1 (instanceRef un19_fpu_cs)) )) - (net (rename cpu_estse_0_un1 "cpu_estse_0.un1") (joined - (portRef O (instanceRef cpu_estse_0_m)) - (portRef I0 (instanceRef cpu_estse_0_p)) + (net DS_000_ENABLE_0_sqmuxa_1 (joined + (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_1)) + (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa)) )) - (net (rename cpu_estse_0_un0 "cpu_estse_0.un0") (joined - (portRef O (instanceRef cpu_estse_0_n)) - (portRef I1 (instanceRef cpu_estse_0_p)) - )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) - )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) - )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) - )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) - )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) - )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) - )) - (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined - (portRef O (instanceRef FPU_CS_INT_0_r)) - (portRef I1 (instanceRef FPU_CS_INT_0_n)) - )) - (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined - (portRef O (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_p)) - )) - (net (rename FPU_CS_INT_0_un0 "FPU_CS_INT_0.un0") (joined - (portRef O (instanceRef FPU_CS_INT_0_n)) - (portRef I1 (instanceRef FPU_CS_INT_0_p)) - )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) - )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) - )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) + (net (rename state_machine_un10_clk_000_ne_1_0 "state_machine.un10_clk_000_ne_1_0") (joined + (portRef O (instanceRef state_machine_un10_clk_000_ne_1_0)) + (portRef I0 (instanceRef state_machine_un10_clk_000_ne)) )) (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined (portRef O (instanceRef DSACK1_INT_0_r)) @@ -2841,6 +2891,30 @@ (portRef O (instanceRef DSACK1_INT_0_n)) (portRef I1 (instanceRef DSACK1_INT_0_p)) )) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) + )) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename cpu_estse_0_un3 "cpu_estse_0.un3") (joined + (portRef O (instanceRef cpu_estse_0_r)) + (portRef I1 (instanceRef cpu_estse_0_n)) + )) + (net (rename cpu_estse_0_un1 "cpu_estse_0.un1") (joined + (portRef O (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_estse_0_p)) + )) + (net (rename cpu_estse_0_un0 "cpu_estse_0.un0") (joined + (portRef O (instanceRef cpu_estse_0_n)) + (portRef I1 (instanceRef cpu_estse_0_p)) + )) (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined (portRef O (instanceRef VMA_INT_0_r)) (portRef I1 (instanceRef VMA_INT_0_n)) @@ -2853,65 +2927,53 @@ (portRef O (instanceRef VMA_INT_0_n)) (portRef I1 (instanceRef VMA_INT_0_p)) )) - (net (rename avec_exp_0_un3 "avec_exp_0.un3") (joined - (portRef O (instanceRef avec_exp_0_r)) - (portRef I1 (instanceRef avec_exp_0_n)) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) )) - (net (rename avec_exp_0_un1 "avec_exp_0.un1") (joined - (portRef O (instanceRef avec_exp_0_m)) - (portRef I0 (instanceRef avec_exp_0_p)) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) )) - (net (rename avec_exp_0_un0 "avec_exp_0.un0") (joined - (portRef O (instanceRef avec_exp_0_n)) - (portRef I1 (instanceRef avec_exp_0_p)) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) + (net (rename cpu_estse_2_un3 "cpu_estse_2.un3") (joined + (portRef O (instanceRef cpu_estse_2_r)) + (portRef I1 (instanceRef cpu_estse_2_n)) )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) + (net (rename cpu_estse_2_un1 "cpu_estse_2.un1") (joined + (portRef O (instanceRef cpu_estse_2_m)) + (portRef I0 (instanceRef cpu_estse_2_p)) )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined - (portRef O (instanceRef RW_000_INT_0_r)) - (portRef I1 (instanceRef RW_000_INT_0_n)) - )) - (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined - (portRef O (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_p)) - )) - (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined - (portRef O (instanceRef RW_000_INT_0_n)) - (portRef I1 (instanceRef RW_000_INT_0_p)) + (net (rename cpu_estse_2_un0 "cpu_estse_2.un0") (joined + (portRef O (instanceRef cpu_estse_2_n)) + (portRef I1 (instanceRef cpu_estse_2_p)) )) (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined (portRef O (instanceRef AS_000_DMA_0_r)) @@ -2937,6 +2999,18 @@ (portRef O (instanceRef DS_000_DMA_0_n)) (portRef I1 (instanceRef DS_000_DMA_0_p)) )) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) + )) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) + )) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) + )) (net (rename CLK_030_H_0_un3 "CLK_030_H_0.un3") (joined (portRef O (instanceRef CLK_030_H_0_r)) (portRef I1 (instanceRef CLK_030_H_0_n)) @@ -2949,6 +3023,114 @@ (portRef O (instanceRef CLK_030_H_0_n)) (portRef I1 (instanceRef CLK_030_H_0_p)) )) + (net (rename cpu_estse_1_un3 "cpu_estse_1.un3") (joined + (portRef O (instanceRef cpu_estse_1_r)) + (portRef I1 (instanceRef cpu_estse_1_n)) + )) + (net (rename cpu_estse_1_un1 "cpu_estse_1.un1") (joined + (portRef O (instanceRef cpu_estse_1_m)) + (portRef I0 (instanceRef cpu_estse_1_p)) + )) + (net (rename cpu_estse_1_un0 "cpu_estse_1.un0") (joined + (portRef O (instanceRef cpu_estse_1_n)) + (portRef I1 (instanceRef cpu_estse_1_p)) + )) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) + )) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) + )) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) + )) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_INT_0_un3 "AMIGA_BUS_ENABLE_INT_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_INT_0_un1 "AMIGA_BUS_ENABLE_INT_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_INT_0_un0 "AMIGA_BUS_ENABLE_INT_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_0_p)) + )) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) + )) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) + )) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined + (portRef O (instanceRef DS_000_ENABLE_0_r)) + (portRef I1 (instanceRef DS_000_ENABLE_0_n)) + )) + (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined + (portRef O (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined + (portRef O (instanceRef DS_000_ENABLE_0_n)) + (portRef I1 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index 78a2dab..565d0ec 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,46 +1,46 @@ -fsm_encoding {7129321291} onehot +fsm_encoding {7135321351} onehot -fsm_state_encoding {7129321291} idle_p {00000001} +fsm_state_encoding {7135321351} idle_p {00000001} -fsm_state_encoding {7129321291} idle_n {00000010} +fsm_state_encoding {7135321351} idle_n {00000010} -fsm_state_encoding {7129321291} as_set_p {00000100} +fsm_state_encoding {7135321351} as_set_p {00000100} -fsm_state_encoding {7129321291} as_set_n {00001000} +fsm_state_encoding {7135321351} as_set_n {00001000} -fsm_state_encoding {7129321291} sample_dtack_p {00010000} +fsm_state_encoding {7135321351} sample_dtack_p {00010000} -fsm_state_encoding {7129321291} data_fetch_n {00100000} +fsm_state_encoding {7135321351} data_fetch_n {00100000} -fsm_state_encoding {7129321291} data_fetch_p {01000000} +fsm_state_encoding {7135321351} data_fetch_p {01000000} -fsm_state_encoding {7129321291} end_cycle_n {10000000} +fsm_state_encoding {7135321351} end_cycle_n {10000000} -fsm_registers {7129321291} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} +fsm_registers {7135321351} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} -fsm_encoding {7120341202} original +fsm_encoding {7125341252} original -fsm_state_encoding {7120341202} e20 {0000} +fsm_state_encoding {7125341252} e20 {0000} -fsm_state_encoding {7120341202} e5 {0010} +fsm_state_encoding {7125341252} e5 {0010} -fsm_state_encoding {7120341202} e6 {0011} +fsm_state_encoding {7125341252} e6 {0011} -fsm_state_encoding {7120341202} e3 {0100} +fsm_state_encoding {7125341252} e3 {0100} -fsm_state_encoding {7120341202} e4 {0101} +fsm_state_encoding {7125341252} e4 {0101} -fsm_state_encoding {7120341202} e1 {0110} +fsm_state_encoding {7125341252} e1 {0110} -fsm_state_encoding {7120341202} e2 {0111} +fsm_state_encoding {7125341252} e2 {0111} -fsm_state_encoding {7120341202} e7 {1010} +fsm_state_encoding {7125341252} e7 {1010} -fsm_state_encoding {7120341202} e8 {1011} +fsm_state_encoding {7125341252} e8 {1011} -fsm_state_encoding {7120341202} e9 {1100} +fsm_state_encoding {7125341252} e9 {1100} -fsm_state_encoding {7120341202} e10 {1111} +fsm_state_encoding {7125341252} e10 {1111} -fsm_registers {7120341202} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]} +fsm_registers {7125341252} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 60e4a44..53f8941 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sat Jun 07 23:03:13 2014 +#-- Written on Mon Jun 09 10:27:18 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 5810250..bb39612 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -312,6 +312,16 @@ F@:@U64d:::6d.qj:vqQt_1Az_q hA_p pRmWqtvQqz_A1h_ q Ap_Wpm;H NR03sDs_FHNoMl"CRqtvQqz_A1h_ q Ap_Wpm"F; RU@@::6c4c:6:Bc:QRQhBhQQ;H NR03sDs_FHNoMl"CRBhQQ"o; +MMRk47_p1j_jjh_QaN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRMz4_7j1_jQj_h +a;N3MR#CNP_0MC_NVDoR#4.;6n +RoMk_M41qv_vqQt_#j_JGlkN;_4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kM__N#j;dj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kMgb_Vk#_O;M +NRN3#PMC_CV0_D#No46R.no; M_Rh4N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ @@ -364,133 +374,81 @@ oR.h_6N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;.n RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_j -.;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_4dN; +oR.h_(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_c4j;M +n;ohMR_d4j;M NRN3#PMC_CV0_D#No46R.no; -M_Rh4;j6 +M_Rh4;jc RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_j -n;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_4(N; +6;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhj_4nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_U4j;M +n;ohMR_(4j;M NRN3#PMC_CV0_D#No46R.no; -M_Rh4;jg +M_Rh4;jU +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_j +g;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh4_4jN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_444;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh4;4. RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_4 -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_44N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_.44;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh.;4j -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_. -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMO_bkC##0C3_.k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C##.C_34kM;M -NRN3#PMC_CV0_D#No46R.no; -MbROk#_C0_#C.M3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#C0#_k43M d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMO_bkC##0C3_4k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C##4C_3jkM;M +RoMhg_4UN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_(.j;M NRN3#PMC_CV0_D#No46R.no; -MbROk#_C0_#CjM3kdN; +M1R7q4Bi_aQh_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoM7B1qiQ4_hja_34kM;M +NRN3#PMC_CV0_D#No46R.no; +M1R7q4Bi_aQh_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMABtqid_jjh_Qa3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRqAtBji_dQj_hja_34kM;M +NRN3#PMC_CV0_D#No46R.no; +MtRAq_Bij_djQ_hajM3kjN; M#R3N_PCM_C0VoDN#.4R6 n;oOMRbCk_#C0#_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMO_bkC##0C3_jk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_.j__M3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3._k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_.j__M3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__34_k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_4j__M3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__34_k;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_jj__M3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oQMRujp_djj__3j_k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRpQu_jjd_jj__M3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;oAMRtiqB_jjd_aQh_kj3M d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMABtqid_jjh_Qa3_jk;M4 +RoMO_bkC##0C3_jk;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqAtBji_dQj_hja_3jkM;M +oRkOb_0C##jC_3jkM;M NRN3#PMC_CV0_D#No46R.no; -M1Rq_jjd_jjj_h1YB3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_djj_jj1BYh_kj3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMqj1_djj_j1j_Y_hBjM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;owMRuBz_1h_Qa3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRzwu__B1Q_hajM3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;owMRuBz_1h_Qa3_jk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1j_jjh_Qa3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;o7MR1iqB4h_Qa3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRq71B_i4Q_hajM3k4N; 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+M#R3N_PCM_C0VoDN#.4R6 +n;oQMRujp_djj__3._k;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRpQu_jjd_.j__M3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oQMRujp_djj__3._k;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRkOb_0C##.C_3dkM;M NRN3#PMC_CV0_D#No46R.no; -MWR)_jjj_aQh_kj3M -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoM)jW_jQj_hja_34kM;M -NRN3#PMC_CV0_D#No46R.no; -MWR)_jjj_aQh_kj3M +MbROk#_C0_#C.M3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oOMRbCk_#C0#_k.3M j;N3MR#CNP_0MC_NVDoR#4.;6n RoMqj1_j7j_vjq_3dkM;M NRN3#PMC_CV0_D#No46R.no; @@ -504,42 +462,87 @@ RoM7j1_j7j_vjq_34kM;M NRN3#PMC_CV0_D#No46R.no; M1R7_jjj_q7v_kj3M j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMB_pij_dj]3_jk;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRiBp_jjd_j]_34kM;M +RoM)jW_j7j_vjq_3dkM;M NRN3#PMC_CV0_D#No46R.no; -MpRBid_jj__]jM3kjN; +MWR)_jjj_q7v_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoM)jW_j7j_vjq_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MpRBid_jj__]jM3kdN; M#R3N_PCM_C0VoDN#.4R6 -n;b@R@4::44::4..+4:k0sCjRf:0jRsRkC0CskRBeB;R -b@:@44::44+:.4V.:NCD#R:fjjNRVDR#CV#NDChRt7b; -RU@@:g4.::d.4:.gd4c+.v:1_Qqvtjqr:R(9fjj:RFoE#10Rvv_qQrtqj9:(R4h_g_,h.hj,_,.4h._.,.h_d_,h.hc,_,.6hn_.;H -NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(g4.d..4g;4" -RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H -NR#3Vls_VF0l#Rv"1_QqvtdqR"N; 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+HVR3#Fl_sMHoNRlC"_1vqtvQq +";N3HRV_#l#00NCosCR +4;N3HR#00NCN_lbMbHoRR"RjRjjjjjj-4R>jRjjjjjjM4\RjRRjjjjjR4j-j>Rjjjjj\4jMRRRjjjjjj4jRR->jjjjjj4j\RMRRjjjjj4jj>R-Rjjjjj4jjR\MRjRjjj4jj-jR>jRjjj4jjMj\RjRRjj4jjRjj-j>Rjj4jj\jjMRRRjj4jjjjjRR->jj4jjjjj\RMRRj4jjjjjj>R-Rj4jjjjjj"\M;R +b@:@U4:.6d4c:.d6:n.+4:kOb_0C#r4j:jf9RjR:jo#EF0bROk#_C0:rj4Rj9hj_4d_,h4,jchj_46_,h4,jnhj_4(_,h4,jUhj_4g_,h4,4jh4_44_,h4,4.h4_4dN; +HsR30_DC04FR;H +NRM#$_lV#_RH8".(464dc."6.;H NR03sDs_FHNoMl"CRO_bkC"#0;H NRM#$_OCMFM8HoFR"sHHoM"ND;H NR#3Vls_VF0l#Rb"Ok#_C0"Rc;H @@ -547,14 +550,14 @@ NR#3VlF_0#"0RO_bkCR#0c ";N3HRV_#l0DNLCR#0"jjjjjRjjjjsjR4jjjj4s4jj4jRj4j4s4Rjjjj4jsjj444Rjjj4s4R4jjj44s4j444Rj444sjR4j4jj4s44j4jR4444s4Rjj4j4js44444R44"4s;H NR#3Vls_FHNoMl"CRO_bkC"#0;H NR#3Vl0_#Ns0CC4oR;H -NRs3FHMoH#N0Ml'CRO_bkCr#0jj:49 -';s@R@U.:4jc:d:j4.:+dn4O.:bCk_#j0r:94jR:fjjNRlO7ERw]w)RHbslbROk#_C09r. -=STO_bkCr#0.S9 -7b=Ok#_C0#_M_.Cr9B +NR03#N_0ClbNbHRMo"RRRjjjjjjjjjRj4-j>Rj\jjMRRRjjjjjjjjjR4j-j>Rj\4jMRRRjjjjjjjj4Rjj-j>Rj\44MRRRjjjjj4jjjRjj-j>R4\jjMRRRjjjjjjj4jRjj-j>R4\j4MRRRjjjjjj4jjRjj-j>R4\4jMRRRjjjj4jjjjRjj-j>R4\44MRRRj4jjjjjjjRjj-4>Rj\4jMRRRjjj4jjjjjRjj-4>Rj\44MRRRjj4jjjjjjRjj-4>R4\jjMRRR4jjjjjjjjRjj-4>R4\44M +";s@R@U.:46c:d:64.:+dn4O.:bCk_#j0r:94jR:fjjNRlO7ERw]w)RHbslbROk#_C09rj +=STO_bkCr#0jS9 +7b=Ok#_C0#_M_jCr9B SpBi=pmi_1_ZQO) S=a)1_ H;N3HRsC0D_R0F4N; -H$R#M#_Vl8_HR4"(.cjd4..j"N; +H$R#M#_Vl8_HR4"(.c6d4..6"N; HsR30FD_sMHoNRlC"kOb_0C#"N; H$R#MM_COHF8M"oRFosHHDMN"N; HVR3#Vl_s#Fl0OR"bCk_#c0R"N; @@ -563,13 +566,13 @@ RNH3lV#_L0ND0C#Rj"jjjjRjsjjjjj4R4jjjjsj4j4Rjs44jj4jRjj4j4sjjj4R4sj4jj44R4j4j4sj4 HVR3#Fl_sMHoNRlC"kOb_0C#"N; HVR3##l_0CN0sRCo4N; HFR3sHHoMM#0NRlC'kOb_0C#r4j:j;9' -@sR@4U:.dj:c.:4jn:d+:4.O_bkCr#0jj:49jRf:ljRNROE7)ww]sRbHOlRbCk_#d0r9T +@sR@4U:.d6:c.:46n:d+:4.O_bkCr#0jj:49jRf:ljRNROE7)ww]sRbHOlRbCk_#40r9T S=kOb_0C#r -d9SO7=bCk_#M0_#r_CdS9 +49SO7=bCk_#M0_#r_C4S9 B=piB_pimQ1Z_SO )1=)a;_H RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4d.jcj4.. +4;N#HR$VM_#Hl_8(R"4d.6c64.. ";N3HRs_0DFosHMCNlRb"Ok#_C0 ";N#HR$CM_M8OFHRMo"HFsoNHMD ";N3HRV_#lVlsF#"0RO_bkCR#0c @@ -578,13 +581,13 @@ NR#3VlN_0L#DC0jR"jRjjjjjjs4jjjjRj4jjsjR44j4j4sjj4j4Rjjjjs4Rj4j44js4j4j4Rj4jjs4R4 ";N3HRV_#lFosHMCNlRb"Ok#_C0 ";N3HRV_#l#00NCosCR 4;N3HRFosHH0M#MCNlRb'Ok#_C0:rj4'j9;R -s@:@U4:.jd4c:.dj:n.+4:kOb_0C#r4j:jf9RjR:jlENORw7w)b]RsRHlO_bkCr#0jS9 -Tb=Ok#_C09rj +s@:@U4:.6d4c:.d6:n.+4:kOb_0C#r4j:jf9RjR:jlENORw7w)b]RsRHlO_bkCr#0.S9 +Tb=Ok#_C09r. =S7O_bkC_#0MC#_r -j9SiBp=iBp_Zm1Q +.9SiBp=iBp_Zm1Q _OS))=1Ha_;H NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(j4.d.c4j;." +RNH#_$MV_#lH"8R(64.d.c46;." RNH3Ds0_HFsolMNCOR"bCk_#;0" RNH#_$MCFMO8oHMRs"FHMoHN;D" RNH3lV#_FVslR#0"kOb_0C#R;c" @@ -593,34 +596,28 @@ HVR3#0l_NCLD#"0RjjjjRjjjjjsj4jjRjs4jj4j4R4jj44sjjjjR4sjjj44jRjj444sj4jjR4s4jj444 RNH3lV#_HFsolMNCOR"bCk_#;0" RNH3lV#_N#00CCso;R4 RNH3HFso#HM0lMNCOR'bCk_#j0r:94j's; -RU@@:.4j::dn4:j.d4U+.u:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r -j9SQT=ujp_dOj_r -j9Sh7=_ -4nSiBp=iBp_Zm1Q -_OS)1=1Ha_;H -NR03sDs_FHNoMl"CRQ_upj"dj;H -NRM3kVOsN_8HMCjGR;R -s@:@U4:j.d4n:jd.:U.+4:pQu_jjdrj.:9jRf:ljRNROE71ww]sRbHQlRujp_dwj7wr1]4S9 -Tu=Qpd_jjr_O4S9 -7_=h4S( -B=piB_pimQ1Z_SO -11=)a;_H -RNH3Ds0_HFsolMNCQR"ujp_d;j" -RNH3VkMs_NOHCM8G;R4 -@sR@4U:jd.:nj:4.U:d+:4.Q_upjrdj.9:jR:fjjNRlO7ERw]w1RHbsluRQpd_jjw7w1.]r9T -S=pQu_jjd_.Or97 -S=4h_UB -SpBi=pmi_1_ZQO1 -S=a)1_ -H;N3HRs_0DFosHMCNlRu"Qpd_jj -";N3HRksMVNHO_MG8CR -.;s@R@Un:.c(:.:c.n:+cc41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w1RHbslvR1_Qqvt(qr9T +RU@@:64.::dc4:.6d4n+.b:Ok#_C0:rj4Rj9fjj:ROlNEwR7wR)]blsHRkOb_0C#r +d9SOT=bCk_#d0r97 +S=kOb_0C#__M#C9rd +pSBip=Bi1_mZOQ_ +=S))_1aHN; +HsR30_DC04FR;H +NRM#$_lV#_RH8".(464dc."6.;H +NR03sDs_FHNoMl"CRO_bkC"#0;H +NRM#$_OCMFM8HoFR"sHHoM"ND;H +NR#3Vls_VF0l#Rb"Ok#_C0"Rc;H +NR#3VlF_0#"0RO_bkCR#0c +";N3HRV_#l0DNLCR#0"jjjjjRjjjjsjR4jjjj4s4jj4jRj4j4s4Rjjjj4jsjj444Rjjj4s4R4jjj44s4j444Rj444sjR4j4jj4s44j4jR4444s4Rjj4j4js44444R44"4s;H +NR#3Vls_FHNoMl"CRO_bkC"#0;H +NR#3Vl0_#Ns0CC4oR;H +NRs3FHMoH#N0Ml'CRO_bkCr#0jj:49 +';s@R@Ug:.6(:.:6.g:+cc41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w1RHbslvR1_Qqvt(qr9T S=_1vqtvQq9r( =S71qv_vqQt_rM#jS9 B=piB_pimQ1Z_SO 11=)a;_H RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4d.g.g4.4 +4;N#HR$VM_#Hl_8(R"4dd6.64d4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -628,13 +625,13 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@U.:dc::cd:.c44g+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rn +';s@R@Un:dc::cd:nc44g+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rn =ST1qv_vqQtr -n9Sh7=__nnHB +n9Sh7=__ngHB SpBi=pmi_1_ZQO) S=a)1_ H;N3HRsC0D_R0F4N; -H$R#M#_Vl8_HR4"(..gd44.g"N; +H$R#M#_Vl8_HR4"(d.6d44d6"N; HsR30FD_sMHoNRlC"_1vqtvQq ";N3HRV_#lVlsF#"0R1qv_vqQtR;d" RNH3lV#_#0F01R"vv_qQRtqU @@ -642,13 +639,13 @@ RNH3lV#_#0F01R"vv_qQRtqU ";N3HRV_#lFosHMCNlRv"1_Qqvt;q" RNH3lV#_N#00CCso;R4 RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s; -RU@@:.dc:dc:c..:j.+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr +RU@@:dd(:dc:(.d:j.+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr 69S1T=vv_qQrtq6S9 -7_=hnHU_ +7v=1_QqvtMq_#9r. pSBip=Bi1_mZOQ_ =S))_1aHN; HsR30_DC04FR;H -NRM#$_lV#_RH8".(4g4d.."g4;H +NRM#$_lV#_RH8"d(464d.d"64;H NR03sDs_FHNoMl"CR1qv_vqQt"N; HVR3#Vl_s#Fl01R"vv_qQRtqd ";N3HRV_#l00F#Rv"1_QqvtUqR"N; @@ -656,13 +653,13 @@ HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjj HVR3#Fl_sMHoNRlC"_1vqtvQq ";N3HRV_#l#00NCosCR 4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@Ud:6Uc6:dUj:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqcS9 +s@:@Ud:((c(:d(j:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqcS9 Tv=1_Qqvtcqr97 -S=(h_j -_HSiBp=iBp_Zm1Q +S=_1vqtvQq#_Mr +d9SiBp=iBp_Zm1Q _OS))=1Ha_;H NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(g4.d..4g;4" +RNH#_$MV_#lH"8R(64ddd.46;4" RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H NR#3Vls_VF0l#Rv"1_QqvtdqR"N; HVR3#0l_FR#0"_1vqtvQq"RU;H @@ -670,13 +667,13 @@ NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsj NR#3Vls_FHNoMl"CR1qv_vqQt"N; HVR3##l_0CN0sRCo4N; HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@dU:nc.::.dn:+.c41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtdqr9T +@sR@dU:Ucc::cdU:+.c41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvtdqr9T S=_1vqtvQq9rd =S71qv_vqQt_rM#cS9 B=piB_pimQ1Z_SO )1=)a;_H RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4d.g.g4.4 +4;N#HR$VM_#Hl_8(R"4dd6.64d4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -684,13 +681,13 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@Un:dg::cd:ng.4.+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r. +';s@R@Ug:d4::cd:g4.4.+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r. =ST1qv_vqQtr .9S17=vv_qQ_tqM6#r9B SpBi=pmi_1_ZQO) S=a)1_ H;N3HRsC0D_R0F4N; -H$R#M#_Vl8_HR4"(..gd44.g"N; +H$R#M#_Vl8_HR4"(d.6d44d6"N; HsR30FD_sMHoNRlC"_1vqtvQq ";N3HRV_#lVlsF#"0R1qv_vqQtR;d" RNH3lV#_#0F01R"vv_qQRtqU @@ -698,13 +695,13 @@ RNH3lV#_#0F01R"vv_qQRtqU ";N3HRV_#lFosHMCNlRv"1_Qqvt;q" RNH3lV#_N#00CCso;R4 RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s; -RU@@:dd(:dc:(.d:d.+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr +RU@@:6dg:dc:g.6:d.+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr 49S1T=vv_qQrtq4S9 -7_=h(Hc_ +7v=1_QqvtMq_#9rn pSBip=Bi1_mZOQ_ =S))_1aHN; HsR30_DC04FR;H -NRM#$_lV#_RH8".(4g4d.."g4;H +NRM#$_lV#_RH8"d(464d.d"64;H NR03sDs_FHNoMl"CR1qv_vqQt"N; HVR3#Vl_s#Fl01R"vv_qQRtqd ";N3HRV_#l00F#Rv"1_QqvtUqR"N; @@ -712,13 +709,13 @@ HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjj HVR3#Fl_sMHoNRlC"_1vqtvQq ";N3HRV_#l#00NCosCR 4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@Ud:UccU:dc.:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqjS9 +s@:@Uc:j6cj:c6.:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqjS9 Tv=1_Qqvtjqr97 -S=_1vqtvQq#_Mr -(9SiBp=iBp_Zm1Q +S=(h_n +_HSiBp=iBp_Zm1Q _OS))=1Ha_;H NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(g4.d..4g;4" +RNH#_$MV_#lH"8R(64ddd.46;4" RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H NR#3Vls_VF0l#Rv"1_QqvtdqR"N; HVR3#0l_FR#0"_1vqtvQq"RU;H @@ -726,31 +723,79 @@ NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsj NR#3Vls_FHNoMl"CR1qv_vqQt"N; HVR3##l_0CN0sRCo4N; HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@4U:466:d4:46n:6+:4.e_vqQRhafjj:ROlNEwR7wR1]blsHRqev_aQh -=STe_vqQ -haSh7=_ -4dSiBp=iBp_Zm1Q -_OS)1=1Ha_;H -NR03sDs_FHNoMl"CRe_vqQ"ha;H -NR$3#MM_HHN0PD4R""N; -HHR3MF_DF4bRds; -RU@@:644::6d4:4664n+.t:Aq_Bij_djQRhafjj:ROlNEwR7wR1]blsHRqAtBji_dQj_hSa -Tt=Aq_Bij_djQ -haSh7=_ -4cSiBp=iBp_Zm1Q -_OS)1=1Ha_;H -NR03sDs_FHNoMl"CRABtqid_jjh_Qa -";N3HR#_$MH0MHPRND";4" -RNH3_HMDbFFR -U;s@R@U4:4(U:d:(44:+cj4B.:pmi_zua_). _6jRf:ljRNROE7)ww]sRbHBlRpmi_zua_). _6T -S=iBp_amz_ u)_ -.6Sh7=_ -46SiBp=iBp_Zm1Q +@sR@4U:jd.:nj:4.U:d+:4.B_pij_jjuY_1hgBr:Rj9fjj:ROlNEwR7wR)]blsHRiBp_jjj_1u_YrhB.S9 +Tp=Bij_jj__u1BYhr +.9SB7=pji_juj__h1YB9r4 +pSBip=Bi1_mZOQ_ +=S))_1aHN; +HsR30FD_sMHoNRlC"iBp_jjj_1u_Y"hB;H +NRN3Is8MCbMskHRMo4N; +HkR3MNVsOM_H8RCG.N; +H#R3$HM_MPH0N"DRj +";s@R@Uj:4.n:d:.4j:+dU4B.:pji_juj__h1YB:rgjf9RjR:jlENORw7w)b]RsRHlB_pij_jjuY_1hdBr9T +S=iBp_jjj_1u_YrhBdS9 +7p=Bij_jj__u1BYhr +.9SiBp=iBp_Zm1Q _OS))=1Ha_;H -NR03sDs_FHNoMl"CRB_pim_zau_) .;6" -RNH3M#$_HHM0DPNR""4;H -NRM3H_FDFb;Rg -@sR@4U:jd.:nj:4.U:d+:4.1 QZ_q7vrj4:9jRf:ljRNROE71ww]sRbH1lRQ_Z 7rvqjS9 +NR03sDs_FHNoMl"CRB_pij_jjuY_1h;B" +RNH3sINMbC8sHkMM4oR;H +NRM3kVOsN_8HMCdGR;H +NR$3#MM_HHN0PDjR""s; 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+R:fjjNRlOqERhR7.blsHR_71j_jj Ahqpj _3Sl +m1=7_jjj_q hA_p jM3k4Q +Sj1=7_jjj_q hA +p S=Q4k_M4Nj#_d +j;sjRf:ljRNROEq.h7RHbsl1R7_jjj_q hA_p j +3MS7m=1j_jjh_ q Ap_kj3MSj +Qkj=M14_vv_qQ_tqjJ_#lNkG_S4 +Q74=1j_jjh_ q Ap_kj3M +d;sjRf:ljRNROEmR).blsHR_71j_jj Ahqpj _3Sb +m_=h4Sj +Q7j=1j_jjh_ q Ap_kj3MS4 +Q74=1j_jjh_ q Ap_kj3M +j;sjRf:ljRNROEQRheblsHR1z7_jjj_aQh_sj3 +=Smz_71j_jjQ_hajM3kdQ +Sj1=7_jjd_ +O;sjRf:ljRNROEq.h7RHbsl7Rz1j_jjh_Qa3_jlm +S=1z7_jjj_aQh_kj3MS4 +Qzj=7j1_jQj_hSa +Q74=1d_jj;_O +fsRjR:jlENOR7qh.sRbHzlR7j1_jQj_hja_3SM +m7=z1j_jjh_Qa3_jk +MjS=QjqOj_ +4SQ=1z7_jjj_aQh_kj3M +d;sjRf:ljRNROEmR).blsHR1z7_jjj_aQh_bj3 +=Smh._4 +jSQ=1z7_jjj_aQh_kj3MS4 +Qz4=7j1_jQj_hja_3jkM; diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 97ebf54..c08f5a3 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sat Jun 07 23:03:13 2014 +#Mon Jun 09 10:27:18 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -19,16 +19,16 @@ VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0) -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:32:129:34|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:53:117:56|Pruning register FPU_CS_INT +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:32:135:34|Pruning register CLK_REF(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:29:110:31|Pruning register DTACK_D0 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:38:119:40|Pruning register CLK_OUT_PRE_33 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_CNT_P(1 downto 0) +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":142:2:142:3|Pruning register CLK_CNT_N(1 downto 0) +@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:61:131:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ... +@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:32:135:34|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -39,7 +39,7 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:34:120:36|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Trying to extract state machine for register cpu_est Extracted state machine for register cpu_est State machine has 11 reachable states with original encodings of: 0000 @@ -55,7 +55,7 @@ State machine has 11 reachable states with original encodings of: 1111 @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Jun 07 23:03:13 2014 +# Mon Jun 09 10:27:18 2014 ###########################################################] Map & Optimize Report @@ -91,16 +91,16 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFFRH 16 uses +DFFRH 44 uses DFFSH 26 uses DFF 1 use BI_DIR 12 uses IBUF 29 uses BUFTH 2 uses OBUF 16 uses -AND2 185 uses +AND2 177 uses INV 148 uses -OR2 20 uses +OR2 21 uses XOR2 2 uses @@ -111,6 +111,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Jun 07 23:03:15 2014 +# Mon Jun 09 10:27:20 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 1ea6759..beee949 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index d8f0c10..6c9c68e 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -19,8 +19,8 @@ 0 C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed - 05/29/14 11:52:27 - 0x8531 + 06/07/14 23:03:24 + 0x5EEA Erase,Program,Verify