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More stability in constraints

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This commit is contained in:
MHeinrichs 2014-10-03 07:18:29 +02:00
parent 02e2b00074
commit a42d9d702b
22 changed files with 5236 additions and 36 deletions
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6
Logic/68030-68000-bus.vhd
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@ -141,9 +141,13 @@ signal CLK_000_PE: STD_LOGIC := '0';
signal CLK_000_NE: STD_LOGIC := '0';
signal CLK_000_NE_D0: STD_LOGIC := '0';
signal DTACK_D0: STD_LOGIC := '1';
begin
--pos edge clock
pos_clk: process(CLK_OSZI)
begin
@ -211,7 +215,7 @@ begin
when E23 => cpu_est <= E9 ;
when E24 => cpu_est <= E10;
when others =>
null;
cpu_est <= E10;
end case;
end if;
end if;

2
Logic/68030_TK.STY
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@ -1,6 +1,4 @@
[STRATEGY-LIST]
Normal=True, 1385910337
[TOUCHED-REPORT]
Design.tt4File=1410033670
[synthesis-type]
tool=Synplify

8
Logic/68030_TK.cmi
View File

@ -2,7 +2,7 @@
MAIN_WINDOW_POSITION=0,185,1920,1200
LEFT_PANE_WIDTH=634
CHILD_FRAME_STATE=Maximal
CHILD_WINDOW_SIZE=1920,790
CHILD_WINDOW_SIZE=1920,789
CHILD_WINDOW_POS=-8,-30
[GUI SETTING]
Remember_Setting=1
@ -18,7 +18,7 @@ Sort_Type=0
Sort_Direction=0
Skip_Next_Pin=0
[Pin Attributes]
sort_column_-1=Pin
sort_column_-1=Slewrate
Type=42,no
Signal/Group Name=209,no
Group Members=111,no
@ -40,9 +40,9 @@ State=43,no
Constraint Name=162,no
Constraint Value=115,no
[OPT WINDOWS]
MAIN_WINDOW_POSITION=0,0,1928,1168
MAIN_WINDOW_POSITION=-32000,-32000,-31840,-31973
CHILD_FRAME_STATE=Maximal
CHILD_WINDOW_SIZE=1928,942
CHILD_WINDOW_SIZE=1907,934
CHILD_WINDOW_POS=-8,-30
[OPT GUI SETTING]
Remember_Setting=1

13
Logic/68030_TK.lci
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 09/06/2014;
TIME = 22:01:10;
DATE = 10/02/2014;
TIME = 23:53:03;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -69,7 +69,6 @@ IPL_030_1_ = Pin, 7, -, B, -;
IPL_030_2_ = Pin, 9, -, B, -;
LDS_000 = Pin, 31, -, D, -;
UDS_000 = Pin, 32, -, D, -;
VMA = Pin, 35, -, D, -;
DTACK = Pin, 30, -, D, -;
RESET = Pin, 3, -, B, -;
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
@ -98,6 +97,7 @@ AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
A_23_ = Pin, 85, -, H, -;
FPU_SENSE = Pin, 91, -, A, -;
A1 = Pin, 60, -, F, -;
VMA = Pin, 35, -, D, -;
[Group Assignments]
layer = OFF;
@ -129,8 +129,11 @@ layer = OFF;
Default = UP;
[Slewrate]
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
SLOW = E, VMA;
FAST = AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH,
AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000, CLK_DIV_OUT, CLK_EXP,
FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030, IPL_030_0_, IPL_030_1_,
IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1;
Default = Slow;
[Region]

13
Logic/68030_TK.lct
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 09/06/2014;
TIME = 22:01:10;
DATE = 10/02/2014;
TIME = 23:53:03;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -69,7 +69,6 @@ IPL_030_1_ = Pin, 7, -, B, -;
IPL_030_2_ = Pin, 9, -, B, -;
LDS_000 = Pin, 31, -, D, -;
UDS_000 = Pin, 32, -, D, -;
VMA = Pin, 35, -, D, -;
DTACK = Pin, 30, -, D, -;
RESET = Pin, 3, -, B, -;
AMIGA_BUS_DATA_DIR = Pin, 48, -, E, -;
@ -98,6 +97,7 @@ AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
A_23_ = Pin, 85, -, H, -;
FPU_SENSE = Pin, 91, -, A, -;
A1 = Pin, 60, -, F, -;
VMA = Pin, 35, -, D, -;
[Group Assignments]
layer = OFF;
@ -129,8 +129,11 @@ layer = OFF;
Default = UP;
[Slewrate]
FAST = CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
SLOW = E, VMA;
FAST = AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH,
AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000, CLK_DIV_OUT, CLK_EXP,
FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030, IPL_030_0_, IPL_030_1_,
IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1;
Default = Slow;
[Region]

5189
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Tue Sep 16 14:49:34 2014
// Design '68030_tk' created Thu Oct 02 23:55:21 2014
// LEGEND: '>' Functional Block Port Separator

3
Logic/68030_tk.ipr
View File

@ -1 +1,2 @@
<LATTICE_ENCRYPTED_BLIF>46523=62:%g@U
<LATTICE_ENCRYPTED_BLIF>23;5<74^
91R

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Tue Sep 16 14:49:27 2014
#-- Written on Thu Oct 02 23:55:15 2014
#device options

9
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Tue Sep 16 14:49:28 2014
#Thu Oct 02 23:55:15 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -18,6 +18,7 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven
@ -46,7 +47,7 @@ State machine has 8 reachable states with original encodings of:
111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 16 14:49:28 2014
# Thu Oct 02 23:55:15 2014
###########################################################]
Map & Optimize Report
@ -65,7 +66,7 @@ original code -> new code
101 -> 00100000
110 -> 01000000
111 -> 10000000
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":195:4:195:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":199:4:199:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
---------------------------------------
Resource Usage Report
@ -90,6 +91,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 16 14:49:29 2014
# Thu Oct 02 23:55:17 2014
###########################################################]

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Tue Sep 16 14:49:28 2014
#-- Written on Thu Oct 02 23:55:15 2014
#project files

4
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -12,7 +12,7 @@ original code -> new code
101 -> 00100000
110 -> 01000000
111 -> 10000000
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":195:4:195:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":199:4:199:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
---------------------------------------
Resource Usage Report
@ -37,6 +37,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 16 14:49:29 2014
# Thu Oct 02 23:55:17 2014
###########################################################]

3
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,4 +1,3 @@
@E: CD492 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":457:4:457:4|character '_' is not allowed as the first character
@E: CD492 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":457:5:457:5|character '_' is not allowed as the first character
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:35:152:35|No identifier "no_reset" in scope
@E|Parse errors encountered - exiting

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>13</data>
<data>14</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1410871768</data>
<data type="timestamp">1412286915</data>
</info>
</job_info>
</job_run_status>

1
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,3 +1,4 @@
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven

2
Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
View File

@ -1,3 +1,3 @@
@N: MF248 |Running in 64-bit mode.
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":195:4:195:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":199:4:199:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>95MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1410871769</data>
<data type="timestamp">1412286917</data>
</info>
</job_info>
</job_run_status>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Tue Sep 16 14:49:28 2014
Written on Thu Oct 02 23:55:15 2014
-->

2
Logic/synwork/BUS68030_compiler.fdep
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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1410871756
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412286909
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_compiler.fdeporig
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1410871756
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412286909
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
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Binary file not shown.

1
Logic/synwork/BUS68030_compiler.tlg
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@ -1,4 +1,5 @@
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:8:127:17|Signal clk_pre_66 is undriven