From a4ead08a9aae5845e32632103b490d15598d41de Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Thu, 24 Sep 2015 17:00:50 +0200 Subject: [PATCH] DMA-Bug fixed When BGACK gets deasserted, the DMA-Statemachine has to wait for AS_000 to deassert too! --- Logic/68030-68000-bus.vhd | 16 +- Logic/68030_TK.STY | 4 +- Logic/68030_TK.tcl | 716 +++ Logic/68030_tk-50MHz.jed | 1115 ++++ Logic/68030_tk-gba060.jed | 1115 ++++ Logic/68030_tk.bl2 | 3056 +++++---- Logic/68030_tk.bl3 | 568 +- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 76 +- Logic/68030_tk.fti | 215 +- Logic/68030_tk.grp | 47 +- Logic/68030_tk.ipr | 2 +- Logic/68030_tk.jed | 1227 ++-- Logic/68030_tk.lco | 161 +- Logic/68030_tk.out | 598 ++ Logic/68030_tk.plc | 173 +- Logic/68030_tk.prd | 1407 ++--- Logic/68030_tk.rpt | 1002 +-- Logic/68030_tk.tal | 52 +- Logic/68030_tk.tt2 | 1238 ++-- Logic/68030_tk.tt3 | 1238 ++-- Logic/68030_tk.tt4 | 617 +- Logic/68030_tk.tte | 617 +- Logic/68030_tk.vcl | 121 +- Logic/68030_tk.vco | 161 +- Logic/68030_tk.xrf | 2 +- Logic/BUS68030.bl0 | 3276 +++++----- Logic/BUS68030.bl1 | 3056 +++++---- Logic/BUS68030.cmd | 8 + Logic/BUS68030.edi | 4072 ++++++------ Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 5526 ++++++++--------- Logic/BUS68030.srr | 21 +- Logic/BUS68030.srs | Bin 12715 -> 12845 bytes Logic/bus68030.exf | 1267 ++-- Logic/bus68030.srf | 21 +- Logic/dm/BUS68030_comp.xdm | 4 +- Logic/run_options.txt | 2 +- Logic/synlog/BUS68030_multi_srs_gen.srr | 2 +- Logic/synlog/bus68030_fpga_mapper.srr | 12 +- .../report/BUS68030_compiler_runstatus.xml | 4 +- .../report/BUS68030_compiler_warnings.txt | 1 - .../report/BUS68030_fpga_mapper_runstatus.xml | 2 +- .../report/BUS68030_fpga_mapper_warnings.txt | 2 +- Logic/syntmp/BUS68030_srr.htm | 69 +- Logic/syntmp/BUS68030_toc.htm | 2 +- Logic/syntmp/run_option.xml | 2 +- Logic/syntmp/statusReport.html | 8 +- Logic/synwork/BUS68030_comp.fdep | 2 +- Logic/synwork/BUS68030_comp.fdeporig | 2 +- Logic/synwork/BUS68030_comp.srs | Bin 12174 -> 12309 bytes Logic/synwork/BUS68030_comp.tlg | 1 - Logic/synwork/BUS68030_mult.srs | Bin 12715 -> 12845 bytes Logic/synwork/BUS68030_mult_srs/skeleton.srs | Bin 1142 -> 1146 bytes Logic/synwork/BUS68030_s.srs | Bin 12174 -> 12309 bytes 55 files changed, 18254 insertions(+), 14656 deletions(-) create mode 100644 Logic/68030_tk-50MHz.jed create mode 100644 Logic/68030_tk-gba060.jed create mode 100644 Logic/BUS68030.cmd diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 8b455c6..4475f50 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -269,6 +269,7 @@ begin BGACK_030_INT <= '0'; elsif ( BGACK_000='1' AND CLK_000_PE='1' + AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too! --AND CLK_000_D0='1' and CLK_000_D1='0' ) then -- BGACK_000 is high here! BGACK_030_INT_PRE<= '1'; @@ -492,10 +493,10 @@ begin end process pos_clk; --output clock assignment - --CLK_DIV_OUT <= CLK_OUT_INT; - --CLK_EXP <= CLK_OUT_INT; - CLK_DIV_OUT <= 'Z'; - CLK_EXP <= CLK_030; + CLK_DIV_OUT <= CLK_OUT_INT; + CLK_EXP <= CLK_OUT_INT; + --CLK_DIV_OUT <= 'Z'; + --CLK_EXP <= CLK_030; @@ -556,10 +557,9 @@ begin --cache inhibit: Tristate for expansion (it decides) and off for the Amiga - CIIN <= 'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides) - '1' WHEN A(31 downto 24) = x"00" and AS_030_D0 ='0' and nEXP_SPACE_D0 = '1' ELSE -- Enable for Kick-rom - 'Z'; --off for the Amiga - + CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom + 'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides) + '0'; --off for the Amiga --e and VMA E <= cpu_est(3); diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index 1bb8e88..b15bf23 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,4 +1,4 @@ -[synthesis-type] -tool=Synplify [STRATEGY-LIST] Normal=True, 1412327082 +[synthesis-type] +tool=Synplify diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index aee4a85..d630a32 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -342396,3 +342396,719 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 07/09/15 18:48:45 ########### + +########## Tcl recorder starts at 09/24/15 15:46:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 15:46:43 ########### + + +########## Tcl recorder starts at 09/24/15 15:46:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 15:46:43 ########### + + +########## Tcl recorder starts at 09/24/15 16:04:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 16:04:18 ########### + + +########## Tcl recorder starts at 09/24/15 16:04:18 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 16:04:18 ########### + + +########## Tcl recorder starts at 09/24/15 16:16:41 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 16:16:41 ########### + + +########## Tcl recorder starts at 09/24/15 16:20:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 16:20:44 ########### + + +########## Tcl recorder starts at 09/24/15 16:20:44 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 09/24/15 16:20:44 ########### + diff --git a/Logic/68030_tk-50MHz.jed b/Logic/68030_tk-50MHz.jed new file mode 100644 index 0000000..ef54cea --- /dev/null +++ b/Logic/68030_tk-50MHz.jed @@ -0,0 +1,1115 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.8.00.04.29.14 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +TITLE: +AUTHOR: +PATTERN: +COMPANY: +REVISION: +DATE: Thu Sep 24 16:17:03 2015 + +ABEL mach447a + * +QP100* +QF54096* +G0*F0* +NOTE Part Number : M4A5-128/64-10VC * +NOTE Handling of Preplacements No Change * +NOTE Use placement data from 68030_tk.vct * +NOTE Global clocks routable as PT clocks? N * +NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y * +NOTE SET/RESET treated as DONT_CARE? N * +NOTE Reduce Unforced Global Clocks? N * +NOTE Iterate between partitioning and place/route? Y * +NOTE Balanced partitioning? Y * +NOTE Reduce Routes Per Placement? N * +NOTE Spread Placement? Y * +NOTE Run Time Upper Bound in 15 minutes 0 * +NOTE Zero Hold Time For Input Registers? Y * +NOTE Table of pin names and numbers* +NOTE PINS SIZE_0_:70 A_30_:5 SIZE_1_:79 A_29_:6 A_28_:15* +NOTE PINS A_31_:4 A_27_:16 A_26_:17 A_25_:18 A_24_:19 IPL_2_:68* +NOTE PINS A_23_:85 A_22_:84 FC_1_:58 A_21_:94 AS_030:82 A_20_:93* +NOTE PINS AS_000:42 A_19_:97 A_18_:95 DS_030:98 A_17_:59* +NOTE PINS UDS_000:32 A_16_:96 LDS_000:31 A1:60 nEXP_SPACE:14* +NOTE PINS BERR:41 BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11* +NOTE PINS CLK_OSZI:61 CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91* +NOTE PINS IPL_1_:56 DTACK:30 IPL_0_:67 AVEC:92 FC_0_:57 VPA:36* +NOTE PINS RST:86 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 IPL_030_2_:9 RW_000:80 A0:69 BG_000:29* +NOTE PINS BGACK_030:83 CLK_EXP:10 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS DSACK1:81 E:66 VMA:35 RESET:3 RW:71 * +NOTE Table of node names and numbers* +NOTE NODES RN_SIZE_0_:263 RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 * +NOTE NODES RN_DS_030:101 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * +NOTE NODES RN_IPL_030_2_:131 RN_RW_000:269 RN_A0:257 RN_BG_000:175 * +NOTE NODES RN_BGACK_030:275 RN_IPL_030_1_:143 RN_IPL_030_0_:137 * +NOTE NODES RN_DSACK1:283 RN_E:251 RN_VMA:173 RN_RESET:125 * +NOTE NODES RN_RW:245 cpu_est_0_:167 cpu_est_1_:187 inst_AS_000_INT:259 * +NOTE NODES SM_AMIGA_5_:139 inst_AMIGA_BUS_ENABLE_DMA_LOW:104 * +NOTE NODES inst_AS_030_D0:277 inst_nEXP_SPACE_D0reg:133 * +NOTE NODES inst_DS_030_D0:184 inst_AS_030_000_SYNC:229 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:103 inst_DS_000_DMA:110 CYCLE_DMA_0_:106 * +NOTE NODES CYCLE_DMA_1_:122 SIZE_DMA_0_:253 SIZE_DMA_1_:119 * +NOTE NODES inst_VPA_D:265 inst_UDS_000_INT:115 inst_LDS_000_INT:109 * +NOTE NODES inst_CLK_OUT_PRE_D:145 inst_DTACK_D0:172 inst_CLK_OUT_PRE_50:142 * +NOTE NODES inst_CLK_000_D1:217 inst_CLK_000_D0:209 inst_CLK_000_PE:155 * +NOTE NODES CLK_000_P_SYNC_9_:166 inst_CLK_000_NE:113 CLK_000_N_SYNC_11_:278 * +NOTE NODES cpu_est_2_:193 IPL_D0_0_:136 IPL_D0_1_:236 IPL_D0_2_:178 * +NOTE NODES SM_AMIGA_3_:161 inst_CLK_000_NE_D0:233 SM_AMIGA_0_:223 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:121 SM_AMIGA_6_:227 * +NOTE NODES RST_DLY_0_:158 RST_DLY_1_:169 RST_DLY_2_:151 * +NOTE NODES RST_DLY_3_:128 RST_DLY_4_:134 RST_DLY_5_:163 * +NOTE NODES RST_DLY_6_:152 RST_DLY_7_:164 N_203_i:170 CLK_000_P_SYNC_0_:230 * +NOTE NODES CLK_000_P_SYNC_1_:256 CLK_000_P_SYNC_2_:250 CLK_000_P_SYNC_3_:266 * +NOTE NODES CLK_000_P_SYNC_4_:130 CLK_000_P_SYNC_5_:260 CLK_000_P_SYNC_6_:224 * +NOTE NODES CLK_000_P_SYNC_7_:194 CLK_000_P_SYNC_8_:241 CLK_000_N_SYNC_0_:235 * +NOTE NODES CLK_000_N_SYNC_1_:160 CLK_000_N_SYNC_2_:146 CLK_000_N_SYNC_3_:140 * +NOTE NODES CLK_000_N_SYNC_4_:154 CLK_000_N_SYNC_5_:254 CLK_000_N_SYNC_6_:112 * +NOTE NODES CLK_000_N_SYNC_7_:248 CLK_000_N_SYNC_8_:188 CLK_000_N_SYNC_9_:211 * +NOTE NODES CLK_000_N_SYNC_10_:272 inst_CLK_030_H:116 SM_AMIGA_1_:239 * +NOTE NODES SM_AMIGA_4_:176 SM_AMIGA_2_:157 inst_DS_000_ENABLE:182 * +NOTE NODES SM_AMIGA_i_7_:221 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N * +NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y * +NOTE SET/RESET treated as DONT_CARE? N * +NOTE Reduce Unforced Global Clocks? N * +NOTE Iterate between partitioning and place/route? Y * +NOTE Balanced partitioning? Y * +NOTE Reduce Routes Per Placement? N * +NOTE Spread Placement? Y * +NOTE Run Time Upper Bound in 15 minutes 0 * +NOTE Zero Hold Time For Input Registers? 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+L052350 111111111111111111111111111111111111111111111111111111111110110111* +L052416 111111111111111111111111111111111111111111111111111111111111111111* +L052482 111111111111111111111111111111111111111111111111111111111111111111* +L052548 111111111111111111111111111111111111111111111111111111111111111111* +L052614 111111111111111111111111111111111111111111111111111111111111111111* +L052680 101111111111111111111111111111111111111111011111111111111111111111* +L052746 111111111111111111111111111111111111111111111111111111111111111111* +L052812 111111111111111111111111111111111111111111111111111111111111111111* +L052878 111111111111111111111111111111111111111111111111111111111111111111* +L052944 111111111111111111111111111111111111111111111111111111111111111111* +L053010 + 111111111111111111111111111111111111111111111111111111111111111111* +L053076 111111111111111111111111111111111111111111111111111111111111111111* +L053142 111111111111111111111111111111111111111111111111111111111111111111* +L053208 111111111111111111111111111111111111111111111111111111111111111111* +L053274 111111111111111111111111111111111111111111111111111111111111111111* +L053340 111111111111111111111111111111111111111111111111111111111111111111* +L053406 111111111111111111111111111111111111111111111111111111111111111111* +L053472 111111111111111111111111111111111111111111111111111111111111111111* +L053538 111111111111111111111111111111111111111111111111111111111111111111* +L053604 111111111111111111111111111111111111111111111111111111111111111111* +L053670 111111111111111111111111111111111111111111111111111111111111111111* +L053736 + 000000000000000000000000000000000000000000000000000000000000000000 + 000000000000000000000000000000000000000000000000000000000000000000* +L053868 0010* +L053872 11100110011100* +L053886 01101011110010* +L053900 00010110010001* +L053914 11101011110011* +L053928 10100110010000* +L053942 01000110011110* +L053956 00010110010101* +L053970 11100011110011* +L053984 01111111111000* +L053998 11100110011110* +L054012 11010011110110* +L054026 11111011110011* +L054040 00111111110001* +L054054 01000110010011* +L054068 11010011111100* +L054082 11111011111111* +E1 +1 +01111100 +1 +01110010 +1 +00000000 +1 +01000011 +1 +01011001 +1 +00000000 +1 +10001110 +1 +10000010 +1 +* +C961A* +U00000000000000000000000000000000* +179E diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index e27bb89..cc4b3be 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,141 +1,138 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE 68030_tk -#$ PINS 75 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ IPL_030_2_ A_25_ A_24_ \ -# IPL_2_ A_23_ A_22_ FC_1_ A_21_ AS_030 A_20_ AS_000 A_19_ RW_000 A_18_ DS_030 A_17_ UDS_000 \ -# A_16_ LDS_000 A_15_ A0 A_14_ A1 A_13_ nEXP_SPACE A_12_ BERR A_11_ BG_030 A_10_ BG_000 A_9_ \ -# BGACK_030 A_8_ BGACK_000 A_7_ CLK_030 A_6_ CLK_000 A_5_ CLK_OSZI A_4_ CLK_DIV_OUT A_3_ \ -# CLK_EXP A_2_ FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ \ -# E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -# AMIGA_BUS_ENABLE_HIGH CIIN -#$ NODES 694 N_193 cpu_est_0_1__un3_n N_190 RW_c cpu_est_0_1__un1_n N_189 \ -# cpu_est_0_1__un0_n N_140 fc_c_0__n bgack_030_int_0_un3_n \ -# pos_clk_un29_clk_000_ne_d0_n bgack_030_int_0_un1_n pos_clk_un23_clk_000_ne_d0_n \ -# fc_c_1__n bgack_030_int_0_un0_n inst_BGACK_030_INTreg \ -# pos_clk_un21_clk_000_ne_d0_n un1_amiga_bus_enable_dma_high_i_m4_0__un3_n vcc_n_n \ -# pos_clk_un7_clk_000_pe_n un1_amiga_bus_enable_dma_high_i_m4_0__un1_n \ -# cpu_est_3_reg N_18 AMIGA_BUS_DATA_DIR_c \ -# un1_amiga_bus_enable_dma_high_i_m4_0__un0_n inst_VMA_INTreg N_22 \ -# ds_000_enable_1_sqmuxa_1_i_m4_un3_n inst_RESET_OUTreg \ -# pos_clk_un11_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un1_n gnd_n_n \ -# pos_clk_un9_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un0_n \ -# un1_amiga_bus_enable_low pos_clk_un14_clk_000_n_sync_n size_dma_0_0__un3_n \ -# un6_as_030 pos_clk_un22_bgack_030_int_n N_6_i size_dma_0_0__un1_n un3_size G_161 \ -# N_48_0 size_dma_0_0__un0_n un4_size N_220 N_3_i size_dma_0_1__un3_n un8_ciin G_159 \ -# N_49_0 size_dma_0_1__un1_n un14_amiga_bus_data_dir pos_clk_un40_bgack_030_int_1_n \ -# pos_clk_un29_bgack_030_int_i_n size_dma_0_1__un0_n un4_as_000 CLK_030_H_0_sqmuxa \ -# pos_clk_un26_bgack_030_int_i_n ipl_030_0_0__un3_n un21_fpu_cs AS_000_DMA_1_sqmuxa \ -# pos_clk_un27_bgack_030_int_0_n ipl_030_0_0__un1_n un22_berr \ -# pos_clk_un24_bgack_030_int_n CLK_030_H_0_sqmuxa_i ipl_030_0_0__un0_n un6_ds_030 \ -# pos_clk_un27_bgack_030_int_n N_7_i ipl_030_0_1__un3_n un6_uds_000 N_176_1 N_47_0 \ -# ipl_030_0_1__un1_n un6_lds_000 N_165 N_133_i ipl_030_0_1__un0_n cpu_est_0_ N_133 \ -# N_176_i ipl_030_0_2__un3_n cpu_est_1_ N_163 N_175_i ipl_030_0_2__un1_n \ -# inst_AS_000_INT N_162 AMIGA_BUS_DATA_DIR_c_0 ipl_030_0_2__un0_n SM_AMIGA_5_ N_164 \ -# pos_clk_ds_000_dma_4_f1_0_n dsack1_int_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW \ -# N_176 N_162_i dsack1_int_0_un1_n inst_AS_030_D0 DS_000_DMA_2_sqmuxa N_163_i \ -# dsack1_int_0_un0_n inst_nEXP_SPACE_D0reg pos_clk_ds_000_dma_4_n N_164_i \ -# as_000_int_0_un3_n inst_DS_030_D0 DS_000_DMA_0_sqmuxa N_165_i as_000_int_0_un1_n \ -# inst_AS_030_000_SYNC pos_clk_ds_000_dma_4_f1_n as_000_int_0_un0_n \ -# inst_BGACK_030_INT_D N_175 pos_clk_un22_bgack_030_int_0_n ds_000_enable_0_un3_n \ -# inst_AS_000_DMA N_47 pos_clk_un9_clk_000_n_sync_i_n ds_000_enable_0_un1_n \ -# inst_DS_000_DMA N_7 clk_000_n_sync_i_10__n ds_000_enable_0_un0_n CYCLE_DMA_0_ \ -# un1_rst_2 pos_clk_un14_clk_000_n_sync_0_n as_030_000_sync_0_un3_n CYCLE_DMA_1_ \ -# pos_clk_un26_bgack_030_int_n N_22_i as_030_000_sync_0_un1_n SIZE_DMA_0_ \ -# pos_clk_un29_bgack_030_int_n N_33_0 as_030_000_sync_0_un0_n SIZE_DMA_1_ N_3 N_18_i \ -# lds_000_int_0_un3_n inst_VPA_D N_6 N_37_0 lds_000_int_0_un1_n inst_UDS_000_INT \ -# un1_amiga_bus_enable_low_i pos_clk_un9_clk_000_ne_i_n lds_000_int_0_un0_n \ -# inst_LDS_000_INT un21_fpu_cs_i pos_clk_un5_clk_000_pe_i_n rw_000_int_0_un3_n \ -# inst_CLK_OUT_PRE_D AS_000_i pos_clk_un7_clk_000_pe_0_n rw_000_int_0_un1_n \ -# inst_DTACK_D0 DS_000_DMA_i pos_clk_un27_clk_000_ne_d0_i_n rw_000_int_0_un0_n \ -# inst_CLK_OUT_PRE_50 pos_clk_un24_bgack_030_int_i_n \ -# pos_clk_un21_clk_000_ne_d0_i_n rw_000_dma_0_un3_n inst_CLK_000_D1 \ -# cycle_dma_i_1__n pos_clk_un23_clk_000_ne_d0_0_n rw_000_dma_0_un1_n \ -# inst_CLK_000_D0 cycle_dma_i_0__n N_136_i rw_000_dma_0_un0_n inst_CLK_000_PE \ -# AS_000_DMA_i N_140_0 uds_000_int_0_un3_n CLK_000_P_SYNC_9_ CLK_EXP_i N_195_i \ -# uds_000_int_0_un1_n inst_CLK_000_NE BERR_i N_196_i uds_000_int_0_un0_n \ -# CLK_000_N_SYNC_11_ RW_000_i N_186_i amiga_bus_enable_dma_low_0_un3_n cpu_est_2_ \ -# DS_000_DMA_0_sqmuxa_i N_188_i amiga_bus_enable_dma_low_0_un1_n IPL_D0_0_ \ -# pos_clk_un40_bgack_030_int_1_i_n N_189_i amiga_bus_enable_dma_low_0_un0_n \ -# IPL_D0_1_ BGACK_030_INT_i N_190_i amiga_bus_enable_dma_high_0_un3_n IPL_D0_2_ \ -# nEXP_SPACE_D0_i N_193_i amiga_bus_enable_dma_high_0_un1_n SM_AMIGA_3_ CLK_000_PE_i \ -# N_191_i amiga_bus_enable_dma_high_0_un0_n inst_CLK_000_NE_D0 CLK_000_NE_i N_192_i \ -# bg_000_0_un3_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_194_i bg_000_0_un1_n \ -# SM_AMIGA_0_ sm_amiga_i_0__n pos_clk_cpu_est_11_0_1__n bg_000_0_un0_n \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH pos_clk_un7_clk_000_d0_i_n N_198_i a0_dma_0_un3_n \ -# inst_DSACK1_INTreg UDS_000_i N_197_i a0_dma_0_un1_n LDS_000_i N_199_i a0_dma_0_un0_n \ -# pos_clk_clk_000_n_sync_2_0__n pos_clk_un11_clk_000_n_sync_i_n \ -# pos_clk_cpu_est_11_0_3__n a_23__n pos_clk_ipl_n CLK_OUT_PRE_D_i N_151_i \ -# pos_clk_un3_ds_030_d0_n DTACK_D0_i N_150_i a_22__n SM_AMIGA_6_ sm_amiga_i_2__n \ -# AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa pos_clk_un29_clk_000_ne_d0_i_n N_135_i a_21__n \ -# RST_DLY_0_ cpu_est_i_0__n N_252_0 RST_DLY_1_ cpu_est_i_3__n N_85_i a_20__n RST_DLY_2_ \ -# cpu_est_i_2__n RST_DLY_3_ cpu_est_i_1__n N_38_0 a_15__n RST_DLY_4_ VPA_D_i \ -# un1_rst_dly_i_m_i_2__n RST_DLY_5_ VMA_INT_i a_14__n RST_DLY_6_ sm_amiga_i_1__n \ -# un1_rst_dly_i_m_i_3__n RST_DLY_7_ RESET_OUT_0_sqmuxa_i a_13__n \ -# pos_clk_un8_bg_030_n N_77_i_i un1_rst_dly_i_m_i_4__n CLK_000_P_SYNC_0_ \ -# un1_rst_dly_i_2__n a_12__n CLK_000_P_SYNC_1_ un1_rst_dly_i_3__n \ -# un1_rst_dly_i_m_i_5__n CLK_000_P_SYNC_2_ un1_rst_dly_i_4__n a_11__n \ -# CLK_000_P_SYNC_3_ un1_rst_dly_i_5__n un1_rst_dly_i_m_i_6__n CLK_000_P_SYNC_4_ \ -# un1_rst_dly_i_6__n a_10__n CLK_000_P_SYNC_5_ un1_rst_dly_i_7__n \ -# un1_rst_dly_i_m_i_7__n CLK_000_P_SYNC_6_ un1_rst_dly_i_8__n a_9__n \ -# CLK_000_P_SYNC_7_ RESET_OUT_i un1_rst_dly_i_m_i_8__n CLK_000_P_SYNC_8_ AS_030_D0_i \ -# a_8__n CLK_000_N_SYNC_0_ AS_030_i un3_as_030_i CLK_000_N_SYNC_1_ A1_i N_76_i a_7__n \ -# CLK_000_N_SYNC_2_ CLK_000_D1_i N_83_i CLK_000_N_SYNC_3_ sm_amiga_i_i_7__n a_6__n \ -# CLK_000_N_SYNC_4_ N_248_i N_84_i CLK_000_N_SYNC_5_ sm_amiga_i_5__n N_115_0 a_5__n \ -# CLK_000_N_SYNC_6_ RW_i N_86_i CLK_000_N_SYNC_7_ CLK_000_D0_i \ -# pos_clk_size_dma_6_0_1__n a_4__n CLK_000_N_SYNC_8_ AS_030_000_SYNC_i N_87_i \ -# CLK_000_N_SYNC_9_ sm_amiga_i_6__n pos_clk_size_dma_6_0_0__n a_3__n \ -# CLK_000_N_SYNC_10_ sm_amiga_i_4__n N_88_i pos_clk_un5_bgack_030_int_d_n \ -# FPU_SENSE_i a_2__n inst_RW_000_INT size_dma_i_0__n N_241_0 inst_RW_000_DMA \ -# size_dma_i_1__n N_242_0 inst_A0_DMA a_i_16__n N_243_0 inst_CLK_030_H a_i_18__n N_93_i \ -# SM_AMIGA_1_ a_i_19__n N_94_i SM_AMIGA_4_ a_i_30__n N_244_0 SM_AMIGA_2_ a_i_31__n \ -# N_245_0 pos_clk_un3_as_030_d0_n a_i_28__n N_246_0 inst_DS_000_ENABLE a_i_29__n \ -# pos_clk_un3_as_030_d0_i_n a_i_26__n pos_clk_un5_bgack_030_int_d_i_n a_i_27__n \ -# N_249_i pos_clk_a0_dma_3_n a_i_24__n N_251_0 a_i_25__n N_71_0 LDS_000_INT_i N_104_i \ -# N_8 DS_030_i N_137_i N_9 UDS_000_INT_i N_10 N_224_i N_160_i N_11 N_225_i N_161_i N_12 \ -# N_226_i N_13 N_159_i N_14 N_157_i N_15 N_158_i N_16 N_91_i N_19 N_90_i N_155_i N_20 \ -# un14_amiga_bus_data_dir_i N_156_i N_21 N_80_i N_23 un6_lds_000_i N_154_i N_24 \ -# un6_uds_000_i N_152_i N_25 un6_ds_030_i N_153_i cpu_est_0_0_ un4_as_000_i N_142_0 \ -# AS_000_INT_i N_141_0 un6_as_030_i N_138_0 AMIGA_BUS_ENABLE_DMA_LOW_i N_132_i \ -# DS_030_D0_i un1_as_030_i AS_030_c pos_clk_un11_ds_030_d0_i_n A0_c_i AS_000_c \ -# size_c_i_1__n N_25_i RW_000_c N_32_0 N_24_i DS_030_c N_31_0 N_23_i UDS_000_c N_30_0 \ -# ipl_c_i_2__n LDS_000_c N_54_0 ipl_c_i_1__n size_c_0__n N_53_0 ipl_c_i_0__n \ -# size_c_1__n N_52_0 DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_8_i \ -# N_46_0 N_9_i N_45_0 N_10_i SM_AMIGA_i_7_ N_44_0 N_115 N_12_i pos_clk_size_dma_6_0__n \ -# N_43_0 pos_clk_size_dma_6_1__n N_13_i G_165 N_42_0 G_166 N_14_i G_167 N_41_0 \ -# un6_uds_000_1 N_15_i N_241 N_40_0 N_242 N_16_i N_243 N_39_0 N_244 N_19_i N_245 N_36_0 \ -# N_246 N_20_i N_78 N_35_0 N_80 N_21_i N_89 N_34_0 N_90 a_c_16__n BG_030_c_i N_91 \ -# pos_clk_un6_bg_030_i_n N_98 a_c_17__n pos_clk_un8_bg_030_0_n N_99 N_251_0_1 N_249 \ -# a_c_18__n N_121_i_1 N_248 pos_clk_cpu_est_11_0_1_3__n N_135 a_c_19__n \ -# pos_clk_cpu_est_11_0_1_1__n N_136 pos_clk_cpu_est_11_0_2_1__n \ -# pos_clk_un7_clk_000_d0_n N_131_i_1 un22_berr_1 N_131_i_2 N_152 N_131_i_3 N_153 \ -# pos_clk_un11_ds_030_d0_i_1_n N_154 un8_ciin_1 N_155 un8_ciin_2 N_141 un8_ciin_3 N_156 \ -# un8_ciin_4 N_157 a_c_24__n un8_ciin_5 N_138 un8_ciin_6 N_158 a_c_25__n un8_ciin_7 N_159 \ -# un8_ciin_8 N_160 a_c_26__n N_116_1 N_142 N_116_2 N_161 a_c_27__n N_116_3 N_132 N_116_4 \ -# N_104 a_c_28__n un22_berr_1_0 N_76 un21_fpu_cs_1 N_71 a_c_29__n N_123_i_1 N_251 \ -# N_123_i_2 N_93 a_c_30__n N_125_i_1 N_94 N_127_i_1 N_88 a_c_31__n N_127_i_2 N_87 \ -# N_129_i_1 N_86 A0_c pos_clk_un6_bg_030_1_n N_84 pos_clk_un7_clk_000_d0_1_n N_83 A1_c \ -# RESET_OUT_0_sqmuxa_7_1 N_116 RESET_OUT_0_sqmuxa_7_2 G_149 nEXP_SPACE_c \ -# RESET_OUT_0_sqmuxa_7_3 G_147 RESET_OUT_0_sqmuxa_5_1 N_213 BERR_c N_135_i_1 G_145 \ -# pos_clk_un27_clk_000_ne_d0_1_n N_211 BG_030_c pos_clk_un27_clk_000_ne_d0_2_n G_143 \ -# pos_clk_un27_clk_000_ne_d0_3_n N_209 BG_000DFFreg pos_clk_un5_clk_000_pe_1_n G_141 \ -# pos_clk_un5_clk_000_pe_2_n G_139 pos_clk_un5_clk_000_pe_3_n N_205 BGACK_000_c \ -# pos_clk_un9_clk_000_ne_1_n G_137 pos_clk_un9_clk_000_ne_2_n RESET_OUT_0_sqmuxa_1 \ -# pos_clk_un9_clk_000_ne_3_n RESET_OUT_0_sqmuxa pos_clk_un9_clk_000_ne_4_n \ -# RESET_OUT_0_sqmuxa_7 N_196_1 RESET_OUT_0_sqmuxa_5 CLK_OSZI_c N_195_1 \ -# un1_rst_dly_i_m_8__n pos_clk_un24_bgack_030_int_1_n un1_rst_dly_i_m_7__n N_165_1 \ -# un1_rst_dly_i_m_6__n CLK_EXP_c N_165_2 un1_rst_dly_i_m_5__n N_165_3 \ -# un1_rst_dly_i_m_4__n N_163_1 un1_rst_dly_i_m_3__n FPU_SENSE_c N_162_1 \ -# un1_rst_dly_i_m_2__n N_176_1_0 N_38 IPL_030DFF_0_reg DS_000_DMA_2_sqmuxa_1 N_85 \ -# N_119_i_1 pos_clk_RST_DLY_5_iv_0_x2_0_ IPL_030DFF_1_reg N_115_0_1 N_252 \ -# pos_clk_ipl_1_n N_97 IPL_030DFF_2_reg as_000_dma_0_un3_n \ -# pos_clk_un27_clk_000_ne_d0_n as_000_dma_0_un1_n N_199_1 ipl_c_0__n \ -# as_000_dma_0_un0_n pos_clk_un5_clk_000_pe_n ds_000_dma_0_un3_n \ -# pos_clk_un9_clk_000_ne_n ipl_c_1__n ds_000_dma_0_un1_n N_150 ds_000_dma_0_un0_n \ -# N_151 ipl_c_2__n vma_int_0_un3_n N_199 vma_int_0_un1_n N_196 vma_int_0_un0_n N_195 \ -# DTACK_c sm_amiga_srsts_i_0_m2_1__un3_n N_188 sm_amiga_srsts_i_0_m2_1__un1_n \ -# pos_clk_cpu_est_11_3__n sm_amiga_srsts_i_0_m2_1__un0_n N_197 cpu_est_0_3__un3_n \ -# N_198 VPA_c cpu_est_0_3__un1_n pos_clk_cpu_est_11_1__n cpu_est_0_3__un0_n N_194 \ -# cpu_est_0_2__un3_n N_192 RST_c cpu_est_0_2__un1_n N_191 cpu_est_0_2__un0_n +#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ +# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 \ +# A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ \ +# BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT \ +# IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST \ +# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 695 N_159 N_21_i bgack_030_int_0_un0_n N_157 N_34_0 as_030_000_sync_0_un3_n \ +# N_158 N_20_i as_030_000_sync_0_un1_n un1_rst_dly_i_m_1__n N_35_0 \ +# as_030_000_sync_0_un0_n N_138 N_16_i ds_000_enable_0_un3_n N_88 N_39_0 \ +# ds_000_enable_0_un1_n inst_BGACK_030_INTreg N_256 N_13_i ds_000_enable_0_un0_n \ +# vcc_n_n N_89 N_42_0 a0_dma_0_un3_n cpu_est_3_reg N_91 N_12_i a0_dma_0_un1_n \ +# inst_VMA_INTreg N_92 N_43_0 a0_dma_0_un0_n inst_RESET_OUTreg pos_clk_a0_dma_3_n \ +# N_8_i size_dma_0_1__un3_n gnd_n_n N_96 N_46_0 size_dma_0_1__un1_n \ +# un1_amiga_bus_enable_low N_72 N_76_i size_dma_0_1__un0_n un6_as_030 N_97 N_72_0 \ +# size_dma_0_0__un3_n un3_size N_116 UDS_000_c_i size_dma_0_0__un1_n un4_size N_104 \ +# LDS_000_c_i size_dma_0_0__un0_n un5_ciin N_76 N_256_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un8_ciin pos_clk_size_dma_6_1__n \ +# pos_clk_un5_bgack_030_int_d_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n \ +# un4_as_000 pos_clk_size_dma_6_0__n pos_clk_un24_bgack_030_int_i_0_0_n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n un1_SM_AMIGA_7 N_250 N_104_i \ +# cpu_est_0_1__un3_n un21_fpu_cs pos_clk_un6_bgack_000_n N_252_0 cpu_est_0_1__un1_n \ +# un22_berr N_251 N_251_0 cpu_est_0_1__un0_n un6_ds_030 N_252 \ +# pos_clk_un6_bgack_000_0_n cpu_est_0_2__un3_n un6_uds_000 \ +# pos_clk_un5_bgack_030_int_d_n N_97_i cpu_est_0_2__un1_n un6_lds_000 \ +# pos_clk_un24_bgack_030_int_i_0_x2 N_96_i cpu_est_0_2__un0_n cpu_est_0_ \ +# DS_000_ENABLE_1_sqmuxa_1 N_250_0 cpu_est_0_3__un3_n cpu_est_1_ un22_berr_1 N_89_i \ +# cpu_est_0_3__un1_n inst_AS_000_INT N_8 pos_clk_size_dma_6_0_0__n \ +# cpu_est_0_3__un0_n SM_AMIGA_5_ N_12 N_88_i ipl_030_0_0__un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW N_13 pos_clk_size_dma_6_0_1__n ipl_030_0_0__un1_n \ +# inst_AS_030_D0 N_16 N_138_0 ipl_030_0_0__un0_n inst_nEXP_SPACE_D0reg N_20 \ +# un1_rst_dly_i_m_i_1__n ipl_030_0_1__un3_n inst_DS_030_D0 N_21 ipl_030_0_1__un1_n \ +# inst_AS_030_000_SYNC N_11 N_157_i ipl_030_0_1__un0_n inst_BGACK_030_INT_D \ +# un1_amiga_bus_enable_low_i N_158_i ipl_030_0_2__un3_n inst_AS_000_DMA \ +# un21_fpu_cs_i N_159_i ipl_030_0_2__un1_n inst_DS_000_DMA BGACK_030_INT_i \ +# ipl_030_0_2__un0_n CYCLE_DMA_0_ AMIGA_BUS_ENABLE_DMA_LOW_i N_257_0 \ +# dsack1_int_0_un3_n CYCLE_DMA_1_ AS_030_i un1_as_000_i dsack1_int_0_un1_n \ +# SIZE_DMA_0_ AS_000_INT_i N_93_i dsack1_int_0_un0_n SIZE_DMA_1_ N_105_i \ +# as_000_int_0_un3_n inst_VPA_D N_91_i N_87_i as_000_int_0_un1_n inst_UDS_000_INT \ +# N_92_i N_86_i as_000_int_0_un0_n inst_LDS_000_INT a_i_19__n AMIGA_BUS_DATA_DIR_c_0 \ +# lds_000_int_0_un3_n inst_CLK_OUT_PRE_D a_i_18__n un1_rst_dly_i_m_i_2__n \ +# lds_000_int_0_un1_n inst_DTACK_D0 a_i_16__n lds_000_int_0_un0_n \ +# inst_CLK_OUT_PRE_50 size_dma_i_1__n un1_rst_dly_i_m_i_3__n rw_000_int_0_un3_n \ +# inst_CLK_000_D1 size_dma_i_0__n rw_000_int_0_un1_n inst_CLK_000_D0 FPU_SENSE_i \ +# un1_rst_dly_i_m_i_4__n rw_000_int_0_un0_n inst_CLK_000_PE CLK_000_D1_i \ +# uds_000_int_0_un3_n CLK_000_P_SYNC_9_ CLK_000_D0_i un1_rst_dly_i_m_i_5__n \ +# uds_000_int_0_un1_n inst_CLK_000_NE AS_030_000_SYNC_i uds_000_int_0_un0_n \ +# CLK_000_N_SYNC_11_ AS_030_D0_i un1_rst_dly_i_m_i_6__n vma_int_0_un3_n cpu_est_2_ \ +# sm_amiga_i_i_7__n vma_int_0_un1_n IPL_D0_0_ AS_000_i un1_rst_dly_i_m_i_7__n \ +# vma_int_0_un0_n IPL_D0_1_ CLK_000_PE_i bg_000_0_un3_n IPL_D0_2_ nEXP_SPACE_D0_i \ +# un1_rst_dly_i_m_i_8__n bg_000_0_un1_n SM_AMIGA_3_ A1_i bg_000_0_un0_n \ +# inst_CLK_000_NE_D0 sm_amiga_i_6__n un3_as_030_i ds_000_dma_0_un3_n \ +# pos_clk_un6_bg_030_n BERR_i un1_as_030_i ds_000_dma_0_un1_n SM_AMIGA_0_ \ +# sm_amiga_i_5__n clk_000_n_sync_i_10__n ds_000_dma_0_un0_n \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH RESET_OUT_0_sqmuxa_i \ +# pos_clk_un9_clk_000_n_sync_i_n as_000_dma_0_un3_n inst_DSACK1_INTreg \ +# un1_rst_dly_i_1__n pos_clk_un14_clk_000_n_sync_0_n as_000_dma_0_un1_n RESET_OUT_i \ +# CLK_EXP_c_i as_000_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n RW_000_i N_244_0 \ +# a_15__n pos_clk_ipl_n un1_rst_dly_i_2__n N_83_i pos_clk_un3_ds_030_d0_n \ +# un1_rst_dly_i_3__n N_115_0 a_14__n SM_AMIGA_6_ un1_rst_dly_i_4__n N_84_i RST_DLY_0_ \ +# un1_rst_dly_i_5__n N_245_0 a_13__n RST_DLY_1_ un1_rst_dly_i_6__n N_85_i RST_DLY_2_ \ +# un1_rst_dly_i_7__n pos_clk_ds_000_dma_4_0_n a_12__n RST_DLY_3_ un1_rst_dly_i_8__n \ +# N_94_i RST_DLY_4_ CLK_OUT_PRE_D_i a_11__n RST_DLY_5_ \ +# pos_clk_un11_clk_000_n_sync_i_n RST_DLY_6_ CLK_030_H_i a_10__n RST_DLY_7_ \ +# AS_000_DMA_i N_73_0 pos_clk_un8_bg_030_n VMA_INT_i a_9__n CLK_000_P_SYNC_0_ VPA_D_i \ +# N_160_i CLK_000_P_SYNC_1_ cpu_est_i_0__n N_161_i a_8__n CLK_000_P_SYNC_2_ \ +# cpu_est_i_1__n CLK_000_P_SYNC_3_ cpu_est_i_3__n N_155_i a_7__n CLK_000_P_SYNC_4_ \ +# a_i_24__n N_156_i CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_d0_i_n a_6__n \ +# CLK_000_P_SYNC_6_ sm_amiga_i_0__n N_154_i CLK_000_P_SYNC_7_ sm_amiga_i_3__n N_152_i \ +# a_5__n CLK_000_P_SYNC_8_ CLK_000_NE_i N_153_i CLK_000_N_SYNC_0_ cpu_est_i_2__n \ +# a_4__n CLK_000_N_SYNC_1_ sm_amiga_i_1__n N_150_i CLK_000_N_SYNC_2_ sm_amiga_i_4__n \ +# N_151_i a_3__n CLK_000_N_SYNC_3_ sm_amiga_i_2__n CLK_000_N_SYNC_4_ \ +# pos_clk_un29_clk_000_ne_d0_i_n N_149_i a_2__n CLK_000_N_SYNC_5_ \ +# DSACK1_INT_0_sqmuxa_i N_147_i CLK_000_N_SYNC_6_ RW_i N_148_i CLK_000_N_SYNC_7_ \ +# un5_ciin_i CLK_000_N_SYNC_8_ DTACK_D0_i N_164_i CLK_000_N_SYNC_9_ a_i_31__n N_165_i \ +# CLK_000_N_SYNC_10_ a_i_29__n N_163_i inst_RW_000_INT a_i_30__n N_199_i \ +# inst_RW_000_DMA a_i_27__n pos_clk_cpu_est_11_0_3__n pos_clk_un7_clk_000_pe_n \ +# a_i_28__n N_197_i inst_A0_DMA a_i_25__n N_198_i DS_000_ENABLE_1_sqmuxa a_i_26__n \ +# N_194_i inst_CLK_030_H UDS_000_INT_i pos_clk_cpu_est_11_0_1__n SM_AMIGA_1_ \ +# LDS_000_INT_i N_192_i SM_AMIGA_4_ DS_030_i N_135_i SM_AMIGA_2_ N_224_i N_162_i \ +# inst_DS_000_ENABLE N_225_i N_191_i AS_000_INT_1_sqmuxa N_226_i N_193_i \ +# DSACK1_INT_1_sqmuxa N_190_i pos_clk_ds_000_dma_4_n N_189_i N_3 \ +# DS_000_ENABLE_1_sqmuxa_i N_188_i un6_lds_000_i N_195_i un6_uds_000_i N_196_i N_6 \ +# un6_ds_030_i N_186_i N_9 DS_000_DMA_i N_143_0 N_10 un4_as_000_i N_142_0 N_14 un8_ciin_i \ +# N_141_0 N_15 un6_as_030_i N_140_0 N_17 DS_030_D0_i N_139_0 N_19 AS_030_c N_166_i N_22 \ +# N_137_i N_23 AS_000_c N_136_i N_24 N_133_i N_25 RW_000_c N_132_i cpu_est_0_0_ N_146_i \ +# DS_030_c N_144_i UDS_000_c un1_SM_AMIGA_7_i pos_clk_un21_clk_000_ne_d0_i_n \ +# LDS_000_c pos_clk_un27_clk_000_ne_d0_i_n pos_clk_un23_clk_000_ne_d0_0_n \ +# size_c_0__n pos_clk_un5_clk_000_pe_i_n pos_clk_un9_clk_000_ne_i_n size_c_1__n \ +# pos_clk_un7_clk_000_pe_0_n pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i \ +# N_32_0 N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n \ +# N_52_0 DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i SM_AMIGA_i_7_ N_55_0 N_115 N_50_0 \ +# pos_clk_cpu_est_11_1__n N_3_i pos_clk_cpu_est_11_3__n N_49_0 N_220 N_6_i G_165 N_48_0 \ +# G_166 N_9_i G_167 N_45_0 un6_uds_000_1 N_10_i pos_clk_un24_bgack_030_int_i_0_n \ +# a_c_16__n N_44_0 N_244 N_14_i N_245 a_c_17__n N_41_0 N_15_i N_80 a_c_18__n N_40_0 N_90 \ +# N_17_i N_100 a_c_19__n N_38_0 N_105 N_19_i pos_clk_un11_clk_000_n_sync_n a_c_20__n \ +# N_36_0 pos_clk_CYCLE_DMA_5_1_i_x2 N_22_i pos_clk_CYCLE_DMA_5_0_i_x2 a_c_21__n \ +# N_33_0 N_135 BG_030_c_i N_133 a_c_22__n pos_clk_un6_bg_030_i_n N_190 \ +# pos_clk_un8_bg_030_0_n N_188 a_c_23__n N_127_i_1 N_189 N_127_i_2 N_136 a_c_24__n \ +# pos_clk_un11_ds_030_d0_i_1_n pos_clk_un7_clk_000_d0_n N_135_i_1 \ +# pos_clk_un29_clk_000_ne_d0_n a_c_25__n pos_clk_cpu_est_11_0_1_1__n \ +# DSACK1_INT_0_sqmuxa pos_clk_cpu_est_11_0_2_1__n pos_clk_un21_clk_000_ne_d0_n \ +# a_c_26__n pos_clk_cpu_est_11_0_1_3__n pos_clk_un5_clk_000_pe_n N_195_1 \ +# pos_clk_un9_clk_000_ne_n a_c_27__n N_196_1 pos_clk_un23_clk_000_ne_d0_n N_131_i_1 \ +# pos_clk_un27_clk_000_ne_d0_n a_c_28__n N_131_i_2 pos_clk_un14_clk_000_n_sync_n \ +# N_131_i_3 N_144 a_c_29__n N_119_i_1 N_146 N_119_i_2 N_143 a_c_30__n N_121_i_1 N_147 \ +# N_123_i_1 N_139 a_c_31__n N_123_i_2 N_148 N_125_i_1 N_149 A0_c N_129_i_1 N_150 N_162_1 \ +# N_140 A1_c N_163_1 N_151 N_165_1 N_152 nEXP_SPACE_c N_165_2 N_153 N_165_3 N_154 BERR_c \ +# un5_ciin_1 N_155 un5_ciin_2 N_141 BG_030_c un5_ciin_3 N_156 un5_ciin_4 N_160 \ +# BG_000DFFreg un5_ciin_5 N_142 un5_ciin_6 N_161 un5_ciin_7 N_164 BGACK_000_c un5_ciin_8 \ +# N_166 un5_ciin_9 N_132 un5_ciin_10 N_191 un5_ciin_11 N_192 pos_clk_un9_clk_000_ne_1_n \ +# N_193 CLK_OSZI_c pos_clk_un9_clk_000_ne_2_n N_194 pos_clk_un9_clk_000_ne_3_n N_197 \ +# pos_clk_un9_clk_000_ne_4_n N_198 CLK_EXP_c pos_clk_un5_clk_000_pe_1_n N_195 \ +# pos_clk_un5_clk_000_pe_2_n N_196 pos_clk_un5_clk_000_pe_3_n N_162 FPU_SENSE_c \ +# pos_clk_un27_clk_000_ne_d0_1_n N_199 pos_clk_un27_clk_000_ne_d0_2_n N_199_1 \ +# IPL_030DFF_0_reg pos_clk_un27_clk_000_ne_d0_3_n N_163 RESET_OUT_0_sqmuxa_7_1 N_165 \ +# IPL_030DFF_1_reg RESET_OUT_0_sqmuxa_7_2 N_73 RESET_OUT_0_sqmuxa_7_3 N_94 \ +# IPL_030DFF_2_reg RESET_OUT_0_sqmuxa_5_1 N_85 N_87_1 N_84 ipl_c_0__n N_87_2 N_83 \ +# pos_clk_un24_bgack_030_int_i_0_0_1_n pos_clk_un9_clk_000_n_sync_n ipl_c_1__n \ +# pos_clk_un24_bgack_030_int_i_0_0_2_n G_149 N_72_0_1 G_147 ipl_c_2__n \ +# pos_clk_un7_clk_000_d0_1_n N_213 un21_fpu_cs_1 G_145 un22_berr_1_0 N_211 DTACK_c \ +# N_116_1 G_143 N_116_2 N_209 N_116_3 G_141 N_116_4 G_139 VPA_c pos_clk_un6_bg_030_1_n \ +# N_205 N_115_0_1 G_137 N_245_0_1 RESET_OUT_0_sqmuxa_1 RST_c N_247_i_1 \ +# RESET_OUT_0_sqmuxa N_248_i_1 RESET_OUT_0_sqmuxa_7 N_249_i_1 RESET_OUT_0_sqmuxa_5 \ +# RW_c pos_clk_ipl_1_n un1_rst_dly_i_m_8__n amiga_bus_enable_dma_high_0_un3_n \ +# un1_rst_dly_i_m_7__n fc_c_0__n amiga_bus_enable_dma_high_0_un1_n \ +# un1_rst_dly_i_m_6__n amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n \ +# fc_c_1__n amiga_bus_enable_dma_low_0_un3_n un1_rst_dly_i_m_4__n \ +# amiga_bus_enable_dma_low_0_un1_n un1_rst_dly_i_m_3__n \ +# amiga_bus_enable_dma_low_0_un0_n un1_rst_dly_i_m_2__n AMIGA_BUS_DATA_DIR_c \ +# rw_000_dma_0_un3_n N_86 rw_000_dma_0_un1_n N_93 rw_000_dma_0_un0_n N_87 \ +# bgack_030_int_0_un3_n G_135 bgack_030_int_0_un1_n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -145,374 +142,366 @@ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \ A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \ A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF \ -LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_193.BLIF \ -cpu_est_0_1__un3_n.BLIF N_190.BLIF RW_c.BLIF cpu_est_0_1__un1_n.BLIF \ -N_189.BLIF cpu_est_0_1__un0_n.BLIF N_140.BLIF fc_c_0__n.BLIF \ -bgack_030_int_0_un3_n.BLIF pos_clk_un29_clk_000_ne_d0_n.BLIF \ -bgack_030_int_0_un1_n.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF fc_c_1__n.BLIF \ -bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.BLIF \ -pos_clk_un21_clk_000_ne_d0_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un3_n.BLIF vcc_n_n.BLIF \ -pos_clk_un7_clk_000_pe_n.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un1_n.BLIF \ -cpu_est_3_reg.BLIF N_18.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un0_n.BLIF inst_VMA_INTreg.BLIF \ -N_22.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n.BLIF inst_RESET_OUTreg.BLIF \ -pos_clk_un11_clk_000_n_sync_n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un1_n.BLIF \ -gnd_n_n.BLIF pos_clk_un9_clk_000_n_sync_n.BLIF \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n.BLIF un1_amiga_bus_enable_low.BLIF \ -pos_clk_un14_clk_000_n_sync_n.BLIF size_dma_0_0__un3_n.BLIF un6_as_030.BLIF \ -pos_clk_un22_bgack_030_int_n.BLIF N_6_i.BLIF size_dma_0_0__un1_n.BLIF \ -un3_size.BLIF G_161.BLIF N_48_0.BLIF size_dma_0_0__un0_n.BLIF un4_size.BLIF \ -N_220.BLIF N_3_i.BLIF size_dma_0_1__un3_n.BLIF un8_ciin.BLIF G_159.BLIF \ -N_49_0.BLIF size_dma_0_1__un1_n.BLIF un14_amiga_bus_data_dir.BLIF \ -pos_clk_un40_bgack_030_int_1_n.BLIF pos_clk_un29_bgack_030_int_i_n.BLIF \ -size_dma_0_1__un0_n.BLIF un4_as_000.BLIF CLK_030_H_0_sqmuxa.BLIF \ -pos_clk_un26_bgack_030_int_i_n.BLIF ipl_030_0_0__un3_n.BLIF un21_fpu_cs.BLIF \ -AS_000_DMA_1_sqmuxa.BLIF pos_clk_un27_bgack_030_int_0_n.BLIF \ -ipl_030_0_0__un1_n.BLIF un22_berr.BLIF pos_clk_un24_bgack_030_int_n.BLIF \ -CLK_030_H_0_sqmuxa_i.BLIF ipl_030_0_0__un0_n.BLIF un6_ds_030.BLIF \ -pos_clk_un27_bgack_030_int_n.BLIF N_7_i.BLIF ipl_030_0_1__un3_n.BLIF \ -un6_uds_000.BLIF N_176_1.BLIF N_47_0.BLIF ipl_030_0_1__un1_n.BLIF \ -un6_lds_000.BLIF N_165.BLIF N_133_i.BLIF ipl_030_0_1__un0_n.BLIF \ -cpu_est_0_.BLIF N_133.BLIF N_176_i.BLIF ipl_030_0_2__un3_n.BLIF \ -cpu_est_1_.BLIF N_163.BLIF N_175_i.BLIF ipl_030_0_2__un1_n.BLIF \ -inst_AS_000_INT.BLIF N_162.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ -ipl_030_0_2__un0_n.BLIF SM_AMIGA_5_.BLIF N_164.BLIF \ -pos_clk_ds_000_dma_4_f1_0_n.BLIF dsack1_int_0_un3_n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_176.BLIF N_162_i.BLIF \ -dsack1_int_0_un1_n.BLIF inst_AS_030_D0.BLIF DS_000_DMA_2_sqmuxa.BLIF \ -N_163_i.BLIF dsack1_int_0_un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF \ -pos_clk_ds_000_dma_4_n.BLIF N_164_i.BLIF as_000_int_0_un3_n.BLIF \ -inst_DS_030_D0.BLIF DS_000_DMA_0_sqmuxa.BLIF N_165_i.BLIF \ -as_000_int_0_un1_n.BLIF inst_AS_030_000_SYNC.BLIF \ -pos_clk_ds_000_dma_4_f1_n.BLIF as_000_int_0_un0_n.BLIF \ -inst_BGACK_030_INT_D.BLIF N_175.BLIF pos_clk_un22_bgack_030_int_0_n.BLIF \ -ds_000_enable_0_un3_n.BLIF inst_AS_000_DMA.BLIF N_47.BLIF \ -pos_clk_un9_clk_000_n_sync_i_n.BLIF ds_000_enable_0_un1_n.BLIF \ -inst_DS_000_DMA.BLIF N_7.BLIF clk_000_n_sync_i_10__n.BLIF \ -ds_000_enable_0_un0_n.BLIF CYCLE_DMA_0_.BLIF un1_rst_2.BLIF \ -pos_clk_un14_clk_000_n_sync_0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -CYCLE_DMA_1_.BLIF pos_clk_un26_bgack_030_int_n.BLIF N_22_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF SIZE_DMA_0_.BLIF \ -pos_clk_un29_bgack_030_int_n.BLIF N_33_0.BLIF as_030_000_sync_0_un0_n.BLIF \ -SIZE_DMA_1_.BLIF N_3.BLIF N_18_i.BLIF lds_000_int_0_un3_n.BLIF inst_VPA_D.BLIF \ -N_6.BLIF N_37_0.BLIF lds_000_int_0_un1_n.BLIF inst_UDS_000_INT.BLIF \ -un1_amiga_bus_enable_low_i.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ -lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.BLIF un21_fpu_cs_i.BLIF \ -pos_clk_un5_clk_000_pe_i_n.BLIF rw_000_int_0_un3_n.BLIF \ -inst_CLK_OUT_PRE_D.BLIF AS_000_i.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF \ -rw_000_int_0_un1_n.BLIF inst_DTACK_D0.BLIF DS_000_DMA_i.BLIF \ -pos_clk_un27_clk_000_ne_d0_i_n.BLIF rw_000_int_0_un0_n.BLIF \ -inst_CLK_OUT_PRE_50.BLIF pos_clk_un24_bgack_030_int_i_n.BLIF \ -pos_clk_un21_clk_000_ne_d0_i_n.BLIF rw_000_dma_0_un3_n.BLIF \ -inst_CLK_000_D1.BLIF cycle_dma_i_1__n.BLIF pos_clk_un23_clk_000_ne_d0_0_n.BLIF \ -rw_000_dma_0_un1_n.BLIF inst_CLK_000_D0.BLIF cycle_dma_i_0__n.BLIF \ -N_136_i.BLIF rw_000_dma_0_un0_n.BLIF inst_CLK_000_PE.BLIF AS_000_DMA_i.BLIF \ -N_140_0.BLIF uds_000_int_0_un3_n.BLIF CLK_000_P_SYNC_9_.BLIF CLK_EXP_i.BLIF \ -N_195_i.BLIF uds_000_int_0_un1_n.BLIF inst_CLK_000_NE.BLIF BERR_i.BLIF \ -N_196_i.BLIF uds_000_int_0_un0_n.BLIF CLK_000_N_SYNC_11_.BLIF RW_000_i.BLIF \ -N_186_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF cpu_est_2_.BLIF \ -DS_000_DMA_0_sqmuxa_i.BLIF N_188_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ -IPL_D0_0_.BLIF pos_clk_un40_bgack_030_int_1_i_n.BLIF N_189_i.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF IPL_D0_1_.BLIF BGACK_030_INT_i.BLIF \ -N_190_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF IPL_D0_2_.BLIF \ -nEXP_SPACE_D0_i.BLIF N_193_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ -SM_AMIGA_3_.BLIF CLK_000_PE_i.BLIF N_191_i.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF inst_CLK_000_NE_D0.BLIF \ -CLK_000_NE_i.BLIF N_192_i.BLIF bg_000_0_un3_n.BLIF pos_clk_un6_bg_030_n.BLIF \ -sm_amiga_i_3__n.BLIF N_194_i.BLIF bg_000_0_un1_n.BLIF SM_AMIGA_0_.BLIF \ -sm_amiga_i_0__n.BLIF pos_clk_cpu_est_11_0_1__n.BLIF bg_000_0_un0_n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF \ -N_198_i.BLIF a0_dma_0_un3_n.BLIF inst_DSACK1_INTreg.BLIF UDS_000_i.BLIF \ -N_197_i.BLIF a0_dma_0_un1_n.BLIF LDS_000_i.BLIF N_199_i.BLIF \ -a0_dma_0_un0_n.BLIF pos_clk_clk_000_n_sync_2_0__n.BLIF \ -pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \ -a_23__n.BLIF pos_clk_ipl_n.BLIF CLK_OUT_PRE_D_i.BLIF N_151_i.BLIF \ -pos_clk_un3_ds_030_d0_n.BLIF DTACK_D0_i.BLIF N_150_i.BLIF a_22__n.BLIF \ -SM_AMIGA_6_.BLIF sm_amiga_i_2__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF \ -pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_135_i.BLIF a_21__n.BLIF RST_DLY_0_.BLIF \ -cpu_est_i_0__n.BLIF N_252_0.BLIF RST_DLY_1_.BLIF cpu_est_i_3__n.BLIF \ -N_85_i.BLIF a_20__n.BLIF RST_DLY_2_.BLIF cpu_est_i_2__n.BLIF RST_DLY_3_.BLIF \ -cpu_est_i_1__n.BLIF N_38_0.BLIF a_15__n.BLIF RST_DLY_4_.BLIF VPA_D_i.BLIF \ -un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_5_.BLIF VMA_INT_i.BLIF a_14__n.BLIF \ -RST_DLY_6_.BLIF sm_amiga_i_1__n.BLIF un1_rst_dly_i_m_i_3__n.BLIF \ -RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa_i.BLIF a_13__n.BLIF \ -pos_clk_un8_bg_030_n.BLIF N_77_i_i.BLIF un1_rst_dly_i_m_i_4__n.BLIF \ -CLK_000_P_SYNC_0_.BLIF un1_rst_dly_i_2__n.BLIF a_12__n.BLIF \ -CLK_000_P_SYNC_1_.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_i_5__n.BLIF \ -CLK_000_P_SYNC_2_.BLIF un1_rst_dly_i_4__n.BLIF a_11__n.BLIF \ -CLK_000_P_SYNC_3_.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_i_6__n.BLIF \ -CLK_000_P_SYNC_4_.BLIF un1_rst_dly_i_6__n.BLIF a_10__n.BLIF \ -CLK_000_P_SYNC_5_.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_i_7__n.BLIF \ -CLK_000_P_SYNC_6_.BLIF un1_rst_dly_i_8__n.BLIF a_9__n.BLIF \ -CLK_000_P_SYNC_7_.BLIF RESET_OUT_i.BLIF un1_rst_dly_i_m_i_8__n.BLIF \ -CLK_000_P_SYNC_8_.BLIF AS_030_D0_i.BLIF a_8__n.BLIF CLK_000_N_SYNC_0_.BLIF \ -AS_030_i.BLIF un3_as_030_i.BLIF CLK_000_N_SYNC_1_.BLIF A1_i.BLIF N_76_i.BLIF \ -a_7__n.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_D1_i.BLIF N_83_i.BLIF \ -CLK_000_N_SYNC_3_.BLIF sm_amiga_i_i_7__n.BLIF a_6__n.BLIF \ -CLK_000_N_SYNC_4_.BLIF N_248_i.BLIF N_84_i.BLIF CLK_000_N_SYNC_5_.BLIF \ -sm_amiga_i_5__n.BLIF N_115_0.BLIF a_5__n.BLIF CLK_000_N_SYNC_6_.BLIF RW_i.BLIF \ -N_86_i.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_D0_i.BLIF \ -pos_clk_size_dma_6_0_1__n.BLIF a_4__n.BLIF CLK_000_N_SYNC_8_.BLIF \ -AS_030_000_SYNC_i.BLIF N_87_i.BLIF CLK_000_N_SYNC_9_.BLIF sm_amiga_i_6__n.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF a_3__n.BLIF CLK_000_N_SYNC_10_.BLIF \ -sm_amiga_i_4__n.BLIF N_88_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -FPU_SENSE_i.BLIF a_2__n.BLIF inst_RW_000_INT.BLIF size_dma_i_0__n.BLIF \ -N_241_0.BLIF inst_RW_000_DMA.BLIF size_dma_i_1__n.BLIF N_242_0.BLIF \ -inst_A0_DMA.BLIF a_i_16__n.BLIF N_243_0.BLIF inst_CLK_030_H.BLIF \ -a_i_18__n.BLIF N_93_i.BLIF SM_AMIGA_1_.BLIF a_i_19__n.BLIF N_94_i.BLIF \ -SM_AMIGA_4_.BLIF a_i_30__n.BLIF N_244_0.BLIF SM_AMIGA_2_.BLIF a_i_31__n.BLIF \ -N_245_0.BLIF pos_clk_un3_as_030_d0_n.BLIF a_i_28__n.BLIF N_246_0.BLIF \ -inst_DS_000_ENABLE.BLIF a_i_29__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF \ -a_i_26__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF a_i_27__n.BLIF \ -N_249_i.BLIF pos_clk_a0_dma_3_n.BLIF a_i_24__n.BLIF N_251_0.BLIF \ -a_i_25__n.BLIF N_71_0.BLIF LDS_000_INT_i.BLIF N_104_i.BLIF N_8.BLIF \ -DS_030_i.BLIF N_137_i.BLIF N_9.BLIF UDS_000_INT_i.BLIF N_10.BLIF N_224_i.BLIF \ -N_160_i.BLIF N_11.BLIF N_225_i.BLIF N_161_i.BLIF N_12.BLIF N_226_i.BLIF \ -N_13.BLIF N_159_i.BLIF N_14.BLIF N_157_i.BLIF N_15.BLIF N_158_i.BLIF N_16.BLIF \ -N_91_i.BLIF N_19.BLIF N_90_i.BLIF N_155_i.BLIF N_20.BLIF \ -un14_amiga_bus_data_dir_i.BLIF N_156_i.BLIF N_21.BLIF N_80_i.BLIF N_23.BLIF \ -un6_lds_000_i.BLIF N_154_i.BLIF N_24.BLIF un6_uds_000_i.BLIF N_152_i.BLIF \ -N_25.BLIF un6_ds_030_i.BLIF N_153_i.BLIF cpu_est_0_0_.BLIF un4_as_000_i.BLIF \ -N_142_0.BLIF AS_000_INT_i.BLIF N_141_0.BLIF un6_as_030_i.BLIF N_138_0.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_132_i.BLIF DS_030_D0_i.BLIF \ -un1_as_030_i.BLIF AS_030_c.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF \ -AS_000_c.BLIF size_c_i_1__n.BLIF N_25_i.BLIF RW_000_c.BLIF N_32_0.BLIF \ -N_24_i.BLIF DS_030_c.BLIF N_31_0.BLIF N_23_i.BLIF UDS_000_c.BLIF N_30_0.BLIF \ -ipl_c_i_2__n.BLIF LDS_000_c.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF \ -size_c_0__n.BLIF N_53_0.BLIF ipl_c_i_0__n.BLIF size_c_1__n.BLIF N_52_0.BLIF \ +LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_159.BLIF N_21_i.BLIF \ +bgack_030_int_0_un0_n.BLIF N_157.BLIF N_34_0.BLIF as_030_000_sync_0_un3_n.BLIF \ +N_158.BLIF N_20_i.BLIF as_030_000_sync_0_un1_n.BLIF un1_rst_dly_i_m_1__n.BLIF \ +N_35_0.BLIF as_030_000_sync_0_un0_n.BLIF N_138.BLIF N_16_i.BLIF \ +ds_000_enable_0_un3_n.BLIF N_88.BLIF N_39_0.BLIF ds_000_enable_0_un1_n.BLIF \ +inst_BGACK_030_INTreg.BLIF N_256.BLIF N_13_i.BLIF ds_000_enable_0_un0_n.BLIF \ +vcc_n_n.BLIF N_89.BLIF N_42_0.BLIF a0_dma_0_un3_n.BLIF cpu_est_3_reg.BLIF \ +N_91.BLIF N_12_i.BLIF a0_dma_0_un1_n.BLIF inst_VMA_INTreg.BLIF N_92.BLIF \ +N_43_0.BLIF a0_dma_0_un0_n.BLIF inst_RESET_OUTreg.BLIF pos_clk_a0_dma_3_n.BLIF \ +N_8_i.BLIF size_dma_0_1__un3_n.BLIF gnd_n_n.BLIF N_96.BLIF N_46_0.BLIF \ +size_dma_0_1__un1_n.BLIF un1_amiga_bus_enable_low.BLIF N_72.BLIF N_76_i.BLIF \ +size_dma_0_1__un0_n.BLIF un6_as_030.BLIF N_97.BLIF N_72_0.BLIF \ +size_dma_0_0__un3_n.BLIF un3_size.BLIF N_116.BLIF UDS_000_c_i.BLIF \ +size_dma_0_0__un1_n.BLIF un4_size.BLIF N_104.BLIF LDS_000_c_i.BLIF \ +size_dma_0_0__un0_n.BLIF un5_ciin.BLIF N_76.BLIF N_256_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un8_ciin.BLIF \ +pos_clk_size_dma_6_1__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un4_as_000.BLIF \ +pos_clk_size_dma_6_0__n.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF un1_SM_AMIGA_7.BLIF \ +N_250.BLIF N_104_i.BLIF cpu_est_0_1__un3_n.BLIF un21_fpu_cs.BLIF \ +pos_clk_un6_bgack_000_n.BLIF N_252_0.BLIF cpu_est_0_1__un1_n.BLIF \ +un22_berr.BLIF N_251.BLIF N_251_0.BLIF cpu_est_0_1__un0_n.BLIF un6_ds_030.BLIF \ +N_252.BLIF pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_2__un3_n.BLIF \ +un6_uds_000.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_97_i.BLIF \ +cpu_est_0_2__un1_n.BLIF un6_lds_000.BLIF \ +pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_96_i.BLIF cpu_est_0_2__un0_n.BLIF \ +cpu_est_0_.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_250_0.BLIF \ +cpu_est_0_3__un3_n.BLIF cpu_est_1_.BLIF un22_berr_1.BLIF N_89_i.BLIF \ +cpu_est_0_3__un1_n.BLIF inst_AS_000_INT.BLIF N_8.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF cpu_est_0_3__un0_n.BLIF SM_AMIGA_5_.BLIF \ +N_12.BLIF N_88_i.BLIF ipl_030_0_0__un3_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_13.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +ipl_030_0_0__un1_n.BLIF inst_AS_030_D0.BLIF N_16.BLIF N_138_0.BLIF \ +ipl_030_0_0__un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_20.BLIF \ +un1_rst_dly_i_m_i_1__n.BLIF ipl_030_0_1__un3_n.BLIF inst_DS_030_D0.BLIF \ +N_21.BLIF ipl_030_0_1__un1_n.BLIF inst_AS_030_000_SYNC.BLIF N_11.BLIF \ +N_157_i.BLIF ipl_030_0_1__un0_n.BLIF inst_BGACK_030_INT_D.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_158_i.BLIF ipl_030_0_2__un3_n.BLIF \ +inst_AS_000_DMA.BLIF un21_fpu_cs_i.BLIF N_159_i.BLIF ipl_030_0_2__un1_n.BLIF \ +inst_DS_000_DMA.BLIF BGACK_030_INT_i.BLIF ipl_030_0_2__un0_n.BLIF \ +CYCLE_DMA_0_.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_257_0.BLIF \ +dsack1_int_0_un3_n.BLIF CYCLE_DMA_1_.BLIF AS_030_i.BLIF un1_as_000_i.BLIF \ +dsack1_int_0_un1_n.BLIF SIZE_DMA_0_.BLIF AS_000_INT_i.BLIF N_93_i.BLIF \ +dsack1_int_0_un0_n.BLIF SIZE_DMA_1_.BLIF N_105_i.BLIF as_000_int_0_un3_n.BLIF \ +inst_VPA_D.BLIF N_91_i.BLIF N_87_i.BLIF as_000_int_0_un1_n.BLIF \ +inst_UDS_000_INT.BLIF N_92_i.BLIF N_86_i.BLIF as_000_int_0_un0_n.BLIF \ +inst_LDS_000_INT.BLIF a_i_19__n.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ +lds_000_int_0_un3_n.BLIF inst_CLK_OUT_PRE_D.BLIF a_i_18__n.BLIF \ +un1_rst_dly_i_m_i_2__n.BLIF lds_000_int_0_un1_n.BLIF inst_DTACK_D0.BLIF \ +a_i_16__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF \ +size_dma_i_1__n.BLIF un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un3_n.BLIF \ +inst_CLK_000_D1.BLIF size_dma_i_0__n.BLIF rw_000_int_0_un1_n.BLIF \ +inst_CLK_000_D0.BLIF FPU_SENSE_i.BLIF un1_rst_dly_i_m_i_4__n.BLIF \ +rw_000_int_0_un0_n.BLIF inst_CLK_000_PE.BLIF CLK_000_D1_i.BLIF \ +uds_000_int_0_un3_n.BLIF CLK_000_P_SYNC_9_.BLIF CLK_000_D0_i.BLIF \ +un1_rst_dly_i_m_i_5__n.BLIF uds_000_int_0_un1_n.BLIF inst_CLK_000_NE.BLIF \ +AS_030_000_SYNC_i.BLIF uds_000_int_0_un0_n.BLIF CLK_000_N_SYNC_11_.BLIF \ +AS_030_D0_i.BLIF un1_rst_dly_i_m_i_6__n.BLIF vma_int_0_un3_n.BLIF \ +cpu_est_2_.BLIF sm_amiga_i_i_7__n.BLIF vma_int_0_un1_n.BLIF IPL_D0_0_.BLIF \ +AS_000_i.BLIF un1_rst_dly_i_m_i_7__n.BLIF vma_int_0_un0_n.BLIF IPL_D0_1_.BLIF \ +CLK_000_PE_i.BLIF bg_000_0_un3_n.BLIF IPL_D0_2_.BLIF nEXP_SPACE_D0_i.BLIF \ +un1_rst_dly_i_m_i_8__n.BLIF bg_000_0_un1_n.BLIF SM_AMIGA_3_.BLIF A1_i.BLIF \ +bg_000_0_un0_n.BLIF inst_CLK_000_NE_D0.BLIF sm_amiga_i_6__n.BLIF \ +un3_as_030_i.BLIF ds_000_dma_0_un3_n.BLIF pos_clk_un6_bg_030_n.BLIF \ +BERR_i.BLIF un1_as_030_i.BLIF ds_000_dma_0_un1_n.BLIF SM_AMIGA_0_.BLIF \ +sm_amiga_i_5__n.BLIF clk_000_n_sync_i_10__n.BLIF ds_000_dma_0_un0_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF RESET_OUT_0_sqmuxa_i.BLIF \ +pos_clk_un9_clk_000_n_sync_i_n.BLIF as_000_dma_0_un3_n.BLIF \ +inst_DSACK1_INTreg.BLIF un1_rst_dly_i_1__n.BLIF \ +pos_clk_un14_clk_000_n_sync_0_n.BLIF as_000_dma_0_un1_n.BLIF RESET_OUT_i.BLIF \ +CLK_EXP_c_i.BLIF as_000_dma_0_un0_n.BLIF pos_clk_clk_000_n_sync_2_0__n.BLIF \ +RW_000_i.BLIF N_244_0.BLIF a_15__n.BLIF pos_clk_ipl_n.BLIF \ +un1_rst_dly_i_2__n.BLIF N_83_i.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +un1_rst_dly_i_3__n.BLIF N_115_0.BLIF a_14__n.BLIF SM_AMIGA_6_.BLIF \ +un1_rst_dly_i_4__n.BLIF N_84_i.BLIF RST_DLY_0_.BLIF un1_rst_dly_i_5__n.BLIF \ +N_245_0.BLIF a_13__n.BLIF RST_DLY_1_.BLIF un1_rst_dly_i_6__n.BLIF N_85_i.BLIF \ +RST_DLY_2_.BLIF un1_rst_dly_i_7__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +a_12__n.BLIF RST_DLY_3_.BLIF un1_rst_dly_i_8__n.BLIF N_94_i.BLIF \ +RST_DLY_4_.BLIF CLK_OUT_PRE_D_i.BLIF a_11__n.BLIF RST_DLY_5_.BLIF \ +pos_clk_un11_clk_000_n_sync_i_n.BLIF RST_DLY_6_.BLIF CLK_030_H_i.BLIF \ +a_10__n.BLIF RST_DLY_7_.BLIF AS_000_DMA_i.BLIF N_73_0.BLIF \ +pos_clk_un8_bg_030_n.BLIF VMA_INT_i.BLIF a_9__n.BLIF CLK_000_P_SYNC_0_.BLIF \ +VPA_D_i.BLIF N_160_i.BLIF CLK_000_P_SYNC_1_.BLIF cpu_est_i_0__n.BLIF \ +N_161_i.BLIF a_8__n.BLIF CLK_000_P_SYNC_2_.BLIF cpu_est_i_1__n.BLIF \ +CLK_000_P_SYNC_3_.BLIF cpu_est_i_3__n.BLIF N_155_i.BLIF a_7__n.BLIF \ +CLK_000_P_SYNC_4_.BLIF a_i_24__n.BLIF N_156_i.BLIF CLK_000_P_SYNC_5_.BLIF \ +pos_clk_un7_clk_000_d0_i_n.BLIF a_6__n.BLIF CLK_000_P_SYNC_6_.BLIF \ +sm_amiga_i_0__n.BLIF N_154_i.BLIF CLK_000_P_SYNC_7_.BLIF sm_amiga_i_3__n.BLIF \ +N_152_i.BLIF a_5__n.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_NE_i.BLIF N_153_i.BLIF \ +CLK_000_N_SYNC_0_.BLIF cpu_est_i_2__n.BLIF a_4__n.BLIF CLK_000_N_SYNC_1_.BLIF \ +sm_amiga_i_1__n.BLIF N_150_i.BLIF CLK_000_N_SYNC_2_.BLIF sm_amiga_i_4__n.BLIF \ +N_151_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_3_.BLIF sm_amiga_i_2__n.BLIF \ +CLK_000_N_SYNC_4_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_149_i.BLIF \ +a_2__n.BLIF CLK_000_N_SYNC_5_.BLIF DSACK1_INT_0_sqmuxa_i.BLIF N_147_i.BLIF \ +CLK_000_N_SYNC_6_.BLIF RW_i.BLIF N_148_i.BLIF CLK_000_N_SYNC_7_.BLIF \ +un5_ciin_i.BLIF CLK_000_N_SYNC_8_.BLIF DTACK_D0_i.BLIF N_164_i.BLIF \ +CLK_000_N_SYNC_9_.BLIF a_i_31__n.BLIF N_165_i.BLIF CLK_000_N_SYNC_10_.BLIF \ +a_i_29__n.BLIF N_163_i.BLIF inst_RW_000_INT.BLIF a_i_30__n.BLIF N_199_i.BLIF \ +inst_RW_000_DMA.BLIF a_i_27__n.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \ +pos_clk_un7_clk_000_pe_n.BLIF a_i_28__n.BLIF N_197_i.BLIF inst_A0_DMA.BLIF \ +a_i_25__n.BLIF N_198_i.BLIF DS_000_ENABLE_1_sqmuxa.BLIF a_i_26__n.BLIF \ +N_194_i.BLIF inst_CLK_030_H.BLIF UDS_000_INT_i.BLIF \ +pos_clk_cpu_est_11_0_1__n.BLIF SM_AMIGA_1_.BLIF LDS_000_INT_i.BLIF \ +N_192_i.BLIF SM_AMIGA_4_.BLIF DS_030_i.BLIF N_135_i.BLIF SM_AMIGA_2_.BLIF \ +N_224_i.BLIF N_162_i.BLIF inst_DS_000_ENABLE.BLIF N_225_i.BLIF N_191_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF N_226_i.BLIF N_193_i.BLIF DSACK1_INT_1_sqmuxa.BLIF \ +N_190_i.BLIF pos_clk_ds_000_dma_4_n.BLIF N_189_i.BLIF N_3.BLIF \ +DS_000_ENABLE_1_sqmuxa_i.BLIF N_188_i.BLIF un6_lds_000_i.BLIF N_195_i.BLIF \ +un6_uds_000_i.BLIF N_196_i.BLIF N_6.BLIF un6_ds_030_i.BLIF N_186_i.BLIF \ +N_9.BLIF DS_000_DMA_i.BLIF N_143_0.BLIF N_10.BLIF un4_as_000_i.BLIF \ +N_142_0.BLIF N_14.BLIF un8_ciin_i.BLIF N_141_0.BLIF N_15.BLIF \ +un6_as_030_i.BLIF N_140_0.BLIF N_17.BLIF DS_030_D0_i.BLIF N_139_0.BLIF \ +N_19.BLIF AS_030_c.BLIF N_166_i.BLIF N_22.BLIF N_137_i.BLIF N_23.BLIF \ +AS_000_c.BLIF N_136_i.BLIF N_24.BLIF N_133_i.BLIF N_25.BLIF RW_000_c.BLIF \ +N_132_i.BLIF cpu_est_0_0_.BLIF N_146_i.BLIF DS_030_c.BLIF N_144_i.BLIF \ +UDS_000_c.BLIF un1_SM_AMIGA_7_i.BLIF pos_clk_un21_clk_000_ne_d0_i_n.BLIF \ +LDS_000_c.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF \ +pos_clk_un23_clk_000_ne_d0_0_n.BLIF size_c_0__n.BLIF \ +pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ +size_c_1__n.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF \ +pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF size_c_i_1__n.BLIF N_25_i.BLIF \ +N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF N_23_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF \ +N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF ipl_c_i_0__n.BLIF N_52_0.BLIF \ DTACK_c_i.BLIF N_57_0.BLIF VPA_c_i.BLIF N_56_0.BLIF nEXP_SPACE_c_i.BLIF \ -N_55_0.BLIF N_50_0.BLIF N_8_i.BLIF N_46_0.BLIF N_9_i.BLIF N_45_0.BLIF \ -N_10_i.BLIF SM_AMIGA_i_7_.BLIF N_44_0.BLIF N_115.BLIF N_12_i.BLIF \ -pos_clk_size_dma_6_0__n.BLIF N_43_0.BLIF pos_clk_size_dma_6_1__n.BLIF \ -N_13_i.BLIF G_165.BLIF N_42_0.BLIF G_166.BLIF N_14_i.BLIF G_167.BLIF \ -N_41_0.BLIF un6_uds_000_1.BLIF N_15_i.BLIF N_241.BLIF N_40_0.BLIF N_242.BLIF \ -N_16_i.BLIF N_243.BLIF N_39_0.BLIF N_244.BLIF N_19_i.BLIF N_245.BLIF \ -N_36_0.BLIF N_246.BLIF N_20_i.BLIF N_78.BLIF N_35_0.BLIF N_80.BLIF N_21_i.BLIF \ -N_89.BLIF N_34_0.BLIF N_90.BLIF a_c_16__n.BLIF BG_030_c_i.BLIF N_91.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF N_98.BLIF a_c_17__n.BLIF \ -pos_clk_un8_bg_030_0_n.BLIF N_99.BLIF N_251_0_1.BLIF N_249.BLIF a_c_18__n.BLIF \ -N_121_i_1.BLIF N_248.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF N_135.BLIF \ -a_c_19__n.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF N_136.BLIF \ -pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_un7_clk_000_d0_n.BLIF N_131_i_1.BLIF \ -un22_berr_1.BLIF N_131_i_2.BLIF N_152.BLIF N_131_i_3.BLIF N_153.BLIF \ -pos_clk_un11_ds_030_d0_i_1_n.BLIF N_154.BLIF un8_ciin_1.BLIF N_155.BLIF \ -un8_ciin_2.BLIF N_141.BLIF un8_ciin_3.BLIF N_156.BLIF un8_ciin_4.BLIF \ -N_157.BLIF a_c_24__n.BLIF un8_ciin_5.BLIF N_138.BLIF un8_ciin_6.BLIF \ -N_158.BLIF a_c_25__n.BLIF un8_ciin_7.BLIF N_159.BLIF un8_ciin_8.BLIF \ -N_160.BLIF a_c_26__n.BLIF N_116_1.BLIF N_142.BLIF N_116_2.BLIF N_161.BLIF \ -a_c_27__n.BLIF N_116_3.BLIF N_132.BLIF N_116_4.BLIF N_104.BLIF a_c_28__n.BLIF \ -un22_berr_1_0.BLIF N_76.BLIF un21_fpu_cs_1.BLIF N_71.BLIF a_c_29__n.BLIF \ -N_123_i_1.BLIF N_251.BLIF N_123_i_2.BLIF N_93.BLIF a_c_30__n.BLIF \ -N_125_i_1.BLIF N_94.BLIF N_127_i_1.BLIF N_88.BLIF a_c_31__n.BLIF \ -N_127_i_2.BLIF N_87.BLIF N_129_i_1.BLIF N_86.BLIF A0_c.BLIF \ -pos_clk_un6_bg_030_1_n.BLIF N_84.BLIF pos_clk_un7_clk_000_d0_1_n.BLIF \ -N_83.BLIF A1_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_116.BLIF \ -RESET_OUT_0_sqmuxa_7_2.BLIF G_149.BLIF nEXP_SPACE_c.BLIF \ -RESET_OUT_0_sqmuxa_7_3.BLIF G_147.BLIF RESET_OUT_0_sqmuxa_5_1.BLIF N_213.BLIF \ -BERR_c.BLIF N_135_i_1.BLIF G_145.BLIF pos_clk_un27_clk_000_ne_d0_1_n.BLIF \ -N_211.BLIF BG_030_c.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF G_143.BLIF \ -pos_clk_un27_clk_000_ne_d0_3_n.BLIF N_209.BLIF BG_000DFFreg.BLIF \ -pos_clk_un5_clk_000_pe_1_n.BLIF G_141.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ -G_139.BLIF pos_clk_un5_clk_000_pe_3_n.BLIF N_205.BLIF BGACK_000_c.BLIF \ -pos_clk_un9_clk_000_ne_1_n.BLIF G_137.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF \ -RESET_OUT_0_sqmuxa_1.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF \ -RESET_OUT_0_sqmuxa.BLIF pos_clk_un9_clk_000_ne_4_n.BLIF \ -RESET_OUT_0_sqmuxa_7.BLIF N_196_1.BLIF RESET_OUT_0_sqmuxa_5.BLIF \ -CLK_OSZI_c.BLIF N_195_1.BLIF un1_rst_dly_i_m_8__n.BLIF \ -pos_clk_un24_bgack_030_int_1_n.BLIF un1_rst_dly_i_m_7__n.BLIF N_165_1.BLIF \ -un1_rst_dly_i_m_6__n.BLIF CLK_EXP_c.BLIF N_165_2.BLIF \ -un1_rst_dly_i_m_5__n.BLIF N_165_3.BLIF un1_rst_dly_i_m_4__n.BLIF N_163_1.BLIF \ -un1_rst_dly_i_m_3__n.BLIF FPU_SENSE_c.BLIF N_162_1.BLIF \ -un1_rst_dly_i_m_2__n.BLIF N_176_1_0.BLIF N_38.BLIF IPL_030DFF_0_reg.BLIF \ -DS_000_DMA_2_sqmuxa_1.BLIF N_85.BLIF N_119_i_1.BLIF \ -pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF IPL_030DFF_1_reg.BLIF N_115_0_1.BLIF \ -N_252.BLIF pos_clk_ipl_1_n.BLIF N_97.BLIF IPL_030DFF_2_reg.BLIF \ -as_000_dma_0_un3_n.BLIF pos_clk_un27_clk_000_ne_d0_n.BLIF \ -as_000_dma_0_un1_n.BLIF N_199_1.BLIF ipl_c_0__n.BLIF as_000_dma_0_un0_n.BLIF \ -pos_clk_un5_clk_000_pe_n.BLIF ds_000_dma_0_un3_n.BLIF \ -pos_clk_un9_clk_000_ne_n.BLIF ipl_c_1__n.BLIF ds_000_dma_0_un1_n.BLIF \ -N_150.BLIF ds_000_dma_0_un0_n.BLIF N_151.BLIF ipl_c_2__n.BLIF \ -vma_int_0_un3_n.BLIF N_199.BLIF vma_int_0_un1_n.BLIF N_196.BLIF \ -vma_int_0_un0_n.BLIF N_195.BLIF DTACK_c.BLIF \ -sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_188.BLIF \ -sm_amiga_srsts_i_0_m2_1__un1_n.BLIF pos_clk_cpu_est_11_3__n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_197.BLIF cpu_est_0_3__un3_n.BLIF \ -N_198.BLIF VPA_c.BLIF cpu_est_0_3__un1_n.BLIF pos_clk_cpu_est_11_1__n.BLIF \ -cpu_est_0_3__un0_n.BLIF N_194.BLIF cpu_est_0_2__un3_n.BLIF N_192.BLIF \ -RST_c.BLIF cpu_est_0_2__un1_n.BLIF N_191.BLIF cpu_est_0_2__un0_n.BLIF \ +SM_AMIGA_i_7_.BLIF N_55_0.BLIF N_115.BLIF N_50_0.BLIF \ +pos_clk_cpu_est_11_1__n.BLIF N_3_i.BLIF pos_clk_cpu_est_11_3__n.BLIF \ +N_49_0.BLIF N_220.BLIF N_6_i.BLIF G_165.BLIF N_48_0.BLIF G_166.BLIF N_9_i.BLIF \ +G_167.BLIF N_45_0.BLIF un6_uds_000_1.BLIF N_10_i.BLIF \ +pos_clk_un24_bgack_030_int_i_0_n.BLIF a_c_16__n.BLIF N_44_0.BLIF N_244.BLIF \ +N_14_i.BLIF N_245.BLIF a_c_17__n.BLIF N_41_0.BLIF N_15_i.BLIF N_80.BLIF \ +a_c_18__n.BLIF N_40_0.BLIF N_90.BLIF N_17_i.BLIF N_100.BLIF a_c_19__n.BLIF \ +N_38_0.BLIF N_105.BLIF N_19_i.BLIF pos_clk_un11_clk_000_n_sync_n.BLIF \ +a_c_20__n.BLIF N_36_0.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_22_i.BLIF \ +pos_clk_CYCLE_DMA_5_0_i_x2.BLIF a_c_21__n.BLIF N_33_0.BLIF N_135.BLIF \ +BG_030_c_i.BLIF N_133.BLIF a_c_22__n.BLIF pos_clk_un6_bg_030_i_n.BLIF \ +N_190.BLIF pos_clk_un8_bg_030_0_n.BLIF N_188.BLIF a_c_23__n.BLIF \ +N_127_i_1.BLIF N_189.BLIF N_127_i_2.BLIF N_136.BLIF a_c_24__n.BLIF \ +pos_clk_un11_ds_030_d0_i_1_n.BLIF pos_clk_un7_clk_000_d0_n.BLIF N_135_i_1.BLIF \ +pos_clk_un29_clk_000_ne_d0_n.BLIF a_c_25__n.BLIF \ +pos_clk_cpu_est_11_0_1_1__n.BLIF DSACK1_INT_0_sqmuxa.BLIF \ +pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_un21_clk_000_ne_d0_n.BLIF \ +a_c_26__n.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF pos_clk_un5_clk_000_pe_n.BLIF \ +N_195_1.BLIF pos_clk_un9_clk_000_ne_n.BLIF a_c_27__n.BLIF N_196_1.BLIF \ +pos_clk_un23_clk_000_ne_d0_n.BLIF N_131_i_1.BLIF \ +pos_clk_un27_clk_000_ne_d0_n.BLIF a_c_28__n.BLIF N_131_i_2.BLIF \ +pos_clk_un14_clk_000_n_sync_n.BLIF N_131_i_3.BLIF N_144.BLIF a_c_29__n.BLIF \ +N_119_i_1.BLIF N_146.BLIF N_119_i_2.BLIF N_143.BLIF a_c_30__n.BLIF \ +N_121_i_1.BLIF N_147.BLIF N_123_i_1.BLIF N_139.BLIF a_c_31__n.BLIF \ +N_123_i_2.BLIF N_148.BLIF N_125_i_1.BLIF N_149.BLIF A0_c.BLIF N_129_i_1.BLIF \ +N_150.BLIF N_162_1.BLIF N_140.BLIF A1_c.BLIF N_163_1.BLIF N_151.BLIF \ +N_165_1.BLIF N_152.BLIF nEXP_SPACE_c.BLIF N_165_2.BLIF N_153.BLIF N_165_3.BLIF \ +N_154.BLIF BERR_c.BLIF un5_ciin_1.BLIF N_155.BLIF un5_ciin_2.BLIF N_141.BLIF \ +BG_030_c.BLIF un5_ciin_3.BLIF N_156.BLIF un5_ciin_4.BLIF N_160.BLIF \ +BG_000DFFreg.BLIF un5_ciin_5.BLIF N_142.BLIF un5_ciin_6.BLIF N_161.BLIF \ +un5_ciin_7.BLIF N_164.BLIF BGACK_000_c.BLIF un5_ciin_8.BLIF N_166.BLIF \ +un5_ciin_9.BLIF N_132.BLIF un5_ciin_10.BLIF N_191.BLIF un5_ciin_11.BLIF \ +N_192.BLIF pos_clk_un9_clk_000_ne_1_n.BLIF N_193.BLIF CLK_OSZI_c.BLIF \ +pos_clk_un9_clk_000_ne_2_n.BLIF N_194.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF \ +N_197.BLIF pos_clk_un9_clk_000_ne_4_n.BLIF N_198.BLIF CLK_EXP_c.BLIF \ +pos_clk_un5_clk_000_pe_1_n.BLIF N_195.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ +N_196.BLIF pos_clk_un5_clk_000_pe_3_n.BLIF N_162.BLIF FPU_SENSE_c.BLIF \ +pos_clk_un27_clk_000_ne_d0_1_n.BLIF N_199.BLIF \ +pos_clk_un27_clk_000_ne_d0_2_n.BLIF N_199_1.BLIF IPL_030DFF_0_reg.BLIF \ +pos_clk_un27_clk_000_ne_d0_3_n.BLIF N_163.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF \ +N_165.BLIF IPL_030DFF_1_reg.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF N_73.BLIF \ +RESET_OUT_0_sqmuxa_7_3.BLIF N_94.BLIF IPL_030DFF_2_reg.BLIF \ +RESET_OUT_0_sqmuxa_5_1.BLIF N_85.BLIF N_87_1.BLIF N_84.BLIF ipl_c_0__n.BLIF \ +N_87_2.BLIF N_83.BLIF pos_clk_un24_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un9_clk_000_n_sync_n.BLIF ipl_c_1__n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_0_2_n.BLIF G_149.BLIF N_72_0_1.BLIF G_147.BLIF \ +ipl_c_2__n.BLIF pos_clk_un7_clk_000_d0_1_n.BLIF N_213.BLIF un21_fpu_cs_1.BLIF \ +G_145.BLIF un22_berr_1_0.BLIF N_211.BLIF DTACK_c.BLIF N_116_1.BLIF G_143.BLIF \ +N_116_2.BLIF N_209.BLIF N_116_3.BLIF G_141.BLIF N_116_4.BLIF G_139.BLIF \ +VPA_c.BLIF pos_clk_un6_bg_030_1_n.BLIF N_205.BLIF N_115_0_1.BLIF G_137.BLIF \ +N_245_0_1.BLIF RESET_OUT_0_sqmuxa_1.BLIF RST_c.BLIF N_247_i_1.BLIF \ +RESET_OUT_0_sqmuxa.BLIF N_248_i_1.BLIF RESET_OUT_0_sqmuxa_7.BLIF \ +N_249_i_1.BLIF RESET_OUT_0_sqmuxa_5.BLIF RW_c.BLIF pos_clk_ipl_1_n.BLIF \ +un1_rst_dly_i_m_8__n.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ +un1_rst_dly_i_m_7__n.BLIF fc_c_0__n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF un1_rst_dly_i_m_6__n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF un1_rst_dly_i_m_5__n.BLIF \ +fc_c_1__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF un1_rst_dly_i_m_4__n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF un1_rst_dly_i_m_3__n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF un1_rst_dly_i_m_2__n.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF rw_000_dma_0_un3_n.BLIF N_86.BLIF \ +rw_000_dma_0_un1_n.BLIF N_93.BLIF rw_000_dma_0_un0_n.BLIF N_87.BLIF \ +bgack_030_int_0_un3_n.BLIF G_135.BLIF bgack_030_int_0_un1_n.BLIF \ AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \ UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \ VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \ -SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ -SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFF_0_reg.D \ -IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ -IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C \ -RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C \ -RST_DLY_6_.D RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ -CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ -CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ -CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ -CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ -CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ -CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ -CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ -CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.D \ -CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C \ -CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ -CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \ -inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ -inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUTreg.D \ -inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C BG_000DFFreg.D BG_000DFFreg.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ +IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D \ +RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D \ +RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D \ +RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ +CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ +CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ +CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \ +CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \ +CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C \ +inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_A0_DMA.D inst_A0_DMA.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_DS_030_D0.D inst_DS_030_D0.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \ inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \ inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \ -UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_193 cpu_est_0_1__un3_n N_190 RW_c \ -cpu_est_0_1__un1_n N_189 cpu_est_0_1__un0_n N_140 fc_c_0__n \ -bgack_030_int_0_un3_n pos_clk_un29_clk_000_ne_d0_n bgack_030_int_0_un1_n \ -pos_clk_un23_clk_000_ne_d0_n fc_c_1__n bgack_030_int_0_un0_n \ -pos_clk_un21_clk_000_ne_d0_n un1_amiga_bus_enable_dma_high_i_m4_0__un3_n \ -vcc_n_n pos_clk_un7_clk_000_pe_n un1_amiga_bus_enable_dma_high_i_m4_0__un1_n \ -N_18 AMIGA_BUS_DATA_DIR_c un1_amiga_bus_enable_dma_high_i_m4_0__un0_n N_22 \ -ds_000_enable_1_sqmuxa_1_i_m4_un3_n pos_clk_un11_clk_000_n_sync_n \ -ds_000_enable_1_sqmuxa_1_i_m4_un1_n gnd_n_n pos_clk_un9_clk_000_n_sync_n \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n un1_amiga_bus_enable_low \ -pos_clk_un14_clk_000_n_sync_n size_dma_0_0__un3_n un6_as_030 \ -pos_clk_un22_bgack_030_int_n N_6_i size_dma_0_0__un1_n un3_size N_48_0 \ -size_dma_0_0__un0_n un4_size N_220 N_3_i size_dma_0_1__un3_n un8_ciin N_49_0 \ -size_dma_0_1__un1_n un14_amiga_bus_data_dir pos_clk_un40_bgack_030_int_1_n \ -pos_clk_un29_bgack_030_int_i_n size_dma_0_1__un0_n un4_as_000 \ -CLK_030_H_0_sqmuxa pos_clk_un26_bgack_030_int_i_n ipl_030_0_0__un3_n \ -un21_fpu_cs AS_000_DMA_1_sqmuxa pos_clk_un27_bgack_030_int_0_n \ -ipl_030_0_0__un1_n un22_berr pos_clk_un24_bgack_030_int_n CLK_030_H_0_sqmuxa_i \ -ipl_030_0_0__un0_n un6_ds_030 pos_clk_un27_bgack_030_int_n N_7_i \ -ipl_030_0_1__un3_n un6_uds_000 N_176_1 N_47_0 ipl_030_0_1__un1_n un6_lds_000 \ -N_165 N_133_i ipl_030_0_1__un0_n N_133 N_176_i ipl_030_0_2__un3_n N_163 \ -N_175_i ipl_030_0_2__un1_n N_162 AMIGA_BUS_DATA_DIR_c_0 ipl_030_0_2__un0_n \ -N_164 pos_clk_ds_000_dma_4_f1_0_n dsack1_int_0_un3_n N_176 N_162_i \ -dsack1_int_0_un1_n DS_000_DMA_2_sqmuxa N_163_i dsack1_int_0_un0_n \ -pos_clk_ds_000_dma_4_n N_164_i as_000_int_0_un3_n DS_000_DMA_0_sqmuxa N_165_i \ -as_000_int_0_un1_n pos_clk_ds_000_dma_4_f1_n as_000_int_0_un0_n N_175 \ -pos_clk_un22_bgack_030_int_0_n ds_000_enable_0_un3_n N_47 \ -pos_clk_un9_clk_000_n_sync_i_n ds_000_enable_0_un1_n N_7 \ -clk_000_n_sync_i_10__n ds_000_enable_0_un0_n un1_rst_2 \ -pos_clk_un14_clk_000_n_sync_0_n as_030_000_sync_0_un3_n \ -pos_clk_un26_bgack_030_int_n N_22_i as_030_000_sync_0_un1_n \ -pos_clk_un29_bgack_030_int_n N_33_0 as_030_000_sync_0_un0_n N_3 N_18_i \ -lds_000_int_0_un3_n N_6 N_37_0 lds_000_int_0_un1_n un1_amiga_bus_enable_low_i \ -pos_clk_un9_clk_000_ne_i_n lds_000_int_0_un0_n un21_fpu_cs_i \ -pos_clk_un5_clk_000_pe_i_n rw_000_int_0_un3_n AS_000_i \ -pos_clk_un7_clk_000_pe_0_n rw_000_int_0_un1_n DS_000_DMA_i \ -pos_clk_un27_clk_000_ne_d0_i_n rw_000_int_0_un0_n \ -pos_clk_un24_bgack_030_int_i_n pos_clk_un21_clk_000_ne_d0_i_n \ -rw_000_dma_0_un3_n cycle_dma_i_1__n pos_clk_un23_clk_000_ne_d0_0_n \ -rw_000_dma_0_un1_n cycle_dma_i_0__n N_136_i rw_000_dma_0_un0_n AS_000_DMA_i \ -N_140_0 uds_000_int_0_un3_n CLK_EXP_i N_195_i uds_000_int_0_un1_n BERR_i \ -N_196_i uds_000_int_0_un0_n RW_000_i N_186_i amiga_bus_enable_dma_low_0_un3_n \ -DS_000_DMA_0_sqmuxa_i N_188_i amiga_bus_enable_dma_low_0_un1_n \ -pos_clk_un40_bgack_030_int_1_i_n N_189_i amiga_bus_enable_dma_low_0_un0_n \ -BGACK_030_INT_i N_190_i amiga_bus_enable_dma_high_0_un3_n nEXP_SPACE_D0_i \ -N_193_i amiga_bus_enable_dma_high_0_un1_n CLK_000_PE_i N_191_i \ -amiga_bus_enable_dma_high_0_un0_n CLK_000_NE_i N_192_i bg_000_0_un3_n \ -pos_clk_un6_bg_030_n sm_amiga_i_3__n N_194_i bg_000_0_un1_n sm_amiga_i_0__n \ -pos_clk_cpu_est_11_0_1__n bg_000_0_un0_n pos_clk_un7_clk_000_d0_i_n N_198_i \ -a0_dma_0_un3_n UDS_000_i N_197_i a0_dma_0_un1_n LDS_000_i N_199_i \ -a0_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n pos_clk_un11_clk_000_n_sync_i_n \ -pos_clk_cpu_est_11_0_3__n a_23__n pos_clk_ipl_n CLK_OUT_PRE_D_i N_151_i \ -pos_clk_un3_ds_030_d0_n DTACK_D0_i N_150_i a_22__n sm_amiga_i_2__n \ -AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa pos_clk_un29_clk_000_ne_d0_i_n N_135_i \ -a_21__n cpu_est_i_0__n N_252_0 cpu_est_i_3__n N_85_i a_20__n cpu_est_i_2__n \ -cpu_est_i_1__n N_38_0 a_15__n VPA_D_i un1_rst_dly_i_m_i_2__n VMA_INT_i a_14__n \ -sm_amiga_i_1__n un1_rst_dly_i_m_i_3__n RESET_OUT_0_sqmuxa_i a_13__n \ -pos_clk_un8_bg_030_n N_77_i_i un1_rst_dly_i_m_i_4__n un1_rst_dly_i_2__n \ -a_12__n un1_rst_dly_i_3__n un1_rst_dly_i_m_i_5__n un1_rst_dly_i_4__n a_11__n \ -un1_rst_dly_i_5__n un1_rst_dly_i_m_i_6__n un1_rst_dly_i_6__n a_10__n \ -un1_rst_dly_i_7__n un1_rst_dly_i_m_i_7__n un1_rst_dly_i_8__n a_9__n \ -RESET_OUT_i un1_rst_dly_i_m_i_8__n AS_030_D0_i a_8__n AS_030_i un3_as_030_i \ -A1_i N_76_i a_7__n CLK_000_D1_i N_83_i sm_amiga_i_i_7__n a_6__n N_248_i N_84_i \ -sm_amiga_i_5__n N_115_0 a_5__n RW_i N_86_i CLK_000_D0_i \ -pos_clk_size_dma_6_0_1__n a_4__n AS_030_000_SYNC_i N_87_i sm_amiga_i_6__n \ -pos_clk_size_dma_6_0_0__n a_3__n sm_amiga_i_4__n N_88_i \ -pos_clk_un5_bgack_030_int_d_n FPU_SENSE_i a_2__n size_dma_i_0__n N_241_0 \ -size_dma_i_1__n N_242_0 a_i_16__n N_243_0 a_i_18__n N_93_i a_i_19__n N_94_i \ -a_i_30__n N_244_0 a_i_31__n N_245_0 pos_clk_un3_as_030_d0_n a_i_28__n N_246_0 \ -a_i_29__n pos_clk_un3_as_030_d0_i_n a_i_26__n pos_clk_un5_bgack_030_int_d_i_n \ -a_i_27__n N_249_i pos_clk_a0_dma_3_n a_i_24__n N_251_0 a_i_25__n N_71_0 \ -LDS_000_INT_i N_104_i N_8 DS_030_i N_137_i N_9 UDS_000_INT_i N_10 N_224_i \ -N_160_i N_11 N_225_i N_161_i N_12 N_226_i N_13 N_159_i N_14 N_157_i N_15 \ -N_158_i N_16 N_91_i N_19 N_90_i N_155_i N_20 un14_amiga_bus_data_dir_i N_156_i \ -N_21 N_80_i N_23 un6_lds_000_i N_154_i N_24 un6_uds_000_i N_152_i N_25 \ -un6_ds_030_i N_153_i un4_as_000_i N_142_0 AS_000_INT_i N_141_0 un6_as_030_i \ -N_138_0 AMIGA_BUS_ENABLE_DMA_LOW_i N_132_i DS_030_D0_i un1_as_030_i AS_030_c \ -pos_clk_un11_ds_030_d0_i_n A0_c_i AS_000_c size_c_i_1__n N_25_i RW_000_c \ -N_32_0 N_24_i DS_030_c N_31_0 N_23_i UDS_000_c N_30_0 ipl_c_i_2__n LDS_000_c \ -N_54_0 ipl_c_i_1__n size_c_0__n N_53_0 ipl_c_i_0__n size_c_1__n N_52_0 \ -DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_8_i N_46_0 \ -N_9_i N_45_0 N_10_i N_44_0 N_115 N_12_i pos_clk_size_dma_6_0__n N_43_0 \ -pos_clk_size_dma_6_1__n N_13_i N_42_0 N_14_i N_41_0 un6_uds_000_1 N_15_i N_241 \ -N_40_0 N_242 N_16_i N_243 N_39_0 N_244 N_19_i N_245 N_36_0 N_246 N_20_i N_78 \ -N_35_0 N_80 N_21_i N_89 N_34_0 N_90 a_c_16__n BG_030_c_i N_91 \ -pos_clk_un6_bg_030_i_n N_98 a_c_17__n pos_clk_un8_bg_030_0_n N_99 N_251_0_1 \ -N_249 a_c_18__n N_121_i_1 N_248 pos_clk_cpu_est_11_0_1_3__n N_135 a_c_19__n \ -pos_clk_cpu_est_11_0_1_1__n N_136 pos_clk_cpu_est_11_0_2_1__n \ -pos_clk_un7_clk_000_d0_n N_131_i_1 un22_berr_1 N_131_i_2 N_152 N_131_i_3 N_153 \ -pos_clk_un11_ds_030_d0_i_1_n N_154 un8_ciin_1 N_155 un8_ciin_2 N_141 \ -un8_ciin_3 N_156 un8_ciin_4 N_157 a_c_24__n un8_ciin_5 N_138 un8_ciin_6 N_158 \ -a_c_25__n un8_ciin_7 N_159 un8_ciin_8 N_160 a_c_26__n N_116_1 N_142 N_116_2 \ -N_161 a_c_27__n N_116_3 N_132 N_116_4 N_104 a_c_28__n un22_berr_1_0 N_76 \ -un21_fpu_cs_1 N_71 a_c_29__n N_123_i_1 N_251 N_123_i_2 N_93 a_c_30__n \ -N_125_i_1 N_94 N_127_i_1 N_88 a_c_31__n N_127_i_2 N_87 N_129_i_1 N_86 A0_c \ -pos_clk_un6_bg_030_1_n N_84 pos_clk_un7_clk_000_d0_1_n N_83 A1_c \ -RESET_OUT_0_sqmuxa_7_1 N_116 RESET_OUT_0_sqmuxa_7_2 nEXP_SPACE_c \ -RESET_OUT_0_sqmuxa_7_3 RESET_OUT_0_sqmuxa_5_1 N_213 BERR_c N_135_i_1 \ -pos_clk_un27_clk_000_ne_d0_1_n N_211 BG_030_c pos_clk_un27_clk_000_ne_d0_2_n \ -pos_clk_un27_clk_000_ne_d0_3_n N_209 pos_clk_un5_clk_000_pe_1_n \ -pos_clk_un5_clk_000_pe_2_n pos_clk_un5_clk_000_pe_3_n N_205 BGACK_000_c \ -pos_clk_un9_clk_000_ne_1_n pos_clk_un9_clk_000_ne_2_n RESET_OUT_0_sqmuxa_1 \ -pos_clk_un9_clk_000_ne_3_n RESET_OUT_0_sqmuxa pos_clk_un9_clk_000_ne_4_n \ -RESET_OUT_0_sqmuxa_7 N_196_1 RESET_OUT_0_sqmuxa_5 CLK_OSZI_c N_195_1 \ -un1_rst_dly_i_m_8__n pos_clk_un24_bgack_030_int_1_n un1_rst_dly_i_m_7__n \ -N_165_1 un1_rst_dly_i_m_6__n CLK_EXP_c N_165_2 un1_rst_dly_i_m_5__n N_165_3 \ -un1_rst_dly_i_m_4__n N_163_1 un1_rst_dly_i_m_3__n FPU_SENSE_c N_162_1 \ -un1_rst_dly_i_m_2__n N_176_1_0 N_38 DS_000_DMA_2_sqmuxa_1 N_85 N_119_i_1 \ -N_115_0_1 N_252 pos_clk_ipl_1_n N_97 as_000_dma_0_un3_n \ -pos_clk_un27_clk_000_ne_d0_n as_000_dma_0_un1_n N_199_1 ipl_c_0__n \ -as_000_dma_0_un0_n pos_clk_un5_clk_000_pe_n ds_000_dma_0_un3_n \ -pos_clk_un9_clk_000_ne_n ipl_c_1__n ds_000_dma_0_un1_n N_150 \ -ds_000_dma_0_un0_n N_151 ipl_c_2__n vma_int_0_un3_n N_199 vma_int_0_un1_n \ -N_196 vma_int_0_un0_n N_195 DTACK_c sm_amiga_srsts_i_0_m2_1__un3_n N_188 \ -sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_cpu_est_11_3__n \ -sm_amiga_srsts_i_0_m2_1__un0_n N_197 cpu_est_0_3__un3_n N_198 VPA_c \ -cpu_est_0_3__un1_n pos_clk_cpu_est_11_1__n cpu_est_0_3__un0_n N_194 \ -cpu_est_0_2__un3_n N_192 RST_c cpu_est_0_2__un1_n N_191 cpu_est_0_2__un0_n \ -AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE G_161 G_159 \ -cpu_est_0_0_ G_165 G_166 G_167 G_149 G_147 G_145 G_143 G_141 G_139 G_137 \ -pos_clk_RST_DLY_5_iv_0_x2_0_ +UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_159 N_21_i bgack_030_int_0_un0_n N_157 \ +N_34_0 as_030_000_sync_0_un3_n N_158 N_20_i as_030_000_sync_0_un1_n \ +un1_rst_dly_i_m_1__n N_35_0 as_030_000_sync_0_un0_n N_138 N_16_i \ +ds_000_enable_0_un3_n N_88 N_39_0 ds_000_enable_0_un1_n N_256 N_13_i \ +ds_000_enable_0_un0_n vcc_n_n N_89 N_42_0 a0_dma_0_un3_n N_91 N_12_i \ +a0_dma_0_un1_n N_92 N_43_0 a0_dma_0_un0_n pos_clk_a0_dma_3_n N_8_i \ +size_dma_0_1__un3_n gnd_n_n N_96 N_46_0 size_dma_0_1__un1_n \ +un1_amiga_bus_enable_low N_72 N_76_i size_dma_0_1__un0_n un6_as_030 N_97 \ +N_72_0 size_dma_0_0__un3_n un3_size N_116 UDS_000_c_i size_dma_0_0__un1_n \ +un4_size N_104 LDS_000_c_i size_dma_0_0__un0_n un5_ciin N_76 N_256_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un8_ciin pos_clk_size_dma_6_1__n \ +pos_clk_un5_bgack_030_int_d_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n \ +un4_as_000 pos_clk_size_dma_6_0__n pos_clk_un24_bgack_030_int_i_0_0_n \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n un1_SM_AMIGA_7 N_250 N_104_i \ +cpu_est_0_1__un3_n un21_fpu_cs pos_clk_un6_bgack_000_n N_252_0 \ +cpu_est_0_1__un1_n un22_berr N_251 N_251_0 cpu_est_0_1__un0_n un6_ds_030 N_252 \ +pos_clk_un6_bgack_000_0_n cpu_est_0_2__un3_n un6_uds_000 \ +pos_clk_un5_bgack_030_int_d_n N_97_i cpu_est_0_2__un1_n un6_lds_000 N_96_i \ +cpu_est_0_2__un0_n DS_000_ENABLE_1_sqmuxa_1 N_250_0 cpu_est_0_3__un3_n \ +un22_berr_1 N_89_i cpu_est_0_3__un1_n N_8 pos_clk_size_dma_6_0_0__n \ +cpu_est_0_3__un0_n N_12 N_88_i ipl_030_0_0__un3_n N_13 \ +pos_clk_size_dma_6_0_1__n ipl_030_0_0__un1_n N_16 N_138_0 ipl_030_0_0__un0_n \ +N_20 un1_rst_dly_i_m_i_1__n ipl_030_0_1__un3_n N_21 ipl_030_0_1__un1_n N_11 \ +N_157_i ipl_030_0_1__un0_n un1_amiga_bus_enable_low_i N_158_i \ +ipl_030_0_2__un3_n un21_fpu_cs_i N_159_i ipl_030_0_2__un1_n BGACK_030_INT_i \ +ipl_030_0_2__un0_n AMIGA_BUS_ENABLE_DMA_LOW_i N_257_0 dsack1_int_0_un3_n \ +AS_030_i un1_as_000_i dsack1_int_0_un1_n AS_000_INT_i N_93_i \ +dsack1_int_0_un0_n N_105_i as_000_int_0_un3_n N_91_i N_87_i as_000_int_0_un1_n \ +N_92_i N_86_i as_000_int_0_un0_n a_i_19__n AMIGA_BUS_DATA_DIR_c_0 \ +lds_000_int_0_un3_n a_i_18__n un1_rst_dly_i_m_i_2__n lds_000_int_0_un1_n \ +a_i_16__n lds_000_int_0_un0_n size_dma_i_1__n un1_rst_dly_i_m_i_3__n \ +rw_000_int_0_un3_n size_dma_i_0__n rw_000_int_0_un1_n FPU_SENSE_i \ +un1_rst_dly_i_m_i_4__n rw_000_int_0_un0_n CLK_000_D1_i uds_000_int_0_un3_n \ +CLK_000_D0_i un1_rst_dly_i_m_i_5__n uds_000_int_0_un1_n AS_030_000_SYNC_i \ +uds_000_int_0_un0_n AS_030_D0_i un1_rst_dly_i_m_i_6__n vma_int_0_un3_n \ +sm_amiga_i_i_7__n vma_int_0_un1_n AS_000_i un1_rst_dly_i_m_i_7__n \ +vma_int_0_un0_n CLK_000_PE_i bg_000_0_un3_n nEXP_SPACE_D0_i \ +un1_rst_dly_i_m_i_8__n bg_000_0_un1_n A1_i bg_000_0_un0_n sm_amiga_i_6__n \ +un3_as_030_i ds_000_dma_0_un3_n pos_clk_un6_bg_030_n BERR_i un1_as_030_i \ +ds_000_dma_0_un1_n sm_amiga_i_5__n clk_000_n_sync_i_10__n ds_000_dma_0_un0_n \ +RESET_OUT_0_sqmuxa_i pos_clk_un9_clk_000_n_sync_i_n as_000_dma_0_un3_n \ +un1_rst_dly_i_1__n pos_clk_un14_clk_000_n_sync_0_n as_000_dma_0_un1_n \ +RESET_OUT_i CLK_EXP_c_i as_000_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n \ +RW_000_i N_244_0 a_15__n pos_clk_ipl_n un1_rst_dly_i_2__n N_83_i \ +pos_clk_un3_ds_030_d0_n un1_rst_dly_i_3__n N_115_0 a_14__n un1_rst_dly_i_4__n \ +N_84_i un1_rst_dly_i_5__n N_245_0 a_13__n un1_rst_dly_i_6__n N_85_i \ +un1_rst_dly_i_7__n pos_clk_ds_000_dma_4_0_n a_12__n un1_rst_dly_i_8__n N_94_i \ +CLK_OUT_PRE_D_i a_11__n pos_clk_un11_clk_000_n_sync_i_n CLK_030_H_i a_10__n \ +AS_000_DMA_i N_73_0 pos_clk_un8_bg_030_n VMA_INT_i a_9__n VPA_D_i N_160_i \ +cpu_est_i_0__n N_161_i a_8__n cpu_est_i_1__n cpu_est_i_3__n N_155_i a_7__n \ +a_i_24__n N_156_i pos_clk_un7_clk_000_d0_i_n a_6__n sm_amiga_i_0__n N_154_i \ +sm_amiga_i_3__n N_152_i a_5__n CLK_000_NE_i N_153_i cpu_est_i_2__n a_4__n \ +sm_amiga_i_1__n N_150_i sm_amiga_i_4__n N_151_i a_3__n sm_amiga_i_2__n \ +pos_clk_un29_clk_000_ne_d0_i_n N_149_i a_2__n DSACK1_INT_0_sqmuxa_i N_147_i \ +RW_i N_148_i un5_ciin_i DTACK_D0_i N_164_i a_i_31__n N_165_i a_i_29__n N_163_i \ +a_i_30__n N_199_i a_i_27__n pos_clk_cpu_est_11_0_3__n pos_clk_un7_clk_000_pe_n \ +a_i_28__n N_197_i a_i_25__n N_198_i DS_000_ENABLE_1_sqmuxa a_i_26__n N_194_i \ +UDS_000_INT_i pos_clk_cpu_est_11_0_1__n LDS_000_INT_i N_192_i DS_030_i N_135_i \ +N_224_i N_162_i N_225_i N_191_i AS_000_INT_1_sqmuxa N_226_i N_193_i \ +DSACK1_INT_1_sqmuxa N_190_i pos_clk_ds_000_dma_4_n N_189_i N_3 \ +DS_000_ENABLE_1_sqmuxa_i N_188_i un6_lds_000_i N_195_i un6_uds_000_i N_196_i \ +N_6 un6_ds_030_i N_186_i N_9 DS_000_DMA_i N_143_0 N_10 un4_as_000_i N_142_0 \ +N_14 un8_ciin_i N_141_0 N_15 un6_as_030_i N_140_0 N_17 DS_030_D0_i N_139_0 \ +N_19 AS_030_c N_166_i N_22 N_137_i N_23 AS_000_c N_136_i N_24 N_133_i N_25 \ +RW_000_c N_132_i N_146_i DS_030_c N_144_i UDS_000_c un1_SM_AMIGA_7_i \ +pos_clk_un21_clk_000_ne_d0_i_n LDS_000_c pos_clk_un27_clk_000_ne_d0_i_n \ +pos_clk_un23_clk_000_ne_d0_0_n size_c_0__n pos_clk_un5_clk_000_pe_i_n \ +pos_clk_un9_clk_000_ne_i_n size_c_1__n pos_clk_un7_clk_000_pe_0_n \ +pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 \ +N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 \ +DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_115 N_50_0 \ +pos_clk_cpu_est_11_1__n N_3_i pos_clk_cpu_est_11_3__n N_49_0 N_220 N_6_i \ +N_48_0 N_9_i N_45_0 un6_uds_000_1 N_10_i pos_clk_un24_bgack_030_int_i_0_n \ +a_c_16__n N_44_0 N_244 N_14_i N_245 a_c_17__n N_41_0 N_15_i N_80 a_c_18__n \ +N_40_0 N_90 N_17_i N_100 a_c_19__n N_38_0 N_105 N_19_i \ +pos_clk_un11_clk_000_n_sync_n a_c_20__n N_36_0 N_22_i a_c_21__n N_33_0 N_135 \ +BG_030_c_i N_133 a_c_22__n pos_clk_un6_bg_030_i_n N_190 pos_clk_un8_bg_030_0_n \ +N_188 a_c_23__n N_127_i_1 N_189 N_127_i_2 N_136 a_c_24__n \ +pos_clk_un11_ds_030_d0_i_1_n pos_clk_un7_clk_000_d0_n N_135_i_1 \ +pos_clk_un29_clk_000_ne_d0_n a_c_25__n pos_clk_cpu_est_11_0_1_1__n \ +DSACK1_INT_0_sqmuxa pos_clk_cpu_est_11_0_2_1__n pos_clk_un21_clk_000_ne_d0_n \ +a_c_26__n pos_clk_cpu_est_11_0_1_3__n pos_clk_un5_clk_000_pe_n N_195_1 \ +pos_clk_un9_clk_000_ne_n a_c_27__n N_196_1 pos_clk_un23_clk_000_ne_d0_n \ +N_131_i_1 pos_clk_un27_clk_000_ne_d0_n a_c_28__n N_131_i_2 \ +pos_clk_un14_clk_000_n_sync_n N_131_i_3 N_144 a_c_29__n N_119_i_1 N_146 \ +N_119_i_2 N_143 a_c_30__n N_121_i_1 N_147 N_123_i_1 N_139 a_c_31__n N_123_i_2 \ +N_148 N_125_i_1 N_149 A0_c N_129_i_1 N_150 N_162_1 N_140 A1_c N_163_1 N_151 \ +N_165_1 N_152 nEXP_SPACE_c N_165_2 N_153 N_165_3 N_154 BERR_c un5_ciin_1 N_155 \ +un5_ciin_2 N_141 BG_030_c un5_ciin_3 N_156 un5_ciin_4 N_160 un5_ciin_5 N_142 \ +un5_ciin_6 N_161 un5_ciin_7 N_164 BGACK_000_c un5_ciin_8 N_166 un5_ciin_9 \ +N_132 un5_ciin_10 N_191 un5_ciin_11 N_192 pos_clk_un9_clk_000_ne_1_n N_193 \ +CLK_OSZI_c pos_clk_un9_clk_000_ne_2_n N_194 pos_clk_un9_clk_000_ne_3_n N_197 \ +pos_clk_un9_clk_000_ne_4_n N_198 CLK_EXP_c pos_clk_un5_clk_000_pe_1_n N_195 \ +pos_clk_un5_clk_000_pe_2_n N_196 pos_clk_un5_clk_000_pe_3_n N_162 FPU_SENSE_c \ +pos_clk_un27_clk_000_ne_d0_1_n N_199 pos_clk_un27_clk_000_ne_d0_2_n N_199_1 \ +pos_clk_un27_clk_000_ne_d0_3_n N_163 RESET_OUT_0_sqmuxa_7_1 N_165 \ +RESET_OUT_0_sqmuxa_7_2 N_73 RESET_OUT_0_sqmuxa_7_3 N_94 RESET_OUT_0_sqmuxa_5_1 \ +N_85 N_87_1 N_84 ipl_c_0__n N_87_2 N_83 pos_clk_un24_bgack_030_int_i_0_0_1_n \ +pos_clk_un9_clk_000_n_sync_n ipl_c_1__n pos_clk_un24_bgack_030_int_i_0_0_2_n \ +N_72_0_1 ipl_c_2__n pos_clk_un7_clk_000_d0_1_n N_213 un21_fpu_cs_1 \ +un22_berr_1_0 N_211 DTACK_c N_116_1 N_116_2 N_209 N_116_3 N_116_4 VPA_c \ +pos_clk_un6_bg_030_1_n N_205 N_115_0_1 N_245_0_1 RESET_OUT_0_sqmuxa_1 RST_c \ +N_247_i_1 RESET_OUT_0_sqmuxa N_248_i_1 RESET_OUT_0_sqmuxa_7 N_249_i_1 \ +RESET_OUT_0_sqmuxa_5 RW_c pos_clk_ipl_1_n un1_rst_dly_i_m_8__n \ +amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n fc_c_0__n \ +amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n \ +amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n fc_c_1__n \ +amiga_bus_enable_dma_low_0_un3_n un1_rst_dly_i_m_4__n \ +amiga_bus_enable_dma_low_0_un1_n un1_rst_dly_i_m_3__n \ +amiga_bus_enable_dma_low_0_un0_n un1_rst_dly_i_m_2__n AMIGA_BUS_DATA_DIR_c \ +rw_000_dma_0_un3_n N_86 rw_000_dma_0_un1_n N_93 rw_000_dma_0_un0_n N_87 \ +bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_030.OE AS_000.OE RW_000.OE \ +DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ +CLK_DIV_OUT.OE DSACK1.OE CIIN.OE pos_clk_un24_bgack_030_int_i_0_x2 \ +cpu_est_0_0_ G_165 G_166 G_167 pos_clk_CYCLE_DMA_5_1_i_x2 \ +pos_clk_CYCLE_DMA_5_0_i_x2 G_149 G_147 G_145 G_143 G_141 G_139 G_137 G_135 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_52_0.BLIF IPL_D0_0_.D +0 1 +.names N_53_0.BLIF IPL_D0_1_.D +0 1 .names N_54_0.BLIF IPL_D0_2_.D 0 1 .names N_131_i_3.BLIF N_165_i.BLIF SM_AMIGA_i_7_.D @@ -527,9 +516,9 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 11 1 .names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 -.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_119_i_1.BLIF N_119_i_2.BLIF SM_AMIGA_1_.D 11 1 -.names N_88_i.BLIF N_137_i.BLIF SM_AMIGA_0_.D +.names N_137_i.BLIF N_146_i.BLIF SM_AMIGA_0_.D 11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 @@ -544,13 +533,7 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 0 1 .names N_31_0.BLIF IPL_030DFF_1_reg.D 0 1 -.names N_32_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names N_52_0.BLIF IPL_D0_0_.D -0 1 -.names N_53_0.BLIF IPL_D0_1_.D -0 1 -.names N_85_i.BLIF RST_c.BLIF RST_DLY_0_.D +.names RST_c.BLIF un1_rst_dly_i_m_i_1__n.BLIF RST_DLY_0_.D 11 1 .names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D 11 1 @@ -566,9 +549,9 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 11 1 .names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D 11 1 -.names G_159.BLIF un1_rst_2.BLIF CYCLE_DMA_0_.D +.names N_249_i_1.BLIF N_257_0.BLIF CYCLE_DMA_0_.D 11 1 -.names G_161.BLIF un1_rst_2.BLIF CYCLE_DMA_1_.D +.names N_248_i_1.BLIF N_257_0.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -578,7 +561,19 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ -1 1 .names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D 11 1 -.names N_42_0.BLIF inst_LDS_000_INT.D +.names N_247_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_93_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D +11 1 +.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_39_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_40_0.BLIF inst_RW_000_INT.D +0 1 +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D 0 1 .names N_43_0.BLIF inst_AS_030_000_SYNC.D 0 1 @@ -594,7 +589,7 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 0 1 .names N_50_0.BLIF inst_DS_030_D0.D 0 1 -.names N_89.BLIF inst_AS_030_D0.D +.names N_90.BLIF inst_AS_030_D0.D 0 1 .names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D 0 1 @@ -602,741 +597,716 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 0 1 .names N_57_0.BLIF inst_DTACK_D0.D 0 1 -.names N_47.BLIF RST_c.BLIF inst_CLK_030_H.D -11 1 -.names N_38.BLIF RST_c.BLIF inst_RESET_OUTreg.D -11 1 -.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_33_0.BLIF inst_BGACK_030_INTreg.D +.names N_33_0.BLIF BG_000DFFreg.D 0 1 -.names N_34_0.BLIF BG_000DFFreg.D +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +.names N_36_0.BLIF inst_VMA_INTreg.D 0 1 -.names N_37_0.BLIF inst_VMA_INTreg.D +.names N_38_0.BLIF inst_UDS_000_INT.D 0 1 -.names N_39_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_40_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_41_0.BLIF inst_RW_000_INT.D -0 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D +.names N_257_0.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_189_i.BLIF cpu_est_0_.BLIF N_193 +.names CLK_000_PE_i.BLIF sm_amiga_i_5__n.BLIF N_159 11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +.names N_21.BLIF N_21_i 0 1 -.names N_190_i.BLIF N_190 -0 1 -.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n 11 1 -.names N_189_i.BLIF N_189 -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names N_138.BLIF sm_amiga_i_6__n.BLIF N_157 11 1 -.names N_140_0.BLIF N_140 -0 1 -.names N_97.BLIF bgack_030_int_0_un3_n -0 1 -.names inst_CLK_000_NE_D0.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF \ -pos_clk_un29_clk_000_ne_d0_n +.names N_21_i.BLIF RST_c.BLIF N_34_0 11 1 -.names inst_BGACK_030_INTreg.BLIF N_97.BLIF bgack_030_int_0_un1_n -11 1 -.names pos_clk_un23_clk_000_ne_d0_0_n.BLIF pos_clk_un23_clk_000_ne_d0_n +.names N_250.BLIF as_030_000_sync_0_un3_n 0 1 -.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_158 11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un21_clk_000_ne_d0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un3_n +.names N_20.BLIF N_20_i 0 1 +.names inst_AS_030_000_SYNC.BLIF N_250.BLIF as_030_000_sync_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_1__n.BLIF un1_rst_dly_i_m_1__n +11 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_105_i.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names N_138_0.BLIF N_138 +0 1 +.names N_16.BLIF N_16_i +0 1 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names BGACK_030_INT_i.BLIF N_256_i.BLIF N_88 +11 1 +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ +ds_000_enable_0_un1_n +11 1 +.names N_256_i.BLIF N_256 +0 1 +.names N_13.BLIF N_13_i +0 1 +.names un1_SM_AMIGA_7_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 .names vcc_n_n 1 -.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n -0 1 -.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un1_n +.names BGACK_030_INT_i.BLIF N_256.BLIF N_89 11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un0_n +.names N_13_i.BLIF RST_c.BLIF N_42_0 11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names SM_AMIGA_5_.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n -0 1 -.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n -11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un1_n -11 1 -.names gnd_n_n -.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \ -pos_clk_un9_clk_000_n_sync_n -11 1 -.names sm_amiga_i_3__n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n.BLIF \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ -un1_amiga_bus_enable_low -11 1 -.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n -0 1 -.names N_246.BLIF size_dma_0_0__un3_n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names pos_clk_un22_bgack_030_int_0_n.BLIF pos_clk_un22_bgack_030_int_n -0 1 -.names N_6.BLIF N_6_i -0 1 -.names pos_clk_size_dma_6_0__n.BLIF N_246.BLIF size_dma_0_0__un1_n -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names N_6_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 -11 1 -.names N_3.BLIF N_3_i -0 1 -.names N_246.BLIF size_dma_0_1__un3_n -0 1 -.names un8_ciin_8.BLIF un8_ciin_5.BLIF un8_ciin -11 1 -.names N_3_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_246.BLIF size_dma_0_1__un1_n -11 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF un14_amiga_bus_data_dir -11 1 -.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF pos_clk_un40_bgack_030_int_1_n -11 1 -.names pos_clk_un29_bgack_030_int_n.BLIF pos_clk_un29_bgack_030_int_i_n -0 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names AS_000_DMA_1_sqmuxa.BLIF AS_000_DMA_i.BLIF CLK_030_H_0_sqmuxa -11 1 -.names pos_clk_un26_bgack_030_int_n.BLIF pos_clk_un26_bgack_030_int_i_n -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 -.names CLK_EXP_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa -11 1 -.names pos_clk_un26_bgack_030_int_i_n.BLIF pos_clk_un29_bgack_030_int_i_n.BLIF \ -pos_clk_un27_bgack_030_int_0_n -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names un22_berr_1_0.BLIF N_116.BLIF un22_berr -11 1 -.names pos_clk_un24_bgack_030_int_1_n.BLIF pos_clk_un27_bgack_030_int_n.BLIF \ -pos_clk_un24_bgack_030_int_n -11 1 -.names CLK_030_H_0_sqmuxa.BLIF CLK_030_H_0_sqmuxa_i -0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names pos_clk_un27_bgack_030_int_0_n.BLIF pos_clk_un27_bgack_030_int_n -0 1 -.names N_7.BLIF N_7_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_176_1 -11 1 -.names CLK_030_H_0_sqmuxa_i.BLIF N_7_i.BLIF N_47_0 -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 -11 1 -.names N_165_3.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_165 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_133_i -11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_133_i.BLIF N_133 -0 1 -.names N_176.BLIF N_176_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names N_163_1.BLIF CLK_000_NE_i.BLIF N_163 -11 1 -.names N_175.BLIF N_175_i -0 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names N_162_1.BLIF CLK_000_PE_i.BLIF N_162 -11 1 -.names N_175_i.BLIF N_176_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names BERR_i.BLIF N_136_i.BLIF N_164 -11 1 -.names AS_000_DMA_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF \ -pos_clk_ds_000_dma_4_f1_0_n -11 1 -.names N_242.BLIF dsack1_int_0_un3_n -0 1 -.names N_176_1_0.BLIF nEXP_SPACE_D0_i.BLIF N_176 -11 1 -.names N_162.BLIF N_162_i -0 1 -.names N_80_i.BLIF N_242.BLIF dsack1_int_0_un1_n -11 1 -.names DS_000_DMA_2_sqmuxa_1.BLIF pos_clk_un40_bgack_030_int_1_i_n.BLIF \ -DS_000_DMA_2_sqmuxa -11 1 -.names N_163.BLIF N_163_i -0 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names DS_000_DMA_0_sqmuxa_i.BLIF pos_clk_ds_000_dma_4_f1_n.BLIF \ -pos_clk_ds_000_dma_4_n -11 1 -.names N_164.BLIF N_164_i -0 1 -.names N_243.BLIF as_000_int_0_un3_n -0 1 -.names RW_000_c.BLIF pos_clk_un24_bgack_030_int_n.BLIF DS_000_DMA_0_sqmuxa -11 1 -.names N_165.BLIF N_165_i -0 1 -.names sm_amiga_i_5__n.BLIF N_243.BLIF as_000_int_0_un1_n -11 1 -.names pos_clk_ds_000_dma_4_f1_0_n.BLIF pos_clk_ds_000_dma_4_f1_n -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_175 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_0_n -11 1 -.names N_241.BLIF ds_000_enable_0_un3_n -0 1 -.names N_47_0.BLIF N_47 -0 1 -.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n -0 1 -.names N_248_i.BLIF N_241.BLIF ds_000_enable_0_un1_n -11 1 -.names inst_CLK_030_H.BLIF pos_clk_un24_bgack_030_int_n.BLIF N_7 -11 1 -.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n -0 1 -.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ -ds_000_enable_0_un0_n -11 1 -.names N_176_1.BLIF RST_c.BLIF un1_rst_2 -11 1 -.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ -pos_clk_un14_clk_000_n_sync_0_n -11 1 -.names N_244.BLIF as_030_000_sync_0_un3_n -0 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_0__n.BLIF pos_clk_un26_bgack_030_int_n -11 1 -.names N_22.BLIF N_22_i -0 1 -.names inst_AS_030_000_SYNC.BLIF N_244.BLIF as_030_000_sync_0_un1_n -11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_1__n.BLIF pos_clk_un29_bgack_030_int_n -11 1 -.names N_22_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_18.BLIF N_18_i -0 1 -.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_18_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ -lds_000_int_0_un1_n -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names pos_clk_un9_clk_000_ne_n.BLIF pos_clk_un9_clk_000_ne_i_n -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names pos_clk_un5_clk_000_pe_n.BLIF pos_clk_un5_clk_000_pe_i_n -0 1 -.names N_115.BLIF rw_000_int_0_un3_n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ -pos_clk_un7_clk_000_pe_0_n -11 1 -.names N_245.BLIF N_115.BLIF rw_000_int_0_un1_n -11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names pos_clk_un27_clk_000_ne_d0_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n -0 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names pos_clk_un24_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_n -0 1 -.names pos_clk_un21_clk_000_ne_d0_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n -0 1 -.names pos_clk_un21_clk_000_ne_d0_i_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF \ -pos_clk_un23_clk_000_ne_d0_0_n -11 1 -.names un14_amiga_bus_data_dir_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -rw_000_dma_0_un1_n -11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names SM_AMIGA_3_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_136_i -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_132_i.BLIF SM_AMIGA_2_.BLIF N_140_0 -11 1 -.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n -0 1 -.names CLK_EXP_c.BLIF CLK_EXP_i -0 1 -.names N_195.BLIF N_195_i -0 1 -.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n -11 1 -.names BERR_c.BLIF BERR_i -0 1 -.names N_196.BLIF N_196_i -0 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_195_i.BLIF N_196_i.BLIF N_186_i -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names DS_000_DMA_0_sqmuxa.BLIF DS_000_DMA_0_sqmuxa_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_188_i -11 1 -.names N_90_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_low_0_un1_n -11 1 -.names pos_clk_un40_bgack_030_int_1_n.BLIF pos_clk_un40_bgack_030_int_1_i_n -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_189_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_190_i -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i -0 1 -.names N_193.BLIF N_193_i -0 1 -.names N_91_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_high_0_un1_n -11 1 -.names inst_CLK_000_PE.BLIF CLK_000_PE_i -0 1 -.names N_191.BLIF N_191_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names inst_CLK_000_NE.BLIF CLK_000_NE_i -0 1 -.names N_192.BLIF N_192_i -0 1 -.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_194.BLIF N_194_i -0 1 -.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \ -pos_clk_cpu_est_11_0_1__n -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names pos_clk_un7_clk_000_d0_n.BLIF pos_clk_un7_clk_000_d0_i_n -0 1 -.names N_198.BLIF N_198_i -0 1 .names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n 0 1 -.names UDS_000_c.BLIF UDS_000_i -0 1 -.names N_197.BLIF N_197_i +.names A1_c.BLIF BGACK_030_INT_i.BLIF N_91 +11 1 +.names N_12.BLIF N_12_i 0 1 .names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ a0_dma_0_un1_n 11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names N_199.BLIF N_199_i -0 1 +.names A1_i.BLIF BGACK_030_INT_i.BLIF N_92 +11 1 +.names N_12_i.BLIF RST_c.BLIF N_43_0 +11 1 .names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF pos_clk_clk_000_n_sync_2_0__n +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 -.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +.names N_8.BLIF N_8_i 0 1 -.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_198_i.BLIF pos_clk_cpu_est_11_0_3__n +.names N_252.BLIF size_dma_0_1__un3_n +0 1 +.names gnd_n_n +.names N_72.BLIF N_105.BLIF N_96 11 1 -.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +.names N_8_i.BLIF RST_c.BLIF N_46_0 11 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names N_151.BLIF N_151_i -0 1 -.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +.names pos_clk_size_dma_6_1__n.BLIF N_252.BLIF size_dma_0_1__un1_n 11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_150.BLIF N_150_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low 11 1 -.names pos_clk_un29_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_i_n +.names N_72_0.BLIF N_72 0 1 -.names N_135_i_1.BLIF sm_amiga_i_6__n.BLIF N_135_i +.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_76_i 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_252_0 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names N_85.BLIF N_85_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_38_0 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n -0 1 -.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i -0 1 -.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n -0 1 -.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_77_i_i -0 1 -.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n -0 1 -.names G_137.BLIF un1_rst_dly_i_2__n -0 1 -.names G_139.BLIF un1_rst_dly_i_3__n -0 1 -.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n -0 1 -.names G_141.BLIF un1_rst_dly_i_4__n -0 1 -.names G_143.BLIF un1_rst_dly_i_5__n -0 1 -.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n -0 1 -.names G_145.BLIF un1_rst_dly_i_6__n -0 1 -.names G_147.BLIF un1_rst_dly_i_7__n -0 1 -.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n -0 1 -.names G_149.BLIF un1_rst_dly_i_8__n -0 1 -.names inst_RESET_OUTreg.BLIF RESET_OUT_i -0 1 -.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names inst_RESET_OUTreg.BLIF un1_as_030_i.BLIF un3_as_030_i +.names N_105.BLIF N_116.BLIF N_97 11 1 -.names A1_c.BLIF A1_i -0 1 -.names N_76.BLIF N_76_i -0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names N_83.BLIF N_83_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_248.BLIF N_248_i -0 1 -.names N_84.BLIF N_84_i -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +.names N_72_0_1.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_72_0 11 1 -.names RW_c.BLIF RW_i +.names N_252.BLIF size_dma_0_0__un3_n 0 1 -.names N_86.BLIF N_86_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names N_86_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_87.BLIF N_87_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_87_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names N_116_4.BLIF N_116_3.BLIF N_116 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names UDS_000_c.BLIF UDS_000_c_i 0 1 -.names N_88.BLIF N_88_i -0 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names N_248.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_241_0 +.names pos_clk_size_dma_6_0__n.BLIF N_252.BLIF size_dma_0_0__un1_n 11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_80_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_242_0 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size 11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_243_0 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_104 11 1 -.names a_c_18__n.BLIF a_i_18__n +.names LDS_000_c.BLIF LDS_000_c_i 0 1 -.names N_93.BLIF N_93_i -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names N_93_i.BLIF N_94_i.BLIF N_244_0 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n 11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF N_245_0 +.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin 11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +.names N_76_i.BLIF N_76 0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_246_0 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_256_i 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF un8_ciin 11 1 -.names a_c_26__n.BLIF a_i_26__n +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n 0 1 .names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ pos_clk_un5_bgack_030_int_d_i_n 11 1 -.names a_c_27__n.BLIF a_i_27__n +.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n 0 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF N_249_i +.names pos_clk_un24_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un24_bgack_030_int_i_0_0_n 11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n 11 1 -.names a_c_24__n.BLIF a_i_24__n +.names un1_SM_AMIGA_7_i.BLIF un1_SM_AMIGA_7 0 1 -.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0 -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_71_0 -11 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i +.names N_250_0.BLIF N_250 0 1 .names N_104.BLIF N_104_i 0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_252_0 +11 1 +.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names un22_berr_1_0.BLIF N_116.BLIF un22_berr +11 1 +.names N_251_0.BLIF N_251 +0 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_251_0 +11 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_252_0.BLIF N_252 +0 1 +.names BGACK_000_c.BLIF N_76.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n +0 1 +.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 +11 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names N_97.BLIF N_97_i +0 1 +.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +11 1 +.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +11 1 +.names N_96.BLIF N_96_i +0 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_105.BLIF un1_SM_AMIGA_7.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names N_96_i.BLIF N_97_i.BLIF N_250_0 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names N_89.BLIF N_89_i +0 1 +.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 .names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 1- 1 -1 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names N_104_i.BLIF RST_c.BLIF N_137_i +.names N_89_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 -1- 1 --1 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 -1- 1 --1 1 -.names G_165.BLIF N_224_i -0 1 -.names N_160.BLIF N_160_i -0 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 -1- 1 --1 1 -.names G_166.BLIF N_225_i -0 1 -.names N_161.BLIF N_161_i -0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12 1- 1 -1 1 -.names G_167.BLIF N_226_i +.names N_88.BLIF N_88_i 0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names N_159.BLIF N_159_i +.names N_88_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_138_0 +11 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names un1_rst_dly_i_m_1__n.BLIF un1_rst_dly_i_m_i_1__n 0 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 1- 1 -1 1 .names N_157.BLIF N_157_i 0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15 -1- 1 --1 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 .names N_158.BLIF N_158_i 0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16 -1- 1 --1 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names N_159.BLIF N_159_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_257_0 +11 1 +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i +11 1 +.names inst_DSACK1_INTreg.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_93.BLIF N_93_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names N_105.BLIF N_105_i +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 .names N_91.BLIF N_91_i 0 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_90.BLIF N_90_i +.names N_87.BLIF N_87_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names N_92.BLIF N_92_i +0 1 +.names N_86.BLIF N_86_i +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names N_86_i.BLIF N_87_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n +0 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n +0 1 +.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +lds_000_int_0_un1_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n +0 1 +.names N_115.BLIF rw_000_int_0_un3_n +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_115.BLIF rw_000_int_0_un1_n +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n +0 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n +0 1 +.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n +0 1 +.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names inst_CLK_000_PE.BLIF CLK_000_PE_i +0 1 +.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i +0 1 +.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n +0 1 +.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names A1_c.BLIF A1_i +0 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names inst_RESET_OUTreg.BLIF un1_as_030_i.BLIF un3_as_030_i +11 1 +.names N_245.BLIF ds_000_dma_0_un3_n +0 1 +.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_245.BLIF ds_000_dma_0_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n +0 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i +0 1 +.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n +0 1 +.names N_244.BLIF as_000_dma_0_un3_n +0 1 +.names G_135.BLIF un1_rst_dly_i_1__n +0 1 +.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ +pos_clk_un14_clk_000_n_sync_0_n +11 1 +.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_244.BLIF as_000_dma_0_un1_n +11 1 +.names inst_RESET_OUTreg.BLIF RESET_OUT_i +0 1 +.names CLK_EXP_c.BLIF CLK_EXP_c_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF pos_clk_clk_000_n_sync_2_0__n +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF N_244_0 +11 1 +.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +11 1 +.names G_137.BLIF un1_rst_dly_i_2__n +0 1 +.names N_83.BLIF N_83_i +0 1 +.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +11 1 +.names G_139.BLIF un1_rst_dly_i_3__n +0 1 +.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +11 1 +.names G_141.BLIF un1_rst_dly_i_4__n +0 1 +.names N_84.BLIF N_84_i +0 1 +.names G_143.BLIF un1_rst_dly_i_5__n +0 1 +.names N_245_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF N_245_0 +11 1 +.names G_145.BLIF un1_rst_dly_i_6__n +0 1 +.names N_85.BLIF N_85_i +0 1 +.names G_147.BLIF un1_rst_dly_i_7__n +0 1 +.names N_85_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names G_149.BLIF un1_rst_dly_i_8__n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_73_0 +11 1 +.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_160.BLIF N_160_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names N_161.BLIF N_161_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 .names N_155.BLIF N_155_i 0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names un14_amiga_bus_data_dir.BLIF un14_amiga_bus_data_dir_i +.names a_c_24__n.BLIF a_i_24__n 0 1 .names N_156.BLIF N_156_i 0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_80.BLIF N_80_i +.names pos_clk_un7_clk_000_d0_n.BLIF pos_clk_un7_clk_000_d0_i_n 0 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 -1- 1 --1 1 -.names un6_lds_000.BLIF un6_lds_000_i +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n 0 1 .names N_154.BLIF N_154_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 -1- 1 --1 1 -.names un6_uds_000.BLIF un6_uds_000_i +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 .names N_152.BLIF N_152_i 0 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names N_153.BLIF N_153_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_150.BLIF N_150_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_151.BLIF N_151_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names pos_clk_un29_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_i_n +0 1 +.names N_149.BLIF N_149_i +0 1 +.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i +0 1 +.names N_147.BLIF N_147_i +0 1 +.names RW_c.BLIF RW_i +0 1 +.names N_148.BLIF N_148_i +0 1 +.names un5_ciin.BLIF un5_ciin_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_164.BLIF N_164_i +0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names N_165.BLIF N_165_i +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names N_163.BLIF N_163_i +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names N_199.BLIF N_199_i +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_198_i.BLIF pos_clk_cpu_est_11_0_3__n +11 1 +.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names N_197.BLIF N_197_i +0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names N_198.BLIF N_198_i +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names N_194.BLIF N_194_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \ +pos_clk_cpu_est_11_0_1__n +11 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_192.BLIF N_192_i +0 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names N_135_i_1.BLIF sm_amiga_i_6__n.BLIF N_135_i +11 1 +.names G_165.BLIF N_224_i +0 1 +.names N_162.BLIF N_162_i +0 1 +.names G_166.BLIF N_225_i +0 1 +.names N_191.BLIF N_191_i +0 1 +.names N_105.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names G_167.BLIF N_226_i +0 1 +.names N_193.BLIF N_193_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF N_105.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_190_i +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_189_i +11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_188_i +11 1 +.names un6_lds_000.BLIF un6_lds_000_i +0 1 +.names N_195.BLIF N_195_i +0 1 +.names un6_uds_000.BLIF un6_uds_000_i +0 1 +.names N_196.BLIF N_196_i +0 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 1- 1 -1 1 .names un6_ds_030.BLIF un6_ds_030_i 0 1 -.names N_153.BLIF N_153_i +.names N_195_i.BLIF N_196_i.BLIF N_186_i +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i 0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_143_0 +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 .names un4_as_000.BLIF un4_as_000_i 0 1 .names N_132_i.BLIF SM_AMIGA_6_.BLIF N_142_0 11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names un8_ciin.BLIF un8_ciin_i 0 1 .names N_132_i.BLIF SM_AMIGA_4_.BLIF N_141_0 11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_15 +1- 1 +-1 1 .names un6_as_030.BLIF un6_as_030_i 0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_138_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names BERR_c.BLIF CLK_000_PE_i.BLIF N_132_i +.names N_132_i.BLIF SM_AMIGA_2_.BLIF N_140_0 11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 +1- 1 +-1 1 .names inst_DS_030_D0.BLIF DS_030_D0_i 0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_139_0 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names N_166.BLIF N_166_i +0 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_166_i.BLIF RST_c.BLIF N_137_i +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 +1- 1 +-1 1 +.names SM_AMIGA_3_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_136_i +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 +1- 1 +-1 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_133_i +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +1- 1 +-1 1 +.names BERR_c.BLIF CLK_000_PE_i.BLIF N_132_i +11 1 +.names N_146.BLIF N_146_i +0 1 +.names N_144.BLIF N_144_i +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_144_i.BLIF un1_SM_AMIGA_7_i +11 1 +.names pos_clk_un21_clk_000_ne_d0_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n +0 1 +.names pos_clk_un27_clk_000_ne_d0_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n +0 1 +.names pos_clk_un21_clk_000_ne_d0_i_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF \ +pos_clk_un23_clk_000_ne_d0_0_n +11 1 +.names pos_clk_un5_clk_000_pe_n.BLIF pos_clk_un5_clk_000_pe_i_n +0 1 +.names pos_clk_un9_clk_000_ne_n.BLIF pos_clk_un9_clk_000_ne_i_n +0 1 +.names pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ +pos_clk_un7_clk_000_pe_0_n 11 1 .names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF \ pos_clk_un11_ds_030_d0_i_n @@ -1381,406 +1351,404 @@ pos_clk_un11_ds_030_d0_i_n 0 1 .names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 11 1 +.names N_115_0.BLIF N_115 +0 1 .names DS_030_i.BLIF RST_c.BLIF N_50_0 11 1 -.names N_8.BLIF N_8_i +.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n 0 1 -.names N_8_i.BLIF RST_c.BLIF N_46_0 +.names N_3.BLIF N_3_i +0 1 +.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n +0 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 +11 1 +.names N_6.BLIF N_6_i +0 1 +.names N_6_i.BLIF RST_c.BLIF N_48_0 11 1 .names N_9.BLIF N_9_i 0 1 .names N_9_i.BLIF RST_c.BLIF N_45_0 11 1 +.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +11 1 .names N_10.BLIF N_10_i 0 1 +.names pos_clk_un24_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_n +0 1 .names N_10_i.BLIF RST_c.BLIF N_44_0 11 1 -.names N_115_0.BLIF N_115 -0 1 -.names N_12.BLIF N_12_i -0 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names N_12_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names N_13.BLIF N_13_i -0 1 -.names N_13_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names N_14.BLIF N_14_i -0 1 -.names N_14_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 -11 1 -.names N_15.BLIF N_15_i -0 1 -.names N_241_0.BLIF N_241 -0 1 -.names N_15_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names N_242_0.BLIF N_242 -0 1 -.names N_16.BLIF N_16_i -0 1 -.names N_243_0.BLIF N_243 -0 1 -.names N_16_i.BLIF RST_c.BLIF N_39_0 -11 1 .names N_244_0.BLIF N_244 0 1 -.names N_19.BLIF N_19_i +.names N_14.BLIF N_14_i 0 1 .names N_245_0.BLIF N_245 0 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_15.BLIF N_15_i +0 1 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_80 +1- 1 +-1 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_90 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_100 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF N_105 +11 1 +.names N_19.BLIF N_19_i +0 1 +.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n +11 1 .names N_19_i.BLIF RST_c.BLIF N_36_0 11 1 -.names N_246_0.BLIF N_246 +.names N_22.BLIF N_22_i 0 1 -.names N_20.BLIF N_20_i -0 1 -.names un1_amiga_bus_enable_dma_high_i_m4_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un0_n.BLIF N_78 -1- 1 --1 1 -.names N_20_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_80 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_89 -11 1 -.names N_21_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names A1_c.BLIF BGACK_030_INT_i.BLIF N_90 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names A1_i.BLIF BGACK_030_INT_i.BLIF N_91 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF N_98 -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n -11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_99 -11 1 -.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_251_0_1 -11 1 -.names N_249_i.BLIF N_249 -0 1 -.names N_150_i.BLIF N_151_i.BLIF N_121_i_1 -11 1 -.names ds_000_enable_1_sqmuxa_1_i_m4_un1_n.BLIF \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n.BLIF N_248 -1- 1 --1 1 -.names N_199_i.BLIF N_197_i.BLIF pos_clk_cpu_est_11_0_1_3__n +.names N_22_i.BLIF RST_c.BLIF N_33_0 11 1 .names N_135_i.BLIF N_135 0 1 -.names N_194_i.BLIF N_192_i.BLIF pos_clk_cpu_est_11_0_1_1__n +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_133_i.BLIF N_133 +0 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names N_190_i.BLIF N_190 +0 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +11 1 +.names N_188_i.BLIF N_188 +0 1 +.names N_157_i.BLIF N_158_i.BLIF N_127_i_1 +11 1 +.names N_189_i.BLIF N_189 +0 1 +.names N_159_i.BLIF RST_c.BLIF N_127_i_2 11 1 .names N_136_i.BLIF N_136 0 1 -.names N_191_i.BLIF N_193_i.BLIF pos_clk_cpu_est_11_0_2_1__n +.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n 11 1 .names pos_clk_un7_clk_000_d0_1_n.BLIF inst_nEXP_SPACE_D0reg.BLIF \ pos_clk_un7_clk_000_d0_n 11 1 -.names N_163_i.BLIF N_137_i.BLIF N_131_i_1 -11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 -11 1 -.names N_162_i.BLIF N_164_i.BLIF N_131_i_2 -11 1 -.names N_136.BLIF sm_amiga_i_4__n.BLIF N_152 -11 1 -.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 -11 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_153 -11 1 -.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n -11 1 -.names CLK_000_PE_i.BLIF sm_amiga_i_3__n.BLIF N_154 -11 1 -.names a_i_31__n.BLIF inst_nEXP_SPACE_D0reg.BLIF un8_ciin_1 -11 1 -.names N_141.BLIF sm_amiga_i_5__n.BLIF N_155 -11 1 -.names AS_030_D0_i.BLIF a_i_24__n.BLIF un8_ciin_2 -11 1 -.names N_141_0.BLIF N_141 -0 1 -.names a_i_25__n.BLIF a_i_26__n.BLIF un8_ciin_3 -11 1 -.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_156 -11 1 -.names a_i_27__n.BLIF a_i_28__n.BLIF un8_ciin_4 -11 1 -.names N_138.BLIF sm_amiga_i_6__n.BLIF N_157 -11 1 -.names a_i_29__n.BLIF a_i_30__n.BLIF un8_ciin_5 -11 1 -.names N_138_0.BLIF N_138 -0 1 -.names un8_ciin_1.BLIF un8_ciin_2.BLIF un8_ciin_6 -11 1 -.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_158 -11 1 -.names un8_ciin_3.BLIF un8_ciin_4.BLIF un8_ciin_7 -11 1 -.names CLK_000_PE_i.BLIF sm_amiga_i_5__n.BLIF N_159 -11 1 -.names un8_ciin_6.BLIF un8_ciin_7.BLIF un8_ciin_8 -11 1 -.names N_142.BLIF SM_AMIGA_i_7_.BLIF N_160 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_116_1 -11 1 -.names N_142_0.BLIF N_142 -0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF N_116_2 -11 1 -.names sm_amiga_i_6__n.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_161 -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF N_116_3 -11 1 -.names N_132_i.BLIF N_132 -0 1 -.names N_116_1.BLIF N_116_2.BLIF N_116_4 -11 1 -.names N_132.BLIF SM_AMIGA_0_.BLIF N_104 -11 1 -.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 -11 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_76 -1- 1 --1 1 -.names FPU_SENSE_i.BLIF N_116.BLIF un21_fpu_cs_1 -11 1 -.names N_71_0.BLIF N_71 -0 1 -.names N_152_i.BLIF N_153_i.BLIF N_123_i_1 -11 1 -.names N_251_0.BLIF N_251 -0 1 -.names N_154_i.BLIF RST_c.BLIF N_123_i_2 -11 1 -.names N_251.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_93 -11 1 -.names N_155_i.BLIF N_156_i.BLIF N_125_i_1 -11 1 -.names N_116.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_94 -11 1 -.names N_157_i.BLIF N_158_i.BLIF N_127_i_1 -11 1 -.names N_71.BLIF sm_amiga_i_0__n.BLIF N_88 -11 1 -.names N_159_i.BLIF RST_c.BLIF N_127_i_2 -11 1 -.names BGACK_030_INT_i.BLIF N_249.BLIF N_87 -11 1 -.names N_160_i.BLIF N_161_i.BLIF N_129_i_1 -11 1 -.names BGACK_030_INT_i.BLIF N_249_i.BLIF N_86 -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84 -11 1 -.names pos_clk_clk_000_n_sync_2_0__n.BLIF AS_030_000_SYNC_i.BLIF \ -pos_clk_un7_clk_000_d0_1_n -11 1 -.names N_252.BLIF sm_amiga_i_2__n.BLIF N_83 -11 1 -.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 -11 1 -.names N_116_4.BLIF N_116_3.BLIF N_116 -11 1 -.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 -11 1 -.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ -RESET_OUT_0_sqmuxa_7_3 -11 1 -.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 -11 1 -.names N_211.BLIF RST_DLY_5_.BLIF N_213 -11 1 .names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_135_i_1 11 1 -.names cpu_est_3_reg.BLIF N_199_1.BLIF pos_clk_un27_clk_000_ne_d0_1_n +.names inst_CLK_000_NE_D0.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF \ +pos_clk_un29_clk_000_ne_d0_n 11 1 -.names N_209.BLIF RST_DLY_4_.BLIF N_211 +.names N_191_i.BLIF N_192_i.BLIF pos_clk_cpu_est_11_0_1_1__n 11 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF pos_clk_un27_clk_000_ne_d0_2_n +.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF DSACK1_INT_0_sqmuxa 11 1 -.names pos_clk_un27_clk_000_ne_d0_1_n.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF \ -pos_clk_un27_clk_000_ne_d0_3_n +.names N_193_i.BLIF N_194_i.BLIF pos_clk_cpu_est_11_0_2_1__n 11 1 -.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un21_clk_000_ne_d0_n 11 1 -.names cpu_est_i_3__n.BLIF inst_CLK_000_PE.BLIF pos_clk_un5_clk_000_pe_1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF pos_clk_un5_clk_000_pe_2_n -11 1 -.names pos_clk_un5_clk_000_pe_1_n.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ -pos_clk_un5_clk_000_pe_3_n -11 1 -.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF pos_clk_un9_clk_000_ne_1_n -11 1 -.names inst_CLK_000_NE.BLIF VPA_D_i.BLIF pos_clk_un9_clk_000_ne_2_n -11 1 -.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF pos_clk_un9_clk_000_ne_3_n -11 1 -.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa -11 1 -.names pos_clk_un9_clk_000_ne_1_n.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF \ -pos_clk_un9_clk_000_ne_4_n -11 1 -.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_196_1 -11 1 -.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 -11 1 -.names N_188.BLIF cpu_est_0_.BLIF N_195_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n -11 1 -.names N_176_1.BLIF pos_clk_un22_bgack_030_int_n.BLIF \ -pos_clk_un24_bgack_030_int_1_n -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n -11 1 -.names N_133_i.BLIF N_135_i.BLIF N_165_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n -11 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_165_2 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n -11 1 -.names N_165_1.BLIF N_165_2.BLIF N_165_3 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n -11 1 -.names N_133.BLIF BERR_i.BLIF N_163_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n -11 1 -.names N_135.BLIF BERR_i.BLIF N_162_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n -11 1 -.names N_176_1.BLIF RW_000_c.BLIF N_176_1_0 -11 1 -.names N_38_0.BLIF N_38 -0 1 -.names RW_000_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF DS_000_DMA_2_sqmuxa_1 -11 1 -.names N_77_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_85 -11 1 -.names N_76_i.BLIF N_83_i.BLIF N_119_i_1 -11 1 -.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 -11 1 -.names N_252_0.BLIF N_252 -0 1 -.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n -11 1 -.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_97 -11 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names pos_clk_un27_clk_000_ne_d0_3_n.BLIF cpu_est_2_.BLIF \ -pos_clk_un27_clk_000_ne_d0_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_199_1 -11 1 -.names pos_clk_un24_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \ -as_000_dma_0_un0_n +.names N_199_i.BLIF N_197_i.BLIF pos_clk_cpu_est_11_0_1_3__n 11 1 .names pos_clk_un5_clk_000_pe_3_n.BLIF cpu_est_i_0__n.BLIF \ pos_clk_un5_clk_000_pe_n 11 1 -.names DS_000_DMA_2_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 +.names N_188.BLIF cpu_est_0_.BLIF N_195_1 +11 1 .names pos_clk_un9_clk_000_ne_4_n.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF \ pos_clk_un9_clk_000_ne_n 11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_2_sqmuxa.BLIF ds_000_dma_0_un1_n +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_196_1 +11 1 +.names pos_clk_un23_clk_000_ne_d0_0_n.BLIF pos_clk_un23_clk_000_ne_d0_n +0 1 +.names N_137_i.BLIF N_162_i.BLIF N_131_i_1 +11 1 +.names pos_clk_un27_clk_000_ne_d0_3_n.BLIF cpu_est_2_.BLIF \ +pos_clk_un27_clk_000_ne_d0_n +11 1 +.names N_163_i.BLIF N_164_i.BLIF N_131_i_2 +11 1 +.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n +0 1 +.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_5__n.BLIF N_144 +11 1 +.names N_147_i.BLIF N_148_i.BLIF N_119_i_1 +11 1 +.names N_143.BLIF sm_amiga_i_0__n.BLIF N_146 +11 1 +.names N_149_i.BLIF RST_c.BLIF N_119_i_2 +11 1 +.names N_143_0.BLIF N_143 +0 1 +.names N_150_i.BLIF N_151_i.BLIF N_121_i_1 +11 1 +.names N_139.BLIF sm_amiga_i_2__n.BLIF N_147 +11 1 +.names N_152_i.BLIF N_153_i.BLIF N_123_i_1 +11 1 +.names N_139_0.BLIF N_139 +0 1 +.names N_154_i.BLIF RST_c.BLIF N_123_i_2 +11 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF N_148 +11 1 +.names N_155_i.BLIF N_156_i.BLIF N_125_i_1 +11 1 +.names CLK_000_PE_i.BLIF sm_amiga_i_1__n.BLIF N_149 +11 1 +.names N_160_i.BLIF N_161_i.BLIF N_129_i_1 11 1 .names N_140.BLIF sm_amiga_i_3__n.BLIF N_150 11 1 -.names pos_clk_ds_000_dma_4_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +.names N_135.BLIF BERR_i.BLIF N_162_1 +11 1 +.names N_140_0.BLIF N_140 +0 1 +.names N_133.BLIF BERR_i.BLIF N_163_1 11 1 .names sm_amiga_i_2__n.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_151 11 1 -.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +.names N_133_i.BLIF N_135_i.BLIF N_165_1 +11 1 +.names N_136.BLIF sm_amiga_i_4__n.BLIF N_152 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_165_2 +11 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_153 +11 1 +.names N_165_1.BLIF N_165_2.BLIF N_165_3 +11 1 +.names CLK_000_PE_i.BLIF sm_amiga_i_3__n.BLIF N_154 +11 1 +.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 +11 1 +.names N_141.BLIF sm_amiga_i_5__n.BLIF N_155 +11 1 +.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 +11 1 +.names N_141_0.BLIF N_141 0 1 -.names N_199_1.BLIF cpu_est_i_2__n.BLIF N_199 +.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 11 1 -.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_156 11 1 -.names N_196_1.BLIF cpu_est_i_2__n.BLIF N_196 +.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names N_142.BLIF SM_AMIGA_i_7_.BLIF N_160 11 1 -.names N_195_1.BLIF cpu_est_i_3__n.BLIF N_195 +.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n +.names N_142_0.BLIF N_142 0 1 -.names N_188_i.BLIF N_188 +.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +11 1 +.names sm_amiga_i_6__n.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_161 +11 1 +.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +11 1 +.names BERR_i.BLIF N_136_i.BLIF N_164 +11 1 +.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +11 1 +.names N_132.BLIF SM_AMIGA_0_.BLIF N_166 +11 1 +.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +11 1 +.names N_132_i.BLIF N_132 0 1 -.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n -11 1 -.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n -0 1 -.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_190.BLIF cpu_est_3_reg.BLIF N_197 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names N_190_i.BLIF cpu_est_i_2__n.BLIF N_198 -11 1 -.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n -11 1 -.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_188_i.BLIF cpu_est_3_reg.BLIF N_194 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_192 -11 1 -.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 11 1 .names N_189.BLIF cpu_est_i_0__n.BLIF N_191 11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 11 1 -.names N_220.BLIF CYCLE_DMA_1_.BLIF G_161 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF G_159 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_192 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF pos_clk_un9_clk_000_ne_1_n +11 1 +.names N_189_i.BLIF cpu_est_0_.BLIF N_193 +11 1 +.names inst_CLK_000_NE.BLIF VPA_D_i.BLIF pos_clk_un9_clk_000_ne_2_n +11 1 +.names N_188_i.BLIF cpu_est_3_reg.BLIF N_194 +11 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF pos_clk_un9_clk_000_ne_3_n +11 1 +.names N_190.BLIF cpu_est_3_reg.BLIF N_197 +11 1 +.names pos_clk_un9_clk_000_ne_1_n.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF \ +pos_clk_un9_clk_000_ne_4_n +11 1 +.names N_190_i.BLIF cpu_est_i_2__n.BLIF N_198 +11 1 +.names cpu_est_i_3__n.BLIF inst_CLK_000_PE.BLIF pos_clk_un5_clk_000_pe_1_n +11 1 +.names N_195_1.BLIF cpu_est_i_3__n.BLIF N_195 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF pos_clk_un5_clk_000_pe_2_n +11 1 +.names N_196_1.BLIF cpu_est_i_2__n.BLIF N_196 +11 1 +.names pos_clk_un5_clk_000_pe_1_n.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ +pos_clk_un5_clk_000_pe_3_n +11 1 +.names N_162_1.BLIF CLK_000_PE_i.BLIF N_162 +11 1 +.names cpu_est_3_reg.BLIF N_199_1.BLIF pos_clk_un27_clk_000_ne_d0_1_n +11 1 +.names N_199_1.BLIF cpu_est_i_2__n.BLIF N_199 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF pos_clk_un27_clk_000_ne_d0_2_n +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_199_1 +11 1 +.names pos_clk_un27_clk_000_ne_d0_1_n.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF \ +pos_clk_un27_clk_000_ne_d0_3_n +11 1 +.names N_163_1.BLIF CLK_000_NE_i.BLIF N_163 +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 +11 1 +.names N_165_3.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_165 +11 1 +.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 +11 1 +.names N_73_0.BLIF N_73 +0 1 +.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ +RESET_OUT_0_sqmuxa_7_3 +11 1 +.names CLK_030_H_i.BLIF N_73.BLIF N_94 +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 +11 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_85 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_87_1 +11 1 +.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_84 +11 1 +.names RW_000_c.BLIF nEXP_SPACE_D0_i.BLIF N_87_2 +11 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_83 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_1_n +11 1 +.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \ +pos_clk_un9_clk_000_n_sync_n +11 1 +.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_104_i.BLIF \ +pos_clk_un24_bgack_030_int_i_0_0_2_n +11 1 +.names sm_amiga_i_i_7__n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_72_0_1 +11 1 +.names pos_clk_clk_000_n_sync_2_0__n.BLIF AS_030_000_SYNC_i.BLIF \ +pos_clk_un7_clk_000_d0_1_n +11 1 +.names N_211.BLIF RST_DLY_5_.BLIF N_213 +11 1 +.names FPU_SENSE_i.BLIF N_116.BLIF un21_fpu_cs_1 +11 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names N_209.BLIF RST_DLY_4_.BLIF N_211 +11 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_116_1 +11 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF N_116_2 +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +11 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF N_116_3 +11 1 +.names N_116_1.BLIF N_116_2.BLIF N_116_4 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 +11 1 +.names N_83_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 +11 1 +.names N_84_i.BLIF RW_000_i.BLIF N_245_0_1 +11 1 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 +11 1 +.names N_94_i.BLIF RST_c.BLIF N_247_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_248_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_249_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 +11 1 +.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n +11 1 +.names N_92_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n +11 1 +.names N_91_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_86 +11 1 +.names N_251.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_93 +11 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_87_1.BLIF N_87_2.BLIF N_87 +11 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2 01 1 10 1 11 0 @@ -1805,6 +1773,16 @@ sm_amiga_srsts_i_0_m2_1__un0_n 10 1 11 0 00 0 +.names CYCLE_DMA_1_.BLIF N_220.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 +01 1 +10 1 +11 0 +00 0 .names RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa_7.BLIF G_149 01 1 10 1 @@ -1840,7 +1818,7 @@ sm_amiga_srsts_i_0_m2_1__un0_n 10 1 11 0 00 0 -.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_ +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF G_135 01 1 10 1 11 0 @@ -1887,10 +1865,10 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_78.BLIF AMIGA_BUS_ENABLE_HIGH +.names N_80.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 -.names vcc_n_n.BLIF CIIN +.names un5_ciin.BLIF CIIN 1 1 0 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ @@ -1899,6 +1877,15 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 @@ -1947,13 +1934,22 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_0_.C @@ -1992,6 +1988,24 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 .names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D 1 1 0 0 @@ -2058,24 +2072,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C 1 1 0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 -0 0 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -2103,27 +2099,27 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C 1 1 0 0 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C 1 1 0 0 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 0 0 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 @@ -2157,18 +2153,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF inst_DTACK_D0.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -2184,12 +2168,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -2265,27 +2243,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names un4_size.BLIF SIZE_0_ 1 1 0 0 -.names RW.PIN.BLIF RW_c -1 1 -0 0 -.names FC_0_.BLIF fc_c_0__n -1 1 -0 0 -.names FC_1_.BLIF fc_c_1__n -1 1 -0 0 -.names A_23_.BLIF a_23__n -1 1 -0 0 -.names A_22_.BLIF a_22__n -1 1 -0 0 -.names A_21_.BLIF a_21__n -1 1 -0 0 -.names A_20_.BLIF a_20__n -1 1 -0 0 .names A_15_.BLIF a_15__n 1 1 0 0 @@ -2364,6 +2321,18 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names A_19_.BLIF a_c_19__n 1 1 0 0 +.names A_20_.BLIF a_c_20__n +1 1 +0 0 +.names A_21_.BLIF a_c_21__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 .names A_24_.BLIF a_c_24__n 1 1 0 0 @@ -2433,22 +2402,31 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names RST.BLIF RST_c 1 1 0 0 +.names RW.PIN.BLIF RW_c +1 1 +0 0 +.names FC_0_.BLIF fc_c_0__n +1 1 +0 0 +.names FC_1_.BLIF fc_c_1__n +1 1 +0 0 .names un3_as_030_i.BLIF AS_030.OE 1 1 0 0 -.names N_98.BLIF AS_000.OE +.names un1_as_000_i.BLIF AS_000.OE 1 1 0 0 -.names N_98.BLIF RW_000.OE +.names un1_as_000_i.BLIF RW_000.OE 1 1 0 0 .names un3_as_030_i.BLIF DS_030.OE 1 1 0 0 -.names N_98.BLIF UDS_000.OE +.names un1_as_000_i.BLIF UDS_000.OE 1 1 0 0 -.names N_98.BLIF LDS_000.OE +.names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 .names un1_as_030_i.BLIF SIZE_0_.OE @@ -2463,7 +2441,7 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names un22_berr.BLIF BERR.OE 1 1 0 0 -.names N_99.BLIF RW.OE +.names N_100.BLIF RW.OE 1 1 0 0 .names gnd_n_n.BLIF CLK_DIV_OUT.OE @@ -2472,7 +2450,7 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE 1 1 0 0 -.names un8_ciin.BLIF CIIN.OE +.names un8_ciin_i.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index b081faa..f2f4e82 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,39 +1,40 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE 68030_tk -#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ IPL_030_2_ A_25_ A_24_ \ -# IPL_2_ FC_1_ AS_030 AS_000 A_19_ RW_000 A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A0 A1 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E VPA \ -# VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -# AMIGA_BUS_ENABLE_HIGH CIIN +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ +# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 \ +# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI IPL_030_1_ \ +# CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E \ +# VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ #$ NODES 84 inst_BGACK_030_INTreg cpu_est_3_reg inst_VMA_INTreg inst_RESET_OUTreg \ -# N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ \ -# inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 \ -# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \ -# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \ -# inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 \ -# inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE \ +# cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \ +# inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC \ +# inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ \ +# SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT \ +# inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 \ +# inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE \ # CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ \ # inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \ # SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ \ # RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ \ # CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ \ # CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ \ -# CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ \ -# CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ \ -# CLK_000_N_SYNC_10_ inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA inst_CLK_030_H \ -# SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ BG_000DFFreg \ -# IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg +# CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ \ +# pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ \ +# CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ \ +# inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ \ +# SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ BG_000DFFreg IPL_030DFF_0_reg \ +# IPL_030DFF_1_reg IPL_030DFF_2_reg .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ -A_26_.BLIF A_25_.BLIF A_24_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ -IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF inst_RESET_OUTreg.BLIF N_165.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ +A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ +inst_BGACK_030_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \ +inst_RESET_OUTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \ +SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ inst_nEXP_SPACE_D0reg.BLIF inst_DS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF \ inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \ CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \ @@ -50,106 +51,102 @@ CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF \ CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF \ CLK_000_P_SYNC_8_.BLIF CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF \ CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF \ -CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF \ -CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \ -inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF inst_DS_000_ENABLE.BLIF \ -SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF IPL_030DFF_0_reg.BLIF \ -IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ -SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +pos_clk_un29_clk_000_ne_d0_i_n.BLIF CLK_000_N_SYNC_5_.BLIF \ +CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \ +CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \ +inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_i_7_.BLIF \ +BG_000DFFreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \ +IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \ VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \ -SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D \ SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ cpu_est_3_reg.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \ -IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ -IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D \ -RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.C \ -RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ -CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ -CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ -CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ -CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ -CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ -CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ -CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ -CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.D \ -CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C \ -CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ -CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +IPL_030DFF_1_reg.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \ +CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \ +CLK_000_N_SYNC_11_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ +RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C \ +RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ +CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ +CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ +CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \ +CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \ +CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.C inst_RESET_OUTreg.D \ +inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ +inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \ inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUTreg.D inst_RESET_OUTreg.C \ -inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C BG_000DFFreg.D BG_000DFFreg.C \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \ -inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \ -inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ -inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \ -UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_165 AS_030.OE AS_000.OE RW_000.OE \ -DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ -CLK_DIV_OUT.OE DSACK1.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \ -SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 RST_DLY_4_.D.X1 RST_DLY_4_.D.X2 \ -RST_DLY_5_.D.X1 RST_DLY_5_.D.X2 RST_DLY_6_.D.X1 RST_DLY_6_.D.X2 \ -inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 +inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D \ +inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C \ +SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ \ +pos_clk_un29_clk_000_ne_d0_i_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE \ +UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \ +DSACK1.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 SM_AMIGA_3_.D.X1 \ +SM_AMIGA_3_.D.X2 RST_DLY_4_.D.X1 RST_DLY_4_.D.X2 RST_DLY_5_.D.X1 \ +RST_DLY_5_.D.X2 RST_DLY_6_.D.X1 RST_DLY_6_.D.X2 inst_CLK_030_H.D.X1 \ +inst_CLK_030_H.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 +.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ +IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D +1-00001- 1 +1-01101- 1 +1-10011- 1 +1-11111- 1 +1------1 1 +------11 1 +--1--0-1 1 +--0--1-1 1 +---10--1 1 +---01--1 1 +-0------ 1 +0100000- 0 +0101100- 0 +0110010- 0 +0111110- 0 +-11--0-0 0 +-10--1-0 0 +-1-10--0 0 +-1-01--0 0 +-1----00 0 +01-----0 0 +.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D +0- 1 +-1 1 +10 0 +.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D +0- 1 +-1 1 +10 0 .names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D 1- 1 -0 1 01 0 -.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF N_165.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF SM_AMIGA_5_.BLIF inst_VPA_D.BLIF \ -inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF cpu_est_2_.BLIF \ -SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \ -SM_AMIGA_i_7_.D -11000000---1-100000- 1 -110000-0--11-100-00- 1 -11000000-1-1-10-0--- 1 -110000-0-111-10----- 1 -1--0--010----100000- 1 -1--0---10-1--100-00- 1 -1--0--0-----0-00000- 1 -1--0--0101---10-0--- 1 -1--0------1-0-00-00- 1 -1--0---1011--10----- 1 -1--0--0--1--0-0-0--- 1 -1--0-----11-0-0----- 1 -1--0-----0---------1 1 -1--0----------0----1 1 --------11---1------0 0 ----------1----1----- 0 --------0---01------0 0 ------1-0----1------0 0 -----1--0----1------0 0 ---1----0----1------0 0 --0-----0----1------0 0 -----------0-----1--0 0 -------1---0--------0 0 ----------0--------10 0 ----------0-------1-0 0 ----------0-----1---0 0 -------------10-----0 0 ----1---------------- 0 -0------------------- 0 ---------------1----0 0 .names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \ SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D @@ -291,37 +288,6 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D -1-01--0 0 -1---0-0 0 -10----0 0 -.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ -IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D -1-00001- 1 -1-01101- 1 -1-10011- 1 -1-11111- 1 -1------1 1 -------11 1 ---1--0-1 1 ---0--1-1 1 ----10--1 1 ----01--1 1 --0------ 1 -0100000- 0 -0101100- 0 -0110010- 0 -0111110- 0 --11--0-0 0 --10--1-0 0 --1-10--0 0 --1-01--0 0 --1----00 0 -01-----0 0 -.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D -0- 1 --1 1 -10 0 -.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D -0- 1 --1 1 -10 0 .names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \ RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_0_.D @@ -444,6 +410,51 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D 01 1 1- 0 -0 0 +.names RST.BLIF inst_RESET_OUTreg.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF \ +RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF inst_RESET_OUTreg.D +1-111111111 1 +11--------- 1 +0---------- 0 +-0-------0- 0 +-0------0-- 0 +-0-----0--- 0 +-0----0---- 0 +-0---0----- 0 +-0--0------ 0 +-0-0------- 0 +-00-------- 0 +-0--------0 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF SM_AMIGA_3_.BLIF \ +inst_DS_000_ENABLE.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D +1-0-11- 1 +10-1--- 1 +11----1 1 +-0-0-0- 0 +-0-00-- 0 +-010--- 0 +-1---00 0 +-1--0-0 0 +-11---0 0 +0------ 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1-1- 1 +-10-- 1 +0---- 1 +-0--1 1 +1110- 0 +10--0 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \ +inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D +-0--1-- 1 +-011--- 1 +-0---0- 1 +0------ 1 +-1----1 1 +10-001- 0 +100-01- 0 +11----0 0 .names RST.BLIF inst_DS_030_D0.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF \ SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D -0-1100 1 @@ -455,6 +466,14 @@ SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D 10-1--1 0 1-00--- 0 110---- 0 +.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \ +AS_000.PIN.BLIF inst_BGACK_030_INTreg.D +1-1-- 1 +1--11 1 +-0--- 1 +-100- 0 +-10-0 0 +01--- 0 .names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \ inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ @@ -574,40 +593,6 @@ inst_DS_000_DMA.D 1- 1 -0 1 01 0 -.names RST.BLIF inst_RESET_OUTreg.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF \ -RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF inst_RESET_OUTreg.D -1-111111111 1 -11--------- 1 -0---------- 0 --0-------0- 0 --0------0-- 0 --0-----0--- 0 --0----0---- 0 --0---0----- 0 --0--0------ 0 --0-0------- 0 --00-------- 0 --0--------0 0 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF SM_AMIGA_3_.BLIF \ -inst_DS_000_ENABLE.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D -1-0-11- 1 -10-1--- 1 -11----1 1 --0-0-0- 0 --0-00-- 0 --010--- 0 --1---00 0 --1--0-0 0 --11---0 0 -0------ 0 -.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \ -inst_BGACK_030_INTreg.D -1-1- 1 --0-- 1 -1--1 1 --100 0 -01-- 0 .names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \ inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D ----01 1 @@ -638,12 +623,12 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.D cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ cpu_est_2_.BLIF inst_VMA_INTreg.D -0-01-1-1 1 -0-------- 1 --1----0- 1 --1--1--- 1 --11------ 1 ---1-1---- 1 --10----- 1 +--1-1---- 1 +0-------- 1 +-11------ 1 --1-----0 1 10-100-11 0 1-0---0-- 0 @@ -660,24 +645,6 @@ A0.PIN.BLIF inst_UDS_000_INT.D 10-10 0 1-00- 0 110-- 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1-1- 1 --10-- 1 -0---- 1 --0--1 1 -1110- 0 -10--0 0 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \ -inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D --0--1-- 1 --011--- 1 --0---0- 1 -0------ 1 --1----1 1 -10-001- 0 -100-01- 0 -11----0 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -685,21 +652,18 @@ inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 1 0 -.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF N_165 -0---1000000 1 -0--0-000000 1 -0-1--000000 1 -00---000000 1 --1010------ 0 ----------1- 0 ---------1-- 0 --------1--- 0 -------1---- 0 ------1----- 0 -1---------- 0 -----------1 0 +.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ +inst_VPA_D.BLIF inst_DTACK_D0.BLIF cpu_est_2_.BLIF inst_CLK_000_NE_D0.BLIF \ +pos_clk_un29_clk_000_ne_d0_i_n +----0-0- 1 +----11-- 1 +---10--- 1 +--1-0--- 1 +-1--0--- 1 +0---0--- 1 +-------0 1 +10000-11 0 +----10-1 0 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -761,14 +725,38 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH 1-0 1 00- 0 1-1 0 -.names CIIN - 1 +.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ +A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +inst_AS_030_D0.BLIF CIIN +0000000011110 1 +-----------0- 0 +----------0-- 0 +---------0--- 0 +--------0---- 0 +-------1----- 0 +------1------ 0 +-----1------- 0 +----1-------- 0 +---1--------- 0 +--1---------- 0 +-1----------- 0 +1------------ 0 +------------1 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ 1 1 0 0 .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF IPL_D0_1_.C +1 1 +0 0 .names CLK_OSZI.BLIF IPL_D0_2_.C 1 1 0 0 @@ -819,13 +807,22 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH .names CLK_OSZI.BLIF IPL_030DFF_1_reg.C 1 1 0 0 -.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D 1 1 0 0 -.names CLK_OSZI.BLIF IPL_D0_0_.C +.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C 1 1 0 0 -.names CLK_OSZI.BLIF IPL_D0_1_.C +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C 1 1 0 0 .names CLK_OSZI.BLIF RST_DLY_0_.C @@ -864,6 +861,24 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH .names CLK_OSZI.BLIF SIZE_DMA_1_.C 1 1 0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 .names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D 1 1 0 0 @@ -931,24 +946,6 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH .names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C 1 1 0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C -1 1 -0 0 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C -1 1 -0 0 .names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -976,27 +973,27 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH .names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C 1 1 0 0 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +.names CLK_OSZI.BLIF inst_CLK_030_H.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C +.names CLK_OSZI.BLIF inst_RESET_OUTreg.C 1 1 0 0 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C +.names CLK_OSZI.BLIF inst_RW_000_DMA.C 1 1 0 0 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C +.names CLK_OSZI.BLIF inst_RW_000_INT.C 1 1 0 0 .names CLK_OSZI.BLIF inst_LDS_000_INT.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 .names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 @@ -1030,18 +1027,6 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH .names CLK_OSZI.BLIF inst_DTACK_D0.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_CLK_030_H.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_RESET_OUTreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 .names CLK_OSZI.BLIF BG_000DFFreg.C 1 1 0 0 @@ -1057,12 +1042,6 @@ SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH .names CLK_OSZI.BLIF inst_UDS_000_INT.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_RW_000_DMA.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_RW_000_INT.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -1210,18 +1189,23 @@ A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE 1 1 0 0 .names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ -A_25_.BLIF A_24_.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE -0000000001 1 ---------1- 0 --------1-- 0 -------1--- 0 ------1---- 0 -----1----- 0 ----1------ 0 ---1------- 0 --1-------- 0 -1--------- 0 ----------0 0 +A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ +inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE +0000000011110- 1 +-------------1 1 +------------10 0 +-----------0-0 0 +----------0--0 0 +---------0---0 0 +--------0----0 0 +-------1-----0 0 +------1------0 0 +-----1-------0 0 +----1--------0 0 +---1---------0 0 +--1----------0 0 +-1-----------0 0 +1------------0 0 .names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ inst_CLK_000_NE_D0.BLIF cpu_est_3_reg.D.X1 11111 1 @@ -1352,4 +1336,48 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2 0--010-00- 0 0--001-0-0 0 0--010-0-0 0 +.names RST.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_i_7_.D.X1 +10 1 +0- 0 +-1 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_6_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X2 +100-----000-000- 1 +10-1----000-000- 1 +10--0---000-000- 1 +10---1--000-000- 1 +1-----0--0----10 1 +1-----0--0---1-0 1 +1------0-0--1--0 1 +1-----0--01----0 1 +1-------10-1---0 1 +11-----0-0-----0 1 +1-----0--1-----1 1 +0--------------- 0 +------1--1------ 0 +---------1-----0 0 +-1-------0-----1 0 +--------10-----1 0 +---------01----1 0 +---------0--1--1 0 +---------0---1-1 0 +---------0----11 0 +-1----110------- 0 +------110-1----- 0 +-1----11---0---- 0 +------111--0---- 0 +------110---1--- 0 +-0----1-0-1-0--- 0 +-0----1-1--00--- 0 +-0----1-0---01-- 0 +-0----1-0---0-1- 0 +-1-----1000--00- 0 +-1-----1-000-00- 0 +-------11000-00- 0 +-------1000-100- 0 +-0------1000000- 0 +-01010--000-000- 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 71c2ab3..c77b7bd 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.8.00.04.29.14 -// Design '68030_tk' created Thu Jul 09 18:48:59 2015 +// Design '68030_tk' created Thu Sep 24 16:20:59 2015 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 62245f1..4d428b6 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,13 +2,11 @@ Copyright(C), 1992-2014, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Thu Jul 09 18:48:59 2015 +Design bus68030 created Thu Sep 24 16:20:59 2015 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- - 1 2 1 Pin SIZE_0_ - 1 2 1 Pin SIZE_0_.OE 1 2 1 Pin SIZE_1_ 1 2 1 Pin SIZE_1_.OE 1 2 1 Pin AS_030- @@ -32,8 +30,10 @@ Design bus68030 created Thu Jul 09 18:48:59 2015 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH - 1 0 1 Pin CIIN - 1 10 1 Pin CIIN.OE + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_ + 1 2 1 Pin SIZE_0_.OE 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -44,7 +44,7 @@ Design bus68030 created Thu Jul 09 18:48:59 2015 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C - 2 4 1 Pin BGACK_030.D- + 3 5 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C 10 8 1 Pin IPL_030_1_.D- 1 1 1 Pin IPL_030_1_.C @@ -62,7 +62,6 @@ Design bus68030 created Thu Jul 09 18:48:59 2015 1 2 1 Pin RW.OE 2 5 1 Pin RW.D- 1 1 1 Pin RW.C - 4 11 1 Node N_165 2 2 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 5 5 1 Node cpu_est_1_.D- @@ -182,6 +181,7 @@ Design bus68030 created Thu Jul 09 18:48:59 2015 1 1 1 Node CLK_000_N_SYNC_3_.C 1 1 1 Node CLK_000_N_SYNC_4_.D 1 1 1 Node CLK_000_N_SYNC_4_.C + 2 8 1 Node pos_clk_un29_clk_000_ne_d0_i_n- 1 1 1 Node CLK_000_N_SYNC_5_.D 1 1 1 Node CLK_000_N_SYNC_5_.C 1 1 1 Node CLK_000_N_SYNC_6_.D @@ -204,21 +204,18 @@ Design bus68030 created Thu Jul 09 18:48:59 2015 1 1 1 Node SM_AMIGA_2_.C 3 7 1 Node inst_DS_000_ENABLE.D 1 1 1 Node inst_DS_000_ENABLE.C - 14 20 1 Node SM_AMIGA_i_7_.D + 13 16 1 Node SM_AMIGA_i_7_.D- 1 1 1 Node SM_AMIGA_i_7_.C + 2 14 1 Node CIIN_0 ========= 346 P-Term Total: 346 - Total Pins: 57 - Total Nodes: 72 + Total Pins: 61 + Total Nodes: 73 Average P-Term/Output: 2 Equations: -SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); - -SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); - SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); @@ -267,9 +264,13 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q # BGACK_030.Q & !SM_AMIGA_i_7_.Q); -CIIN = (1); +CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); -CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q); +CIIN.OE = (CIIN_0); + +SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q @@ -305,8 +306,9 @@ A0.C = (CLK_OSZI); BG_000.C = (CLK_OSZI); -!BGACK_030.D = (!BGACK_000 & RST - # RST & !BGACK_030.Q & !inst_CLK_000_PE.Q); +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN); BGACK_030.C = (CLK_OSZI); @@ -371,11 +373,6 @@ RW.OE = (!BGACK_030.Q & RESET.Q); RW.C = (CLK_OSZI); -N_165 = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); - cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); @@ -687,6 +684,9 @@ CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); CLK_000_N_SYNC_4_.C = (CLK_OSZI); +!pos_clk_un29_clk_000_ne_d0_i_n = (inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); CLK_000_N_SYNC_5_.C = (CLK_OSZI); @@ -747,23 +747,25 @@ inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q inst_DS_000_ENABLE.C = (CLK_OSZI); -SM_AMIGA_i_7_.D = (RST & !N_165 & !inst_CLK_000_PE.Q & BERR.PIN - # RST & !N_165 & !SM_AMIGA_0_.Q & BERR.PIN - # RST & !N_165 & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & !N_165 & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); +!SM_AMIGA_i_7_.D = (!RST + # inst_CLK_000_PE.Q & SM_AMIGA_0_.Q + # SM_AMIGA_0_.Q & !BERR.PIN + # SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !BERR.PIN + # SM_AMIGA_3_.Q & pos_clk_un29_clk_000_ne_d0_i_n & !BERR.PIN + # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & !BERR.PIN + # !SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); +CIIN_0 = (inst_nEXP_SPACE_D0reg.Q + # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + Reverse-Polarity Equations: diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index d30c4e7..924571b 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -16,6 +16,10 @@ DATA LOCATION A_16_:A_*_96 // INP DATA LOCATION A_17_:F_*_59 // INP DATA LOCATION A_18_:A_*_95 // INP DATA LOCATION A_19_:A_*_97 // INP +DATA LOCATION A_20_:A_*_93 // INP +DATA LOCATION A_21_:A_*_94 // INP +DATA LOCATION A_22_:H_*_84 // INP +DATA LOCATION A_23_:H_*_85 // INP DATA LOCATION A_24_:C_*_19 // INP DATA LOCATION A_25_:C_*_18 // INP DATA LOCATION A_26_:C_*_17 // INP @@ -30,35 +34,36 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT +DATA LOCATION CIIN_0:E_5 // NOD DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_N_SYNC_0_:D_7 // NOD +DATA LOCATION CLK_000_N_SYNC_0_:F_6 // NOD DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD -DATA LOCATION CLK_000_N_SYNC_1_:A_15 // NOD -DATA LOCATION CLK_000_N_SYNC_2_:A_11 // NOD -DATA LOCATION CLK_000_N_SYNC_3_:A_7 // NOD -DATA LOCATION CLK_000_N_SYNC_4_:D_3 // NOD -DATA LOCATION CLK_000_N_SYNC_5_:A_3 // NOD -DATA LOCATION CLK_000_N_SYNC_6_:D_14 // NOD -DATA LOCATION CLK_000_N_SYNC_7_:E_8 // NOD -DATA LOCATION CLK_000_N_SYNC_8_:A_14 // NOD -DATA LOCATION CLK_000_N_SYNC_9_:G_3 // NOD -DATA LOCATION CLK_000_P_SYNC_0_:D_11 // NOD -DATA LOCATION CLK_000_P_SYNC_1_:G_11 // NOD -DATA LOCATION CLK_000_P_SYNC_2_:B_3 // NOD -DATA LOCATION CLK_000_P_SYNC_3_:C_9 // NOD -DATA LOCATION CLK_000_P_SYNC_4_:B_4 // NOD -DATA LOCATION CLK_000_P_SYNC_5_:E_9 // NOD -DATA LOCATION CLK_000_P_SYNC_6_:E_5 // NOD -DATA LOCATION CLK_000_P_SYNC_7_:G_7 // NOD -DATA LOCATION CLK_000_P_SYNC_8_:C_5 // NOD -DATA LOCATION CLK_000_P_SYNC_9_:C_2 // NOD +DATA LOCATION CLK_000_N_SYNC_1_:G_7 // NOD +DATA LOCATION CLK_000_N_SYNC_2_:G_3 // NOD +DATA LOCATION CLK_000_N_SYNC_3_:B_7 // NOD +DATA LOCATION CLK_000_N_SYNC_4_:B_3 // NOD +DATA LOCATION CLK_000_N_SYNC_5_:B_14 // NOD +DATA LOCATION CLK_000_N_SYNC_6_:A_6 // NOD +DATA LOCATION CLK_000_N_SYNC_7_:B_10 // NOD +DATA LOCATION CLK_000_N_SYNC_8_:G_14 // NOD +DATA LOCATION CLK_000_N_SYNC_9_:F_2 // NOD +DATA LOCATION CLK_000_P_SYNC_0_:D_10 // NOD +DATA LOCATION CLK_000_P_SYNC_1_:C_11 // NOD +DATA LOCATION CLK_000_P_SYNC_2_:B_11 // NOD +DATA LOCATION CLK_000_P_SYNC_3_:C_7 // NOD +DATA LOCATION CLK_000_P_SYNC_4_:D_6 // NOD +DATA LOCATION CLK_000_P_SYNC_5_:F_10 // NOD +DATA LOCATION CLK_000_P_SYNC_6_:A_3 // NOD +DATA LOCATION CLK_000_P_SYNC_7_:A_14 // NOD +DATA LOCATION CLK_000_P_SYNC_8_:A_10 // NOD +DATA LOCATION CLK_000_P_SYNC_9_:A_7 // NOD DATA LOCATION CLK_030:*_*_64 // INP DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CYCLE_DMA_0_:A_10 // NOD -DATA LOCATION CYCLE_DMA_1_:A_6 // NOD +DATA LOCATION CYCLE_DMA_0_:A_2 // NOD +DATA LOCATION CYCLE_DMA_1_:A_13 // NOD DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1} DATA LOCATION DS_030:A_0_98 // IO DATA LOCATION DTACK:D_*_30 // INP @@ -68,38 +73,37 @@ DATA LOCATION FC_1_:F_*_58 // INP DATA LOCATION FPU_CS:H_1_78 // OUT DATA LOCATION FPU_SENSE:A_*_91 // INP DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_} -DATA LOCATION IPL_030_1_:B_6_7 // IO {RN_IPL_030_1_} -DATA LOCATION IPL_030_2_:B_2_9 // IO {RN_IPL_030_2_} +DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_} +DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:B_7 // NOD -DATA LOCATION IPL_D0_1_:C_13 // NOD -DATA LOCATION IPL_D0_2_:B_13 // NOD +DATA LOCATION IPL_D0_0_:D_3 // NOD +DATA LOCATION IPL_D0_1_:D_14 // NOD +DATA LOCATION IPL_D0_2_:G_11 // NOD DATA LOCATION LDS_000:D_12_31 // IO -DATA LOCATION N_165:F_6 // NOD -DATA LOCATION RESET:B_14_3 // IO {RN_RESET} +DATA LOCATION RESET:B_0_3 // IO {RN_RESET} DATA LOCATION RN_A0:G_8 // NOD {A0} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1} DATA LOCATION RN_E:G_4 // NOD {E} DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} -DATA LOCATION RN_IPL_030_1_:B_6 // NOD {IPL_030_1_} -DATA LOCATION RN_IPL_030_2_:B_2 // NOD {IPL_030_2_} -DATA LOCATION RN_RESET:B_14 // NOD {RESET} +DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} +DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} +DATA LOCATION RN_RESET:B_0 // NOD {RESET} DATA LOCATION RN_RW:G_0 // NOD {RW} DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} DATA LOCATION RN_VMA:D_0 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RST_DLY_0_:B_10 // NOD -DATA LOCATION RST_DLY_1_:A_1 // NOD +DATA LOCATION RST_DLY_0_:C_6 // NOD +DATA LOCATION RST_DLY_1_:B_13 // NOD DATA LOCATION RST_DLY_2_:B_5 // NOD -DATA LOCATION RST_DLY_3_:B_0 // NOD -DATA LOCATION RST_DLY_4_:B_12 // NOD -DATA LOCATION RST_DLY_5_:A_12 // NOD -DATA LOCATION RST_DLY_6_:B_11 // NOD -DATA LOCATION RST_DLY_7_:A_5 // NOD +DATA LOCATION RST_DLY_3_:C_9 // NOD +DATA LOCATION RST_DLY_4_:C_14 // NOD +DATA LOCATION RST_DLY_5_:B_9 // NOD +DATA LOCATION RST_DLY_6_:C_2 // NOD +DATA LOCATION RST_DLY_7_:C_10 // NOD DATA LOCATION RW:G_0_71 // IO {RN_RW} DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} DATA LOCATION SIZE_0_:G_12_70 // IO @@ -107,43 +111,44 @@ DATA LOCATION SIZE_1_:H_12_79 // IO DATA LOCATION SIZE_DMA_0_:G_6 // NOD DATA LOCATION SIZE_DMA_1_:G_2 // NOD DATA LOCATION SM_AMIGA_0_:F_9 // NOD -DATA LOCATION SM_AMIGA_1_:F_1 // NOD -DATA LOCATION SM_AMIGA_2_:F_2 // NOD -DATA LOCATION SM_AMIGA_3_:F_12 // NOD -DATA LOCATION SM_AMIGA_4_:F_10 // NOD -DATA LOCATION SM_AMIGA_5_:F_4 // NOD -DATA LOCATION SM_AMIGA_6_:C_4 // NOD -DATA LOCATION SM_AMIGA_i_7_:F_0 // NOD +DATA LOCATION SM_AMIGA_1_:C_1 // NOD +DATA LOCATION SM_AMIGA_2_:C_13 // NOD +DATA LOCATION SM_AMIGA_3_:C_8 // NOD +DATA LOCATION SM_AMIGA_4_:F_1 // NOD +DATA LOCATION SM_AMIGA_5_:F_12 // NOD +DATA LOCATION SM_AMIGA_6_:F_5 // NOD +DATA LOCATION SM_AMIGA_i_7_:F_8 // NOD DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:D_6 // NOD -DATA LOCATION cpu_est_1_:D_13 // NOD -DATA LOCATION cpu_est_2_:D_2 // NOD +DATA LOCATION cpu_est_0_:C_5 // NOD +DATA LOCATION cpu_est_1_:G_5 // NOD +DATA LOCATION cpu_est_2_:C_12 // NOD DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:G_10 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:G_14 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_3 // NOD DATA LOCATION inst_AS_000_DMA:A_8 // NOD -DATA LOCATION inst_AS_000_INT:C_1 // NOD -DATA LOCATION inst_AS_030_000_SYNC:C_8 // NOD +DATA LOCATION inst_AS_000_INT:A_1 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_13 // NOD DATA LOCATION inst_AS_030_D0:H_5 // NOD DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD -DATA LOCATION inst_CLK_000_D0:G_13 // NOD -DATA LOCATION inst_CLK_000_D1:F_8 // NOD -DATA LOCATION inst_CLK_000_NE:G_9 // NOD -DATA LOCATION inst_CLK_000_NE_D0:B_15 // NOD -DATA LOCATION inst_CLK_000_PE:D_9 // NOD -DATA LOCATION inst_CLK_030_H:A_2 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:A_9 // NOD -DATA LOCATION inst_CLK_OUT_PRE_D:G_15 // NOD -DATA LOCATION inst_DS_000_DMA:A_13 // NOD -DATA LOCATION inst_DS_000_ENABLE:C_12 // NOD -DATA LOCATION inst_DS_030_D0:D_10 // NOD -DATA LOCATION inst_DTACK_D0:D_15 // NOD -DATA LOCATION inst_LDS_000_INT:B_9 // NOD -DATA LOCATION inst_UDS_000_INT:F_5 // NOD -DATA LOCATION inst_VPA_D:F_13 // NOD -DATA LOCATION inst_nEXP_SPACE_D0reg:G_5 // NOD +DATA LOCATION inst_CLK_000_D0:B_2 // NOD +DATA LOCATION inst_CLK_000_D1:D_9 // NOD +DATA LOCATION inst_CLK_000_NE:F_4 // NOD +DATA LOCATION inst_CLK_000_NE_D0:E_8 // NOD +DATA LOCATION inst_CLK_000_PE:C_4 // NOD +DATA LOCATION inst_CLK_030_H:A_9 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:E_9 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:E_13 // NOD +DATA LOCATION inst_DS_000_DMA:A_5 // NOD +DATA LOCATION inst_DS_000_ENABLE:A_12 // NOD +DATA LOCATION inst_DS_030_D0:D_7 // NOD +DATA LOCATION inst_DTACK_D0:B_6 // NOD +DATA LOCATION inst_LDS_000_INT:G_9 // NOD +DATA LOCATION inst_UDS_000_INT:G_13 // NOD +DATA LOCATION inst_VPA_D:D_13 // NOD +DATA LOCATION inst_nEXP_SPACE_D0reg:F_0 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP +DATA LOCATION pos_clk_un29_clk_000_ne_d0_i_n:D_2 // NOD DATA IO_DIR A0:BI DATA IO_DIR A1:IN DATA IO_DIR AMIGA_ADDR_ENABLE:OUT @@ -157,6 +162,10 @@ DATA IO_DIR A_16_:IN DATA IO_DIR A_17_:IN DATA IO_DIR A_18_:IN DATA IO_DIR A_19_:IN +DATA IO_DIR A_20_:IN +DATA IO_DIR A_21_:IN +DATA IO_DIR A_22_:IN +DATA IO_DIR A_23_:IN DATA IO_DIR A_24_:IN DATA IO_DIR A_25_:IN DATA IO_DIR A_26_:IN @@ -202,46 +211,48 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL SIZE_0_:1 -DATA SLEW SIZE_0_:1 -DATA PW_LEVEL A_30_:1 -DATA SLEW A_30_:1 -DATA PW_LEVEL SIZE_1_:1 -DATA SLEW SIZE_1_:1 -DATA PW_LEVEL A_29_:1 -DATA SLEW A_29_:1 DATA PW_LEVEL A_28_:1 DATA SLEW A_28_:1 -DATA PW_LEVEL A_31_:1 -DATA SLEW A_31_:1 DATA PW_LEVEL A_27_:1 DATA SLEW A_27_:1 +DATA PW_LEVEL SIZE_1_:1 +DATA SLEW SIZE_1_:1 DATA PW_LEVEL A_26_:1 DATA SLEW A_26_:1 DATA PW_LEVEL A_25_:1 DATA SLEW A_25_:1 +DATA PW_LEVEL A_31_:1 +DATA SLEW A_31_:1 DATA PW_LEVEL A_24_:1 DATA SLEW A_24_:1 +DATA PW_LEVEL A_23_:1 +DATA SLEW A_23_:1 +DATA PW_LEVEL A_22_:1 +DATA SLEW A_22_:1 +DATA PW_LEVEL A_21_:1 +DATA SLEW A_21_:1 DATA PW_LEVEL IPL_2_:1 DATA SLEW IPL_2_:1 -DATA PW_LEVEL FC_1_:1 -DATA SLEW FC_1_:1 -DATA PW_LEVEL AS_030:1 -DATA SLEW AS_030:1 -DATA PW_LEVEL AS_000:1 -DATA SLEW AS_000:1 +DATA PW_LEVEL A_20_:1 +DATA SLEW A_20_:1 DATA PW_LEVEL A_19_:1 DATA SLEW A_19_:1 +DATA PW_LEVEL FC_1_:1 +DATA SLEW FC_1_:1 DATA PW_LEVEL A_18_:1 DATA SLEW A_18_:1 -DATA PW_LEVEL DS_030:1 -DATA SLEW DS_030:1 +DATA PW_LEVEL AS_030:1 +DATA SLEW AS_030:1 DATA PW_LEVEL A_17_:1 DATA SLEW A_17_:1 -DATA PW_LEVEL UDS_000:1 -DATA SLEW UDS_000:1 +DATA PW_LEVEL AS_000:1 +DATA SLEW AS_000:1 DATA PW_LEVEL A_16_:1 DATA SLEW A_16_:1 +DATA PW_LEVEL DS_030:1 +DATA SLEW DS_030:1 +DATA PW_LEVEL UDS_000:1 +DATA SLEW UDS_000:1 DATA PW_LEVEL LDS_000:1 DATA SLEW LDS_000:1 DATA PW_LEVEL A1:1 @@ -260,20 +271,20 @@ DATA PW_LEVEL CLK_DIV_OUT:1 DATA SLEW CLK_DIV_OUT:0 DATA PW_LEVEL CLK_EXP:1 DATA SLEW CLK_EXP:0 -DATA PW_LEVEL FPU_CS:1 -DATA SLEW FPU_CS:0 -DATA PW_LEVEL FPU_SENSE:1 -DATA SLEW FPU_SENSE:1 DATA PW_LEVEL IPL_1_:1 DATA SLEW IPL_1_:1 -DATA PW_LEVEL DTACK:1 -DATA SLEW DTACK:1 +DATA PW_LEVEL FPU_CS:1 +DATA SLEW FPU_CS:0 DATA PW_LEVEL IPL_0_:1 DATA SLEW IPL_0_:1 -DATA PW_LEVEL AVEC:1 -DATA SLEW AVEC:1 +DATA PW_LEVEL FPU_SENSE:1 +DATA SLEW FPU_SENSE:1 DATA PW_LEVEL FC_0_:1 DATA SLEW FC_0_:1 +DATA PW_LEVEL DTACK:1 +DATA SLEW DTACK:1 +DATA PW_LEVEL AVEC:1 +DATA SLEW AVEC:1 DATA SLEW VPA:1 DATA SLEW RST:1 DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 @@ -286,6 +297,12 @@ DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 DATA PW_LEVEL CIIN:1 DATA SLEW CIIN:1 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:1 +DATA PW_LEVEL A_30_:1 +DATA SLEW A_30_:1 +DATA PW_LEVEL A_29_:1 +DATA SLEW A_29_:1 DATA PW_LEVEL IPL_030_2_:1 DATA SLEW IPL_030_2_:1 DATA PW_LEVEL RW_000:1 @@ -310,8 +327,6 @@ DATA PW_LEVEL RESET:1 DATA SLEW RESET:1 DATA PW_LEVEL RW:1 DATA SLEW RW:1 -DATA PW_LEVEL N_165:1 -DATA SLEW N_165:1 DATA PW_LEVEL cpu_est_0_:1 DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:1 @@ -430,6 +445,8 @@ DATA PW_LEVEL CLK_000_N_SYNC_3_:1 DATA SLEW CLK_000_N_SYNC_3_:1 DATA PW_LEVEL CLK_000_N_SYNC_4_:1 DATA SLEW CLK_000_N_SYNC_4_:1 +DATA PW_LEVEL pos_clk_un29_clk_000_ne_d0_i_n:1 +DATA SLEW pos_clk_un29_clk_000_ne_d0_i_n:1 DATA PW_LEVEL CLK_000_N_SYNC_5_:1 DATA SLEW CLK_000_N_SYNC_5_:1 DATA PW_LEVEL CLK_000_N_SYNC_6_:1 @@ -454,6 +471,8 @@ DATA PW_LEVEL inst_DS_000_ENABLE:1 DATA SLEW inst_DS_000_ENABLE:1 DATA PW_LEVEL SM_AMIGA_i_7_:1 DATA SLEW SM_AMIGA_i_7_:1 +DATA PW_LEVEL CIIN_0:1 +DATA SLEW CIIN_0:1 DATA PW_LEVEL RN_IPL_030_2_:1 DATA PW_LEVEL RN_RW_000:1 DATA PW_LEVEL RN_A0:1 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 7068f67..51efa5a 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,28 +1,29 @@ -GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H RST_DLY_1_ RST_DLY_5_ RST_DLY_7_ - inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ - CLK_000_N_SYNC_3_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_8_ inst_CLK_OUT_PRE_50 - DS_030 AVEC -GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ - IPL_030_2_ RN_IPL_030_2_ RST_DLY_3_ RST_DLY_0_ RST_DLY_2_ RST_DLY_4_ - RST_DLY_6_ inst_LDS_000_INT IPL_D0_0_ IPL_D0_2_ CLK_000_P_SYNC_2_ - CLK_000_P_SYNC_4_ inst_CLK_000_NE_D0 CLK_EXP -GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_DS_000_ENABLE inst_AS_000_INT - IPL_D0_1_ CLK_000_P_SYNC_9_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_8_ AMIGA_BUS_ENABLE_LOW +GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_DS_000_ENABLE + CYCLE_DMA_1_ inst_AS_000_INT CYCLE_DMA_0_ CLK_000_P_SYNC_9_ CLK_000_P_SYNC_6_ + CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_6_ DS_030 AVEC -GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 cpu_est_1_ cpu_est_2_ cpu_est_0_ - CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ inst_DTACK_D0 inst_DS_030_D0 - inst_CLK_000_PE CLK_000_N_SYNC_4_ CLK_000_N_SYNC_6_ LDS_000 UDS_000 - AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE -GROUP MACH_SEG_E CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_N_SYNC_7_ - CIIN BERR AMIGA_BUS_DATA_DIR AS_000 -GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_1_ - SM_AMIGA_4_ SM_AMIGA_5_ inst_UDS_000_INT inst_VPA_D inst_CLK_000_D1 - N_165 -GROUP MACH_SEG_G A0 RN_A0 RW RN_RW E RN_E SIZE_DMA_0_ SIZE_DMA_1_ inst_AMIGA_BUS_ENABLE_DMA_LOW - inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_nEXP_SPACE_D0reg inst_CLK_000_D0 - inst_CLK_000_NE CLK_000_P_SYNC_1_ CLK_000_P_SYNC_7_ CLK_000_N_SYNC_9_ - inst_CLK_OUT_PRE_D SIZE_0_ CLK_DIV_OUT +GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ + IPL_030_2_ RN_IPL_030_2_ RST_DLY_1_ RST_DLY_2_ RST_DLY_5_ inst_DTACK_D0 + inst_CLK_000_D0 CLK_000_P_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ + CLK_000_N_SYNC_5_ CLK_000_N_SYNC_7_ CLK_EXP +GROUP MACH_SEG_C SM_AMIGA_3_ SM_AMIGA_2_ RST_DLY_3_ RST_DLY_0_ RST_DLY_4_ + RST_DLY_6_ RST_DLY_7_ SM_AMIGA_1_ cpu_est_2_ inst_AMIGA_BUS_ENABLE_DMA_LOW + cpu_est_0_ inst_CLK_000_PE CLK_000_P_SYNC_1_ CLK_000_P_SYNC_3_ AMIGA_BUS_ENABLE_LOW + +GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 CLK_000_P_SYNC_0_ inst_VPA_D + inst_DS_030_D0 IPL_D0_0_ IPL_D0_1_ CLK_000_P_SYNC_4_ inst_CLK_000_D1 + LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE pos_clk_un29_clk_000_ne_d0_i_n + +GROUP MACH_SEG_E inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 inst_CLK_000_NE_D0 + CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 +GROUP MACH_SEG_F SM_AMIGA_i_7_ inst_AS_030_000_SYNC SM_AMIGA_6_ SM_AMIGA_0_ + SM_AMIGA_4_ SM_AMIGA_5_ CLK_000_N_SYNC_0_ inst_nEXP_SPACE_D0reg inst_CLK_000_NE + CLK_000_P_SYNC_5_ CLK_000_N_SYNC_9_ +GROUP MACH_SEG_G A0 RN_A0 RW RN_RW E RN_E inst_LDS_000_INT SIZE_DMA_0_ + SIZE_DMA_1_ cpu_est_1_ inst_UDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH + IPL_D0_2_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_8_ SIZE_0_ + CLK_DIV_OUT GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_ FPU_CS AS_030 SIZE_1_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 22ec451..bc30fde 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -9273210z*5A(L3- \ No newline at end of file +9467445Fv,kS- \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 6058fb3..ef54cea 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Thu Jul 09 18:49:07 2015 +DATE: Thu Sep 24 16:17:03 2015 ABEL mach447a * @@ -33,467 +33,468 @@ NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* NOTE PINS SIZE_0_:70 A_30_:5 SIZE_1_:79 A_29_:6 A_28_:15* NOTE PINS A_31_:4 A_27_:16 A_26_:17 A_25_:18 A_24_:19 IPL_2_:68* -NOTE PINS FC_1_:58 AS_030:82 AS_000:42 A_19_:97 A_18_:95* -NOTE PINS DS_030:98 A_17_:59 UDS_000:32 A_16_:96 LDS_000:31* -NOTE PINS A1:60 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28* -NOTE PINS CLK_030:64 CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65* -NOTE PINS CLK_EXP:10 FPU_CS:78 FPU_SENSE:91 IPL_1_:56 DTACK:30* -NOTE PINS IPL_0_:67 AVEC:92 FC_0_:57 VPA:36 RST:86 AMIGA_ADDR_ENABLE:33* -NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS A_23_:85 A_22_:84 FC_1_:58 A_21_:94 AS_030:82 A_20_:93* +NOTE PINS AS_000:42 A_19_:97 A_18_:95 DS_030:98 A_17_:59* +NOTE PINS UDS_000:32 A_16_:96 LDS_000:31 A1:60 nEXP_SPACE:14* +NOTE PINS BERR:41 BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11* +NOTE PINS CLK_OSZI:61 CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91* +NOTE PINS IPL_1_:56 DTACK:30 IPL_0_:67 AVEC:92 FC_0_:57 VPA:36* +NOTE PINS RST:86 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* NOTE PINS CIIN:47 IPL_030_2_:9 RW_000:80 A0:69 BG_000:29* -NOTE PINS BGACK_030:83 IPL_030_1_:7 IPL_030_0_:8 DSACK1:81* -NOTE PINS E:66 VMA:35 RESET:3 RW:71 * +NOTE PINS BGACK_030:83 CLK_EXP:10 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS DSACK1:81 E:66 VMA:35 RESET:3 RW:71 * NOTE Table of node names and numbers* NOTE NODES RN_SIZE_0_:263 RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 * NOTE NODES RN_DS_030:101 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * -NOTE NODES RN_IPL_030_2_:128 RN_RW_000:269 RN_A0:257 RN_BG_000:175 * -NOTE NODES RN_BGACK_030:275 RN_IPL_030_1_:134 RN_IPL_030_0_:137 * -NOTE NODES RN_DSACK1:283 RN_E:251 RN_VMA:173 RN_RESET:146 * -NOTE NODES RN_RW:245 N_165:230 cpu_est_0_:182 cpu_est_1_:193 * -NOTE NODES inst_AS_000_INT:151 SM_AMIGA_5_:227 inst_AMIGA_BUS_ENABLE_DMA_LOW:266 * -NOTE NODES inst_AS_030_D0:277 inst_nEXP_SPACE_D0reg:253 * -NOTE NODES inst_DS_030_D0:188 inst_AS_030_000_SYNC:161 inst_BGACK_030_INT_D:289 * -NOTE NODES inst_AS_000_DMA:113 inst_DS_000_DMA:121 CYCLE_DMA_0_:116 * -NOTE NODES CYCLE_DMA_1_:110 SIZE_DMA_0_:254 SIZE_DMA_1_:248 * -NOTE NODES inst_VPA_D:241 inst_UDS_000_INT:229 inst_LDS_000_INT:139 * -NOTE NODES inst_CLK_OUT_PRE_D:268 inst_DTACK_D0:196 inst_CLK_OUT_PRE_50:115 * -NOTE NODES inst_CLK_000_D1:233 inst_CLK_000_D0:265 inst_CLK_000_PE:187 * -NOTE NODES CLK_000_P_SYNC_9_:152 inst_CLK_000_NE:259 CLK_000_N_SYNC_11_:278 * -NOTE NODES cpu_est_2_:176 IPL_D0_0_:136 IPL_D0_1_:169 IPL_D0_2_:145 * -NOTE NODES SM_AMIGA_3_:239 inst_CLK_000_NE_D0:148 SM_AMIGA_0_:235 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:260 SM_AMIGA_6_:155 * -NOTE NODES RST_DLY_0_:140 RST_DLY_1_:103 RST_DLY_2_:133 * -NOTE NODES RST_DLY_3_:125 RST_DLY_4_:143 RST_DLY_5_:119 * -NOTE NODES RST_DLY_6_:142 RST_DLY_7_:109 CLK_000_P_SYNC_0_:190 * -NOTE NODES CLK_000_P_SYNC_1_:262 CLK_000_P_SYNC_2_:130 CLK_000_P_SYNC_3_:163 * -NOTE NODES CLK_000_P_SYNC_4_:131 CLK_000_P_SYNC_5_:211 CLK_000_P_SYNC_6_:205 * -NOTE NODES CLK_000_P_SYNC_7_:256 CLK_000_P_SYNC_8_:157 CLK_000_N_SYNC_0_:184 * -NOTE NODES CLK_000_N_SYNC_1_:124 CLK_000_N_SYNC_2_:118 CLK_000_N_SYNC_3_:112 * -NOTE NODES CLK_000_N_SYNC_4_:178 CLK_000_N_SYNC_5_:106 CLK_000_N_SYNC_6_:194 * -NOTE NODES CLK_000_N_SYNC_7_:209 CLK_000_N_SYNC_8_:122 CLK_000_N_SYNC_9_:250 * -NOTE NODES CLK_000_N_SYNC_10_:272 inst_CLK_030_H:104 SM_AMIGA_1_:223 * -NOTE NODES SM_AMIGA_4_:236 SM_AMIGA_2_:224 inst_DS_000_ENABLE:167 * -NOTE NODES SM_AMIGA_i_7_:221 * +NOTE NODES RN_IPL_030_2_:131 RN_RW_000:269 RN_A0:257 RN_BG_000:175 * +NOTE NODES RN_BGACK_030:275 RN_IPL_030_1_:143 RN_IPL_030_0_:137 * +NOTE NODES RN_DSACK1:283 RN_E:251 RN_VMA:173 RN_RESET:125 * +NOTE NODES RN_RW:245 cpu_est_0_:167 cpu_est_1_:187 inst_AS_000_INT:259 * +NOTE NODES SM_AMIGA_5_:139 inst_AMIGA_BUS_ENABLE_DMA_LOW:104 * +NOTE NODES inst_AS_030_D0:277 inst_nEXP_SPACE_D0reg:133 * +NOTE NODES inst_DS_030_D0:184 inst_AS_030_000_SYNC:229 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:103 inst_DS_000_DMA:110 CYCLE_DMA_0_:106 * +NOTE NODES CYCLE_DMA_1_:122 SIZE_DMA_0_:253 SIZE_DMA_1_:119 * +NOTE NODES inst_VPA_D:265 inst_UDS_000_INT:115 inst_LDS_000_INT:109 * +NOTE NODES inst_CLK_OUT_PRE_D:145 inst_DTACK_D0:172 inst_CLK_OUT_PRE_50:142 * +NOTE NODES inst_CLK_000_D1:217 inst_CLK_000_D0:209 inst_CLK_000_PE:155 * +NOTE NODES CLK_000_P_SYNC_9_:166 inst_CLK_000_NE:113 CLK_000_N_SYNC_11_:278 * +NOTE NODES cpu_est_2_:193 IPL_D0_0_:136 IPL_D0_1_:236 IPL_D0_2_:178 * +NOTE NODES SM_AMIGA_3_:161 inst_CLK_000_NE_D0:233 SM_AMIGA_0_:223 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:121 SM_AMIGA_6_:227 * +NOTE NODES RST_DLY_0_:158 RST_DLY_1_:169 RST_DLY_2_:151 * +NOTE NODES RST_DLY_3_:128 RST_DLY_4_:134 RST_DLY_5_:163 * +NOTE NODES RST_DLY_6_:152 RST_DLY_7_:164 N_203_i:170 CLK_000_P_SYNC_0_:230 * +NOTE NODES CLK_000_P_SYNC_1_:256 CLK_000_P_SYNC_2_:250 CLK_000_P_SYNC_3_:266 * +NOTE NODES CLK_000_P_SYNC_4_:130 CLK_000_P_SYNC_5_:260 CLK_000_P_SYNC_6_:224 * +NOTE NODES CLK_000_P_SYNC_7_:194 CLK_000_P_SYNC_8_:241 CLK_000_N_SYNC_0_:235 * +NOTE NODES CLK_000_N_SYNC_1_:160 CLK_000_N_SYNC_2_:146 CLK_000_N_SYNC_3_:140 * +NOTE NODES CLK_000_N_SYNC_4_:154 CLK_000_N_SYNC_5_:254 CLK_000_N_SYNC_6_:112 * +NOTE NODES CLK_000_N_SYNC_7_:248 CLK_000_N_SYNC_8_:188 CLK_000_N_SYNC_9_:211 * +NOTE NODES CLK_000_N_SYNC_10_:272 inst_CLK_030_H:116 SM_AMIGA_1_:239 * +NOTE NODES SM_AMIGA_4_:176 SM_AMIGA_2_:157 inst_DS_000_ENABLE:182 * +NOTE NODES SM_AMIGA_i_7_:221 CIIN_0:205 * NOTE BLOCK 0 * L000000 - 110111111011111111111111111111111111111111111111111111111101111111 - 111101111111111111111111111111111101111111111111111111101111111111 - 111111111111111111111111111111111111111111111111111111111111110111 - 111111111111111111111111111111111111111111111111111111111111111110 - 111111111111111111111111110111111111111111111111111101111111111111 - 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111111111111111111110111111111110111111111100111011111111111101101* -L009798 111111111111111111110111111111111011111111100111011111111111101110* -L009864 111111111111111111111110111111111111111111101111011111111111111111* -L009930 111111111111111111111111111111111011111111111111011111111111111111* -L009996 000000000000000000000000000000000000000000000000000000000000000000* -L010062 000000000000000000000000000000000000000000000000000000000000000000* +L009600 011101011111111101111101110111111111011111110111110111111111011111* +L009666 011111111111111111101111111111111111111111111111111111101111111111* +L009732 000000000000000000000000000000000000000000000000000000000000000000* +L009798 000000000000000000000000000000000000000000000000000000000000000000* +L009864 000000000000000000000000000000000000000000000000000000000000000000* +L009930 011111111111111111111111111111111011111111111111111111111111111111* +L009996 101111111111111111111101111111111111111111111111111111111111111111* +L010062 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111111111111111110111111111111111011111111111111011111111111111111* +L010326 011111111011111111101111111111111011110111011111101111111111111111* +L010392 011111111011111111101111111111111011111011101111101111111111111111* +L010458 011111110111111111011111111111111011111011101111101111111111111111* +L010524 011111110111111111011111111111111011110111011111101111111111111111* +L010590 011111111111111111111111111111111010111111111111111111111111111111* +L010656 011111111111111111111111111111111110111111111111101111111111111111* +L010722 011111111111111111111111111111111110110111101111111111111111111111* +L010788 011111111111111111111111111111111110111011011111111111111111111111* +L010854 011111111011111111011111111111111110111111111111111111111111111111* +L010920 011111110111111111101111111111111110111111111111111111111111111111* L010986 000000000000000000000000000000000000000000000000000000000000000000* -L011052 111111111111111110111111111111111111111111111111011111111111111110* -L011118 111111111111111110111111111111111111111111101111011111111111011111* -L011184 111111111111111110111111111111111111111111011111011111111111101111* -L011250 111111111111111110110111111111111111111111111011011111111111111111* -L011316 111111111111111110111011111111111111111111110111011111111111111111* -L011382 111111111111111111111111111111111111111111111111101111111111111111* -L011448 111101111111011111111111111111111111111111111111111111111111111111* -L011514 111111111111011111111111111110111111111111111111111111111111111111* -L011580 101110111111111111111111111101111101111110111111111111111111111111* +L011052 111111111111111111111111111111111111111101111111111111111111111111* +L011118 011111111111101111111111111101111111111111111111111111111101111111* +L011184 010111101111011111111111111111111111111111111111111111111111111111* +L011250 010111111111011111111111111101111111111111111111111111111111111111* +L011316 000000000000000000000000000000000000000000000000000000000000000000* +L011382 111111111111111011111111111111111111111111111111111111111111111111* +L011448 000000000000000000000000000000000000000000000000000000000000000000* +L011514 000000000000000000000000000000000000000000000000000000000000000000* +L011580 000000000000000000000000000000000000000000000000000000000000000000* L011646 000000000000000000000000000000000000000000000000000000000000000000* L011712 000000000000000000000000000000000000000000000000000000000000000000* -L011778 110111111111110111011111011111011111111111111111011101010111110111* -L011844 111111111111111111111111011111111111111111111111011111101111111111* -L011910 111111111111111111111111101111111111111111111111011111011111111111* -L011976 110111111111110111011111011111011111111111111111011101110111110111* -L012042 000000000000000000000000000000000000000000000000000000000000000000* -L012108 111111111111111111111111111111111111111111111011011111111111111111* -L012174 111111111111110111111111111111111111111111111111101111111111111111* -L012240 110111111111111011011111011111011111111111111111011101011111110111* -L012306 110111111111110111011111011111011111111111111111111101011011110111* -L012372 000000000000000000000000000000000000000000000000000000000000000000* +L011778 011111111011111111101111111111110111111011101111011111111111111111* +L011844 011111111011111111101111111111111011111011101111101111111111111111* +L011910 011111110111111111011111111111110111111011101111011111111111111111* +L011976 011111110111111111011111111111111011111011101111101111111111111111* +L012042 011111111111111111111111101111111111111111101111111111111111111111* +L012108 111111111111110111111111111111111111111111111111111111111111111111* +L012174 011111111111111111111111101111111011111111111111011111111111111111* +L012240 011111111111111111111111101111110111111111111111101111111111111111* +L012306 011111111111111111111111101111111111111011111111111111111111111111* +L012372 011111111011111111011111101111111111111111111111111111111111111111* L012438 111111111111111111111111111111111111111111111111111111111111111111* -L012504 110111111111111111111111111111111111111111111111101111111111111111* -L012570 111111111111111111011111011111111111111111111111011101011111110111* +L012504 111111111111111111111111111111011111111111111111111111111111111111* +L012570 011111110111111111101111101111111111111111111111111111111111111111* L012636 000000000000000000000000000000000000000000000000000000000000000000* L012702 000000000000000000000000000000000000000000000000000000000000000000* L012768 000000000000000000000000000000000000000000000000000000000000000000* -L012834 111111111111111111111111111111111111111111111111111111011111111111* -L012900 111111111111111111111111111111111111111111111111011111111101111111* -L012966 110111111111110111011111011111011111111111111111011101010111110111* -L013032 000000000000000000000000000000000000000000000000000000000000000000* -L013098 000000000000000000000000000000000000000000000000000000000000000000* +L012834 111111111111111111111111111111111111111111111111111111111111111111* +L012900 111111111111111111111111111111111111111111111111111111111111111111* +L012966 111111111111111111111111111111111111111111111111111111111111111111* +L013032 111111111111111111111111111111111111111111111111111111111111111111* +L013098 111111111111111111111111111111111111111111111111111111111111111111* L013164 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L013296 0010* L013300 10100110011000* -L013314 00111011111110* -L013328 11100110010001* -L013342 00110110011111* -L013356 00000110010010* -L013370 10100110011110* -L013384 11100110010000* -L013398 01100110011111* -L013412 11000110011001* +L013314 00010110011110* +L013328 10100110010100* +L013342 00100110011111* +L013356 11100110010011* +L013370 01110110011111* +L013384 00000111010110* +L013398 01110110011110* +L013412 11100110011000* L013426 10110110010011* -L013440 10000110010000* -L013454 10000111010010* -L013468 00000111010000* -L013482 01000110010011* -L013496 10000110010001* -L013510 00110110011111* +L013440 00110110010001* +L013454 00100110010011* +L013468 11100110011000* +L013482 00110110010010* +L013496 00000110010100* +L013510 11101111111111* NOTE BLOCK 2 * L013524 - 111111110111111111101011111111111110111111111111111111111111111111 - 111111111111111111111110111111111111111111111111111111111111111111 - 111110101111111111111111111111110111111111111111101110111111111111 - 111111111101111110111111101110011111111111111111111111111101111110 - 111111111111111111111111111111111111111111110111111011111111111111 - 111111111111111111111111111111111111111011111111111111011111111111 - 111111111111010111111111111111111111111111111111111111111111110111 - 111111111111111111111111111011111111111110111111111111111111111111 - 101011111111111111111111111111111111111111111111111111111111111111* + 111111110101101111111111101111111111111111111111111111111111011111 + 111111111111111101111111110111111111101111111111011111111111111101 + 111111111111110111111101111111111111111110111111111111011111111111 + 111110111111111111110111111101011111111111110111111111111111111111 + 110111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111101111111 + 111111011111111111011111111111111111111111111111110111111111111111 + 111111111111111111111111111111111111111111111110111111111111111111 + 011111111111111111111111111111110110111111101111111101111111111111* L014118 000000000000000000000000000000000000000000000000000000000000000000* -L014184 111111111111111111111011111111111111111110111111111111111111111111* +L014184 101111111111111111111111111111111111111111111110111111111111111111* L014250 000000000000000000000000000000000000000000000000000000000000000000* L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 011111111111111111111111111101111111111111111111111111111111111111* -L014580 010111111111111111111111111011111111111111111011111111111111111111* -L014646 000000000000000000000000000000000000000000000000000000000000000000* -L014712 000000000000000000000000000000000000000000000000000000000000000000* -L014778 000000000000000000000000000000000000000000000000000000000000000000* +L014514 110111101111111111111111111111111111111111011111111111111111111111* +L014580 110111111111111111111111111111111111111111011111111111101111111111* +L014646 110111111111111111111111111111111111111111011111111111111111101111* +L014712 111011011111111111111111111111111111111111011111111111011111011111* +L014778 110111111111111101110101110111111111111111010111111111111111111111* L014844 000000000000000000000000000000000000000000000000000000000000000000* -L014910 111111111111111111111111111111011111111111111111111111111111111111* -L014976 111111111111111111111111111111111111111111111111111111111111111111* -L015042 111111111111111111111111111111111111111111111111111111111111111111* -L015108 111111111111111111111111111111111111111111111111111111111111111111* -L015174 111111111111111111111111111111111111111111111111111111111111111111* -L015240 111111111111111111111111111111111111111111111111111111111111111111* -L015306 111111111111111111111111111111111111111111111111111111111111111111* -L015372 111111111111111111111111111111111111111111111111111111111111111111* -L015438 111111111111111111111111111111111111111111111111111111111111111111* -L015504 111111111111111111111111111111111111111111111111111111111111111111* +L014910 111111111111111111111111111111111111111111100111111111111111111111* +L014976 110111011111111111110101110111111111111111011011111111011111011111* +L015042 110111011111111110110101110111111111111111110111111111011111011111* +L015108 000000000000000000000000000000000000000000000000000000000000000000* +L015174 000000000000000000000000000000000000000000000000000000000000000000* +L015240 111111111111111111111111111111111111111111111111011111111111111111* +L015306 000000000000000000000000000000000000000000000000000000000000000000* +L015372 000000000000000000000000000000000000000000000000000000000000000000* +L015438 000000000000000000000000000000000000000000000000000000000000000000* +L015504 000000000000000000000000000000000000000000000000000000000000000000* L015570 000000000000000000000000000000000000000000000000000000000000000000* -L015636 011101111111111111101111111111111011111111111111111011111111111101* -L015702 011111111111111111111111111111111111111111111111111011111101111111* -L015768 010111111111111011111111111111111111111111111111111111111101111111* +L015636 111111111111111111111111111111111111111111111111111111111111111101* +L015702 000000000000000000000000000000000000000000000000000000000000000000* +L015768 000000000000000000000000000000000000000000000000000000000000000000* L015834 000000000000000000000000000000000000000000000000000000000000000000* L015900 000000000000000000000000000000000000000000000000000000000000000000* -L015966 111111111111111111111111111111111111111111111111111101111111111111* -L016032 111111111111111111111111111111111111111111111111111111111111111111* -L016098 111111111111111111111111111111111111111111111111111111111111111111* -L016164 111111111111111111111111111111111111111111111111111111111111111111* -L016230 111111111111111111111111111111111111111111111111111111111111111111* +L015966 111111111110110111111111011111111111111101011111111111111111111111* +L016032 111101111011110111111111101111111111111101011111111010111101111111* +L016098 111111111111110111111111111111011111111111011111111111111111111111* +L016164 111111111111111111111111111110011101111111011111111111111111111111* +L016230 000000000000000000000000000000000000000000000000000000000000000000* L016296 000000000000000000000000000000000000000000000000000000000000000000* -L016362 111111111111111111111111111111111111111111111111111111111111111111* -L016428 111111111111111111111111111111111111111111111111111111111111111111* -L016494 111111111111111111111111111111111111111111111111111111111111111111* -L016560 111111111111111111111111111111111111111111111111111111111111111111* -L016626 111111111111111111111111111111111111111111111111111111111111111111* -L016692 111111111111111111111111111111111111111111111111111111111111111111* -L016758 111111111111111111111111111111111111111111111111111111111111111111* -L016824 111111111111111111111111111111111111111111111111111111111111111111* -L016890 111111111111111111111111111111111111111111111111111111111111111111* -L016956 111111111111111111111111111111111111111111111111111111111111111111* +L016362 111111101111111111111111111111111111111111011111111111011111111111* +L016428 111111011111111111111111111111111111111111011111111111101111111111* +L016494 110111111111111101110101110111111111111111010111111111011111011111* +L016560 000000000000000000000000000000000000000000000000000000000000000000* +L016626 000000000000000000000000000000000000000000000000000000000000000000* +L016692 111111111111111111111111111111111111011111111111111111111111111111* +L016758 000000000000000000000000000000000000000000000000000000000000000000* +L016824 000000000000000000000000000000000000000000000000000000000000000000* +L016890 000000000000000000000000000000000000000000000000000000000000000000* +L016956 000000000000000000000000000000000000000000000000000000000000000000* L017022 000000000000000000000000000000000000000000000000000000000000000000* -L017088 010111111111111111111111111011111011111111111111111111111111111111* -L017154 010111111111111111111111101011111111110101111111111011111111111101* -L017220 010111111111111111111111111011111111110101111111111011011111111101* -L017286 010111111111111111111111111011111111110101111111111011111111110101* -L017352 010111111111111110111111111011111111110101111111111011111111111101* -L017418 111111111101111111111111111111111111111111111111111111111111111111* -L017484 010111111111011111111111111011111111110101111111111011111111111101* -L017550 010111111111111111111111111011111111110101111111101011111111111101* -L017616 000000000000000000000000000000000000000000000000000000000000000000* +L017088 111111111111110111111111111111111111111111101111111111111111111111* +L017154 111111111111111011111111111101110111111111011111111111111111111111* +L017220 111111111110110111111111011111111011111101111111111111111111111111* +L017286 111101111011110111111111101111111011111101111111111010111101111111* +L017352 111111111111110111111111111111111110111111111111111111111111111111* +L017418 111111111111111111111111110111111111111111101111111111111111111111* +L017484 110111011111111111110101111011111111111111011111111111011111011111* +L017550 110111011111111111110101110111111111111111111011111111011111011111* +L017616 110111011111111110110101110111111111111111111111111111011111011111* L017682 000000000000000000000000000000000000000000000000000000000000000000* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 111111111111111111111111111111111111111111111111111111111111111111* -L017880 111111111111111111111111111111111111111111111111111111111111111111* -L017946 111111111111111111111111111111111111111111111111111111111111111111* -L018012 111111111111111111111111111111111111111111111111111111111111111111* -L018078 111111111111111111111111111111111111111111111111111111111111111111* -L018144 111111111111111111111111111111111111111111111111111111111111111111* -L018210 111111111111111111111111111111111111111111111111111111111111111111* -L018276 111111111111111111111111111111111111111111111111111111111111111111* -L018342 111111111111111111111111111111111111111111111111111111111111111111* -L018408 111111111111111111111111111111111111111111111111111111111111111111* +L017814 110111011111111111110101110111111111111111010111111111011111011111* +L017880 111111111111111101111111111111111111111111011111111111111111111111* +L017946 000000000000000000000000000000000000000000000000000000000000000000* +L018012 000000000000000000000000000000000000000000000000000000000000000000* +L018078 000000000000000000000000000000000000000000000000000000000000000000* +L018144 111111111111011111111111111111111111111111111111111111111111111111* +L018210 000000000000000000000000000000000000000000000000000000000000000000* +L018276 000000000000000000000000000000000000000000000000000000000000000000* +L018342 000000000000000000000000000000000000000000000000000000000000000000* +L018408 000000000000000000000000000000000000000000000000000000000000000000* L018474 000000000000000000000000000000000000000000000000000000000000000000* -L018540 011111111111111111111111111110111101111111111111111111111111111111* -L018606 010111110111111111111111111011111111111111111111111111111111111111* -L018672 011111111111111111111101111101111111111111111111111111111111111111* +L018540 111111111011111111111111111111111111111101111111111111111111111111* +L018606 111111110111111111111111111111111111111110111111111111111111111111* +L018672 000000000000000000000000000000000000000000000000000000000000000000* L018738 000000000000000000000000000000000000000000000000000000000000000000* L018804 000000000000000000000000000000000000000000000000000000000000000000* -L018870 011111101111111111111111111111111111111111111111111111111111111111* -L018936 111111111111111111111111111111111111111111111111111111111111111111* -L019002 111111111111111111111111111111111111111111111111111111111111111111* -L019068 111111111111111111111111111111111111111111111111111111111111111111* -L019134 111111111111111111111111111111111111111111111111111111111111111111* +L018870 111111101111111111111111111111111111111111011111111111111111011111* +L018936 111111111111111111111111111111111111111111011111111111101111011111* +L019002 111111011111111111111111111111111111111111011111111111011111101111* +L019068 110111111111111101110101110111111111111111010111111111111111011111* +L019134 000000000000000000000000000000000000000000000000000000000000000000* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 111111111111111111111111111111111111111111111111111111111111111111* -L019332 111111111111111111111111111111111111111111111111111111111111111111* -L019398 111111111111111111111111111111111111111111111111111111111111111111* -L019464 111111111111111111111111111111111111111111111111111111111111111111* -L019530 111111111111111111111111111111111111111111111111111111111111111111* -L019596 111111111111111111111111111111111111111111111111111111111111111111* -L019662 111111111111111111111111111111111111111111111111111111111111111111* -L019728 111111111111111111111111111111111111111111111111111111111111111111* -L019794 111111111111111111111111111111111111111111111111111111111111111111* -L019860 111111111111111111111111111111111111111111111111111111111111111111* +L019266 111111111110111111111111011111111111111101111111111111111111111111* +L019332 111101111011111111111111101111111111111101111111111010111101111111* +L019398 000000000000000000000000000000000000000000000000000000000000000000* +L019464 000000000000000000000000000000000000000000000000000000000000000000* +L019530 000000000000000000000000000000000000000000000000000000000000000000* +L019596 111111111111111111101111111111111111111111011111111111111111111111* +L019662 000000000000000000000000000000000000000000000000000000000000000000* +L019728 000000000000000000000000000000000000000000000000000000000000000000* +L019794 000000000000000000000000000000000000000000000000000000000000000000* +L019860 000000000000000000000000000000000000000000000000000000000000000000* L019926 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L020058 0010* L020062 01100011111000* -L020076 11100110010011* -L020090 00010110010001* -L020104 11101011110011* -L020118 10100110010000* -L020132 00000110010010* -L020146 11011111110001* -L020160 11111011110011* -L020174 11100110010000* -L020188 00110110010010* -L020202 11010011110110* -L020216 11111011111111* +L020076 10100110010011* +L020090 10100111010001* +L020104 00100110010011* +L020118 00100110010000* +L020132 10100110010010* +L020146 10100110010000* +L020160 00100110010011* +L020174 10100111010001* +L020188 10100111010011* +L020202 10100110010110* +L020216 00100110011110* L020230 10100110010000* -L020244 01000110010010* -L020258 11011111110001* -L020272 11110011111111* +L020244 10100110010011* +L020258 11100011110001* +L020272 01100110011111* NOTE BLOCK 3 * L020286 - 111111110111111101111111101111101111111111111111111111111101111111 - 111111111111111111111011111101110111111111111111111111111011111111 - 111111111111111111111111111111111111111110111111111111101111111111 - 111101111111111111111110111111111111111111111011111111111111111111 - 111111111101111111111111111111111111111111111111111011111111111111 - 111111111111111111111111111111111111111111011111111111111111111111 - 110111111111110111011111111111111111111111111111111111111111111111 - 111111111111011111111111111011111111111111111110111111111111011111 - 101111011111111111111111111111111101011111111111111111111111111111* + 111111111111111111111111101111011111111111111111111111111111111111 + 111111111111111110111111111101111111111111111111111111111111110111 + 011111111111111111111111111111111111111111111011111111111101111110 + 111111111111011111101110111111111111111111111110111111111111111111 + 111111111101111111111111111111111111111111111111111001111111111111 + 110111111111111111111111111111111111111111111111111111110111111111 + 111111111111110111111111111111111011110111111111111111111111011111 + 111101110111111111111111111011111111111110111111111111111111111111 + 111111011111111111111111111111111110011111101111111111011111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 101111111111111111111111111111111111101111111111111111111111111111* -L021012 111111011111110111111110111111111111101111011111111111111111101111* -L021078 011111011111111111110110111111101111011111101111111111111111011111* +L020946 111111111111111111111111111111111111101111101111111111111111111111* +L021012 110111111111010111111110111111101111101111111111111111111111111111* +L021078 110111111111111011111110101111011111011111011111111111111111011111* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 011111111111111111111111010110111111111111110111111111111111111111* -L021342 011111111111111111111111111110111110111111111111111111111111111111* +L021276 011111111111111111111111110110110111111111011111111111111111111111* +L021342 111111111111111111111111111110111111111111011111111111101111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111011111111111111111111111111111111111011111111111111111111111* -L021738 111111111111111101111101111111111111111111111111111111111111011111* -L021804 111111111111111101111111111111111111111111101111111111111111101111* -L021870 111111011111111110111111111111111111111111111111111111111111111111* +L021672 111111111111111111111111111111111111111111011111111111111111010111* +L021738 111111011111111111111111111111111111111111011111111111111111110111* +L021804 111111011111101111111111111111111101111111011111111111111111111111* +L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* -L022002 110111111111111111111111111111111111111111111111111111111111111111* +L022002 111111111111111111111111111111111111111111011011111111111111111111* L022068 000000000000000000000000000000000000000000000000000000000000000000* L022134 000000000000000000000000000000000000000000000000000000000000000000* L022200 000000000000000000000000000000000000000000000000000000000000000000* L022266 000000000000000000000000000000000000000000000000000000000000000000* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 111111111111111111111111111111111111111111111110111111110111111111* -L022464 111111111111111111111111111111111111111111111101111011111111111111* +L022398 111111111111111111111111111111111111111110111111111111110111111111* +L022464 111111111111111111111111111111111111111101111111111011111111111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* @@ -503,65 +504,65 @@ L022860 000000000000000000000000000000000000000000000000000000000000000000* L022926 000000000000000000000000000000000000000000000000000000000000000000* L022992 000000000000000000000000000000000000000000000000000000000000000000* L023058 - 111111111111111111111111111111111111111111111101111111111101111111* -L023124 111111111111111101111111111111111111111111111111111111111111101111* -L023190 111111111111111110111111111111111111111111111111111111111111011111* -L023256 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111101111111111101111111111111* +L023124 111111111111111111111111111111111111111111011111111111111101111011* +L023190 111111110111111111111111111011111101111111011111111111111111111111* +L023256 111111111111111101111111111111111111111111011111111111111111110111* L023322 000000000000000000000000000000000000000000000000000000000000000000* L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 111111111111111111111111101111111111111101111111111111111111111111* +L023454 111111111110111111111111111111111111111111011111111111111111111111* L023520 000000000000000000000000000000000000000000000000000000000000000000* L023586 000000000000000000000000000000000000000000000000000000000000000000* L023652 000000000000000000000000000000000000000000000000000000000000000000* L023718 000000000000000000000000000000000000000000000000000000000000000000* L023784 - 111111111111111111111111111111111111111111111101111111111101111111* -L023850 111111110110111111111111111111111111111111111111111111101111111111* + 111111111111111111111111111111111111111101111111111101111111111111* +L023850 111111110110111111111111111111111111111011111111111111111111111111* L023916 000000000000000000000000000000000000000000000000000000000000000000* L023982 000000000000000000000000000000000000000000000000000000000000000000* L024048 000000000000000000000000000000000000000000000000000000000000000000* L024114 000000000000000000000000000000000000000000000000000000000000000000* -L024180 111101111111111111111111111111111111111111111111111111111111111111* -L024246 000000000000000000000000000000000000000000000000000000000000000000* -L024312 000000000000000000000000000000000000000000000000000000000000000000* -L024378 000000000000000000000000000000000000000000000000000000000000000000* -L024444 000000000000000000000000000000000000000000000000000000000000000000* +L024180 111111111111111011111101111111011111111111111111111111111111111111* +L024246 110111111111111011111110111111101111111111111111111111111111111111* +L024312 110111111111110111111110111111011111111111111111111111111111111101* +L024378 111011111111111111111101111111011111111111111111111111111111111101* +L024444 111111111111111011111111111111111111111111111111111111111111111110* L024510 000000000000000000000000000000000000000000000000000000000000000000* -L024576 011111111110111111111111111111111111111111111111111111111111111111* -L024642 000000000000000000000000000000000000000000000000000000000000000000* -L024708 000000000000000000000000000000000000000000000000000000000000000000* -L024774 000000000000000000000000000000000000000000000000000000000000000000* -L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 111111111111111111111111011111111111111110111111111111111111111111* -L024972 000000000000000000000000000000000000000000000000000000000000000000* -L025038 000000000000000000000000000000000000000000000000000000000000000000* -L025104 000000000000000000000000000000000000000000000000000000000000000000* -L025170 000000000000000000000000000000000000000000000000000000000000000000* +L024576 111111111111111111111111111111111111111111111101111111111111111111* +L024642 111111111111111111111111111111111111111111111111111111111111111111* +L024708 111111111111111111111111111111111111111111111111111111111111111111* +L024774 111111111111111111111111111111111111111111111111111111111111111111* +L024840 111111111111111111111111111111111111111111111111111111111111111111* +L024906 111111111111111111111111111111111111111111111111111111111111111111* +L024972 111111111111111111111111111111111111111111111111111111111111111111* +L025038 111111111111111111111111111111111111111111111111111111111111111111* +L025104 111111111111111111111111111111111111111111111111111111111111111111* +L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111110110111111111111111111111011111111111111111111111111111111* -L025368 000000000000000000000000000000000000000000000000000000000000000000* -L025434 000000000000000000000000000000000000000000000000000000000000000000* -L025500 000000000000000000000000000000000000000000000000000000000000000000* -L025566 000000000000000000000000000000000000000000000000000000000000000000* -L025632 111111111111111111111101111111111111111111101111111111111111011111* -L025698 111111011111111111111110111111111111111111101111111111111111101111* -L025764 111111011111111101111110111111111111111111011111111111111111011111* -L025830 111111101111111101111101111111111111111111111111111111111111011111* -L025896 111111111111111110111111111111111111111111101111111111111111111111* +L025302 111110110110111111111111111111111111111111111111111111111111111111* +L025368 111111111111111111111111111111111111111111111111111111111111111111* +L025434 111111111111111111111111111111111111111111111111111111111111111111* +L025500 111111111111111111111111111111111111111111111111111111111111111111* +L025566 111111111111111111111111111111111111111111111111111111111111111111* +L025632 110111111111110111111111111111111111111111111111111111111111111111* +L025698 111111111111111111111101111111011111111111111111111111111111111101* +L025764 111111111111111011111111111111101111111111111111111111111111111101* +L025830 110111111111111111111111111111111111111111111111111111111111111110* +L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111111011111111111111111111111111111111111111111111111111111* -L026094 000000000000000000000000000000000000000000000000000000000000000000* -L026160 000000000000000000000000000000000000000000000000000000000000000000* -L026226 000000000000000000000000000000000000000000000000000000000000000000* -L026292 000000000000000000000000000000000000000000000000000000000000000000* -L026358 011111111111111111101111111111111111111111111111111111111111111111* -L026424 000000000000000000000000000000000000000000000000000000000000000000* -L026490 000000000000000000000000000000000000000000000000000000000000000000* -L026556 000000000000000000000000000000000000000000000000000000000000000000* -L026622 000000000000000000000000000000000000000000000000000000000000000000* +L026028 111111111111111111011111111111111111111111111111111111111111111111* +L026094 111111111111111111111111111111111111111111111111111111111111111111* +L026160 111111111111111111111111111111111111111111111111111111111111111111* +L026226 111111111111111111111111111111111111111111111111111111111111111111* +L026292 111111111111111111111111111111111111111111111111111111111111111111* +L026358 111111111111111111111111111111111111111111111111111111111111111111* +L026424 111111111111111111111111111111111111111111111111111111111111111111* +L026490 111111111111111111111111111111111111111111111111111111111111111111* +L026556 111111111111111111111111111111111111111111111111111111111111111111* +L026622 111111111111111111111111111111111111111111111111111111111111111111* L026688 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* @@ -569,44 +570,44 @@ L026820 0010* L026824 10100111010000* L026838 11100110011110* L026852 10100110010100* -L026866 00100110011111* +L026866 01100110011111* L026880 10101011111001* L026894 00100011111111* L026908 10100110010100* -L026922 00100110010010* +L026922 01100110010010* L026936 01101011110011* -L026950 00100110010011* -L026964 01100110010000* -L026978 00100110010011* -L026992 01101111111011* -L027006 11100110011111* -L027020 00100110010000* -L027034 01100110010010* +L026950 11100110010011* +L026964 00010110010000* +L026978 11101111110011* +L026992 01110011111011* +L027006 10100110011111* +L027020 00010110010000* +L027034 11101011110010* NOTE BLOCK 4 * L027048 - 111111111111111111111111111111111111111111111111111111111101111111 - 110111111111111111111111111111111111110111111111111111111111111111 - 111111111101111111111111010111111110111111111111111111111111111111 - 011111101111111110011111111111111111111110011111111111111111111111 - 111111111111110111110111111111111111111111110111111111111111111111 - 111111111111111111111111111111111111011111111111111111011111111111 - 111110111111011111111111111111111111111111111111111111111011110111 - 111111111011111111111111111111111111111111111110111111111111111110 - 111111111111111111111101111111111011111111111111111111111111111111* + 111111111111111111111111111111111111111111111111011111111111111111 + 111111111111111111111011111111111111110111111111110111111111111111 + 111111110101101111111111111111111111111111110111111111110111111111 + 111011011111111111111111111111111101111111111111111111101111111111 + 011111111111110111111111111111111111111111111111111111111111111111 + 111111111111111111111111011111111111011101111111111111111111111111 + 111111111111111111111111111111111011111111101111111101111111110111 + 111111111111111111111111111010011111111111111110111111111101111110 + 111110111111111110101101111111111111111111111111111111111111111111* L027642 - 111111111111101101111101111111111101011101111111111111101111111010* + 110111111111011111111101101111111111011111111111111110011111111010* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 111111101111111111111111111111111011111111111110111111110111111111* -L028104 111111111111111111111111111111111111111111111101111111111011111111* +L028038 111110111111111111111111111111111111111111011110111111111011111111* +L028104 111111111111111111111111111111111111111111101101111111111111111111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 111111111111111111111111111111111111111111111101111111111101111111* + 011111111111111111111111111111111111111111111101111111111111111111* L028434 111111111111111111111111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* @@ -619,16 +620,16 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111111111111111111111111111111111111111111011111111111111111110* +L029160 111111111111111111111011111111111111111111111111111111111111111110* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 111101111111111111111111111111111111111111111111111111111111111111* -L029556 111111111111111111111111111111111111111111111111111111111111111111* -L029622 111111111111111111111111111111111111111111111111111111111111111111* -L029688 111111111111111111111111111111111111111111111111111111111111111111* -L029754 111111111111111111111111111111111111111111111111111111111111111111* +L029490 111111101010111001011111111011011110111011111011111011111101111111* +L029556 111111111111111111111111111111111111111111111111111111110111111111* +L029622 000000000000000000000000000000000000000000000000000000000000000000* +L029688 000000000000000000000000000000000000000000000000000000000000000000* +L029754 000000000000000000000000000000000000000000000000000000000000000000* L029820 000000000000000000000000000000000000000000000000000000000000000000* L029886 111111111111111111111111111111111111111111111111111111111111111111* @@ -643,12 +644,12 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 111111111111111111110111111111111111111111111111111111111111111111* +L030612 111111111111111111111111111111111111111111111111011111111111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 011111111111111111111111111111111111111111111111111111111111111111* +L030942 111111111111111111111111111111111111111101111111111111111111111111* L031008 111111111111111111111111111111111111111111111111111111111111111111* L031074 111111111111111111111111111111111111111111111111111111111111111111* L031140 111111111111111111111111111111111111111111111111111111111111111111* @@ -666,13 +667,13 @@ L031800 111111111111111111111111111111111111111111111111111111111111111111* L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 - 111011011010111011101111101011111111111011101111111111111111111111* -L032064 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111101111111111111111111111111111111111111* +L032064 111111101010111001011111111011011110111011111011111011111101111111* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* L032328 111111111111111111111111111111111111111111111111111111111111111111* -L032394 111111111111111111111111111111111111111111111111111111111111111111* +L032394 111111111111111111111111111111110111111111111111111111111111111111* L032460 111111111111111111111111111111111111111111111111111111111111111111* L032526 111111111111111111111111111111111111111111111111111111111111111111* L032592 111111111111111111111111111111111111111111111111111111111111111111* @@ -698,69 +699,69 @@ L033600 10101111110011* L033614 11011011110100* L033628 11110011110010* L033642 01111111111001* -L033656 00000110011111* -L033670 11010111110000* -L033684 11110011111111* +L033656 10101011111111* +L033670 11011111110000* +L033684 11111011111111* L033698 00110110010000* L033712 00000110011110* -L033726 11010111110000* -L033740 11111111111111* -L033754 00110011110001* -L033768 11001011111111* -L033782 11110111111100* -L033796 11111111111111* +L033726 11011111110001* +L033740 11110011111110* +L033754 00111011110000* +L033768 00000110011110* +L033782 11010111111101* +L033796 11111111111110* NOTE BLOCK 5 * L033810 - 111111111111101101111111101111111110111111111111111111111111111111 - 111111111111111111111111111111111111101011111111111111101111111111 - 111111111111110111101110111111101111111111111111111111111111111110 - 111110111111111111111111111101111111111111111011111111111010111111 - 111111111111111111111011111111111111111111111111111111111111110111 - 111111111111111111111111111111111111111101011111111111111111111111 - 111111111111111111111111111111111111111111111111110111111111111111 - 111111110111111111111111111111111111111111111111111111111111111111 - 101011011111111111111111110111111111111111111111111101111111111111* + 111111111111111111111111111111111111011111111111111111111111111011 + 111111111110111111111111111111110111111111111111111111111111111111 + 111111111111111111101111111111111111111111101111101111110101111111 + 111111111111110111111011101001111111111111111111111111111111111111 + 111111111111111111111111111111101101111111111111111011111111111111 + 111110111111011111111111111111111111111011111111111111111111111111 + 111111110111111110111101111111111111111111111111111111111111011111 + 111111111111111111111111111111111111111110111111111111101111111111 + 101011011111111111111111111111111111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 011111111111111111111110111111111110101111111111110111011111111111* -L034536 011111111111011101111110111111111111101111111111110111011111111011* -L034602 011101011011101101111110111111111111101111101111110110011111111111* -L034668 011111111111111111111010111111111110101111111111110111111110111111* -L034734 011111111111011101111010111111111111101111111111110111111110111011* -L034800 011101011011101101111010111111111111101111101111110110111110111111* -L034866 011111111111111111111110111110111110101011111111111111011011111111* -L034932 011111111111011101111110111110111111101011111111111111011011111011* -L034998 011101011011101101111110111110111111101011101111111110011011111111* -L035064 011111111111111111111010111110111110101011111111111111111010111111* +L034470 101111111111111111111111111111111111111111111111111111111111111111* +L034536 111111111111111111111111111101011111111111111111111111111111111111* +L034602 111111101111111011111011111111101011111111111111111111111010111011* +L034668 111111101111111011011011111111101011111111111111111111111110111011* +L034734 111110101111111011111011111111101011111111111111111111111110111011* +L034800 111111101111111001111011111111101011111111111111111111111110111011* +L034866 111011111111111111111111111111110111111111111111111111111111101111* +L034932 111011111111111111111111111111011111111111111111111111111111111111* +L034998 111011111111111111110111111110111111111111111111111111111111111111* +L035064 111011111111111111111111111111111111011111111111111111111101111111* L035130 000000000000000000000000000000000000000000000000000000000000000000* -L035196 011111111111011101111010111110111111101011111111111111111010111011* -L035262 011101011011101101111010111110111111101011101111111110111010111111* -L035328 010111111111111111111110111111111111111111111111111011111111111111* -L035394 010111111111111111111110111111111111101111111111111111111111111111* +L035196 111111111101111111111111111111111111111111111111111111111111111111* +L035262 111011111111111111111111111111111111111111111111111111111111100111* +L035328 111011011111111111111111111110111111111111111111111111111111111111* +L035394 111011111111110111111111111110111111111111111111111111111111111111* L035460 000000000000000000000000000000000000000000000000000000000000000000* -L035526 011111111111111111111011111111111111111111111111110111110111111111* -L035592 010111111111111111110111111111111111111111111111111111101111111111* -L035658 010111111111111111110111111111111111111111111111111111110111111111* +L035526 011111111111111111111111111111101111111111111111111111111111010111* +L035592 010111111111111111111111111110011111111111111111111111111111111111* +L035658 000000000000000000000000000000000000000000000000000000000000000000* L035724 000000000000000000000000000000000000000000000000000000000000000000* L035790 000000000000000000000000000000000000000000000000000000000000000000* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 011111111111011101111111111111111101111111111111111111111111111011* -L035988 011101011011101101111111111111111101111111101111111110111111111111* -L036054 011111111111111111111111111111111101111111111111111111110111111111* -L036120 010111111111111111111111111111111111111111111111111011110111111111* +L035922 011101111111111110101111111111111111111111111111111011110111111111* +L035988 011111111111111111110111111111111111111111111111111011111111111111* +L036054 010111111111111111110111111110111111111111111111111111111111111111* +L036120 000000000000000000000000000000000000000000000000000000000000000000* L036186 000000000000000000000000000000000000000000000000000000000000000000* -L036252 011111111111111111101111111111111111111101111111111111111111111111* -L036318 011111111111111111101111111110111111111111111111111111111111111111* -L036384 011111111111111111111111111101101111111110111111111111111111111111* -L036450 000000000000000000000000000000000000000000000000000000000000000000* -L036516 000000000000000000000000000000000000000000000000000000000000000000* +L036252 010111111111111111101111111111111111111111111111111111101111111111* +L036318 010111111111111111111111101111111111110101111111111011100111111111* +L036384 010111111111011111111111111111111111110101111111111011100111111111* +L036450 010111110111111111111111111111111111110101111111111011100111111111* +L036516 010111111111111111111111111011111111110101111111111011100111111111* L036582 000000000000000000000000000000000000000000000000000000000000000000* -L036648 011111111111111111111111111101111111111111111111110111111110111111* -L036714 010111111111111111111111111111111111111111111111111111101101111111* -L036780 010111111111111111111111111101111111111111111111111111111101111111* +L036648 111110111111111101111111111111111111111111111111111111111111111111* +L036714 010111111111111111111101111111111111110101111111111011100111111111* +L036780 010111111111111111111111111111111111110101111111101011100111111111* L036846 000000000000000000000000000000000000000000000000000000000000000000* L036912 000000000000000000000000000000000000000000000000000000000000000000* L036978 111111111111111111111111111111111111111111111111111111111111111111* @@ -770,23 +771,23 @@ L037176 111111111111111111111111111111111111111111111111111111111111111111* L037242 111111111111111111111111111111111111111111111111111111111111111111* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 111111111111111111111111011111111111111111111111111111111111111111* -L037440 111111111111111111111011111110111110101011111011111111111010111111* -L037506 111111111111110111111011111110111110101011111111111111111010111111* -L037572 111111111111111111111011111110111110101011111111111111111010111110* -L037638 111111111111111111111011011110111110101011111111111111111010111111* -L037704 011111111111111111110111111111111111101111111111111111011111111111* -L037770 010111111111111111111111111111111111011111111111111011111111111111* -L037836 000000000000000000000000000000000000000000000000000000000000000000* -L037902 000000000000000000000000000000000000000000000000000000000000000000* -L037968 000000000000000000000000000000000000000000000000000000000000000000* +L037374 111111111111111111111111111111111111111111111111111111111111011111* +L037440 111111111111111111111111111111111111111111111111111111111111111111* +L037506 111111111111111111111111111111111111111111111111111111111111111111* +L037572 111111111111111111111111111111111111111111111111111111111111111111* +L037638 111111111111111111111111111111111111111111111111111111111111111111* +L037704 111101111111111110111111111111111111111111111111111111111111111111* +L037770 111111111111111111111111111111111111111111111111111111111111111111* +L037836 111111111111111111111111111111111111111111111111111111111111111111* +L037902 111111111111111111111111111111111111111111111111111111111111111111* +L037968 111111111111111111111111111111111111111111111111111111111111111111* L038034 000000000000000000000000000000000000000000000000000000000000000000* -L038100 011111111111111111111111111111111111111111111111111111011101111111* -L038166 011111111111111111111111111111111111110111111111111111111101111111* -L038232 010111111111111111111111111111111111110111111111111011111111111111* -L038298 000000000000000000000000000000000000000000000000000000000000000000* -L038364 000000000000000000000000000000000000000000000000000000000000000000* +L038100 011111111111111111111111111111111111111111101111111111111111111111* +L038166 111111111111111111111111111111111111111111111111111111111111111111* +L038232 111111111111111111111111111111111111111111111111111111111111111111* +L038298 111111111111111111111111111111111111111111111111111111111111111111* +L038364 111111111111111111111111111111111111111111111111111111111111111111* L038430 111111111111111111111111111111111111111111111111111111111111111111* L038496 111111111111111111111111111111111111111111111111111111111111111111* L038562 111111111111111111111111111111111111111111111111111111111111111111* @@ -794,16 +795,16 @@ L038628 111111111111111111111111111111111111111111111111111111111111111111* L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 101111111111111111111111111111111101111111111111111111111111111111* -L038892 011111111111111111111111111111111110110111111111110111111111111111* -L038958 111111111111011101111111111111111101111011111111111111111111111011* -L039024 111101011011101101111111111111111101111011101111111110111111111111* -L039090 111011111111111111111111111111111101111111111111111111111111111111* -L039156 011111111111111111111111111011111111111111111111111111111111111111* -L039222 111111111111111111111111111111111111111111111111111111111111111111* -L039288 111111111111111111111111111111111111111111111111111111111111111111* -L039354 111111111111111111111111111111111111111111111111111111111111111111* -L039420 111111111111111111111111111111111111111111111111111111111111111111* +L038826 111111111111111111111111111111111111111111111111111111111111111111* +L038892 111111111111111111111111111111111111111111111111111111111111111111* +L038958 111111111111111111111111111111111111111111111111111111111111111111* +L039024 111111111111111111111111111111111111111111111111111111111111111111* +L039090 111111111111111111111111111111111111111111111111111111111111111111* +L039156 111111111111111111111111111111111101111111111111111111111111111111* +L039222 011111111111110111111111111101111111111111111111111111111111111011* +L039288 010111111111111111111111111111111111111111111111111111111111100111* +L039354 010111111111110111111111111111111111111111111111111111111111110111* +L039420 000000000000000000000000000000000000000000000000000000000000000000* L039486 000000000000000000000000000000000000000000000000000000000000000000* L039552 111111111111111111111111111111111111111111111111111111111111111111* @@ -820,175 +821,175 @@ L040212 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* -L040348 10100110011110* +L040348 11100110011110* L040362 10110110010010* -L040376 10000110011110* +L040376 00000110011110* L040390 11000011110011* -L040404 10000110011111* +L040404 10100110011111* L040418 11100110010011* -L040432 10001011111110* -L040446 11100011110011* -L040460 00000110011111* -L040474 10100110010011* -L040488 10100110011110* -L040502 11101111111110* -L040516 10100111011111* -L040530 01000110011111* -L040544 11010011111110* -L040558 11111011111111* +L040432 00110110011110* +L040446 11101111110011* +L040460 00110110011111* +L040474 00000110010011* +L040488 01010110011110* +L040502 11101011111110* +L040516 10110110011110* +L040530 00110110011111* +L040544 11011111111110* +L040558 11110011111110* NOTE BLOCK 6 * L040572 - 111111111111111101011011111101111111111111111111111111111111111111 - 111111111111111111111111111111011111111111111011111111111111111111 - 111111111110111111111111111011111111111111111111111111111111111111 - 111110111111111111111111111111111111111111111110111111111111111110 - 111111111111111111111110111111111110111101111111111111111111111111 - 110111011111111111111111111111111111111111111111111111111011111111 - 111111111111101111111111111111111111110111111111011111111111111111 - 101111110111111011111111011111111111111111111111111110111111111111 - 111111111111111111111111111111110111111111101111111111111111111111* + 111111111111111111111111111111011111111111011111111111111111111111 + 111111111111111111111111101111110111111111111111111111111111111111 + 111111111111111111111110111111111111111111111111111110111011110110 + 111110100110111111111111111111111111110111111111111111111111111111 + 011111111111111111111111111111111110111111111111111111111111111111 + 111111111111111011011111111111111111111111111111111111111101111111 + 111111111111101111111111111111111111111101111111110111011111111111 + 111111111111111101111111111011111111111111111110111111111111111111 + 111011111111111111110111111111111111111111111111101111111111111111* L041166 - 000000000000000000000000000000000000000000000000000000000000000000* -L041232 011111111111111111111111111111111110111111011111111111110111111111* -L041298 101111111111101111111111111111111111111111011111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111* +L041232 111111111111110111111111111111111110111111111101011111111111111111* +L041298 111111111111101111111111111111111111111111111110011111111111111111* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 000000000000000000000000000000000000000000000000000000000000000000* +L041562 111111111111111111111111111111111111111111011111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111111111111111111111111111111111111111111101111111111111111111111* -L042024 011111111111111111111111111111111111111111111101111111110111111111* -L042090 101111111111111111111111101111111111111111111111101111111111111111* +L041958 111111111111111111111111111111111111111101111111111111111111111111* +L042024 000000000000000000000000000000000000000000000000000000000000000000* +L042090 000000000000000000000000000000000000000000000000000000000000000000* L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* -L042288 111111111111111111111111111111111111111101111111111111111111111111* +L042288 111111111111111111111111111111111111111111111111111101111111111111* L042354 000000000000000000000000000000000000000000000000000000000000000000* L042420 000000000000000000000000000000000000000000000000000000000000000000* L042486 000000000000000000000000000000000000000000000000000000000000000000* L042552 000000000000000000000000000000000000000000000000000000000000000000* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111101111011111111111111111111111111111111111111111111111111111111* -L042750 111001111111111111111111111111111111111111111111111111111111111111* -L042816 110111110111111101111111111111111011111111111111111111111111111111* -L042882 111011111011111101111111111111111011111111111111111111111111111111* -L042948 111101111111111110111111111111111111111111111111111111111111111111* -L043014 111111111111111111111111111111101111111111011111111111111111111111* -L043080 000000000000000000000000000000000000000000000000000000000000000000* -L043146 000000000000000000000000000000000000000000000000000000000000000000* +L042684 111101111111111111111111111111101111111111111111111111111111111111* +L042750 111101111111111111111111111111111111111111111111111011111111111111* +L042816 111111111111111111111111111111011111111111111111110111111110111101* +L042882 111111111111111111111111111111101111111111111111111011111110111101* +L042948 111101111111111111111111111111111111111111111111111111111111111110* +L043014 111111111111111011111111111111111111111111111101011111111111111111* +L043080 111111101111111111111111111111111111111111111101011111111111111111* +L043146 111111111111111110111111111111111111111111111110011111101111111111* L043212 000000000000000000000000000000000000000000000000000000000000000000* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 011111111111111111111111111111111111111111011111111111111011111111* -L043476 011111111110111111111111111111111111111111011111111111111111111111* -L043542 101111111111111111111111101111111111111111011111101111111111111111* +L043410 111111110111111111111111111111111111111111111111111111111111111111* +L043476 000000000000000000000000000000000000000000000000000000000000000000* +L043542 000000000000000000000000000000000000000000000000000000000000000000* L043608 000000000000000000000000000000000000000000000000000000000000000000* L043674 000000000000000000000000000000000000000000000000000000000000000000* -L043740 111111111111111111111111111111111111111111111111111101111111111111* +L043740 111111111111111111111101111111111111111111111111111111111111111111* L043806 000000000000000000000000000000000000000000000000000000000000000000* L043872 000000000000000000000000000000000000000000000000000000000000000000* L043938 000000000000000000000000000000000000000000000000000000000000000000* L044004 000000000000000000000000000000000000000000000000000000000000000000* L044070 - 101111111111111111011111111111111111111111111111111111111111111110* -L044136 111111111111111111111111111111111111111111101111111111111111111111* -L044202 011111111111111111111111110111111111111111111111111111110111111111* -L044268 101111111111111111111111011111111111111111111111111111111111111111* + 011111111111111111111111111111111111111111111110111111111111111011* +L044136 111111111111111111111111111111111111111111111111101111111111111111* +L044202 111111111111110111111111111111111111111111111101111111110111111111* +L044268 111111111111111101111111111111111111111111111110111111111111111111* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 111111111111110111111111111111111111111111111111111111111111111111* -L044532 000000000000000000000000000000000000000000000000000000000000000000* +L044466 111111111111111111111111111111110111111111111111011111111111111111* +L044532 110111111111111111111111101011111111111111111111011111111111111111* L044598 000000000000000000000000000000000000000000000000000000000000000000* L044664 000000000000000000000000000000000000000000000000000000000000000000* L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 - 101111111111111111111111111111111111111111111111111111111111111110* -L044862 101111111111111111111110111111111111111111011111111111111111111111* -L044928 011111111111111111111111111111111111111111011011111111110111111111* -L044994 000000000000000000000000000000000000000000000000000000000000000000* -L045060 000000000000000000000000000000000000000000000000000000000000000000* -L045126 000000000000000000000000000000000000000000000000000000000000000000* -L045192 111111011111111111111111111111111111111111111111111111111111111111* -L045258 000000000000000000000000000000000000000000000000000000000000000000* -L045324 000000000000000000000000000000000000000000000000000000000000000000* -L045390 000000000000000000000000000000000000000000000000000000000000000000* -L045456 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111111111110111111111111111011* +L044862 111111111111111111111111111111111111110111111111111111111111111111* +L044928 111111111111111111111111111111111111111111111111111111111111111111* +L044994 111111111111111111111111111111111111111111111111111111111111111111* +L045060 111111111111111111111111111111111111111111111111111111111111111111* +L045126 111111111111111111111111111111111111111111111111111111111111111111* +L045192 111111111111111111111111111111111111111111111111111111111111111111* +L045258 111111111111111111111111111111111111111111111111111111111111111111* +L045324 111111111111111111111111111111111111111111111111111111111111111111* +L045390 111111111111111111111111111111111111111111111111111111111111111111* +L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 - 101111111111111111011111111111111111111111111111111111111111111111* -L045588 111111111101111111111111111111111111111111111110111111111111111111* -L045654 000000000000000000000000000000000000000000000000000000000000000000* -L045720 000000000000000000000000000000000000000000000000000000000000000000* -L045786 000000000000000000000000000000000000000000000000000000000000000000* -L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 111111111111111111111111111101111111111111111111111111111111111111* -L045984 000000000000000000000000000000000000000000000000000000000000000000* -L046050 000000000000000000000000000000000000000000000000000000000000000000* -L046116 000000000000000000000000000000000000000000000000000000000000000000* -L046182 000000000000000000000000000000000000000000000000000000000000000000* + 011111111111111111111111111111111111111111111110111111111111111111* +L045588 111111011111111111101111111111111111111111111111111111111111111111* +L045654 111111111111111111111111111111111111111111111111111111111111111111* +L045720 111111111111111111111111111111111111111111111111111111111111111111* +L045786 111111111111111111111111111111111111111111111111111111111111111111* +L045852 111111111111111111111111111111111111111111111111111111111111111111* +L045918 111111111111111111111011111111111111111111111111011111111111111111* +L045984 111111111111111111111111111111111111111111111111111111111111111111* +L046050 111111111111111111111111111111111111111111111111111111111111111111* +L046116 111111111111111111111111111111111111111111111111111111111111111111* +L046182 111111111111111111111111111111111111111111111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 101111111111111111111101111111111111111111011111111111111111111111* -L046380 011111111111111111111011111111111111111111011111111111110111111111* -L046446 000000000000000000000000000000000000000000000000000000000000000000* -L046512 000000000000000000000000000000000000000000000000000000000000000000* -L046578 000000000000000000000000000000000000000000000000000000000000000000* -L046644 111111111111111111111111111111111111110111111111111111111111111111* -L046710 000000000000000000000000000000000000000000000000000000000000000000* -L046776 000000000000000000000000000000000000000000000000000000000000000000* -L046842 000000000000000000000000000000000000000000000000000000000000000000* -L046908 000000000000000000000000000000000000000000000000000000000000000000* +L046314 111111111101111111111111111111111111111111111111111111111111111111* +L046380 111111111111111111111111111111111111111111111111111111111111111111* +L046446 111111111111111111111111111111111111111111111111111111111111111111* +L046512 111111111111111111111111111111111111111111111111111111111111111111* +L046578 111111111111111111111111111111111111111111111111111111111111111111* +L046644 111111111111111111111111111111111111111111111111111111111111111111* +L046710 111111111111111111111111111111111111111111111111111111111111111111* +L046776 111111111111111111111111111111111111111111111111111111111111111111* +L046842 111111111111111111111111111111111111111111111111111111111111111111* +L046908 111111111111111111111111111111111111111111111111111111111111111111* L046974 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* L047110 11100110011000* -L047124 00101011111110* -L047138 10100110010101* +L047124 00100110011110* +L047138 00100110010100* L047152 00100110011111* -L047166 10100110011000* -L047180 01100110010010* -L047194 11100110010000* -L047208 00100110010011* -L047222 10100110010001* -L047236 00100110010011* -L047250 11100110010100* -L047264 00100110010010* -L047278 00100011110010* -L047292 00100110010011* -L047306 11100110010001* -L047320 00100110011111* +L047166 10100110011001* +L047180 11100110010011* +L047194 00100110010000* +L047208 00100110010010* +L047222 10100110010000* +L047236 11100110010011* +L047250 00010110010101* +L047264 11101111110011* +L047278 00110011110010* +L047292 01000110010010* +L047306 00010110010000* +L047320 11101011111111* NOTE BLOCK 7 * L047334 - 111110111111111111011111111111111111111110111111111111111111111111 - 111111111111111111111111111111111111111111111111111011111111111110 - 111111111111111111111111111111111110111111111111111111111110111111 - 111111111111111111111011101011111111111111111010101111111111111111 - 111111111110111111111111111111101111111111111111111111111111111111 - 111111111111011111111111111111111111011111111111111111111111111111 - 111111011111110111111101111111111111111111111111111111101111110111 - 101111111011111111111111111111111111111011111111111111111111111111 - 111011111111111101111111111110111011111111101111111111111111101111* + 111111111111111111111111111111111111111110011111111111111111111011 + 111111111111111110111111111111110111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111101111110111111111 + 111111101111111111111111101011111111111111111111111111111101111111 + 111111111111111111111011111111111111111111111111111001111111111111 + 111111111111011111111111111111011111011111111111111111111111111111 + 111111111110111111111101111110111101111111111111111111111111111111 + 111111111111111111111111111111111111111111111110111111101111111110 + 101010111011111111011111111111111111110111111111111111111111101111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 111111111101111011111011111111111111111111011111111111111111101111* -L048060 111111111101111111111011111111111111111111011111111111111111101110* -L048126 111111111111111111110111111111111111111111011111111011111111111111* +L047994 011111111111111111111111111111111011111111111111110111111110101111* +L048060 011111111111111111111011111111111011111111111111110111111111101111* +L048126 011111111111111110111111111111110111111111111111111111111111111111* L048192 000000000000000000000000000000000000000000000000000000000000000000* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 111111111111101110111110010111111101011011111111111111111111111011* +L048324 111111111111101111111110010111111110011011111111011111111111111110* L048390 000000000000000000000000000000000000000000000000000000000000000000* L048456 000000000000000000000000000000000000000000000000000000000000000000* L048522 000000000000000000000000000000000000000000000000000000000000000000* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111111111111111111111111111111011111111111111111* +L048720 111111111111111111111111111101111111111111111111111111111111111111* L048786 111111111111111111111111111111111111111111111111111111111111111111* L048852 111111111111111111111111111111111111111111111111111111111111111111* L048918 111111111111111111111111111111111111111111111111111111111111111111* @@ -1000,19 +1001,19 @@ L049248 111111111111111111111111111111111111111111111111111111111111111111* L049314 111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111111111111111111111111111111111101111011111111111111111111111* -L049512 101111111111111011111111111111111111111111011111111111111111111111* -L049578 000000000000000000000000000000000000000000000000000000000000000000* +L049446 101111111111111111111111111111111111111111111111111111111111111111* +L049512 111111111111111111111111111111111111011111111101111111111111111111* +L049578 111101111111111111111111111111111111011111111111111111111101111111* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111111111111111111111111111111111011011111111111111111111111* +L049776 011111111111111111111111111111111111111111111111111111111111111110* L049842 111111111111111111111111111111111111111111111111111111111111111111* L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 - 101111111111111111011111111111111111111111111011111111111111111111* -L050172 111111111111111111111111111101111111111111111111111111111111111111* + 111111111111111111111111111111111111111111111110111101111011111111* +L050172 111111110111111111111111111111111111111111111111111111111111111111* L050238 111111111111111111111111111111111111111111111111111111111111111111* L050304 111111111111111111111111111111111111111111111111111111111111111111* L050370 111111111111111111111111111111111111111111111111111111111111111111* @@ -1023,19 +1024,19 @@ L050634 111111111111111111111111111111111111111111111111111111111111111111* L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 - 111111111111111111111111111111111111111111110111111111111111111111* -L050898 111111101111111111111111111111111011111111111111111111111111111111* + 111111111111111111111111111111111111111111111111111111110111111111* +L050898 111110111111111111101111111111111111111111111111111111111111111111* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111111111111111111111111111111011111111110011111011111111111111111* -L051294 111101111111111111111111111111011111111111011111011111111111111111* -L051360 111111111111111111111111111101011111111111011111111111111111111111* -L051426 110111111011111111111111111111111111111111011111111111101111111111* +L051228 011111111111111111111111111101111111111110111111111111111111110111* +L051294 011111111111111111111111111101111111111111011111111111111111110111* +L051360 011111110111111111111111111111111111111111111111111111111111110111* +L051426 010111111110111111111111111111111111111111111111111111101111111111* L051492 000000000000000000000000000000000000000000000000000000000000000000* L051558 - 011111111111111111011111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111111101111101111111111111* L051624 111111111111111111111111111111111111111111111111111111111111111111* L051690 111111111111111111111111111111111111111111111111111111111111111111* L051756 111111111111111111111111111111111111111111111111111111111111111111* @@ -1047,13 +1048,13 @@ L052086 111111111111111111111111111111111111111111111111111111111111111111* L052152 111111111111111111111111111111111111111111111111111111111111111111* L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 - 101111111111111111111111111111111111111111111011111111111111111111* -L052350 111111111111111111111111111111111111111111111101111111111110111111* + 111111111111111111111111111111111111111111111110111111111011111111* +L052350 111111101111111111111111111111011111111111111111111111111111111111* L052416 111111111111111111111111111111111111111111111111111111111111111111* L052482 111111111111111111111111111111111111111111111111111111111111111111* L052548 111111111111111111111111111111111111111111111111111111111111111111* L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 101111111111111111111111111111111111111111011111111111111111111111* +L052680 011111111111111111111111111111111111111111111110111111111111111111* L052746 111111111111111111111111111111111111111111111111111111111111111111* L052812 111111111111111111111111111111111111111111111111111111111111111111* L052878 111111111111111111111111111111111111111111111111111111111111111111* @@ -1075,10 +1076,10 @@ L053736 000000000000000000000000000000000000000000000000000000000000000000* L053868 0010* L053872 11100110011100* -L053886 01101011111110* +L053886 01101011110010* L053900 00010110010001* -L053914 11101011111111* -L053928 11100110010000* +L053914 11101011110011* +L053928 10100110010000* L053942 01000110011110* L053956 00010110010101* L053970 11100011110011* @@ -1109,6 +1110,6 @@ E1 10000010 1 * -C42BE* +CF9B2* U00000000000000000000000000000000* -FD2E +11B6 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 199cdfa..2bfa1de 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 7/9/15; -TIME = 18:49:07; +DATE = 9/24/15; +TIME = 16:21:08; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,26 +76,27 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -SIZE_0_ = pin,70,-,G,-; -A_30_ = pin,5,-,B,-; -SIZE_1_ = pin,79,-,H,-; -A_29_ = pin,6,-,B,-; A_28_ = pin,15,-,C,-; -A_31_ = pin,4,-,B,-; A_27_ = pin,16,-,C,-; +SIZE_1_ = pin,79,-,H,-; A_26_ = pin,17,-,C,-; A_25_ = pin,18,-,C,-; +A_31_ = pin,4,-,B,-; A_24_ = pin,19,-,C,-; +A_23_ = pin,85,-,H,-; +A_22_ = pin,84,-,H,-; +A_21_ = pin,94,-,A,-; IPL_2_ = pin,68,-,G,-; -FC_1_ = pin,58,-,F,-; -AS_030 = pin,82,-,H,-; -AS_000 = pin,42,-,E,-; +A_20_ = pin,93,-,A,-; A_19_ = pin,97,-,A,-; +FC_1_ = pin,58,-,F,-; A_18_ = pin,95,-,A,-; -DS_030 = pin,98,-,A,-; +AS_030 = pin,82,-,H,-; A_17_ = pin,59,-,F,-; -UDS_000 = pin,32,-,D,-; +AS_000 = pin,42,-,E,-; A_16_ = pin,96,-,A,-; +DS_030 = pin,98,-,A,-; +UDS_000 = pin,32,-,D,-; LDS_000 = pin,31,-,D,-; A1 = pin,60,-,F,-; nEXP_SPACE = pin,14,-,-,-; @@ -107,13 +108,13 @@ CLK_000 = pin,11,-,-,-; CLK_OSZI = pin,61,-,-,-; CLK_DIV_OUT = pin,65,-,G,-; CLK_EXP = pin,10,-,B,-; -FPU_CS = pin,78,-,H,-; -FPU_SENSE = pin,91,-,A,-; IPL_1_ = pin,56,-,F,-; -DTACK = pin,30,-,D,-; +FPU_CS = pin,78,-,H,-; IPL_0_ = pin,67,-,G,-; -AVEC = pin,92,-,A,-; +FPU_SENSE = pin,91,-,A,-; FC_0_ = pin,57,-,F,-; +DTACK = pin,30,-,D,-; +AVEC = pin,92,-,A,-; VPA = pin,36,-,-,-; RST = pin,86,-,-,-; AMIGA_ADDR_ENABLE = pin,33,-,D,-; @@ -121,6 +122,9 @@ AMIGA_BUS_DATA_DIR = pin,48,-,E,-; AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; CIIN = pin,47,-,E,-; +SIZE_0_ = pin,70,-,G,-; +A_30_ = pin,5,-,B,-; +A_29_ = pin,6,-,B,-; IPL_030_2_ = pin,9,-,B,-; RW_000 = pin,80,-,H,-; A0 = pin,69,-,G,-; @@ -133,78 +137,79 @@ E = pin,66,-,G,-; VMA = pin,35,-,D,-; RESET = pin,3,-,B,-; RW = pin,71,-,G,-; -N_165 = node,-,-,F,6; -cpu_est_0_ = node,-,-,D,6; -cpu_est_1_ = node,-,-,D,13; -inst_AS_000_INT = node,-,-,C,1; -SM_AMIGA_5_ = node,-,-,F,4; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,G,14; +cpu_est_0_ = node,-,-,C,5; +cpu_est_1_ = node,-,-,G,5; +inst_AS_000_INT = node,-,-,A,1; +SM_AMIGA_5_ = node,-,-,F,12; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,3; inst_AS_030_D0 = node,-,-,H,5; -inst_nEXP_SPACE_D0reg = node,-,-,G,5; -inst_DS_030_D0 = node,-,-,D,10; -inst_AS_030_000_SYNC = node,-,-,C,8; +inst_nEXP_SPACE_D0reg = node,-,-,F,0; +inst_DS_030_D0 = node,-,-,D,7; +inst_AS_030_000_SYNC = node,-,-,F,13; inst_BGACK_030_INT_D = node,-,-,H,13; inst_AS_000_DMA = node,-,-,A,8; -inst_DS_000_DMA = node,-,-,A,13; -CYCLE_DMA_0_ = node,-,-,A,10; -CYCLE_DMA_1_ = node,-,-,A,6; +inst_DS_000_DMA = node,-,-,A,5; +CYCLE_DMA_0_ = node,-,-,A,2; +CYCLE_DMA_1_ = node,-,-,A,13; SIZE_DMA_0_ = node,-,-,G,6; SIZE_DMA_1_ = node,-,-,G,2; -inst_VPA_D = node,-,-,F,13; -inst_UDS_000_INT = node,-,-,F,5; -inst_LDS_000_INT = node,-,-,B,9; -inst_CLK_OUT_PRE_D = node,-,-,G,15; -inst_DTACK_D0 = node,-,-,D,15; -inst_CLK_OUT_PRE_50 = node,-,-,A,9; -inst_CLK_000_D1 = node,-,-,F,8; -inst_CLK_000_D0 = node,-,-,G,13; -inst_CLK_000_PE = node,-,-,D,9; -CLK_000_P_SYNC_9_ = node,-,-,C,2; -inst_CLK_000_NE = node,-,-,G,9; +inst_VPA_D = node,-,-,D,13; +inst_UDS_000_INT = node,-,-,G,13; +inst_LDS_000_INT = node,-,-,G,9; +inst_CLK_OUT_PRE_D = node,-,-,E,13; +inst_DTACK_D0 = node,-,-,B,6; +inst_CLK_OUT_PRE_50 = node,-,-,E,9; +inst_CLK_000_D1 = node,-,-,D,9; +inst_CLK_000_D0 = node,-,-,B,2; +inst_CLK_000_PE = node,-,-,C,4; +CLK_000_P_SYNC_9_ = node,-,-,A,7; +inst_CLK_000_NE = node,-,-,F,4; CLK_000_N_SYNC_11_ = node,-,-,H,6; -cpu_est_2_ = node,-,-,D,2; -IPL_D0_0_ = node,-,-,B,7; -IPL_D0_1_ = node,-,-,C,13; -IPL_D0_2_ = node,-,-,B,13; -SM_AMIGA_3_ = node,-,-,F,12; -inst_CLK_000_NE_D0 = node,-,-,B,15; +cpu_est_2_ = node,-,-,C,12; +IPL_D0_0_ = node,-,-,D,3; +IPL_D0_1_ = node,-,-,D,14; +IPL_D0_2_ = node,-,-,G,11; +SM_AMIGA_3_ = node,-,-,C,8; +inst_CLK_000_NE_D0 = node,-,-,E,8; SM_AMIGA_0_ = node,-,-,F,9; inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,G,10; -SM_AMIGA_6_ = node,-,-,C,4; -RST_DLY_0_ = node,-,-,B,10; -RST_DLY_1_ = node,-,-,A,1; +SM_AMIGA_6_ = node,-,-,F,5; +RST_DLY_0_ = node,-,-,C,6; +RST_DLY_1_ = node,-,-,B,13; RST_DLY_2_ = node,-,-,B,5; -RST_DLY_3_ = node,-,-,B,0; -RST_DLY_4_ = node,-,-,B,12; -RST_DLY_5_ = node,-,-,A,12; -RST_DLY_6_ = node,-,-,B,11; -RST_DLY_7_ = node,-,-,A,5; -CLK_000_P_SYNC_0_ = node,-,-,D,11; -CLK_000_P_SYNC_1_ = node,-,-,G,11; -CLK_000_P_SYNC_2_ = node,-,-,B,3; -CLK_000_P_SYNC_3_ = node,-,-,C,9; -CLK_000_P_SYNC_4_ = node,-,-,B,4; -CLK_000_P_SYNC_5_ = node,-,-,E,9; -CLK_000_P_SYNC_6_ = node,-,-,E,5; -CLK_000_P_SYNC_7_ = node,-,-,G,7; -CLK_000_P_SYNC_8_ = node,-,-,C,5; -CLK_000_N_SYNC_0_ = node,-,-,D,7; -CLK_000_N_SYNC_1_ = node,-,-,A,15; -CLK_000_N_SYNC_2_ = node,-,-,A,11; -CLK_000_N_SYNC_3_ = node,-,-,A,7; -CLK_000_N_SYNC_4_ = node,-,-,D,3; -CLK_000_N_SYNC_5_ = node,-,-,A,3; -CLK_000_N_SYNC_6_ = node,-,-,D,14; -CLK_000_N_SYNC_7_ = node,-,-,E,8; -CLK_000_N_SYNC_8_ = node,-,-,A,14; -CLK_000_N_SYNC_9_ = node,-,-,G,3; +RST_DLY_3_ = node,-,-,C,9; +RST_DLY_4_ = node,-,-,C,14; +RST_DLY_5_ = node,-,-,B,9; +RST_DLY_6_ = node,-,-,C,2; +RST_DLY_7_ = node,-,-,C,10; +CLK_000_P_SYNC_0_ = node,-,-,D,10; +CLK_000_P_SYNC_1_ = node,-,-,C,11; +CLK_000_P_SYNC_2_ = node,-,-,B,11; +CLK_000_P_SYNC_3_ = node,-,-,C,7; +CLK_000_P_SYNC_4_ = node,-,-,D,6; +CLK_000_P_SYNC_5_ = node,-,-,F,10; +CLK_000_P_SYNC_6_ = node,-,-,A,3; +CLK_000_P_SYNC_7_ = node,-,-,A,14; +CLK_000_P_SYNC_8_ = node,-,-,A,10; +CLK_000_N_SYNC_0_ = node,-,-,F,6; +CLK_000_N_SYNC_1_ = node,-,-,G,7; +CLK_000_N_SYNC_2_ = node,-,-,G,3; +CLK_000_N_SYNC_3_ = node,-,-,B,7; +CLK_000_N_SYNC_4_ = node,-,-,B,3; +pos_clk_un29_clk_000_ne_d0_i_n = node,-,-,D,2; +CLK_000_N_SYNC_5_ = node,-,-,B,14; +CLK_000_N_SYNC_6_ = node,-,-,A,6; +CLK_000_N_SYNC_7_ = node,-,-,B,10; +CLK_000_N_SYNC_8_ = node,-,-,G,14; +CLK_000_N_SYNC_9_ = node,-,-,F,2; CLK_000_N_SYNC_10_ = node,-,-,H,2; -inst_CLK_030_H = node,-,-,A,2; -SM_AMIGA_1_ = node,-,-,F,1; -SM_AMIGA_4_ = node,-,-,F,10; -SM_AMIGA_2_ = node,-,-,F,2; -inst_DS_000_ENABLE = node,-,-,C,12; -SM_AMIGA_i_7_ = node,-,-,F,0; +inst_CLK_030_H = node,-,-,A,9; +SM_AMIGA_1_ = node,-,-,C,1; +SM_AMIGA_4_ = node,-,-,F,1; +SM_AMIGA_2_ = node,-,-,C,13; +inst_DS_000_ENABLE = node,-,-,A,12; +SM_AMIGA_i_7_ = node,-,-,F,8; +CIIN_0 = node,-,-,E,5; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 96b072d..4aee406 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -2388,6 +2388,604 @@ 14 A_28_ 1 -1 -1 1 4 14 -1 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 376 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 367 6 1 6 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 371 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21 + 65 E 5 373 6 0 65 -1 5 0 21 + 80 DSACK1 5 372 7 0 80 -1 4 0 21 + 82 BGACK_030 5 369 7 0 82 -1 3 0 21 + 34 VMA 5 374 3 0 34 -1 3 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 368 3 0 28 -1 2 0 21 + 2 RESET 5 375 1 0 2 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 375 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 2 5 0 1 2 3 5 -1 -1 1 0 21 + 317 inst_CLK_000_PE 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21 + 326 inst_CLK_000_NE_D0 3 -1 1 4 2 3 5 6 -1 -1 1 0 21 + 364 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 14 0 21 + 373 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 325 SM_AMIGA_3_ 3 -1 2 3 0 2 5 -1 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 359 SM_AMIGA_1_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 296 SM_AMIGA_5_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 2 0 21 + 293 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 333 RST_DLY_3_ 3 -1 2 2 1 2 -1 -1 6 0 21 + 332 RST_DLY_2_ 3 -1 2 2 1 2 -1 -1 5 0 21 + 361 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 335 RST_DLY_5_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 4 0 21 + 374 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 362 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 360 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 336 RST_DLY_6_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 329 SM_AMIGA_6_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 337 RST_DLY_7_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 334 RST_DLY_4_ 3 -1 2 2 1 2 -1 -1 2 1 21 + 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 316 inst_CLK_000_D0 3 -1 6 2 3 5 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 358 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 372 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 376 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 363 pos_clk_un23_clk_000_ne_d0_0_n 3 -1 2 1 5 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 357 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_9_ 3 -1 5 1 7 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_5_ 3 -1 4 1 1 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_4_ 3 -1 3 1 4 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_3_ 3 -1 1 1 3 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_1_ 3 -1 4 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_6_ 3 -1 3 1 1 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_5_ 3 -1 1 1 3 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_4_ 3 -1 2 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 2 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 6 1 3 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 5 1 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 6 1 6 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 6 1 7 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 6 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 1 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 59 A1 1 -1 -1 2 0 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 376 6 2 6 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 367 6 1 0 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 371 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21 + 65 E 5 373 6 0 65 -1 5 0 21 + 80 DSACK1 5 372 7 0 80 -1 4 0 21 + 82 BGACK_030 5 369 7 0 82 -1 3 0 21 + 34 VMA 5 374 3 0 34 -1 3 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 368 3 0 28 -1 2 0 21 + 2 RESET 5 375 1 0 2 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 375 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21 + 317 inst_CLK_000_PE 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 5 3 4 5 6 7 -1 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 1 4 1 2 3 5 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 4 0 3 5 6 -1 -1 1 0 21 + 364 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 13 0 21 + 373 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 325 SM_AMIGA_3_ 3 -1 2 3 2 5 6 -1 -1 5 0 21 + 294 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 296 SM_AMIGA_5_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 334 RST_DLY_3_ 3 -1 2 2 1 2 -1 -1 6 0 21 + 333 RST_DLY_2_ 3 -1 2 2 1 2 -1 -1 5 0 21 + 362 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 336 RST_DLY_5_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 332 RST_DLY_1_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21 + 374 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 363 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21 + 361 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 360 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 337 RST_DLY_6_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 329 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 338 RST_DLY_7_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 335 RST_DLY_4_ 3 -1 2 2 1 2 -1 -1 2 1 21 + 327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 326 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21 + 316 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 372 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 376 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 331 N_264_i 3 -1 2 1 5 -1 -1 2 0 21 + 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 4 1 3 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 1 1 4 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 4 1 1 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 1 1 4 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 3 1 2 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 4 1 3 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 3 1 4 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 4 1 0 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 3 1 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 6 1 6 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 0 3 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 6 1 2 3 5 6 7 40 -1 1 0 21 + 79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 377 6 2 3 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 368 6 1 0 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21 + 65 E 5 374 6 0 65 -1 5 0 21 + 80 DSACK1 5 373 7 0 80 -1 4 0 21 + 82 BGACK_030 5 370 7 0 82 -1 3 0 21 + 34 VMA 5 375 3 0 34 -1 3 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 369 3 0 28 -1 2 0 21 + 2 RESET 5 376 1 0 2 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 370 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 376 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21 + 317 inst_CLK_000_PE 3 -1 2 6 0 1 2 3 5 7 -1 -1 1 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21 + 296 SM_AMIGA_5_ 3 -1 1 5 1 3 5 6 7 -1 -1 3 0 21 + 298 inst_AS_030_D0 3 -1 7 5 3 4 5 6 7 -1 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 0 4 1 2 3 5 -1 -1 1 0 21 + 364 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 13 0 21 + 374 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 325 SM_AMIGA_3_ 3 -1 2 3 2 3 5 -1 -1 5 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 361 SM_AMIGA_4_ 3 -1 3 3 2 3 5 -1 -1 3 0 21 + 329 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 326 inst_CLK_000_NE_D0 3 -1 5 3 2 3 6 -1 -1 1 0 21 + 316 inst_CLK_000_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 333 RST_DLY_3_ 3 -1 1 2 1 2 -1 -1 6 0 21 + 332 RST_DLY_2_ 3 -1 2 2 1 2 -1 -1 5 0 21 + 362 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 335 RST_DLY_5_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21 + 375 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 360 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 336 RST_DLY_6_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 337 RST_DLY_7_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 334 RST_DLY_4_ 3 -1 1 2 1 2 -1 -1 2 1 21 + 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 309 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 373 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 368 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 363 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 365 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 N_203_i 3 -1 2 1 5 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 4 1 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 4 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 377 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 368 6 1 6 68 -1 3 0 21 + 97 DS_030 5 -1 0 1 3 97 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21 + 65 E 5 374 6 0 65 -1 5 0 21 + 80 DSACK1 5 373 7 0 80 -1 4 0 21 + 82 BGACK_030 5 370 7 0 82 -1 3 0 21 + 34 VMA 5 375 3 0 34 -1 3 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 369 3 0 28 -1 2 0 21 + 2 RESET 5 376 1 0 2 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 370 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 376 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21 + 299 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21 + 319 inst_CLK_000_NE 3 -1 5 5 1 2 3 4 5 -1 -1 1 0 21 + 317 inst_CLK_000_PE 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 + 298 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21 + 364 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 13 0 21 + 374 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21 + 325 SM_AMIGA_3_ 3 -1 2 3 0 2 5 -1 -1 5 0 21 + 294 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 5 0 21 + 321 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 360 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 296 SM_AMIGA_5_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 326 inst_CLK_000_NE_D0 3 -1 4 3 2 3 6 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 2 5 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 333 RST_DLY_3_ 3 -1 2 2 1 2 -1 -1 6 0 21 + 332 RST_DLY_2_ 3 -1 1 2 1 2 -1 -1 5 0 21 + 362 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 335 RST_DLY_5_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 311 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 4 0 21 + 375 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 363 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 361 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 336 RST_DLY_6_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 2 2 1 2 -1 -1 3 0 21 + 329 SM_AMIGA_6_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 337 RST_DLY_7_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 334 RST_DLY_4_ 3 -1 2 2 1 2 -1 -1 2 1 21 + 328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 295 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 316 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21 + 315 inst_CLK_000_D1 3 -1 3 2 3 5 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 1 2 2 3 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 + 372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 373 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 368 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 365 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 352 pos_clk_un29_clk_000_ne_d0_i_n 3 -1 3 1 5 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 5 1 7 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 6 1 5 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_4_ 3 -1 1 1 1 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_4_ 3 -1 3 1 5 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_3_ 3 -1 2 1 3 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_2_ 3 -1 1 1 2 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_0_ 3 -1 3 1 2 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 CLK_000_N_SYNC_11_ 3 -1 7 1 5 -1 -1 1 0 21 + 318 CLK_000_P_SYNC_9_ 3 -1 0 1 2 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 1 7 -1 -1 1 0 21 + 300 inst_DS_030_D0 3 -1 3 1 6 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 1 7 63 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A1 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 3 A_31_ 1 -1 -1 1 4 3 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index d02df1f..ec03198 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,29 +8,30 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Thu Jul 09 18:49:07 2015 +; DATE Thu Sep 24 16:21:08 2015 -Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 -Pin 5 A_30_ -Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 -Pin 6 A_29_ Pin 15 A_28_ -Pin 4 A_31_ Pin 16 A_27_ +Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 Pin 17 A_26_ Pin 18 A_25_ +Pin 4 A_31_ Pin 19 A_24_ +Pin 85 A_23_ +Pin 84 A_22_ +Pin 94 A_21_ Pin 68 IPL_2_ -Pin 58 FC_1_ -Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 -Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203 +Pin 93 A_20_ Pin 97 A_19_ +Pin 58 FC_1_ Pin 95 A_18_ -Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101 +Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 Pin 59 A_17_ -Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 +Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203 Pin 96 A_16_ +Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101 +Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 Pin 60 A1 Pin 14 nEXP_SPACE @@ -42,13 +43,13 @@ Pin 11 CLK_000 Pin 61 CLK_OSZI Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247 Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127 -Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 -Pin 91 FPU_SENSE Pin 56 IPL_1_ -Pin 30 DTACK +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 Pin 67 IPL_0_ -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 91 FPU_SENSE Pin 57 FC_0_ +Pin 30 DTACK +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 36 VPA Pin 86 RST Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 @@ -56,19 +57,21 @@ Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149 Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179 Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 -Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 128 +Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 +Pin 5 A_30_ +Pin 6 A_29_ +Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 Pin 69 A0 Reg ; S6=1 S9=1 Pair 257 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 134 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283 Pin 66 E Reg ; S6=1 S9=1 Pair 251 Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 -Pin 3 RESET Reg ; S6=1 S9=1 Pair 146 +Pin 3 RESET Reg ; S6=1 S9=1 Pair 125 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 -Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1 Node 281 RN_AS_030 Comb ; S6=1 S9=1 Node 203 RN_AS_000 Comb ; S6=1 S9=1 @@ -76,89 +79,91 @@ Node 101 RN_DS_030 Comb ; S6=1 S9=1 Node 185 RN_UDS_000 Comb ; S6=1 S9=1 Node 191 RN_LDS_000 Comb ; S6=1 S9=1 Node 197 RN_BERR Comb ; S6=1 S9=1 -Node 128 RN_IPL_030_2_ Reg ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 +Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 269 RN_RW_000 Reg ; S6=1 S9=1 Node 257 RN_A0 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 -Node 134 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 Node 283 RN_DSACK1 Reg ; S6=1 S9=1 Node 251 RN_E Reg ; S6=1 S9=1 Node 173 RN_VMA Reg ; S6=1 S9=1 -Node 146 RN_RESET Reg ; S6=1 S9=1 +Node 125 RN_RESET Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 -Node 230 N_165 Comb ; S6=1 S9=1 -Node 182 cpu_est_0_ Reg ; S6=1 S9=1 -Node 193 cpu_est_1_ Reg ; S6=1 S9=1 -Node 151 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 227 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 266 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 157 cpu_est_0_ Reg ; S6=1 S9=1 +Node 253 cpu_est_1_ Reg ; S6=1 S9=1 +Node 103 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 239 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 154 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 Node 277 inst_AS_030_D0 Reg ; S6=1 S9=1 -Node 253 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1 -Node 188 inst_DS_030_D0 Reg ; S6=1 S9=1 -Node 161 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 221 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1 +Node 184 inst_DS_030_D0 Reg ; S6=1 S9=1 +Node 241 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 Node 113 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 116 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 110 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 109 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 104 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 121 CYCLE_DMA_1_ Reg ; S6=1 S9=1 Node 254 SIZE_DMA_0_ Reg ; S6=1 S9=1 Node 248 SIZE_DMA_1_ Reg ; S6=1 S9=1 -Node 241 inst_VPA_D Reg ; S6=1 S9=1 -Node 229 inst_UDS_000_INT Reg ; S6=1 S9=1 -Node 139 inst_LDS_000_INT Reg ; S6=1 S9=1 -Node 268 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 196 inst_DTACK_D0 Reg ; S6=1 S9=1 -Node 115 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 233 inst_CLK_000_D1 Reg ; S6=1 S9=1 -Node 265 inst_CLK_000_D0 Reg ; S6=1 S9=1 -Node 187 inst_CLK_000_PE Reg ; S6=1 S9=1 -Node 152 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 -Node 259 inst_CLK_000_NE Reg ; S6=1 S9=1 +Node 193 inst_VPA_D Reg ; S6=1 S9=1 +Node 265 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 259 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 217 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 134 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 211 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 187 inst_CLK_000_D1 Reg ; S6=1 S9=1 +Node 128 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 155 inst_CLK_000_PE Reg ; S6=1 S9=1 +Node 112 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 +Node 227 inst_CLK_000_NE Reg ; S6=1 S9=1 Node 278 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1 -Node 176 cpu_est_2_ Reg ; S6=1 S9=1 -Node 136 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 169 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 145 IPL_D0_2_ Reg ; S6=1 S9=1 -Node 239 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 148 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 +Node 167 cpu_est_2_ Reg ; S6=1 S9=1 +Node 178 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 194 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 262 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 161 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 209 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 Node 235 SM_AMIGA_0_ Reg ; S6=1 S9=1 Node 260 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 155 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 140 RST_DLY_0_ Reg ; S6=1 S9=1 -Node 103 RST_DLY_1_ Reg ; S6=1 S9=1 +Node 229 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 158 RST_DLY_0_ Reg ; S6=1 S9=1 +Node 145 RST_DLY_1_ Reg ; S6=1 S9=1 Node 133 RST_DLY_2_ Reg ; S6=1 S9=1 -Node 125 RST_DLY_3_ Reg ; S6=1 S9=1 -Node 143 RST_DLY_4_ Reg ; S6=1 S9=1 -Node 119 RST_DLY_5_ Reg ; S6=1 S9=1 -Node 142 RST_DLY_6_ Reg ; S6=1 S9=1 -Node 109 RST_DLY_7_ Reg ; S6=1 S9=1 -Node 190 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 -Node 262 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 -Node 130 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 -Node 163 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 -Node 131 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 -Node 211 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 -Node 205 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 -Node 256 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 -Node 157 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 -Node 184 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 -Node 124 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 -Node 118 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 -Node 112 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 -Node 178 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 -Node 106 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 -Node 194 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 -Node 209 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 -Node 122 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 -Node 250 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 +Node 163 RST_DLY_3_ Reg ; S6=1 S9=1 +Node 170 RST_DLY_4_ Reg ; S6=1 S9=1 +Node 139 RST_DLY_5_ Reg ; S6=1 S9=1 +Node 152 RST_DLY_6_ Reg ; S6=1 S9=1 +Node 164 RST_DLY_7_ Reg ; S6=1 S9=1 +Node 188 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 +Node 166 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 +Node 142 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 +Node 160 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 +Node 182 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 +Node 236 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 +Node 106 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 +Node 122 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 +Node 116 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 +Node 230 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 +Node 256 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 +Node 250 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 +Node 136 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 +Node 130 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 +Node 176 pos_clk_un29_clk_000_ne_d0_i_n Comb ; S6=1 S9=1 +Node 146 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 +Node 110 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 +Node 140 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 +Node 266 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 +Node 224 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1 -Node 104 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 223 SM_AMIGA_1_ Reg ; S6=1 S9=1 -Node 236 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 224 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 167 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 221 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 115 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 151 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 223 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 169 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 119 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 233 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 205 CIIN_0 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index dbc77c7..df6a884 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Thu Jul 09 18:49:07 2015 -End : Thu Jul 09 18:49:07 2015 $$$ Elapsed time: 00:00:00 +Start: Thu Sep 24 16:21:08 2015 +End : Thu Sep 24 16:21:08 2015 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,33 +21,33 @@ Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 16 | 16 => 100% | 8 | 6 => 75% | 33 | 30 => 90% - 1.| 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 29 => 87% - 2 | 16 | 9 | 9 => 100% | 8 | 7 => 87% | 33 | 28 => 84% - 3 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 28 => 84% - 4 | 16 | 7 | 7 => 100% | 8 | 4 => 50% | 33 | 27 => 81% - 5 | 16 | 11 | 11 => 100% | 8 | 5 => 62% | 33 | 28 => 84% - 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 27 => 81% - 7 | 16 | 10 | 10 => 100% | 8 | 6 => 75% | 33 | 31 => 93% + 0 | 16 | 14 | 14 => 100% | 8 | 8 => 100% | 33 | 27 => 81% + 1 | 16 | 15 | 15 => 100% | 8 | 8 => 100% | 33 | 28 => 84% + 2 | 16 | 15 | 15 => 100% | 8 | 7 => 87% | 33 | 31 => 93% + 3 | 16 | 14 | 14 => 100% | 8 | 8 => 100% | 33 | 29 => 87% + 4 | 16 | 8 | 8 => 100% | 8 | 4 => 50% | 33 | 31 => 93% + 5 | 16 | 11 | 11 => 100% | 8 | 5 => 62% | 33 | 30 => 90% + 6 | 16 | 15 | 15 => 100% | 8 | 7 => 87% | 33 | 30 => 90% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 31 => 93% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 28.50 => 86% + | Avg number of array inputs in used blocks : 29.63 => 89% -* Input/Clock Signal count: 28 -> placed: 28 = 100% +* Input/Clock Signal count: 32 -> placed: 32 = 100% Resources Available Used ----------------------------------------------------------------- Input Pins : 2 2 => 100% - I/O Pins : 64 51 => 79% + I/O Pins : 64 55 => 85% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 8 => 100% - Macrocells : 128 101 => 78% - PT Clusters : 128 59 => 46% + Macrocells : 128 102 => 79% + PT Clusters : 128 60 => 46% - Single PT Clusters : 128 53 => 41% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 1250] Route [ 0] +* Attempts: Place [ 146] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -57,9 +57,9 @@ _|____|____|____|_______________|____|_____________|___|________________ | | | +- Signal-to-Pin Assignment | | | | Fanout to Logic Blocks Signal Name ___|__|__|____|____________________________________________________________ - 1| 6| IO| 69|=> .1..|.5..| A0 + 1| 6| IO| 69|=> ....|..6.| A0 |=> Paired w/: RN_A0 - 2| 5|INP| 60|=> ....|..6.| A1 + 2| 5|INP| 60|=> ..2.|..6.| A1 3| 3|OUT| 33|=> ....|....| AMIGA_ADDR_ENABLE 4| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 5| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH @@ -67,161 +67,166 @@ ___|__|__|____|____________________________________________________________ 7| 4| IO| 42|=> 0...|4..7| AS_000 8| 7| IO| 82|=> ....|4..7| AS_030 9| 0|OUT| 92|=> ....|....| AVEC - 10| 0|INP| 96|=> ..2.|4..7| A_16_ - 11| 5|INP| 59|=> ..2.|4..7| A_17_ - 12| 0|INP| 95|=> ..2.|4..7| A_18_ - 13| 0|INP| 97|=> ..2.|4..7| A_19_ - 14| 2|INP| 19|=> ....|4...| A_24_ - 15| 2|INP| 18|=> ....|4...| A_25_ - 16| 2|INP| 17|=> ....|4...| A_26_ - 17| 2|INP| 16|=> ....|4...| A_27_ - 18| 2|INP| 15|=> ....|4...| A_28_ - 19| 1|INP| 6|=> ....|4...| A_29_ - 20| 1|INP| 5|=> ....|4...| A_30_ - 21| 1|INP| 4|=> ....|4...| A_31_ - 22| 4| IO| 41|=> ..2.|.5.7| BERR - 23| 3|INP| 28|=> ....|4..7| BGACK_000 - 24| 7| IO| 83|=> ....|....| BGACK_030 + 10| 0|INP| 96|=> ....|45.7| A_16_ + 11| 5|INP| 59|=> ....|45.7| A_17_ + 12| 0|INP| 95|=> ....|45.7| A_18_ + 13| 0|INP| 97|=> ....|45.7| A_19_ + 14| 0|INP| 93|=> ....|4...| A_20_ + 15| 0|INP| 94|=> ....|4...| A_21_ + 16| 7|INP| 84|=> ....|4...| A_22_ + 17| 7|INP| 85|=> ....|4...| A_23_ + 18| 2|INP| 19|=> ....|4...| A_24_ + 19| 2|INP| 18|=> ....|4...| A_25_ + 20| 2|INP| 17|=> ....|4...| A_26_ + 21| 2|INP| 16|=> ....|4...| A_27_ + 22| 2|INP| 15|=> ....|4...| A_28_ + 23| 1|INP| 6|=> ....|4...| A_29_ + 24| 1|INP| 5|=> ....|4...| A_30_ + 25| 1|INP| 4|=> ....|4...| A_31_ + 26| 4| IO| 41|=> 0.2.|.5.7| BERR + 27| 3|INP| 28|=> ....|4..7| BGACK_000 + 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 - 25| 3| IO| 29|=> ....|....| BG_000 + 29| 3| IO| 29|=> ....|....| BG_000 |=> Paired w/: RN_BG_000 - 26| 2|INP| 21|=> ...3|....| BG_030 - 27| 4|OUT| 47|=> ....|....| CIIN - 28| +|INP| 11|=> ....|..6.| CLK_000 - 29| 3|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_ - 30| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_ - 31| 7|NOD| . |=> ....|..6.| CLK_000_N_SYNC_11_ - 32| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_1_ - 33| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_2_ - 34| 0|NOD| . |=> ...3|....| CLK_000_N_SYNC_3_ - 35| 3|NOD| . |=> 0...|....| CLK_000_N_SYNC_4_ - 36| 0|NOD| . |=> ...3|....| CLK_000_N_SYNC_5_ - 37| 3|NOD| . |=> ....|4...| CLK_000_N_SYNC_6_ - 38| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_ - 39| 0|NOD| . |=> ....|..6.| CLK_000_N_SYNC_8_ - 40| 6|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ - 41| 3|NOD| . |=> ....|..6.| CLK_000_P_SYNC_0_ - 42| 6|NOD| . |=> .1..|....| CLK_000_P_SYNC_1_ - 43| 1|NOD| . |=> ..2.|....| CLK_000_P_SYNC_2_ - 44| 2|NOD| . |=> .1..|....| CLK_000_P_SYNC_3_ - 45| 1|NOD| . |=> ....|4...| CLK_000_P_SYNC_4_ - 46| 4|NOD| . |=> ....|4...| CLK_000_P_SYNC_5_ - 47| 4|NOD| . |=> ....|..6.| CLK_000_P_SYNC_6_ - 48| 6|NOD| . |=> ..2.|....| CLK_000_P_SYNC_7_ - 49| 2|NOD| . |=> ..2.|....| CLK_000_P_SYNC_8_ - 50| 2|NOD| . |=> ...3|....| CLK_000_P_SYNC_9_ - 51| +|INP| 64|=> 01..|...7| CLK_030 - 52| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 53| 1|OUT| 10|=> ....|....| CLK_EXP - 54| +|Cin| 61|=> ....|....| CLK_OSZI - 55| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ - 56| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ - 57| 7| IO| 81|=> ....|....| DSACK1 + 30| 2|INP| 21|=> ...3|....| BG_030 + 31| 4|OUT| 47|=> ....|....| CIIN + 32| 4|NOD| . |=> ....|4...| CIIN_0 + 33| +|INP| 11|=> .1..|....| CLK_000 + 34| 5|NOD| . |=> ....|..6.| CLK_000_N_SYNC_0_ + 35| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_ + 36| 7|NOD| . |=> ....|.5..| CLK_000_N_SYNC_11_ + 37| 6|NOD| . |=> ....|..6.| CLK_000_N_SYNC_1_ + 38| 6|NOD| . |=> .1..|....| CLK_000_N_SYNC_2_ + 39| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_3_ + 40| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_4_ + 41| 1|NOD| . |=> 0...|....| CLK_000_N_SYNC_5_ + 42| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_6_ + 43| 1|NOD| . |=> ....|..6.| CLK_000_N_SYNC_7_ + 44| 6|NOD| . |=> ....|.5..| CLK_000_N_SYNC_8_ + 45| 5|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ + 46| 3|NOD| . |=> ..2.|....| CLK_000_P_SYNC_0_ + 47| 2|NOD| . |=> .1..|....| CLK_000_P_SYNC_1_ + 48| 1|NOD| . |=> ..2.|....| CLK_000_P_SYNC_2_ + 49| 2|NOD| . |=> ...3|....| CLK_000_P_SYNC_3_ + 50| 3|NOD| . |=> ....|.5..| CLK_000_P_SYNC_4_ + 51| 5|NOD| . |=> 0...|....| CLK_000_P_SYNC_5_ + 52| 0|NOD| . |=> 0...|....| CLK_000_P_SYNC_6_ + 53| 0|NOD| . |=> 0...|....| CLK_000_P_SYNC_7_ + 54| 0|NOD| . |=> 0...|....| CLK_000_P_SYNC_8_ + 55| 0|NOD| . |=> ..2.|....| CLK_000_P_SYNC_9_ + 56| +|INP| 64|=> 01..|...7| CLK_030 + 57| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 58| 1|OUT| 10|=> ....|....| CLK_EXP + 59| +|Cin| 61|=> ....|....| CLK_OSZI + 60| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ + 61| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ + 62| 7| IO| 81|=> ....|....| DSACK1 |=> Paired w/: RN_DSACK1 - 58| 0| IO| 98|=> ...3|....| DS_030 - 59| 3|INP| 30|=> ...3|....| DTACK - 60| 6| IO| 66|=> ....|....| E + 63| 0| IO| 98|=> ...3|....| DS_030 + 64| 3|INP| 30|=> .1..|....| DTACK + 65| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 61| 5|INP| 57|=> ..2.|4..7| FC_0_ - 62| 5|INP| 58|=> ..2.|4..7| FC_1_ - 63| 7|OUT| 78|=> ....|....| FPU_CS - 64| 0|INP| 91|=> ....|4..7| FPU_SENSE - 65| 1| IO| 8|=> ....|....| IPL_030_0_ + 66| 5|INP| 57|=> ....|45.7| FC_0_ + 67| 5|INP| 58|=> ....|45.7| FC_1_ + 68| 7|OUT| 78|=> ....|....| FPU_CS + 69| 0|INP| 91|=> ....|4..7| FPU_SENSE + 70| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 66| 1| IO| 7|=> ....|....| IPL_030_1_ + 71| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 67| 1| IO| 9|=> ....|....| IPL_030_2_ + 72| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 68| 6|INP| 67|=> .1..|....| IPL_0_ - 69| 5|INP| 56|=> .12.|....| IPL_1_ - 70| 6|INP| 68|=> .1..|....| IPL_2_ - 71| 1|NOD| . |=> .1..|....| IPL_D0_0_ - 72| 2|NOD| . |=> .1..|....| IPL_D0_1_ - 73| 1|NOD| . |=> .1..|....| IPL_D0_2_ - 74| 3| IO| 31|=> 0...|..6.| LDS_000 - 75| 5|NOD| . |=> ....|.5..| N_165 - 76| 1| IO| 3|=> ....|....| RESET + 73| 6|INP| 67|=> .1.3|....| IPL_0_ + 74| 5|INP| 56|=> .1.3|....| IPL_1_ + 75| 6|INP| 68|=> .1..|..6.| IPL_2_ + 76| 3|NOD| . |=> .1..|....| IPL_D0_0_ + 77| 3|NOD| . |=> .1..|....| IPL_D0_1_ + 78| 6|NOD| . |=> .1..|....| IPL_D0_2_ + 79| 3| IO| 31|=> 0...|..6.| LDS_000 + 80| 1| IO| 3|=> ....|....| RESET |=> Paired w/: RN_RESET - 77| 6|NOD| . |=> ....|..6.| RN_A0 + 81| 6|NOD| . |=> ....|..6.| RN_A0 |=> Paired w/: A0 - 78| 7|NOD| . |=> 0.23|4.67| RN_BGACK_030 + 82| 7|NOD| . |=> 0.23|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 - 79| 3|NOD| . |=> ...3|....| RN_BG_000 + 83| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 80| 7|NOD| . |=> ....|...7| RN_DSACK1 + 84| 7|NOD| . |=> ....|...7| RN_DSACK1 |=> Paired w/: DSACK1 - 81| 6|NOD| . |=> ...3|.56.| RN_E + 85| 6|NOD| . |=> ..23|..6.| RN_E |=> Paired w/: E - 82| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 86| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 83| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 87| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 84| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 88| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 85| 1|NOD| . |=> 01.3|4.67| RN_RESET + 89| 1|NOD| . |=> 01.3|4.67| RN_RESET |=> Paired w/: RESET - 86| 6|NOD| . |=> ....|..6.| RN_RW + 90| 6|NOD| . |=> ....|..6.| RN_RW |=> Paired w/: RW - 87| 7|NOD| . |=> ....|...7| RN_RW_000 + 91| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 88| 3|NOD| . |=> ...3|.5..| RN_VMA + 92| 3|NOD| . |=> ..23|....| RN_VMA |=> Paired w/: VMA - 89| +|INP| 86|=> 0123|.567| RST - 90| 1|NOD| . |=> 01..|....| RST_DLY_0_ - 91| 0|NOD| . |=> 01..|....| RST_DLY_1_ - 92| 1|NOD| . |=> 01..|....| RST_DLY_2_ - 93| 1|NOD| . |=> 01..|....| RST_DLY_3_ - 94| 1|NOD| . |=> 01..|....| RST_DLY_4_ - 95| 0|NOD| . |=> 01..|....| RST_DLY_5_ - 96| 1|NOD| . |=> 01..|....| RST_DLY_6_ - 97| 0|NOD| . |=> 01..|....| RST_DLY_7_ - 98| 6| IO| 71|=> ..2.|...7| RW + 93| +|INP| 86|=> 0123|.567| RST + 94| 2|NOD| . |=> .12.|....| RST_DLY_0_ + 95| 1|NOD| . |=> .12.|....| RST_DLY_1_ + 96| 1|NOD| . |=> .12.|....| RST_DLY_2_ + 97| 2|NOD| . |=> .12.|....| RST_DLY_3_ + 98| 2|NOD| . |=> .12.|....| RST_DLY_4_ + 99| 1|NOD| . |=> .12.|....| RST_DLY_5_ + 100| 2|NOD| . |=> .12.|....| RST_DLY_6_ + 101| 2|NOD| . |=> .12.|....| RST_DLY_7_ + 102| 6| IO| 71|=> 0...|...7| RW |=> Paired w/: RN_RW - 99| 7| IO| 80|=> 0...|4.6.| RW_000 + 103| 7| IO| 80|=> 0...|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 100| 6| IO| 70|=> .1..|....| SIZE_0_ - 101| 7| IO| 79|=> .1..|....| SIZE_1_ - 102| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ - 103| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ - 104| 5|NOD| . |=> ....|.5.7| SM_AMIGA_0_ - 105| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ - 106| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ - 107| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_3_ - 108| 5|NOD| . |=> ....|.5..| SM_AMIGA_4_ - 109| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_ - 110| 2|NOD| . |=> .12.|.5..| SM_AMIGA_6_ - 111| 5|NOD| . |=> ..23|...7| SM_AMIGA_i_7_ - 112| 3| IO| 32|=> 0...|..6.| UDS_000 - 113| 3| IO| 35|=> ....|....| VMA + 104| 6| IO| 70|=> ....|..6.| SIZE_0_ + 105| 7| IO| 79|=> ....|..6.| SIZE_1_ + 106| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ + 107| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ + 108| 5|NOD| . |=> ....|.5.7| SM_AMIGA_0_ + 109| 2|NOD| . |=> ..2.|.5.7| SM_AMIGA_1_ + 110| 2|NOD| . |=> ..2.|.5..| SM_AMIGA_2_ + 111| 2|NOD| . |=> 0.2.|.5..| SM_AMIGA_3_ + 112| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_4_ + 113| 5|NOD| . |=> 0...|.5.7| SM_AMIGA_5_ + 114| 5|NOD| . |=> ....|.56.| SM_AMIGA_6_ + 115| 5|NOD| . |=> ...3|.5.7| SM_AMIGA_i_7_ + 116| 3| IO| 32|=> 0...|..6.| UDS_000 + 117| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 114| +|INP| 36|=> ....|.5..| VPA - 115| 3|NOD| . |=> ...3|.56.| cpu_est_0_ - 116| 3|NOD| . |=> ...3|.56.| cpu_est_1_ - 117| 3|NOD| . |=> ...3|.56.| cpu_est_2_ - 118| 6|NOD| . |=> ...3|..6.| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 119| 6|NOD| . |=> ..2.|..6.| inst_AMIGA_BUS_ENABLE_DMA_LOW - 120| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA - 121| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT - 122| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC - 123| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0 - 124| 7|NOD| . |=> ..2.|..6.| inst_BGACK_030_INT_D - 125| 6|NOD| . |=> ..23|.5..| inst_CLK_000_D0 - 126| 5|NOD| . |=> ..23|.5..| inst_CLK_000_D1 - 127| 6|NOD| . |=> 01.3|.5..| inst_CLK_000_NE - 128| 1|NOD| . |=> ...3|.56.| inst_CLK_000_NE_D0 - 129| 3|NOD| . |=> 0.23|.5.7| inst_CLK_000_PE - 130| 0|NOD| . |=> 0...|....| inst_CLK_030_H - 131| 0|NOD| . |=> 0...|..6.| inst_CLK_OUT_PRE_50 - 132| 6|NOD| . |=> ....|...7| inst_CLK_OUT_PRE_D - 133| 0|NOD| . |=> 0...|....| inst_DS_000_DMA - 134| 2|NOD| . |=> ..23|....| inst_DS_000_ENABLE - 135| 3|NOD| . |=> .1..|.5..| inst_DS_030_D0 - 136| 3|NOD| . |=> ....|.5..| inst_DTACK_D0 - 137| 1|NOD| . |=> .1.3|....| inst_LDS_000_INT - 138| 5|NOD| . |=> ...3|.5..| inst_UDS_000_INT - 139| 5|NOD| . |=> ...3|.5..| inst_VPA_D - 140| 6|NOD| . |=> 0.23|4567| inst_nEXP_SPACE_D0reg - 141| +|INP| 14|=> ....|..6.| nEXP_SPACE + 118| +|INP| 36|=> ...3|....| VPA + 119| 2|NOD| . |=> ..23|..6.| cpu_est_0_ + 120| 6|NOD| . |=> ..23|..6.| cpu_est_1_ + 121| 2|NOD| . |=> ..23|..6.| cpu_est_2_ + 122| 6|NOD| . |=> ...3|..6.| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 123| 2|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 124| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA + 125| 0|NOD| . |=> 0...|4...| inst_AS_000_INT + 126| 5|NOD| . |=> ....|.5..| inst_AS_030_000_SYNC + 127| 7|NOD| . |=> 0..3|45.7| inst_AS_030_D0 + 128| 7|NOD| . |=> ..2.|.56.| inst_BGACK_030_INT_D + 129| 1|NOD| . |=> ...3|.5..| inst_CLK_000_D0 + 130| 3|NOD| . |=> ...3|.5..| inst_CLK_000_D1 + 131| 5|NOD| . |=> .123|45..| inst_CLK_000_NE + 132| 4|NOD| . |=> ..23|..6.| inst_CLK_000_NE_D0 + 133| 2|NOD| . |=> 0.23|.5.7| inst_CLK_000_PE + 134| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 135| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 + 136| 4|NOD| . |=> ....|...7| inst_CLK_OUT_PRE_D + 137| 0|NOD| . |=> 0...|....| inst_DS_000_DMA + 138| 0|NOD| . |=> 0..3|....| inst_DS_000_ENABLE + 139| 3|NOD| . |=> ....|..6.| inst_DS_030_D0 + 140| 1|NOD| . |=> ..23|....| inst_DTACK_D0 + 141| 6|NOD| . |=> ...3|..6.| inst_LDS_000_INT + 142| 6|NOD| . |=> ...3|..6.| inst_UDS_000_INT + 143| 3|NOD| . |=> ..23|....| inst_VPA_D + 144| 5|NOD| . |=> 0..3|4567| inst_nEXP_SPACE_D0reg + 145| +|INP| 14|=> ....|.5..| nEXP_SPACE + 146| 3|NOD| . |=> ....|.5..| pos_clk_un29_clk_000_ne_d0_i_n --------------------------------------------------------------------------- =========================================================================== < C:/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -313,8 +318,8 @@ ____|_____|_________|______________________________________________________ 81 | I_O | 7_04|*| DSACK1 82 | I_O | 7_03|*| AS_030 83 | I_O | 7_02|*| BGACK_030 - 84 | I_O | 7_01| | - - 85 | I_O | 7_00| | - + 84 | I_O | 7_01|*| A_22_ + 85 | I_O | 7_00|*| A_23_ 86 | Inp | |*| RST 87 | Vcc | | | (pwr/test) 88 | GND | | | (pwr/test) @@ -322,8 +327,8 @@ ____|_____|_________|______________________________________________________ 90 | Vcc | | | (pwr/test) 91 | I_O | 0_00|*| FPU_SENSE 92 | I_O | 0_01|*| AVEC - 93 | I_O | 0_02| | - - 94 | I_O | 0_03| | - + 93 | I_O | 0_02|*| A_20_ + 94 | I_O | 0_03|*| A_21_ 95 | I_O | 0_04|*| A_18_ 96 | I_O | 0_05|*| A_16_ 97 | I_O | 0_06|*| A_19_ @@ -342,21 +347,21 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| RST_DLY_1_|NOD| | S | 4 | 4 to [ 1]| 1 XOR free - 2|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 2]| 1 XOR to [ 2] as logic PT - 3|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| AVEC|OUT| | S | 1 | 4 to [ 2]| 1 XOR to [ 4] for 1 PT sig - 5| RST_DLY_7_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6| CYCLE_DMA_1_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free - 7|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 1|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 1]| 1 XOR free + 2| CYCLE_DMA_0_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 3|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 6] for 1 PT sig + 7|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 7] for 1 PT sig 8|inst_AS_000_DMA|NOD| | S | 7 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10| CYCLE_DMA_0_|NOD| | S | 2 | 4 to [10]| 1 XOR free -11|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig -12| RST_DLY_5_|NOD| | S | 4 | 4 to [12]| 1 XOR free -13|inst_DS_000_DMA|NOD| | S | 9 | 4 to [13]| 1 XOR to [13] as logic PT -14|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig -15|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig + 9|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [12]| 1 XOR free +13| CYCLE_DMA_1_|NOD| | S | 3 | 4 to [13]| 1 XOR free +14|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Maximum PT Capacity @@ -369,21 +374,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DS_030| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| RST_DLY_1_|NOD| | S | 4 |=> can support up to [ 13] logic PT(s) - 2|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 5| RST_DLY_7_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) - 6| CYCLE_DMA_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 7|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 8|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 13] logic PT(s) - 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -10| CYCLE_DMA_0_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) -11|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -12| RST_DLY_5_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) -13|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 13] logic PT(s) -14|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -15|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 1|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) + 2| CYCLE_DMA_0_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 5|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 13] logic PT(s) + 6|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 7|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 8|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 9] logic PT(s) + 9|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 14] logic PT(s) +10|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) +13| CYCLE_DMA_1_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) +14|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Node-Pin Assignments @@ -394,21 +399,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1| RST_DLY_1_|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2|inst_CLK_030_H|NOD| | => | 6 7 0 1 | 97 98 91 92 - 3|CLK_000_N_SYNC_5_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1|inst_AS_000_INT|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2| CYCLE_DMA_0_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 3|CLK_000_P_SYNC_6_|NOD| | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5| RST_DLY_7_|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6| CYCLE_DMA_1_|NOD| | => | 0 1 2 3 | 91 92 93 94 - 7|CLK_000_N_SYNC_3_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 5|inst_DS_000_DMA|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6|CLK_000_N_SYNC_6_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 7|CLK_000_P_SYNC_9_|NOD| | => | 0 1 2 3 | 91 92 93 94 8|inst_AS_000_DMA|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 92 93 94 95 -10| CYCLE_DMA_0_|NOD| | => | 2 3 4 5 | 93 94 95 96 -11|CLK_000_N_SYNC_2_|NOD| | => | 2 3 4 5 | 93 94 95 96 -12| RST_DLY_5_|NOD| | => | 3 4 5 6 | 94 95 96 97 -13|inst_DS_000_DMA|NOD| | => | 3 4 5 6 | 94 95 96 97 -14|CLK_000_N_SYNC_8_|NOD| | => | 4 5 6 7 | 95 96 97 98 -15|CLK_000_N_SYNC_1_|NOD| | => | 4 5 6 7 | 95 96 97 98 + 9|inst_CLK_030_H|NOD| | => | 1 2 3 4 | 92 93 94 95 +10|CLK_000_P_SYNC_8_|NOD| | => | 2 3 4 5 | 93 94 95 96 +11| | | | => | 2 3 4 5 | 93 94 95 96 +12|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 94 95 96 97 +13| CYCLE_DMA_1_|NOD| | => | 3 4 5 6 | 94 95 96 97 +14|CLK_000_P_SYNC_7_|NOD| | => | 4 5 6 7 | 95 96 97 98 +15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > IO-to-Node Pin Mapping @@ -421,8 +426,8 @@ _|_________________|__|_____|____________________|________________________ _|_________________|__|___|_____|___________________________________________ 0| FPU_SENSE|INP|*| 91| => | 0 1 2 3 4 5 6 7 1| AVEC|OUT|*| 92| => | 2 3 ( 4) 5 6 7 8 9 - 2| | | | 93| => | 4 5 6 7 8 9 10 11 - 3| | | | 94| => | 6 7 8 9 10 11 12 13 + 2| A_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 + 3| A_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 5| A_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 6| A_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 @@ -439,8 +444,8 @@ _|_________________|__|___|_____|___________________________________________ _|_________________|__|___|_____|__________________________________________ 0| FPU_SENSE|INP|*| 91| => | Input macrocell [ -] 1| AVEC|OUT|*| 92| => | Input macrocell [ -] - 2| | | | 93| => | Input macrocell [ -] - 3| | | | 94| => | Input macrocell [ -] + 2| A_20_|INP|*| 93| => | Input macrocell [ -] + 3| A_21_|INP|*| 94| => | Input macrocell [ -] 4| A_18_|INP|*| 95| => | Input macrocell [ -] 5| A_16_|INP|*| 96| => | Input macrocell [ -] 6| A_19_|INP|*| 97| => | Input macrocell [ -] @@ -458,42 +463,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101| IO DS_030| | ] - [MCell 1 |103|NOD RST_DLY_1_| |*] + [MCell 1 |103|NOD inst_AS_000_INT| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD inst_CLK_030_H| |*] - [MCell 3 |106|NOD CLK_000_N_SYNC_5_| |*] + [MCell 2 |104|NOD CYCLE_DMA_0_| |*] + [MCell 3 |106|NOD CLK_000_P_SYNC_6_| |*] - 2 [IOpin 2 | 93| -| | ] + 2 [IOpin 2 | 93|INP A_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD RST_DLY_7_| |*] + [MCell 5 |109|NOD inst_DS_000_DMA| |*] - 3 [IOpin 3 | 94| -| | ] + 3 [IOpin 3 | 94|INP A_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD CYCLE_DMA_1_| |*] - [MCell 7 |112|NOD CLK_000_N_SYNC_3_| |*] + [MCell 6 |110|NOD CLK_000_N_SYNC_6_| |*] + [MCell 7 |112|NOD CLK_000_P_SYNC_9_| |*] 4 [IOpin 4 | 95|INP A_18_|*|*] [RegIn 4 |114| -| | ] [MCell 8 |113|NOD inst_AS_000_DMA| |*] - [MCell 9 |115|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 9 |115|NOD inst_CLK_030_H| |*] 5 [IOpin 5 | 96|INP A_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116|NOD CYCLE_DMA_0_| |*] - [MCell 11 |118|NOD CLK_000_N_SYNC_2_| |*] + [MCell 10 |116|NOD CLK_000_P_SYNC_8_| |*] + [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119|NOD RST_DLY_5_| |*] - [MCell 13 |121|NOD inst_DS_000_DMA| |*] + [MCell 12 |119|NOD inst_DS_000_ENABLE| |*] + [MCell 13 |121|NOD CYCLE_DMA_1_| |*] 7 [IOpin 7 | 98| IO DS_030|*|*] [RegIn 7 |123| -| | ] - [MCell 14 |122|NOD CLK_000_N_SYNC_8_| |*] - [MCell 15 |124|NOD CLK_000_N_SYNC_1_| |*] + [MCell 14 |122|NOD CLK_000_P_SYNC_7_| |*] + [MCell 15 |124| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Logic Array Fan-in @@ -501,39 +506,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 1 12 ( 143)| RST_DLY_4_ -Mux02| Mcel 1 10 ( 140)| RST_DLY_0_ -Mux03| Mcel 0 8 ( 113)| inst_AS_000_DMA +Mux00| Mcel 0 13 ( 121)| CYCLE_DMA_1_ +Mux01| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux02| Mcel 5 10 ( 236)| CLK_000_P_SYNC_5_ +Mux03| Mcel 0 14 ( 122)| CLK_000_P_SYNC_7_ Mux04| Input Pin ( 64)| CLK_030 -Mux05| ... | ... -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 0 11 ( 118)| CLK_000_N_SYNC_2_ -Mux08| Mcel 4 8 ( 209)| CLK_000_N_SYNC_7_ -Mux09| Mcel 0 1 ( 103)| RST_DLY_1_ -Mux10| Mcel 0 6 ( 110)| CYCLE_DMA_1_ -Mux11| ... | ... -Mux12| Mcel 3 9 ( 187)| inst_CLK_000_PE -Mux13| Mcel 0 15 ( 124)| CLK_000_N_SYNC_1_ -Mux14| Mcel 0 10 ( 116)| CYCLE_DMA_0_ -Mux15| Mcel 0 12 ( 119)| RST_DLY_5_ +Mux05| Mcel 5 0 ( 221)| inst_nEXP_SPACE_D0reg +Mux06| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux07| Mcel 2 8 ( 161)| SM_AMIGA_3_ +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 1 14 ( 146)| CLK_000_N_SYNC_5_ +Mux10| ... | ... +Mux11| IOPin 6 6 ( 71)| RW +Mux12| Mcel 0 1 ( 103)| inst_AS_000_INT +Mux13| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux14| Mcel 0 10 ( 116)| CLK_000_P_SYNC_8_ +Mux15| Mcel 0 12 ( 119)| inst_DS_000_ENABLE Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| Mcel 1 11 ( 142)| RST_DLY_6_ -Mux18| Mcel 0 5 ( 109)| RST_DLY_7_ -Mux19| Mcel 0 9 ( 115)| inst_CLK_OUT_PRE_50 -Mux20| IOPin 3 3 ( 32)| UDS_000 -Mux21| Mcel 3 7 ( 184)| CLK_000_N_SYNC_0_ -Mux22| Mcel 3 3 ( 178)| CLK_000_N_SYNC_4_ -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 0 5 ( 109)| inst_DS_000_DMA +Mux19| Mcel 0 9 ( 115)| inst_CLK_030_H +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 0 2 ( 104)| CYCLE_DMA_0_ +Mux23| ... | ... Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 0 2 ( 104)| inst_CLK_030_H -Mux26| Mcel 1 0 ( 125)| RST_DLY_3_ -Mux27| Mcel 6 9 ( 259)| inst_CLK_000_NE -Mux28| Mcel 0 13 ( 121)| inst_DS_000_DMA -Mux29| Mcel 1 14 ( 146)| RN_RESET -Mux30| ... | ... -Mux31| Mcel 1 5 ( 133)| RST_DLY_2_ -Mux32| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux25| Mcel 0 3 ( 106)| CLK_000_P_SYNC_6_ +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| ... | ... +Mux28| IOPin 7 5 ( 80)| RW_000 +Mux29| ... | ... +Mux30| Mcel 0 8 ( 113)| inst_AS_000_DMA +Mux31| ... | ... +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Macrocell (MCell) Cluster Assignments @@ -545,22 +550,22 @@ Mux32| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| RST_DLY_3_|NOD| | S | 6 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| CLK_EXP|OUT| | S | 1 | 4 to [ 0]| 1 XOR to [ 1] for 1 PT sig - 2| IPL_030_2_| IO| | S |10 | 4 to [ 2]| 1 XOR to [ 2] as logic PT - 3|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 to [ 2]| 1 XOR to [ 3] for 1 PT sig - 4|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 to [ 2]| 1 XOR to [ 4] for 1 PT sig + 0| RESET| IO| | S | 2 | 4 to [ 0]| 1 XOR free + 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig + 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT 5| RST_DLY_2_|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| IPL_030_1_| IO| | S |10 | 4 to [ 6]| 1 XOR to [ 6] as logic PT - 7| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig - 8| IPL_030_0_| IO| | S |10 | 4 to [ 6]| 1 XOR to [ 6] as logic PT - 9|inst_LDS_000_INT|NOD| | S | 4 | 4 to [ 8]| 1 XOR to [ 8] as logic PT -10| RST_DLY_0_|NOD| | S | 3 | 4 to [ 8]| 1 XOR to [ 8] as logic PT -11| RST_DLY_6_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -12| RST_DLY_4_|NOD| | S | 2 :+: 1| 4 to [10]| 1 XOR to [12] -13| IPL_D0_2_|NOD| | S | 1 | 4 to [11]| 1 XOR to [13] for 1 PT sig -14| RESET| IO| | S | 2 | 4 to [12]| 1 XOR free -15|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 to [14]| 1 XOR to [15] for 1 PT sig + 6| inst_DTACK_D0|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 6] for 1 PT sig + 7|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| IPL_030_0_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 9| RST_DLY_5_|NOD| | S | 4 | 4 to [ 8]| 1 XOR to [ 8] as logic PT +10|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [11] for 1 PT sig +12| IPL_030_1_| IO| | S |10 | 4 to [12]| 1 XOR to [12] as logic PT +13| RST_DLY_1_|NOD| | S | 4 | 4 to [12]| 1 XOR to [12] as logic PT +14|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 to [13]| 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Maximum PT Capacity @@ -572,22 +577,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RST_DLY_3_|NOD| | S | 6 |=> can support up to [ 9] logic PT(s) - 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) - 2| IPL_030_2_| IO| | S |10 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 4|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 0| RESET| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 2|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 3|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 13] logic PT(s) 5| RST_DLY_2_|NOD| | S | 5 |=> can support up to [ 9] logic PT(s) - 6| IPL_030_1_| IO| | S |10 |=> can support up to [ 14] logic PT(s) - 7| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 14] logic PT(s) - 9|inst_LDS_000_INT|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) -10| RST_DLY_0_|NOD| | S | 3 |=> can support up to [ 4] logic PT(s) -11| RST_DLY_6_|NOD| | S | 3 |=> can support up to [ 4] logic PT(s) -12| RST_DLY_4_|NOD| | S | 2 :+: 1|=> can support up to [ 5] logic PT(s) -13| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) -14| RESET| IO| | S | 2 |=> can support up to [ 4] logic PT(s) -15|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 6| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 7|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 18] logic PT(s) + 9| RST_DLY_5_|NOD| | S | 4 |=> can support up to [ 8] logic PT(s) +10|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +11|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +12| IPL_030_1_| IO| | S |10 |=> can support up to [ 14] logic PT(s) +13| RST_DLY_1_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) +14|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments @@ -597,22 +602,22 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 1] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| RST_DLY_3_|NOD| | => | 5 6 7 0 | 5 4 3 10 + 0| RESET| IO| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) - 2| IPL_030_2_| IO| | => | 6 7 0 ( 1)| 4 3 10 ( 9) - 3|CLK_000_P_SYNC_2_|NOD| | => | 6 7 0 1 | 4 3 10 9 - 4|CLK_000_P_SYNC_4_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 2|inst_CLK_000_D0|NOD| | => | 6 7 0 1 | 4 3 10 9 + 3|CLK_000_N_SYNC_4_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| RST_DLY_2_|NOD| | => | 7 0 1 2 | 3 10 9 8 - 6| IPL_030_1_| IO| | => | 0 1 2 ( 3)| 10 9 8 ( 7) - 7| IPL_D0_0_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 6| inst_DTACK_D0|NOD| | => | 0 1 2 3 | 10 9 8 7 + 7|CLK_000_N_SYNC_3_|NOD| | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 9 8 7 6 -10| RST_DLY_0_|NOD| | => | 2 3 4 5 | 8 7 6 5 -11| RST_DLY_6_|NOD| | => | 2 3 4 5 | 8 7 6 5 -12| RST_DLY_4_|NOD| | => | 3 4 5 6 | 7 6 5 4 -13| IPL_D0_2_|NOD| | => | 3 4 5 6 | 7 6 5 4 -14| RESET| IO| | => | 4 5 6 ( 7)| 6 5 4 ( 3) -15|inst_CLK_000_NE_D0|NOD| | => | 4 5 6 7 | 6 5 4 3 + 9| RST_DLY_5_|NOD| | => | 1 2 3 4 | 9 8 7 6 +10|CLK_000_N_SYNC_7_|NOD| | => | 2 3 4 5 | 8 7 6 5 +11|CLK_000_P_SYNC_2_|NOD| | => | 2 3 4 5 | 8 7 6 5 +12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 +13| RST_DLY_1_|NOD| | => | 3 4 5 6 | 7 6 5 4 +14|CLK_000_N_SYNC_5_|NOD| | => | 4 5 6 7 | 6 5 4 3 +15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO-to-Node Pin Mapping @@ -624,13 +629,13 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| CLK_EXP|OUT|*| 10| => | 0 ( 1) 2 3 4 5 6 7 - 1| IPL_030_2_| IO|*| 9| => | ( 2) 3 4 5 6 7 8 9 + 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_030_0_| IO|*| 8| => | 4 5 6 7 ( 8) 9 10 11 - 3| IPL_030_1_| IO|*| 7| => | ( 6) 7 8 9 10 11 12 13 + 3| IPL_030_1_| IO|*| 7| => | 6 7 8 9 10 11 (12) 13 4| A_29_|INP|*| 6| => | 8 9 10 11 12 13 14 15 5| A_30_|INP|*| 5| => | 10 11 12 13 14 15 0 1 6| A_31_|INP|*| 4| => | 12 13 14 15 0 1 2 3 - 7| RESET| IO|*| 3| => | (14) 15 0 1 2 3 4 5 + 7| RESET| IO|*| 3| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table @@ -665,43 +670,43 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 10|OUT CLK_EXP|*| ] [RegIn 0 |126| -| | ] - [MCell 0 |125|NOD RST_DLY_3_| |*] + [MCell 0 |125|NOD RN_RESET| |*] paired w/[ RESET] [MCell 1 |127|OUT CLK_EXP| | ] 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 3 |130|NOD CLK_000_P_SYNC_2_| |*] + [MCell 2 |128|NOD inst_CLK_000_D0| |*] + [MCell 3 |130|NOD CLK_000_N_SYNC_4_| |*] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] - [MCell 4 |131|NOD CLK_000_P_SYNC_4_| |*] + [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] [MCell 5 |133|NOD RST_DLY_2_| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 7 |136|NOD IPL_D0_0_| |*] + [MCell 6 |134|NOD inst_DTACK_D0| |*] + [MCell 7 |136|NOD CLK_000_N_SYNC_3_| |*] 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD inst_LDS_000_INT| |*] + [MCell 9 |139|NOD RST_DLY_5_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD RST_DLY_0_| |*] - [MCell 11 |142|NOD RST_DLY_6_| |*] + [MCell 10 |140|NOD CLK_000_N_SYNC_7_| |*] + [MCell 11 |142|NOD CLK_000_P_SYNC_2_| |*] 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] - [MCell 12 |143|NOD RST_DLY_4_| |*] - [MCell 13 |145|NOD IPL_D0_2_| |*] + [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] + [MCell 13 |145|NOD RST_DLY_1_| |*] 7 [IOpin 7 | 3| IO RESET|*| ] paired w/[ RN_RESET] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD RN_RESET| |*] paired w/[ RESET] - [MCell 15 |148|NOD inst_CLK_000_NE_D0| |*] + [MCell 14 |146|NOD CLK_000_N_SYNC_5_| |*] + [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Logic Array Fan-in @@ -709,39 +714,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A0 -Mux01| Mcel 1 12 ( 143)| RST_DLY_4_ -Mux02| Mcel 3 10 ( 188)| inst_DS_030_D0 -Mux03| Mcel 2 9 ( 163)| CLK_000_P_SYNC_3_ -Mux04| Input Pin ( 64)| CLK_030 -Mux05| ... | ... -Mux06| Mcel 1 9 ( 139)| inst_LDS_000_INT -Mux07| Mcel 1 11 ( 142)| RST_DLY_6_ +Mux00| Mcel 1 0 ( 125)| RN_RESET +Mux01| Mcel 1 7 ( 136)| CLK_000_N_SYNC_3_ +Mux02| Mcel 2 2 ( 152)| RST_DLY_6_ +Mux03| Input Pin ( 11)| CLK_000 +Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux05| Mcel 6 3 ( 250)| CLK_000_N_SYNC_2_ +Mux06| Mcel 1 9 ( 139)| RST_DLY_5_ +Mux07| Mcel 2 14 ( 170)| RST_DLY_4_ Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux09| Mcel 0 1 ( 103)| RST_DLY_1_ -Mux10| Mcel 1 13 ( 145)| IPL_D0_2_ -Mux11| Mcel 1 6 ( 134)| RN_IPL_030_1_ -Mux12| Mcel 1 10 ( 140)| RST_DLY_0_ -Mux13| Mcel 6 11 ( 262)| CLK_000_P_SYNC_1_ -Mux14| Mcel 2 4 ( 155)| SM_AMIGA_6_ -Mux15| Mcel 0 12 ( 119)| RST_DLY_5_ +Mux09| Mcel 2 6 ( 158)| RST_DLY_0_ +Mux10| Mcel 5 4 ( 227)| inst_CLK_000_NE +Mux11| ... | ... +Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ +Mux13| Mcel 3 3 ( 178)| IPL_D0_0_ +Mux14| IOPin 3 5 ( 30)| DTACK +Mux15| Mcel 0 6 ( 110)| CLK_000_N_SYNC_6_ Mux16| IOPin 6 2 ( 67)| IPL_0_ -Mux17| IOPin 6 5 ( 70)| SIZE_0_ -Mux18| Mcel 1 2 ( 128)| RN_IPL_030_2_ -Mux19| ... | ... -Mux20| IOPin 7 6 ( 79)| SIZE_1_ +Mux17| Mcel 3 14 ( 194)| IPL_D0_1_ +Mux18| Mcel 2 10 ( 164)| RST_DLY_7_ +Mux19| Mcel 1 3 ( 130)| CLK_000_N_SYNC_4_ +Mux20| Input Pin ( 64)| CLK_030 Mux21| IOPin 5 4 ( 56)| IPL_1_ -Mux22| IOPin 6 3 ( 68)| IPL_2_ -Mux23| ... | ... +Mux22| ... | ... +Mux23| Mcel 2 9 ( 163)| RST_DLY_3_ Mux24| Input Pin ( 86)| RST Mux25| ... | ... -Mux26| Mcel 1 0 ( 125)| RST_DLY_3_ -Mux27| Mcel 6 9 ( 259)| inst_CLK_000_NE -Mux28| Mcel 0 5 ( 109)| RST_DLY_7_ -Mux29| Mcel 1 14 ( 146)| RN_RESET -Mux30| Mcel 2 13 ( 169)| IPL_D0_1_ +Mux26| Mcel 6 11 ( 262)| IPL_D0_2_ +Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ +Mux28| Mcel 1 13 ( 145)| RST_DLY_1_ +Mux29| Mcel 2 11 ( 166)| CLK_000_P_SYNC_1_ +Mux30| ... | ... Mux31| Mcel 1 5 ( 133)| RST_DLY_2_ -Mux32| Mcel 1 7 ( 136)| IPL_D0_0_ +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Macrocell (MCell) Cluster Assignments @@ -754,20 +759,20 @@ Mux32| Mcel 1 7 ( 136)| IPL_D0_0_ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 1]| 1 XOR free - 2|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3| | ? | | S | | 4 free | 1 XOR free - 4| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 4]| 1 XOR free - 5|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| | ? | | S | | 4 free | 1 XOR free - 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10| | ? | | S | | 4 free | 1 XOR free -11| | ? | | S | | 4 free | 1 XOR free -12|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [12]| 1 XOR free -13| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| | ? | | S | | 4 free | 1 XOR free + 1| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2| RST_DLY_6_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 3]| 1 XOR free + 4|inst_CLK_000_PE|NOD| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| cpu_est_0_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6| RST_DLY_0_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free + 7|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 9| RST_DLY_3_|NOD| | S | 6 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| RST_DLY_7_|NOD| | S | 2 | 4 to [10]| 1 XOR free +11|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [11] for 1 PT sig +12| cpu_est_2_|NOD| | S | 4 | 4 to [12]| 1 XOR free +13| SM_AMIGA_2_|NOD| | S | 4 | 4 to [13]| 1 XOR free +14| RST_DLY_4_|NOD| | S | 2 :+: 1| 4 to [14]| 1 XOR to [14] 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -780,22 +785,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) - 2|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 13] logic PT(s) - 4| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) - 5|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) - 6| | ? | | S | |=> can support up to [ 14] logic PT(s) - 7| | ? | | S | |=> can support up to [ 10] logic PT(s) - 8|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 19] logic PT(s) - 9|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) -10| | ? | | S | |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) -13| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 14] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 2| RST_DLY_6_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 3|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 4|inst_CLK_000_PE|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 5| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) + 6| RST_DLY_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 7|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 8| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 9] logic PT(s) + 9| RST_DLY_3_|NOD| | S | 6 |=> can support up to [ 9] logic PT(s) +10| RST_DLY_7_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) +11|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) +12| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) +13| SM_AMIGA_2_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) +14| RST_DLY_4_|NOD| | S | 2 :+: 1|=> can support up to [ 9] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -806,20 +811,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 1|inst_AS_000_INT|NOD| | => | 5 6 7 0 | 20 21 22 15 - 2|CLK_000_P_SYNC_9_|NOD| | => | 6 7 0 1 | 21 22 15 16 - 3| | | | => | 6 7 0 1 | 21 22 15 16 - 4| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 22 15 16 17 - 5|CLK_000_P_SYNC_8_|NOD| | => | 7 0 1 2 | 22 15 16 17 - 6| | | | => | 0 1 2 3 | 15 16 17 18 - 7| | | | => | 0 1 2 3 | 15 16 17 18 - 8|inst_AS_030_000_SYNC|NOD| | => | 1 2 3 4 | 16 17 18 19 - 9|CLK_000_P_SYNC_3_|NOD| | => | 1 2 3 4 | 16 17 18 19 -10| | | | => | 2 3 4 5 | 17 18 19 20 -11| | | | => | 2 3 4 5 | 17 18 19 20 -12|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 18 19 20 21 -13| IPL_D0_1_|NOD| | => | 3 4 5 6 | 18 19 20 21 -14| | | | => | 4 5 6 7 | 19 20 21 22 + 1| SM_AMIGA_1_|NOD| | => | 5 6 7 0 | 20 21 22 15 + 2| RST_DLY_6_|NOD| | => | 6 7 0 1 | 21 22 15 16 + 3|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 6 7 0 1 | 21 22 15 16 + 4|inst_CLK_000_PE|NOD| | => | 7 0 1 2 | 22 15 16 17 + 5| cpu_est_0_|NOD| | => | 7 0 1 2 | 22 15 16 17 + 6| RST_DLY_0_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 7|CLK_000_P_SYNC_3_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 8| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 16 17 18 19 + 9| RST_DLY_3_|NOD| | => | 1 2 3 4 | 16 17 18 19 +10| RST_DLY_7_|NOD| | => | 2 3 4 5 | 17 18 19 20 +11|CLK_000_P_SYNC_1_|NOD| | => | 2 3 4 5 | 17 18 19 20 +12| cpu_est_2_|NOD| | => | 3 4 5 6 | 18 19 20 21 +13| SM_AMIGA_2_|NOD| | => | 3 4 5 6 | 18 19 20 21 +14| RST_DLY_4_|NOD| | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== @@ -870,41 +875,41 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 15|INP A_28_|*|*] [RegIn 0 |150| -| | ] [MCell 0 |149|OUT AMIGA_BUS_ENABLE_LOW| | ] - [MCell 1 |151|NOD inst_AS_000_INT| |*] + [MCell 1 |151|NOD SM_AMIGA_1_| |*] 1 [IOpin 1 | 16|INP A_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD CLK_000_P_SYNC_9_| |*] - [MCell 3 |154| -| | ] + [MCell 2 |152|NOD RST_DLY_6_| |*] + [MCell 3 |154|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] 2 [IOpin 2 | 17|INP A_26_|*|*] [RegIn 2 |156| -| | ] - [MCell 4 |155|NOD SM_AMIGA_6_| |*] - [MCell 5 |157|NOD CLK_000_P_SYNC_8_| |*] + [MCell 4 |155|NOD inst_CLK_000_PE| |*] + [MCell 5 |157|NOD cpu_est_0_| |*] 3 [IOpin 3 | 18|INP A_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158| -| | ] - [MCell 7 |160| -| | ] + [MCell 6 |158|NOD RST_DLY_0_| |*] + [MCell 7 |160|NOD CLK_000_P_SYNC_3_| |*] 4 [IOpin 4 | 19|INP A_24_|*|*] [RegIn 4 |162| -| | ] - [MCell 8 |161|NOD inst_AS_030_000_SYNC| |*] - [MCell 9 |163|NOD CLK_000_P_SYNC_3_| |*] + [MCell 8 |161|NOD SM_AMIGA_3_| |*] + [MCell 9 |163|NOD RST_DLY_3_| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164| -| | ] - [MCell 11 |166| -| | ] + [MCell 10 |164|NOD RST_DLY_7_| |*] + [MCell 11 |166|NOD CLK_000_P_SYNC_1_| |*] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] - [MCell 12 |167|NOD inst_DS_000_ENABLE| |*] - [MCell 13 |169|NOD IPL_D0_1_| |*] + [MCell 12 |167|NOD cpu_est_2_| |*] + [MCell 13 |169|NOD SM_AMIGA_2_| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] - [MCell 14 |170| -| | ] + [MCell 14 |170|NOD RST_DLY_4_| |*] [MCell 15 |172| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -913,39 +918,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 5 8 ( 233)| inst_CLK_000_D1 -Mux03| IOPin 5 4 ( 56)| IPL_1_ -Mux04| Mcel 2 12 ( 167)| inst_DS_000_ENABLE -Mux05| Mcel 1 3 ( 130)| CLK_000_P_SYNC_2_ -Mux06| IOPin 0 5 ( 96)| A_16_ -Mux07| Mcel 3 9 ( 187)| inst_CLK_000_PE -Mux08| IOPin 5 1 ( 59)| A_17_ -Mux09| Mcel 6 13 ( 265)| inst_CLK_000_D0 -Mux10| Mcel 6 14 ( 266)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux11| IOPin 6 6 ( 71)| RW -Mux12| IOPin 5 2 ( 58)| FC_1_ -Mux13| Mcel 7 5 ( 277)| inst_AS_030_D0 -Mux14| Mcel 5 4 ( 227)| SM_AMIGA_5_ -Mux15| Mcel 2 5 ( 157)| CLK_000_P_SYNC_8_ -Mux16| Mcel 2 8 ( 161)| inst_AS_030_000_SYNC -Mux17| Mcel 5 12 ( 239)| SM_AMIGA_3_ -Mux18| ... | ... +Mux00| Mcel 1 5 ( 133)| RST_DLY_2_ +Mux01| Mcel 2 1 ( 151)| SM_AMIGA_1_ +Mux02| Mcel 3 10 ( 188)| CLK_000_P_SYNC_0_ +Mux03| IOPin 5 0 ( 60)| A1 +Mux04| Mcel 2 12 ( 167)| cpu_est_2_ +Mux05| ... | ... +Mux06| Mcel 1 9 ( 139)| RST_DLY_5_ +Mux07| Mcel 2 5 ( 157)| cpu_est_0_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE_D0 +Mux09| Mcel 2 6 ( 158)| RST_DLY_0_ +Mux10| Mcel 5 4 ( 227)| inst_CLK_000_NE +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 2 3 ( 154)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux13| Mcel 2 9 ( 163)| RST_DLY_3_ +Mux14| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux15| Mcel 5 1 ( 223)| SM_AMIGA_4_ +Mux16| Mcel 2 8 ( 161)| SM_AMIGA_3_ +Mux17| Mcel 1 11 ( 142)| CLK_000_P_SYNC_2_ +Mux18| Mcel 2 10 ( 164)| RST_DLY_7_ Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| ... | ... -Mux22| Mcel 2 1 ( 151)| inst_AS_000_INT -Mux23| ... | ... -Mux24| IOPin 5 3 ( 57)| FC_0_ -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux26| Mcel 6 7 ( 256)| CLK_000_P_SYNC_7_ -Mux27| IOPin 0 6 ( 97)| A_19_ -Mux28| ... | ... -Mux29| Mcel 2 4 ( 155)| SM_AMIGA_6_ -Mux30| ... | ... -Mux31| IOPin 0 4 ( 95)| A_18_ -Mux32| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux21| Mcel 1 13 ( 145)| RST_DLY_1_ +Mux22| Mcel 6 5 ( 253)| cpu_est_1_ +Mux23| Mcel 1 6 ( 134)| inst_DTACK_D0 +Mux24| Input Pin ( 86)| RST +Mux25| IOPin 4 0 ( 41)| BERR +Mux26| Mcel 3 0 ( 173)| RN_VMA +Mux27| ... | ... +Mux28| Mcel 0 7 ( 112)| CLK_000_P_SYNC_9_ +Mux29| Mcel 3 13 ( 193)| inst_VPA_D +Mux30| Mcel 2 13 ( 169)| SM_AMIGA_2_ +Mux31| Mcel 2 14 ( 170)| RST_DLY_4_ +Mux32| Mcel 2 2 ( 152)| RST_DLY_6_ --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Macrocell (MCell) Cluster Assignments @@ -959,20 +964,20 @@ Mux32| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| cpu_est_2_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free - 3|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 2|pos_clk_un29_clk_000_ne_d0_i_n|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 3| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| cpu_est_0_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free - 7|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 6|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7|inst_DS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_CLK_000_PE|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig -10|inst_DS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig + 9|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| cpu_est_1_|NOD| | S | 5 | 4 to [13]| 1 XOR to [13] as logic PT -14|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Maximum PT Capacity @@ -986,20 +991,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) 1| BG_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 2| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) - 3|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 13] logic PT(s) - 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 6| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 17] logic PT(s) - 7|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 2|pos_clk_un29_clk_000_ne_d0_i_n|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 3| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 17] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 6|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) + 7|inst_DS_030_D0|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) 8| UDS_000| IO| | S | 1 |=> can support up to [ 17] logic PT(s) - 9|inst_CLK_000_PE|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) -10|inst_DS_030_D0|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) -11|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -12| LDS_000| IO| | S | 1 |=> can support up to [ 13] logic PT(s) -13| cpu_est_1_|NOD| | S | 5 |=> can support up to [ 17] logic PT(s) -14|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) -15| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 9|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +10|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 17] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 18] logic PT(s) +13| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +14| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -1011,20 +1016,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 - 3|CLK_000_N_SYNC_4_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2|pos_clk_un29_clk_000_ne_d0_i_n|NOD| | => | 6 7 0 1 | 29 28 35 34 + 3| IPL_D0_0_|NOD| | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6| cpu_est_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 - 7|CLK_000_N_SYNC_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6|CLK_000_P_SYNC_4_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7|inst_DS_030_D0|NOD| | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 - 9|inst_CLK_000_PE|NOD| | => | 1 2 3 4 | 34 33 32 31 -10|inst_DS_030_D0|NOD| | => | 2 3 4 5 | 33 32 31 30 -11|CLK_000_P_SYNC_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 34 33 32 31 +10|CLK_000_P_SYNC_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 +11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13| cpu_est_1_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14|CLK_000_N_SYNC_6_|NOD| | => | 4 5 6 7 | 31 30 29 28 -15| inst_DTACK_D0|NOD| | => | 4 5 6 7 | 31 30 29 28 +13| inst_VPA_D|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| IPL_D0_1_|NOD| | => | 4 5 6 7 | 31 30 29 28 +15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > IO-to-Node Pin Mapping @@ -1080,8 +1085,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD cpu_est_2_| |*] - [MCell 3 |178|NOD CLK_000_N_SYNC_4_| |*] + [MCell 2 |176|NOD pos_clk_un29_clk_000_ne_d0_i_n| |*] + [MCell 3 |178|NOD IPL_D0_0_| |*] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] [RegIn 2 |180| -| | ] @@ -1090,28 +1095,28 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD cpu_est_0_| |*] - [MCell 7 |184|NOD CLK_000_N_SYNC_0_| |*] + [MCell 6 |182|NOD CLK_000_P_SYNC_4_| |*] + [MCell 7 |184|NOD inst_DS_030_D0| |*] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] - [MCell 9 |187|NOD inst_CLK_000_PE| |*] + [MCell 9 |187|NOD inst_CLK_000_D1| |*] 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD inst_DS_030_D0| |*] - [MCell 11 |190|NOD CLK_000_P_SYNC_0_| |*] + [MCell 10 |188|NOD CLK_000_P_SYNC_0_| |*] + [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD cpu_est_1_| |*] + [MCell 13 |193|NOD inst_VPA_D| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD CLK_000_N_SYNC_6_| |*] - [MCell 15 |196|NOD inst_DTACK_D0| |*] + [MCell 14 |194|NOD IPL_D0_1_| |*] + [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Logic Array Fan-in @@ -1119,37 +1124,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 0 7 ( 112)| CLK_000_N_SYNC_3_ -Mux02| Mcel 2 2 ( 152)| CLK_000_P_SYNC_9_ -Mux03| Mcel 3 2 ( 176)| cpu_est_2_ -Mux04| Mcel 2 12 ( 167)| inst_DS_000_ENABLE +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| Mcel 3 13 ( 193)| inst_VPA_D +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 6 5 ( 253)| cpu_est_1_ +Mux04| Mcel 7 5 ( 277)| inst_AS_030_D0 Mux05| IOPin 0 7 ( 98)| DS_030 -Mux06| Mcel 0 3 ( 106)| CLK_000_N_SYNC_5_ -Mux07| Mcel 3 9 ( 187)| inst_CLK_000_PE -Mux08| Mcel 1 15 ( 148)| inst_CLK_000_NE_D0 -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Mcel 6 9 ( 259)| inst_CLK_000_NE -Mux11| Mcel 6 4 ( 251)| RN_E -Mux12| Mcel 6 13 ( 265)| inst_CLK_000_D0 -Mux13| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux06| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux07| Mcel 3 9 ( 187)| inst_CLK_000_D1 +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE_D0 +Mux09| Mcel 0 12 ( 119)| inst_DS_000_ENABLE +Mux10| Mcel 1 2 ( 128)| inst_CLK_000_D0 +Mux11| Mcel 1 6 ( 134)| inst_DTACK_D0 +Mux12| Mcel 6 13 ( 265)| inst_UDS_000_INT +Mux13| Input Pin ( 36)| VPA Mux14| IOPin 2 6 ( 21)| BG_030 -Mux15| Mcel 5 13 ( 241)| inst_VPA_D -Mux16| Mcel 1 9 ( 139)| inst_LDS_000_INT +Mux15| Mcel 2 7 ( 160)| CLK_000_P_SYNC_3_ +Mux16| IOPin 6 2 ( 67)| IPL_0_ Mux17| Mcel 3 1 ( 175)| RN_BG_000 Mux18| Mcel 3 0 ( 173)| RN_VMA Mux19| ... | ... -Mux20| Mcel 5 8 ( 233)| inst_CLK_000_D1 -Mux21| Mcel 3 13 ( 193)| cpu_est_1_ -Mux22| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| ... | ... -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux26| ... | ... -Mux27| Mcel 5 5 ( 229)| inst_UDS_000_INT -Mux28| Mcel 6 10 ( 260)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux29| Mcel 1 14 ( 146)| RN_RESET -Mux30| Mcel 3 6 ( 182)| cpu_est_0_ +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ +Mux21| IOPin 5 4 ( 56)| IPL_1_ +Mux22| Mcel 6 10 ( 260)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux23| Mcel 2 12 ( 167)| cpu_est_2_ +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 5 0 ( 221)| inst_nEXP_SPACE_D0reg +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 6 9 ( 259)| inst_LDS_000_INT +Mux28| Mcel 2 5 ( 157)| cpu_est_0_ +Mux29| Mcel 5 4 ( 227)| inst_CLK_000_NE +Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -1168,15 +1173,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 8|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| | ? | | S | | 4 free | 1 XOR free +13|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1193,18 +1198,18 @@ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 18] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) - 5|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 18] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 18] logic PT(s) - 8|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 9|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 8|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 18] logic PT(s) -11| | ? | | S | |=> can support up to [ 19] logic PT(s) -12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) +13|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1220,15 +1225,15 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5|CLK_000_P_SYNC_6_|NOD| | => | 7 0 1 2 | 48 41 42 43 + 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8|CLK_000_N_SYNC_7_|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9|CLK_000_P_SYNC_5_|NOD| | => | 1 2 3 4 | 42 43 44 45 + 8|inst_CLK_000_NE_D0|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) -13| | | | => | 3 4 5 6 | 44 45 46 47 +13|inst_CLK_OUT_PRE_D|NOD| | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 --------------------------------------------------------------------------- @@ -1290,7 +1295,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD CLK_000_P_SYNC_6_| |*] + [MCell 5 |205|NOD CIIN_0| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1299,8 +1304,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD CLK_000_N_SYNC_7_| |*] - [MCell 9 |211|NOD CLK_000_P_SYNC_5_| |*] + [MCell 8 |209|NOD inst_CLK_000_NE_D0| |*] + [MCell 9 |211|NOD inst_CLK_OUT_PRE_50| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1310,7 +1315,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] [MCell 12 |215|OUT CIIN| | ] - [MCell 13 |217| -| | ] + [MCell 13 |217|NOD inst_CLK_OUT_PRE_D| |*] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] [RegIn 7 |219| -| | ] @@ -1323,39 +1328,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 1 4 ( 131)| CLK_000_P_SYNC_4_ -Mux01| IOPin 1 6 ( 4)| A_31_ -Mux02| Mcel 4 9 ( 211)| CLK_000_P_SYNC_5_ -Mux03| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux00| Mcel 1 0 ( 125)| RN_RESET +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 4 9 ( 211)| inst_CLK_OUT_PRE_50 +Mux03| Mcel 4 5 ( 205)| CIIN_0 Mux04| Mcel 7 5 ( 277)| inst_AS_030_D0 -Mux05| IOPin 2 4 ( 19)| A_24_ -Mux06| IOPin 0 5 ( 96)| A_16_ +Mux05| Mcel 5 0 ( 221)| inst_nEXP_SPACE_D0reg +Mux06| IOPin 5 3 ( 57)| FC_0_ Mux07| IOPin 2 0 ( 15)| A_28_ Mux08| IOPin 5 1 ( 59)| A_17_ -Mux09| IOPin 2 2 ( 17)| A_26_ -Mux10| Mcel 3 14 ( 194)| CLK_000_N_SYNC_6_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 5 4 ( 227)| inst_CLK_000_NE Mux11| IOPin 0 0 ( 91)| FPU_SENSE -Mux12| IOPin 2 3 ( 18)| A_25_ +Mux12| Mcel 0 1 ( 103)| inst_AS_000_INT Mux13| IOPin 1 4 ( 6)| A_29_ -Mux14| ... | ... -Mux15| ... | ... +Mux14| IOPin 2 4 ( 19)| A_24_ +Mux15| IOPin 0 3 ( 94)| A_21_ Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux17| IOPin 2 2 ( 17)| A_26_ +Mux18| IOPin 7 0 ( 85)| A_23_ Mux19| IOPin 1 5 ( 5)| A_30_ -Mux20| IOPin 5 2 ( 58)| FC_1_ +Mux20| IOPin 7 1 ( 84)| A_22_ Mux21| IOPin 2 1 ( 16)| A_27_ -Mux22| Mcel 2 1 ( 151)| inst_AS_000_INT +Mux22| IOPin 2 3 ( 18)| A_25_ Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| ... | ... -Mux25| ... | ... -Mux26| ... | ... +Mux25| IOPin 1 6 ( 4)| A_31_ +Mux26| IOPin 0 5 ( 96)| A_16_ Mux27| IOPin 0 6 ( 97)| A_19_ Mux28| IOPin 7 5 ( 80)| RW_000 -Mux29| Mcel 1 14 ( 146)| RN_RESET +Mux29| IOPin 0 2 ( 93)| A_20_ Mux30| ... | ... Mux31| IOPin 0 4 ( 95)| A_18_ -Mux32| IOPin 7 3 ( 82)| AS_030 +Mux32| IOPin 3 7 ( 28)| BGACK_000 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Macrocell (MCell) Cluster Assignments @@ -1367,21 +1372,21 @@ Mux32| IOPin 7 3 ( 82)| AS_030 | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| SM_AMIGA_i_7_|NOD| | S |14 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 2| SM_AMIGA_2_|NOD| | S | 4 | 4 to [ 0]| 1 XOR free - 3| | ? | | S | | 4 to [ 1]| 1 XOR free - 4| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free - 5|inst_UDS_000_INT|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6| N_165|NOD| | S | 4 | 4 to [ 4]| 1 XOR free - 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 6]| 1 XOR to [ 8] for 1 PT sig + 0|inst_nEXP_SPACE_D0reg|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4|inst_CLK_000_NE|NOD| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 to [ 8]| 1 XOR free + 8| SM_AMIGA_i_7_|NOD| | S |13 | 4 to [ 8]| 1 XOR to [ 8] as logic PT 9| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10| SM_AMIGA_4_|NOD| | S | 3 | 4 to [10]| 1 XOR free +10|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free -12| SM_AMIGA_3_|NOD| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT -13| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_5_|NOD| | S | 3 | 4 to [12]| 1 XOR free +13|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 to [13]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1394,22 +1399,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_i_7_|NOD| | S |14 |=> can support up to [ 15] logic PT(s) - 1| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 2| SM_AMIGA_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 3| | ? | | S | |=> can support up to [ 1] logic PT(s) - 4| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 5|inst_UDS_000_INT|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 6| N_165|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) + 0|inst_nEXP_SPACE_D0reg|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 2|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4|inst_CLK_000_NE|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 6|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) + 8| SM_AMIGA_i_7_|NOD| | S |13 |=> can support up to [ 14] logic PT(s) 9| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -10| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) -13| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 14] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) +10|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +13|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Node-Pin Assignments @@ -1419,20 +1424,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| SM_AMIGA_i_7_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1| SM_AMIGA_1_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 2| SM_AMIGA_2_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 0|inst_nEXP_SPACE_D0reg|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| SM_AMIGA_4_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2|CLK_000_N_SYNC_9_|NOD| | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 - 4| SM_AMIGA_5_|NOD| | => | 7 0 1 2 | 53 60 59 58 - 5|inst_UDS_000_INT|NOD| | => | 7 0 1 2 | 53 60 59 58 - 6| N_165|NOD| | => | 0 1 2 3 | 60 59 58 57 + 4|inst_CLK_000_NE|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 6|CLK_000_N_SYNC_0_|NOD| | => | 0 1 2 3 | 60 59 58 57 7| | | | => | 0 1 2 3 | 60 59 58 57 - 8|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 59 58 57 56 + 8| SM_AMIGA_i_7_|NOD| | => | 1 2 3 4 | 59 58 57 56 9| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 59 58 57 56 -10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 58 57 56 55 +10|CLK_000_P_SYNC_5_|NOD| | => | 2 3 4 5 | 58 57 56 55 11| | | | => | 2 3 4 5 | 58 57 56 55 -12| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 57 56 55 54 -13| inst_VPA_D|NOD| | => | 3 4 5 6 | 57 56 55 54 +12| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 57 56 55 54 +13|inst_AS_030_000_SYNC|NOD| | => | 3 4 5 6 | 57 56 55 54 14| | | | => | 4 5 6 7 | 56 55 54 53 15| | | | => | 4 5 6 7 | 56 55 54 53 --------------------------------------------------------------------------- @@ -1483,38 +1488,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60|INP A1|*|*] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD SM_AMIGA_i_7_| |*] - [MCell 1 |223|NOD SM_AMIGA_1_| |*] + [MCell 0 |221|NOD inst_nEXP_SPACE_D0reg| |*] + [MCell 1 |223|NOD SM_AMIGA_4_| |*] 1 [IOpin 1 | 59|INP A_17_|*|*] [RegIn 1 |225| -| | ] - [MCell 2 |224|NOD SM_AMIGA_2_| |*] + [MCell 2 |224|NOD CLK_000_N_SYNC_9_| |*] [MCell 3 |226| -| | ] 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD SM_AMIGA_5_| |*] - [MCell 5 |229|NOD inst_UDS_000_INT| |*] + [MCell 4 |227|NOD inst_CLK_000_NE| |*] + [MCell 5 |229|NOD SM_AMIGA_6_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] - [MCell 6 |230|NOD N_165| |*] + [MCell 6 |230|NOD CLK_000_N_SYNC_0_| |*] [MCell 7 |232| -| | ] 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233|NOD inst_CLK_000_D1| |*] + [MCell 8 |233|NOD SM_AMIGA_i_7_| |*] [MCell 9 |235|NOD SM_AMIGA_0_| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] - [MCell 10 |236|NOD SM_AMIGA_4_| |*] + [MCell 10 |236|NOD CLK_000_P_SYNC_5_| |*] [MCell 11 |238| -| | ] 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD SM_AMIGA_3_| |*] - [MCell 13 |241|NOD inst_VPA_D| |*] + [MCell 12 |239|NOD SM_AMIGA_5_| |*] + [MCell 13 |241|NOD inst_AS_030_000_SYNC| |*] 7 [IOpin 7 | 53| -| | ] [RegIn 7 |243| -| | ] @@ -1527,39 +1532,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| Mcel 2 13 ( 169)| SM_AMIGA_2_ Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 6 4 ( 251)| RN_E -Mux03| Mcel 3 2 ( 176)| cpu_est_2_ -Mux04| Mcel 3 6 ( 182)| cpu_est_0_ -Mux05| ... | ... -Mux06| Mcel 5 13 ( 241)| inst_VPA_D -Mux07| Mcel 2 8 ( 161)| inst_AS_030_000_SYNC -Mux08| Mcel 1 15 ( 148)| inst_CLK_000_NE_D0 -Mux09| Mcel 5 5 ( 229)| inst_UDS_000_INT -Mux10| Mcel 5 1 ( 223)| SM_AMIGA_1_ -Mux11| Mcel 5 6 ( 230)| N_165 -Mux12| Mcel 6 13 ( 265)| inst_CLK_000_D0 -Mux13| Input Pin ( 36)| VPA -Mux14| Mcel 2 4 ( 155)| SM_AMIGA_6_ -Mux15| IOPin 6 4 ( 69)| A0 -Mux16| ... | ... -Mux17| Mcel 5 12 ( 239)| SM_AMIGA_3_ -Mux18| Mcel 5 9 ( 235)| SM_AMIGA_0_ -Mux19| Mcel 5 10 ( 236)| SM_AMIGA_4_ -Mux20| Mcel 3 10 ( 188)| inst_DS_030_D0 -Mux21| Mcel 3 13 ( 193)| cpu_est_1_ -Mux22| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ +Mux03| Mcel 3 2 ( 176)| pos_clk_un29_clk_000_ne_d0_i_n +Mux04| IOPin 0 4 ( 95)| A_18_ +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| Mcel 2 8 ( 161)| SM_AMIGA_3_ +Mux08| IOPin 5 1 ( 59)| A_17_ +Mux09| Mcel 5 5 ( 229)| SM_AMIGA_6_ +Mux10| Mcel 6 14 ( 266)| CLK_000_N_SYNC_8_ +Mux11| IOPin 0 5 ( 96)| A_16_ +Mux12| IOPin 5 2 ( 58)| FC_1_ +Mux13| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux14| Mcel 5 4 ( 227)| inst_CLK_000_NE +Mux15| Mcel 5 13 ( 241)| inst_AS_030_000_SYNC +Mux16| Mcel 3 6 ( 182)| CLK_000_P_SYNC_4_ +Mux17| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux18| Mcel 1 2 ( 128)| inst_CLK_000_D0 +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Mcel 7 6 ( 278)| CLK_000_N_SYNC_11_ +Mux22| Mcel 2 1 ( 151)| SM_AMIGA_1_ Mux23| ... | ... -Mux24| ... | ... -Mux25| Mcel 3 9 ( 187)| inst_CLK_000_PE -Mux26| Mcel 3 0 ( 173)| RN_VMA -Mux27| Mcel 6 9 ( 259)| inst_CLK_000_NE -Mux28| Mcel 5 2 ( 224)| SM_AMIGA_2_ -Mux29| Mcel 5 4 ( 227)| SM_AMIGA_5_ -Mux30| ... | ... -Mux31| Mcel 3 15 ( 196)| inst_DTACK_D0 -Mux32| Mcel 5 8 ( 233)| inst_CLK_000_D1 +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 +Mux26| ... | ... +Mux27| IOPin 0 6 ( 97)| A_19_ +Mux28| ... | ... +Mux29| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux30| Mcel 5 1 ( 223)| SM_AMIGA_4_ +Mux31| Mcel 5 0 ( 221)| inst_nEXP_SPACE_D0reg +Mux32| Mcel 5 9 ( 235)| SM_AMIGA_0_ --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments @@ -1574,19 +1579,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| SIZE_DMA_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free - 3|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 3|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| E| IO| | S | 5 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5|inst_nEXP_SPACE_D0reg|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 5| cpu_est_1_|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT 6| SIZE_DMA_0_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free - 7|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 7|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig 8| A0| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9|inst_CLK_000_NE|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 9|inst_LDS_000_INT|NOD| | S | 4 | 4 to [ 9]| 1 XOR free 10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [10]| 1 XOR free -11|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +11| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig 12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [14]| 1 XOR free -15|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13|inst_UDS_000_INT|NOD| | S | 3 | 4 to [13]| 1 XOR free +14|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Maximum PT Capacity @@ -1601,19 +1606,19 @@ _|_________________|__|__|___|_____|_______________________________________ 0| RW| IO| | S | 2 |=> can support up to [ 9] logic PT(s) 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) 2| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 4| E| IO| | S | 5 |=> can support up to [ 13] logic PT(s) - 5|inst_nEXP_SPACE_D0reg|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 6| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) - 7|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 8| A0| IO| | S | 3 |=> can support up to [ 13] logic PT(s) - 9|inst_CLK_000_NE|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) -10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 17] logic PT(s) -11|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| E| IO| | S | 5 |=> can support up to [ 9] logic PT(s) + 5| cpu_est_1_|NOD| | S | 5 |=> can support up to [ 9] logic PT(s) + 6| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 7|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 8| A0| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 9|inst_LDS_000_INT|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) +10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) +11| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) 12| SIZE_0_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) -13|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -14|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) -15|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +13|inst_UDS_000_INT|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) +14|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1626,19 +1631,19 @@ _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) 2| SIZE_DMA_1_|NOD| | => | 6 7 0 1 | 71 72 65 66 - 3|CLK_000_N_SYNC_9_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3|CLK_000_N_SYNC_2_|NOD| | => | 6 7 0 1 | 71 72 65 66 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5|inst_nEXP_SPACE_D0reg|NOD| | => | 7 0 1 2 | 72 65 66 67 + 5| cpu_est_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 6| SIZE_DMA_0_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 7|CLK_000_P_SYNC_7_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 7|CLK_000_N_SYNC_1_|NOD| | => | 0 1 2 3 | 65 66 67 68 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9|inst_CLK_000_NE|NOD| | => | 1 2 3 4 | 66 67 68 69 + 9|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 66 67 68 69 10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 2 3 4 5 | 67 68 69 70 -11|CLK_000_P_SYNC_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 +11| IPL_D0_2_|NOD| | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13|inst_CLK_000_D0|NOD| | => | 3 4 5 6 | 68 69 70 71 -14|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 4 5 6 7 | 69 70 71 72 -15|inst_CLK_OUT_PRE_D|NOD| | => | 4 5 6 7 | 69 70 71 72 +13|inst_UDS_000_INT|NOD| | => | 3 4 5 6 | 68 69 70 71 +14|CLK_000_N_SYNC_8_|NOD| | => | 4 5 6 7 | 69 70 71 72 +15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO-to-Node Pin Mapping @@ -1696,37 +1701,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] [MCell 2 |248|NOD SIZE_DMA_1_| |*] - [MCell 3 |250|NOD CLK_000_N_SYNC_9_| |*] + [MCell 3 |250|NOD CLK_000_N_SYNC_2_| |*] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|NOD RN_E| |*] paired w/[ E] - [MCell 5 |253|NOD inst_nEXP_SPACE_D0reg| |*] + [MCell 5 |253|NOD cpu_est_1_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] [MCell 6 |254|NOD SIZE_DMA_0_| |*] - [MCell 7 |256|NOD CLK_000_P_SYNC_7_| |*] + [MCell 7 |256|NOD CLK_000_N_SYNC_1_| |*] 4 [IOpin 4 | 69| IO A0|*|*] paired w/[ RN_A0] [RegIn 4 |258| -| | ] [MCell 8 |257|NOD RN_A0| |*] paired w/[ A0] - [MCell 9 |259|NOD inst_CLK_000_NE| |*] + [MCell 9 |259|NOD inst_LDS_000_INT| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] [MCell 10 |260|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] - [MCell 11 |262|NOD CLK_000_P_SYNC_1_| |*] + [MCell 11 |262|NOD IPL_D0_2_| |*] 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] [RegIn 6 |264| -| | ] [MCell 12 |263| IO SIZE_0_| | ] - [MCell 13 |265|NOD inst_CLK_000_D0| |*] + [MCell 13 |265|NOD inst_UDS_000_INT| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] - [MCell 15 |268|NOD inst_CLK_OUT_PRE_D| |*] + [MCell 14 |266|NOD CLK_000_N_SYNC_8_| |*] + [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Logic Array Fan-in @@ -1735,38 +1740,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| Mcel 3 13 ( 193)| cpu_est_1_ -Mux02| Mcel 6 4 ( 251)| RN_E -Mux03| Mcel 3 11 ( 190)| CLK_000_P_SYNC_0_ -Mux04| Mcel 3 6 ( 182)| cpu_est_0_ -Mux05| Mcel 6 6 ( 254)| SIZE_DMA_0_ +Mux01| Mcel 5 6 ( 230)| CLK_000_N_SYNC_0_ +Mux02| Mcel 1 10 ( 140)| CLK_000_N_SYNC_7_ +Mux03| IOPin 5 0 ( 60)| A1 +Mux04| Mcel 6 2 ( 248)| SIZE_DMA_1_ +Mux05| Mcel 6 10 ( 260)| inst_AMIGA_BUS_ENABLE_DMA_HIGH Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 7 6 ( 278)| CLK_000_N_SYNC_11_ -Mux08| Mcel 1 15 ( 148)| inst_CLK_000_NE_D0 -Mux09| Mcel 1 14 ( 146)| RN_RESET -Mux10| Mcel 6 14 ( 266)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux11| IOPin 5 0 ( 60)| A1 -Mux12| IOPin 3 3 ( 32)| UDS_000 -Mux13| Mcel 6 8 ( 257)| RN_A0 -Mux14| Input Pin ( 11)| CLK_000 -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux07| Mcel 2 5 ( 157)| cpu_est_0_ +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 5 5 ( 229)| SM_AMIGA_6_ +Mux10| Mcel 6 8 ( 257)| RN_A0 +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 6 7 ( 256)| CLK_000_N_SYNC_1_ +Mux13| Mcel 3 7 ( 184)| inst_DS_030_D0 +Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux15| Mcel 2 12 ( 167)| cpu_est_2_ +Mux16| Mcel 4 8 ( 209)| inst_CLK_000_NE_D0 Mux17| Mcel 6 0 ( 245)| RN_RW -Mux18| ... | ... -Mux19| Mcel 0 9 ( 115)| inst_CLK_OUT_PRE_50 -Mux20| Mcel 0 14 ( 122)| CLK_000_N_SYNC_8_ +Mux18| IOPin 6 4 ( 69)| A0 +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux20| IOPin 7 6 ( 79)| SIZE_1_ Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 10 ( 260)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux23| Mcel 6 2 ( 248)| SIZE_DMA_1_ +Mux22| Mcel 6 5 ( 253)| cpu_est_1_ +Mux23| Mcel 6 6 ( 254)| SIZE_DMA_0_ Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| ... | ... -Mux26| Mcel 4 5 ( 205)| CLK_000_P_SYNC_6_ -Mux27| ... | ... -Mux28| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux25| Mcel 6 13 ( 265)| inst_UDS_000_INT +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 6 9 ( 259)| inst_LDS_000_INT +Mux28| ... | ... Mux29| ... | ... -Mux30| ... | ... -Mux31| ... | ... -Mux32| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg +Mux30| IOPin 6 3 ( 68)| IPL_2_ +Mux31| Mcel 5 0 ( 221)| inst_nEXP_SPACE_D0reg +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1782,7 +1787,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free - 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free + 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free 5|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free @@ -1809,7 +1814,7 @@ _|_________________|__|__|___|_____|_______________________________________ 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) 2|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 18] logic PT(s) + 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) 5|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 6|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 13] logic PT(s) @@ -1856,8 +1861,8 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| | | | 85| => | 0 1 2 3 4 5 6 7 - 1| | | | 84| => | 2 3 4 5 6 7 8 9 + 0| A_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 + 1| A_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 4| DSACK1| IO|*| 81| => | 8 ( 9) 10 11 12 13 14 15 @@ -1874,8 +1879,8 @@ _|_________________|__|___|_____|___________________________________________ | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ - 0| | | | 85| => | Input macrocell [ -] - 1| | | | 84| => | Input macrocell [ -] + 0| A_23_|INP|*| 85| => | Input macrocell [ -] + 1| A_22_|INP|*| 84| => | Input macrocell [ -] 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BGACK_030] 3| AS_030| IO|*| 82| => | Input macrocell [ -] @@ -1895,12 +1900,12 @@ IMX No. | +---- Block IO Pin or Macrocell Number | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ - 0 [IOpin 0 | 85| -| | ] + 0 [IOpin 0 | 85|INP A_23_|*|*] [RegIn 0 |270| -| | ] [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] [MCell 1 |271|OUT FPU_CS| | ] - 1 [IOpin 1 | 84| -| | ] + 1 [IOpin 1 | 84|INP A_22_|*|*] [RegIn 1 |273| -| | ] [MCell 2 |272|NOD CLK_000_N_SYNC_10_| |*] [MCell 3 |274| -| | ] @@ -1943,35 +1948,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 6 15 ( 268)| inst_CLK_OUT_PRE_D +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ Mux03| Mcel 0 8 ( 113)| inst_AS_000_DMA -Mux04| Mcel 7 5 ( 277)| inst_AS_030_D0 -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux06| IOPin 0 6 ( 97)| A_19_ -Mux07| Mcel 3 9 ( 187)| inst_CLK_000_PE -Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| Mcel 1 14 ( 146)| RN_RESET -Mux10| Mcel 5 4 ( 227)| SM_AMIGA_5_ -Mux11| IOPin 0 5 ( 96)| A_16_ +Mux04| IOPin 0 4 ( 95)| A_18_ +Mux05| Mcel 7 9 ( 283)| RN_DSACK1 +Mux06| IOPin 0 5 ( 96)| A_16_ +Mux07| ... | ... +Mux08| IOPin 5 1 ( 59)| A_17_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| ... | ... +Mux11| IOPin 6 6 ( 71)| RW Mux12| IOPin 5 2 ( 58)| FC_1_ -Mux13| IOPin 5 1 ( 59)| A_17_ -Mux14| Mcel 7 2 ( 272)| CLK_000_N_SYNC_10_ -Mux15| Mcel 5 1 ( 223)| SM_AMIGA_1_ +Mux13| Mcel 7 5 ( 277)| inst_AS_030_D0 +Mux14| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux15| Mcel 5 2 ( 224)| CLK_000_N_SYNC_9_ Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 5 3 ( 57)| FC_0_ +Mux17| Mcel 5 12 ( 239)| SM_AMIGA_5_ Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| IOPin 7 3 ( 82)| AS_030 +Mux19| IOPin 0 0 ( 91)| FPU_SENSE Mux20| Input Pin ( 64)| CLK_030 Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| inst_nEXP_SPACE_D0reg -Mux23| Mcel 6 2 ( 248)| SIZE_DMA_1_ -Mux24| Mcel 6 3 ( 250)| CLK_000_N_SYNC_9_ -Mux25| IOPin 6 6 ( 71)| RW -Mux26| ... | ... -Mux27| Mcel 7 9 ( 283)| RN_DSACK1 -Mux28| ... | ... +Mux22| Mcel 2 1 ( 151)| SM_AMIGA_1_ +Mux23| Mcel 4 13 ( 217)| inst_CLK_OUT_PRE_D +Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux25| Mcel 5 0 ( 221)| inst_nEXP_SPACE_D0reg +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| IOPin 0 6 ( 97)| A_19_ +Mux28| Mcel 7 2 ( 272)| CLK_000_N_SYNC_10_ Mux29| Mcel 6 6 ( 254)| SIZE_DMA_0_ Mux30| Mcel 7 0 ( 269)| RN_RW_000 -Mux31| IOPin 0 4 ( 95)| A_18_ +Mux31| Mcel 6 2 ( 248)| SIZE_DMA_1_ Mux32| Mcel 5 9 ( 235)| SM_AMIGA_0_ --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 3e80148..face428 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Thu Jul 09 18:49:07 2015 +Project Fitted on : Thu Sep 24 16:21:08 2015 Device : M4A5-128/64 Package : 100TQFP @@ -37,7 +37,7 @@ Fitter 00:00:00 Design_Summary ~~~~~~~~~~~~~~ - Total Input Pins : 28 + Total Input Pins : 32 Total Output Pins : 18 Total Bidir I/O Pins : 11 Total Flip-Flops : 83 @@ -53,14 +53,14 @@ Device_Resource_Summary Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% -I/O Pins 64 51 13 --> 79% -Logic Macrocells 128 101 27 --> 78% +I/O Pins 64 55 9 --> 85% +Logic Macrocells 128 102 26 --> 79% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 228 36 --> 86% +CSM Outputs/Total Block Inputs 264 237 27 --> 89% Logical Product Terms 640 253 387 --> 39% -Product Term Clusters 128 58 70 --> 45% +Product Term Clusters 128 59 69 --> 46%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 30 6 0 16 0 0 47 5 Lo -Block B 29 8 0 16 0 0 62 1 Lo -Block C 28 7 0 9 0 7 20 11 Lo -Block D 28 8 0 16 0 0 28 10 Lo -Block E 27 4 0 7 0 9 8 15 Lo -Block F 28 5 0 11 0 5 43 5 Lo -Block G 27 7 0 16 0 0 29 9 Lo -Block H 31 6 0 10 0 6 16 13 Lo +Block A 27 8 0 14 0 2 41 6 Lo +Block B 28 8 0 15 0 1 53 5 Lo +Block C 31 7 0 15 0 1 41 4 Lo +Block D 29 8 0 14 0 2 19 12 Lo +Block E 31 4 0 8 0 8 10 14 Lo +Block F 30 5 0 11 0 5 36 7 Lo +Block G 30 7 0 15 0 1 36 7 Lo +Block H 31 8 0 10 0 6 17 13 Lo --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -250,8 +250,8 @@ Pin No| Type |Pad |Pin | Signal name 81 | I_O | H4 | * |DSACK1 82 | I_O | H3 | * |AS_030 83 | I_O | H2 | * |BGACK_030 -84 | I_O | H1 | | -85 | I_O | H0 | | +84 | I_O | H1 | * |A_22_ +85 | I_O | H0 | * |A_23_ 86 | Inp | | * |RST 87 | Vcc | | | 88 | GND | | | @@ -259,8 +259,8 @@ Pin No| Type |Pad |Pin | Signal name 90 | Vcc | | | 91 | I_O | A0 | * |FPU_SENSE 92 | I_O | A1 | * |AVEC -93 | I_O | A2 | | -94 | I_O | A3 | | +93 | I_O | A2 | * |A_20_ +94 | I_O | A3 | * |A_21_ 95 | I_O | A4 | * |A_18_ 96 | I_O | A5 | * |A_16_ 97 | I_O | A6 | * |A_19_ @@ -287,11 +287,15 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O ------G- Low Slow A1 - 96 A . I/O --C-E--H Low Slow A_16_ - 59 F . I/O --C-E--H Low Slow A_17_ - 95 A . I/O --C-E--H Low Slow A_18_ - 97 A . I/O --C-E--H Low Slow A_19_ + 60 F . I/O --C---G- Low Slow A1 + 96 A . I/O ----EF-H Low Slow A_16_ + 59 F . I/O ----EF-H Low Slow A_17_ + 95 A . I/O ----EF-H Low Slow A_18_ + 97 A . I/O ----EF-H Low Slow A_19_ + 93 A . I/O ----E--- Low Slow A_20_ + 94 A . I/O ----E--- Low Slow A_21_ + 84 H . I/O ----E--- Low Slow A_22_ + 85 H . I/O ----E--- Low Slow A_23_ 19 C . I/O ----E--- Low Slow A_24_ 18 C . I/O ----E--- Low Slow A_25_ 17 C . I/O ----E--- Low Slow A_26_ @@ -302,16 +306,16 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 4 B . I/O ----E--- Low Slow A_31_ 28 D . I/O ----E--H Low Slow BGACK_000 21 C . I/O ---D---- Low Slow BG_030 - 30 D . I/O ---D---- Low Slow DTACK - 57 F . I/O --C-E--H Low Slow FC_0_ - 58 F . I/O --C-E--H Low Slow FC_1_ + 30 D . I/O -B------ Low Slow DTACK + 57 F . I/O ----EF-H Low Slow FC_0_ + 58 F . I/O ----EF-H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O -B------ Low Slow IPL_0_ - 56 F . I/O -BC----- Low Slow IPL_1_ - 68 G . I/O -B------ Low Slow IPL_2_ - 11 . . Ck/I ------G- - Slow CLK_000 - 14 . . Ck/I ------G- - Slow nEXP_SPACE - 36 . . Ded -----F-- - Slow VPA + 67 G . I/O -B-D---- Low Slow IPL_0_ + 56 F . I/O -B-D---- Low Slow IPL_1_ + 68 G . I/O -B----G- Low Slow IPL_2_ + 11 . . Ck/I -B------ - Slow CLK_000 + 14 . . Ck/I -----F-- - Slow nEXP_SPACE + 36 . . Ded ---D---- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI 64 . . Ck/I AB-----H - Slow CLK_030 86 . . Ded ABCD-FGH - Slow RST @@ -335,7 +339,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH 20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Low Slow AVEC - 83 H 2 DFF * * -------- Low Slow BGACK_030 + 83 H 3 DFF * * -------- Low Slow BGACK_030 29 D 2 DFF * * -------- Low Slow BG_000 47 E 1 COM -------- Low Slow CIIN 65 G 1 COM -------- Low Fast CLK_DIV_OUT @@ -363,16 +367,16 @@ Bidir_Signal_List Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 69 G 3 DFF * * -B---F-- Low Slow A0 + 69 G 3 DFF * * ------G- Low Slow A0 42 E 1 COM A---E--H Low Slow AS_000 82 H 1 COM ----E--H Low Slow AS_030 - 41 E 1 COM --C--F-H Low Slow BERR + 41 E 1 COM A-C--F-H Low Slow BERR 98 A 1 COM ---D---- Low Slow DS_030 31 D 1 COM A-----G- Low Slow LDS_000 - 71 G 2 DFF * * --C----H Low Slow RW + 71 G 2 DFF * * A------H Low Slow RW 80 H 3 DFF * * A---E-G- Low Slow RW_000 - 70 G 1 COM -B------ Low Slow SIZE_0_ - 79 H 1 COM -B------ Low Slow SIZE_1_ + 70 G 1 COM ------G- Low Slow SIZE_0_ + 79 H 1 COM ------G- Low Slow SIZE_1_ 32 D 1 COM A-----G- Low Slow UDS_000 ---------------------------------------------------------------------- @@ -389,90 +393,91 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - D7 D 1 DFF * * A------- Low Slow CLK_000_N_SYNC_0_ + E5 E 2 COM ----E--- Low Slow CIIN_0 + F6 F 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_0_ H2 H 1 DFF * * -------H Low Slow CLK_000_N_SYNC_10_ - H6 H 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_11_ - A15 A 1 DFF * * A------- Low Slow CLK_000_N_SYNC_1_ - A11 A 1 DFF * * A------- Low Slow CLK_000_N_SYNC_2_ - A7 A 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_3_ - D3 D 1 DFF * * A------- Low Slow CLK_000_N_SYNC_4_ - A3 A 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_5_ - D14 D 1 DFF * * ----E--- Low Slow CLK_000_N_SYNC_6_ - E8 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_7_ - A14 A 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_8_ - G3 G 1 DFF * * -------H Low Slow CLK_000_N_SYNC_9_ - D11 D 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_0_ - G11 G 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_1_ - B3 B 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_2_ - C9 C 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_3_ - B4 B 1 DFF * * ----E--- Low Slow CLK_000_P_SYNC_4_ - E9 E 1 DFF * * ----E--- Low Slow CLK_000_P_SYNC_5_ - E5 E 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_6_ - G7 G 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_7_ - C5 C 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_8_ - C2 C 1 DFF * * ---D---- Low Slow CLK_000_P_SYNC_9_ - A10 A 2 DFF * * A------- Low Slow CYCLE_DMA_0_ - A6 A 3 DFF * * A------- Low Slow CYCLE_DMA_1_ - B7 B 1 DFF * * -B------ Low Slow IPL_D0_0_ - C13 C 1 DFF * * -B------ Low Slow IPL_D0_1_ - B13 B 1 DFF * * -B------ Low Slow IPL_D0_2_ - F6 F 4 COM -----F-- Low Slow N_165 + H6 H 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_11_ + G7 G 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_1_ + G3 G 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_2_ + B7 B 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_3_ + B3 B 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_4_ + B14 B 1 DFF * * A------- Low Slow CLK_000_N_SYNC_5_ + A6 A 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_6_ + B10 B 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_7_ + G14 G 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_8_ + F2 F 1 DFF * * -------H Low Slow CLK_000_N_SYNC_9_ + D10 D 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_0_ + C11 C 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_1_ + B11 B 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_2_ + C7 C 1 DFF * * ---D---- Low Slow CLK_000_P_SYNC_3_ + D6 D 1 DFF * * -----F-- Low Slow CLK_000_P_SYNC_4_ + F10 F 1 DFF * * A------- Low Slow CLK_000_P_SYNC_5_ + A3 A 1 DFF * * A------- Low Slow CLK_000_P_SYNC_6_ + A14 A 1 DFF * * A------- Low Slow CLK_000_P_SYNC_7_ + A10 A 1 DFF * * A------- Low Slow CLK_000_P_SYNC_8_ + A7 A 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_9_ + A2 A 2 DFF * * A------- Low Slow CYCLE_DMA_0_ + A13 A 3 DFF * * A------- Low Slow CYCLE_DMA_1_ + D3 D 1 DFF * * -B------ Low Slow IPL_D0_0_ + D14 D 1 DFF * * -B------ Low Slow IPL_D0_1_ + G11 G 1 DFF * * -B------ Low Slow IPL_D0_2_ G8 G 3 DFF * * ------G- Low - RN_A0 --> A0 - H4 H 2 DFF * * A-CDE-GH Low - RN_BGACK_030 --> BGACK_030 + H4 H 3 DFF * * A-CDEFGH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF * * ---D---- Low - RN_BG_000 --> BG_000 H9 H 4 DFF * * -------H Low - RN_DSACK1 --> DSACK1 - G4 G 5 DFF * * ---D-FG- Low - RN_E --> E + G4 G 5 DFF * * --CD--G- Low - RN_E --> E B8 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ - B6 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ - B2 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ - B14 B 2 DFF * * AB-DE-GH Low - RN_RESET --> RESET + B12 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ + B4 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ + B0 B 2 DFF * * AB-DE-GH Low - RN_RESET --> RESET G0 G 2 DFF * * ------G- Low - RN_RW --> RW H0 H 3 DFF * * -------H Low - RN_RW_000 --> RW_000 - D0 D 3 TFF * * ---D-F-- Low - RN_VMA --> VMA - B10 B 3 DFF * * AB------ Low Slow RST_DLY_0_ - A1 A 4 DFF * * AB------ Low Slow RST_DLY_1_ - B5 B 5 DFF * * AB------ Low Slow RST_DLY_2_ - B0 B 6 DFF * * AB------ Low Slow RST_DLY_3_ - B12 B 2 TFF * * AB------ Low Slow RST_DLY_4_ - A12 A 4 TFF * * AB------ Low Slow RST_DLY_5_ - B11 B 3 TFF * * AB------ Low Slow RST_DLY_6_ - A5 A 2 DFF * * AB------ Low Slow RST_DLY_7_ + D0 D 3 TFF * * --CD---- Low - RN_VMA --> VMA + C6 C 3 DFF * * -BC----- Low Slow RST_DLY_0_ + B13 B 4 DFF * * -BC----- Low Slow RST_DLY_1_ + B5 B 5 DFF * * -BC----- Low Slow RST_DLY_2_ + C9 C 6 DFF * * -BC----- Low Slow RST_DLY_3_ + C14 C 2 TFF * * -BC----- Low Slow RST_DLY_4_ + B9 B 4 TFF * * -BC----- Low Slow RST_DLY_5_ + C2 C 3 TFF * * -BC----- Low Slow RST_DLY_6_ + C10 C 2 DFF * * -BC----- Low Slow RST_DLY_7_ G6 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_ G2 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_ F9 F 2 DFF * * -----F-H Low Slow SM_AMIGA_0_ - F1 F 3 DFF * * -----F-H Low Slow SM_AMIGA_1_ - F2 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_ - F12 F 5 TFF * * --C--F-- Low Slow SM_AMIGA_3_ - F10 F 3 DFF * * -----F-- Low Slow SM_AMIGA_4_ - F4 F 3 DFF * * --C--F-H Low Slow SM_AMIGA_5_ - C4 C 3 DFF * * -BC--F-- Low Slow SM_AMIGA_6_ - F0 F 14 DFF * * --CD---H Low Slow SM_AMIGA_i_7_ - D6 D 2 DFF * * ---D-FG- Low Slow cpu_est_0_ - D13 D 5 DFF * * ---D-FG- Low Slow cpu_est_1_ - D2 D 4 DFF * * ---D-FG- Low Slow cpu_est_2_ + C1 C 3 DFF * * --C--F-H Low Slow SM_AMIGA_1_ + C13 C 4 DFF * * --C--F-- Low Slow SM_AMIGA_2_ + C8 C 5 TFF * * A-C--F-- Low Slow SM_AMIGA_3_ + F1 F 3 DFF * * --C--F-- Low Slow SM_AMIGA_4_ + F12 F 3 DFF * * A----F-H Low Slow SM_AMIGA_5_ + F5 F 3 DFF * * -----FG- Low Slow SM_AMIGA_6_ + F8 F 13 DFF * * ---D-F-H Low Slow SM_AMIGA_i_7_ + C5 C 2 DFF * * --CD--G- Low Slow cpu_est_0_ + G5 G 5 DFF * * --CD--G- Low Slow cpu_est_1_ + C12 C 4 DFF * * --CD--G- Low Slow cpu_est_2_ G10 G 2 DFF * * ---D--G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - G14 G 2 DFF * * --C---G- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + C3 C 2 DFF * * --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW A8 A 7 DFF * * A------H Low Slow inst_AS_000_DMA - C1 C 2 DFF * * --C-E--- Low Slow inst_AS_000_INT - C8 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC - H5 H 1 DFF * * --CDE--H Low Slow inst_AS_030_D0 - H13 H 1 DFF * * --C---G- Low Slow inst_BGACK_030_INT_D - G13 G 1 DFF * * --CD-F-- Low Slow inst_CLK_000_D0 - F8 F 1 DFF * * --CD-F-- Low Slow inst_CLK_000_D1 - G9 G 1 DFF * * AB-D-F-- Low Slow inst_CLK_000_NE - B15 B 1 DFF * * ---D-FG- Low Slow inst_CLK_000_NE_D0 - D9 D 1 DFF * * A-CD-F-H Low Slow inst_CLK_000_PE - A2 A 8 DFF * * A------- Low Slow inst_CLK_030_H - A9 A 1 DFF * * A-----G- Low Slow inst_CLK_OUT_PRE_50 - G15 G 1 DFF * * -------H Low Slow inst_CLK_OUT_PRE_D - A13 A 9 DFF * * A------- Low Slow inst_DS_000_DMA - C12 C 3 DFF * * --CD---- Low Slow inst_DS_000_ENABLE - D10 D 1 DFF * * -B---F-- Low Slow inst_DS_030_D0 - D15 D 1 DFF * * -----F-- Low Slow inst_DTACK_D0 - B9 B 4 DFF * * -B-D---- Low Slow inst_LDS_000_INT - F5 F 3 DFF * * ---D-F-- Low Slow inst_UDS_000_INT - F13 F 1 DFF * * ---D-F-- Low Slow inst_VPA_D - G5 G 1 DFF * * A-CDEFGH Low Slow inst_nEXP_SPACE_D0reg + A1 A 2 DFF * * A---E--- Low Slow inst_AS_000_INT + F13 F 7 DFF * * -----F-- Low Slow inst_AS_030_000_SYNC + H5 H 1 DFF * * A--DEF-H Low Slow inst_AS_030_D0 + H13 H 1 DFF * * --C--FG- Low Slow inst_BGACK_030_INT_D + B2 B 1 DFF * * ---D-F-- Low Slow inst_CLK_000_D0 + D9 D 1 DFF * * ---D-F-- Low Slow inst_CLK_000_D1 + F4 F 1 DFF * * -BCDEF-- Low Slow inst_CLK_000_NE + E8 E 1 DFF * * --CD--G- Low Slow inst_CLK_000_NE_D0 + C4 C 1 DFF * * A-CD-F-H Low Slow inst_CLK_000_PE + A9 A 8 DFF * * A------- Low Slow inst_CLK_030_H + E9 E 1 DFF * * ----E--- Low Slow inst_CLK_OUT_PRE_50 + E13 E 1 DFF * * -------H Low Slow inst_CLK_OUT_PRE_D + A5 A 9 DFF * * A------- Low Slow inst_DS_000_DMA + A12 A 3 DFF * * A--D---- Low Slow inst_DS_000_ENABLE + D7 D 1 DFF * * ------G- Low Slow inst_DS_030_D0 + B6 B 1 DFF * * --CD---- Low Slow inst_DTACK_D0 + G9 G 4 DFF * * ---D--G- Low Slow inst_LDS_000_INT + G13 G 3 DFF * * ---D--G- Low Slow inst_UDS_000_INT + D13 D 1 DFF * * --CD---- Low Slow inst_VPA_D + F0 F 1 DFF * * A--DEFGH Low Slow inst_nEXP_SPACE_D0reg + D2 D 2 COM -----F-- Low Slow pos_clk_un29_clk_000_ne_d0_i_n ---------------------------------------------------------------------- Power : Hi = High @@ -487,119 +492,122 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - SIZE_0_{ H}:inst_LDS_000_INT{ B} - A_30_{ C}: CIIN{ E} - SIZE_1_{ I}:inst_LDS_000_INT{ B} - A_29_{ C}: CIIN{ E} - A_28_{ D}: CIIN{ E} - A_31_{ C}: CIIN{ E} - A_27_{ D}: CIIN{ E} - A_26_{ D}: CIIN{ E} - A_25_{ D}: CIIN{ E} - A_24_{ D}: CIIN{ E} + A_28_{ D}: CIIN{ E} CIIN_0{ E} + A_27_{ D}: CIIN{ E} CIIN_0{ E} + SIZE_1_{ I}:inst_LDS_000_INT{ G} + A_26_{ D}: CIIN{ E} CIIN_0{ E} + A_25_{ D}: CIIN{ E} CIIN_0{ E} + A_31_{ C}: CIIN{ E} CIIN_0{ E} + A_24_{ D}: CIIN{ E} CIIN_0{ E} + A_23_{ I}: CIIN{ E} CIIN_0{ E} + A_22_{ I}: CIIN{ E} CIIN_0{ E} + A_21_{ B}: CIIN{ E} CIIN_0{ E} IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_2_{ B} - FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + : IPL_D0_2_{ G} + A_20_{ B}: CIIN{ E} CIIN_0{ E} + A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} : inst_AS_030_D0{ H} + A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} - :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} - : CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} - A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + : BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} + A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} DS_030{ B}: UDS_000{ D} LDS_000{ D} inst_DS_030_D0{ D} - A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} UDS_000{ E}: A0{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A} - A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} SIZE_DMA_0_{ G} : SIZE_DMA_1_{ G} inst_CLK_030_H{ A} - A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} - nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ G} - BERR{ F}: DSACK1{ H}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} - :inst_AS_030_000_SYNC{ C} SM_AMIGA_3_{ F} SM_AMIGA_0_{ F} - : SM_AMIGA_6_{ C} SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} - : SM_AMIGA_2_{ F}inst_DS_000_ENABLE{ C} SM_AMIGA_i_7_{ F} + A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} + nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ F} + BERR{ F}: DSACK1{ H}inst_AS_000_INT{ A} SM_AMIGA_5_{ F} + :inst_AS_030_000_SYNC{ F} SM_AMIGA_3_{ C} SM_AMIGA_0_{ F} + : SM_AMIGA_6_{ F} SM_AMIGA_1_{ C} SM_AMIGA_4_{ F} + : SM_AMIGA_2_{ C}inst_DS_000_ENABLE{ A} SM_AMIGA_i_7_{ F} BG_030{ D}: BG_000{ D} BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} CLK_030{. }: CLK_EXP{ B} DSACK1{ H}inst_AS_000_DMA{ A} :inst_DS_000_DMA{ A} inst_CLK_030_H{ A} - CLK_000{. }:inst_CLK_000_D0{ G} - FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} + CLK_000{. }:inst_CLK_000_D0{ B} IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_1_{ C} - DTACK{ E}: inst_DTACK_D0{ D} + : IPL_D0_1_{ D} IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_0_{ B} - FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - VPA{. }: inst_VPA_D{ F} + : IPL_D0_0_{ D} + FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + DTACK{ E}: inst_DTACK_D0{ B} + VPA{. }: inst_VPA_D{ D} RST{. }: IPL_030_2_{ B} RW_000{ H} A0{ G} : BG_000{ D} BGACK_030{ H} IPL_030_1_{ B} : IPL_030_0_{ B} DSACK1{ H} VMA{ D} - : RESET{ B} RW{ G}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} inst_AS_030_D0{ H} - :inst_nEXP_SPACE_D0reg{ G} inst_DS_030_D0{ D}inst_AS_030_000_SYNC{ C} + : RESET{ B} RW{ G}inst_AS_000_INT{ A} + : SM_AMIGA_5_{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} inst_AS_030_D0{ H} + :inst_nEXP_SPACE_D0reg{ F} inst_DS_030_D0{ D}inst_AS_030_000_SYNC{ F} :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} - : SIZE_DMA_1_{ G} inst_VPA_D{ F}inst_UDS_000_INT{ F} - :inst_LDS_000_INT{ B} inst_DTACK_D0{ D} IPL_D0_0_{ B} - : IPL_D0_1_{ C} IPL_D0_2_{ B} SM_AMIGA_3_{ F} - : SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} SM_AMIGA_6_{ C} - : RST_DLY_0_{ B} RST_DLY_1_{ A} RST_DLY_2_{ B} - : RST_DLY_3_{ B} RST_DLY_4_{ B} RST_DLY_5_{ A} - : RST_DLY_6_{ B} RST_DLY_7_{ A} inst_CLK_030_H{ A} - : SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} SM_AMIGA_2_{ F} - :inst_DS_000_ENABLE{ C} SM_AMIGA_i_7_{ F} + : SIZE_DMA_1_{ G} inst_VPA_D{ D}inst_UDS_000_INT{ G} + :inst_LDS_000_INT{ G} inst_DTACK_D0{ B} IPL_D0_0_{ D} + : IPL_D0_1_{ D} IPL_D0_2_{ G} SM_AMIGA_3_{ C} + : SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} SM_AMIGA_6_{ F} + : RST_DLY_0_{ C} RST_DLY_1_{ B} RST_DLY_2_{ B} + : RST_DLY_3_{ C} RST_DLY_4_{ C} RST_DLY_5_{ B} + : RST_DLY_6_{ C} RST_DLY_7_{ C} inst_CLK_030_H{ A} + : SM_AMIGA_1_{ C} SM_AMIGA_4_{ F} SM_AMIGA_2_{ C} + :inst_DS_000_ENABLE{ A} SM_AMIGA_i_7_{ F} + SIZE_0_{ H}:inst_LDS_000_INT{ G} + A_30_{ C}: CIIN{ E} CIIN_0{ E} + A_29_{ C}: CIIN{ E} CIIN_0{ E} RN_IPL_030_2_{ C}: IPL_030_2_{ B} RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A} RN_RW_000{ I}: RW_000{ H} - A0{ H}:inst_UDS_000_INT{ F}inst_LDS_000_INT{ B} + A0{ H}:inst_UDS_000_INT{ G}inst_LDS_000_INT{ G} RN_A0{ H}: A0{ G} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: SIZE_0_{ G} SIZE_1_{ H} AS_030{ H} - : AS_000{ E} DS_030{ A} UDS_000{ D} - : LDS_000{ D}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} - :AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H} A0{ G} - : BGACK_030{ H} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} - :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A} +RN_BGACK_030{ I}: SIZE_1_{ H} AS_030{ H} AS_000{ E} + : DS_030{ A} UDS_000{ D} LDS_000{ D} + :AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} + : SIZE_0_{ G} RW_000{ H} A0{ G} + : BGACK_030{ H} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} + :inst_AS_030_000_SYNC{ F}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A} :inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} : inst_CLK_030_H{ A} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} RN_DSACK1{ I}: DSACK1{ H} - RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} - RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ C} SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} + : SM_AMIGA_2_{ C} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} + : SM_AMIGA_2_{ C} RN_RESET{ C}: AS_030{ H} AS_000{ E} DS_030{ A} : UDS_000{ D} LDS_000{ D} RW_000{ H} : A0{ G} RESET{ B} RW{ G} - RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ A} RN_RW{ H}: RW{ G} - N_165{ G}: SM_AMIGA_i_7_{ F} - cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} - : cpu_est_1_{ D} cpu_est_2_{ D} SM_AMIGA_3_{ F} - : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} - cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} -inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} -SM_AMIGA_5_{ G}: RW_000{ H} N_165{ F}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C} - : SM_AMIGA_i_7_{ F} -inst_AMIGA_BUS_ENABLE_DMA_LOW{ H}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} + cpu_est_0_{ D}: E{ G} VMA{ D} cpu_est_0_{ C} + : cpu_est_1_{ G} cpu_est_2_{ C} SM_AMIGA_3_{ C} + :pos_clk_un29_clk_000_ne_d0_i_n{ D} SM_AMIGA_2_{ C} + cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ C} SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} + : SM_AMIGA_2_{ C} +inst_AS_000_INT{ B}: AS_000{ E}inst_AS_000_INT{ A} +SM_AMIGA_5_{ G}: RW_000{ H}inst_AS_000_INT{ A} SM_AMIGA_5_{ F} + : SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ A} SM_AMIGA_i_7_{ F} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D} DSACK1{ H} - :inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ C} -inst_nEXP_SPACE_D0reg{ H}: SIZE_0_{ G} SIZE_1_{ H} AS_030{ H} - : DS_030{ A}AMIGA_BUS_DATA_DIR{ E} CIIN{ E} - : A0{ G} BG_000{ D} DSACK1{ H} - : N_165{ F}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C} -inst_DS_030_D0{ E}:inst_UDS_000_INT{ F}inst_LDS_000_INT{ B} -inst_AS_030_000_SYNC{ D}: N_165{ F}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C} -inst_BGACK_030_INT_D{ I}: A0{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} - :inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} + :inst_AS_000_INT{ A}inst_AS_030_000_SYNC{ F}inst_DS_000_ENABLE{ A} + : CIIN_0{ E} +inst_nEXP_SPACE_D0reg{ G}: SIZE_1_{ H} AS_030{ H} DS_030{ A} + :AMIGA_BUS_DATA_DIR{ E} SIZE_0_{ G} A0{ G} + : BG_000{ D} DSACK1{ H}inst_AS_030_000_SYNC{ F} + : SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} CIIN_0{ E} +inst_DS_030_D0{ E}:inst_UDS_000_INT{ G}inst_LDS_000_INT{ G} +inst_AS_030_000_SYNC{ G}:inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} +inst_BGACK_030_INT_D{ I}: A0{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} + :inst_AS_030_000_SYNC{ F} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : inst_CLK_030_H{ A} @@ -608,102 +616,101 @@ CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} : CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ A} : inst_CLK_030_H{ A} -SIZE_DMA_0_{ H}: SIZE_0_{ G} SIZE_1_{ H} SIZE_DMA_0_{ G} -SIZE_DMA_1_{ H}: SIZE_0_{ G} SIZE_1_{ H} SIZE_DMA_1_{ G} - inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G} +SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G} + inst_VPA_D{ E}: VMA{ D} SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} + : SM_AMIGA_2_{ C} +inst_UDS_000_INT{ H}: UDS_000{ D}inst_UDS_000_INT{ G} +inst_LDS_000_INT{ H}: LDS_000{ D}inst_LDS_000_INT{ G} +inst_CLK_OUT_PRE_D{ F}: DSACK1{ H} +inst_DTACK_D0{ C}: SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} SM_AMIGA_2_{ C} +inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_D{ E}inst_CLK_OUT_PRE_50{ E} +inst_CLK_000_D1{ E}: SM_AMIGA_6_{ F}CLK_000_P_SYNC_0_{ D}CLK_000_N_SYNC_0_{ F} : SM_AMIGA_i_7_{ F} -inst_UDS_000_INT{ G}: UDS_000{ D}inst_UDS_000_INT{ F} -inst_LDS_000_INT{ C}: LDS_000{ D}inst_LDS_000_INT{ B} -inst_CLK_OUT_PRE_D{ H}: DSACK1{ H} -inst_DTACK_D0{ E}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -inst_CLK_OUT_PRE_50{ B}:inst_CLK_OUT_PRE_D{ G}inst_CLK_OUT_PRE_50{ A} -inst_CLK_000_D1{ G}: N_165{ F} SM_AMIGA_6_{ C}CLK_000_P_SYNC_0_{ D} - :CLK_000_N_SYNC_0_{ D} -inst_CLK_000_D0{ H}: BG_000{ D} N_165{ F}inst_CLK_000_D1{ F} - : SM_AMIGA_6_{ C}CLK_000_P_SYNC_0_{ D}CLK_000_N_SYNC_0_{ D} -inst_CLK_000_PE{ E}: RW_000{ H} BGACK_030{ H} VMA{ D} +inst_CLK_000_D0{ C}: BG_000{ D}inst_CLK_000_D1{ D} SM_AMIGA_6_{ F} + :CLK_000_P_SYNC_0_{ D}CLK_000_N_SYNC_0_{ F} SM_AMIGA_i_7_{ F} +inst_CLK_000_PE{ D}: RW_000{ H} BGACK_030{ H} VMA{ D} : SM_AMIGA_5_{ F} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} - : SM_AMIGA_3_{ F} SM_AMIGA_0_{ F} SM_AMIGA_6_{ C} - : SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_3_{ C} SM_AMIGA_0_{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_1_{ C} SM_AMIGA_4_{ F} SM_AMIGA_2_{ C} : SM_AMIGA_i_7_{ F} -CLK_000_P_SYNC_9_{ D}:inst_CLK_000_PE{ D} -inst_CLK_000_NE{ H}: VMA{ D} RESET{ B} SM_AMIGA_5_{ F} - :inst_CLK_000_NE_D0{ B} SM_AMIGA_0_{ F} RST_DLY_0_{ B} - : RST_DLY_1_{ A} RST_DLY_2_{ B} RST_DLY_3_{ B} - : RST_DLY_4_{ B} RST_DLY_5_{ A} RST_DLY_6_{ B} - : RST_DLY_7_{ A} SM_AMIGA_1_{ F} SM_AMIGA_4_{ F} +CLK_000_P_SYNC_9_{ B}:inst_CLK_000_PE{ C} +inst_CLK_000_NE{ G}: VMA{ D} RESET{ B} SM_AMIGA_5_{ F} + :inst_CLK_000_NE_D0{ E} SM_AMIGA_0_{ F} RST_DLY_0_{ C} + : RST_DLY_1_{ B} RST_DLY_2_{ B} RST_DLY_3_{ C} + : RST_DLY_4_{ C} RST_DLY_5_{ B} RST_DLY_6_{ C} + : RST_DLY_7_{ C} SM_AMIGA_1_{ C} SM_AMIGA_4_{ F} : SM_AMIGA_i_7_{ F} -CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ G} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} - IPL_D0_0_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_1_{ D}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_2_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} -SM_AMIGA_3_{ G}: N_165{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - :inst_DS_000_ENABLE{ C} SM_AMIGA_i_7_{ F} -inst_CLK_000_NE_D0{ C}: E{ G} cpu_est_0_{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} -SM_AMIGA_0_{ G}: RW_000{ H} N_165{ F} SM_AMIGA_0_{ F} +CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ F} + cpu_est_2_{ D}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ C} SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} + : SM_AMIGA_2_{ C} + IPL_D0_0_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +SM_AMIGA_3_{ D}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C}inst_DS_000_ENABLE{ A} : SM_AMIGA_i_7_{ F} +inst_CLK_000_NE_D0{ F}: E{ G} cpu_est_0_{ C} cpu_est_1_{ G} + : cpu_est_2_{ C} SM_AMIGA_3_{ C}pos_clk_un29_clk_000_ne_d0_i_n{ D} + : SM_AMIGA_2_{ C} +SM_AMIGA_0_{ G}: RW_000{ H} SM_AMIGA_0_{ F} SM_AMIGA_i_7_{ F} inst_AMIGA_BUS_ENABLE_DMA_HIGH{ H}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G} -SM_AMIGA_6_{ D}: N_165{ F} SM_AMIGA_5_{ F}inst_UDS_000_INT{ F} - :inst_LDS_000_INT{ B} SM_AMIGA_6_{ C} SM_AMIGA_i_7_{ F} - RST_DLY_0_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_1_{ B}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_2_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_3_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_4_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_5_{ B}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_6_{ C}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} - RST_DLY_7_{ B}: RESET{ B} RST_DLY_0_{ B} RST_DLY_1_{ A} - : RST_DLY_2_{ B} RST_DLY_3_{ B} RST_DLY_4_{ B} - : RST_DLY_5_{ A} RST_DLY_6_{ B} RST_DLY_7_{ A} -CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ G} -CLK_000_P_SYNC_1_{ H}:CLK_000_P_SYNC_2_{ B} +SM_AMIGA_6_{ G}: SM_AMIGA_5_{ F}inst_UDS_000_INT{ G}inst_LDS_000_INT{ G} + : SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} + RST_DLY_0_{ D}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_1_{ C}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_2_{ C}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_3_{ D}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_4_{ D}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_5_{ C}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_6_{ D}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} + RST_DLY_7_{ D}: RESET{ B} RST_DLY_0_{ C} RST_DLY_1_{ B} + : RST_DLY_2_{ B} RST_DLY_3_{ C} RST_DLY_4_{ C} + : RST_DLY_5_{ B} RST_DLY_6_{ C} RST_DLY_7_{ C} +CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ C} +CLK_000_P_SYNC_1_{ D}:CLK_000_P_SYNC_2_{ B} CLK_000_P_SYNC_2_{ C}:CLK_000_P_SYNC_3_{ C} -CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ B} -CLK_000_P_SYNC_4_{ C}:CLK_000_P_SYNC_5_{ E} -CLK_000_P_SYNC_5_{ F}:CLK_000_P_SYNC_6_{ E} -CLK_000_P_SYNC_6_{ F}:CLK_000_P_SYNC_7_{ G} -CLK_000_P_SYNC_7_{ H}:CLK_000_P_SYNC_8_{ C} -CLK_000_P_SYNC_8_{ D}:CLK_000_P_SYNC_9_{ C} -CLK_000_N_SYNC_0_{ E}:CLK_000_N_SYNC_1_{ A} -CLK_000_N_SYNC_1_{ B}:CLK_000_N_SYNC_2_{ A} -CLK_000_N_SYNC_2_{ B}:CLK_000_N_SYNC_3_{ A} -CLK_000_N_SYNC_3_{ B}:CLK_000_N_SYNC_4_{ D} -CLK_000_N_SYNC_4_{ E}:CLK_000_N_SYNC_5_{ A} -CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ D} -CLK_000_N_SYNC_6_{ E}:CLK_000_N_SYNC_7_{ E} -CLK_000_N_SYNC_7_{ F}:CLK_000_N_SYNC_8_{ A} -CLK_000_N_SYNC_8_{ B}:CLK_000_N_SYNC_9_{ G} -CLK_000_N_SYNC_9_{ H}: DSACK1{ H}CLK_000_N_SYNC_10_{ H} +CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ D} +CLK_000_P_SYNC_4_{ E}:CLK_000_P_SYNC_5_{ F} +CLK_000_P_SYNC_5_{ G}:CLK_000_P_SYNC_6_{ A} +CLK_000_P_SYNC_6_{ B}:CLK_000_P_SYNC_7_{ A} +CLK_000_P_SYNC_7_{ B}:CLK_000_P_SYNC_8_{ A} +CLK_000_P_SYNC_8_{ B}:CLK_000_P_SYNC_9_{ A} +CLK_000_N_SYNC_0_{ G}:CLK_000_N_SYNC_1_{ G} +CLK_000_N_SYNC_1_{ H}:CLK_000_N_SYNC_2_{ G} +CLK_000_N_SYNC_2_{ H}:CLK_000_N_SYNC_3_{ B} +CLK_000_N_SYNC_3_{ C}:CLK_000_N_SYNC_4_{ B} +CLK_000_N_SYNC_4_{ C}:CLK_000_N_SYNC_5_{ B} +pos_clk_un29_clk_000_ne_d0_i_n{ E}: SM_AMIGA_i_7_{ F} +CLK_000_N_SYNC_5_{ C}:CLK_000_N_SYNC_6_{ A} +CLK_000_N_SYNC_6_{ B}:CLK_000_N_SYNC_7_{ B} +CLK_000_N_SYNC_7_{ C}:CLK_000_N_SYNC_8_{ G} +CLK_000_N_SYNC_8_{ H}:CLK_000_N_SYNC_9_{ F} +CLK_000_N_SYNC_9_{ G}: DSACK1{ H}CLK_000_N_SYNC_10_{ H} CLK_000_N_SYNC_10_{ I}: DSACK1{ H}CLK_000_N_SYNC_11_{ H} inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A} -SM_AMIGA_1_{ G}: DSACK1{ H} N_165{ F} SM_AMIGA_0_{ F} - : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} -SM_AMIGA_4_{ G}: N_165{ F} SM_AMIGA_3_{ F} SM_AMIGA_4_{ F} +SM_AMIGA_1_{ D}: DSACK1{ H} SM_AMIGA_0_{ F} SM_AMIGA_1_{ C} : SM_AMIGA_i_7_{ F} -SM_AMIGA_2_{ G}: N_165{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} - : SM_AMIGA_i_7_{ F} -inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C} -SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H}inst_AS_030_000_SYNC{ C} - : SM_AMIGA_6_{ C} +SM_AMIGA_4_{ G}: SM_AMIGA_3_{ C} SM_AMIGA_4_{ F} SM_AMIGA_i_7_{ F} +SM_AMIGA_2_{ D}: SM_AMIGA_1_{ C} SM_AMIGA_2_{ C} SM_AMIGA_i_7_{ F} +inst_DS_000_ENABLE{ B}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ A} +SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H}inst_AS_030_000_SYNC{ F} + : SM_AMIGA_6_{ F} + CIIN_0{ F}: CIIN{ E} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -722,23 +729,23 @@ Equations : | | | | | DS_030 | | | | | AVEC | * | S | BS | BR | inst_AS_000_DMA -| * | S | BS | BR | RST_DLY_5_ -| * | S | BS | BR | RST_DLY_1_ -| * | S | BS | BR | RST_DLY_7_ -| * | S | BS | BR | inst_CLK_OUT_PRE_50 +| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | inst_AS_000_INT | * | S | BS | BR | inst_DS_000_DMA | * | S | BS | BR | inst_CLK_030_H | * | S | BS | BR | CYCLE_DMA_1_ | * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | CLK_000_N_SYNC_8_ -| * | S | BS | BR | CLK_000_N_SYNC_5_ -| * | S | BS | BR | CLK_000_N_SYNC_3_ -| * | S | BS | BR | CLK_000_N_SYNC_2_ -| * | S | BS | BR | CLK_000_N_SYNC_1_ +| * | S | BS | BR | CLK_000_N_SYNC_6_ +| * | S | BS | BR | CLK_000_P_SYNC_8_ +| * | S | BS | BR | CLK_000_P_SYNC_7_ +| * | S | BS | BR | CLK_000_P_SYNC_6_ +| * | S | BS | BR | CLK_000_P_SYNC_9_ | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ | | | | | FPU_SENSE +| | | | | A_21_ +| | | | | A_20_ Block B @@ -748,26 +755,25 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | RST_DLY_3_ -| | | | | CLK_EXP | * | S | BS | BR | IPL_030_2_ -| * | S | BS | BR | CLK_000_P_SYNC_2_ -| * | S | BS | BR | CLK_000_P_SYNC_4_ -| * | S | BS | BR | RST_DLY_2_ -| * | S | BS | BR | IPL_030_1_ -| * | S | BS | BR | IPL_D0_0_ | * | S | BS | BR | IPL_030_0_ -| * | S | BS | BR | inst_LDS_000_INT -| * | S | BS | BR | RST_DLY_0_ -| * | S | BS | BR | RST_DLY_6_ -| * | S | BS | BR | RST_DLY_4_ +| * | S | BS | BR | IPL_030_1_ | * | S | BS | BR | RESET -| * | S | BS | BR | IPL_D0_2_ -| * | S | BS | BR | inst_CLK_000_NE_D0 -| * | S | BS | BR | RN_IPL_030_2_ -| * | S | BS | BR | RN_IPL_030_1_ -| * | S | BS | BR | RN_IPL_030_0_ +| | | | | CLK_EXP | * | S | BS | BR | RN_RESET +| * | S | BS | BR | RST_DLY_2_ +| * | S | BS | BR | RST_DLY_5_ +| * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | inst_CLK_000_D0 +| * | S | BS | BR | inst_DTACK_D0 +| * | S | BS | BR | RN_IPL_030_0_ +| * | S | BS | BR | RN_IPL_030_1_ +| * | S | BS | BR | RN_IPL_030_2_ +| * | S | BS | BR | CLK_000_N_SYNC_7_ +| * | S | BS | BR | CLK_000_N_SYNC_5_ +| * | S | BS | BR | CLK_000_N_SYNC_4_ +| * | S | BS | BR | CLK_000_N_SYNC_3_ +| * | S | BS | BR | CLK_000_P_SYNC_2_ | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ @@ -781,14 +787,20 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AMIGA_BUS_ENABLE_LOW -| * | S | BS | BR | SM_AMIGA_6_ -| * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | inst_DS_000_ENABLE -| * | S | BS | BR | inst_AS_000_INT -| * | S | BS | BR | CLK_000_P_SYNC_8_ +| * | S | BS | BR | inst_CLK_000_PE +| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | cpu_est_2_ +| * | S | BS | BR | SM_AMIGA_1_ +| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | RST_DLY_3_ +| * | S | BS | BR | SM_AMIGA_2_ +| * | S | BS | BR | RST_DLY_6_ +| * | S | BS | BR | RST_DLY_0_ +| * | S | BS | BR | RST_DLY_7_ +| * | S | BS | BR | RST_DLY_4_ +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | * | S | BS | BR | CLK_000_P_SYNC_3_ -| * | S | BS | BR | IPL_D0_1_ -| * | S | BS | BR | CLK_000_P_SYNC_9_ +| * | S | BS | BR | CLK_000_P_SYNC_1_ | | | | | BG_030 | | | | | A_24_ | | | | | A_25_ @@ -810,18 +822,16 @@ Equations : | | | | | AMIGA_BUS_ENABLE_HIGH | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE -| * | S | BS | BR | inst_CLK_000_PE -| * | S | BS | BR | cpu_est_1_ -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | cpu_est_0_ | * | S | BS | BR | RN_VMA -| * | S | BS | BR | inst_DS_030_D0 +| * | S | BS | BR | inst_CLK_000_D1 +| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | RN_BG_000 -| * | S | BS | BR | CLK_000_N_SYNC_6_ -| * | S | BS | BR | CLK_000_N_SYNC_4_ -| * | S | BS | BR | CLK_000_N_SYNC_0_ +| | | | | pos_clk_un29_clk_000_ne_d0_i_n +| * | S | BS | BR | CLK_000_P_SYNC_4_ | * | S | BS | BR | CLK_000_P_SYNC_0_ -| * | S | BS | BR | inst_DTACK_D0 +| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | IPL_D0_0_ +| * | S | BS | BR | inst_DS_030_D0 | | | | | BGACK_000 | | | | | DTACK @@ -833,13 +843,14 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| | | | | AS_000 | | | | | BERR +| | | | | AS_000 | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN -| * | S | BS | BR | CLK_000_N_SYNC_7_ -| * | S | BS | BR | CLK_000_P_SYNC_6_ -| * | S | BS | BR | CLK_000_P_SYNC_5_ +| * | S | BS | BR | inst_CLK_000_NE_D0 +| | | | | CIIN_0 +| * | S | BS | BR | inst_CLK_OUT_PRE_50 +| * | S | BS | BR | inst_CLK_OUT_PRE_D Block F @@ -849,22 +860,22 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_nEXP_SPACE_D0reg +| * | S | BS | BR | inst_CLK_000_NE | * | S | BS | BR | SM_AMIGA_i_7_ | * | S | BS | BR | SM_AMIGA_5_ -| * | S | BS | BR | inst_CLK_000_D1 -| * | S | BS | BR | SM_AMIGA_3_ -| * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | inst_UDS_000_INT -| * | S | BS | BR | SM_AMIGA_0_ -| * | S | BS | BR | inst_VPA_D -| * | S | BS | BR | SM_AMIGA_2_ -| | | | | N_165 | * | S | BS | BR | SM_AMIGA_4_ +| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | SM_AMIGA_0_ +| * | S | BS | BR | inst_AS_030_000_SYNC +| * | S | BS | BR | CLK_000_N_SYNC_9_ +| * | S | BS | BR | CLK_000_N_SYNC_0_ +| * | S | BS | BR | CLK_000_P_SYNC_5_ | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ -| | | | | IPL_1_ | | | | | A1 +| | | | | IPL_1_ Block G @@ -874,25 +885,24 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | A0 | * | S | BS | BR | RW +| * | S | BS | BR | A0 | | | | | SIZE_0_ | * | S | BS | BR | E | | | | | CLK_DIV_OUT -| * | S | BS | BR | inst_nEXP_SPACE_D0reg -| * | S | BS | BR | inst_CLK_000_NE | * | S | BS | BR | RN_E -| * | S | BS | BR | inst_CLK_000_D0 +| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | inst_UDS_000_INT | * | S | BS | BR | SIZE_DMA_1_ | * | S | BS | BR | SIZE_DMA_0_ | * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | * | S | BS | BR | RN_A0 | * | S | BS | BR | RN_RW -| * | S | BS | BR | CLK_000_N_SYNC_9_ -| * | S | BS | BR | CLK_000_P_SYNC_7_ -| * | S | BS | BR | CLK_000_P_SYNC_1_ -| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | CLK_000_N_SYNC_8_ +| * | S | BS | BR | CLK_000_N_SYNC_2_ +| * | S | BS | BR | CLK_000_N_SYNC_1_ +| * | S | BS | BR | IPL_D0_2_ | | | | | IPL_2_ | | | | | IPL_0_ @@ -917,6 +927,8 @@ Equations : | * | S | BS | BR | RN_RW_000 | * | S | BS | BR | CLK_000_N_SYNC_10_ | * | S | BS | BR | CLK_000_N_SYNC_11_ +| | | | | A_23_ +| | | | | A_22_ (S) means the macrocell is configured in synchronous mode @@ -933,22 +945,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 RST pin 86 mx A17 RST_DLY_6_ mcell B11 -mx A1 RST_DLY_4_ mcell B12 mx A18 RST_DLY_7_ mcell A5 -mx A2 RST_DLY_0_ mcell B10 mx A19inst_CLK_OUT_PRE_50 mcell A9 -mx A3 inst_AS_000_DMA mcell A8 mx A20 UDS_000 pin 32 -mx A4 CLK_030 pin 64 mx A21CLK_000_N_SYNC_0_ mcell D7 -mx A5 ... ... mx A22CLK_000_N_SYNC_4_ mcell D3 -mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4 -mx A7CLK_000_N_SYNC_2_ mcell A11 mx A24 LDS_000 pin 31 -mx A8CLK_000_N_SYNC_7_ mcell E8 mx A25 inst_CLK_030_H mcell A2 -mx A9 RST_DLY_1_ mcell A1 mx A26 RST_DLY_3_ mcell B0 -mx A10 CYCLE_DMA_1_ mcell A6 mx A27 inst_CLK_000_NE mcell G9 -mx A11 ... ... mx A28 inst_DS_000_DMA mcell A13 -mx A12 inst_CLK_000_PE mcell D9 mx A29 RN_RESET mcell B14 -mx A13CLK_000_N_SYNC_1_ mcell A15 mx A30 ... ... -mx A14 CYCLE_DMA_0_ mcell A10 mx A31 RST_DLY_2_ mcell B5 -mx A15 RST_DLY_5_ mcell A12 mx A32inst_nEXP_SPACE_D0reg mcell G5 +mx A0 CYCLE_DMA_1_ mcell A13 mx A17 BERR pin 41 +mx A1 SM_AMIGA_5_ mcell F12 mx A18 inst_DS_000_DMA mcell A5 +mx A2CLK_000_P_SYNC_5_ mcell F10 mx A19 inst_CLK_030_H mcell A9 +mx A3CLK_000_P_SYNC_7_ mcell A14 mx A20 RN_BGACK_030 mcell H4 +mx A4 CLK_030 pin 64 mx A21 RST pin 86 +mx A5inst_nEXP_SPACE_D0reg mcell F0 mx A22 CYCLE_DMA_0_ mcell A2 +mx A6 inst_CLK_000_PE mcell C4 mx A23 ... ... +mx A7 SM_AMIGA_3_ mcell C8 mx A24 LDS_000 pin 31 +mx A8 UDS_000 pin 32 mx A25CLK_000_P_SYNC_6_ mcell A3 +mx A9CLK_000_N_SYNC_5_ mcell B14 mx A26 RN_RESET mcell B0 +mx A10 ... ... mx A27 ... ... +mx A11 RW pin 71 mx A28 RW_000 pin 80 +mx A12 inst_AS_000_INT mcell A1 mx A29 ... ... +mx A13 inst_AS_030_D0 mcell H5 mx A30 inst_AS_000_DMA mcell A8 +mx A14CLK_000_P_SYNC_8_ mcell A10 mx A31 ... ... +mx A15inst_DS_000_ENABLE mcell A12 mx A32 ... ... mx A16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -957,22 +969,22 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 A0 pin 69 mx B17 SIZE_0_ pin 70 -mx B1 RST_DLY_4_ mcell B12 mx B18 RN_IPL_030_2_ mcell B2 -mx B2 inst_DS_030_D0 mcell D10 mx B19 ... ... -mx B3CLK_000_P_SYNC_3_ mcell C9 mx B20 SIZE_1_ pin 79 -mx B4 CLK_030 pin 64 mx B21 IPL_1_ pin 56 -mx B5 ... ... mx B22 IPL_2_ pin 68 -mx B6inst_LDS_000_INT mcell B9 mx B23 ... ... -mx B7 RST_DLY_6_ mcell B11 mx B24 RST pin 86 +mx B0 RN_RESET mcell B0 mx B17 IPL_D0_1_ mcell D14 +mx B1CLK_000_N_SYNC_3_ mcell B7 mx B18 RST_DLY_7_ mcell C10 +mx B2 RST_DLY_6_ mcell C2 mx B19CLK_000_N_SYNC_4_ mcell B3 +mx B3 CLK_000 pin 11 mx B20 CLK_030 pin 64 +mx B4 IPL_2_ pin 68 mx B21 IPL_1_ pin 56 +mx B5CLK_000_N_SYNC_2_ mcell G3 mx B22 ... ... +mx B6 RST_DLY_5_ mcell B9 mx B23 RST_DLY_3_ mcell C9 +mx B7 RST_DLY_4_ mcell C14 mx B24 RST pin 86 mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ... -mx B9 RST_DLY_1_ mcell A1 mx B26 RST_DLY_3_ mcell B0 -mx B10 IPL_D0_2_ mcell B13 mx B27 inst_CLK_000_NE mcell G9 -mx B11 RN_IPL_030_1_ mcell B6 mx B28 RST_DLY_7_ mcell A5 -mx B12 RST_DLY_0_ mcell B10 mx B29 RN_RESET mcell B14 -mx B13CLK_000_P_SYNC_1_ mcell G11 mx B30 IPL_D0_1_ mcell C13 -mx B14 SM_AMIGA_6_ mcell C4 mx B31 RST_DLY_2_ mcell B5 -mx B15 RST_DLY_5_ mcell A12 mx B32 IPL_D0_0_ mcell B7 +mx B9 RST_DLY_0_ mcell C6 mx B26 IPL_D0_2_ mcell G11 +mx B10 inst_CLK_000_NE mcell F4 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 RST_DLY_1_ mcell B13 +mx B12 RN_IPL_030_1_ mcell B12 mx B29CLK_000_P_SYNC_1_ mcell C11 +mx B13 IPL_D0_0_ mcell D3 mx B30 ... ... +mx B14 DTACK pin 30 mx B31 RST_DLY_2_ mcell B5 +mx B15CLK_000_N_SYNC_6_ mcell A6 mx B32 ... ... mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -981,23 +993,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 RST pin 86 mx C17 SM_AMIGA_3_ mcell F12 -mx C1 BERR pin 41 mx C18 ... ... -mx C2 inst_CLK_000_D1 mcell F8 mx C19inst_BGACK_030_INT_D mcell H13 -mx C3 IPL_1_ pin 56 mx C20 RN_BGACK_030 mcell H4 -mx C4inst_DS_000_ENABLE mcell C12 mx C21 ... ... -mx C5CLK_000_P_SYNC_2_ mcell B3 mx C22 inst_AS_000_INT mcell C1 -mx C6 A_16_ pin 96 mx C23 ... ... -mx C7 inst_CLK_000_PE mcell D9 mx C24 FC_0_ pin 57 -mx C8 A_17_ pin 59 mx C25 SM_AMIGA_i_7_ mcell F0 -mx C9 inst_CLK_000_D0 mcell G13 mx C26CLK_000_P_SYNC_7_ mcell G7 -mx C10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G14 mx C27 A_19_ pin 97 -mx C11 RW pin 71 mx C28 ... ... -mx C12 FC_1_ pin 58 mx C29 SM_AMIGA_6_ mcell C4 -mx C13 inst_AS_030_D0 mcell H5 mx C30 ... ... -mx C14 SM_AMIGA_5_ mcell F4 mx C31 A_18_ pin 95 -mx C15CLK_000_P_SYNC_8_ mcell C5 mx C32inst_nEXP_SPACE_D0reg mcell G5 -mx C16inst_AS_030_000_SYNC mcell C8 +mx C0 RST_DLY_2_ mcell B5 mx C17CLK_000_P_SYNC_2_ mcell B11 +mx C1 SM_AMIGA_1_ mcell C1 mx C18 RST_DLY_7_ mcell C10 +mx C2CLK_000_P_SYNC_0_ mcell D10 mx C19inst_BGACK_030_INT_D mcell H13 +mx C3 A1 pin 60 mx C20 RN_BGACK_030 mcell H4 +mx C4 cpu_est_2_ mcell C12 mx C21 RST_DLY_1_ mcell B13 +mx C5 ... ... mx C22 cpu_est_1_ mcell G5 +mx C6 RST_DLY_5_ mcell B9 mx C23 inst_DTACK_D0 mcell B6 +mx C7 cpu_est_0_ mcell C5 mx C24 RST pin 86 +mx C8inst_CLK_000_NE_D0 mcell E8 mx C25 BERR pin 41 +mx C9 RST_DLY_0_ mcell C6 mx C26 RN_VMA mcell D0 +mx C10 inst_CLK_000_NE mcell F4 mx C27 ... ... +mx C11 RN_E mcell G4 mx C28CLK_000_P_SYNC_9_ mcell A7 +mx C12inst_AMIGA_BUS_ENABLE_DMA_LOW mcell C3 mx C29 inst_VPA_D mcell D13 +mx C13 RST_DLY_3_ mcell C9 mx C30 SM_AMIGA_2_ mcell C13 +mx C14 inst_CLK_000_PE mcell C4 mx C31 RST_DLY_4_ mcell C14 +mx C15 SM_AMIGA_4_ mcell F1 mx C32 RST_DLY_6_ mcell C2 +mx C16 SM_AMIGA_3_ mcell C8 ---------------------------------------------------------------------------- @@ -1005,23 +1017,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RST pin 86 mx D17 RN_BG_000 mcell D1 -mx D1CLK_000_N_SYNC_3_ mcell A7 mx D18 RN_VMA mcell D0 -mx D2CLK_000_P_SYNC_9_ mcell C2 mx D19 ... ... -mx D3 cpu_est_2_ mcell D2 mx D20 inst_CLK_000_D1 mcell F8 -mx D4inst_DS_000_ENABLE mcell C12 mx D21 cpu_est_1_ mcell D13 -mx D5 DS_030 pin 98 mx D22inst_nEXP_SPACE_D0reg mcell G5 -mx D6CLK_000_N_SYNC_5_ mcell A3 mx D23 RN_BGACK_030 mcell H4 -mx D7 inst_CLK_000_PE mcell D9 mx D24 ... ... -mx D8inst_CLK_000_NE_D0 mcell B15 mx D25 SM_AMIGA_i_7_ mcell F0 -mx D9 DTACK pin 30 mx D26 ... ... -mx D10 inst_CLK_000_NE mcell G9 mx D27inst_UDS_000_INT mcell F5 -mx D11 RN_E mcell G4 mx D28inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G10 -mx D12 inst_CLK_000_D0 mcell G13 mx D29 RN_RESET mcell B14 -mx D13 inst_AS_030_D0 mcell H5 mx D30 cpu_est_0_ mcell D6 +mx D0 RN_BGACK_030 mcell H4 mx D17 RN_BG_000 mcell D1 +mx D1 inst_VPA_D mcell D13 mx D18 RN_VMA mcell D0 +mx D2 RN_E mcell G4 mx D19 ... ... +mx D3 cpu_est_1_ mcell G5 mx D20 SM_AMIGA_i_7_ mcell F8 +mx D4 inst_AS_030_D0 mcell H5 mx D21 IPL_1_ pin 56 +mx D5 DS_030 pin 98 mx D22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G10 +mx D6 inst_CLK_000_PE mcell C4 mx D23 cpu_est_2_ mcell C12 +mx D7 inst_CLK_000_D1 mcell D9 mx D24 RST pin 86 +mx D8inst_CLK_000_NE_D0 mcell E8 mx D25inst_nEXP_SPACE_D0reg mcell F0 +mx D9inst_DS_000_ENABLE mcell A12 mx D26 RN_RESET mcell B0 +mx D10 inst_CLK_000_D0 mcell B2 mx D27inst_LDS_000_INT mcell G9 +mx D11 inst_DTACK_D0 mcell B6 mx D28 cpu_est_0_ mcell C5 +mx D12inst_UDS_000_INT mcell G13 mx D29 inst_CLK_000_NE mcell F4 +mx D13 VPA pin 36 mx D30 ... ... mx D14 BG_030 pin 21 mx D31 ... ... -mx D15 inst_VPA_D mcell F13 mx D32 ... ... -mx D16inst_LDS_000_INT mcell B9 +mx D15CLK_000_P_SYNC_3_ mcell C7 mx D32 ... ... +mx D16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -1029,22 +1041,22 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0CLK_000_P_SYNC_4_ mcell B4 mx E17 FC_0_ pin 57 -mx E1 A_31_ pin 4 mx E18 BGACK_000 pin 28 -mx E2CLK_000_P_SYNC_5_ mcell E9 mx E19 A_30_ pin 5 -mx E3inst_nEXP_SPACE_D0reg mcell G5 mx E20 FC_1_ pin 58 +mx E0 RN_RESET mcell B0 mx E17 A_26_ pin 17 +mx E1 FC_1_ pin 58 mx E18 A_23_ pin 85 +mx E2inst_CLK_OUT_PRE_50 mcell E9 mx E19 A_30_ pin 5 +mx E3 CIIN_0 mcell E5 mx E20 A_22_ pin 84 mx E4 inst_AS_030_D0 mcell H5 mx E21 A_27_ pin 16 -mx E5 A_24_ pin 19 mx E22 inst_AS_000_INT mcell C1 -mx E6 A_16_ pin 96 mx E23 RN_BGACK_030 mcell H4 +mx E5inst_nEXP_SPACE_D0reg mcell F0 mx E22 A_25_ pin 18 +mx E6 FC_0_ pin 57 mx E23 RN_BGACK_030 mcell H4 mx E7 A_28_ pin 15 mx E24 ... ... -mx E8 A_17_ pin 59 mx E25 ... ... -mx E9 A_26_ pin 17 mx E26 ... ... -mx E10CLK_000_N_SYNC_6_ mcell D14 mx E27 A_19_ pin 97 +mx E8 A_17_ pin 59 mx E25 A_31_ pin 4 +mx E9 AS_030 pin 82 mx E26 A_16_ pin 96 +mx E10 inst_CLK_000_NE mcell F4 mx E27 A_19_ pin 97 mx E11 FPU_SENSE pin 91 mx E28 RW_000 pin 80 -mx E12 A_25_ pin 18 mx E29 RN_RESET mcell B14 +mx E12 inst_AS_000_INT mcell A1 mx E29 A_20_ pin 93 mx E13 A_29_ pin 6 mx E30 ... ... -mx E14 ... ... mx E31 A_18_ pin 95 -mx E15 ... ... mx E32 AS_030 pin 82 +mx E14 A_24_ pin 19 mx E31 A_18_ pin 95 +mx E15 A_21_ pin 94 mx E32 BGACK_000 pin 28 mx E16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -1053,23 +1065,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0 RST pin 86 mx F17 SM_AMIGA_3_ mcell F12 -mx F1 BERR pin 41 mx F18 SM_AMIGA_0_ mcell F9 -mx F2 RN_E mcell G4 mx F19 SM_AMIGA_4_ mcell F10 -mx F3 cpu_est_2_ mcell D2 mx F20 inst_DS_030_D0 mcell D10 -mx F4 cpu_est_0_ mcell D6 mx F21 cpu_est_1_ mcell D13 -mx F5 ... ... mx F22inst_nEXP_SPACE_D0reg mcell G5 -mx F6 inst_VPA_D mcell F13 mx F23 ... ... -mx F7inst_AS_030_000_SYNC mcell C8 mx F24 ... ... -mx F8inst_CLK_000_NE_D0 mcell B15 mx F25 inst_CLK_000_PE mcell D9 -mx F9inst_UDS_000_INT mcell F5 mx F26 RN_VMA mcell D0 -mx F10 SM_AMIGA_1_ mcell F1 mx F27 inst_CLK_000_NE mcell G9 -mx F11 N_165 mcell F6 mx F28 SM_AMIGA_2_ mcell F2 -mx F12 inst_CLK_000_D0 mcell G13 mx F29 SM_AMIGA_5_ mcell F4 -mx F13 VPA pin 36 mx F30 ... ... -mx F14 SM_AMIGA_6_ mcell C4 mx F31 inst_DTACK_D0 mcell D15 -mx F15 A0 pin 69 mx F32 inst_CLK_000_D1 mcell F8 -mx F16 ... ... +mx F0 SM_AMIGA_2_ mcell C13 mx F17 SM_AMIGA_5_ mcell F12 +mx F1 BERR pin 41 mx F18 inst_CLK_000_D0 mcell B2 +mx F2 SM_AMIGA_i_7_ mcell F8 mx F19inst_BGACK_030_INT_D mcell H13 +mx F3pos_clk_un29_clk_000_ne_d0_i_n mcell D2 mx F20 RN_BGACK_030 mcell H4 +mx F4 A_18_ pin 95 mx F21CLK_000_N_SYNC_11_ mcell H6 +mx F5 nEXP_SPACE pin 14 mx F22 SM_AMIGA_1_ mcell C1 +mx F6 FC_0_ pin 57 mx F23 ... ... +mx F7 SM_AMIGA_3_ mcell C8 mx F24 RST pin 86 +mx F8 A_17_ pin 59 mx F25 inst_CLK_000_D1 mcell D9 +mx F9 SM_AMIGA_6_ mcell F5 mx F26 ... ... +mx F10CLK_000_N_SYNC_8_ mcell G14 mx F27 A_19_ pin 97 +mx F11 A_16_ pin 96 mx F28 ... ... +mx F12 FC_1_ pin 58 mx F29 inst_CLK_000_PE mcell C4 +mx F13 inst_AS_030_D0 mcell H5 mx F30 SM_AMIGA_4_ mcell F1 +mx F14 inst_CLK_000_NE mcell F4 mx F31inst_nEXP_SPACE_D0reg mcell F0 +mx F15inst_AS_030_000_SYNC mcell F13 mx F32 SM_AMIGA_0_ mcell F9 +mx F16CLK_000_P_SYNC_4_ mcell D6 ---------------------------------------------------------------------------- @@ -1078,22 +1090,22 @@ BLOCK_G_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx G0 RN_BGACK_030 mcell H4 mx G17 RN_RW mcell G0 -mx G1 cpu_est_1_ mcell D13 mx G18 ... ... -mx G2 RN_E mcell G4 mx G19inst_CLK_OUT_PRE_50 mcell A9 -mx G3CLK_000_P_SYNC_0_ mcell D11 mx G20CLK_000_N_SYNC_8_ mcell A14 -mx G4 cpu_est_0_ mcell D6 mx G21 RST pin 86 -mx G5 SIZE_DMA_0_ mcell G6 mx G22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G10 -mx G6 RW_000 pin 80 mx G23 SIZE_DMA_1_ mcell G2 -mx G7CLK_000_N_SYNC_11_ mcell H6 mx G24 LDS_000 pin 31 -mx G8inst_CLK_000_NE_D0 mcell B15 mx G25 ... ... -mx G9 RN_RESET mcell B14 mx G26CLK_000_P_SYNC_6_ mcell E5 -mx G10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell G14 mx G27 ... ... -mx G11 A1 pin 60 mx G28inst_BGACK_030_INT_D mcell H13 -mx G12 UDS_000 pin 32 mx G29 ... ... -mx G13 RN_A0 mcell G8 mx G30 ... ... -mx G14 CLK_000 pin 11 mx G31 ... ... -mx G15 nEXP_SPACE pin 14 mx G32inst_nEXP_SPACE_D0reg mcell G5 -mx G16 cpu_est_2_ mcell D2 +mx G1CLK_000_N_SYNC_0_ mcell F6 mx G18 A0 pin 69 +mx G2CLK_000_N_SYNC_7_ mcell B10 mx G19inst_BGACK_030_INT_D mcell H13 +mx G3 A1 pin 60 mx G20 SIZE_1_ pin 79 +mx G4 SIZE_DMA_1_ mcell G2 mx G21 RST pin 86 +mx G5inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell G10 mx G22 cpu_est_1_ mcell G5 +mx G6 RW_000 pin 80 mx G23 SIZE_DMA_0_ mcell G6 +mx G7 cpu_est_0_ mcell C5 mx G24 LDS_000 pin 31 +mx G8 UDS_000 pin 32 mx G25inst_UDS_000_INT mcell G13 +mx G9 SM_AMIGA_6_ mcell F5 mx G26 RN_RESET mcell B0 +mx G10 RN_A0 mcell G8 mx G27inst_LDS_000_INT mcell G9 +mx G11 RN_E mcell G4 mx G28 ... ... +mx G12CLK_000_N_SYNC_1_ mcell G7 mx G29 ... ... +mx G13 inst_DS_030_D0 mcell D7 mx G30 IPL_2_ pin 68 +mx G14 SIZE_0_ pin 70 mx G31inst_nEXP_SPACE_D0reg mcell F0 +mx G15 cpu_est_2_ mcell C12 mx G32 ... ... +mx G16inst_CLK_000_NE_D0 mcell E8 ---------------------------------------------------------------------------- @@ -1101,22 +1113,22 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RN_BGACK_030 mcell H4 mx H17 FC_0_ pin 57 +mx H0 RN_BGACK_030 mcell H4 mx H17 SM_AMIGA_5_ mcell F12 mx H1 BERR pin 41 mx H18 BGACK_000 pin 28 -mx H2inst_CLK_OUT_PRE_D mcell G15 mx H19 AS_030 pin 82 +mx H2 SM_AMIGA_i_7_ mcell F8 mx H19 FPU_SENSE pin 91 mx H3 inst_AS_000_DMA mcell A8 mx H20 CLK_030 pin 64 -mx H4 inst_AS_030_D0 mcell H5 mx H21 RST pin 86 -mx H5 SM_AMIGA_i_7_ mcell F0 mx H22inst_nEXP_SPACE_D0reg mcell G5 -mx H6 A_19_ pin 97 mx H23 SIZE_DMA_1_ mcell G2 -mx H7 inst_CLK_000_PE mcell D9 mx H24CLK_000_N_SYNC_9_ mcell G3 -mx H8 FPU_SENSE pin 91 mx H25 RW pin 71 -mx H9 RN_RESET mcell B14 mx H26 ... ... -mx H10 SM_AMIGA_5_ mcell F4 mx H27 RN_DSACK1 mcell H9 -mx H11 A_16_ pin 96 mx H28 ... ... +mx H4 A_18_ pin 95 mx H21 RST pin 86 +mx H5 RN_DSACK1 mcell H9 mx H22 SM_AMIGA_1_ mcell C1 +mx H6 A_16_ pin 96 mx H23inst_CLK_OUT_PRE_D mcell E13 +mx H7 ... ... mx H24 FC_0_ pin 57 +mx H8 A_17_ pin 59 mx H25inst_nEXP_SPACE_D0reg mcell F0 +mx H9 AS_030 pin 82 mx H26 RN_RESET mcell B0 +mx H10 ... ... mx H27 A_19_ pin 97 +mx H11 RW pin 71 mx H28CLK_000_N_SYNC_10_ mcell H2 mx H12 FC_1_ pin 58 mx H29 SIZE_DMA_0_ mcell G6 -mx H13 A_17_ pin 59 mx H30 RN_RW_000 mcell H0 -mx H14CLK_000_N_SYNC_10_ mcell H2 mx H31 A_18_ pin 95 -mx H15 SM_AMIGA_1_ mcell F1 mx H32 SM_AMIGA_0_ mcell F9 +mx H13 inst_AS_030_D0 mcell H5 mx H30 RN_RW_000 mcell H0 +mx H14 inst_CLK_000_PE mcell C4 mx H31 SIZE_DMA_1_ mcell G2 +mx H15CLK_000_N_SYNC_9_ mcell F2 mx H32 SM_AMIGA_0_ mcell F9 mx H16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -1132,8 +1144,6 @@ PostFit_Equations P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- - 1 2 1 Pin SIZE_0_ - 1 2 1 Pin SIZE_0_.OE 1 2 1 Pin SIZE_1_ 1 2 1 Pin SIZE_1_.OE 1 2 1 Pin AS_030- @@ -1157,8 +1167,10 @@ PostFit_Equations 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH - 1 0 1 Pin CIIN - 1 10 1 Pin CIIN.OE + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_ + 1 2 1 Pin SIZE_0_.OE 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -1169,7 +1181,7 @@ PostFit_Equations 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C - 2 4 1 Pin BGACK_030.D- + 3 5 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C 10 8 1 Pin IPL_030_1_.D- 1 1 1 Pin IPL_030_1_.C @@ -1187,7 +1199,6 @@ PostFit_Equations 1 2 1 Pin RW.OE 2 5 1 Pin RW.D- 1 1 1 Pin RW.C - 4 11 1 Node N_165 2 2 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 5 5 1 Node cpu_est_1_.D- @@ -1307,6 +1318,7 @@ PostFit_Equations 1 1 1 Node CLK_000_N_SYNC_3_.C 1 1 1 Node CLK_000_N_SYNC_4_.D 1 1 1 Node CLK_000_N_SYNC_4_.C + 2 8 1 Node pos_clk_un29_clk_000_ne_d0_i_n- 1 1 1 Node CLK_000_N_SYNC_5_.D 1 1 1 Node CLK_000_N_SYNC_5_.C 1 1 1 Node CLK_000_N_SYNC_6_.D @@ -1329,21 +1341,18 @@ PostFit_Equations 1 1 1 Node SM_AMIGA_2_.C 3 7 1 Node inst_DS_000_ENABLE.D 1 1 1 Node inst_DS_000_ENABLE.C - 14 20 1 Node SM_AMIGA_i_7_.D + 13 16 1 Node SM_AMIGA_i_7_.D- 1 1 1 Node SM_AMIGA_i_7_.C + 2 14 1 Node CIIN_0 ========= 346 P-Term Total: 346 - Total Pins: 57 - Total Nodes: 72 + Total Pins: 61 + Total Nodes: 73 Average P-Term/Output: 2 Equations: -SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); - -SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); - SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); @@ -1392,9 +1401,13 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q # BGACK_030.Q & !SM_AMIGA_i_7_.Q); -CIIN = (1); +CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); -CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q); +CIIN.OE = (CIIN_0); + +SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q @@ -1430,8 +1443,9 @@ A0.C = (CLK_OSZI); BG_000.C = (CLK_OSZI); -!BGACK_030.D = (!BGACK_000 & RST - # RST & !BGACK_030.Q & !inst_CLK_000_PE.Q); +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN); BGACK_030.C = (CLK_OSZI); @@ -1496,11 +1510,6 @@ RW.OE = (!BGACK_030.Q & RESET.Q); RW.C = (CLK_OSZI); -N_165 = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); - cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); @@ -1812,6 +1821,9 @@ CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); CLK_000_N_SYNC_4_.C = (CLK_OSZI); +!pos_clk_un29_clk_000_ne_d0_i_n = (inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); CLK_000_N_SYNC_5_.C = (CLK_OSZI); @@ -1872,23 +1884,25 @@ inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q inst_DS_000_ENABLE.C = (CLK_OSZI); -SM_AMIGA_i_7_.D = (RST & !N_165 & !inst_CLK_000_PE.Q & BERR.PIN - # RST & !N_165 & !SM_AMIGA_0_.Q & BERR.PIN - # RST & !N_165 & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & !N_165 & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q - # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); +!SM_AMIGA_i_7_.D = (!RST + # inst_CLK_000_PE.Q & SM_AMIGA_0_.Q + # SM_AMIGA_0_.Q & !BERR.PIN + # SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !BERR.PIN + # SM_AMIGA_3_.Q & pos_clk_un29_clk_000_ne_d0_i_n & !BERR.PIN + # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & !BERR.PIN + # !SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); +CIIN_0 = (inst_nEXP_SPACE_D0reg.Q + # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + Reverse-Polarity Equations: diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 2d3f516..ad74413 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -46,66 +46,64 @@ SIGNAL NAME min max min max min max min max DS_030 .. .. .. .. 1 2 .. .. FPU_CS .. .. .. .. 1 2 .. .. AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. - SM_AMIGA_5_ 1 1 .. .. .. .. 1 2 - inst_AS_030_D0 1 2 .. .. .. .. 1 1 -inst_nEXP_SPACE_D0reg 1 1 1 1 .. .. 1 2 -inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 + BGACK_030 1 2 0 1 .. .. 1 1 + RN_BGACK_030 1 2 0 1 .. .. 1 1 + E .. .. 0 0 .. .. 1 2 + RN_E .. .. 0 0 .. .. 1 2 + VMA 1 1 0 0 .. .. 1 2 + RN_VMA 1 1 0 0 .. .. 1 2 + cpu_est_0_ .. .. .. .. .. .. 1 2 + cpu_est_1_ .. .. .. .. .. .. 1 2 + inst_AS_030_D0 1 2 1 1 .. .. 1 1 CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1 + inst_VPA_D 1 1 .. .. .. .. 1 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 inst_LDS_000_INT 1 1 1 1 .. .. 2 2 - inst_CLK_000_D1 .. .. .. .. .. .. 1 2 - inst_CLK_000_D0 1 1 .. .. .. .. 1 2 - SM_AMIGA_3_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_0_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_6_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_1_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_4_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_2_ 1 1 .. .. .. .. 1 2 + inst_DTACK_D0 1 1 .. .. .. .. 1 2 + cpu_est_2_ .. .. .. .. .. .. 1 2 +inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 2 inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 AS_030 .. .. .. .. 1 1 .. .. AS_000 .. .. .. .. 1 1 .. .. CLK_EXP .. .. .. .. 1 1 .. .. + CIIN .. .. .. .. 1 1 .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 RW_000 1 1 0 0 .. .. 1 1 RN_RW_000 1 1 0 0 .. .. 1 1 BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 - BGACK_030 1 1 0 1 .. .. 1 1 - RN_BGACK_030 1 1 0 1 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 DSACK1 1 1 0 0 .. .. 1 1 RN_DSACK1 1 1 0 0 .. .. 1 1 - E .. .. 0 0 .. .. 1 1 - RN_E .. .. 0 0 .. .. 1 1 - VMA 1 1 0 0 .. .. 1 1 - RN_VMA 1 1 0 0 .. .. 1 1 RESET 1 1 0 0 .. .. 1 1 RN_RESET 1 1 0 0 .. .. 1 1 RW 1 1 0 0 .. .. 1 1 RN_RW 1 1 0 0 .. .. 1 1 - cpu_est_0_ .. .. .. .. .. .. 1 1 - cpu_est_1_ .. .. .. .. .. .. 1 1 + SM_AMIGA_5_ 1 1 .. .. .. .. 1 1 inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. +inst_nEXP_SPACE_D0reg 1 1 1 1 .. .. 1 1 +inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 - inst_VPA_D 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 - inst_DTACK_D0 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 + inst_CLK_000_D1 .. .. .. .. .. .. 1 1 + inst_CLK_000_D0 1 1 .. .. .. .. 1 1 inst_CLK_000_PE .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 inst_CLK_000_NE .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 - cpu_est_2_ .. .. .. .. .. .. 1 1 IPL_D0_0_ 1 1 .. .. .. .. 1 1 IPL_D0_1_ 1 1 .. .. .. .. 1 1 IPL_D0_2_ 1 1 .. .. .. .. 1 1 -inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 + SM_AMIGA_3_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_0_ 1 1 .. .. .. .. 1 1 inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. + SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 RST_DLY_0_ 1 1 .. .. .. .. 1 1 RST_DLY_1_ 1 1 .. .. .. .. 1 1 RST_DLY_2_ 1 1 .. .. .. .. 1 1 @@ -134,4 +132,8 @@ CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 - SM_AMIGA_i_7_ 1 1 1 1 .. .. 1 1 \ No newline at end of file + SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_4_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_2_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_i_7_ 1 1 1 1 .. .. 1 1 + CIIN_0 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 8054d59..68834fc 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,616 +1,632 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE 68030_tk -#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ A_25_ A_24_ IPL_2_ FC_1_ AS_030 AS_000 A_19_ A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW -#$ NODES 72 N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW +#$ NODES 72 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ .type fr -.i 123 +.i 127 .o 198 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q N_165 cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN -.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C inst_LDS_000_INT.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C BGACK_030.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C RW.C RW_000.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ N_165 AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 604 ---------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1------------------------------------------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------------0-------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------------0----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------------0-----------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------1-------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -------------------------------------1-1-----------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------1---------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------1------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ pos_clk_un29_clk_000_ne_d0_i_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 620 +------------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+---------------------------------------0----------------------------0--------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------------------------1------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0------------1---------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +--------------------------------------------------------------------1---------------------------1----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +--------------------------------------------------------------0--------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0-----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------1--------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +---------------------------------------1-1------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------1----------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------1-------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index ed07de7..957bff2 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,616 +1,632 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE 68030_tk -#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ A_25_ A_24_ IPL_2_ FC_1_ AS_030 AS_000 A_19_ A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW -#$ NODES 72 N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW +#$ NODES 72 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ .type fr -.i 123 +.i 127 .o 198 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q N_165 cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN -.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C inst_LDS_000_INT.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C BGACK_030.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C RW.C RW_000.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ N_165 AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 604 ---------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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--------------1-------------01---------01--1----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -------------------------------------1----------------------0-------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------0-------------------0---------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -------------------------------1------------------0---------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------1---------------0---------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----------------------------------1--------------0---------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------------------------------------------1---1-----------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------------------------------------------0-----------0---1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -------------------------------------0----------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------------------------------10------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------------------------------------------------------------1-----------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------------0------------1--------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ --------------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------------0-------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------------0----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------------0-----------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------1-------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ -------------------------------------1-1-----------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------1---------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------1------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ pos_clk_un29_clk_000_ne_d0_i_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 620 +------------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +-------1-----1------------------0---------------01-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0-------------0-01-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0-----1------------------0--------------001-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-----1------------------0---------------10-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0-------------0-10-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0-----1------------------0--------------010-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-----1------------------0-------------0-01--------------------------------------------------------1----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-----1------------------0-------------0-10--------------------------------------------------------1----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0--------------001--------------------------------------------------------0----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0--------------010--------------------------------------------------------0----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0---------------01-------------------------------------------------------------------01--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0---------------10-------------------------------------------------------------------01--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------0---------------------------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------------------0-----------------------------1------------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------------------0-----------------------------1-------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------------------0-----------------------------1--------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------------------0-----------------------------1--------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------0--0-----------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1---------------------------0--0--------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1---------------------------0------------------------------0----------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------------------------------------------------1---------------------------------------1----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------0------------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1--------------------1-----------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------1---------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------------1--------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1--------------------------------------1---1---------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1--------------------------------------0-----------0-------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------------------------------------0--------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0----------1------------------1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------1------1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1------------1-----1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------0----1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1--------------1---1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-----------------01--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------0-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---------------------------------------1----------------------0--------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +--------------------------------------------------------------------0--------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------------------0----------------------------0--------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------------------------------------1------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0------------1---------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +--------------------------------------------------------------------1---------------------------1----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +-----------------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +--------------------------------------------------------------0--------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0-----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +------------------------------------------------------------0------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +---------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1-------------------------1--------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +---------------------------------------1-1------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------1----------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------1-------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index cb1a686..a38edf5 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,13 +1,14 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE BUS68030 -#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ A_25_ A_24_ - IPL_2_ FC_1_ AS_030 AS_000 A_19_ A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A1 +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ + A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP - FPU_CS FPU_SENSE IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_ - RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW -#$ NODES 72 N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ + IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ + A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA + RESET RW +#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D @@ -20,60 +21,60 @@ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ - CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ - CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H - SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ + CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ + CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ + CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ + inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0 .type f -.i 123 -.o 199 +.i 128 +.o 200 .ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_19_ A_18_ - A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q N_165 cpu_est_0_.Q - cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q - inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q - inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q - CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q - inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q - inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q - inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q - IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q - inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q - RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q - RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q - CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q - CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q - CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q - CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q - CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q - SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q - IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN - DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN - RW.PIN -.ob SIZE_0_ SIZE_0_.OE SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE - DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE - CLK_DIV_OUT CLK_DIV_OUT.OE CLK_EXP FPU_CS% AVEC AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE - IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% - BG_000.C BGACK_030.D% BGACK_030.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% - IPL_030_0_.C DSACK1.D% DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C - RW.D% RW.C RW.OE N_165 cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D% cpu_est_1_.C - inst_AS_000_INT.D% inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C - inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C - inst_AS_030_D0.D% inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D% - inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D% inst_DS_030_D0.C - inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% - inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D - inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C - SIZE_DMA_0_.D% SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% - inst_VPA_D.C inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D - inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% - inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D - inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D - inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D - inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D - cpu_est_2_.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% - IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C inst_CLK_000_NE_D0.D - inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C + FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ + A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q + RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q + inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q + inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q + inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q + inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q + inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q + cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q + inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q + SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q + RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q + CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q + CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q + CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q + pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q + CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q + RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q + inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q + IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN + SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN CIIN_0 +.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE + UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE + CLK_EXP FPU_CS% AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% + AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C + RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D + BGACK_030.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C DSACK1.D% + DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D% RW.C RW.OE + cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D% cpu_est_1_.C inst_AS_000_INT.D% + inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C + inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D% + inst_DS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C + inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D + inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C + SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C inst_UDS_000_INT.D% + inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D + inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D + inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D + CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D + CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D% IPL_D0_0_.C + IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C + inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1 RST_DLY_4_.T.X2 @@ -85,254 +86,252 @@ CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D - CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D - CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D - CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D - CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D - SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_2_.D SM_AMIGA_2_.C - inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C -.phase 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+------------------------------------------------------------0------------------------------------------------1---------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index b819466..2031291 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,13 +1,14 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE BUS68030 -#$ PINS 57 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ A_25_ A_24_ - IPL_2_ FC_1_ AS_030 AS_000 A_19_ A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A1 +#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ + A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP - FPU_CS FPU_SENSE IPL_1_ DTACK IPL_0_ AVEC FC_0_ VPA RST AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_ - RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW -#$ NODES 72 N_165 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ + IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ + A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA + RESET RW +#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D @@ -20,60 +21,60 @@ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ - CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ - CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H - SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ + CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ + CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ + CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ + inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0 .type f -.i 123 -.o 199 +.i 128 +.o 200 .ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_19_ A_18_ - A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q N_165 cpu_est_0_.Q - cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q - inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q - inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q - CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q - inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q - inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q - inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q - IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q - inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q - RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q - RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q - CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q - CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q - CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q - CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q - CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q - SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q - IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN - DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN - RW.PIN -.ob SIZE_0_ SIZE_0_.OE SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE - DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE - CLK_DIV_OUT CLK_DIV_OUT.OE CLK_EXP FPU_CS- AVEC AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE - IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- - BG_000.C BGACK_030.D- BGACK_030.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- - IPL_030_0_.C DSACK1.D- DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C - RW.D- RW.C RW.OE N_165 cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D- cpu_est_1_.C - inst_AS_000_INT.D- inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C - inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C - inst_AS_030_D0.D- inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D- - inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D- inst_DS_030_D0.C - inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- - inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D - inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C - SIZE_DMA_0_.D- SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- - inst_VPA_D.C inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D - inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- - inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D - inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D - inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D - inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D - cpu_est_2_.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- - IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C inst_CLK_000_NE_D0.D - inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C + FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ + A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q + RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q + inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q + inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q + inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q + inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q + inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q + cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q + inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q + SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q + RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q + CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q + CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q + CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q + pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q + CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q + RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q + inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q + IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN + SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN CIIN_0 +.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE + UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE + CLK_EXP FPU_CS- AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- + AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C + RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D + BGACK_030.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C DSACK1.D- + DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D- RW.C RW.OE + cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D- cpu_est_1_.C inst_AS_000_INT.D- + inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C + inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D- + inst_DS_030_D0.C inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C + inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D + inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C + SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C inst_UDS_000_INT.D- + inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D + inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D + inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D + CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D + CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D- IPL_D0_0_.C + IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C SM_AMIGA_3_.T SM_AMIGA_3_.C + inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1 RST_DLY_4_.T.X2 @@ -85,254 +86,252 @@ CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D - CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D - CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D - CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D - CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D - SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_2_.D SM_AMIGA_2_.C - inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C -.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 242 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index f41a4cc..9202d64 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 7/9/15; -TIME = 18:49:07; +DATE = 9/24/15; +TIME = 16:21:08; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -136,14 +136,14 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF +BERR = OUTPUT,41,4,-; RW_000 = BIDIR,80,7,-; AS_000 = OUTPUT,42,4,-; -BERR = OUTPUT,41,4,-; -A0 = BIDIR,69,6,-; RW = BIDIR,71,6,-; AS_030 = OUTPUT,82,7,-; UDS_000 = OUTPUT,32,3,-; LDS_000 = OUTPUT,31,3,-; +A0 = BIDIR,69,6,-; DS_030 = OUTPUT,98,0,-; SIZE_1_ = OUTPUT,79,7,-; SIZE_0_ = OUTPUT,70,6,-; @@ -152,8 +152,8 @@ IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; E = OUTPUT,66,6,-; DSACK1 = OUTPUT,81,7,-; -VMA = OUTPUT,35,3,-; BGACK_030 = OUTPUT,83,7,-; +VMA = OUTPUT,35,3,-; AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; BG_000 = OUTPUT,29,3,-; @@ -165,88 +165,89 @@ CIIN = OUTPUT,47,4,-; AMIGA_ADDR_ENABLE = OUTPUT,33,3,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; -inst_nEXP_SPACE_D0reg = NODE,*,6,-; -RN_RESET = NODE,-1,1,-; RN_BGACK_030 = NODE,-1,7,-; -inst_CLK_000_PE = NODE,*,3,-; -inst_CLK_000_NE = NODE,*,6,-; +RN_RESET = NODE,-1,1,-; +inst_nEXP_SPACE_D0reg = NODE,*,5,-; +inst_CLK_000_NE = NODE,*,5,-; +inst_CLK_000_PE = NODE,*,2,-; inst_AS_030_D0 = NODE,*,7,-; SM_AMIGA_i_7_ = NODE,*,5,-; RN_E = NODE,-1,6,-; -cpu_est_1_ = NODE,*,3,-; -cpu_est_2_ = NODE,*,3,-; -SM_AMIGA_6_ = NODE,*,2,-; +SM_AMIGA_3_ = NODE,*,2,-; +cpu_est_1_ = NODE,*,6,-; +cpu_est_2_ = NODE,*,2,-; +SM_AMIGA_1_ = NODE,*,2,-; SM_AMIGA_5_ = NODE,*,5,-; -cpu_est_0_ = NODE,*,3,-; -inst_CLK_000_NE_D0 = NODE,*,1,-; -inst_CLK_000_D0 = NODE,*,6,-; -inst_CLK_000_D1 = NODE,*,5,-; +cpu_est_0_ = NODE,*,2,-; +inst_CLK_000_NE_D0 = NODE,*,4,-; +inst_BGACK_030_INT_D = NODE,*,7,-; inst_AS_000_DMA = NODE,*,0,-; -inst_AS_030_000_SYNC = NODE,*,2,-; -RST_DLY_3_ = NODE,*,1,-; +RST_DLY_3_ = NODE,*,2,-; RST_DLY_2_ = NODE,*,1,-; -SM_AMIGA_3_ = NODE,*,5,-; -RST_DLY_5_ = NODE,*,0,-; -RST_DLY_1_ = NODE,*,0,-; -inst_LDS_000_INT = NODE,*,1,-; +SM_AMIGA_2_ = NODE,*,2,-; +RST_DLY_5_ = NODE,*,1,-; +RST_DLY_1_ = NODE,*,1,-; +inst_LDS_000_INT = NODE,*,6,-; RN_VMA = NODE,-1,3,-; -inst_DS_000_ENABLE = NODE,*,2,-; -SM_AMIGA_1_ = NODE,*,5,-; -RST_DLY_6_ = NODE,*,1,-; -RST_DLY_0_ = NODE,*,1,-; -inst_UDS_000_INT = NODE,*,5,-; +inst_DS_000_ENABLE = NODE,*,0,-; +SM_AMIGA_4_ = NODE,*,5,-; +RST_DLY_6_ = NODE,*,2,-; +RST_DLY_0_ = NODE,*,2,-; +SM_AMIGA_6_ = NODE,*,5,-; +inst_UDS_000_INT = NODE,*,6,-; SIZE_DMA_1_ = NODE,*,6,-; SIZE_DMA_0_ = NODE,*,6,-; -RST_DLY_7_ = NODE,*,0,-; -RST_DLY_4_ = NODE,*,1,-; +RST_DLY_7_ = NODE,*,2,-; +RST_DLY_4_ = NODE,*,2,-; inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,6,-; SM_AMIGA_0_ = NODE,*,5,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,6,-; -inst_AS_000_INT = NODE,*,2,-; -inst_CLK_OUT_PRE_50 = NODE,*,0,-; -inst_VPA_D = NODE,*,5,-; -inst_BGACK_030_INT_D = NODE,*,7,-; -inst_DS_030_D0 = NODE,*,3,-; +inst_AS_000_INT = NODE,*,0,-; +inst_CLK_000_D0 = NODE,*,1,-; +inst_CLK_000_D1 = NODE,*,3,-; +inst_DTACK_D0 = NODE,*,1,-; +inst_VPA_D = NODE,*,3,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; inst_DS_000_DMA = NODE,*,0,-; inst_CLK_030_H = NODE,*,0,-; +inst_AS_030_000_SYNC = NODE,*,5,-; RN_DSACK1 = NODE,-1,7,-; -SM_AMIGA_2_ = NODE,*,5,-; -N_165 = NODE,*,5,-; RN_A0 = NODE,-1,6,-; RN_RW_000 = NODE,-1,7,-; -SM_AMIGA_4_ = NODE,*,5,-; CYCLE_DMA_1_ = NODE,*,0,-; RN_RW = NODE,-1,6,-; RN_BG_000 = NODE,-1,3,-; +CIIN_0 = NODE,*,4,-; +pos_clk_un29_clk_000_ne_d0_i_n = NODE,*,3,-; CYCLE_DMA_0_ = NODE,*,0,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-; CLK_000_N_SYNC_10_ = NODE,*,7,-; -CLK_000_N_SYNC_9_ = NODE,*,6,-; -CLK_000_N_SYNC_8_ = NODE,*,0,-; -CLK_000_N_SYNC_7_ = NODE,*,4,-; -CLK_000_N_SYNC_6_ = NODE,*,3,-; -CLK_000_N_SYNC_5_ = NODE,*,0,-; -CLK_000_N_SYNC_4_ = NODE,*,3,-; -CLK_000_N_SYNC_3_ = NODE,*,0,-; -CLK_000_N_SYNC_2_ = NODE,*,0,-; -CLK_000_N_SYNC_1_ = NODE,*,0,-; -CLK_000_N_SYNC_0_ = NODE,*,3,-; -CLK_000_P_SYNC_8_ = NODE,*,2,-; -CLK_000_P_SYNC_7_ = NODE,*,6,-; -CLK_000_P_SYNC_6_ = NODE,*,4,-; -CLK_000_P_SYNC_5_ = NODE,*,4,-; -CLK_000_P_SYNC_4_ = NODE,*,1,-; +CLK_000_N_SYNC_9_ = NODE,*,5,-; +CLK_000_N_SYNC_8_ = NODE,*,6,-; +CLK_000_N_SYNC_7_ = NODE,*,1,-; +CLK_000_N_SYNC_6_ = NODE,*,0,-; +CLK_000_N_SYNC_5_ = NODE,*,1,-; +CLK_000_N_SYNC_4_ = NODE,*,1,-; +CLK_000_N_SYNC_3_ = NODE,*,1,-; +CLK_000_N_SYNC_2_ = NODE,*,6,-; +CLK_000_N_SYNC_1_ = NODE,*,6,-; +CLK_000_N_SYNC_0_ = NODE,*,5,-; +CLK_000_P_SYNC_8_ = NODE,*,0,-; +CLK_000_P_SYNC_7_ = NODE,*,0,-; +CLK_000_P_SYNC_6_ = NODE,*,0,-; +CLK_000_P_SYNC_5_ = NODE,*,5,-; +CLK_000_P_SYNC_4_ = NODE,*,3,-; CLK_000_P_SYNC_3_ = NODE,*,2,-; CLK_000_P_SYNC_2_ = NODE,*,1,-; -CLK_000_P_SYNC_1_ = NODE,*,6,-; +CLK_000_P_SYNC_1_ = NODE,*,2,-; CLK_000_P_SYNC_0_ = NODE,*,3,-; -IPL_D0_2_ = NODE,*,1,-; -IPL_D0_1_ = NODE,*,2,-; -IPL_D0_0_ = NODE,*,1,-; +IPL_D0_2_ = NODE,*,6,-; +IPL_D0_1_ = NODE,*,3,-; +IPL_D0_0_ = NODE,*,3,-; CLK_000_N_SYNC_11_ = NODE,*,7,-; -CLK_000_P_SYNC_9_ = NODE,*,2,-; -inst_DTACK_D0 = NODE,*,3,-; -inst_CLK_OUT_PRE_D = NODE,*,6,-; +CLK_000_P_SYNC_9_ = NODE,*,0,-; +inst_CLK_OUT_PRE_50 = NODE,*,4,-; +inst_CLK_OUT_PRE_D = NODE,*,4,-; +inst_DS_030_D0 = NODE,*,3,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 210dd6a..69fcc80 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 7/9/15; -TIME = 18:49:07; +DATE = 9/24/15; +TIME = 16:21:08; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -136,26 +136,27 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; -SIZE_0_ = BIDIR,70, G,-; -A_30_ = INPUT,5, B,-; -SIZE_1_ = BIDIR,79, H,-; -A_29_ = INPUT,6, B,-; A_28_ = INPUT,15, C,-; -A_31_ = INPUT,4, B,-; A_27_ = INPUT,16, C,-; +SIZE_1_ = BIDIR,79, H,-; A_26_ = INPUT,17, C,-; A_25_ = INPUT,18, C,-; +A_31_ = INPUT,4, B,-; A_24_ = INPUT,19, C,-; +A_23_ = INPUT,85, H,-; +A_22_ = INPUT,84, H,-; +A_21_ = INPUT,94, A,-; IPL_2_ = INPUT,68, G,-; -FC_1_ = INPUT,58, F,-; -AS_030 = BIDIR,82, H,-; -AS_000 = BIDIR,42, E,-; +A_20_ = INPUT,93, A,-; A_19_ = INPUT,97, A,-; +FC_1_ = INPUT,58, F,-; A_18_ = INPUT,95, A,-; -DS_030 = BIDIR,98, A,-; +AS_030 = BIDIR,82, H,-; A_17_ = INPUT,59, F,-; -UDS_000 = BIDIR,32, D,-; +AS_000 = BIDIR,42, E,-; A_16_ = INPUT,96, A,-; +DS_030 = BIDIR,98, A,-; +UDS_000 = BIDIR,32, D,-; LDS_000 = BIDIR,31, D,-; A1 = INPUT,60, F,-; nEXP_SPACE = INPUT,14,-,-; @@ -167,13 +168,13 @@ CLK_000 = INPUT,11,-,-; CLK_OSZI = INPUT,61,-,-; CLK_DIV_OUT = OUTPUT,65, G,-; CLK_EXP = OUTPUT,10, B,-; -FPU_CS = OUTPUT,78, H,-; -FPU_SENSE = INPUT,91, A,-; IPL_1_ = INPUT,56, F,-; -DTACK = INPUT,30, D,-; +FPU_CS = OUTPUT,78, H,-; IPL_0_ = INPUT,67, G,-; -AVEC = OUTPUT,92, A,-; +FPU_SENSE = INPUT,91, A,-; FC_0_ = INPUT,57, F,-; +DTACK = INPUT,30, D,-; +AVEC = OUTPUT,92, A,-; VPA = INPUT,36,-,-; RST = INPUT,86,-,-; AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; @@ -181,6 +182,9 @@ AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; CIIN = OUTPUT,47, E,-; +SIZE_0_ = BIDIR,70, G,-; +A_30_ = INPUT,5, B,-; +A_29_ = INPUT,6, B,-; IPL_030_2_ = OUTPUT,9, B,-; RW_000 = BIDIR,80, H,-; A0 = BIDIR,69, G,-; @@ -193,75 +197,76 @@ E = OUTPUT,66, G,-; VMA = OUTPUT,35, D,-; RESET = OUTPUT,3, B,-; RW = BIDIR,71, G,-; -N_165 = NODE,6, F,-; -cpu_est_0_ = NODE,6, D,-; -cpu_est_1_ = NODE,13, D,-; -inst_AS_000_INT = NODE,1, C,-; -SM_AMIGA_5_ = NODE,4, F,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,14, G,-; +cpu_est_0_ = NODE,5, C,-; +cpu_est_1_ = NODE,5, G,-; +inst_AS_000_INT = NODE,1, A,-; +SM_AMIGA_5_ = NODE,12, F,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,3, C,-; inst_AS_030_D0 = NODE,5, H,-; -inst_nEXP_SPACE_D0reg = NODE,5, G,-; -inst_DS_030_D0 = NODE,10, D,-; -inst_AS_030_000_SYNC = NODE,8, C,-; +inst_nEXP_SPACE_D0reg = NODE,0, F,-; +inst_DS_030_D0 = NODE,7, D,-; +inst_AS_030_000_SYNC = NODE,13, F,-; inst_BGACK_030_INT_D = NODE,13, H,-; inst_AS_000_DMA = NODE,8, A,-; -inst_DS_000_DMA = NODE,13, A,-; -CYCLE_DMA_0_ = NODE,10, A,-; -CYCLE_DMA_1_ = NODE,6, A,-; +inst_DS_000_DMA = NODE,5, A,-; +CYCLE_DMA_0_ = NODE,2, A,-; +CYCLE_DMA_1_ = NODE,13, A,-; SIZE_DMA_0_ = NODE,6, G,-; SIZE_DMA_1_ = NODE,2, G,-; -inst_VPA_D = NODE,13, F,-; -inst_UDS_000_INT = NODE,5, F,-; -inst_LDS_000_INT = NODE,9, B,-; -inst_CLK_OUT_PRE_D = NODE,15, G,-; -inst_DTACK_D0 = NODE,15, D,-; -inst_CLK_OUT_PRE_50 = NODE,9, A,-; -inst_CLK_000_D1 = NODE,8, F,-; -inst_CLK_000_D0 = NODE,13, G,-; -inst_CLK_000_PE = NODE,9, D,-; -CLK_000_P_SYNC_9_ = NODE,2, C,-; -inst_CLK_000_NE = NODE,9, G,-; +inst_VPA_D = NODE,13, D,-; +inst_UDS_000_INT = NODE,13, G,-; +inst_LDS_000_INT = NODE,9, G,-; +inst_CLK_OUT_PRE_D = NODE,13, E,-; +inst_DTACK_D0 = NODE,6, B,-; +inst_CLK_OUT_PRE_50 = NODE,9, E,-; +inst_CLK_000_D1 = NODE,9, D,-; +inst_CLK_000_D0 = NODE,2, B,-; +inst_CLK_000_PE = NODE,4, C,-; +CLK_000_P_SYNC_9_ = NODE,7, A,-; +inst_CLK_000_NE = NODE,4, F,-; CLK_000_N_SYNC_11_ = NODE,6, H,-; -cpu_est_2_ = NODE,2, D,-; -IPL_D0_0_ = NODE,7, B,-; -IPL_D0_1_ = NODE,13, C,-; -IPL_D0_2_ = NODE,13, B,-; -SM_AMIGA_3_ = NODE,12, F,-; -inst_CLK_000_NE_D0 = NODE,15, B,-; +cpu_est_2_ = NODE,12, C,-; +IPL_D0_0_ = NODE,3, D,-; +IPL_D0_1_ = NODE,14, D,-; +IPL_D0_2_ = NODE,11, G,-; +SM_AMIGA_3_ = NODE,8, C,-; +inst_CLK_000_NE_D0 = NODE,8, E,-; SM_AMIGA_0_ = NODE,9, F,-; inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,10, G,-; -SM_AMIGA_6_ = NODE,4, C,-; -RST_DLY_0_ = NODE,10, B,-; -RST_DLY_1_ = NODE,1, A,-; +SM_AMIGA_6_ = NODE,5, F,-; +RST_DLY_0_ = NODE,6, C,-; +RST_DLY_1_ = NODE,13, B,-; RST_DLY_2_ = NODE,5, B,-; -RST_DLY_3_ = NODE,0, B,-; -RST_DLY_4_ = NODE,12, B,-; -RST_DLY_5_ = NODE,12, A,-; -RST_DLY_6_ = NODE,11, B,-; -RST_DLY_7_ = NODE,5, A,-; -CLK_000_P_SYNC_0_ = NODE,11, D,-; -CLK_000_P_SYNC_1_ = NODE,11, G,-; -CLK_000_P_SYNC_2_ = NODE,3, B,-; -CLK_000_P_SYNC_3_ = NODE,9, C,-; -CLK_000_P_SYNC_4_ = NODE,4, B,-; -CLK_000_P_SYNC_5_ = NODE,9, E,-; -CLK_000_P_SYNC_6_ = NODE,5, E,-; -CLK_000_P_SYNC_7_ = NODE,7, G,-; -CLK_000_P_SYNC_8_ = NODE,5, C,-; -CLK_000_N_SYNC_0_ = NODE,7, D,-; -CLK_000_N_SYNC_1_ = NODE,15, A,-; -CLK_000_N_SYNC_2_ = NODE,11, A,-; -CLK_000_N_SYNC_3_ = NODE,7, A,-; -CLK_000_N_SYNC_4_ = NODE,3, D,-; -CLK_000_N_SYNC_5_ = NODE,3, A,-; -CLK_000_N_SYNC_6_ = NODE,14, D,-; -CLK_000_N_SYNC_7_ = NODE,8, E,-; -CLK_000_N_SYNC_8_ = NODE,14, A,-; -CLK_000_N_SYNC_9_ = NODE,3, G,-; +RST_DLY_3_ = NODE,9, C,-; +RST_DLY_4_ = NODE,14, C,-; +RST_DLY_5_ = NODE,9, B,-; +RST_DLY_6_ = NODE,2, C,-; +RST_DLY_7_ = NODE,10, C,-; +CLK_000_P_SYNC_0_ = NODE,10, D,-; +CLK_000_P_SYNC_1_ = NODE,11, C,-; +CLK_000_P_SYNC_2_ = NODE,11, B,-; +CLK_000_P_SYNC_3_ = NODE,7, C,-; +CLK_000_P_SYNC_4_ = NODE,6, D,-; +CLK_000_P_SYNC_5_ = NODE,10, F,-; +CLK_000_P_SYNC_6_ = NODE,3, A,-; +CLK_000_P_SYNC_7_ = NODE,14, A,-; +CLK_000_P_SYNC_8_ = NODE,10, A,-; +CLK_000_N_SYNC_0_ = NODE,6, F,-; +CLK_000_N_SYNC_1_ = NODE,7, G,-; +CLK_000_N_SYNC_2_ = NODE,3, G,-; +CLK_000_N_SYNC_3_ = NODE,7, B,-; +CLK_000_N_SYNC_4_ = NODE,3, B,-; +pos_clk_un29_clk_000_ne_d0_i_n = NODE,2, D,-; +CLK_000_N_SYNC_5_ = NODE,14, B,-; +CLK_000_N_SYNC_6_ = NODE,6, A,-; +CLK_000_N_SYNC_7_ = NODE,10, B,-; +CLK_000_N_SYNC_8_ = NODE,14, G,-; +CLK_000_N_SYNC_9_ = NODE,2, F,-; CLK_000_N_SYNC_10_ = NODE,2, H,-; -inst_CLK_030_H = NODE,2, A,-; -SM_AMIGA_1_ = NODE,1, F,-; -SM_AMIGA_4_ = NODE,10, F,-; -SM_AMIGA_2_ = NODE,2, F,-; -inst_DS_000_ENABLE = NODE,12, C,-; -SM_AMIGA_i_7_ = NODE,0, F,-; +inst_CLK_030_H = NODE,9, A,-; +SM_AMIGA_1_ = NODE,1, C,-; +SM_AMIGA_4_ = NODE,1, F,-; +SM_AMIGA_2_ = NODE,13, C,-; +inst_DS_000_ENABLE = NODE,12, A,-; +SM_AMIGA_i_7_ = NODE,8, F,-; +CIIN_0 = NODE,5, E,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index c97992f..c7c4021 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.8.00.04.29.14 -Design '68030_tk' created Thu Jul 09 18:48:59 2015 +Design '68030_tk' created Thu Sep 24 16:20:59 2015 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 4fd2688..e1b73fa 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,238 +1,238 @@ -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ IPL_030_2_ A_25_ A_24_ IPL_2_ A_23_ A_22_ FC_1_ A_21_ AS_030 A_20_ AS_000 A_19_ RW_000 A_18_ DS_030 A_17_ UDS_000 A_16_ LDS_000 A_15_ A0 A_14_ A1 A_13_ nEXP_SPACE A_12_ BERR A_11_ BG_030 A_10_ BG_000 A_9_ BGACK_030 A_8_ BGACK_000 A_7_ CLK_030 A_6_ CLK_000 A_5_ CLK_OSZI A_4_ CLK_DIV_OUT A_3_ CLK_EXP A_2_ FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN -#$ NODES 694 N_193 cpu_est_0_1__un3_n N_190 RW_c cpu_est_0_1__un1_n N_189 cpu_est_0_1__un0_n N_140 fc_c_0__n bgack_030_int_0_un3_n \ -# pos_clk_un29_clk_000_ne_d0_n bgack_030_int_0_un1_n pos_clk_un23_clk_000_ne_d0_n fc_c_1__n bgack_030_int_0_un0_n inst_BGACK_030_INTreg pos_clk_un21_clk_000_ne_d0_n un1_amiga_bus_enable_dma_high_i_m4_0__un3_n vcc_n_n pos_clk_un7_clk_000_pe_n \ -# un1_amiga_bus_enable_dma_high_i_m4_0__un1_n cpu_est_3_reg N_18 AMIGA_BUS_DATA_DIR_c un1_amiga_bus_enable_dma_high_i_m4_0__un0_n inst_VMA_INTreg N_22 ds_000_enable_1_sqmuxa_1_i_m4_un3_n inst_RESET_OUTreg pos_clk_un11_clk_000_n_sync_n \ -# ds_000_enable_1_sqmuxa_1_i_m4_un1_n gnd_n_n pos_clk_un9_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un0_n un1_amiga_bus_enable_low pos_clk_un14_clk_000_n_sync_n size_dma_0_0__un3_n un6_as_030 pos_clk_un22_bgack_030_int_n N_6_i \ -# size_dma_0_0__un1_n un3_size G_161 N_48_0 size_dma_0_0__un0_n un4_size N_220 N_3_i size_dma_0_1__un3_n un8_ciin \ -# G_159 N_49_0 size_dma_0_1__un1_n un14_amiga_bus_data_dir pos_clk_un40_bgack_030_int_1_n pos_clk_un29_bgack_030_int_i_n size_dma_0_1__un0_n un4_as_000 CLK_030_H_0_sqmuxa pos_clk_un26_bgack_030_int_i_n \ -# ipl_030_0_0__un3_n un21_fpu_cs AS_000_DMA_1_sqmuxa pos_clk_un27_bgack_030_int_0_n ipl_030_0_0__un1_n un22_berr pos_clk_un24_bgack_030_int_n CLK_030_H_0_sqmuxa_i ipl_030_0_0__un0_n un6_ds_030 \ -# pos_clk_un27_bgack_030_int_n N_7_i ipl_030_0_1__un3_n un6_uds_000 N_176_1 N_47_0 ipl_030_0_1__un1_n un6_lds_000 N_165 N_133_i \ -# ipl_030_0_1__un0_n cpu_est_0_ N_133 N_176_i ipl_030_0_2__un3_n cpu_est_1_ N_163 N_175_i ipl_030_0_2__un1_n inst_AS_000_INT \ -# N_162 AMIGA_BUS_DATA_DIR_c_0 ipl_030_0_2__un0_n SM_AMIGA_5_ N_164 pos_clk_ds_000_dma_4_f1_0_n dsack1_int_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW N_176 N_162_i \ -# dsack1_int_0_un1_n inst_AS_030_D0 DS_000_DMA_2_sqmuxa N_163_i dsack1_int_0_un0_n inst_nEXP_SPACE_D0reg pos_clk_ds_000_dma_4_n N_164_i as_000_int_0_un3_n inst_DS_030_D0 \ -# DS_000_DMA_0_sqmuxa N_165_i as_000_int_0_un1_n inst_AS_030_000_SYNC pos_clk_ds_000_dma_4_f1_n as_000_int_0_un0_n inst_BGACK_030_INT_D N_175 pos_clk_un22_bgack_030_int_0_n ds_000_enable_0_un3_n \ -# inst_AS_000_DMA N_47 pos_clk_un9_clk_000_n_sync_i_n ds_000_enable_0_un1_n inst_DS_000_DMA N_7 clk_000_n_sync_i_10__n ds_000_enable_0_un0_n CYCLE_DMA_0_ un1_rst_2 \ -# pos_clk_un14_clk_000_n_sync_0_n as_030_000_sync_0_un3_n CYCLE_DMA_1_ pos_clk_un26_bgack_030_int_n N_22_i as_030_000_sync_0_un1_n SIZE_DMA_0_ pos_clk_un29_bgack_030_int_n N_33_0 as_030_000_sync_0_un0_n \ -# SIZE_DMA_1_ N_3 N_18_i lds_000_int_0_un3_n inst_VPA_D N_6 N_37_0 lds_000_int_0_un1_n inst_UDS_000_INT un1_amiga_bus_enable_low_i \ -# pos_clk_un9_clk_000_ne_i_n lds_000_int_0_un0_n inst_LDS_000_INT un21_fpu_cs_i pos_clk_un5_clk_000_pe_i_n rw_000_int_0_un3_n inst_CLK_OUT_PRE_D AS_000_i pos_clk_un7_clk_000_pe_0_n rw_000_int_0_un1_n \ -# inst_DTACK_D0 DS_000_DMA_i pos_clk_un27_clk_000_ne_d0_i_n rw_000_int_0_un0_n inst_CLK_OUT_PRE_50 pos_clk_un24_bgack_030_int_i_n pos_clk_un21_clk_000_ne_d0_i_n rw_000_dma_0_un3_n inst_CLK_000_D1 cycle_dma_i_1__n \ -# pos_clk_un23_clk_000_ne_d0_0_n rw_000_dma_0_un1_n inst_CLK_000_D0 cycle_dma_i_0__n N_136_i rw_000_dma_0_un0_n inst_CLK_000_PE AS_000_DMA_i N_140_0 uds_000_int_0_un3_n \ -# CLK_000_P_SYNC_9_ CLK_EXP_i N_195_i uds_000_int_0_un1_n inst_CLK_000_NE BERR_i N_196_i uds_000_int_0_un0_n CLK_000_N_SYNC_11_ RW_000_i \ -# N_186_i amiga_bus_enable_dma_low_0_un3_n cpu_est_2_ DS_000_DMA_0_sqmuxa_i N_188_i amiga_bus_enable_dma_low_0_un1_n IPL_D0_0_ pos_clk_un40_bgack_030_int_1_i_n N_189_i amiga_bus_enable_dma_low_0_un0_n \ -# IPL_D0_1_ BGACK_030_INT_i N_190_i amiga_bus_enable_dma_high_0_un3_n IPL_D0_2_ nEXP_SPACE_D0_i N_193_i amiga_bus_enable_dma_high_0_un1_n SM_AMIGA_3_ CLK_000_PE_i \ -# N_191_i amiga_bus_enable_dma_high_0_un0_n inst_CLK_000_NE_D0 CLK_000_NE_i N_192_i bg_000_0_un3_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_194_i bg_000_0_un1_n \ -# SM_AMIGA_0_ sm_amiga_i_0__n pos_clk_cpu_est_11_0_1__n bg_000_0_un0_n inst_AMIGA_BUS_ENABLE_DMA_HIGH pos_clk_un7_clk_000_d0_i_n N_198_i a0_dma_0_un3_n inst_DSACK1_INTreg UDS_000_i \ -# N_197_i a0_dma_0_un1_n LDS_000_i N_199_i a0_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n pos_clk_un11_clk_000_n_sync_i_n pos_clk_cpu_est_11_0_3__n a_23__n pos_clk_ipl_n \ -# CLK_OUT_PRE_D_i N_151_i pos_clk_un3_ds_030_d0_n DTACK_D0_i N_150_i a_22__n SM_AMIGA_6_ sm_amiga_i_2__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa pos_clk_un29_clk_000_ne_d0_i_n \ -# N_135_i a_21__n RST_DLY_0_ cpu_est_i_0__n N_252_0 RST_DLY_1_ cpu_est_i_3__n N_85_i a_20__n RST_DLY_2_ \ -# cpu_est_i_2__n RST_DLY_3_ cpu_est_i_1__n N_38_0 a_15__n RST_DLY_4_ VPA_D_i un1_rst_dly_i_m_i_2__n RST_DLY_5_ VMA_INT_i \ -# a_14__n RST_DLY_6_ sm_amiga_i_1__n un1_rst_dly_i_m_i_3__n RST_DLY_7_ RESET_OUT_0_sqmuxa_i a_13__n pos_clk_un8_bg_030_n N_77_i_i un1_rst_dly_i_m_i_4__n \ -# CLK_000_P_SYNC_0_ un1_rst_dly_i_2__n a_12__n CLK_000_P_SYNC_1_ un1_rst_dly_i_3__n un1_rst_dly_i_m_i_5__n CLK_000_P_SYNC_2_ un1_rst_dly_i_4__n a_11__n CLK_000_P_SYNC_3_ \ -# un1_rst_dly_i_5__n un1_rst_dly_i_m_i_6__n CLK_000_P_SYNC_4_ un1_rst_dly_i_6__n a_10__n CLK_000_P_SYNC_5_ un1_rst_dly_i_7__n un1_rst_dly_i_m_i_7__n CLK_000_P_SYNC_6_ un1_rst_dly_i_8__n \ -# a_9__n CLK_000_P_SYNC_7_ RESET_OUT_i un1_rst_dly_i_m_i_8__n CLK_000_P_SYNC_8_ AS_030_D0_i a_8__n CLK_000_N_SYNC_0_ AS_030_i un3_as_030_i \ -# CLK_000_N_SYNC_1_ A1_i N_76_i a_7__n CLK_000_N_SYNC_2_ CLK_000_D1_i N_83_i CLK_000_N_SYNC_3_ sm_amiga_i_i_7__n a_6__n \ -# CLK_000_N_SYNC_4_ N_248_i N_84_i CLK_000_N_SYNC_5_ sm_amiga_i_5__n N_115_0 a_5__n CLK_000_N_SYNC_6_ RW_i N_86_i \ -# CLK_000_N_SYNC_7_ CLK_000_D0_i pos_clk_size_dma_6_0_1__n a_4__n CLK_000_N_SYNC_8_ AS_030_000_SYNC_i N_87_i CLK_000_N_SYNC_9_ sm_amiga_i_6__n pos_clk_size_dma_6_0_0__n \ -# a_3__n CLK_000_N_SYNC_10_ sm_amiga_i_4__n N_88_i pos_clk_un5_bgack_030_int_d_n FPU_SENSE_i a_2__n inst_RW_000_INT size_dma_i_0__n N_241_0 \ -# inst_RW_000_DMA size_dma_i_1__n N_242_0 inst_A0_DMA a_i_16__n N_243_0 inst_CLK_030_H a_i_18__n N_93_i SM_AMIGA_1_ \ -# a_i_19__n N_94_i SM_AMIGA_4_ a_i_30__n N_244_0 SM_AMIGA_2_ a_i_31__n N_245_0 pos_clk_un3_as_030_d0_n a_i_28__n \ -# N_246_0 inst_DS_000_ENABLE a_i_29__n pos_clk_un3_as_030_d0_i_n a_i_26__n pos_clk_un5_bgack_030_int_d_i_n a_i_27__n N_249_i pos_clk_a0_dma_3_n a_i_24__n \ -# N_251_0 a_i_25__n N_71_0 LDS_000_INT_i N_104_i N_8 DS_030_i N_137_i N_9 UDS_000_INT_i \ -# N_10 N_224_i N_160_i N_11 N_225_i N_161_i N_12 N_226_i N_13 N_159_i \ -# N_14 N_157_i N_15 N_158_i N_16 N_91_i N_19 N_90_i N_155_i N_20 \ -# un14_amiga_bus_data_dir_i N_156_i N_21 N_80_i N_23 un6_lds_000_i N_154_i N_24 un6_uds_000_i N_152_i \ -# N_25 un6_ds_030_i N_153_i cpu_est_0_0_ un4_as_000_i N_142_0 AS_000_INT_i N_141_0 un6_as_030_i N_138_0 \ -# AMIGA_BUS_ENABLE_DMA_LOW_i N_132_i DS_030_D0_i un1_as_030_i AS_030_c pos_clk_un11_ds_030_d0_i_n A0_c_i AS_000_c size_c_i_1__n N_25_i \ -# RW_000_c N_32_0 N_24_i DS_030_c N_31_0 N_23_i UDS_000_c N_30_0 ipl_c_i_2__n LDS_000_c \ -# N_54_0 ipl_c_i_1__n size_c_0__n N_53_0 ipl_c_i_0__n size_c_1__n N_52_0 DTACK_c_i N_57_0 VPA_c_i \ -# N_56_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_8_i N_46_0 N_9_i N_45_0 N_10_i SM_AMIGA_i_7_ \ -# N_44_0 N_115 N_12_i pos_clk_size_dma_6_0__n N_43_0 pos_clk_size_dma_6_1__n N_13_i G_165 N_42_0 G_166 \ -# N_14_i G_167 N_41_0 un6_uds_000_1 N_15_i N_241 N_40_0 N_242 N_16_i N_243 \ -# N_39_0 N_244 N_19_i N_245 N_36_0 N_246 N_20_i N_78 N_35_0 N_80 \ -# N_21_i N_89 N_34_0 N_90 a_c_16__n BG_030_c_i N_91 pos_clk_un6_bg_030_i_n N_98 a_c_17__n \ -# pos_clk_un8_bg_030_0_n N_99 N_251_0_1 N_249 a_c_18__n N_121_i_1 N_248 pos_clk_cpu_est_11_0_1_3__n N_135 a_c_19__n \ -# pos_clk_cpu_est_11_0_1_1__n N_136 pos_clk_cpu_est_11_0_2_1__n pos_clk_un7_clk_000_d0_n N_131_i_1 un22_berr_1 N_131_i_2 N_152 N_131_i_3 N_153 \ -# pos_clk_un11_ds_030_d0_i_1_n N_154 un8_ciin_1 N_155 un8_ciin_2 N_141 un8_ciin_3 N_156 un8_ciin_4 N_157 \ -# a_c_24__n un8_ciin_5 N_138 un8_ciin_6 N_158 a_c_25__n un8_ciin_7 N_159 un8_ciin_8 N_160 \ -# a_c_26__n N_116_1 N_142 N_116_2 N_161 a_c_27__n N_116_3 N_132 N_116_4 N_104 \ -# a_c_28__n un22_berr_1_0 N_76 un21_fpu_cs_1 N_71 a_c_29__n N_123_i_1 N_251 N_123_i_2 N_93 \ -# a_c_30__n N_125_i_1 N_94 N_127_i_1 N_88 a_c_31__n N_127_i_2 N_87 N_129_i_1 N_86 \ -# A0_c pos_clk_un6_bg_030_1_n N_84 pos_clk_un7_clk_000_d0_1_n N_83 A1_c RESET_OUT_0_sqmuxa_7_1 N_116 RESET_OUT_0_sqmuxa_7_2 G_149 \ -# nEXP_SPACE_c RESET_OUT_0_sqmuxa_7_3 G_147 RESET_OUT_0_sqmuxa_5_1 N_213 BERR_c N_135_i_1 G_145 pos_clk_un27_clk_000_ne_d0_1_n N_211 \ -# BG_030_c pos_clk_un27_clk_000_ne_d0_2_n G_143 pos_clk_un27_clk_000_ne_d0_3_n N_209 BG_000DFFreg pos_clk_un5_clk_000_pe_1_n G_141 pos_clk_un5_clk_000_pe_2_n G_139 \ -# pos_clk_un5_clk_000_pe_3_n N_205 BGACK_000_c pos_clk_un9_clk_000_ne_1_n G_137 pos_clk_un9_clk_000_ne_2_n RESET_OUT_0_sqmuxa_1 pos_clk_un9_clk_000_ne_3_n RESET_OUT_0_sqmuxa pos_clk_un9_clk_000_ne_4_n \ -# RESET_OUT_0_sqmuxa_7 N_196_1 RESET_OUT_0_sqmuxa_5 CLK_OSZI_c N_195_1 un1_rst_dly_i_m_8__n pos_clk_un24_bgack_030_int_1_n un1_rst_dly_i_m_7__n N_165_1 un1_rst_dly_i_m_6__n \ -# CLK_EXP_c N_165_2 un1_rst_dly_i_m_5__n N_165_3 un1_rst_dly_i_m_4__n N_163_1 un1_rst_dly_i_m_3__n FPU_SENSE_c N_162_1 un1_rst_dly_i_m_2__n \ -# N_176_1_0 N_38 IPL_030DFF_0_reg DS_000_DMA_2_sqmuxa_1 N_85 N_119_i_1 pos_clk_RST_DLY_5_iv_0_x2_0_ IPL_030DFF_1_reg N_115_0_1 N_252 \ -# pos_clk_ipl_1_n N_97 IPL_030DFF_2_reg as_000_dma_0_un3_n pos_clk_un27_clk_000_ne_d0_n as_000_dma_0_un1_n N_199_1 ipl_c_0__n as_000_dma_0_un0_n pos_clk_un5_clk_000_pe_n \ -# ds_000_dma_0_un3_n pos_clk_un9_clk_000_ne_n ipl_c_1__n ds_000_dma_0_un1_n N_150 ds_000_dma_0_un0_n N_151 ipl_c_2__n vma_int_0_un3_n N_199 \ -# vma_int_0_un1_n N_196 vma_int_0_un0_n N_195 DTACK_c sm_amiga_srsts_i_0_m2_1__un3_n N_188 sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_cpu_est_11_3__n sm_amiga_srsts_i_0_m2_1__un0_n \ -# N_197 cpu_est_0_3__un3_n N_198 VPA_c cpu_est_0_3__un1_n pos_clk_cpu_est_11_1__n cpu_est_0_3__un0_n N_194 cpu_est_0_2__un3_n N_192 \ -# RST_c cpu_est_0_2__un1_n N_191 cpu_est_0_2__un0_n +#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 695 N_159 N_21_i bgack_030_int_0_un0_n N_157 N_34_0 as_030_000_sync_0_un3_n N_158 N_20_i as_030_000_sync_0_un1_n un1_rst_dly_i_m_1__n \ +# N_35_0 as_030_000_sync_0_un0_n N_138 N_16_i ds_000_enable_0_un3_n N_88 N_39_0 ds_000_enable_0_un1_n inst_BGACK_030_INTreg N_256 \ +# N_13_i ds_000_enable_0_un0_n vcc_n_n N_89 N_42_0 a0_dma_0_un3_n cpu_est_3_reg N_91 N_12_i a0_dma_0_un1_n \ +# inst_VMA_INTreg N_92 N_43_0 a0_dma_0_un0_n inst_RESET_OUTreg pos_clk_a0_dma_3_n N_8_i size_dma_0_1__un3_n gnd_n_n N_96 \ +# N_46_0 size_dma_0_1__un1_n un1_amiga_bus_enable_low N_72 N_76_i size_dma_0_1__un0_n un6_as_030 N_97 N_72_0 size_dma_0_0__un3_n \ +# un3_size N_116 UDS_000_c_i size_dma_0_0__un1_n un4_size N_104 LDS_000_c_i size_dma_0_0__un0_n un5_ciin N_76 \ +# N_256_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un8_ciin pos_clk_size_dma_6_1__n pos_clk_un5_bgack_030_int_d_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n un4_as_000 pos_clk_size_dma_6_0__n pos_clk_un24_bgack_030_int_i_0_0_n un1_amiga_bus_enable_dma_high_i_m2_0__un0_n \ +# un1_SM_AMIGA_7 N_250 N_104_i cpu_est_0_1__un3_n un21_fpu_cs pos_clk_un6_bgack_000_n N_252_0 cpu_est_0_1__un1_n un22_berr N_251 \ +# N_251_0 cpu_est_0_1__un0_n un6_ds_030 N_252 pos_clk_un6_bgack_000_0_n cpu_est_0_2__un3_n un6_uds_000 pos_clk_un5_bgack_030_int_d_n N_97_i cpu_est_0_2__un1_n \ +# un6_lds_000 pos_clk_un24_bgack_030_int_i_0_x2 N_96_i cpu_est_0_2__un0_n cpu_est_0_ DS_000_ENABLE_1_sqmuxa_1 N_250_0 cpu_est_0_3__un3_n cpu_est_1_ un22_berr_1 \ +# N_89_i cpu_est_0_3__un1_n inst_AS_000_INT N_8 pos_clk_size_dma_6_0_0__n cpu_est_0_3__un0_n SM_AMIGA_5_ N_12 N_88_i ipl_030_0_0__un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW N_13 pos_clk_size_dma_6_0_1__n ipl_030_0_0__un1_n inst_AS_030_D0 N_16 N_138_0 ipl_030_0_0__un0_n inst_nEXP_SPACE_D0reg N_20 \ +# un1_rst_dly_i_m_i_1__n ipl_030_0_1__un3_n inst_DS_030_D0 N_21 ipl_030_0_1__un1_n inst_AS_030_000_SYNC N_11 N_157_i ipl_030_0_1__un0_n inst_BGACK_030_INT_D \ +# un1_amiga_bus_enable_low_i N_158_i ipl_030_0_2__un3_n inst_AS_000_DMA un21_fpu_cs_i N_159_i ipl_030_0_2__un1_n inst_DS_000_DMA BGACK_030_INT_i ipl_030_0_2__un0_n \ +# CYCLE_DMA_0_ AMIGA_BUS_ENABLE_DMA_LOW_i N_257_0 dsack1_int_0_un3_n CYCLE_DMA_1_ AS_030_i un1_as_000_i dsack1_int_0_un1_n SIZE_DMA_0_ AS_000_INT_i \ +# N_93_i dsack1_int_0_un0_n SIZE_DMA_1_ N_105_i as_000_int_0_un3_n inst_VPA_D N_91_i N_87_i as_000_int_0_un1_n inst_UDS_000_INT \ +# N_92_i N_86_i as_000_int_0_un0_n inst_LDS_000_INT a_i_19__n AMIGA_BUS_DATA_DIR_c_0 lds_000_int_0_un3_n inst_CLK_OUT_PRE_D a_i_18__n un1_rst_dly_i_m_i_2__n \ +# lds_000_int_0_un1_n inst_DTACK_D0 a_i_16__n lds_000_int_0_un0_n inst_CLK_OUT_PRE_50 size_dma_i_1__n un1_rst_dly_i_m_i_3__n rw_000_int_0_un3_n inst_CLK_000_D1 size_dma_i_0__n \ +# rw_000_int_0_un1_n inst_CLK_000_D0 FPU_SENSE_i un1_rst_dly_i_m_i_4__n rw_000_int_0_un0_n inst_CLK_000_PE CLK_000_D1_i uds_000_int_0_un3_n CLK_000_P_SYNC_9_ CLK_000_D0_i \ +# un1_rst_dly_i_m_i_5__n uds_000_int_0_un1_n inst_CLK_000_NE AS_030_000_SYNC_i uds_000_int_0_un0_n CLK_000_N_SYNC_11_ AS_030_D0_i un1_rst_dly_i_m_i_6__n vma_int_0_un3_n cpu_est_2_ \ +# sm_amiga_i_i_7__n vma_int_0_un1_n IPL_D0_0_ AS_000_i un1_rst_dly_i_m_i_7__n vma_int_0_un0_n IPL_D0_1_ CLK_000_PE_i bg_000_0_un3_n IPL_D0_2_ \ +# nEXP_SPACE_D0_i un1_rst_dly_i_m_i_8__n bg_000_0_un1_n SM_AMIGA_3_ A1_i bg_000_0_un0_n inst_CLK_000_NE_D0 sm_amiga_i_6__n un3_as_030_i ds_000_dma_0_un3_n \ +# pos_clk_un6_bg_030_n BERR_i un1_as_030_i ds_000_dma_0_un1_n SM_AMIGA_0_ sm_amiga_i_5__n clk_000_n_sync_i_10__n ds_000_dma_0_un0_n inst_AMIGA_BUS_ENABLE_DMA_HIGH RESET_OUT_0_sqmuxa_i \ +# pos_clk_un9_clk_000_n_sync_i_n as_000_dma_0_un3_n inst_DSACK1_INTreg un1_rst_dly_i_1__n pos_clk_un14_clk_000_n_sync_0_n as_000_dma_0_un1_n RESET_OUT_i CLK_EXP_c_i as_000_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n \ +# RW_000_i N_244_0 a_15__n pos_clk_ipl_n un1_rst_dly_i_2__n N_83_i pos_clk_un3_ds_030_d0_n un1_rst_dly_i_3__n N_115_0 a_14__n \ +# SM_AMIGA_6_ un1_rst_dly_i_4__n N_84_i RST_DLY_0_ un1_rst_dly_i_5__n N_245_0 a_13__n RST_DLY_1_ un1_rst_dly_i_6__n N_85_i \ +# RST_DLY_2_ un1_rst_dly_i_7__n pos_clk_ds_000_dma_4_0_n a_12__n RST_DLY_3_ un1_rst_dly_i_8__n N_94_i RST_DLY_4_ CLK_OUT_PRE_D_i a_11__n \ +# RST_DLY_5_ pos_clk_un11_clk_000_n_sync_i_n RST_DLY_6_ CLK_030_H_i a_10__n RST_DLY_7_ AS_000_DMA_i N_73_0 pos_clk_un8_bg_030_n VMA_INT_i \ +# a_9__n CLK_000_P_SYNC_0_ VPA_D_i N_160_i CLK_000_P_SYNC_1_ cpu_est_i_0__n N_161_i a_8__n CLK_000_P_SYNC_2_ cpu_est_i_1__n \ +# CLK_000_P_SYNC_3_ cpu_est_i_3__n N_155_i a_7__n CLK_000_P_SYNC_4_ a_i_24__n N_156_i CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_d0_i_n a_6__n \ +# CLK_000_P_SYNC_6_ sm_amiga_i_0__n N_154_i CLK_000_P_SYNC_7_ sm_amiga_i_3__n N_152_i a_5__n CLK_000_P_SYNC_8_ CLK_000_NE_i N_153_i \ +# CLK_000_N_SYNC_0_ cpu_est_i_2__n a_4__n CLK_000_N_SYNC_1_ sm_amiga_i_1__n N_150_i CLK_000_N_SYNC_2_ sm_amiga_i_4__n N_151_i a_3__n \ +# CLK_000_N_SYNC_3_ sm_amiga_i_2__n CLK_000_N_SYNC_4_ pos_clk_un29_clk_000_ne_d0_i_n N_149_i a_2__n CLK_000_N_SYNC_5_ DSACK1_INT_0_sqmuxa_i N_147_i CLK_000_N_SYNC_6_ \ +# RW_i N_148_i CLK_000_N_SYNC_7_ un5_ciin_i CLK_000_N_SYNC_8_ DTACK_D0_i N_164_i CLK_000_N_SYNC_9_ a_i_31__n N_165_i \ +# CLK_000_N_SYNC_10_ a_i_29__n N_163_i inst_RW_000_INT a_i_30__n N_199_i inst_RW_000_DMA a_i_27__n pos_clk_cpu_est_11_0_3__n pos_clk_un7_clk_000_pe_n \ +# a_i_28__n N_197_i inst_A0_DMA a_i_25__n N_198_i DS_000_ENABLE_1_sqmuxa a_i_26__n N_194_i inst_CLK_030_H UDS_000_INT_i \ +# pos_clk_cpu_est_11_0_1__n SM_AMIGA_1_ LDS_000_INT_i N_192_i SM_AMIGA_4_ DS_030_i N_135_i SM_AMIGA_2_ N_224_i N_162_i \ +# inst_DS_000_ENABLE N_225_i N_191_i AS_000_INT_1_sqmuxa N_226_i N_193_i DSACK1_INT_1_sqmuxa N_190_i pos_clk_ds_000_dma_4_n N_189_i \ +# N_3 DS_000_ENABLE_1_sqmuxa_i N_188_i un6_lds_000_i N_195_i un6_uds_000_i N_196_i N_6 un6_ds_030_i N_186_i \ +# N_9 DS_000_DMA_i N_143_0 N_10 un4_as_000_i N_142_0 N_14 un8_ciin_i N_141_0 N_15 \ +# un6_as_030_i N_140_0 N_17 DS_030_D0_i N_139_0 N_19 AS_030_c N_166_i N_22 N_137_i \ +# N_23 AS_000_c N_136_i N_24 N_133_i N_25 RW_000_c N_132_i cpu_est_0_0_ N_146_i \ +# DS_030_c N_144_i UDS_000_c un1_SM_AMIGA_7_i pos_clk_un21_clk_000_ne_d0_i_n LDS_000_c pos_clk_un27_clk_000_ne_d0_i_n pos_clk_un23_clk_000_ne_d0_0_n size_c_0__n pos_clk_un5_clk_000_pe_i_n \ +# pos_clk_un9_clk_000_ne_i_n size_c_1__n pos_clk_un7_clk_000_pe_0_n pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 \ +# N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 DTACK_c_i N_57_0 \ +# VPA_c_i N_56_0 nEXP_SPACE_c_i SM_AMIGA_i_7_ N_55_0 N_115 N_50_0 pos_clk_cpu_est_11_1__n N_3_i pos_clk_cpu_est_11_3__n \ +# N_49_0 N_220 N_6_i G_165 N_48_0 G_166 N_9_i G_167 N_45_0 un6_uds_000_1 \ +# N_10_i pos_clk_un24_bgack_030_int_i_0_n a_c_16__n N_44_0 N_244 N_14_i N_245 a_c_17__n N_41_0 N_15_i \ +# N_80 a_c_18__n N_40_0 N_90 N_17_i N_100 a_c_19__n N_38_0 N_105 N_19_i \ +# pos_clk_un11_clk_000_n_sync_n a_c_20__n N_36_0 pos_clk_CYCLE_DMA_5_1_i_x2 N_22_i pos_clk_CYCLE_DMA_5_0_i_x2 a_c_21__n N_33_0 N_135 BG_030_c_i \ +# N_133 a_c_22__n pos_clk_un6_bg_030_i_n N_190 pos_clk_un8_bg_030_0_n N_188 a_c_23__n N_127_i_1 N_189 N_127_i_2 \ +# N_136 a_c_24__n pos_clk_un11_ds_030_d0_i_1_n pos_clk_un7_clk_000_d0_n N_135_i_1 pos_clk_un29_clk_000_ne_d0_n a_c_25__n pos_clk_cpu_est_11_0_1_1__n DSACK1_INT_0_sqmuxa pos_clk_cpu_est_11_0_2_1__n \ +# pos_clk_un21_clk_000_ne_d0_n a_c_26__n pos_clk_cpu_est_11_0_1_3__n pos_clk_un5_clk_000_pe_n N_195_1 pos_clk_un9_clk_000_ne_n a_c_27__n N_196_1 pos_clk_un23_clk_000_ne_d0_n N_131_i_1 \ +# pos_clk_un27_clk_000_ne_d0_n a_c_28__n N_131_i_2 pos_clk_un14_clk_000_n_sync_n N_131_i_3 N_144 a_c_29__n N_119_i_1 N_146 N_119_i_2 \ +# N_143 a_c_30__n N_121_i_1 N_147 N_123_i_1 N_139 a_c_31__n N_123_i_2 N_148 N_125_i_1 \ +# N_149 A0_c N_129_i_1 N_150 N_162_1 N_140 A1_c N_163_1 N_151 N_165_1 \ +# N_152 nEXP_SPACE_c N_165_2 N_153 N_165_3 N_154 BERR_c un5_ciin_1 N_155 un5_ciin_2 \ +# N_141 BG_030_c un5_ciin_3 N_156 un5_ciin_4 N_160 BG_000DFFreg un5_ciin_5 N_142 un5_ciin_6 \ +# N_161 un5_ciin_7 N_164 BGACK_000_c un5_ciin_8 N_166 un5_ciin_9 N_132 un5_ciin_10 N_191 \ +# un5_ciin_11 N_192 pos_clk_un9_clk_000_ne_1_n N_193 CLK_OSZI_c pos_clk_un9_clk_000_ne_2_n N_194 pos_clk_un9_clk_000_ne_3_n N_197 pos_clk_un9_clk_000_ne_4_n \ +# N_198 CLK_EXP_c pos_clk_un5_clk_000_pe_1_n N_195 pos_clk_un5_clk_000_pe_2_n N_196 pos_clk_un5_clk_000_pe_3_n N_162 FPU_SENSE_c pos_clk_un27_clk_000_ne_d0_1_n \ +# N_199 pos_clk_un27_clk_000_ne_d0_2_n N_199_1 IPL_030DFF_0_reg pos_clk_un27_clk_000_ne_d0_3_n N_163 RESET_OUT_0_sqmuxa_7_1 N_165 IPL_030DFF_1_reg RESET_OUT_0_sqmuxa_7_2 \ +# N_73 RESET_OUT_0_sqmuxa_7_3 N_94 IPL_030DFF_2_reg RESET_OUT_0_sqmuxa_5_1 N_85 N_87_1 N_84 ipl_c_0__n N_87_2 \ +# N_83 pos_clk_un24_bgack_030_int_i_0_0_1_n pos_clk_un9_clk_000_n_sync_n ipl_c_1__n pos_clk_un24_bgack_030_int_i_0_0_2_n G_149 N_72_0_1 G_147 ipl_c_2__n pos_clk_un7_clk_000_d0_1_n \ +# N_213 un21_fpu_cs_1 G_145 un22_berr_1_0 N_211 DTACK_c N_116_1 G_143 N_116_2 N_209 \ +# N_116_3 G_141 N_116_4 G_139 VPA_c pos_clk_un6_bg_030_1_n N_205 N_115_0_1 G_137 N_245_0_1 \ +# RESET_OUT_0_sqmuxa_1 RST_c N_247_i_1 RESET_OUT_0_sqmuxa N_248_i_1 RESET_OUT_0_sqmuxa_7 N_249_i_1 RESET_OUT_0_sqmuxa_5 RW_c pos_clk_ipl_1_n \ +# un1_rst_dly_i_m_8__n amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n fc_c_0__n amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n fc_c_1__n amiga_bus_enable_dma_low_0_un3_n \ +# un1_rst_dly_i_m_4__n amiga_bus_enable_dma_low_0_un1_n un1_rst_dly_i_m_3__n amiga_bus_enable_dma_low_0_un0_n un1_rst_dly_i_m_2__n AMIGA_BUS_DATA_DIR_c rw_000_dma_0_un3_n N_86 rw_000_dma_0_un1_n N_93 \ +# rw_000_dma_0_un0_n N_87 bgack_030_int_0_un3_n G_135 bgack_030_int_0_un1_n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \ A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF \ A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ - FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_193.BLIF cpu_est_0_1__un3_n.BLIF N_190.BLIF RW_c.BLIF cpu_est_0_1__un1_n.BLIF N_189.BLIF cpu_est_0_1__un0_n.BLIF N_140.BLIF \ - fc_c_0__n.BLIF bgack_030_int_0_un3_n.BLIF pos_clk_un29_clk_000_ne_d0_n.BLIF bgack_030_int_0_un1_n.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF fc_c_1__n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.BLIF pos_clk_un21_clk_000_ne_d0_n.BLIF \ - un1_amiga_bus_enable_dma_high_i_m4_0__un3_n.BLIF vcc_n_n.BLIF pos_clk_un7_clk_000_pe_n.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un1_n.BLIF cpu_est_3_reg.BLIF N_18.BLIF AMIGA_BUS_DATA_DIR_c.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un0_n.BLIF inst_VMA_INTreg.BLIF \ - N_22.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n.BLIF inst_RESET_OUTreg.BLIF pos_clk_un11_clk_000_n_sync_n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un1_n.BLIF gnd_n_n.BLIF pos_clk_un9_clk_000_n_sync_n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un0_n.BLIF un1_amiga_bus_enable_low.BLIF \ - pos_clk_un14_clk_000_n_sync_n.BLIF size_dma_0_0__un3_n.BLIF un6_as_030.BLIF pos_clk_un22_bgack_030_int_n.BLIF N_6_i.BLIF size_dma_0_0__un1_n.BLIF un3_size.BLIF G_161.BLIF N_48_0.BLIF \ - size_dma_0_0__un0_n.BLIF un4_size.BLIF N_220.BLIF N_3_i.BLIF size_dma_0_1__un3_n.BLIF un8_ciin.BLIF G_159.BLIF N_49_0.BLIF size_dma_0_1__un1_n.BLIF \ - un14_amiga_bus_data_dir.BLIF pos_clk_un40_bgack_030_int_1_n.BLIF pos_clk_un29_bgack_030_int_i_n.BLIF size_dma_0_1__un0_n.BLIF un4_as_000.BLIF CLK_030_H_0_sqmuxa.BLIF pos_clk_un26_bgack_030_int_i_n.BLIF ipl_030_0_0__un3_n.BLIF un21_fpu_cs.BLIF \ - AS_000_DMA_1_sqmuxa.BLIF pos_clk_un27_bgack_030_int_0_n.BLIF ipl_030_0_0__un1_n.BLIF un22_berr.BLIF pos_clk_un24_bgack_030_int_n.BLIF CLK_030_H_0_sqmuxa_i.BLIF ipl_030_0_0__un0_n.BLIF un6_ds_030.BLIF pos_clk_un27_bgack_030_int_n.BLIF \ - N_7_i.BLIF ipl_030_0_1__un3_n.BLIF un6_uds_000.BLIF N_176_1.BLIF N_47_0.BLIF ipl_030_0_1__un1_n.BLIF un6_lds_000.BLIF N_165.BLIF N_133_i.BLIF \ - ipl_030_0_1__un0_n.BLIF cpu_est_0_.BLIF N_133.BLIF N_176_i.BLIF ipl_030_0_2__un3_n.BLIF cpu_est_1_.BLIF N_163.BLIF N_175_i.BLIF ipl_030_0_2__un1_n.BLIF \ - inst_AS_000_INT.BLIF N_162.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF ipl_030_0_2__un0_n.BLIF SM_AMIGA_5_.BLIF N_164.BLIF pos_clk_ds_000_dma_4_f1_0_n.BLIF dsack1_int_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ - N_176.BLIF N_162_i.BLIF dsack1_int_0_un1_n.BLIF inst_AS_030_D0.BLIF DS_000_DMA_2_sqmuxa.BLIF N_163_i.BLIF dsack1_int_0_un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF pos_clk_ds_000_dma_4_n.BLIF \ - N_164_i.BLIF as_000_int_0_un3_n.BLIF inst_DS_030_D0.BLIF DS_000_DMA_0_sqmuxa.BLIF N_165_i.BLIF as_000_int_0_un1_n.BLIF inst_AS_030_000_SYNC.BLIF pos_clk_ds_000_dma_4_f1_n.BLIF as_000_int_0_un0_n.BLIF \ - inst_BGACK_030_INT_D.BLIF N_175.BLIF pos_clk_un22_bgack_030_int_0_n.BLIF ds_000_enable_0_un3_n.BLIF inst_AS_000_DMA.BLIF N_47.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF ds_000_enable_0_un1_n.BLIF inst_DS_000_DMA.BLIF \ - N_7.BLIF clk_000_n_sync_i_10__n.BLIF ds_000_enable_0_un0_n.BLIF CYCLE_DMA_0_.BLIF un1_rst_2.BLIF pos_clk_un14_clk_000_n_sync_0_n.BLIF as_030_000_sync_0_un3_n.BLIF CYCLE_DMA_1_.BLIF pos_clk_un26_bgack_030_int_n.BLIF \ - N_22_i.BLIF as_030_000_sync_0_un1_n.BLIF SIZE_DMA_0_.BLIF pos_clk_un29_bgack_030_int_n.BLIF N_33_0.BLIF as_030_000_sync_0_un0_n.BLIF SIZE_DMA_1_.BLIF N_3.BLIF N_18_i.BLIF \ - lds_000_int_0_un3_n.BLIF inst_VPA_D.BLIF N_6.BLIF N_37_0.BLIF lds_000_int_0_un1_n.BLIF inst_UDS_000_INT.BLIF un1_amiga_bus_enable_low_i.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF lds_000_int_0_un0_n.BLIF \ - inst_LDS_000_INT.BLIF un21_fpu_cs_i.BLIF pos_clk_un5_clk_000_pe_i_n.BLIF rw_000_int_0_un3_n.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_i.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF rw_000_int_0_un1_n.BLIF inst_DTACK_D0.BLIF \ - DS_000_DMA_i.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF rw_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF pos_clk_un24_bgack_030_int_i_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n.BLIF rw_000_dma_0_un3_n.BLIF inst_CLK_000_D1.BLIF cycle_dma_i_1__n.BLIF \ - pos_clk_un23_clk_000_ne_d0_0_n.BLIF rw_000_dma_0_un1_n.BLIF inst_CLK_000_D0.BLIF cycle_dma_i_0__n.BLIF N_136_i.BLIF rw_000_dma_0_un0_n.BLIF inst_CLK_000_PE.BLIF AS_000_DMA_i.BLIF N_140_0.BLIF \ - uds_000_int_0_un3_n.BLIF CLK_000_P_SYNC_9_.BLIF CLK_EXP_i.BLIF N_195_i.BLIF uds_000_int_0_un1_n.BLIF inst_CLK_000_NE.BLIF BERR_i.BLIF N_196_i.BLIF uds_000_int_0_un0_n.BLIF \ - CLK_000_N_SYNC_11_.BLIF RW_000_i.BLIF N_186_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF cpu_est_2_.BLIF DS_000_DMA_0_sqmuxa_i.BLIF N_188_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF IPL_D0_0_.BLIF \ - pos_clk_un40_bgack_030_int_1_i_n.BLIF N_189_i.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF IPL_D0_1_.BLIF BGACK_030_INT_i.BLIF N_190_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF IPL_D0_2_.BLIF nEXP_SPACE_D0_i.BLIF \ - N_193_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF SM_AMIGA_3_.BLIF CLK_000_PE_i.BLIF N_191_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF inst_CLK_000_NE_D0.BLIF CLK_000_NE_i.BLIF N_192_i.BLIF \ - bg_000_0_un3_n.BLIF pos_clk_un6_bg_030_n.BLIF sm_amiga_i_3__n.BLIF N_194_i.BLIF bg_000_0_un1_n.BLIF SM_AMIGA_0_.BLIF sm_amiga_i_0__n.BLIF pos_clk_cpu_est_11_0_1__n.BLIF bg_000_0_un0_n.BLIF \ - inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_198_i.BLIF a0_dma_0_un3_n.BLIF inst_DSACK1_INTreg.BLIF UDS_000_i.BLIF N_197_i.BLIF a0_dma_0_un1_n.BLIF LDS_000_i.BLIF \ - N_199_i.BLIF a0_dma_0_un0_n.BLIF pos_clk_clk_000_n_sync_2_0__n.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_cpu_est_11_0_3__n.BLIF a_23__n.BLIF pos_clk_ipl_n.BLIF CLK_OUT_PRE_D_i.BLIF N_151_i.BLIF \ - pos_clk_un3_ds_030_d0_n.BLIF DTACK_D0_i.BLIF N_150_i.BLIF a_22__n.BLIF SM_AMIGA_6_.BLIF sm_amiga_i_2__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_135_i.BLIF \ - a_21__n.BLIF RST_DLY_0_.BLIF cpu_est_i_0__n.BLIF N_252_0.BLIF RST_DLY_1_.BLIF cpu_est_i_3__n.BLIF N_85_i.BLIF a_20__n.BLIF RST_DLY_2_.BLIF \ - cpu_est_i_2__n.BLIF RST_DLY_3_.BLIF cpu_est_i_1__n.BLIF N_38_0.BLIF a_15__n.BLIF RST_DLY_4_.BLIF VPA_D_i.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_5_.BLIF \ - VMA_INT_i.BLIF a_14__n.BLIF RST_DLY_6_.BLIF sm_amiga_i_1__n.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa_i.BLIF a_13__n.BLIF pos_clk_un8_bg_030_n.BLIF \ - N_77_i_i.BLIF un1_rst_dly_i_m_i_4__n.BLIF CLK_000_P_SYNC_0_.BLIF un1_rst_dly_i_2__n.BLIF a_12__n.BLIF CLK_000_P_SYNC_1_.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_i_5__n.BLIF CLK_000_P_SYNC_2_.BLIF \ - un1_rst_dly_i_4__n.BLIF a_11__n.BLIF CLK_000_P_SYNC_3_.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_i_6__n.BLIF CLK_000_P_SYNC_4_.BLIF un1_rst_dly_i_6__n.BLIF a_10__n.BLIF CLK_000_P_SYNC_5_.BLIF \ - un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_i_7__n.BLIF CLK_000_P_SYNC_6_.BLIF un1_rst_dly_i_8__n.BLIF a_9__n.BLIF CLK_000_P_SYNC_7_.BLIF RESET_OUT_i.BLIF un1_rst_dly_i_m_i_8__n.BLIF CLK_000_P_SYNC_8_.BLIF \ - AS_030_D0_i.BLIF a_8__n.BLIF CLK_000_N_SYNC_0_.BLIF AS_030_i.BLIF un3_as_030_i.BLIF CLK_000_N_SYNC_1_.BLIF A1_i.BLIF N_76_i.BLIF a_7__n.BLIF \ - CLK_000_N_SYNC_2_.BLIF CLK_000_D1_i.BLIF N_83_i.BLIF CLK_000_N_SYNC_3_.BLIF sm_amiga_i_i_7__n.BLIF a_6__n.BLIF CLK_000_N_SYNC_4_.BLIF N_248_i.BLIF N_84_i.BLIF \ - CLK_000_N_SYNC_5_.BLIF sm_amiga_i_5__n.BLIF N_115_0.BLIF a_5__n.BLIF CLK_000_N_SYNC_6_.BLIF RW_i.BLIF N_86_i.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_D0_i.BLIF \ - pos_clk_size_dma_6_0_1__n.BLIF a_4__n.BLIF CLK_000_N_SYNC_8_.BLIF AS_030_000_SYNC_i.BLIF N_87_i.BLIF CLK_000_N_SYNC_9_.BLIF sm_amiga_i_6__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF a_3__n.BLIF \ - CLK_000_N_SYNC_10_.BLIF sm_amiga_i_4__n.BLIF N_88_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF FPU_SENSE_i.BLIF a_2__n.BLIF inst_RW_000_INT.BLIF size_dma_i_0__n.BLIF N_241_0.BLIF \ - inst_RW_000_DMA.BLIF size_dma_i_1__n.BLIF N_242_0.BLIF inst_A0_DMA.BLIF a_i_16__n.BLIF N_243_0.BLIF inst_CLK_030_H.BLIF a_i_18__n.BLIF N_93_i.BLIF \ - SM_AMIGA_1_.BLIF a_i_19__n.BLIF N_94_i.BLIF SM_AMIGA_4_.BLIF a_i_30__n.BLIF N_244_0.BLIF SM_AMIGA_2_.BLIF a_i_31__n.BLIF N_245_0.BLIF \ - pos_clk_un3_as_030_d0_n.BLIF a_i_28__n.BLIF N_246_0.BLIF inst_DS_000_ENABLE.BLIF a_i_29__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF a_i_26__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF a_i_27__n.BLIF \ - N_249_i.BLIF pos_clk_a0_dma_3_n.BLIF a_i_24__n.BLIF N_251_0.BLIF a_i_25__n.BLIF N_71_0.BLIF LDS_000_INT_i.BLIF N_104_i.BLIF N_8.BLIF \ - DS_030_i.BLIF N_137_i.BLIF N_9.BLIF UDS_000_INT_i.BLIF N_10.BLIF N_224_i.BLIF N_160_i.BLIF N_11.BLIF N_225_i.BLIF \ - N_161_i.BLIF N_12.BLIF N_226_i.BLIF N_13.BLIF N_159_i.BLIF N_14.BLIF N_157_i.BLIF N_15.BLIF N_158_i.BLIF \ - N_16.BLIF N_91_i.BLIF N_19.BLIF N_90_i.BLIF N_155_i.BLIF N_20.BLIF un14_amiga_bus_data_dir_i.BLIF N_156_i.BLIF N_21.BLIF \ - N_80_i.BLIF N_23.BLIF un6_lds_000_i.BLIF N_154_i.BLIF N_24.BLIF un6_uds_000_i.BLIF N_152_i.BLIF N_25.BLIF un6_ds_030_i.BLIF \ - N_153_i.BLIF cpu_est_0_0_.BLIF un4_as_000_i.BLIF N_142_0.BLIF AS_000_INT_i.BLIF N_141_0.BLIF un6_as_030_i.BLIF N_138_0.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF \ - N_132_i.BLIF DS_030_D0_i.BLIF un1_as_030_i.BLIF AS_030_c.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF AS_000_c.BLIF size_c_i_1__n.BLIF N_25_i.BLIF \ - RW_000_c.BLIF N_32_0.BLIF N_24_i.BLIF DS_030_c.BLIF N_31_0.BLIF N_23_i.BLIF UDS_000_c.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF \ - LDS_000_c.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF size_c_0__n.BLIF N_53_0.BLIF ipl_c_i_0__n.BLIF size_c_1__n.BLIF N_52_0.BLIF DTACK_c_i.BLIF \ - N_57_0.BLIF VPA_c_i.BLIF N_56_0.BLIF nEXP_SPACE_c_i.BLIF N_55_0.BLIF N_50_0.BLIF N_8_i.BLIF N_46_0.BLIF N_9_i.BLIF \ - N_45_0.BLIF N_10_i.BLIF SM_AMIGA_i_7_.BLIF N_44_0.BLIF N_115.BLIF N_12_i.BLIF pos_clk_size_dma_6_0__n.BLIF N_43_0.BLIF pos_clk_size_dma_6_1__n.BLIF \ - N_13_i.BLIF G_165.BLIF N_42_0.BLIF G_166.BLIF N_14_i.BLIF G_167.BLIF N_41_0.BLIF un6_uds_000_1.BLIF N_15_i.BLIF \ - N_241.BLIF N_40_0.BLIF N_242.BLIF N_16_i.BLIF N_243.BLIF N_39_0.BLIF N_244.BLIF N_19_i.BLIF N_245.BLIF \ - N_36_0.BLIF N_246.BLIF N_20_i.BLIF N_78.BLIF N_35_0.BLIF N_80.BLIF N_21_i.BLIF N_89.BLIF N_34_0.BLIF \ - N_90.BLIF a_c_16__n.BLIF BG_030_c_i.BLIF N_91.BLIF pos_clk_un6_bg_030_i_n.BLIF N_98.BLIF a_c_17__n.BLIF pos_clk_un8_bg_030_0_n.BLIF N_99.BLIF \ - N_251_0_1.BLIF N_249.BLIF a_c_18__n.BLIF N_121_i_1.BLIF N_248.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF N_135.BLIF a_c_19__n.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF \ - N_136.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_un7_clk_000_d0_n.BLIF N_131_i_1.BLIF un22_berr_1.BLIF N_131_i_2.BLIF N_152.BLIF N_131_i_3.BLIF N_153.BLIF \ - pos_clk_un11_ds_030_d0_i_1_n.BLIF N_154.BLIF un8_ciin_1.BLIF N_155.BLIF un8_ciin_2.BLIF N_141.BLIF un8_ciin_3.BLIF N_156.BLIF un8_ciin_4.BLIF \ - N_157.BLIF a_c_24__n.BLIF un8_ciin_5.BLIF N_138.BLIF un8_ciin_6.BLIF N_158.BLIF a_c_25__n.BLIF un8_ciin_7.BLIF N_159.BLIF \ - un8_ciin_8.BLIF N_160.BLIF a_c_26__n.BLIF N_116_1.BLIF N_142.BLIF N_116_2.BLIF N_161.BLIF a_c_27__n.BLIF N_116_3.BLIF \ - N_132.BLIF N_116_4.BLIF N_104.BLIF a_c_28__n.BLIF un22_berr_1_0.BLIF N_76.BLIF un21_fpu_cs_1.BLIF N_71.BLIF a_c_29__n.BLIF \ - N_123_i_1.BLIF N_251.BLIF N_123_i_2.BLIF N_93.BLIF a_c_30__n.BLIF N_125_i_1.BLIF N_94.BLIF N_127_i_1.BLIF N_88.BLIF \ - a_c_31__n.BLIF N_127_i_2.BLIF N_87.BLIF N_129_i_1.BLIF N_86.BLIF A0_c.BLIF pos_clk_un6_bg_030_1_n.BLIF N_84.BLIF pos_clk_un7_clk_000_d0_1_n.BLIF \ - N_83.BLIF A1_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_116.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF G_149.BLIF nEXP_SPACE_c.BLIF RESET_OUT_0_sqmuxa_7_3.BLIF G_147.BLIF \ - RESET_OUT_0_sqmuxa_5_1.BLIF N_213.BLIF BERR_c.BLIF N_135_i_1.BLIF G_145.BLIF pos_clk_un27_clk_000_ne_d0_1_n.BLIF N_211.BLIF BG_030_c.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF \ - G_143.BLIF pos_clk_un27_clk_000_ne_d0_3_n.BLIF N_209.BLIF BG_000DFFreg.BLIF pos_clk_un5_clk_000_pe_1_n.BLIF G_141.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF G_139.BLIF pos_clk_un5_clk_000_pe_3_n.BLIF \ - N_205.BLIF BGACK_000_c.BLIF pos_clk_un9_clk_000_ne_1_n.BLIF G_137.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF RESET_OUT_0_sqmuxa_1.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF RESET_OUT_0_sqmuxa.BLIF pos_clk_un9_clk_000_ne_4_n.BLIF \ - RESET_OUT_0_sqmuxa_7.BLIF N_196_1.BLIF RESET_OUT_0_sqmuxa_5.BLIF CLK_OSZI_c.BLIF N_195_1.BLIF un1_rst_dly_i_m_8__n.BLIF pos_clk_un24_bgack_030_int_1_n.BLIF un1_rst_dly_i_m_7__n.BLIF N_165_1.BLIF \ - un1_rst_dly_i_m_6__n.BLIF CLK_EXP_c.BLIF N_165_2.BLIF un1_rst_dly_i_m_5__n.BLIF N_165_3.BLIF un1_rst_dly_i_m_4__n.BLIF N_163_1.BLIF un1_rst_dly_i_m_3__n.BLIF FPU_SENSE_c.BLIF \ - N_162_1.BLIF un1_rst_dly_i_m_2__n.BLIF N_176_1_0.BLIF N_38.BLIF IPL_030DFF_0_reg.BLIF DS_000_DMA_2_sqmuxa_1.BLIF N_85.BLIF N_119_i_1.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF \ - IPL_030DFF_1_reg.BLIF N_115_0_1.BLIF N_252.BLIF pos_clk_ipl_1_n.BLIF N_97.BLIF IPL_030DFF_2_reg.BLIF as_000_dma_0_un3_n.BLIF pos_clk_un27_clk_000_ne_d0_n.BLIF as_000_dma_0_un1_n.BLIF \ - N_199_1.BLIF ipl_c_0__n.BLIF as_000_dma_0_un0_n.BLIF pos_clk_un5_clk_000_pe_n.BLIF ds_000_dma_0_un3_n.BLIF pos_clk_un9_clk_000_ne_n.BLIF ipl_c_1__n.BLIF ds_000_dma_0_un1_n.BLIF N_150.BLIF \ - ds_000_dma_0_un0_n.BLIF N_151.BLIF ipl_c_2__n.BLIF vma_int_0_un3_n.BLIF N_199.BLIF vma_int_0_un1_n.BLIF N_196.BLIF vma_int_0_un0_n.BLIF N_195.BLIF \ - DTACK_c.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_188.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF pos_clk_cpu_est_11_3__n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_197.BLIF cpu_est_0_3__un3_n.BLIF N_198.BLIF \ - VPA_c.BLIF cpu_est_0_3__un1_n.BLIF pos_clk_cpu_est_11_1__n.BLIF cpu_est_0_3__un0_n.BLIF N_194.BLIF cpu_est_0_2__un3_n.BLIF N_192.BLIF RST_c.BLIF cpu_est_0_2__un1_n.BLIF \ - N_191.BLIF cpu_est_0_2__un0_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN \ - SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN + FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_159.BLIF N_21_i.BLIF bgack_030_int_0_un0_n.BLIF N_157.BLIF N_34_0.BLIF as_030_000_sync_0_un3_n.BLIF N_158.BLIF N_20_i.BLIF \ + as_030_000_sync_0_un1_n.BLIF un1_rst_dly_i_m_1__n.BLIF N_35_0.BLIF as_030_000_sync_0_un0_n.BLIF N_138.BLIF N_16_i.BLIF ds_000_enable_0_un3_n.BLIF N_88.BLIF N_39_0.BLIF \ + ds_000_enable_0_un1_n.BLIF inst_BGACK_030_INTreg.BLIF N_256.BLIF N_13_i.BLIF ds_000_enable_0_un0_n.BLIF vcc_n_n.BLIF N_89.BLIF N_42_0.BLIF a0_dma_0_un3_n.BLIF \ + cpu_est_3_reg.BLIF N_91.BLIF N_12_i.BLIF a0_dma_0_un1_n.BLIF inst_VMA_INTreg.BLIF N_92.BLIF N_43_0.BLIF a0_dma_0_un0_n.BLIF inst_RESET_OUTreg.BLIF \ + pos_clk_a0_dma_3_n.BLIF N_8_i.BLIF size_dma_0_1__un3_n.BLIF gnd_n_n.BLIF N_96.BLIF N_46_0.BLIF size_dma_0_1__un1_n.BLIF un1_amiga_bus_enable_low.BLIF N_72.BLIF \ + N_76_i.BLIF size_dma_0_1__un0_n.BLIF un6_as_030.BLIF N_97.BLIF N_72_0.BLIF size_dma_0_0__un3_n.BLIF un3_size.BLIF N_116.BLIF UDS_000_c_i.BLIF \ + size_dma_0_0__un1_n.BLIF un4_size.BLIF N_104.BLIF LDS_000_c_i.BLIF size_dma_0_0__un0_n.BLIF un5_ciin.BLIF N_76.BLIF N_256_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ + un8_ciin.BLIF pos_clk_size_dma_6_1__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un4_as_000.BLIF pos_clk_size_dma_6_0__n.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF un1_SM_AMIGA_7.BLIF \ + N_250.BLIF N_104_i.BLIF cpu_est_0_1__un3_n.BLIF un21_fpu_cs.BLIF pos_clk_un6_bgack_000_n.BLIF N_252_0.BLIF cpu_est_0_1__un1_n.BLIF un22_berr.BLIF N_251.BLIF \ + N_251_0.BLIF cpu_est_0_1__un0_n.BLIF un6_ds_030.BLIF N_252.BLIF pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_2__un3_n.BLIF un6_uds_000.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_97_i.BLIF \ + cpu_est_0_2__un1_n.BLIF un6_lds_000.BLIF pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_96_i.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_0_.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_250_0.BLIF cpu_est_0_3__un3_n.BLIF \ + cpu_est_1_.BLIF un22_berr_1.BLIF N_89_i.BLIF cpu_est_0_3__un1_n.BLIF inst_AS_000_INT.BLIF N_8.BLIF pos_clk_size_dma_6_0_0__n.BLIF cpu_est_0_3__un0_n.BLIF SM_AMIGA_5_.BLIF \ + N_12.BLIF N_88_i.BLIF ipl_030_0_0__un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_13.BLIF pos_clk_size_dma_6_0_1__n.BLIF ipl_030_0_0__un1_n.BLIF inst_AS_030_D0.BLIF N_16.BLIF \ + N_138_0.BLIF ipl_030_0_0__un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_20.BLIF un1_rst_dly_i_m_i_1__n.BLIF ipl_030_0_1__un3_n.BLIF inst_DS_030_D0.BLIF N_21.BLIF ipl_030_0_1__un1_n.BLIF \ + inst_AS_030_000_SYNC.BLIF N_11.BLIF N_157_i.BLIF ipl_030_0_1__un0_n.BLIF inst_BGACK_030_INT_D.BLIF un1_amiga_bus_enable_low_i.BLIF N_158_i.BLIF ipl_030_0_2__un3_n.BLIF inst_AS_000_DMA.BLIF \ + un21_fpu_cs_i.BLIF N_159_i.BLIF ipl_030_0_2__un1_n.BLIF inst_DS_000_DMA.BLIF BGACK_030_INT_i.BLIF ipl_030_0_2__un0_n.BLIF CYCLE_DMA_0_.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_257_0.BLIF \ + dsack1_int_0_un3_n.BLIF CYCLE_DMA_1_.BLIF AS_030_i.BLIF un1_as_000_i.BLIF dsack1_int_0_un1_n.BLIF SIZE_DMA_0_.BLIF AS_000_INT_i.BLIF N_93_i.BLIF dsack1_int_0_un0_n.BLIF \ + SIZE_DMA_1_.BLIF N_105_i.BLIF as_000_int_0_un3_n.BLIF inst_VPA_D.BLIF N_91_i.BLIF N_87_i.BLIF as_000_int_0_un1_n.BLIF inst_UDS_000_INT.BLIF N_92_i.BLIF \ + N_86_i.BLIF as_000_int_0_un0_n.BLIF inst_LDS_000_INT.BLIF a_i_19__n.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF lds_000_int_0_un3_n.BLIF inst_CLK_OUT_PRE_D.BLIF a_i_18__n.BLIF un1_rst_dly_i_m_i_2__n.BLIF \ + lds_000_int_0_un1_n.BLIF inst_DTACK_D0.BLIF a_i_16__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF size_dma_i_1__n.BLIF un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un3_n.BLIF inst_CLK_000_D1.BLIF \ + size_dma_i_0__n.BLIF rw_000_int_0_un1_n.BLIF inst_CLK_000_D0.BLIF FPU_SENSE_i.BLIF un1_rst_dly_i_m_i_4__n.BLIF rw_000_int_0_un0_n.BLIF inst_CLK_000_PE.BLIF CLK_000_D1_i.BLIF uds_000_int_0_un3_n.BLIF \ + CLK_000_P_SYNC_9_.BLIF CLK_000_D0_i.BLIF un1_rst_dly_i_m_i_5__n.BLIF uds_000_int_0_un1_n.BLIF inst_CLK_000_NE.BLIF AS_030_000_SYNC_i.BLIF uds_000_int_0_un0_n.BLIF CLK_000_N_SYNC_11_.BLIF AS_030_D0_i.BLIF \ + un1_rst_dly_i_m_i_6__n.BLIF vma_int_0_un3_n.BLIF cpu_est_2_.BLIF sm_amiga_i_i_7__n.BLIF vma_int_0_un1_n.BLIF IPL_D0_0_.BLIF AS_000_i.BLIF un1_rst_dly_i_m_i_7__n.BLIF vma_int_0_un0_n.BLIF \ + IPL_D0_1_.BLIF CLK_000_PE_i.BLIF bg_000_0_un3_n.BLIF IPL_D0_2_.BLIF nEXP_SPACE_D0_i.BLIF un1_rst_dly_i_m_i_8__n.BLIF bg_000_0_un1_n.BLIF SM_AMIGA_3_.BLIF A1_i.BLIF \ + bg_000_0_un0_n.BLIF inst_CLK_000_NE_D0.BLIF sm_amiga_i_6__n.BLIF un3_as_030_i.BLIF ds_000_dma_0_un3_n.BLIF pos_clk_un6_bg_030_n.BLIF BERR_i.BLIF un1_as_030_i.BLIF ds_000_dma_0_un1_n.BLIF \ + SM_AMIGA_0_.BLIF sm_amiga_i_5__n.BLIF clk_000_n_sync_i_10__n.BLIF ds_000_dma_0_un0_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF RESET_OUT_0_sqmuxa_i.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF as_000_dma_0_un3_n.BLIF inst_DSACK1_INTreg.BLIF \ + un1_rst_dly_i_1__n.BLIF pos_clk_un14_clk_000_n_sync_0_n.BLIF as_000_dma_0_un1_n.BLIF RESET_OUT_i.BLIF CLK_EXP_c_i.BLIF as_000_dma_0_un0_n.BLIF pos_clk_clk_000_n_sync_2_0__n.BLIF RW_000_i.BLIF N_244_0.BLIF \ + a_15__n.BLIF pos_clk_ipl_n.BLIF un1_rst_dly_i_2__n.BLIF N_83_i.BLIF pos_clk_un3_ds_030_d0_n.BLIF un1_rst_dly_i_3__n.BLIF N_115_0.BLIF a_14__n.BLIF SM_AMIGA_6_.BLIF \ + un1_rst_dly_i_4__n.BLIF N_84_i.BLIF RST_DLY_0_.BLIF un1_rst_dly_i_5__n.BLIF N_245_0.BLIF a_13__n.BLIF RST_DLY_1_.BLIF un1_rst_dly_i_6__n.BLIF N_85_i.BLIF \ + RST_DLY_2_.BLIF un1_rst_dly_i_7__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF a_12__n.BLIF RST_DLY_3_.BLIF un1_rst_dly_i_8__n.BLIF N_94_i.BLIF RST_DLY_4_.BLIF CLK_OUT_PRE_D_i.BLIF \ + a_11__n.BLIF RST_DLY_5_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF RST_DLY_6_.BLIF CLK_030_H_i.BLIF a_10__n.BLIF RST_DLY_7_.BLIF AS_000_DMA_i.BLIF N_73_0.BLIF \ + pos_clk_un8_bg_030_n.BLIF VMA_INT_i.BLIF a_9__n.BLIF CLK_000_P_SYNC_0_.BLIF VPA_D_i.BLIF N_160_i.BLIF CLK_000_P_SYNC_1_.BLIF cpu_est_i_0__n.BLIF N_161_i.BLIF \ + a_8__n.BLIF CLK_000_P_SYNC_2_.BLIF cpu_est_i_1__n.BLIF CLK_000_P_SYNC_3_.BLIF cpu_est_i_3__n.BLIF N_155_i.BLIF a_7__n.BLIF CLK_000_P_SYNC_4_.BLIF a_i_24__n.BLIF \ + N_156_i.BLIF CLK_000_P_SYNC_5_.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF a_6__n.BLIF CLK_000_P_SYNC_6_.BLIF sm_amiga_i_0__n.BLIF N_154_i.BLIF CLK_000_P_SYNC_7_.BLIF sm_amiga_i_3__n.BLIF \ + N_152_i.BLIF a_5__n.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_NE_i.BLIF N_153_i.BLIF CLK_000_N_SYNC_0_.BLIF cpu_est_i_2__n.BLIF a_4__n.BLIF CLK_000_N_SYNC_1_.BLIF \ + sm_amiga_i_1__n.BLIF N_150_i.BLIF CLK_000_N_SYNC_2_.BLIF sm_amiga_i_4__n.BLIF N_151_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_3_.BLIF sm_amiga_i_2__n.BLIF CLK_000_N_SYNC_4_.BLIF \ + pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_149_i.BLIF a_2__n.BLIF CLK_000_N_SYNC_5_.BLIF DSACK1_INT_0_sqmuxa_i.BLIF N_147_i.BLIF CLK_000_N_SYNC_6_.BLIF RW_i.BLIF N_148_i.BLIF \ + CLK_000_N_SYNC_7_.BLIF un5_ciin_i.BLIF CLK_000_N_SYNC_8_.BLIF DTACK_D0_i.BLIF N_164_i.BLIF CLK_000_N_SYNC_9_.BLIF a_i_31__n.BLIF N_165_i.BLIF CLK_000_N_SYNC_10_.BLIF \ + a_i_29__n.BLIF N_163_i.BLIF inst_RW_000_INT.BLIF a_i_30__n.BLIF N_199_i.BLIF inst_RW_000_DMA.BLIF a_i_27__n.BLIF pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF \ + a_i_28__n.BLIF N_197_i.BLIF inst_A0_DMA.BLIF a_i_25__n.BLIF N_198_i.BLIF DS_000_ENABLE_1_sqmuxa.BLIF a_i_26__n.BLIF N_194_i.BLIF inst_CLK_030_H.BLIF \ + UDS_000_INT_i.BLIF pos_clk_cpu_est_11_0_1__n.BLIF SM_AMIGA_1_.BLIF LDS_000_INT_i.BLIF N_192_i.BLIF SM_AMIGA_4_.BLIF DS_030_i.BLIF N_135_i.BLIF SM_AMIGA_2_.BLIF \ + N_224_i.BLIF N_162_i.BLIF inst_DS_000_ENABLE.BLIF N_225_i.BLIF N_191_i.BLIF AS_000_INT_1_sqmuxa.BLIF N_226_i.BLIF N_193_i.BLIF DSACK1_INT_1_sqmuxa.BLIF \ + N_190_i.BLIF pos_clk_ds_000_dma_4_n.BLIF N_189_i.BLIF N_3.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF N_188_i.BLIF un6_lds_000_i.BLIF N_195_i.BLIF un6_uds_000_i.BLIF \ + N_196_i.BLIF N_6.BLIF un6_ds_030_i.BLIF N_186_i.BLIF N_9.BLIF DS_000_DMA_i.BLIF N_143_0.BLIF N_10.BLIF un4_as_000_i.BLIF \ + N_142_0.BLIF N_14.BLIF un8_ciin_i.BLIF N_141_0.BLIF N_15.BLIF un6_as_030_i.BLIF N_140_0.BLIF N_17.BLIF DS_030_D0_i.BLIF \ + N_139_0.BLIF N_19.BLIF AS_030_c.BLIF N_166_i.BLIF N_22.BLIF N_137_i.BLIF N_23.BLIF AS_000_c.BLIF N_136_i.BLIF \ + N_24.BLIF N_133_i.BLIF N_25.BLIF RW_000_c.BLIF N_132_i.BLIF cpu_est_0_0_.BLIF N_146_i.BLIF DS_030_c.BLIF N_144_i.BLIF \ + UDS_000_c.BLIF un1_SM_AMIGA_7_i.BLIF pos_clk_un21_clk_000_ne_d0_i_n.BLIF LDS_000_c.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF pos_clk_un23_clk_000_ne_d0_0_n.BLIF size_c_0__n.BLIF pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ + size_c_1__n.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF size_c_i_1__n.BLIF N_25_i.BLIF N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF \ + N_23_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF ipl_c_i_0__n.BLIF N_52_0.BLIF DTACK_c_i.BLIF \ + N_57_0.BLIF VPA_c_i.BLIF N_56_0.BLIF nEXP_SPACE_c_i.BLIF SM_AMIGA_i_7_.BLIF N_55_0.BLIF N_115.BLIF N_50_0.BLIF pos_clk_cpu_est_11_1__n.BLIF \ + N_3_i.BLIF pos_clk_cpu_est_11_3__n.BLIF N_49_0.BLIF N_220.BLIF N_6_i.BLIF G_165.BLIF N_48_0.BLIF G_166.BLIF N_9_i.BLIF \ + G_167.BLIF N_45_0.BLIF un6_uds_000_1.BLIF N_10_i.BLIF pos_clk_un24_bgack_030_int_i_0_n.BLIF a_c_16__n.BLIF N_44_0.BLIF N_244.BLIF N_14_i.BLIF \ + N_245.BLIF a_c_17__n.BLIF N_41_0.BLIF N_15_i.BLIF N_80.BLIF a_c_18__n.BLIF N_40_0.BLIF N_90.BLIF N_17_i.BLIF \ + N_100.BLIF a_c_19__n.BLIF N_38_0.BLIF N_105.BLIF N_19_i.BLIF pos_clk_un11_clk_000_n_sync_n.BLIF a_c_20__n.BLIF N_36_0.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ + N_22_i.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF a_c_21__n.BLIF N_33_0.BLIF N_135.BLIF BG_030_c_i.BLIF N_133.BLIF a_c_22__n.BLIF pos_clk_un6_bg_030_i_n.BLIF \ + N_190.BLIF pos_clk_un8_bg_030_0_n.BLIF N_188.BLIF a_c_23__n.BLIF N_127_i_1.BLIF N_189.BLIF N_127_i_2.BLIF N_136.BLIF a_c_24__n.BLIF \ + pos_clk_un11_ds_030_d0_i_1_n.BLIF pos_clk_un7_clk_000_d0_n.BLIF N_135_i_1.BLIF pos_clk_un29_clk_000_ne_d0_n.BLIF a_c_25__n.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF DSACK1_INT_0_sqmuxa.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_un21_clk_000_ne_d0_n.BLIF \ + a_c_26__n.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF pos_clk_un5_clk_000_pe_n.BLIF N_195_1.BLIF pos_clk_un9_clk_000_ne_n.BLIF a_c_27__n.BLIF N_196_1.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF N_131_i_1.BLIF \ + pos_clk_un27_clk_000_ne_d0_n.BLIF a_c_28__n.BLIF N_131_i_2.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_131_i_3.BLIF N_144.BLIF a_c_29__n.BLIF N_119_i_1.BLIF N_146.BLIF \ + N_119_i_2.BLIF N_143.BLIF a_c_30__n.BLIF N_121_i_1.BLIF N_147.BLIF N_123_i_1.BLIF N_139.BLIF a_c_31__n.BLIF N_123_i_2.BLIF \ + N_148.BLIF N_125_i_1.BLIF N_149.BLIF A0_c.BLIF N_129_i_1.BLIF N_150.BLIF N_162_1.BLIF N_140.BLIF A1_c.BLIF \ + N_163_1.BLIF N_151.BLIF N_165_1.BLIF N_152.BLIF nEXP_SPACE_c.BLIF N_165_2.BLIF N_153.BLIF N_165_3.BLIF N_154.BLIF \ + BERR_c.BLIF un5_ciin_1.BLIF N_155.BLIF un5_ciin_2.BLIF N_141.BLIF BG_030_c.BLIF un5_ciin_3.BLIF N_156.BLIF un5_ciin_4.BLIF \ + N_160.BLIF BG_000DFFreg.BLIF un5_ciin_5.BLIF N_142.BLIF un5_ciin_6.BLIF N_161.BLIF un5_ciin_7.BLIF N_164.BLIF BGACK_000_c.BLIF \ + un5_ciin_8.BLIF N_166.BLIF un5_ciin_9.BLIF N_132.BLIF un5_ciin_10.BLIF N_191.BLIF un5_ciin_11.BLIF N_192.BLIF pos_clk_un9_clk_000_ne_1_n.BLIF \ + N_193.BLIF CLK_OSZI_c.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF N_194.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF N_197.BLIF pos_clk_un9_clk_000_ne_4_n.BLIF N_198.BLIF CLK_EXP_c.BLIF \ + pos_clk_un5_clk_000_pe_1_n.BLIF N_195.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF N_196.BLIF pos_clk_un5_clk_000_pe_3_n.BLIF N_162.BLIF FPU_SENSE_c.BLIF pos_clk_un27_clk_000_ne_d0_1_n.BLIF N_199.BLIF \ + pos_clk_un27_clk_000_ne_d0_2_n.BLIF N_199_1.BLIF IPL_030DFF_0_reg.BLIF pos_clk_un27_clk_000_ne_d0_3_n.BLIF N_163.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_165.BLIF IPL_030DFF_1_reg.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ + N_73.BLIF RESET_OUT_0_sqmuxa_7_3.BLIF N_94.BLIF IPL_030DFF_2_reg.BLIF RESET_OUT_0_sqmuxa_5_1.BLIF N_85.BLIF N_87_1.BLIF N_84.BLIF ipl_c_0__n.BLIF \ + N_87_2.BLIF N_83.BLIF pos_clk_un24_bgack_030_int_i_0_0_1_n.BLIF pos_clk_un9_clk_000_n_sync_n.BLIF ipl_c_1__n.BLIF pos_clk_un24_bgack_030_int_i_0_0_2_n.BLIF G_149.BLIF N_72_0_1.BLIF G_147.BLIF \ + ipl_c_2__n.BLIF pos_clk_un7_clk_000_d0_1_n.BLIF N_213.BLIF un21_fpu_cs_1.BLIF G_145.BLIF un22_berr_1_0.BLIF N_211.BLIF DTACK_c.BLIF N_116_1.BLIF \ + G_143.BLIF N_116_2.BLIF N_209.BLIF N_116_3.BLIF G_141.BLIF N_116_4.BLIF G_139.BLIF VPA_c.BLIF pos_clk_un6_bg_030_1_n.BLIF \ + N_205.BLIF N_115_0_1.BLIF G_137.BLIF N_245_0_1.BLIF RESET_OUT_0_sqmuxa_1.BLIF RST_c.BLIF N_247_i_1.BLIF RESET_OUT_0_sqmuxa.BLIF N_248_i_1.BLIF \ + RESET_OUT_0_sqmuxa_7.BLIF N_249_i_1.BLIF RESET_OUT_0_sqmuxa_5.BLIF RW_c.BLIF pos_clk_ipl_1_n.BLIF un1_rst_dly_i_m_8__n.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF un1_rst_dly_i_m_7__n.BLIF fc_c_0__n.BLIF \ + amiga_bus_enable_dma_high_0_un1_n.BLIF un1_rst_dly_i_m_6__n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF un1_rst_dly_i_m_5__n.BLIF fc_c_1__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF un1_rst_dly_i_m_4__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF un1_rst_dly_i_m_3__n.BLIF \ + amiga_bus_enable_dma_low_0_un0_n.BLIF un1_rst_dly_i_m_2__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF rw_000_dma_0_un3_n.BLIF N_86.BLIF rw_000_dma_0_un1_n.BLIF N_93.BLIF rw_000_dma_0_un0_n.BLIF N_87.BLIF \ + bgack_030_int_0_un3_n.BLIF G_135.BLIF bgack_030_int_0_un1_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN \ + SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA RESET \ - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C \ - SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ - SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ - IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C RST_DLY_0_.D \ - RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C \ - RST_DLY_6_.D RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ - SIZE_DMA_1_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ - CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ - CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C \ - CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ - CLK_000_P_SYNC_7_.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_A0_DMA.D inst_A0_DMA.C \ - inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D \ - inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ - BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_RW_000_DMA.D \ - inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ - inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C G_159.X1 G_159.X2 cpu_est_0_0_.X1 \ - cpu_est_0_0_.X2 pos_clk_RST_DLY_5_iv_0_x2_0_.X1 pos_clk_RST_DLY_5_iv_0_x2_0_.X2 G_137.X1 G_137.X2 G_149.X1 G_149.X2 G_147.X1 G_147.X2 G_145.X1 G_145.X2 \ - G_143.X1 G_143.X2 G_141.X1 G_141.X2 G_139.X1 G_139.X2 G_167.X1 G_167.X2 G_165.X1 G_165.X2 G_166.X1 \ - G_166.X2 G_161.X1 G_161.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_193 cpu_est_0_1__un3_n N_190 RW_c cpu_est_0_1__un1_n N_189 cpu_est_0_1__un0_n N_140 \ - fc_c_0__n bgack_030_int_0_un3_n pos_clk_un29_clk_000_ne_d0_n bgack_030_int_0_un1_n pos_clk_un23_clk_000_ne_d0_n fc_c_1__n bgack_030_int_0_un0_n pos_clk_un21_clk_000_ne_d0_n un1_amiga_bus_enable_dma_high_i_m4_0__un3_n vcc_n_n pos_clk_un7_clk_000_pe_n \ - un1_amiga_bus_enable_dma_high_i_m4_0__un1_n N_18 AMIGA_BUS_DATA_DIR_c un1_amiga_bus_enable_dma_high_i_m4_0__un0_n N_22 ds_000_enable_1_sqmuxa_1_i_m4_un3_n pos_clk_un11_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un1_n gnd_n_n pos_clk_un9_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un0_n \ - un1_amiga_bus_enable_low pos_clk_un14_clk_000_n_sync_n size_dma_0_0__un3_n un6_as_030 pos_clk_un22_bgack_030_int_n N_6_i size_dma_0_0__un1_n un3_size N_48_0 size_dma_0_0__un0_n un4_size \ - N_220 N_3_i size_dma_0_1__un3_n un8_ciin N_49_0 size_dma_0_1__un1_n un14_amiga_bus_data_dir pos_clk_un40_bgack_030_int_1_n pos_clk_un29_bgack_030_int_i_n size_dma_0_1__un0_n un4_as_000 \ - CLK_030_H_0_sqmuxa pos_clk_un26_bgack_030_int_i_n ipl_030_0_0__un3_n un21_fpu_cs AS_000_DMA_1_sqmuxa pos_clk_un27_bgack_030_int_0_n ipl_030_0_0__un1_n un22_berr pos_clk_un24_bgack_030_int_n CLK_030_H_0_sqmuxa_i ipl_030_0_0__un0_n \ - un6_ds_030 pos_clk_un27_bgack_030_int_n N_7_i ipl_030_0_1__un3_n un6_uds_000 N_176_1 N_47_0 ipl_030_0_1__un1_n un6_lds_000 N_165 N_133_i \ - ipl_030_0_1__un0_n N_133 N_176_i ipl_030_0_2__un3_n N_163 N_175_i ipl_030_0_2__un1_n N_162 AMIGA_BUS_DATA_DIR_c_0 ipl_030_0_2__un0_n N_164 \ - pos_clk_ds_000_dma_4_f1_0_n dsack1_int_0_un3_n N_176 N_162_i dsack1_int_0_un1_n DS_000_DMA_2_sqmuxa N_163_i dsack1_int_0_un0_n pos_clk_ds_000_dma_4_n N_164_i as_000_int_0_un3_n \ - DS_000_DMA_0_sqmuxa N_165_i as_000_int_0_un1_n pos_clk_ds_000_dma_4_f1_n as_000_int_0_un0_n N_175 pos_clk_un22_bgack_030_int_0_n ds_000_enable_0_un3_n N_47 pos_clk_un9_clk_000_n_sync_i_n ds_000_enable_0_un1_n \ - N_7 clk_000_n_sync_i_10__n ds_000_enable_0_un0_n un1_rst_2 pos_clk_un14_clk_000_n_sync_0_n as_030_000_sync_0_un3_n pos_clk_un26_bgack_030_int_n N_22_i as_030_000_sync_0_un1_n pos_clk_un29_bgack_030_int_n N_33_0 \ - as_030_000_sync_0_un0_n N_3 N_18_i lds_000_int_0_un3_n N_6 N_37_0 lds_000_int_0_un1_n un1_amiga_bus_enable_low_i pos_clk_un9_clk_000_ne_i_n lds_000_int_0_un0_n un21_fpu_cs_i \ - pos_clk_un5_clk_000_pe_i_n rw_000_int_0_un3_n AS_000_i pos_clk_un7_clk_000_pe_0_n rw_000_int_0_un1_n DS_000_DMA_i pos_clk_un27_clk_000_ne_d0_i_n rw_000_int_0_un0_n pos_clk_un24_bgack_030_int_i_n pos_clk_un21_clk_000_ne_d0_i_n rw_000_dma_0_un3_n \ - cycle_dma_i_1__n pos_clk_un23_clk_000_ne_d0_0_n rw_000_dma_0_un1_n cycle_dma_i_0__n N_136_i rw_000_dma_0_un0_n AS_000_DMA_i N_140_0 uds_000_int_0_un3_n CLK_EXP_i N_195_i \ - uds_000_int_0_un1_n BERR_i N_196_i uds_000_int_0_un0_n RW_000_i N_186_i amiga_bus_enable_dma_low_0_un3_n DS_000_DMA_0_sqmuxa_i N_188_i amiga_bus_enable_dma_low_0_un1_n pos_clk_un40_bgack_030_int_1_i_n \ - N_189_i amiga_bus_enable_dma_low_0_un0_n BGACK_030_INT_i N_190_i amiga_bus_enable_dma_high_0_un3_n nEXP_SPACE_D0_i N_193_i amiga_bus_enable_dma_high_0_un1_n CLK_000_PE_i N_191_i amiga_bus_enable_dma_high_0_un0_n \ - CLK_000_NE_i N_192_i bg_000_0_un3_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_194_i bg_000_0_un1_n sm_amiga_i_0__n pos_clk_cpu_est_11_0_1__n bg_000_0_un0_n pos_clk_un7_clk_000_d0_i_n \ - N_198_i a0_dma_0_un3_n UDS_000_i N_197_i a0_dma_0_un1_n LDS_000_i N_199_i a0_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n pos_clk_un11_clk_000_n_sync_i_n pos_clk_cpu_est_11_0_3__n \ - a_23__n pos_clk_ipl_n CLK_OUT_PRE_D_i N_151_i pos_clk_un3_ds_030_d0_n DTACK_D0_i N_150_i a_22__n sm_amiga_i_2__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa pos_clk_un29_clk_000_ne_d0_i_n \ - N_135_i a_21__n cpu_est_i_0__n N_252_0 cpu_est_i_3__n N_85_i a_20__n cpu_est_i_2__n cpu_est_i_1__n N_38_0 a_15__n \ - VPA_D_i un1_rst_dly_i_m_i_2__n VMA_INT_i a_14__n sm_amiga_i_1__n un1_rst_dly_i_m_i_3__n RESET_OUT_0_sqmuxa_i a_13__n pos_clk_un8_bg_030_n N_77_i_i un1_rst_dly_i_m_i_4__n \ - un1_rst_dly_i_2__n a_12__n un1_rst_dly_i_3__n un1_rst_dly_i_m_i_5__n un1_rst_dly_i_4__n a_11__n un1_rst_dly_i_5__n un1_rst_dly_i_m_i_6__n un1_rst_dly_i_6__n a_10__n un1_rst_dly_i_7__n \ - un1_rst_dly_i_m_i_7__n un1_rst_dly_i_8__n a_9__n RESET_OUT_i un1_rst_dly_i_m_i_8__n AS_030_D0_i a_8__n AS_030_i un3_as_030_i A1_i N_76_i \ - a_7__n CLK_000_D1_i N_83_i sm_amiga_i_i_7__n a_6__n N_248_i N_84_i sm_amiga_i_5__n N_115_0 a_5__n RW_i \ - N_86_i CLK_000_D0_i pos_clk_size_dma_6_0_1__n a_4__n AS_030_000_SYNC_i N_87_i sm_amiga_i_6__n pos_clk_size_dma_6_0_0__n a_3__n sm_amiga_i_4__n N_88_i \ - pos_clk_un5_bgack_030_int_d_n FPU_SENSE_i a_2__n size_dma_i_0__n N_241_0 size_dma_i_1__n N_242_0 a_i_16__n N_243_0 a_i_18__n N_93_i \ - a_i_19__n N_94_i a_i_30__n N_244_0 a_i_31__n N_245_0 pos_clk_un3_as_030_d0_n a_i_28__n N_246_0 a_i_29__n pos_clk_un3_as_030_d0_i_n \ - a_i_26__n pos_clk_un5_bgack_030_int_d_i_n a_i_27__n N_249_i pos_clk_a0_dma_3_n a_i_24__n N_251_0 a_i_25__n N_71_0 LDS_000_INT_i N_104_i \ - N_8 DS_030_i N_137_i N_9 UDS_000_INT_i N_10 N_224_i N_160_i N_11 N_225_i N_161_i \ - N_12 N_226_i N_13 N_159_i N_14 N_157_i N_15 N_158_i N_16 N_91_i N_19 \ - N_90_i N_155_i N_20 un14_amiga_bus_data_dir_i N_156_i N_21 N_80_i N_23 un6_lds_000_i N_154_i N_24 \ - un6_uds_000_i N_152_i N_25 un6_ds_030_i N_153_i un4_as_000_i N_142_0 AS_000_INT_i N_141_0 un6_as_030_i N_138_0 \ - AMIGA_BUS_ENABLE_DMA_LOW_i N_132_i DS_030_D0_i un1_as_030_i AS_030_c pos_clk_un11_ds_030_d0_i_n A0_c_i AS_000_c size_c_i_1__n N_25_i RW_000_c \ - N_32_0 N_24_i DS_030_c N_31_0 N_23_i UDS_000_c N_30_0 ipl_c_i_2__n LDS_000_c N_54_0 ipl_c_i_1__n \ - size_c_0__n N_53_0 ipl_c_i_0__n size_c_1__n N_52_0 DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 \ - N_50_0 N_8_i N_46_0 N_9_i N_45_0 N_10_i N_44_0 N_115 N_12_i pos_clk_size_dma_6_0__n N_43_0 \ - pos_clk_size_dma_6_1__n N_13_i N_42_0 N_14_i N_41_0 un6_uds_000_1 N_15_i N_241 N_40_0 N_242 N_16_i \ - N_243 N_39_0 N_244 N_19_i N_245 N_36_0 N_246 N_20_i N_78 N_35_0 N_80 \ - N_21_i N_89 N_34_0 N_90 a_c_16__n BG_030_c_i N_91 pos_clk_un6_bg_030_i_n N_98 a_c_17__n pos_clk_un8_bg_030_0_n \ - N_99 N_251_0_1 N_249 a_c_18__n N_121_i_1 N_248 pos_clk_cpu_est_11_0_1_3__n N_135 a_c_19__n pos_clk_cpu_est_11_0_1_1__n N_136 \ - pos_clk_cpu_est_11_0_2_1__n pos_clk_un7_clk_000_d0_n N_131_i_1 un22_berr_1 N_131_i_2 N_152 N_131_i_3 N_153 pos_clk_un11_ds_030_d0_i_1_n N_154 un8_ciin_1 \ - N_155 un8_ciin_2 N_141 un8_ciin_3 N_156 un8_ciin_4 N_157 a_c_24__n un8_ciin_5 N_138 un8_ciin_6 \ - N_158 a_c_25__n un8_ciin_7 N_159 un8_ciin_8 N_160 a_c_26__n N_116_1 N_142 N_116_2 N_161 \ - a_c_27__n N_116_3 N_132 N_116_4 N_104 a_c_28__n un22_berr_1_0 N_76 un21_fpu_cs_1 N_71 a_c_29__n \ - N_123_i_1 N_251 N_123_i_2 N_93 a_c_30__n N_125_i_1 N_94 N_127_i_1 N_88 a_c_31__n N_127_i_2 \ - N_87 N_129_i_1 N_86 A0_c pos_clk_un6_bg_030_1_n N_84 pos_clk_un7_clk_000_d0_1_n N_83 A1_c RESET_OUT_0_sqmuxa_7_1 N_116 \ - RESET_OUT_0_sqmuxa_7_2 nEXP_SPACE_c RESET_OUT_0_sqmuxa_7_3 RESET_OUT_0_sqmuxa_5_1 N_213 BERR_c N_135_i_1 pos_clk_un27_clk_000_ne_d0_1_n N_211 BG_030_c pos_clk_un27_clk_000_ne_d0_2_n \ - pos_clk_un27_clk_000_ne_d0_3_n N_209 pos_clk_un5_clk_000_pe_1_n pos_clk_un5_clk_000_pe_2_n pos_clk_un5_clk_000_pe_3_n N_205 BGACK_000_c pos_clk_un9_clk_000_ne_1_n pos_clk_un9_clk_000_ne_2_n RESET_OUT_0_sqmuxa_1 pos_clk_un9_clk_000_ne_3_n \ - RESET_OUT_0_sqmuxa pos_clk_un9_clk_000_ne_4_n RESET_OUT_0_sqmuxa_7 N_196_1 RESET_OUT_0_sqmuxa_5 CLK_OSZI_c N_195_1 un1_rst_dly_i_m_8__n pos_clk_un24_bgack_030_int_1_n un1_rst_dly_i_m_7__n N_165_1 \ - un1_rst_dly_i_m_6__n CLK_EXP_c N_165_2 un1_rst_dly_i_m_5__n N_165_3 un1_rst_dly_i_m_4__n N_163_1 un1_rst_dly_i_m_3__n FPU_SENSE_c N_162_1 un1_rst_dly_i_m_2__n \ - N_176_1_0 N_38 DS_000_DMA_2_sqmuxa_1 N_85 N_119_i_1 N_115_0_1 N_252 pos_clk_ipl_1_n N_97 as_000_dma_0_un3_n pos_clk_un27_clk_000_ne_d0_n \ - as_000_dma_0_un1_n N_199_1 ipl_c_0__n as_000_dma_0_un0_n pos_clk_un5_clk_000_pe_n ds_000_dma_0_un3_n pos_clk_un9_clk_000_ne_n ipl_c_1__n ds_000_dma_0_un1_n N_150 ds_000_dma_0_un0_n \ - N_151 ipl_c_2__n vma_int_0_un3_n N_199 vma_int_0_un1_n N_196 vma_int_0_un0_n N_195 DTACK_c sm_amiga_srsts_i_0_m2_1__un3_n N_188 \ - sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_cpu_est_11_3__n sm_amiga_srsts_i_0_m2_1__un0_n N_197 cpu_est_0_3__un3_n N_198 VPA_c cpu_est_0_3__un1_n pos_clk_cpu_est_11_1__n cpu_est_0_3__un0_n N_194 \ - cpu_est_0_2__un3_n N_192 RST_c cpu_est_0_2__un1_n N_191 cpu_est_0_2__un0_n AS_030.OE AS_000.OE RW_000.OE \ - DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \ - DSACK1.OE CIIN.OE + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C \ + IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D \ + SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C \ + cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C CLK_000_N_SYNC_9_.D \ + CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ + RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D \ + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C \ + CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ + CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ + CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ + CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ + inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_A0_DMA.D \ + inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C \ + inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D \ + inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ + inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C pos_clk_un24_bgack_030_int_i_0_x2.X1 pos_clk_un24_bgack_030_int_i_0_x2.X2 G_135.X1 \ + G_135.X2 G_149.X1 G_149.X2 G_147.X1 G_147.X2 G_145.X1 G_145.X2 G_143.X1 G_143.X2 G_141.X1 G_141.X2 \ + G_139.X1 G_139.X2 G_137.X1 G_137.X2 cpu_est_0_0_.X1 cpu_est_0_0_.X2 pos_clk_CYCLE_DMA_5_0_i_x2.X1 pos_clk_CYCLE_DMA_5_0_i_x2.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 G_165.X1 \ + G_165.X2 G_166.X1 G_166.X2 G_167.X1 G_167.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_159 N_21_i bgack_030_int_0_un0_n N_157 N_34_0 as_030_000_sync_0_un3_n \ + N_158 N_20_i as_030_000_sync_0_un1_n un1_rst_dly_i_m_1__n N_35_0 as_030_000_sync_0_un0_n N_138 N_16_i ds_000_enable_0_un3_n N_88 N_39_0 \ + ds_000_enable_0_un1_n N_256 N_13_i ds_000_enable_0_un0_n vcc_n_n N_89 N_42_0 a0_dma_0_un3_n N_91 N_12_i a0_dma_0_un1_n \ + N_92 N_43_0 a0_dma_0_un0_n pos_clk_a0_dma_3_n N_8_i size_dma_0_1__un3_n gnd_n_n N_96 N_46_0 size_dma_0_1__un1_n un1_amiga_bus_enable_low \ + N_72 N_76_i size_dma_0_1__un0_n un6_as_030 N_97 N_72_0 size_dma_0_0__un3_n un3_size N_116 UDS_000_c_i size_dma_0_0__un1_n \ + un4_size N_104 LDS_000_c_i size_dma_0_0__un0_n un5_ciin N_76 N_256_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un8_ciin pos_clk_size_dma_6_1__n pos_clk_un5_bgack_030_int_d_i_n \ + un1_amiga_bus_enable_dma_high_i_m2_0__un1_n un4_as_000 pos_clk_size_dma_6_0__n pos_clk_un24_bgack_030_int_i_0_0_n un1_amiga_bus_enable_dma_high_i_m2_0__un0_n un1_SM_AMIGA_7 N_250 N_104_i cpu_est_0_1__un3_n un21_fpu_cs pos_clk_un6_bgack_000_n \ + N_252_0 cpu_est_0_1__un1_n un22_berr N_251 N_251_0 cpu_est_0_1__un0_n un6_ds_030 N_252 pos_clk_un6_bgack_000_0_n cpu_est_0_2__un3_n un6_uds_000 \ + pos_clk_un5_bgack_030_int_d_n N_97_i cpu_est_0_2__un1_n un6_lds_000 N_96_i cpu_est_0_2__un0_n DS_000_ENABLE_1_sqmuxa_1 N_250_0 cpu_est_0_3__un3_n un22_berr_1 N_89_i \ + cpu_est_0_3__un1_n N_8 pos_clk_size_dma_6_0_0__n cpu_est_0_3__un0_n N_12 N_88_i ipl_030_0_0__un3_n N_13 pos_clk_size_dma_6_0_1__n ipl_030_0_0__un1_n N_16 \ + N_138_0 ipl_030_0_0__un0_n N_20 un1_rst_dly_i_m_i_1__n ipl_030_0_1__un3_n N_21 ipl_030_0_1__un1_n N_11 N_157_i ipl_030_0_1__un0_n un1_amiga_bus_enable_low_i \ + N_158_i ipl_030_0_2__un3_n un21_fpu_cs_i N_159_i ipl_030_0_2__un1_n BGACK_030_INT_i ipl_030_0_2__un0_n AMIGA_BUS_ENABLE_DMA_LOW_i N_257_0 dsack1_int_0_un3_n AS_030_i \ + un1_as_000_i dsack1_int_0_un1_n AS_000_INT_i N_93_i dsack1_int_0_un0_n N_105_i as_000_int_0_un3_n N_91_i N_87_i as_000_int_0_un1_n N_92_i \ + N_86_i as_000_int_0_un0_n a_i_19__n AMIGA_BUS_DATA_DIR_c_0 lds_000_int_0_un3_n a_i_18__n un1_rst_dly_i_m_i_2__n lds_000_int_0_un1_n a_i_16__n lds_000_int_0_un0_n size_dma_i_1__n \ + un1_rst_dly_i_m_i_3__n rw_000_int_0_un3_n size_dma_i_0__n rw_000_int_0_un1_n FPU_SENSE_i un1_rst_dly_i_m_i_4__n rw_000_int_0_un0_n CLK_000_D1_i uds_000_int_0_un3_n CLK_000_D0_i un1_rst_dly_i_m_i_5__n \ + uds_000_int_0_un1_n AS_030_000_SYNC_i uds_000_int_0_un0_n AS_030_D0_i un1_rst_dly_i_m_i_6__n vma_int_0_un3_n sm_amiga_i_i_7__n vma_int_0_un1_n AS_000_i un1_rst_dly_i_m_i_7__n vma_int_0_un0_n \ + CLK_000_PE_i bg_000_0_un3_n nEXP_SPACE_D0_i un1_rst_dly_i_m_i_8__n bg_000_0_un1_n A1_i bg_000_0_un0_n sm_amiga_i_6__n un3_as_030_i ds_000_dma_0_un3_n pos_clk_un6_bg_030_n \ + BERR_i un1_as_030_i ds_000_dma_0_un1_n sm_amiga_i_5__n clk_000_n_sync_i_10__n ds_000_dma_0_un0_n RESET_OUT_0_sqmuxa_i pos_clk_un9_clk_000_n_sync_i_n as_000_dma_0_un3_n un1_rst_dly_i_1__n pos_clk_un14_clk_000_n_sync_0_n \ + as_000_dma_0_un1_n RESET_OUT_i CLK_EXP_c_i as_000_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n RW_000_i N_244_0 a_15__n pos_clk_ipl_n un1_rst_dly_i_2__n N_83_i \ + pos_clk_un3_ds_030_d0_n un1_rst_dly_i_3__n N_115_0 a_14__n un1_rst_dly_i_4__n N_84_i un1_rst_dly_i_5__n N_245_0 a_13__n un1_rst_dly_i_6__n N_85_i \ + un1_rst_dly_i_7__n pos_clk_ds_000_dma_4_0_n a_12__n un1_rst_dly_i_8__n N_94_i CLK_OUT_PRE_D_i a_11__n pos_clk_un11_clk_000_n_sync_i_n CLK_030_H_i a_10__n AS_000_DMA_i \ + N_73_0 pos_clk_un8_bg_030_n VMA_INT_i a_9__n VPA_D_i N_160_i cpu_est_i_0__n N_161_i a_8__n cpu_est_i_1__n cpu_est_i_3__n \ + N_155_i a_7__n a_i_24__n N_156_i pos_clk_un7_clk_000_d0_i_n a_6__n sm_amiga_i_0__n N_154_i sm_amiga_i_3__n N_152_i a_5__n \ + CLK_000_NE_i N_153_i cpu_est_i_2__n a_4__n sm_amiga_i_1__n N_150_i sm_amiga_i_4__n N_151_i a_3__n sm_amiga_i_2__n pos_clk_un29_clk_000_ne_d0_i_n \ + N_149_i a_2__n DSACK1_INT_0_sqmuxa_i N_147_i RW_i N_148_i un5_ciin_i DTACK_D0_i N_164_i a_i_31__n N_165_i \ + a_i_29__n N_163_i a_i_30__n N_199_i a_i_27__n pos_clk_cpu_est_11_0_3__n pos_clk_un7_clk_000_pe_n a_i_28__n N_197_i a_i_25__n N_198_i \ + DS_000_ENABLE_1_sqmuxa a_i_26__n N_194_i UDS_000_INT_i pos_clk_cpu_est_11_0_1__n LDS_000_INT_i N_192_i DS_030_i N_135_i N_224_i N_162_i \ + N_225_i N_191_i AS_000_INT_1_sqmuxa N_226_i N_193_i DSACK1_INT_1_sqmuxa N_190_i pos_clk_ds_000_dma_4_n N_189_i N_3 DS_000_ENABLE_1_sqmuxa_i \ + N_188_i un6_lds_000_i N_195_i un6_uds_000_i N_196_i N_6 un6_ds_030_i N_186_i N_9 DS_000_DMA_i N_143_0 \ + N_10 un4_as_000_i N_142_0 N_14 un8_ciin_i N_141_0 N_15 un6_as_030_i N_140_0 N_17 DS_030_D0_i \ + N_139_0 N_19 AS_030_c N_166_i N_22 N_137_i N_23 AS_000_c N_136_i N_24 N_133_i \ + N_25 RW_000_c N_132_i N_146_i DS_030_c N_144_i UDS_000_c un1_SM_AMIGA_7_i pos_clk_un21_clk_000_ne_d0_i_n LDS_000_c pos_clk_un27_clk_000_ne_d0_i_n \ + pos_clk_un23_clk_000_ne_d0_0_n size_c_0__n pos_clk_un5_clk_000_pe_i_n pos_clk_un9_clk_000_ne_i_n size_c_1__n pos_clk_un7_clk_000_pe_0_n pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 \ + N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 DTACK_c_i \ + N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_115 N_50_0 pos_clk_cpu_est_11_1__n N_3_i pos_clk_cpu_est_11_3__n N_49_0 \ + N_220 N_6_i N_48_0 N_9_i N_45_0 un6_uds_000_1 N_10_i pos_clk_un24_bgack_030_int_i_0_n a_c_16__n N_44_0 N_244 \ + N_14_i N_245 a_c_17__n N_41_0 N_15_i N_80 a_c_18__n N_40_0 N_90 N_17_i N_100 \ + a_c_19__n N_38_0 N_105 N_19_i pos_clk_un11_clk_000_n_sync_n a_c_20__n N_36_0 N_22_i a_c_21__n N_33_0 N_135 \ + BG_030_c_i N_133 a_c_22__n pos_clk_un6_bg_030_i_n N_190 pos_clk_un8_bg_030_0_n N_188 a_c_23__n N_127_i_1 N_189 N_127_i_2 \ + N_136 a_c_24__n pos_clk_un11_ds_030_d0_i_1_n pos_clk_un7_clk_000_d0_n N_135_i_1 pos_clk_un29_clk_000_ne_d0_n a_c_25__n pos_clk_cpu_est_11_0_1_1__n DSACK1_INT_0_sqmuxa pos_clk_cpu_est_11_0_2_1__n pos_clk_un21_clk_000_ne_d0_n \ + a_c_26__n pos_clk_cpu_est_11_0_1_3__n pos_clk_un5_clk_000_pe_n N_195_1 pos_clk_un9_clk_000_ne_n a_c_27__n N_196_1 pos_clk_un23_clk_000_ne_d0_n N_131_i_1 pos_clk_un27_clk_000_ne_d0_n a_c_28__n \ + N_131_i_2 pos_clk_un14_clk_000_n_sync_n N_131_i_3 N_144 a_c_29__n N_119_i_1 N_146 N_119_i_2 N_143 a_c_30__n N_121_i_1 \ + N_147 N_123_i_1 N_139 a_c_31__n N_123_i_2 N_148 N_125_i_1 N_149 A0_c N_129_i_1 N_150 \ + N_162_1 N_140 A1_c N_163_1 N_151 N_165_1 N_152 nEXP_SPACE_c N_165_2 N_153 N_165_3 \ + N_154 BERR_c un5_ciin_1 N_155 un5_ciin_2 N_141 BG_030_c un5_ciin_3 N_156 un5_ciin_4 N_160 \ + un5_ciin_5 N_142 un5_ciin_6 N_161 un5_ciin_7 N_164 BGACK_000_c un5_ciin_8 N_166 un5_ciin_9 N_132 \ + un5_ciin_10 N_191 un5_ciin_11 N_192 pos_clk_un9_clk_000_ne_1_n N_193 CLK_OSZI_c pos_clk_un9_clk_000_ne_2_n N_194 pos_clk_un9_clk_000_ne_3_n N_197 \ + pos_clk_un9_clk_000_ne_4_n N_198 CLK_EXP_c pos_clk_un5_clk_000_pe_1_n N_195 pos_clk_un5_clk_000_pe_2_n N_196 pos_clk_un5_clk_000_pe_3_n N_162 FPU_SENSE_c pos_clk_un27_clk_000_ne_d0_1_n \ + N_199 pos_clk_un27_clk_000_ne_d0_2_n N_199_1 pos_clk_un27_clk_000_ne_d0_3_n N_163 RESET_OUT_0_sqmuxa_7_1 N_165 RESET_OUT_0_sqmuxa_7_2 N_73 RESET_OUT_0_sqmuxa_7_3 N_94 \ + RESET_OUT_0_sqmuxa_5_1 N_85 N_87_1 N_84 ipl_c_0__n N_87_2 N_83 pos_clk_un24_bgack_030_int_i_0_0_1_n pos_clk_un9_clk_000_n_sync_n ipl_c_1__n pos_clk_un24_bgack_030_int_i_0_0_2_n \ + N_72_0_1 ipl_c_2__n pos_clk_un7_clk_000_d0_1_n N_213 un21_fpu_cs_1 un22_berr_1_0 N_211 DTACK_c N_116_1 N_116_2 N_209 \ + N_116_3 N_116_4 VPA_c pos_clk_un6_bg_030_1_n N_205 N_115_0_1 N_245_0_1 RESET_OUT_0_sqmuxa_1 RST_c N_247_i_1 RESET_OUT_0_sqmuxa \ + N_248_i_1 RESET_OUT_0_sqmuxa_7 N_249_i_1 RESET_OUT_0_sqmuxa_5 RW_c pos_clk_ipl_1_n un1_rst_dly_i_m_8__n amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n fc_c_0__n amiga_bus_enable_dma_high_0_un1_n \ + un1_rst_dly_i_m_6__n amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n fc_c_1__n amiga_bus_enable_dma_low_0_un3_n un1_rst_dly_i_m_4__n amiga_bus_enable_dma_low_0_un1_n un1_rst_dly_i_m_3__n amiga_bus_enable_dma_low_0_un0_n un1_rst_dly_i_m_2__n AMIGA_BUS_DATA_DIR_c \ + rw_000_dma_0_un3_n N_86 rw_000_dma_0_un1_n N_93 rw_000_dma_0_un0_n N_87 bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_030.OE \ + AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE \ + RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE .names un6_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c @@ -243,13 +243,13 @@ 1 1 .names AS_000.PIN AS_000_c 1 1 -.names N_98.BLIF AS_000.OE +.names un1_as_000_i.BLIF AS_000.OE 1 1 .names inst_RW_000_INT.BLIF RW_000 1 1 .names RW_000.PIN RW_000_c 1 1 -.names N_98.BLIF RW_000.OE +.names un1_as_000_i.BLIF RW_000.OE 1 1 .names un6_ds_030_i.BLIF DS_030 1 1 @@ -261,13 +261,13 @@ 1 1 .names UDS_000.PIN UDS_000_c 1 1 -.names N_98.BLIF UDS_000.OE +.names un1_as_000_i.BLIF UDS_000.OE 1 1 .names un6_lds_000_i.BLIF LDS_000 1 1 .names LDS_000.PIN LDS_000_c 1 1 -.names N_98.BLIF LDS_000.OE +.names un1_as_000_i.BLIF LDS_000.OE 1 1 .names un4_size.BLIF SIZE_0_ 1 1 @@ -297,7 +297,7 @@ 1 1 .names RW.PIN RW_c 1 1 -.names N_99.BLIF RW.OE +.names N_100.BLIF RW.OE 1 1 .names gnd_n_n.BLIF CLK_DIV_OUT 1 1 @@ -307,1624 +307,1626 @@ 1 1 .names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE 1 1 -.names vcc_n_n.BLIF CIIN +.names un5_ciin.BLIF CIIN 1 1 -.names un8_ciin.BLIF CIIN.OE +.names un8_ciin_i.BLIF CIIN.OE 1 1 -.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 -1- 1 --1 1 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D -1 1 -.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n -11 1 -.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF pos_clk_un40_bgack_030_int_1_n -11 1 -.names N_115.BLIF rw_000_int_0_un3_n +.names N_252.BLIF size_dma_0_0__un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C -1 1 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D -1 1 -.names pos_clk_clk_000_n_sync_2_0__n.BLIF AS_030_000_SYNC_i.BLIF pos_clk_un7_clk_000_d0_1_n +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_245.BLIF N_115.BLIF rw_000_int_0_un1_n -11 1 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D -1 1 -.names pos_clk_un7_clk_000_d0_1_n.BLIF inst_nEXP_SPACE_D0reg.BLIF pos_clk_un7_clk_000_d0_n -11 1 -.names pos_clk_un29_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_i_n -0 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 -11 1 -.names sm_amiga_i_2__n.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_151 -11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14 -1- 1 --1 1 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 -11 1 -.names N_140.BLIF sm_amiga_i_3__n.BLIF N_150 -11 1 -.names un14_amiga_bus_data_dir.BLIF un14_amiga_bus_data_dir_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C -1 1 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -.names a_i_29__n.BLIF a_i_30__n.BLIF un8_ciin_5 -11 1 -.names inst_CLK_000_NE_D0.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_n -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -.names un8_ciin_1.BLIF un8_ciin_2.BLIF un8_ciin_6 -11 1 -.names pos_clk_un21_clk_000_ne_d0_i_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF pos_clk_un23_clk_000_ne_d0_0_n -11 1 -.names un14_amiga_bus_data_dir_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n -11 1 -.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D -1 1 -.names un8_ciin_3.BLIF un8_ciin_4.BLIF un8_ciin_7 -11 1 -.names pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF pos_clk_un7_clk_000_pe_0_n -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -.names un8_ciin_6.BLIF un8_ciin_7.BLIF un8_ciin_8 -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -.names un8_ciin_8.BLIF un8_ciin_5.BLIF un8_ciin -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un21_clk_000_ne_d0_n -11 1 -.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n -0 1 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_116_1 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n -11 1 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D -1 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF N_116_2 -11 1 -.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C 1 1 .names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D 1 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF N_116_3 +.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 11 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names pos_clk_size_dma_6_0__n.BLIF N_252.BLIF size_dma_0_0__un1_n 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 1- 1 -1 1 .names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D 1 1 -.names N_116_1.BLIF N_116_2.BLIF N_116_4 +.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i +0 1 +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +1 1 +.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 +11 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 -1 1 -.names N_90.BLIF N_90_i +.names N_115.BLIF rw_000_int_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D 1 1 -.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D +.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +11 1 +.names N_8_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_115.BLIF rw_000_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C 1 1 -.names N_116_4.BLIF N_116_3.BLIF N_116 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D 1 1 -.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 11 1 -.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +.names N_12_i.BLIF RST_c.BLIF N_43_0 11 1 -.names N_90_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names un22_berr_1_0.BLIF N_116.BLIF un22_berr -11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D 1 1 -.names FPU_SENSE_i.BLIF N_116.BLIF un21_fpu_cs_1 +.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +.names N_13_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_15 1- 1 -1 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_19 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +11 1 +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +11 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin +11 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF pos_clk_un9_clk_000_ne_1_n 11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +.names inst_CLK_000_PE.BLIF CLK_000_PE_i 0 1 -.names N_91.BLIF N_91_i +.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +.names inst_CLK_000_NE.BLIF VPA_D_i.BLIF pos_clk_un9_clk_000_ne_2_n +11 1 +.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_76_i +11 1 +.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D 1 1 .names N_152_i.BLIF N_153_i.BLIF N_123_i_1 11 1 -.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names N_199_i.BLIF N_197_i.BLIF pos_clk_cpu_est_11_0_1_3__n -11 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names N_91_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_198_i.BLIF pos_clk_cpu_est_11_0_3__n -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_19 1- 1 -1 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names N_194_i.BLIF N_192_i.BLIF pos_clk_cpu_est_11_0_1_1__n -11 1 -.names N_18_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D 1 1 -.names N_191_i.BLIF N_193_i.BLIF pos_clk_cpu_est_11_0_2_1__n +.names N_154_i.BLIF RST_c.BLIF N_123_i_2 11 1 -.names N_22_i.BLIF RST_c.BLIF N_33_0 +.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n 11 1 .names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_cpu_est_11_0_1__n +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +.names N_123_i_1.BLIF N_123_i_2.BLIF SM_AMIGA_3_.D +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n 11 1 -.names N_97.BLIF bgack_030_int_0_un3_n -0 1 .names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names N_163_i.BLIF N_137_i.BLIF N_131_i_1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D +1 1 +.names N_155_i.BLIF N_156_i.BLIF N_125_i_1 11 1 -.names inst_BGACK_030_INTreg.BLIF N_97.BLIF bgack_030_int_0_un1_n -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names N_162_i.BLIF N_164_i.BLIF N_131_i_2 -11 1 -.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_80 1- 1 -1 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D +1 1 +.names N_125_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_160_i.BLIF N_161_i.BLIF N_129_i_1 +11 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF N_105 +11 1 +.names N_22_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names N_129_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_19_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +.names N_135.BLIF BERR_i.BLIF N_162_1 +11 1 +.names N_105.BLIF un1_SM_AMIGA_7.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names N_162_1.BLIF CLK_000_PE_i.BLIF N_162 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names N_133.BLIF BERR_i.BLIF N_163_1 +11 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF pos_clk_clk_000_n_sync_2_0__n +11 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_163_1.BLIF CLK_000_NE_i.BLIF N_163 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_10_i.BLIF RST_c.BLIF N_44_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +.names N_133_i.BLIF N_135_i.BLIF N_165_1 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +11 1 +.names N_9_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_165_2 +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names inst_DS_030_D0.BLIF DS_030_D0_i +0 1 +.names N_165_1.BLIF N_165_2.BLIF N_165_3 +11 1 +.names A1_c.BLIF A1_i +0 1 +.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +11 1 +.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_cpu_est_11_0_1__n +11 1 +.names A1_i.BLIF BGACK_030_INT_i.BLIF N_92 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +.names N_199_i.BLIF N_197_i.BLIF pos_clk_cpu_est_11_0_1_3__n +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_198_i.BLIF pos_clk_cpu_est_11_0_3__n +11 1 +.names N_72.BLIF N_105.BLIF N_96 +11 1 +.names un8_ciin.BLIF un8_ciin_i +0 1 +.names N_188.BLIF cpu_est_0_.BLIF N_195_1 +11 1 +.names N_105.BLIF N_116.BLIF N_97 +11 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names N_195_1.BLIF cpu_est_i_3__n.BLIF N_195 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_104 +11 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_196_1 +11 1 +.names N_88_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_196_1.BLIF cpu_est_i_2__n.BLIF N_196 +11 1 +.names N_89_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names N_137_i.BLIF N_162_i.BLIF N_131_i_1 +11 1 +.names N_96_i.BLIF N_97_i.BLIF N_250_0 +11 1 +.names un6_uds_000.BLIF un6_uds_000_i +0 1 +.names N_163_i.BLIF N_164_i.BLIF N_131_i_2 +11 1 +.names BGACK_000_c.BLIF N_76.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names un6_lds_000.BLIF un6_lds_000_i +0 1 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C 1 1 .names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names inst_DS_030_D0.BLIF DS_030_D0_i +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_251_0 +11 1 +.names N_245.BLIF ds_000_dma_0_un3_n 0 1 .names N_131_i_3.BLIF N_165_i.BLIF SM_AMIGA_i_7_.D 11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_189_i +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_252_0 11 1 -.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +.names pos_clk_ds_000_dma_4_n.BLIF N_245.BLIF ds_000_dma_0_un1_n 11 1 -.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n +.names N_147_i.BLIF N_148_i.BLIF N_119_i_1 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF pos_clk_un11_ds_030_d0_i_n +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_188_i +.names N_149_i.BLIF RST_c.BLIF N_119_i_2 11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 -.names a_i_31__n.BLIF inst_nEXP_SPACE_D0reg.BLIF un8_ciin_1 -11 1 -.names N_195_i.BLIF N_196_i.BLIF N_186_i -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n -11 1 -.names AS_030_D0_i.BLIF a_i_24__n.BLIF un8_ciin_2 -11 1 -.names N_190_i.BLIF cpu_est_i_2__n.BLIF N_198 -11 1 -.names un6_as_030.BLIF un6_as_030_i -0 1 -.names a_i_25__n.BLIF a_i_26__n.BLIF un8_ciin_3 -11 1 -.names N_190.BLIF cpu_est_3_reg.BLIF N_197 -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names a_i_27__n.BLIF a_i_28__n.BLIF un8_ciin_4 -11 1 -.names N_188_i.BLIF cpu_est_3_reg.BLIF N_194 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 -.names N_16.BLIF N_16_i -0 1 -.names N_189_i.BLIF cpu_est_0_.BLIF N_193 -11 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names N_39_0.BLIF inst_UDS_000_INT.D -0 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_19.BLIF N_19_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names un6_uds_000.BLIF un6_uds_000_i -0 1 -.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_192 -11 1 -.names un6_lds_000.BLIF un6_lds_000_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 -.names N_20.BLIF N_20_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n -0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_189.BLIF cpu_est_i_0__n.BLIF N_191 -11 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un1_n -11 1 -.names N_21.BLIF N_21_i -0 1 -.names N_132_i.BLIF SM_AMIGA_2_.BLIF N_140_0 -11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names N_34_0.BLIF BG_000DFFreg.D -0 1 -.names SM_AMIGA_3_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_136_i -11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C -1 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names N_211.BLIF RST_DLY_5_.BLIF N_213 -11 1 -.names vcc_n_n -1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names N_209.BLIF RST_DLY_4_.BLIF N_211 -11 1 -.names gnd_n_n -.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n -0 1 -.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 -11 1 -.names A_23_.BLIF a_23__n -1 1 -.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_251_0_1 -11 1 -.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 -11 1 -.names A_22_.BLIF a_22__n -1 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C -1 1 -.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0 -11 1 -.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 -11 1 -.names A_21_.BLIF a_21__n -1 1 -.names N_150_i.BLIF N_151_i.BLIF N_121_i_1 -11 1 -.names N_252.BLIF sm_amiga_i_2__n.BLIF N_83 -11 1 -.names A_20_.BLIF a_20__n -1 1 -.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D -11 1 -.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_97 -11 1 -.names A_15_.BLIF a_15__n -1 1 -.names N_50_0.BLIF inst_DS_030_D0.D -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names A_14_.BLIF a_14__n -1 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C -1 1 -.names N_8.BLIF N_8_i -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_252_0 -11 1 -.names A_13_.BLIF a_13__n -1 1 -.names N_46_0.BLIF inst_A0_DMA.D -0 1 -.names A_12_.BLIF a_12__n -1 1 -.names N_9.BLIF N_9_i -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names A_11_.BLIF a_11__n -1 1 -.names N_45_0.BLIF inst_DSACK1_INTreg.D -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_199_1 -11 1 -.names A_10_.BLIF a_10__n -1 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names N_10.BLIF N_10_i -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names A_9_.BLIF a_9__n -1 1 -.names N_44_0.BLIF inst_AS_000_INT.D -0 1 -.names N_199_1.BLIF cpu_est_i_2__n.BLIF N_199 -11 1 -.names A_8_.BLIF a_8__n -1 1 -.names N_12.BLIF N_12_i -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_190_i -11 1 -.names A_7_.BLIF a_7__n -1 1 -.names N_43_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names G_141.BLIF un1_rst_dly_i_4__n -0 1 -.names A_6_.BLIF a_6__n -1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_13.BLIF N_13_i -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n -11 1 -.names A_5_.BLIF a_5__n -1 1 -.names N_42_0.BLIF inst_LDS_000_INT.D -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_2_.D -11 1 -.names A_4_.BLIF a_4__n -1 1 -.names N_14.BLIF N_14_i -0 1 -.names G_139.BLIF un1_rst_dly_i_3__n -0 1 -.names A_3_.BLIF a_3__n -1 1 -.names N_41_0.BLIF inst_RW_000_INT.D -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n -11 1 -.names A_2_.BLIF a_2__n -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names N_15.BLIF N_15_i -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D -11 1 -.names N_40_0.BLIF inst_RW_000_DMA.D -0 1 -.names G_137.BLIF un1_rst_dly_i_2__n -0 1 -.names N_31_0.BLIF IPL_030DFF_1_reg.D -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n -11 1 -.names N_23.BLIF N_23_i -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_38_0 -11 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C -1 1 -.names N_30_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names N_38.BLIF RST_c.BLIF inst_RESET_OUTreg.D -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i -0 1 -.names N_54_0.BLIF IPL_D0_2_.D -0 1 -.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_77_i_i -0 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names N_77_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_85 -11 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names N_53_0.BLIF IPL_D0_1_.D -0 1 -.names N_85_i.BLIF RST_c.BLIF RST_DLY_0_.D -11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names N_52_0.BLIF IPL_D0_0_.D -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names N_57_0.BLIF inst_DTACK_D0.D -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D -11 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names G_149.BLIF un1_rst_dly_i_8__n -0 1 -.names N_56_0.BLIF inst_VPA_D.D -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_7__n.BLIF RST_DLY_6_.D -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D -0 1 -.names G_147.BLIF un1_rst_dly_i_7__n -0 1 -.names N_158.BLIF N_158_i -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n -11 1 -.names N_155.BLIF N_155_i -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_6__n.BLIF RST_DLY_5_.D -11 1 -.names N_156.BLIF N_156_i -0 1 -.names G_145.BLIF un1_rst_dly_i_6__n -0 1 -.names CLK_OSZI_c.BLIF inst_DS_030_D0.C -1 1 -.names N_154.BLIF N_154_i -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n -11 1 -.names N_152.BLIF N_152_i -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_5__n.BLIF RST_DLY_4_.D -11 1 -.names N_153.BLIF N_153_i -0 1 -.names G_143.BLIF un1_rst_dly_i_5__n -0 1 -.names N_142_0.BLIF N_142 -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -.names N_141_0.BLIF N_141 -0 1 -.names RST_c.BLIF un1_rst_dly_i_m_i_4__n.BLIF RST_DLY_3_.D -11 1 -.names N_138_0.BLIF N_138 -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_132_i.BLIF N_132 -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_89 -11 1 -.names A0_c.BLIF A0_c_i -0 1 -.names N_71.BLIF sm_amiga_i_0__n.BLIF N_88 -11 1 -.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C -1 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names BGACK_030_INT_i.BLIF N_249.BLIF N_87 -11 1 -.names N_25.BLIF N_25_i -0 1 -.names BGACK_030_INT_i.BLIF N_249_i.BLIF N_86 -11 1 -.names N_32_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84 -11 1 -.names N_24.BLIF N_24_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names N_93.BLIF N_93_i -0 1 -.names inst_RESET_OUTreg.BLIF RESET_OUT_i -0 1 -.names N_94.BLIF N_94_i -0 1 -.names inst_RESET_OUTreg.BLIF un1_as_030_i.BLIF un3_as_030_i -11 1 -.names N_244_0.BLIF N_244 -0 1 -.names N_245_0.BLIF N_245 -0 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names N_246_0.BLIF N_246 -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C -1 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n -0 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names N_249_i.BLIF N_249 -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names N_251_0.BLIF N_251 -0 1 -.names N_248.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_241_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -.names N_71_0.BLIF N_71 -0 1 -.names N_88_i.BLIF N_137_i.BLIF SM_AMIGA_0_.D -11 1 -.names N_104.BLIF N_104_i -0 1 -.names N_87_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_160.BLIF N_160_i -0 1 -.names N_86_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C -1 1 -.names N_161.BLIF N_161_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names N_159.BLIF N_159_i -0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names N_157.BLIF N_157_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D -11 1 -.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n -0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_99 -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF N_98 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n -0 1 -.names N_116.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_94 -11 1 -.names N_76.BLIF N_76_i -0 1 -.names N_251.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_93 -11 1 -.names N_83.BLIF N_83_i -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names N_84.BLIF N_84_i -0 1 -.names A1_c.BLIF A1_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_115_0.BLIF N_115 -0 1 -.names A1_i.BLIF BGACK_030_INT_i.BLIF N_91 -11 1 -.names N_86.BLIF N_86_i -0 1 -.names A1_c.BLIF BGACK_030_INT_i.BLIF N_90 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names N_132.BLIF SM_AMIGA_0_.BLIF N_104 -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -.names N_87.BLIF N_87_i -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un1_n -11 1 -.names N_88.BLIF N_88_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un0_n -11 1 -.names N_241_0.BLIF N_241 -0 1 -.names un1_amiga_bus_enable_dma_high_i_m4_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un0_n.BLIF N_78 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -.names N_242_0.BLIF N_242 -0 1 -.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_71_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names N_243_0.BLIF N_243 -0 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF N_249_i -11 1 -.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n -0 1 .names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_un5_bgack_030_int_d_i_n 11 1 -.names N_198.BLIF N_198_i -0 1 -.names RW_c.BLIF RW_i -0 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -.names N_197.BLIF N_197_i -0 1 -.names SM_AMIGA_5_.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names N_199.BLIF N_199_i -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un1_n -11 1 -.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n -0 1 -.names sm_amiga_i_3__n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un0_n -11 1 -.names N_151.BLIF N_151_i -0 1 -.names ds_000_enable_1_sqmuxa_1_i_m4_un1_n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un0_n.BLIF N_248 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C 1 1 -.names N_150.BLIF N_150_i -0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +.names N_119_i_1.BLIF N_119_i_2.BLIF SM_AMIGA_1_.D 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names N_135_i.BLIF N_135 -0 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_246_0 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_256_i 11 1 -.names N_252_0.BLIF N_252 +.names N_244.BLIF as_000_dma_0_un3_n 0 1 +.names N_150_i.BLIF N_151_i.BLIF N_121_i_1 +11 1 .names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names N_85.BLIF N_85_i -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF N_245_0 +.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_244.BLIF as_000_dma_0_un1_n 11 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names N_38_0.BLIF N_38 -0 1 -.names N_93_i.BLIF N_94_i.BLIF N_244_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n -0 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_243_0 -11 1 -.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n -0 1 -.names N_80_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_242_0 -11 1 -.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n -0 1 -.names N_248.BLIF N_248_i -0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n -0 1 -.names N_138.BLIF sm_amiga_i_6__n.BLIF N_157 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n -0 1 -.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_158 -11 1 -.names pos_clk_un27_clk_000_ne_d0_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n +.names N_36_0.BLIF inst_VMA_INTreg.D 0 1 .names CLK_000_PE_i.BLIF sm_amiga_i_5__n.BLIF N_159 11 1 -.names pos_clk_un21_clk_000_ne_d0_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n -0 1 -.names N_142.BLIF SM_AMIGA_i_7_.BLIF N_160 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names N_22.BLIF N_22_i +0 1 +.names BERR_c.BLIF BERR_i +0 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C 1 1 -.names pos_clk_un23_clk_000_ne_d0_0_n.BLIF pos_clk_un23_clk_000_ne_d0_n +.names N_33_0.BLIF BG_000DFFreg.D 0 1 -.names sm_amiga_i_6__n.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_161 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_158 11 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names N_136_i.BLIF N_136 -0 1 -.names BERR_c.BLIF CLK_000_PE_i.BLIF N_132_i -11 1 -.names N_140_0.BLIF N_140 -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_138_0 -11 1 -.names N_195.BLIF N_195_i -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 -.names N_196.BLIF N_196_i -0 1 -.names N_132_i.BLIF SM_AMIGA_4_.BLIF N_141_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names N_188_i.BLIF N_188 +.names vcc_n_n +1 +.names BG_030_c.BLIF BG_030_c_i 0 1 .names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names N_189_i.BLIF N_189 +.names gnd_n_n +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n 0 1 -.names N_132_i.BLIF SM_AMIGA_6_.BLIF N_142_0 +.names N_138.BLIF sm_amiga_i_6__n.BLIF N_157 11 1 -.names A_16_.BLIF a_c_16__n +.names A_15_.BLIF a_15__n 1 1 -.names N_190_i.BLIF N_190 +.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n 0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C -1 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names N_193.BLIF N_193_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names N_191.BLIF N_191_i -0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF pos_clk_clk_000_n_sync_2_0__n +.names N_211.BLIF RST_DLY_5_.BLIF N_213 11 1 -.names A_19_.BLIF a_c_19__n +.names A_14_.BLIF a_14__n 1 1 -.names N_192.BLIF N_192_i -0 1 -.names N_104_i.BLIF RST_c.BLIF N_137_i +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +.names N_157_i.BLIF N_158_i.BLIF N_127_i_1 11 1 -.names N_194.BLIF N_194_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C -1 1 -.names pos_clk_ds_000_dma_4_f1_0_n.BLIF pos_clk_ds_000_dma_4_f1_n -0 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C -1 1 -.names N_162.BLIF N_162_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_163.BLIF N_163_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +.names N_209.BLIF RST_DLY_4_.BLIF N_211 11 1 -.names A_24_.BLIF a_c_24__n +.names A_13_.BLIF a_13__n 1 1 -.names N_164.BLIF N_164_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names N_165.BLIF N_165_i -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +.names N_159_i.BLIF RST_c.BLIF N_127_i_2 11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C -1 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names pos_clk_un22_bgack_030_int_0_n.BLIF pos_clk_un22_bgack_030_int_n -0 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 11 1 -.names A_27_.BLIF a_c_27__n +.names A_12_.BLIF a_12__n 1 1 -.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i +.names N_127_i_1.BLIF N_127_i_2.BLIF SM_AMIGA_5_.D 11 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF un14_amiga_bus_data_dir +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 11 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C +.names A_11_.BLIF a_11__n 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names N_22.BLIF N_22_i -0 1 -.names N_136.BLIF sm_amiga_i_4__n.BLIF N_152 +.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n 11 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names N_33_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_153 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 11 1 -.names N_18.BLIF N_18_i -0 1 -.names CLK_000_PE_i.BLIF sm_amiga_i_3__n.BLIF N_154 +.names A_10_.BLIF a_10__n +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF pos_clk_un11_ds_030_d0_i_n 11 1 -.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D -1 1 -.names A1.BLIF A1_c -1 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_141.BLIF sm_amiga_i_5__n.BLIF N_155 +.names BGACK_030_INT_i.BLIF N_256_i.BLIF N_88 11 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C +.names A_9_.BLIF a_9__n 1 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names pos_clk_un9_clk_000_ne_n.BLIF pos_clk_un9_clk_000_ne_i_n -0 1 -.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_156 +.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_135_i_1 11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C -1 1 -.names pos_clk_un5_clk_000_pe_n.BLIF pos_clk_un5_clk_000_pe_i_n -0 1 -.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +.names BGACK_030_INT_i.BLIF N_256.BLIF N_89 11 1 -.names BG_030.BLIF BG_030_c +.names A_8_.BLIF a_8__n 1 1 -.names N_6.BLIF N_6_i -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names BG_000DFFreg.BLIF BG_000 -1 1 -.names N_48_0.BLIF inst_AS_000_DMA.D -0 1 -.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +.names N_135_i_1.BLIF sm_amiga_i_6__n.BLIF N_135_i 11 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names AS_030_i.BLIF RST_c.BLIF N_90 +11 1 +.names A_7_.BLIF a_7__n 1 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +.names N_191_i.BLIF N_192_i.BLIF pos_clk_cpu_est_11_0_1_1__n +11 1 +.names A1_c.BLIF BGACK_030_INT_i.BLIF N_91 +11 1 +.names A_6_.BLIF a_6__n 1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 +.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C +1 1 +.names N_193_i.BLIF N_194_i.BLIF pos_clk_cpu_est_11_0_2_1__n +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names A_5_.BLIF a_5__n 1 1 .names N_3.BLIF N_3_i 0 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names BGACK_000.BLIF BGACK_000_c +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_86 +11 1 +.names A_4_.BLIF a_4__n 1 1 .names N_49_0.BLIF inst_DS_000_DMA.D 0 1 -.names a_c_25__n.BLIF a_i_25__n +.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_93 +11 1 +.names A_3_.BLIF a_3__n +1 1 +.names N_6.BLIF N_6_i +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_100 +11 1 +.names A_2_.BLIF a_2__n +1 1 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names N_48_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_86_i.BLIF N_87_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_9.BLIF N_9_i +0 1 +.names N_93_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D +11 1 +.names N_45_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names inst_RESET_OUTreg.BLIF RESET_OUT_i +0 1 +.names N_10.BLIF N_10_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names N_44_0.BLIF inst_AS_000_INT.D +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_257_0 +11 1 +.names N_14.BLIF N_14_i +0 1 +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_1__n.BLIF RST_DLY_0_.D +11 1 +.names N_15.BLIF N_15_i +0 1 +.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names N_40_0.BLIF inst_RW_000_INT.D +0 1 +.names G_135.BLIF un1_rst_dly_i_1__n +0 1 +.names N_17.BLIF N_17_i +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_1__n.BLIF un1_rst_dly_i_m_1__n +11 1 +.names N_38_0.BLIF inst_UDS_000_INT.D +0 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_138_0 +11 1 +.names N_19.BLIF N_19_i +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_6__n.BLIF RST_DLY_5_.D +11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_23.BLIF N_23_i +0 1 +.names G_145.BLIF un1_rst_dly_i_6__n +0 1 +.names N_30_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_5__n.BLIF RST_DLY_4_.D +11 1 +.names N_54_0.BLIF IPL_D0_2_.D +0 1 +.names G_143.BLIF un1_rst_dly_i_5__n +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n +11 1 +.names N_53_0.BLIF IPL_D0_1_.D +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_4__n.BLIF RST_DLY_3_.D +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names G_141.BLIF un1_rst_dly_i_4__n +0 1 +.names N_52_0.BLIF IPL_D0_0_.D +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_2_.D +11 1 +.names N_57_0.BLIF inst_DTACK_D0.D +0 1 +.names G_139.BLIF un1_rst_dly_i_3__n +0 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n +11 1 +.names N_56_0.BLIF inst_VPA_D.D +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +0 1 +.names G_137.BLIF un1_rst_dly_i_2__n +0 1 +.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n +11 1 +.names N_50_0.BLIF inst_DS_030_D0.D +0 1 +.names inst_RESET_OUTreg.BLIF un1_as_030_i.BLIF un3_as_030_i +11 1 +.names N_146.BLIF N_146_i +0 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +.names N_144.BLIF N_144_i +0 1 +.names un1_SM_AMIGA_7_i.BLIF un1_SM_AMIGA_7 +0 1 +.names pos_clk_un21_clk_000_ne_d0_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n +0 1 +.names pos_clk_un27_clk_000_ne_d0_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n +0 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names pos_clk_un23_clk_000_ne_d0_0_n.BLIF pos_clk_un23_clk_000_ne_d0_n +0 1 +.names pos_clk_un5_clk_000_pe_n.BLIF pos_clk_un5_clk_000_pe_i_n +0 1 +.names pos_clk_un9_clk_000_ne_n.BLIF pos_clk_un9_clk_000_ne_i_n +0 1 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa +11 1 +.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names A0_c.BLIF A0_c_i +0 1 +.names G_149.BLIF un1_rst_dly_i_8__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n +11 1 +.names N_25.BLIF N_25_i +0 1 +.names RST_c.BLIF un1_rst_dly_i_m_i_7__n.BLIF RST_DLY_6_.D +11 1 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names G_147.BLIF un1_rst_dly_i_7__n +0 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names N_24.BLIF N_24_i +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +.names N_31_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_85_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF pos_clk_ds_000_dma_4_0_n +11 1 +.names N_193.BLIF N_193_i +0 1 +.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF N_244_0 +11 1 +.names N_190_i.BLIF N_190 +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names CLK_OSZI_c.BLIF inst_DS_030_D0.C +1 1 +.names N_189_i.BLIF N_189 +0 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names N_188_i.BLIF N_188 +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_195.BLIF N_195_i +0 1 +.names CLK_030_H_i.BLIF N_73.BLIF N_94 +11 1 +.names N_196.BLIF N_196_i +0 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_85 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names N_143_0.BLIF N_143 +0 1 +.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_84 +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +.names N_142_0.BLIF N_142 +0 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_83 +11 1 +.names N_141_0.BLIF N_141 +0 1 +.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n +11 1 +.names N_140_0.BLIF N_140 +0 1 +.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +0 1 +.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C +1 1 +.names N_139_0.BLIF N_139 +0 1 +.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un9_clk_000_n_sync_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +.names N_166.BLIF N_166_i +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names N_136_i.BLIF N_136 +0 1 +.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n +11 1 +.names N_133_i.BLIF N_133 +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names N_132_i.BLIF N_132 +0 1 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names N_147.BLIF N_147_i +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_148.BLIF N_148_i +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names N_164.BLIF N_164_i +0 1 +.names pos_clk_un7_clk_000_d0_n.BLIF pos_clk_un7_clk_000_d0_i_n +0 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names N_165.BLIF N_165_i +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_163.BLIF N_163_i +0 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names N_199.BLIF N_199_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names N_197.BLIF N_197_i +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_199_1 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names N_198.BLIF N_198_i +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names N_194.BLIF N_194_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n +0 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +.names N_192.BLIF N_192_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names N_135_i.BLIF N_135 +0 1 +.names N_162.BLIF N_162_i +0 1 +.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_73_0 +11 1 +.names N_191.BLIF N_191_i +0 1 +.names N_132_i.BLIF SM_AMIGA_6_.BLIF N_142_0 +11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +.names N_245_0.BLIF N_245 +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names N_85.BLIF N_85_i +0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_143_0 +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names N_189.BLIF cpu_est_i_0__n.BLIF N_191 +11 1 +.names N_94.BLIF N_94_i +0 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_192 +11 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names N_73_0.BLIF N_73 +0 1 +.names N_189_i.BLIF cpu_est_0_.BLIF N_193 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names N_160.BLIF N_160_i +0 1 +.names N_188_i.BLIF cpu_est_3_reg.BLIF N_194 +11 1 +.names N_161.BLIF N_161_i +0 1 +.names N_190.BLIF cpu_est_3_reg.BLIF N_197 +11 1 +.names N_155.BLIF N_155_i +0 1 +.names N_190_i.BLIF cpu_est_i_2__n.BLIF N_198 +11 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names N_156.BLIF N_156_i +0 1 +.names N_195_i.BLIF N_196_i.BLIF N_186_i +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names N_154.BLIF N_154_i +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_188_i +11 1 +.names N_152.BLIF N_152_i +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_189_i +11 1 +.names N_153.BLIF N_153_i +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_190_i +11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names N_150.BLIF N_150_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names N_151.BLIF N_151_i +0 1 +.names N_199_1.BLIF cpu_est_i_2__n.BLIF N_199 +11 1 +.names N_149.BLIF N_149_i +0 1 +.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_156 +11 1 +.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n +0 1 +.names N_142.BLIF SM_AMIGA_i_7_.BLIF N_160 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C +1 1 +.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n +0 1 +.names sm_amiga_i_6__n.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_161 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n +0 1 +.names BERR_i.BLIF N_136_i.BLIF N_164 +11 1 +.names A_16_.BLIF a_c_16__n +1 1 +.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n +0 1 +.names N_132.BLIF SM_AMIGA_0_.BLIF N_166 +11 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n +0 1 +.names N_137_i.BLIF N_146_i.BLIF SM_AMIGA_0_.D +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +1 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n +0 1 +.names BERR_c.BLIF CLK_000_PE_i.BLIF N_132_i +11 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_133_i +11 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n +0 1 +.names SM_AMIGA_3_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_136_i +11 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n +0 1 +.names N_166_i.BLIF RST_c.BLIF N_137_i +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n +0 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_139_0 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names CLK_EXP_c.BLIF CLK_EXP_c_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names N_244_0.BLIF N_244 +0 1 +.names N_132_i.BLIF SM_AMIGA_2_.BLIF N_140_0 +11 1 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names N_83.BLIF N_83_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names N_115_0.BLIF N_115 +0 1 +.names N_132_i.BLIF SM_AMIGA_4_.BLIF N_141_0 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names N_84.BLIF N_84_i +0 1 +.names N_105.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names A_28_.BLIF a_c_28__n +1 1 +.names N_250_0.BLIF N_250 +0 1 +.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i +0 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names N_89.BLIF N_89_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF N_105.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +1 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_5__n.BLIF N_144 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names N_88.BLIF N_88_i +0 1 +.names N_143.BLIF sm_amiga_i_0__n.BLIF N_146 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names N_139.BLIF sm_amiga_i_2__n.BLIF N_147 +11 1 +.names A1.BLIF A1_c +1 1 +.names N_138_0.BLIF N_138 +0 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF N_148 +11 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names un1_rst_dly_i_m_1__n.BLIF un1_rst_dly_i_m_i_1__n +0 1 +.names CLK_000_PE_i.BLIF sm_amiga_i_1__n.BLIF N_149 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names N_157.BLIF N_157_i +0 1 +.names N_140.BLIF sm_amiga_i_3__n.BLIF N_150 +11 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_158.BLIF N_158_i +0 1 +.names pos_clk_un29_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_i_n 0 1 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C 1 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names N_159.BLIF N_159_i +0 1 +.names sm_amiga_i_2__n.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_151 +11 1 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names N_257_0.BLIF inst_BGACK_030_INT_D.D +0 1 +.names N_136.BLIF sm_amiga_i_4__n.BLIF N_152 +11 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_93.BLIF N_93_i +0 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_153 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 .names CLK_030.BLIF CLK_EXP_c 1 1 -.names pos_clk_un29_bgack_030_int_n.BLIF pos_clk_un29_bgack_030_int_i_n -0 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names CLK_000.BLIF inst_CLK_000_D0.D -1 1 -.names pos_clk_un26_bgack_030_int_n.BLIF pos_clk_un26_bgack_030_int_i_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C -1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names pos_clk_un27_bgack_030_int_0_n.BLIF pos_clk_un27_bgack_030_int_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names CLK_030_H_0_sqmuxa.BLIF CLK_030_H_0_sqmuxa_i -0 1 -.names a_c_29__n.BLIF a_i_29__n +.names N_87.BLIF N_87_i 0 1 +.names CLK_000_PE_i.BLIF sm_amiga_i_3__n.BLIF N_154 +11 1 .names CLK_OSZI_c.BLIF inst_CLK_000_D0.C 1 1 -.names CLK_EXP_c.BLIF CLK_EXP +.names CLK_000.BLIF inst_CLK_000_D0.D 1 1 -.names N_7.BLIF N_7_i +.names N_86.BLIF N_86_i 0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names un21_fpu_cs_i.BLIF FPU_CS -1 1 -.names N_47_0.BLIF N_47 -0 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -.names FPU_SENSE.BLIF FPU_SENSE_c -1 1 -.names N_133_i.BLIF N_133 -0 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_CLK_000_PE.BLIF G_159.X1 -1 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ -1 1 -.names N_176.BLIF N_176_i -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ -1 1 -.names N_175.BLIF N_175_i -0 1 -.names CYCLE_DMA_0_.BLIF G_159.X2 -1 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +.names N_141.BLIF sm_amiga_i_5__n.BLIF N_155 +11 1 +.names CLK_OSZI.BLIF CLK_OSZI_c 1 1 .names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names CLK_OSZI_c.BLIF RST_DLY_3_.C +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D 1 1 +.names N_8.BLIF N_8_i +0 1 +.names CYCLE_DMA_0_.BLIF pos_clk_un24_bgack_030_int_i_0_x2.X1 +1 1 +.names CLK_EXP_c.BLIF CLK_EXP +1 1 +.names N_46_0.BLIF inst_A0_DMA.D +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names N_76_i.BLIF N_76 +0 1 +.names CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2.X2 +1 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names N_72_0.BLIF N_72 +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un21_clk_000_ne_d0_n +11 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF pos_clk_un7_clk_000_pe_0_n +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +.names inst_CLK_000_NE.BLIF G_135.X1 +1 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names N_256_i.BLIF N_256 +0 1 +.names pos_clk_un21_clk_000_ne_d0_i_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF pos_clk_un23_clk_000_ne_d0_0_n +11 1 .names IPL_0_.BLIF ipl_c_0__n 1 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names un5_ciin.BLIF un5_ciin_i +0 1 +.names RST_DLY_0_.BLIF G_135.X2 +1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names pos_clk_un24_bgack_030_int_i_0_0_n.BLIF pos_clk_un24_bgack_030_int_i_0_n +0 1 +.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF un8_ciin +11 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names N_104.BLIF N_104_i +0 1 +.names inst_CLK_000_NE_D0.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_n +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C +1 1 +.names N_252_0.BLIF N_252 +0 1 +.names RW_c.BLIF RW_i +0 1 +.names RESET_OUT_0_sqmuxa_7.BLIF G_149.X1 +1 1 +.names DTACK.BLIF DTACK_c +1 1 +.names N_251_0.BLIF N_251 +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +11 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF DSACK1_INT_0_sqmuxa +11 1 +.names RST_DLY_7_.BLIF G_149.X2 +1 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names N_97.BLIF N_97_i +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_144_i.BLIF un1_SM_AMIGA_7_i +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +.names VPA.BLIF VPA_c +1 1 +.names N_96.BLIF N_96_i +0 1 +.names G_165.BLIF N_224_i +0 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names N_21.BLIF N_21_i +0 1 +.names G_166.BLIF N_225_i +0 1 +.names N_213.BLIF G_147.X1 +1 1 +.names RST.BLIF RST_c +1 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names G_167.BLIF N_226_i +0 1 +.names inst_RESET_OUTreg.BLIF RESET +1 1 +.names N_20.BLIF N_20_i +0 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_3_.C +1 1 +.names RST_DLY_6_.BLIF G_147.X2 +1 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_16.BLIF N_16_i +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names N_39_0.BLIF inst_RW_000_DMA.D +0 1 +.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +11 1 +.names N_211.BLIF G_145.X1 +1 1 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +.names N_13.BLIF N_13_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_4_.C +1 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 +11 1 +.names RST_DLY_5_.BLIF G_145.X2 +1 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names N_12.BLIF N_12_i +0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names N_80.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +.names N_43_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names CLK_OSZI_c.BLIF RST_DLY_5_.C +1 1 +.names N_209.BLIF G_143.X1 +1 1 +.names N_248_i_1.BLIF N_257_0.BLIF CYCLE_DMA_1_.D +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_249_i_1 +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names RST_DLY_4_.BLIF G_143.X2 +1 1 +.names N_249_i_1.BLIF N_257_0.BLIF CYCLE_DMA_0_.D +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names G_165.BLIF N_224_i -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_0_.X1 -1 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names G_166.BLIF N_225_i -0 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_0__n.BLIF pos_clk_un26_bgack_030_int_n -11 1 -.names G_167.BLIF N_226_i -0 1 -.names CLK_OSZI_c.BLIF RST_DLY_4_.C -1 1 -.names cpu_est_0_.BLIF cpu_est_0_0_.X2 -1 1 -.names DTACK.BLIF DTACK_c -1 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n -0 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_1__n.BLIF pos_clk_un29_bgack_030_int_n -11 1 -.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 -11 1 -.names cpu_est_3_reg.BLIF E -1 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names inst_CLK_000_NE.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.X1 -1 1 -.names VPA.BLIF VPA_c -1 1 -.names N_3_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D -0 1 -.names CLK_OSZI_c.BLIF RST_DLY_5_.C -1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names N_6_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names N_89.BLIF inst_AS_030_D0.D -0 1 -.names RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.X2 -1 1 -.names RST.BLIF RST_c -1 1 -.names pos_clk_un24_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_n -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_57_0 -11 1 -.names inst_RESET_OUTreg.BLIF RESET -1 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 -11 1 .names CLK_OSZI_c.BLIF RST_DLY_6_.C 1 1 -.names RESET_OUT_0_sqmuxa_1.BLIF G_137.X1 -1 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names pos_clk_un24_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 -11 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_23_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names RST_DLY_1_.BLIF G_137.X2 -1 1 -.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE -1 1 -.names DS_000_DMA_2_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 -.names N_24_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_2_sqmuxa.BLIF ds_000_dma_0_un1_n -11 1 -.names N_25_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_7_.C -1 1 -.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names pos_clk_ds_000_dma_4_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names N_246.BLIF size_dma_0_0__un3_n -0 1 -.names RESET_OUT_0_sqmuxa_7.BLIF G_149.X1 -1 1 -.names N_78.BLIF AMIGA_BUS_ENABLE_HIGH -1 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names pos_clk_size_dma_6_0__n.BLIF N_246.BLIF size_dma_0_0__un1_n -11 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names RST_DLY_7_.BLIF G_149.X2 -1 1 -.names N_163_1.BLIF CLK_000_NE_i.BLIF N_163 -11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -.names N_135.BLIF BERR_i.BLIF N_162_1 -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names N_246.BLIF size_dma_0_1__un3_n -0 1 -.names N_162_1.BLIF CLK_000_PE_i.BLIF N_162 -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names pos_clk_size_dma_6_1__n.BLIF N_246.BLIF size_dma_0_1__un1_n -11 1 -.names N_213.BLIF G_147.X1 -1 1 -.names N_176_1.BLIF RW_000_c.BLIF N_176_1_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_175 -11 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names N_176_1_0.BLIF nEXP_SPACE_D0_i.BLIF N_176 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_133_i -11 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -.names RST_DLY_6_.BLIF G_147.X2 -1 1 -.names RW_000_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF DS_000_DMA_2_sqmuxa_1 -11 1 -.names BERR_c.BLIF BERR_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names DS_000_DMA_2_sqmuxa_1.BLIF pos_clk_un40_bgack_030_int_1_i_n.BLIF DS_000_DMA_2_sqmuxa -11 1 -.names BERR_i.BLIF N_136_i.BLIF N_164 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names N_76_i.BLIF N_83_i.BLIF N_119_i_1 -11 1 -.names CLK_030_H_0_sqmuxa_i.BLIF N_7_i.BLIF N_47_0 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_211.BLIF G_145.X1 -1 1 -.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names N_47.BLIF RST_c.BLIF inst_CLK_030_H.D -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 -11 1 -.names inst_CLK_030_H.BLIF pos_clk_un24_bgack_030_int_n.BLIF N_7 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names RST_DLY_5_.BLIF G_145.X2 -1 1 -.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 -11 1 -.names G_161.BLIF un1_rst_2.BLIF CYCLE_DMA_1_.D -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n -11 1 -.names G_159.BLIF un1_rst_2.BLIF CYCLE_DMA_0_.D -11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 .names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n 11 1 -.names RW_000_c.BLIF pos_clk_un24_bgack_030_int_n.BLIF DS_000_DMA_0_sqmuxa -11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names N_209.BLIF G_143.X1 -1 1 -.names inst_CLK_000_NE.BLIF VPA_D_i.BLIF pos_clk_un9_clk_000_ne_2_n -11 1 -.names CLK_EXP_c.BLIF CLK_EXP_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF pos_clk_un9_clk_000_ne_3_n -11 1 -.names CLK_EXP_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names RST_DLY_4_.BLIF G_143.X2 -1 1 -.names pos_clk_un9_clk_000_ne_1_n.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF pos_clk_un9_clk_000_ne_4_n -11 1 -.names N_176_1.BLIF RST_c.BLIF un1_rst_2 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names pos_clk_un9_clk_000_ne_4_n.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF pos_clk_un9_clk_000_ne_n -11 1 -.names pos_clk_un26_bgack_030_int_i_n.BLIF pos_clk_un29_bgack_030_int_i_n.BLIF pos_clk_un27_bgack_030_int_0_n -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C -1 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_196_1 -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names RESET_OUT_0_sqmuxa_5.BLIF G_141.X1 -1 1 -.names N_196_1.BLIF cpu_est_i_2__n.BLIF N_196 -11 1 -.names AS_000_DMA_1_sqmuxa.BLIF AS_000_DMA_i.BLIF CLK_030_H_0_sqmuxa -11 1 .names N_21_i.BLIF RST_c.BLIF N_34_0 11 1 -.names N_188.BLIF cpu_est_0_.BLIF N_195_1 +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 11 1 -.names pos_clk_un7_clk_000_d0_n.BLIF pos_clk_un7_clk_000_d0_i_n +.names RESET_OUT_0_sqmuxa_5.BLIF G_141.X1 +1 1 +.names un22_berr_1_0.BLIF N_116.BLIF un22_berr +11 1 +.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_90.BLIF inst_AS_030_D0.D 0 1 -.names N_20_i.BLIF RST_c.BLIF N_35_0 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_116_1 11 1 +.names N_92.BLIF N_92_i +0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 .names RST_DLY_3_.BLIF G_141.X2 1 1 -.names N_195_1.BLIF cpu_est_i_3__n.BLIF N_195 +.names a_c_17__n.BLIF a_i_16__n.BLIF N_116_2 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n 0 1 -.names N_19_i.BLIF RST_c.BLIF N_36_0 +.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +.names CLK_OSZI_c.BLIF RST_DLY_7_.C 1 1 -.names N_176_1.BLIF pos_clk_un22_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_1_n +.names a_i_18__n.BLIF a_i_19__n.BLIF N_116_3 11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_16_i.BLIF RST_c.BLIF N_39_0 +.names N_92_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n 11 1 -.names pos_clk_un24_bgack_030_int_1_n.BLIF pos_clk_un27_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_n +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names inst_CLK_000_NE.BLIF CLK_000_NE_i -0 1 -.names N_15_i.BLIF RST_c.BLIF N_40_0 +.names N_116_1.BLIF N_116_2.BLIF N_116_4 11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 .names N_205.BLIF G_139.X1 1 1 -.names N_133_i.BLIF N_135_i.BLIF N_165_1 +.names N_116_4.BLIF N_116_3.BLIF N_116 11 1 -.names inst_CLK_000_PE.BLIF CLK_000_PE_i +.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n 0 1 -.names N_14_i.BLIF RST_c.BLIF N_41_0 +.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 -.names pos_clk_clk_000_n_sync_2_0__n.BLIF CLK_000_N_SYNC_0_.D +.names N_91.BLIF N_91_i +0 1 +.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_165_2 -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i -0 1 -.names N_13_i.BLIF RST_c.BLIF N_42_0 -11 1 .names RST_DLY_2_.BLIF G_139.X2 1 1 -.names N_165_1.BLIF N_165_2.BLIF N_165_3 +.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n 0 1 -.names N_12_i.BLIF RST_c.BLIF N_43_0 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C -1 1 -.names N_165_3.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_165 +.names N_83_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_176_1 +.names N_91_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n 11 1 -.names N_10_i.BLIF RST_c.BLIF N_44_0 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 11 1 -.names N_133.BLIF BERR_i.BLIF N_163_1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n 11 1 -.names pos_clk_un40_bgack_030_int_1_n.BLIF pos_clk_un40_bgack_030_int_1_i_n +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n 0 1 -.names N_9_i.BLIF RST_c.BLIF N_45_0 -11 1 -.names IPL_D0_2_.BLIF G_167.X1 +.names RESET_OUT_0_sqmuxa_1.BLIF G_137.X1 1 1 -.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF RESET_OUT_0_sqmuxa_7_3 +.names N_84_i.BLIF RW_000_i.BLIF N_245_0_1 11 1 -.names DS_000_DMA_0_sqmuxa.BLIF DS_000_DMA_0_sqmuxa_i +.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +.names N_245_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF N_245_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n 0 1 -.names N_8_i.BLIF RST_c.BLIF N_46_0 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 -11 1 -.names DS_000_DMA_0_sqmuxa_i.BLIF pos_clk_ds_000_dma_4_f1_n.BLIF pos_clk_ds_000_dma_4_n -11 1 -.names DS_030_i.BLIF RST_c.BLIF N_50_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +.names RST_DLY_1_.BLIF G_137.X2 1 1 -.names ipl_c_2__n.BLIF G_167.X2 +.names N_94_i.BLIF RST_c.BLIF N_247_i_1 +11 1 +.names N_251.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names N_247_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_6_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_248_i_1 +11 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_0_.X1 1 1 .names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 11 1 -.names AS_000_DMA_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF pos_clk_ds_000_dma_4_f1_0_n -11 1 -.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names DS_030_i.BLIF RST_c.BLIF N_50_0 11 1 .names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 11 1 -.names N_175_i.BLIF N_176_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_0_0_.X2 +1 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_87_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 .names RST_c.BLIF VPA_c_i.BLIF N_56_0 11 1 -.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_135_i_1 +.names RW_000_c.BLIF nEXP_SPACE_D0_i.BLIF N_87_2 11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_80.BLIF N_80_i -0 1 -.names IPL_D0_0_.BLIF G_165.X1 -1 1 -.names N_135_i_1.BLIF sm_amiga_i_6__n.BLIF N_135_i -11 1 -.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_242.BLIF dsack1_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C -1 1 -.names cpu_est_3_reg.BLIF N_199_1.BLIF pos_clk_un27_clk_000_ne_d0_1_n -11 1 -.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names N_80_i.BLIF N_242.BLIF dsack1_int_0_un1_n -11 1 -.names ipl_c_0__n.BLIF G_165.X2 -1 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF pos_clk_un27_clk_000_ne_d0_2_n -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names pos_clk_un27_clk_000_ne_d0_1_n.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF pos_clk_un27_clk_000_ne_d0_3_n -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 -1- 1 --1 1 -.names pos_clk_un27_clk_000_ne_d0_3_n.BLIF cpu_est_2_.BLIF pos_clk_un27_clk_000_ne_d0_n +.names DTACK_c_i.BLIF RST_c.BLIF N_57_0 11 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names N_243.BLIF as_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 -.names IPL_D0_1_.BLIF G_166.X1 -1 1 -.names cpu_est_i_3__n.BLIF inst_CLK_000_PE.BLIF pos_clk_un5_clk_000_pe_1_n +.names N_87_1.BLIF N_87_2.BLIF N_87 11 1 -.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n -11 1 -.names sm_amiga_i_5__n.BLIF N_243.BLIF as_000_int_0_un1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF pos_clk_un5_clk_000_pe_2_n -11 1 -.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +.names N_105.BLIF N_105_i 0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0 11 1 -.names ipl_c_1__n.BLIF G_166.X2 +.names inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X1 1 1 -.names pos_clk_un5_clk_000_pe_1_n.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF pos_clk_un5_clk_000_pe_3_n +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_1_n 11 1 -.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un9_clk_000_n_sync_n -11 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 -1- 1 --1 1 -.names pos_clk_un5_clk_000_pe_3_n.BLIF cpu_est_i_0__n.BLIF pos_clk_un5_clk_000_pe_n -11 1 -.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n -11 1 -.names N_241.BLIF ds_000_enable_0_un3_n +.names N_250.BLIF as_030_000_sync_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_104_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_2_n +11 1 +.names inst_AS_030_000_SYNC.BLIF N_250.BLIF as_030_000_sync_0_un1_n +11 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0 +11 1 +.names CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X2 1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF pos_clk_un9_clk_000_ne_1_n +.names pos_clk_un24_bgack_030_int_i_0_0_1_n.BLIF pos_clk_un24_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un24_bgack_030_int_i_0_0_n 11 1 -.names UDS_000_c.BLIF UDS_000_i -0 1 -.names N_248_i.BLIF N_241.BLIF ds_000_enable_0_un1_n +.names N_105_i.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n 11 1 -.names CYCLE_DMA_1_.BLIF G_161.X1 +.names N_23_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C 1 1 -.names N_154_i.BLIF RST_c.BLIF N_123_i_2 -11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names N_123_i_1.BLIF N_123_i_2.BLIF SM_AMIGA_3_.D -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_0_n -11 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 -1- 1 --1 1 -.names N_220.BLIF G_161.X2 -1 1 -.names N_155_i.BLIF N_156_i.BLIF N_125_i_1 -11 1 -.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_80 -11 1 -.names N_244.BLIF as_030_000_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C -1 1 -.names N_125_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa -11 1 -.names inst_AS_030_000_SYNC.BLIF N_244.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_157_i.BLIF N_158_i.BLIF N_127_i_1 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -1 1 -.names N_159_i.BLIF RST_c.BLIF N_127_i_2 -11 1 -.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +.names sm_amiga_i_i_7__n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_72_0_1 11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12 1- 1 -1 1 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D -1 1 -.names N_127_i_1.BLIF N_127_i_2.BLIF SM_AMIGA_5_.D +.names N_24_i.BLIF RST_c.BLIF N_31_0 11 1 -.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n +.names N_72_0_1.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_72_0 +11 1 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names N_25_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 +1 1 +.names pos_clk_clk_000_n_sync_2_0__n.BLIF AS_030_000_SYNC_i.BLIF pos_clk_un7_clk_000_d0_1_n +11 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un1_n +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names pos_clk_un7_clk_000_d0_1_n.BLIF inst_nEXP_SPACE_D0reg.BLIF pos_clk_un7_clk_000_d0_n +11 1 +.names un1_SM_AMIGA_7_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +.names N_220.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 +1 1 +.names FPU_SENSE_i.BLIF N_116.BLIF un21_fpu_cs_1 +11 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 +1- 1 +-1 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 +1- 1 +-1 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un1_n +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names IPL_D0_0_.BLIF G_165.X1 +1 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF pos_clk_un9_clk_000_ne_3_n +11 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +.names pos_clk_un9_clk_000_ne_1_n.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF pos_clk_un9_clk_000_ne_4_n +11 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names ipl_c_0__n.BLIF G_165.X2 +1 1 +.names pos_clk_un9_clk_000_ne_4_n.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF pos_clk_un9_clk_000_ne_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 +1- 1 +-1 1 +.names cpu_est_i_3__n.BLIF inst_CLK_000_PE.BLIF pos_clk_un5_clk_000_pe_1_n +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF pos_clk_un5_clk_000_pe_2_n +11 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +.names IPL_D0_1_.BLIF G_166.X1 +1 1 +.names pos_clk_un5_clk_000_pe_1_n.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF pos_clk_un5_clk_000_pe_3_n +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names pos_clk_un5_clk_000_pe_3_n.BLIF cpu_est_i_0__n.BLIF pos_clk_un5_clk_000_pe_n +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +1- 1 +-1 1 +.names ipl_c_1__n.BLIF G_166.X2 +1 1 +.names cpu_est_3_reg.BLIF N_199_1.BLIF pos_clk_un27_clk_000_ne_d0_1_n +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size +11 1 +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n +0 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF pos_clk_un27_clk_000_ne_d0_2_n +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names inst_DSACK1_INTreg.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +.names pos_clk_un27_clk_000_ne_d0_1_n.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF pos_clk_un27_clk_000_ne_d0_3_n +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names IPL_D0_2_.BLIF G_167.X1 +1 1 +.names pos_clk_un27_clk_000_ne_d0_3_n.BLIF cpu_est_2_.BLIF pos_clk_un27_clk_000_ne_d0_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names pos_clk_clk_000_n_sync_2_0__n.BLIF CLK_000_N_SYNC_0_.D +1 1 +.names ipl_c_2__n.BLIF G_167.X2 +1 1 +.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF RESET_OUT_0_sqmuxa_7_3 +11 1 +.names N_252.BLIF size_dma_0_1__un3_n +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_252.BLIF size_dma_0_1__un1_n +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names cpu_est_0_0_.BLIF cpu_est_0_.D +1 1 +.names N_165_3.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_165 +11 1 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 .names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D 1 1 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D -1 1 -.names N_160_i.BLIF N_161_i.BLIF N_129_i_1 +.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 11 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_76 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 .names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un1_n 11 1 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D -1 1 -.names N_129_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D 1 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 91458a4..a36a727 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,141 +1,138 @@ #$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Thu Jul 09 18:48:59 2015 +#$ DATE Thu Sep 24 16:20:59 2015 #$ MODULE bus68030 -#$ PINS 75 SIZE_0_ A_30_ SIZE_1_ A_29_ A_28_ A_31_ A_27_ A_26_ IPL_030_2_ A_25_ A_24_ \ -# IPL_2_ A_23_ A_22_ FC_1_ A_21_ AS_030 A_20_ AS_000 A_19_ RW_000 A_18_ DS_030 A_17_ UDS_000 \ -# A_16_ LDS_000 A_15_ A0 A_14_ A1 A_13_ nEXP_SPACE A_12_ BERR A_11_ BG_030 A_10_ BG_000 A_9_ \ -# BGACK_030 A_8_ BGACK_000 A_7_ CLK_030 A_6_ CLK_000 A_5_ CLK_OSZI A_4_ CLK_DIV_OUT A_3_ \ -# CLK_EXP A_2_ FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ \ -# E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -# AMIGA_BUS_ENABLE_HIGH CIIN -#$ NODES 694 N_193 cpu_est_0_1__un3_n N_190 RW_c cpu_est_0_1__un1_n N_189 \ -# cpu_est_0_1__un0_n N_140 fc_c_0__n bgack_030_int_0_un3_n \ -# pos_clk_un29_clk_000_ne_d0_n bgack_030_int_0_un1_n pos_clk_un23_clk_000_ne_d0_n \ -# fc_c_1__n bgack_030_int_0_un0_n inst_BGACK_030_INTreg \ -# pos_clk_un21_clk_000_ne_d0_n un1_amiga_bus_enable_dma_high_i_m4_0__un3_n vcc_n_n \ -# pos_clk_un7_clk_000_pe_n un1_amiga_bus_enable_dma_high_i_m4_0__un1_n \ -# cpu_est_3_reg N_18 AMIGA_BUS_DATA_DIR_c \ -# un1_amiga_bus_enable_dma_high_i_m4_0__un0_n inst_VMA_INTreg N_22 \ -# ds_000_enable_1_sqmuxa_1_i_m4_un3_n inst_RESET_OUTreg \ -# pos_clk_un11_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un1_n gnd_n_n \ -# pos_clk_un9_clk_000_n_sync_n ds_000_enable_1_sqmuxa_1_i_m4_un0_n \ -# un1_amiga_bus_enable_low pos_clk_un14_clk_000_n_sync_n size_dma_0_0__un3_n \ -# un6_as_030 pos_clk_un22_bgack_030_int_n N_6_i size_dma_0_0__un1_n un3_size G_161 \ -# N_48_0 size_dma_0_0__un0_n un4_size N_220 N_3_i size_dma_0_1__un3_n un8_ciin G_159 \ -# N_49_0 size_dma_0_1__un1_n un14_amiga_bus_data_dir pos_clk_un40_bgack_030_int_1_n \ -# pos_clk_un29_bgack_030_int_i_n size_dma_0_1__un0_n un4_as_000 CLK_030_H_0_sqmuxa \ -# pos_clk_un26_bgack_030_int_i_n ipl_030_0_0__un3_n un21_fpu_cs AS_000_DMA_1_sqmuxa \ -# pos_clk_un27_bgack_030_int_0_n ipl_030_0_0__un1_n un22_berr \ -# pos_clk_un24_bgack_030_int_n CLK_030_H_0_sqmuxa_i ipl_030_0_0__un0_n un6_ds_030 \ -# pos_clk_un27_bgack_030_int_n N_7_i ipl_030_0_1__un3_n un6_uds_000 N_176_1 N_47_0 \ -# ipl_030_0_1__un1_n un6_lds_000 N_165 N_133_i ipl_030_0_1__un0_n cpu_est_0_ N_133 \ -# N_176_i ipl_030_0_2__un3_n cpu_est_1_ N_163 N_175_i ipl_030_0_2__un1_n \ -# inst_AS_000_INT N_162 AMIGA_BUS_DATA_DIR_c_0 ipl_030_0_2__un0_n SM_AMIGA_5_ N_164 \ -# pos_clk_ds_000_dma_4_f1_0_n dsack1_int_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW \ -# N_176 N_162_i dsack1_int_0_un1_n inst_AS_030_D0 DS_000_DMA_2_sqmuxa N_163_i \ -# dsack1_int_0_un0_n inst_nEXP_SPACE_D0reg pos_clk_ds_000_dma_4_n N_164_i \ -# as_000_int_0_un3_n inst_DS_030_D0 DS_000_DMA_0_sqmuxa N_165_i as_000_int_0_un1_n \ -# inst_AS_030_000_SYNC pos_clk_ds_000_dma_4_f1_n as_000_int_0_un0_n \ -# inst_BGACK_030_INT_D N_175 pos_clk_un22_bgack_030_int_0_n ds_000_enable_0_un3_n \ -# inst_AS_000_DMA N_47 pos_clk_un9_clk_000_n_sync_i_n ds_000_enable_0_un1_n \ -# inst_DS_000_DMA N_7 clk_000_n_sync_i_10__n ds_000_enable_0_un0_n CYCLE_DMA_0_ \ -# un1_rst_2 pos_clk_un14_clk_000_n_sync_0_n as_030_000_sync_0_un3_n CYCLE_DMA_1_ \ -# pos_clk_un26_bgack_030_int_n N_22_i as_030_000_sync_0_un1_n SIZE_DMA_0_ \ -# pos_clk_un29_bgack_030_int_n N_33_0 as_030_000_sync_0_un0_n SIZE_DMA_1_ N_3 N_18_i \ -# lds_000_int_0_un3_n inst_VPA_D N_6 N_37_0 lds_000_int_0_un1_n inst_UDS_000_INT \ -# un1_amiga_bus_enable_low_i pos_clk_un9_clk_000_ne_i_n lds_000_int_0_un0_n \ -# inst_LDS_000_INT un21_fpu_cs_i pos_clk_un5_clk_000_pe_i_n rw_000_int_0_un3_n \ -# inst_CLK_OUT_PRE_D AS_000_i pos_clk_un7_clk_000_pe_0_n rw_000_int_0_un1_n \ -# inst_DTACK_D0 DS_000_DMA_i pos_clk_un27_clk_000_ne_d0_i_n rw_000_int_0_un0_n \ -# inst_CLK_OUT_PRE_50 pos_clk_un24_bgack_030_int_i_n \ -# pos_clk_un21_clk_000_ne_d0_i_n rw_000_dma_0_un3_n inst_CLK_000_D1 \ -# cycle_dma_i_1__n pos_clk_un23_clk_000_ne_d0_0_n rw_000_dma_0_un1_n \ -# inst_CLK_000_D0 cycle_dma_i_0__n N_136_i rw_000_dma_0_un0_n inst_CLK_000_PE \ -# AS_000_DMA_i N_140_0 uds_000_int_0_un3_n CLK_000_P_SYNC_9_ CLK_EXP_i N_195_i \ -# uds_000_int_0_un1_n inst_CLK_000_NE BERR_i N_196_i uds_000_int_0_un0_n \ -# CLK_000_N_SYNC_11_ RW_000_i N_186_i amiga_bus_enable_dma_low_0_un3_n cpu_est_2_ \ -# DS_000_DMA_0_sqmuxa_i N_188_i amiga_bus_enable_dma_low_0_un1_n IPL_D0_0_ \ -# pos_clk_un40_bgack_030_int_1_i_n N_189_i amiga_bus_enable_dma_low_0_un0_n \ -# IPL_D0_1_ BGACK_030_INT_i N_190_i amiga_bus_enable_dma_high_0_un3_n IPL_D0_2_ \ -# nEXP_SPACE_D0_i N_193_i amiga_bus_enable_dma_high_0_un1_n SM_AMIGA_3_ CLK_000_PE_i \ -# N_191_i amiga_bus_enable_dma_high_0_un0_n inst_CLK_000_NE_D0 CLK_000_NE_i N_192_i \ -# bg_000_0_un3_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_194_i bg_000_0_un1_n \ -# SM_AMIGA_0_ sm_amiga_i_0__n pos_clk_cpu_est_11_0_1__n bg_000_0_un0_n \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH pos_clk_un7_clk_000_d0_i_n N_198_i a0_dma_0_un3_n \ -# inst_DSACK1_INTreg UDS_000_i N_197_i a0_dma_0_un1_n LDS_000_i N_199_i a0_dma_0_un0_n \ -# pos_clk_clk_000_n_sync_2_0__n pos_clk_un11_clk_000_n_sync_i_n \ -# pos_clk_cpu_est_11_0_3__n a_23__n pos_clk_ipl_n CLK_OUT_PRE_D_i N_151_i \ -# pos_clk_un3_ds_030_d0_n DTACK_D0_i N_150_i a_22__n SM_AMIGA_6_ sm_amiga_i_2__n \ -# AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa pos_clk_un29_clk_000_ne_d0_i_n N_135_i a_21__n \ -# RST_DLY_0_ cpu_est_i_0__n N_252_0 RST_DLY_1_ cpu_est_i_3__n N_85_i a_20__n RST_DLY_2_ \ -# cpu_est_i_2__n RST_DLY_3_ cpu_est_i_1__n N_38_0 a_15__n RST_DLY_4_ VPA_D_i \ -# un1_rst_dly_i_m_i_2__n RST_DLY_5_ VMA_INT_i a_14__n RST_DLY_6_ sm_amiga_i_1__n \ -# un1_rst_dly_i_m_i_3__n RST_DLY_7_ RESET_OUT_0_sqmuxa_i a_13__n \ -# pos_clk_un8_bg_030_n N_77_i_i un1_rst_dly_i_m_i_4__n CLK_000_P_SYNC_0_ \ -# un1_rst_dly_i_2__n a_12__n CLK_000_P_SYNC_1_ un1_rst_dly_i_3__n \ -# un1_rst_dly_i_m_i_5__n CLK_000_P_SYNC_2_ un1_rst_dly_i_4__n a_11__n \ -# CLK_000_P_SYNC_3_ un1_rst_dly_i_5__n un1_rst_dly_i_m_i_6__n CLK_000_P_SYNC_4_ \ -# un1_rst_dly_i_6__n a_10__n CLK_000_P_SYNC_5_ un1_rst_dly_i_7__n \ -# un1_rst_dly_i_m_i_7__n CLK_000_P_SYNC_6_ un1_rst_dly_i_8__n a_9__n \ -# CLK_000_P_SYNC_7_ RESET_OUT_i un1_rst_dly_i_m_i_8__n CLK_000_P_SYNC_8_ AS_030_D0_i \ -# a_8__n CLK_000_N_SYNC_0_ AS_030_i un3_as_030_i CLK_000_N_SYNC_1_ A1_i N_76_i a_7__n \ -# CLK_000_N_SYNC_2_ CLK_000_D1_i N_83_i CLK_000_N_SYNC_3_ sm_amiga_i_i_7__n a_6__n \ -# CLK_000_N_SYNC_4_ N_248_i N_84_i CLK_000_N_SYNC_5_ sm_amiga_i_5__n N_115_0 a_5__n \ -# CLK_000_N_SYNC_6_ RW_i N_86_i CLK_000_N_SYNC_7_ CLK_000_D0_i \ -# pos_clk_size_dma_6_0_1__n a_4__n CLK_000_N_SYNC_8_ AS_030_000_SYNC_i N_87_i \ -# CLK_000_N_SYNC_9_ sm_amiga_i_6__n pos_clk_size_dma_6_0_0__n a_3__n \ -# CLK_000_N_SYNC_10_ sm_amiga_i_4__n N_88_i pos_clk_un5_bgack_030_int_d_n \ -# FPU_SENSE_i a_2__n inst_RW_000_INT size_dma_i_0__n N_241_0 inst_RW_000_DMA \ -# size_dma_i_1__n N_242_0 inst_A0_DMA a_i_16__n N_243_0 inst_CLK_030_H a_i_18__n N_93_i \ -# SM_AMIGA_1_ a_i_19__n N_94_i SM_AMIGA_4_ a_i_30__n N_244_0 SM_AMIGA_2_ a_i_31__n \ -# N_245_0 pos_clk_un3_as_030_d0_n a_i_28__n N_246_0 inst_DS_000_ENABLE a_i_29__n \ -# pos_clk_un3_as_030_d0_i_n a_i_26__n pos_clk_un5_bgack_030_int_d_i_n a_i_27__n \ -# N_249_i pos_clk_a0_dma_3_n a_i_24__n N_251_0 a_i_25__n N_71_0 LDS_000_INT_i N_104_i \ -# N_8 DS_030_i N_137_i N_9 UDS_000_INT_i N_10 N_224_i N_160_i N_11 N_225_i N_161_i N_12 \ -# N_226_i N_13 N_159_i N_14 N_157_i N_15 N_158_i N_16 N_91_i N_19 N_90_i N_155_i N_20 \ -# un14_amiga_bus_data_dir_i N_156_i N_21 N_80_i N_23 un6_lds_000_i N_154_i N_24 \ -# un6_uds_000_i N_152_i N_25 un6_ds_030_i N_153_i cpu_est_0_0_ un4_as_000_i N_142_0 \ -# AS_000_INT_i N_141_0 un6_as_030_i N_138_0 AMIGA_BUS_ENABLE_DMA_LOW_i N_132_i \ -# DS_030_D0_i un1_as_030_i AS_030_c pos_clk_un11_ds_030_d0_i_n A0_c_i AS_000_c \ -# size_c_i_1__n N_25_i RW_000_c N_32_0 N_24_i DS_030_c N_31_0 N_23_i UDS_000_c N_30_0 \ -# ipl_c_i_2__n LDS_000_c N_54_0 ipl_c_i_1__n size_c_0__n N_53_0 ipl_c_i_0__n \ -# size_c_1__n N_52_0 DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_8_i \ -# N_46_0 N_9_i N_45_0 N_10_i SM_AMIGA_i_7_ N_44_0 N_115 N_12_i pos_clk_size_dma_6_0__n \ -# N_43_0 pos_clk_size_dma_6_1__n N_13_i G_165 N_42_0 G_166 N_14_i G_167 N_41_0 \ -# un6_uds_000_1 N_15_i N_241 N_40_0 N_242 N_16_i N_243 N_39_0 N_244 N_19_i N_245 N_36_0 \ -# N_246 N_20_i N_78 N_35_0 N_80 N_21_i N_89 N_34_0 N_90 a_c_16__n BG_030_c_i N_91 \ -# pos_clk_un6_bg_030_i_n N_98 a_c_17__n pos_clk_un8_bg_030_0_n N_99 N_251_0_1 N_249 \ -# a_c_18__n N_121_i_1 N_248 pos_clk_cpu_est_11_0_1_3__n N_135 a_c_19__n \ -# pos_clk_cpu_est_11_0_1_1__n N_136 pos_clk_cpu_est_11_0_2_1__n \ -# pos_clk_un7_clk_000_d0_n N_131_i_1 un22_berr_1 N_131_i_2 N_152 N_131_i_3 N_153 \ -# pos_clk_un11_ds_030_d0_i_1_n N_154 un8_ciin_1 N_155 un8_ciin_2 N_141 un8_ciin_3 N_156 \ -# un8_ciin_4 N_157 a_c_24__n un8_ciin_5 N_138 un8_ciin_6 N_158 a_c_25__n un8_ciin_7 N_159 \ -# un8_ciin_8 N_160 a_c_26__n N_116_1 N_142 N_116_2 N_161 a_c_27__n N_116_3 N_132 N_116_4 \ -# N_104 a_c_28__n un22_berr_1_0 N_76 un21_fpu_cs_1 N_71 a_c_29__n N_123_i_1 N_251 \ -# N_123_i_2 N_93 a_c_30__n N_125_i_1 N_94 N_127_i_1 N_88 a_c_31__n N_127_i_2 N_87 \ -# N_129_i_1 N_86 A0_c pos_clk_un6_bg_030_1_n N_84 pos_clk_un7_clk_000_d0_1_n N_83 A1_c \ -# RESET_OUT_0_sqmuxa_7_1 N_116 RESET_OUT_0_sqmuxa_7_2 G_149 nEXP_SPACE_c \ -# RESET_OUT_0_sqmuxa_7_3 G_147 RESET_OUT_0_sqmuxa_5_1 N_213 BERR_c N_135_i_1 G_145 \ -# pos_clk_un27_clk_000_ne_d0_1_n N_211 BG_030_c pos_clk_un27_clk_000_ne_d0_2_n G_143 \ -# pos_clk_un27_clk_000_ne_d0_3_n N_209 BG_000DFFreg pos_clk_un5_clk_000_pe_1_n G_141 \ -# pos_clk_un5_clk_000_pe_2_n G_139 pos_clk_un5_clk_000_pe_3_n N_205 BGACK_000_c \ -# pos_clk_un9_clk_000_ne_1_n G_137 pos_clk_un9_clk_000_ne_2_n RESET_OUT_0_sqmuxa_1 \ -# pos_clk_un9_clk_000_ne_3_n RESET_OUT_0_sqmuxa pos_clk_un9_clk_000_ne_4_n \ -# RESET_OUT_0_sqmuxa_7 N_196_1 RESET_OUT_0_sqmuxa_5 CLK_OSZI_c N_195_1 \ -# un1_rst_dly_i_m_8__n pos_clk_un24_bgack_030_int_1_n un1_rst_dly_i_m_7__n N_165_1 \ -# un1_rst_dly_i_m_6__n CLK_EXP_c N_165_2 un1_rst_dly_i_m_5__n N_165_3 \ -# un1_rst_dly_i_m_4__n N_163_1 un1_rst_dly_i_m_3__n FPU_SENSE_c N_162_1 \ -# un1_rst_dly_i_m_2__n N_176_1_0 N_38 IPL_030DFF_0_reg DS_000_DMA_2_sqmuxa_1 N_85 \ -# N_119_i_1 pos_clk_RST_DLY_5_iv_0_x2_0_ IPL_030DFF_1_reg N_115_0_1 N_252 \ -# pos_clk_ipl_1_n N_97 IPL_030DFF_2_reg as_000_dma_0_un3_n \ -# pos_clk_un27_clk_000_ne_d0_n as_000_dma_0_un1_n N_199_1 ipl_c_0__n \ -# as_000_dma_0_un0_n pos_clk_un5_clk_000_pe_n ds_000_dma_0_un3_n \ -# pos_clk_un9_clk_000_ne_n ipl_c_1__n ds_000_dma_0_un1_n N_150 ds_000_dma_0_un0_n \ -# N_151 ipl_c_2__n vma_int_0_un3_n N_199 vma_int_0_un1_n N_196 vma_int_0_un0_n N_195 \ -# DTACK_c sm_amiga_srsts_i_0_m2_1__un3_n N_188 sm_amiga_srsts_i_0_m2_1__un1_n \ -# pos_clk_cpu_est_11_3__n sm_amiga_srsts_i_0_m2_1__un0_n N_197 cpu_est_0_3__un3_n \ -# N_198 VPA_c cpu_est_0_3__un1_n pos_clk_cpu_est_11_1__n cpu_est_0_3__un0_n N_194 \ -# cpu_est_0_2__un3_n N_192 RST_c cpu_est_0_2__un1_n N_191 cpu_est_0_2__un0_n +#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \ +# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 \ +# A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ \ +# BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT \ +# IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST \ +# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ +#$ NODES 695 N_159 N_21_i bgack_030_int_0_un0_n N_157 N_34_0 as_030_000_sync_0_un3_n \ +# N_158 N_20_i as_030_000_sync_0_un1_n un1_rst_dly_i_m_1__n N_35_0 \ +# as_030_000_sync_0_un0_n N_138 N_16_i ds_000_enable_0_un3_n N_88 N_39_0 \ +# ds_000_enable_0_un1_n inst_BGACK_030_INTreg N_256 N_13_i ds_000_enable_0_un0_n \ +# vcc_n_n N_89 N_42_0 a0_dma_0_un3_n cpu_est_3_reg N_91 N_12_i a0_dma_0_un1_n \ +# inst_VMA_INTreg N_92 N_43_0 a0_dma_0_un0_n inst_RESET_OUTreg pos_clk_a0_dma_3_n \ +# N_8_i size_dma_0_1__un3_n gnd_n_n N_96 N_46_0 size_dma_0_1__un1_n \ +# un1_amiga_bus_enable_low N_72 N_76_i size_dma_0_1__un0_n un6_as_030 N_97 N_72_0 \ +# size_dma_0_0__un3_n un3_size N_116 UDS_000_c_i size_dma_0_0__un1_n un4_size N_104 \ +# LDS_000_c_i size_dma_0_0__un0_n un5_ciin N_76 N_256_i \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un8_ciin pos_clk_size_dma_6_1__n \ +# pos_clk_un5_bgack_030_int_d_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n \ +# un4_as_000 pos_clk_size_dma_6_0__n pos_clk_un24_bgack_030_int_i_0_0_n \ +# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n un1_SM_AMIGA_7 N_250 N_104_i \ +# cpu_est_0_1__un3_n un21_fpu_cs pos_clk_un6_bgack_000_n N_252_0 cpu_est_0_1__un1_n \ +# un22_berr N_251 N_251_0 cpu_est_0_1__un0_n un6_ds_030 N_252 \ +# pos_clk_un6_bgack_000_0_n cpu_est_0_2__un3_n un6_uds_000 \ +# pos_clk_un5_bgack_030_int_d_n N_97_i cpu_est_0_2__un1_n un6_lds_000 \ +# pos_clk_un24_bgack_030_int_i_0_x2 N_96_i cpu_est_0_2__un0_n cpu_est_0_ \ +# DS_000_ENABLE_1_sqmuxa_1 N_250_0 cpu_est_0_3__un3_n cpu_est_1_ un22_berr_1 N_89_i \ +# cpu_est_0_3__un1_n inst_AS_000_INT N_8 pos_clk_size_dma_6_0_0__n \ +# cpu_est_0_3__un0_n SM_AMIGA_5_ N_12 N_88_i ipl_030_0_0__un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW N_13 pos_clk_size_dma_6_0_1__n ipl_030_0_0__un1_n \ +# inst_AS_030_D0 N_16 N_138_0 ipl_030_0_0__un0_n inst_nEXP_SPACE_D0reg N_20 \ +# un1_rst_dly_i_m_i_1__n ipl_030_0_1__un3_n inst_DS_030_D0 N_21 ipl_030_0_1__un1_n \ +# inst_AS_030_000_SYNC N_11 N_157_i ipl_030_0_1__un0_n inst_BGACK_030_INT_D \ +# un1_amiga_bus_enable_low_i N_158_i ipl_030_0_2__un3_n inst_AS_000_DMA \ +# un21_fpu_cs_i N_159_i ipl_030_0_2__un1_n inst_DS_000_DMA BGACK_030_INT_i \ +# ipl_030_0_2__un0_n CYCLE_DMA_0_ AMIGA_BUS_ENABLE_DMA_LOW_i N_257_0 \ +# dsack1_int_0_un3_n CYCLE_DMA_1_ AS_030_i un1_as_000_i dsack1_int_0_un1_n \ +# SIZE_DMA_0_ AS_000_INT_i N_93_i dsack1_int_0_un0_n SIZE_DMA_1_ N_105_i \ +# as_000_int_0_un3_n inst_VPA_D N_91_i N_87_i as_000_int_0_un1_n inst_UDS_000_INT \ +# N_92_i N_86_i as_000_int_0_un0_n inst_LDS_000_INT a_i_19__n AMIGA_BUS_DATA_DIR_c_0 \ +# lds_000_int_0_un3_n inst_CLK_OUT_PRE_D a_i_18__n un1_rst_dly_i_m_i_2__n \ +# lds_000_int_0_un1_n inst_DTACK_D0 a_i_16__n lds_000_int_0_un0_n \ +# inst_CLK_OUT_PRE_50 size_dma_i_1__n un1_rst_dly_i_m_i_3__n rw_000_int_0_un3_n \ +# inst_CLK_000_D1 size_dma_i_0__n rw_000_int_0_un1_n inst_CLK_000_D0 FPU_SENSE_i \ +# un1_rst_dly_i_m_i_4__n rw_000_int_0_un0_n inst_CLK_000_PE CLK_000_D1_i \ +# uds_000_int_0_un3_n CLK_000_P_SYNC_9_ CLK_000_D0_i un1_rst_dly_i_m_i_5__n \ +# uds_000_int_0_un1_n inst_CLK_000_NE AS_030_000_SYNC_i uds_000_int_0_un0_n \ +# CLK_000_N_SYNC_11_ AS_030_D0_i un1_rst_dly_i_m_i_6__n vma_int_0_un3_n cpu_est_2_ \ +# sm_amiga_i_i_7__n vma_int_0_un1_n IPL_D0_0_ AS_000_i un1_rst_dly_i_m_i_7__n \ +# vma_int_0_un0_n IPL_D0_1_ CLK_000_PE_i bg_000_0_un3_n IPL_D0_2_ nEXP_SPACE_D0_i \ +# un1_rst_dly_i_m_i_8__n bg_000_0_un1_n SM_AMIGA_3_ A1_i bg_000_0_un0_n \ +# inst_CLK_000_NE_D0 sm_amiga_i_6__n un3_as_030_i ds_000_dma_0_un3_n \ +# pos_clk_un6_bg_030_n BERR_i un1_as_030_i ds_000_dma_0_un1_n SM_AMIGA_0_ \ +# sm_amiga_i_5__n clk_000_n_sync_i_10__n ds_000_dma_0_un0_n \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH RESET_OUT_0_sqmuxa_i \ +# pos_clk_un9_clk_000_n_sync_i_n as_000_dma_0_un3_n inst_DSACK1_INTreg \ +# un1_rst_dly_i_1__n pos_clk_un14_clk_000_n_sync_0_n as_000_dma_0_un1_n RESET_OUT_i \ +# CLK_EXP_c_i as_000_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n RW_000_i N_244_0 \ +# a_15__n pos_clk_ipl_n un1_rst_dly_i_2__n N_83_i pos_clk_un3_ds_030_d0_n \ +# un1_rst_dly_i_3__n N_115_0 a_14__n SM_AMIGA_6_ un1_rst_dly_i_4__n N_84_i RST_DLY_0_ \ +# un1_rst_dly_i_5__n N_245_0 a_13__n RST_DLY_1_ un1_rst_dly_i_6__n N_85_i RST_DLY_2_ \ +# un1_rst_dly_i_7__n pos_clk_ds_000_dma_4_0_n a_12__n RST_DLY_3_ un1_rst_dly_i_8__n \ +# N_94_i RST_DLY_4_ CLK_OUT_PRE_D_i a_11__n RST_DLY_5_ \ +# pos_clk_un11_clk_000_n_sync_i_n RST_DLY_6_ CLK_030_H_i a_10__n RST_DLY_7_ \ +# AS_000_DMA_i N_73_0 pos_clk_un8_bg_030_n VMA_INT_i a_9__n CLK_000_P_SYNC_0_ VPA_D_i \ +# N_160_i CLK_000_P_SYNC_1_ cpu_est_i_0__n N_161_i a_8__n CLK_000_P_SYNC_2_ \ +# cpu_est_i_1__n CLK_000_P_SYNC_3_ cpu_est_i_3__n N_155_i a_7__n CLK_000_P_SYNC_4_ \ +# a_i_24__n N_156_i CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_d0_i_n a_6__n \ +# CLK_000_P_SYNC_6_ sm_amiga_i_0__n N_154_i CLK_000_P_SYNC_7_ sm_amiga_i_3__n N_152_i \ +# a_5__n CLK_000_P_SYNC_8_ CLK_000_NE_i N_153_i CLK_000_N_SYNC_0_ cpu_est_i_2__n \ +# a_4__n CLK_000_N_SYNC_1_ sm_amiga_i_1__n N_150_i CLK_000_N_SYNC_2_ sm_amiga_i_4__n \ +# N_151_i a_3__n CLK_000_N_SYNC_3_ sm_amiga_i_2__n CLK_000_N_SYNC_4_ \ +# pos_clk_un29_clk_000_ne_d0_i_n N_149_i a_2__n CLK_000_N_SYNC_5_ \ +# DSACK1_INT_0_sqmuxa_i N_147_i CLK_000_N_SYNC_6_ RW_i N_148_i CLK_000_N_SYNC_7_ \ +# un5_ciin_i CLK_000_N_SYNC_8_ DTACK_D0_i N_164_i CLK_000_N_SYNC_9_ a_i_31__n N_165_i \ +# CLK_000_N_SYNC_10_ a_i_29__n N_163_i inst_RW_000_INT a_i_30__n N_199_i \ +# inst_RW_000_DMA a_i_27__n pos_clk_cpu_est_11_0_3__n pos_clk_un7_clk_000_pe_n \ +# a_i_28__n N_197_i inst_A0_DMA a_i_25__n N_198_i DS_000_ENABLE_1_sqmuxa a_i_26__n \ +# N_194_i inst_CLK_030_H UDS_000_INT_i pos_clk_cpu_est_11_0_1__n SM_AMIGA_1_ \ +# LDS_000_INT_i N_192_i SM_AMIGA_4_ DS_030_i N_135_i SM_AMIGA_2_ N_224_i N_162_i \ +# inst_DS_000_ENABLE N_225_i N_191_i AS_000_INT_1_sqmuxa N_226_i N_193_i \ +# DSACK1_INT_1_sqmuxa N_190_i pos_clk_ds_000_dma_4_n N_189_i N_3 \ +# DS_000_ENABLE_1_sqmuxa_i N_188_i un6_lds_000_i N_195_i un6_uds_000_i N_196_i N_6 \ +# un6_ds_030_i N_186_i N_9 DS_000_DMA_i N_143_0 N_10 un4_as_000_i N_142_0 N_14 un8_ciin_i \ +# N_141_0 N_15 un6_as_030_i N_140_0 N_17 DS_030_D0_i N_139_0 N_19 AS_030_c N_166_i N_22 \ +# N_137_i N_23 AS_000_c N_136_i N_24 N_133_i N_25 RW_000_c N_132_i cpu_est_0_0_ N_146_i \ +# DS_030_c N_144_i UDS_000_c un1_SM_AMIGA_7_i pos_clk_un21_clk_000_ne_d0_i_n \ +# LDS_000_c pos_clk_un27_clk_000_ne_d0_i_n pos_clk_un23_clk_000_ne_d0_0_n \ +# size_c_0__n pos_clk_un5_clk_000_pe_i_n pos_clk_un9_clk_000_ne_i_n size_c_1__n \ +# pos_clk_un7_clk_000_pe_0_n pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i \ +# N_32_0 N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n \ +# N_52_0 DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i SM_AMIGA_i_7_ N_55_0 N_115 N_50_0 \ +# pos_clk_cpu_est_11_1__n N_3_i pos_clk_cpu_est_11_3__n N_49_0 N_220 N_6_i G_165 N_48_0 \ +# G_166 N_9_i G_167 N_45_0 un6_uds_000_1 N_10_i pos_clk_un24_bgack_030_int_i_0_n \ +# a_c_16__n N_44_0 N_244 N_14_i N_245 a_c_17__n N_41_0 N_15_i N_80 a_c_18__n N_40_0 N_90 \ +# N_17_i N_100 a_c_19__n N_38_0 N_105 N_19_i pos_clk_un11_clk_000_n_sync_n a_c_20__n \ +# N_36_0 pos_clk_CYCLE_DMA_5_1_i_x2 N_22_i pos_clk_CYCLE_DMA_5_0_i_x2 a_c_21__n \ +# N_33_0 N_135 BG_030_c_i N_133 a_c_22__n pos_clk_un6_bg_030_i_n N_190 \ +# pos_clk_un8_bg_030_0_n N_188 a_c_23__n N_127_i_1 N_189 N_127_i_2 N_136 a_c_24__n \ +# pos_clk_un11_ds_030_d0_i_1_n pos_clk_un7_clk_000_d0_n N_135_i_1 \ +# pos_clk_un29_clk_000_ne_d0_n a_c_25__n pos_clk_cpu_est_11_0_1_1__n \ +# DSACK1_INT_0_sqmuxa pos_clk_cpu_est_11_0_2_1__n pos_clk_un21_clk_000_ne_d0_n \ +# a_c_26__n pos_clk_cpu_est_11_0_1_3__n pos_clk_un5_clk_000_pe_n N_195_1 \ +# pos_clk_un9_clk_000_ne_n a_c_27__n N_196_1 pos_clk_un23_clk_000_ne_d0_n N_131_i_1 \ +# pos_clk_un27_clk_000_ne_d0_n a_c_28__n N_131_i_2 pos_clk_un14_clk_000_n_sync_n \ +# N_131_i_3 N_144 a_c_29__n N_119_i_1 N_146 N_119_i_2 N_143 a_c_30__n N_121_i_1 N_147 \ +# N_123_i_1 N_139 a_c_31__n N_123_i_2 N_148 N_125_i_1 N_149 A0_c N_129_i_1 N_150 N_162_1 \ +# N_140 A1_c N_163_1 N_151 N_165_1 N_152 nEXP_SPACE_c N_165_2 N_153 N_165_3 N_154 BERR_c \ +# un5_ciin_1 N_155 un5_ciin_2 N_141 BG_030_c un5_ciin_3 N_156 un5_ciin_4 N_160 \ +# BG_000DFFreg un5_ciin_5 N_142 un5_ciin_6 N_161 un5_ciin_7 N_164 BGACK_000_c un5_ciin_8 \ +# N_166 un5_ciin_9 N_132 un5_ciin_10 N_191 un5_ciin_11 N_192 pos_clk_un9_clk_000_ne_1_n \ +# N_193 CLK_OSZI_c pos_clk_un9_clk_000_ne_2_n N_194 pos_clk_un9_clk_000_ne_3_n N_197 \ +# pos_clk_un9_clk_000_ne_4_n N_198 CLK_EXP_c pos_clk_un5_clk_000_pe_1_n N_195 \ +# pos_clk_un5_clk_000_pe_2_n N_196 pos_clk_un5_clk_000_pe_3_n N_162 FPU_SENSE_c \ +# pos_clk_un27_clk_000_ne_d0_1_n N_199 pos_clk_un27_clk_000_ne_d0_2_n N_199_1 \ +# IPL_030DFF_0_reg pos_clk_un27_clk_000_ne_d0_3_n N_163 RESET_OUT_0_sqmuxa_7_1 N_165 \ +# IPL_030DFF_1_reg RESET_OUT_0_sqmuxa_7_2 N_73 RESET_OUT_0_sqmuxa_7_3 N_94 \ +# IPL_030DFF_2_reg RESET_OUT_0_sqmuxa_5_1 N_85 N_87_1 N_84 ipl_c_0__n N_87_2 N_83 \ +# pos_clk_un24_bgack_030_int_i_0_0_1_n pos_clk_un9_clk_000_n_sync_n ipl_c_1__n \ +# pos_clk_un24_bgack_030_int_i_0_0_2_n G_149 N_72_0_1 G_147 ipl_c_2__n \ +# pos_clk_un7_clk_000_d0_1_n N_213 un21_fpu_cs_1 G_145 un22_berr_1_0 N_211 DTACK_c \ +# N_116_1 G_143 N_116_2 N_209 N_116_3 G_141 N_116_4 G_139 VPA_c pos_clk_un6_bg_030_1_n \ +# N_205 N_115_0_1 G_137 N_245_0_1 RESET_OUT_0_sqmuxa_1 RST_c N_247_i_1 \ +# RESET_OUT_0_sqmuxa N_248_i_1 RESET_OUT_0_sqmuxa_7 N_249_i_1 RESET_OUT_0_sqmuxa_5 \ +# RW_c pos_clk_ipl_1_n un1_rst_dly_i_m_8__n amiga_bus_enable_dma_high_0_un3_n \ +# un1_rst_dly_i_m_7__n fc_c_0__n amiga_bus_enable_dma_high_0_un1_n \ +# un1_rst_dly_i_m_6__n amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n \ +# fc_c_1__n amiga_bus_enable_dma_low_0_un3_n un1_rst_dly_i_m_4__n \ +# amiga_bus_enable_dma_low_0_un1_n un1_rst_dly_i_m_3__n \ +# amiga_bus_enable_dma_low_0_un0_n un1_rst_dly_i_m_2__n AMIGA_BUS_DATA_DIR_c \ +# rw_000_dma_0_un3_n N_86 rw_000_dma_0_un1_n N_93 rw_000_dma_0_un0_n N_87 \ +# bgack_030_int_0_un3_n G_135 bgack_030_int_0_un1_n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ @@ -145,374 +142,366 @@ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \ A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \ A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF \ -LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_193.BLIF \ -cpu_est_0_1__un3_n.BLIF N_190.BLIF RW_c.BLIF cpu_est_0_1__un1_n.BLIF \ -N_189.BLIF cpu_est_0_1__un0_n.BLIF N_140.BLIF fc_c_0__n.BLIF \ -bgack_030_int_0_un3_n.BLIF pos_clk_un29_clk_000_ne_d0_n.BLIF \ -bgack_030_int_0_un1_n.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF fc_c_1__n.BLIF \ -bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.BLIF \ -pos_clk_un21_clk_000_ne_d0_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un3_n.BLIF vcc_n_n.BLIF \ -pos_clk_un7_clk_000_pe_n.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un1_n.BLIF \ -cpu_est_3_reg.BLIF N_18.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un0_n.BLIF inst_VMA_INTreg.BLIF \ -N_22.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n.BLIF inst_RESET_OUTreg.BLIF \ -pos_clk_un11_clk_000_n_sync_n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un1_n.BLIF \ -gnd_n_n.BLIF pos_clk_un9_clk_000_n_sync_n.BLIF \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n.BLIF un1_amiga_bus_enable_low.BLIF \ -pos_clk_un14_clk_000_n_sync_n.BLIF size_dma_0_0__un3_n.BLIF un6_as_030.BLIF \ -pos_clk_un22_bgack_030_int_n.BLIF N_6_i.BLIF size_dma_0_0__un1_n.BLIF \ -un3_size.BLIF G_161.BLIF N_48_0.BLIF size_dma_0_0__un0_n.BLIF un4_size.BLIF \ -N_220.BLIF N_3_i.BLIF size_dma_0_1__un3_n.BLIF un8_ciin.BLIF G_159.BLIF \ -N_49_0.BLIF size_dma_0_1__un1_n.BLIF un14_amiga_bus_data_dir.BLIF \ -pos_clk_un40_bgack_030_int_1_n.BLIF pos_clk_un29_bgack_030_int_i_n.BLIF \ -size_dma_0_1__un0_n.BLIF un4_as_000.BLIF CLK_030_H_0_sqmuxa.BLIF \ -pos_clk_un26_bgack_030_int_i_n.BLIF ipl_030_0_0__un3_n.BLIF un21_fpu_cs.BLIF \ -AS_000_DMA_1_sqmuxa.BLIF pos_clk_un27_bgack_030_int_0_n.BLIF \ -ipl_030_0_0__un1_n.BLIF un22_berr.BLIF pos_clk_un24_bgack_030_int_n.BLIF \ -CLK_030_H_0_sqmuxa_i.BLIF ipl_030_0_0__un0_n.BLIF un6_ds_030.BLIF \ -pos_clk_un27_bgack_030_int_n.BLIF N_7_i.BLIF ipl_030_0_1__un3_n.BLIF \ -un6_uds_000.BLIF N_176_1.BLIF N_47_0.BLIF ipl_030_0_1__un1_n.BLIF \ -un6_lds_000.BLIF N_165.BLIF N_133_i.BLIF ipl_030_0_1__un0_n.BLIF \ -cpu_est_0_.BLIF N_133.BLIF N_176_i.BLIF ipl_030_0_2__un3_n.BLIF \ -cpu_est_1_.BLIF N_163.BLIF N_175_i.BLIF ipl_030_0_2__un1_n.BLIF \ -inst_AS_000_INT.BLIF N_162.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ -ipl_030_0_2__un0_n.BLIF SM_AMIGA_5_.BLIF N_164.BLIF \ -pos_clk_ds_000_dma_4_f1_0_n.BLIF dsack1_int_0_un3_n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_176.BLIF N_162_i.BLIF \ -dsack1_int_0_un1_n.BLIF inst_AS_030_D0.BLIF DS_000_DMA_2_sqmuxa.BLIF \ -N_163_i.BLIF dsack1_int_0_un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF \ -pos_clk_ds_000_dma_4_n.BLIF N_164_i.BLIF as_000_int_0_un3_n.BLIF \ -inst_DS_030_D0.BLIF DS_000_DMA_0_sqmuxa.BLIF N_165_i.BLIF \ -as_000_int_0_un1_n.BLIF inst_AS_030_000_SYNC.BLIF \ -pos_clk_ds_000_dma_4_f1_n.BLIF as_000_int_0_un0_n.BLIF \ -inst_BGACK_030_INT_D.BLIF N_175.BLIF pos_clk_un22_bgack_030_int_0_n.BLIF \ -ds_000_enable_0_un3_n.BLIF inst_AS_000_DMA.BLIF N_47.BLIF \ -pos_clk_un9_clk_000_n_sync_i_n.BLIF ds_000_enable_0_un1_n.BLIF \ -inst_DS_000_DMA.BLIF N_7.BLIF clk_000_n_sync_i_10__n.BLIF \ -ds_000_enable_0_un0_n.BLIF CYCLE_DMA_0_.BLIF un1_rst_2.BLIF \ -pos_clk_un14_clk_000_n_sync_0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -CYCLE_DMA_1_.BLIF pos_clk_un26_bgack_030_int_n.BLIF N_22_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF SIZE_DMA_0_.BLIF \ -pos_clk_un29_bgack_030_int_n.BLIF N_33_0.BLIF as_030_000_sync_0_un0_n.BLIF \ -SIZE_DMA_1_.BLIF N_3.BLIF N_18_i.BLIF lds_000_int_0_un3_n.BLIF inst_VPA_D.BLIF \ -N_6.BLIF N_37_0.BLIF lds_000_int_0_un1_n.BLIF inst_UDS_000_INT.BLIF \ -un1_amiga_bus_enable_low_i.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ -lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.BLIF un21_fpu_cs_i.BLIF \ -pos_clk_un5_clk_000_pe_i_n.BLIF rw_000_int_0_un3_n.BLIF \ -inst_CLK_OUT_PRE_D.BLIF AS_000_i.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF \ -rw_000_int_0_un1_n.BLIF inst_DTACK_D0.BLIF DS_000_DMA_i.BLIF \ -pos_clk_un27_clk_000_ne_d0_i_n.BLIF rw_000_int_0_un0_n.BLIF \ -inst_CLK_OUT_PRE_50.BLIF pos_clk_un24_bgack_030_int_i_n.BLIF \ -pos_clk_un21_clk_000_ne_d0_i_n.BLIF rw_000_dma_0_un3_n.BLIF \ -inst_CLK_000_D1.BLIF cycle_dma_i_1__n.BLIF pos_clk_un23_clk_000_ne_d0_0_n.BLIF \ -rw_000_dma_0_un1_n.BLIF inst_CLK_000_D0.BLIF cycle_dma_i_0__n.BLIF \ -N_136_i.BLIF rw_000_dma_0_un0_n.BLIF inst_CLK_000_PE.BLIF AS_000_DMA_i.BLIF \ -N_140_0.BLIF uds_000_int_0_un3_n.BLIF CLK_000_P_SYNC_9_.BLIF CLK_EXP_i.BLIF \ -N_195_i.BLIF uds_000_int_0_un1_n.BLIF inst_CLK_000_NE.BLIF BERR_i.BLIF \ -N_196_i.BLIF uds_000_int_0_un0_n.BLIF CLK_000_N_SYNC_11_.BLIF RW_000_i.BLIF \ -N_186_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF cpu_est_2_.BLIF \ -DS_000_DMA_0_sqmuxa_i.BLIF N_188_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ -IPL_D0_0_.BLIF pos_clk_un40_bgack_030_int_1_i_n.BLIF N_189_i.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF IPL_D0_1_.BLIF BGACK_030_INT_i.BLIF \ -N_190_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF IPL_D0_2_.BLIF \ -nEXP_SPACE_D0_i.BLIF N_193_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ -SM_AMIGA_3_.BLIF CLK_000_PE_i.BLIF N_191_i.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF inst_CLK_000_NE_D0.BLIF \ -CLK_000_NE_i.BLIF N_192_i.BLIF bg_000_0_un3_n.BLIF pos_clk_un6_bg_030_n.BLIF \ -sm_amiga_i_3__n.BLIF N_194_i.BLIF bg_000_0_un1_n.BLIF SM_AMIGA_0_.BLIF \ -sm_amiga_i_0__n.BLIF pos_clk_cpu_est_11_0_1__n.BLIF bg_000_0_un0_n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF \ -N_198_i.BLIF a0_dma_0_un3_n.BLIF inst_DSACK1_INTreg.BLIF UDS_000_i.BLIF \ -N_197_i.BLIF a0_dma_0_un1_n.BLIF LDS_000_i.BLIF N_199_i.BLIF \ -a0_dma_0_un0_n.BLIF pos_clk_clk_000_n_sync_2_0__n.BLIF \ -pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \ -a_23__n.BLIF pos_clk_ipl_n.BLIF CLK_OUT_PRE_D_i.BLIF N_151_i.BLIF \ -pos_clk_un3_ds_030_d0_n.BLIF DTACK_D0_i.BLIF N_150_i.BLIF a_22__n.BLIF \ -SM_AMIGA_6_.BLIF sm_amiga_i_2__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF \ -pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_135_i.BLIF a_21__n.BLIF RST_DLY_0_.BLIF \ -cpu_est_i_0__n.BLIF N_252_0.BLIF RST_DLY_1_.BLIF cpu_est_i_3__n.BLIF \ -N_85_i.BLIF a_20__n.BLIF RST_DLY_2_.BLIF cpu_est_i_2__n.BLIF RST_DLY_3_.BLIF \ -cpu_est_i_1__n.BLIF N_38_0.BLIF a_15__n.BLIF RST_DLY_4_.BLIF VPA_D_i.BLIF \ -un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_5_.BLIF VMA_INT_i.BLIF a_14__n.BLIF \ -RST_DLY_6_.BLIF sm_amiga_i_1__n.BLIF un1_rst_dly_i_m_i_3__n.BLIF \ -RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa_i.BLIF a_13__n.BLIF \ -pos_clk_un8_bg_030_n.BLIF N_77_i_i.BLIF un1_rst_dly_i_m_i_4__n.BLIF \ -CLK_000_P_SYNC_0_.BLIF un1_rst_dly_i_2__n.BLIF a_12__n.BLIF \ -CLK_000_P_SYNC_1_.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_i_5__n.BLIF \ -CLK_000_P_SYNC_2_.BLIF un1_rst_dly_i_4__n.BLIF a_11__n.BLIF \ -CLK_000_P_SYNC_3_.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_i_6__n.BLIF \ -CLK_000_P_SYNC_4_.BLIF un1_rst_dly_i_6__n.BLIF a_10__n.BLIF \ -CLK_000_P_SYNC_5_.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_i_7__n.BLIF \ -CLK_000_P_SYNC_6_.BLIF un1_rst_dly_i_8__n.BLIF a_9__n.BLIF \ -CLK_000_P_SYNC_7_.BLIF RESET_OUT_i.BLIF un1_rst_dly_i_m_i_8__n.BLIF \ -CLK_000_P_SYNC_8_.BLIF AS_030_D0_i.BLIF a_8__n.BLIF CLK_000_N_SYNC_0_.BLIF \ -AS_030_i.BLIF un3_as_030_i.BLIF CLK_000_N_SYNC_1_.BLIF A1_i.BLIF N_76_i.BLIF \ -a_7__n.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_D1_i.BLIF N_83_i.BLIF \ -CLK_000_N_SYNC_3_.BLIF sm_amiga_i_i_7__n.BLIF a_6__n.BLIF \ -CLK_000_N_SYNC_4_.BLIF N_248_i.BLIF N_84_i.BLIF CLK_000_N_SYNC_5_.BLIF \ -sm_amiga_i_5__n.BLIF N_115_0.BLIF a_5__n.BLIF CLK_000_N_SYNC_6_.BLIF RW_i.BLIF \ -N_86_i.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_D0_i.BLIF \ -pos_clk_size_dma_6_0_1__n.BLIF a_4__n.BLIF CLK_000_N_SYNC_8_.BLIF \ -AS_030_000_SYNC_i.BLIF N_87_i.BLIF CLK_000_N_SYNC_9_.BLIF sm_amiga_i_6__n.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF a_3__n.BLIF CLK_000_N_SYNC_10_.BLIF \ -sm_amiga_i_4__n.BLIF N_88_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -FPU_SENSE_i.BLIF a_2__n.BLIF inst_RW_000_INT.BLIF size_dma_i_0__n.BLIF \ -N_241_0.BLIF inst_RW_000_DMA.BLIF size_dma_i_1__n.BLIF N_242_0.BLIF \ -inst_A0_DMA.BLIF a_i_16__n.BLIF N_243_0.BLIF inst_CLK_030_H.BLIF \ -a_i_18__n.BLIF N_93_i.BLIF SM_AMIGA_1_.BLIF a_i_19__n.BLIF N_94_i.BLIF \ -SM_AMIGA_4_.BLIF a_i_30__n.BLIF N_244_0.BLIF SM_AMIGA_2_.BLIF a_i_31__n.BLIF \ -N_245_0.BLIF pos_clk_un3_as_030_d0_n.BLIF a_i_28__n.BLIF N_246_0.BLIF \ -inst_DS_000_ENABLE.BLIF a_i_29__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF \ -a_i_26__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF a_i_27__n.BLIF \ -N_249_i.BLIF pos_clk_a0_dma_3_n.BLIF a_i_24__n.BLIF N_251_0.BLIF \ -a_i_25__n.BLIF N_71_0.BLIF LDS_000_INT_i.BLIF N_104_i.BLIF N_8.BLIF \ -DS_030_i.BLIF N_137_i.BLIF N_9.BLIF UDS_000_INT_i.BLIF N_10.BLIF N_224_i.BLIF \ -N_160_i.BLIF N_11.BLIF N_225_i.BLIF N_161_i.BLIF N_12.BLIF N_226_i.BLIF \ -N_13.BLIF N_159_i.BLIF N_14.BLIF N_157_i.BLIF N_15.BLIF N_158_i.BLIF N_16.BLIF \ -N_91_i.BLIF N_19.BLIF N_90_i.BLIF N_155_i.BLIF N_20.BLIF \ -un14_amiga_bus_data_dir_i.BLIF N_156_i.BLIF N_21.BLIF N_80_i.BLIF N_23.BLIF \ -un6_lds_000_i.BLIF N_154_i.BLIF N_24.BLIF un6_uds_000_i.BLIF N_152_i.BLIF \ -N_25.BLIF un6_ds_030_i.BLIF N_153_i.BLIF cpu_est_0_0_.BLIF un4_as_000_i.BLIF \ -N_142_0.BLIF AS_000_INT_i.BLIF N_141_0.BLIF un6_as_030_i.BLIF N_138_0.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_132_i.BLIF DS_030_D0_i.BLIF \ -un1_as_030_i.BLIF AS_030_c.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF \ -AS_000_c.BLIF size_c_i_1__n.BLIF N_25_i.BLIF RW_000_c.BLIF N_32_0.BLIF \ -N_24_i.BLIF DS_030_c.BLIF N_31_0.BLIF N_23_i.BLIF UDS_000_c.BLIF N_30_0.BLIF \ -ipl_c_i_2__n.BLIF LDS_000_c.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF \ -size_c_0__n.BLIF N_53_0.BLIF ipl_c_i_0__n.BLIF size_c_1__n.BLIF N_52_0.BLIF \ +LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_159.BLIF N_21_i.BLIF \ +bgack_030_int_0_un0_n.BLIF N_157.BLIF N_34_0.BLIF as_030_000_sync_0_un3_n.BLIF \ +N_158.BLIF N_20_i.BLIF as_030_000_sync_0_un1_n.BLIF un1_rst_dly_i_m_1__n.BLIF \ +N_35_0.BLIF as_030_000_sync_0_un0_n.BLIF N_138.BLIF N_16_i.BLIF \ +ds_000_enable_0_un3_n.BLIF N_88.BLIF N_39_0.BLIF ds_000_enable_0_un1_n.BLIF \ +inst_BGACK_030_INTreg.BLIF N_256.BLIF N_13_i.BLIF ds_000_enable_0_un0_n.BLIF \ +vcc_n_n.BLIF N_89.BLIF N_42_0.BLIF a0_dma_0_un3_n.BLIF cpu_est_3_reg.BLIF \ +N_91.BLIF N_12_i.BLIF a0_dma_0_un1_n.BLIF inst_VMA_INTreg.BLIF N_92.BLIF \ +N_43_0.BLIF a0_dma_0_un0_n.BLIF inst_RESET_OUTreg.BLIF pos_clk_a0_dma_3_n.BLIF \ +N_8_i.BLIF size_dma_0_1__un3_n.BLIF gnd_n_n.BLIF N_96.BLIF N_46_0.BLIF \ +size_dma_0_1__un1_n.BLIF un1_amiga_bus_enable_low.BLIF N_72.BLIF N_76_i.BLIF \ +size_dma_0_1__un0_n.BLIF un6_as_030.BLIF N_97.BLIF N_72_0.BLIF \ +size_dma_0_0__un3_n.BLIF un3_size.BLIF N_116.BLIF UDS_000_c_i.BLIF \ +size_dma_0_0__un1_n.BLIF un4_size.BLIF N_104.BLIF LDS_000_c_i.BLIF \ +size_dma_0_0__un0_n.BLIF un5_ciin.BLIF N_76.BLIF N_256_i.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un8_ciin.BLIF \ +pos_clk_size_dma_6_1__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un4_as_000.BLIF \ +pos_clk_size_dma_6_0__n.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF un1_SM_AMIGA_7.BLIF \ +N_250.BLIF N_104_i.BLIF cpu_est_0_1__un3_n.BLIF un21_fpu_cs.BLIF \ +pos_clk_un6_bgack_000_n.BLIF N_252_0.BLIF cpu_est_0_1__un1_n.BLIF \ +un22_berr.BLIF N_251.BLIF N_251_0.BLIF cpu_est_0_1__un0_n.BLIF un6_ds_030.BLIF \ +N_252.BLIF pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_2__un3_n.BLIF \ +un6_uds_000.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_97_i.BLIF \ +cpu_est_0_2__un1_n.BLIF un6_lds_000.BLIF \ +pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_96_i.BLIF cpu_est_0_2__un0_n.BLIF \ +cpu_est_0_.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_250_0.BLIF \ +cpu_est_0_3__un3_n.BLIF cpu_est_1_.BLIF un22_berr_1.BLIF N_89_i.BLIF \ +cpu_est_0_3__un1_n.BLIF inst_AS_000_INT.BLIF N_8.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF cpu_est_0_3__un0_n.BLIF SM_AMIGA_5_.BLIF \ +N_12.BLIF N_88_i.BLIF ipl_030_0_0__un3_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_13.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +ipl_030_0_0__un1_n.BLIF inst_AS_030_D0.BLIF N_16.BLIF N_138_0.BLIF \ +ipl_030_0_0__un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_20.BLIF \ +un1_rst_dly_i_m_i_1__n.BLIF ipl_030_0_1__un3_n.BLIF inst_DS_030_D0.BLIF \ +N_21.BLIF ipl_030_0_1__un1_n.BLIF inst_AS_030_000_SYNC.BLIF N_11.BLIF \ +N_157_i.BLIF ipl_030_0_1__un0_n.BLIF inst_BGACK_030_INT_D.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_158_i.BLIF ipl_030_0_2__un3_n.BLIF \ +inst_AS_000_DMA.BLIF un21_fpu_cs_i.BLIF N_159_i.BLIF ipl_030_0_2__un1_n.BLIF \ +inst_DS_000_DMA.BLIF BGACK_030_INT_i.BLIF ipl_030_0_2__un0_n.BLIF \ +CYCLE_DMA_0_.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_257_0.BLIF \ +dsack1_int_0_un3_n.BLIF CYCLE_DMA_1_.BLIF AS_030_i.BLIF un1_as_000_i.BLIF \ +dsack1_int_0_un1_n.BLIF SIZE_DMA_0_.BLIF AS_000_INT_i.BLIF N_93_i.BLIF \ +dsack1_int_0_un0_n.BLIF SIZE_DMA_1_.BLIF N_105_i.BLIF as_000_int_0_un3_n.BLIF \ +inst_VPA_D.BLIF N_91_i.BLIF N_87_i.BLIF as_000_int_0_un1_n.BLIF \ +inst_UDS_000_INT.BLIF N_92_i.BLIF N_86_i.BLIF as_000_int_0_un0_n.BLIF \ +inst_LDS_000_INT.BLIF a_i_19__n.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ +lds_000_int_0_un3_n.BLIF inst_CLK_OUT_PRE_D.BLIF a_i_18__n.BLIF \ +un1_rst_dly_i_m_i_2__n.BLIF lds_000_int_0_un1_n.BLIF inst_DTACK_D0.BLIF \ +a_i_16__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF \ +size_dma_i_1__n.BLIF un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un3_n.BLIF \ +inst_CLK_000_D1.BLIF size_dma_i_0__n.BLIF rw_000_int_0_un1_n.BLIF \ +inst_CLK_000_D0.BLIF FPU_SENSE_i.BLIF un1_rst_dly_i_m_i_4__n.BLIF \ +rw_000_int_0_un0_n.BLIF inst_CLK_000_PE.BLIF CLK_000_D1_i.BLIF \ +uds_000_int_0_un3_n.BLIF CLK_000_P_SYNC_9_.BLIF CLK_000_D0_i.BLIF \ +un1_rst_dly_i_m_i_5__n.BLIF uds_000_int_0_un1_n.BLIF inst_CLK_000_NE.BLIF \ +AS_030_000_SYNC_i.BLIF uds_000_int_0_un0_n.BLIF CLK_000_N_SYNC_11_.BLIF \ +AS_030_D0_i.BLIF un1_rst_dly_i_m_i_6__n.BLIF vma_int_0_un3_n.BLIF \ +cpu_est_2_.BLIF sm_amiga_i_i_7__n.BLIF vma_int_0_un1_n.BLIF IPL_D0_0_.BLIF \ +AS_000_i.BLIF un1_rst_dly_i_m_i_7__n.BLIF vma_int_0_un0_n.BLIF IPL_D0_1_.BLIF \ +CLK_000_PE_i.BLIF bg_000_0_un3_n.BLIF IPL_D0_2_.BLIF nEXP_SPACE_D0_i.BLIF \ +un1_rst_dly_i_m_i_8__n.BLIF bg_000_0_un1_n.BLIF SM_AMIGA_3_.BLIF A1_i.BLIF \ +bg_000_0_un0_n.BLIF inst_CLK_000_NE_D0.BLIF sm_amiga_i_6__n.BLIF \ +un3_as_030_i.BLIF ds_000_dma_0_un3_n.BLIF pos_clk_un6_bg_030_n.BLIF \ +BERR_i.BLIF un1_as_030_i.BLIF ds_000_dma_0_un1_n.BLIF SM_AMIGA_0_.BLIF \ +sm_amiga_i_5__n.BLIF clk_000_n_sync_i_10__n.BLIF ds_000_dma_0_un0_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF RESET_OUT_0_sqmuxa_i.BLIF \ +pos_clk_un9_clk_000_n_sync_i_n.BLIF as_000_dma_0_un3_n.BLIF \ +inst_DSACK1_INTreg.BLIF un1_rst_dly_i_1__n.BLIF \ +pos_clk_un14_clk_000_n_sync_0_n.BLIF as_000_dma_0_un1_n.BLIF RESET_OUT_i.BLIF \ +CLK_EXP_c_i.BLIF as_000_dma_0_un0_n.BLIF pos_clk_clk_000_n_sync_2_0__n.BLIF \ +RW_000_i.BLIF N_244_0.BLIF a_15__n.BLIF pos_clk_ipl_n.BLIF \ +un1_rst_dly_i_2__n.BLIF N_83_i.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +un1_rst_dly_i_3__n.BLIF N_115_0.BLIF a_14__n.BLIF SM_AMIGA_6_.BLIF \ +un1_rst_dly_i_4__n.BLIF N_84_i.BLIF RST_DLY_0_.BLIF un1_rst_dly_i_5__n.BLIF \ +N_245_0.BLIF a_13__n.BLIF RST_DLY_1_.BLIF un1_rst_dly_i_6__n.BLIF N_85_i.BLIF \ +RST_DLY_2_.BLIF un1_rst_dly_i_7__n.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +a_12__n.BLIF RST_DLY_3_.BLIF un1_rst_dly_i_8__n.BLIF N_94_i.BLIF \ +RST_DLY_4_.BLIF CLK_OUT_PRE_D_i.BLIF a_11__n.BLIF RST_DLY_5_.BLIF \ +pos_clk_un11_clk_000_n_sync_i_n.BLIF RST_DLY_6_.BLIF CLK_030_H_i.BLIF \ +a_10__n.BLIF RST_DLY_7_.BLIF AS_000_DMA_i.BLIF N_73_0.BLIF \ +pos_clk_un8_bg_030_n.BLIF VMA_INT_i.BLIF a_9__n.BLIF CLK_000_P_SYNC_0_.BLIF \ +VPA_D_i.BLIF N_160_i.BLIF CLK_000_P_SYNC_1_.BLIF cpu_est_i_0__n.BLIF \ +N_161_i.BLIF a_8__n.BLIF CLK_000_P_SYNC_2_.BLIF cpu_est_i_1__n.BLIF \ +CLK_000_P_SYNC_3_.BLIF cpu_est_i_3__n.BLIF N_155_i.BLIF a_7__n.BLIF \ +CLK_000_P_SYNC_4_.BLIF a_i_24__n.BLIF N_156_i.BLIF CLK_000_P_SYNC_5_.BLIF \ +pos_clk_un7_clk_000_d0_i_n.BLIF a_6__n.BLIF CLK_000_P_SYNC_6_.BLIF \ +sm_amiga_i_0__n.BLIF N_154_i.BLIF CLK_000_P_SYNC_7_.BLIF sm_amiga_i_3__n.BLIF \ +N_152_i.BLIF a_5__n.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_NE_i.BLIF N_153_i.BLIF \ +CLK_000_N_SYNC_0_.BLIF cpu_est_i_2__n.BLIF a_4__n.BLIF CLK_000_N_SYNC_1_.BLIF \ +sm_amiga_i_1__n.BLIF N_150_i.BLIF CLK_000_N_SYNC_2_.BLIF sm_amiga_i_4__n.BLIF \ +N_151_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_3_.BLIF sm_amiga_i_2__n.BLIF \ +CLK_000_N_SYNC_4_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_149_i.BLIF \ +a_2__n.BLIF CLK_000_N_SYNC_5_.BLIF DSACK1_INT_0_sqmuxa_i.BLIF N_147_i.BLIF \ +CLK_000_N_SYNC_6_.BLIF RW_i.BLIF N_148_i.BLIF CLK_000_N_SYNC_7_.BLIF \ +un5_ciin_i.BLIF CLK_000_N_SYNC_8_.BLIF DTACK_D0_i.BLIF N_164_i.BLIF \ +CLK_000_N_SYNC_9_.BLIF a_i_31__n.BLIF N_165_i.BLIF CLK_000_N_SYNC_10_.BLIF \ +a_i_29__n.BLIF N_163_i.BLIF inst_RW_000_INT.BLIF a_i_30__n.BLIF N_199_i.BLIF \ +inst_RW_000_DMA.BLIF a_i_27__n.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \ +pos_clk_un7_clk_000_pe_n.BLIF a_i_28__n.BLIF N_197_i.BLIF inst_A0_DMA.BLIF \ +a_i_25__n.BLIF N_198_i.BLIF DS_000_ENABLE_1_sqmuxa.BLIF a_i_26__n.BLIF \ +N_194_i.BLIF inst_CLK_030_H.BLIF UDS_000_INT_i.BLIF \ +pos_clk_cpu_est_11_0_1__n.BLIF SM_AMIGA_1_.BLIF LDS_000_INT_i.BLIF \ +N_192_i.BLIF SM_AMIGA_4_.BLIF DS_030_i.BLIF N_135_i.BLIF SM_AMIGA_2_.BLIF \ +N_224_i.BLIF N_162_i.BLIF inst_DS_000_ENABLE.BLIF N_225_i.BLIF N_191_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF N_226_i.BLIF N_193_i.BLIF DSACK1_INT_1_sqmuxa.BLIF \ +N_190_i.BLIF pos_clk_ds_000_dma_4_n.BLIF N_189_i.BLIF N_3.BLIF \ +DS_000_ENABLE_1_sqmuxa_i.BLIF N_188_i.BLIF un6_lds_000_i.BLIF N_195_i.BLIF \ +un6_uds_000_i.BLIF N_196_i.BLIF N_6.BLIF un6_ds_030_i.BLIF N_186_i.BLIF \ +N_9.BLIF DS_000_DMA_i.BLIF N_143_0.BLIF N_10.BLIF un4_as_000_i.BLIF \ +N_142_0.BLIF N_14.BLIF un8_ciin_i.BLIF N_141_0.BLIF N_15.BLIF \ +un6_as_030_i.BLIF N_140_0.BLIF N_17.BLIF DS_030_D0_i.BLIF N_139_0.BLIF \ +N_19.BLIF AS_030_c.BLIF N_166_i.BLIF N_22.BLIF N_137_i.BLIF N_23.BLIF \ +AS_000_c.BLIF N_136_i.BLIF N_24.BLIF N_133_i.BLIF N_25.BLIF RW_000_c.BLIF \ +N_132_i.BLIF cpu_est_0_0_.BLIF N_146_i.BLIF DS_030_c.BLIF N_144_i.BLIF \ +UDS_000_c.BLIF un1_SM_AMIGA_7_i.BLIF pos_clk_un21_clk_000_ne_d0_i_n.BLIF \ +LDS_000_c.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF \ +pos_clk_un23_clk_000_ne_d0_0_n.BLIF size_c_0__n.BLIF \ +pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ +size_c_1__n.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF \ +pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF size_c_i_1__n.BLIF N_25_i.BLIF \ +N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF N_23_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF \ +N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF ipl_c_i_0__n.BLIF N_52_0.BLIF \ DTACK_c_i.BLIF N_57_0.BLIF VPA_c_i.BLIF N_56_0.BLIF nEXP_SPACE_c_i.BLIF \ -N_55_0.BLIF N_50_0.BLIF N_8_i.BLIF N_46_0.BLIF N_9_i.BLIF N_45_0.BLIF \ -N_10_i.BLIF SM_AMIGA_i_7_.BLIF N_44_0.BLIF N_115.BLIF N_12_i.BLIF \ -pos_clk_size_dma_6_0__n.BLIF N_43_0.BLIF pos_clk_size_dma_6_1__n.BLIF \ -N_13_i.BLIF G_165.BLIF N_42_0.BLIF G_166.BLIF N_14_i.BLIF G_167.BLIF \ -N_41_0.BLIF un6_uds_000_1.BLIF N_15_i.BLIF N_241.BLIF N_40_0.BLIF N_242.BLIF \ -N_16_i.BLIF N_243.BLIF N_39_0.BLIF N_244.BLIF N_19_i.BLIF N_245.BLIF \ -N_36_0.BLIF N_246.BLIF N_20_i.BLIF N_78.BLIF N_35_0.BLIF N_80.BLIF N_21_i.BLIF \ -N_89.BLIF N_34_0.BLIF N_90.BLIF a_c_16__n.BLIF BG_030_c_i.BLIF N_91.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF N_98.BLIF a_c_17__n.BLIF \ -pos_clk_un8_bg_030_0_n.BLIF N_99.BLIF N_251_0_1.BLIF N_249.BLIF a_c_18__n.BLIF \ -N_121_i_1.BLIF N_248.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF N_135.BLIF \ -a_c_19__n.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF N_136.BLIF \ -pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_un7_clk_000_d0_n.BLIF N_131_i_1.BLIF \ -un22_berr_1.BLIF N_131_i_2.BLIF N_152.BLIF N_131_i_3.BLIF N_153.BLIF \ -pos_clk_un11_ds_030_d0_i_1_n.BLIF N_154.BLIF un8_ciin_1.BLIF N_155.BLIF \ -un8_ciin_2.BLIF N_141.BLIF un8_ciin_3.BLIF N_156.BLIF un8_ciin_4.BLIF \ -N_157.BLIF a_c_24__n.BLIF un8_ciin_5.BLIF N_138.BLIF un8_ciin_6.BLIF \ -N_158.BLIF a_c_25__n.BLIF un8_ciin_7.BLIF N_159.BLIF un8_ciin_8.BLIF \ -N_160.BLIF a_c_26__n.BLIF N_116_1.BLIF N_142.BLIF N_116_2.BLIF N_161.BLIF \ -a_c_27__n.BLIF N_116_3.BLIF N_132.BLIF N_116_4.BLIF N_104.BLIF a_c_28__n.BLIF \ -un22_berr_1_0.BLIF N_76.BLIF un21_fpu_cs_1.BLIF N_71.BLIF a_c_29__n.BLIF \ -N_123_i_1.BLIF N_251.BLIF N_123_i_2.BLIF N_93.BLIF a_c_30__n.BLIF \ -N_125_i_1.BLIF N_94.BLIF N_127_i_1.BLIF N_88.BLIF a_c_31__n.BLIF \ -N_127_i_2.BLIF N_87.BLIF N_129_i_1.BLIF N_86.BLIF A0_c.BLIF \ -pos_clk_un6_bg_030_1_n.BLIF N_84.BLIF pos_clk_un7_clk_000_d0_1_n.BLIF \ -N_83.BLIF A1_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_116.BLIF \ -RESET_OUT_0_sqmuxa_7_2.BLIF G_149.BLIF nEXP_SPACE_c.BLIF \ -RESET_OUT_0_sqmuxa_7_3.BLIF G_147.BLIF RESET_OUT_0_sqmuxa_5_1.BLIF N_213.BLIF \ -BERR_c.BLIF N_135_i_1.BLIF G_145.BLIF pos_clk_un27_clk_000_ne_d0_1_n.BLIF \ -N_211.BLIF BG_030_c.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF G_143.BLIF \ -pos_clk_un27_clk_000_ne_d0_3_n.BLIF N_209.BLIF BG_000DFFreg.BLIF \ -pos_clk_un5_clk_000_pe_1_n.BLIF G_141.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ -G_139.BLIF pos_clk_un5_clk_000_pe_3_n.BLIF N_205.BLIF BGACK_000_c.BLIF \ -pos_clk_un9_clk_000_ne_1_n.BLIF G_137.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF \ -RESET_OUT_0_sqmuxa_1.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF \ -RESET_OUT_0_sqmuxa.BLIF pos_clk_un9_clk_000_ne_4_n.BLIF \ -RESET_OUT_0_sqmuxa_7.BLIF N_196_1.BLIF RESET_OUT_0_sqmuxa_5.BLIF \ -CLK_OSZI_c.BLIF N_195_1.BLIF un1_rst_dly_i_m_8__n.BLIF \ -pos_clk_un24_bgack_030_int_1_n.BLIF un1_rst_dly_i_m_7__n.BLIF N_165_1.BLIF \ -un1_rst_dly_i_m_6__n.BLIF CLK_EXP_c.BLIF N_165_2.BLIF \ -un1_rst_dly_i_m_5__n.BLIF N_165_3.BLIF un1_rst_dly_i_m_4__n.BLIF N_163_1.BLIF \ -un1_rst_dly_i_m_3__n.BLIF FPU_SENSE_c.BLIF N_162_1.BLIF \ -un1_rst_dly_i_m_2__n.BLIF N_176_1_0.BLIF N_38.BLIF IPL_030DFF_0_reg.BLIF \ -DS_000_DMA_2_sqmuxa_1.BLIF N_85.BLIF N_119_i_1.BLIF \ -pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF IPL_030DFF_1_reg.BLIF N_115_0_1.BLIF \ -N_252.BLIF pos_clk_ipl_1_n.BLIF N_97.BLIF IPL_030DFF_2_reg.BLIF \ -as_000_dma_0_un3_n.BLIF pos_clk_un27_clk_000_ne_d0_n.BLIF \ -as_000_dma_0_un1_n.BLIF N_199_1.BLIF ipl_c_0__n.BLIF as_000_dma_0_un0_n.BLIF \ -pos_clk_un5_clk_000_pe_n.BLIF ds_000_dma_0_un3_n.BLIF \ -pos_clk_un9_clk_000_ne_n.BLIF ipl_c_1__n.BLIF ds_000_dma_0_un1_n.BLIF \ -N_150.BLIF ds_000_dma_0_un0_n.BLIF N_151.BLIF ipl_c_2__n.BLIF \ -vma_int_0_un3_n.BLIF N_199.BLIF vma_int_0_un1_n.BLIF N_196.BLIF \ -vma_int_0_un0_n.BLIF N_195.BLIF DTACK_c.BLIF \ -sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_188.BLIF \ -sm_amiga_srsts_i_0_m2_1__un1_n.BLIF pos_clk_cpu_est_11_3__n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_197.BLIF cpu_est_0_3__un3_n.BLIF \ -N_198.BLIF VPA_c.BLIF cpu_est_0_3__un1_n.BLIF pos_clk_cpu_est_11_1__n.BLIF \ -cpu_est_0_3__un0_n.BLIF N_194.BLIF cpu_est_0_2__un3_n.BLIF N_192.BLIF \ -RST_c.BLIF cpu_est_0_2__un1_n.BLIF N_191.BLIF cpu_est_0_2__un0_n.BLIF \ +SM_AMIGA_i_7_.BLIF N_55_0.BLIF N_115.BLIF N_50_0.BLIF \ +pos_clk_cpu_est_11_1__n.BLIF N_3_i.BLIF pos_clk_cpu_est_11_3__n.BLIF \ +N_49_0.BLIF N_220.BLIF N_6_i.BLIF G_165.BLIF N_48_0.BLIF G_166.BLIF N_9_i.BLIF \ +G_167.BLIF N_45_0.BLIF un6_uds_000_1.BLIF N_10_i.BLIF \ +pos_clk_un24_bgack_030_int_i_0_n.BLIF a_c_16__n.BLIF N_44_0.BLIF N_244.BLIF \ +N_14_i.BLIF N_245.BLIF a_c_17__n.BLIF N_41_0.BLIF N_15_i.BLIF N_80.BLIF \ +a_c_18__n.BLIF N_40_0.BLIF N_90.BLIF N_17_i.BLIF N_100.BLIF a_c_19__n.BLIF \ +N_38_0.BLIF N_105.BLIF N_19_i.BLIF pos_clk_un11_clk_000_n_sync_n.BLIF \ +a_c_20__n.BLIF N_36_0.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_22_i.BLIF \ +pos_clk_CYCLE_DMA_5_0_i_x2.BLIF a_c_21__n.BLIF N_33_0.BLIF N_135.BLIF \ +BG_030_c_i.BLIF N_133.BLIF a_c_22__n.BLIF pos_clk_un6_bg_030_i_n.BLIF \ +N_190.BLIF pos_clk_un8_bg_030_0_n.BLIF N_188.BLIF a_c_23__n.BLIF \ +N_127_i_1.BLIF N_189.BLIF N_127_i_2.BLIF N_136.BLIF a_c_24__n.BLIF \ +pos_clk_un11_ds_030_d0_i_1_n.BLIF pos_clk_un7_clk_000_d0_n.BLIF N_135_i_1.BLIF \ +pos_clk_un29_clk_000_ne_d0_n.BLIF a_c_25__n.BLIF \ +pos_clk_cpu_est_11_0_1_1__n.BLIF DSACK1_INT_0_sqmuxa.BLIF \ +pos_clk_cpu_est_11_0_2_1__n.BLIF pos_clk_un21_clk_000_ne_d0_n.BLIF \ +a_c_26__n.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF pos_clk_un5_clk_000_pe_n.BLIF \ +N_195_1.BLIF pos_clk_un9_clk_000_ne_n.BLIF a_c_27__n.BLIF N_196_1.BLIF \ +pos_clk_un23_clk_000_ne_d0_n.BLIF N_131_i_1.BLIF \ +pos_clk_un27_clk_000_ne_d0_n.BLIF a_c_28__n.BLIF N_131_i_2.BLIF \ +pos_clk_un14_clk_000_n_sync_n.BLIF N_131_i_3.BLIF N_144.BLIF a_c_29__n.BLIF \ +N_119_i_1.BLIF N_146.BLIF N_119_i_2.BLIF N_143.BLIF a_c_30__n.BLIF \ +N_121_i_1.BLIF N_147.BLIF N_123_i_1.BLIF N_139.BLIF a_c_31__n.BLIF \ +N_123_i_2.BLIF N_148.BLIF N_125_i_1.BLIF N_149.BLIF A0_c.BLIF N_129_i_1.BLIF \ +N_150.BLIF N_162_1.BLIF N_140.BLIF A1_c.BLIF N_163_1.BLIF N_151.BLIF \ +N_165_1.BLIF N_152.BLIF nEXP_SPACE_c.BLIF N_165_2.BLIF N_153.BLIF N_165_3.BLIF \ +N_154.BLIF BERR_c.BLIF un5_ciin_1.BLIF N_155.BLIF un5_ciin_2.BLIF N_141.BLIF \ +BG_030_c.BLIF un5_ciin_3.BLIF N_156.BLIF un5_ciin_4.BLIF N_160.BLIF \ +BG_000DFFreg.BLIF un5_ciin_5.BLIF N_142.BLIF un5_ciin_6.BLIF N_161.BLIF \ +un5_ciin_7.BLIF N_164.BLIF BGACK_000_c.BLIF un5_ciin_8.BLIF N_166.BLIF \ +un5_ciin_9.BLIF N_132.BLIF un5_ciin_10.BLIF N_191.BLIF un5_ciin_11.BLIF \ +N_192.BLIF pos_clk_un9_clk_000_ne_1_n.BLIF N_193.BLIF CLK_OSZI_c.BLIF \ +pos_clk_un9_clk_000_ne_2_n.BLIF N_194.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF \ +N_197.BLIF pos_clk_un9_clk_000_ne_4_n.BLIF N_198.BLIF CLK_EXP_c.BLIF \ +pos_clk_un5_clk_000_pe_1_n.BLIF N_195.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ +N_196.BLIF pos_clk_un5_clk_000_pe_3_n.BLIF N_162.BLIF FPU_SENSE_c.BLIF \ +pos_clk_un27_clk_000_ne_d0_1_n.BLIF N_199.BLIF \ +pos_clk_un27_clk_000_ne_d0_2_n.BLIF N_199_1.BLIF IPL_030DFF_0_reg.BLIF \ +pos_clk_un27_clk_000_ne_d0_3_n.BLIF N_163.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF \ +N_165.BLIF IPL_030DFF_1_reg.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF N_73.BLIF \ +RESET_OUT_0_sqmuxa_7_3.BLIF N_94.BLIF IPL_030DFF_2_reg.BLIF \ +RESET_OUT_0_sqmuxa_5_1.BLIF N_85.BLIF N_87_1.BLIF N_84.BLIF ipl_c_0__n.BLIF \ +N_87_2.BLIF N_83.BLIF pos_clk_un24_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un9_clk_000_n_sync_n.BLIF ipl_c_1__n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_0_2_n.BLIF G_149.BLIF N_72_0_1.BLIF G_147.BLIF \ +ipl_c_2__n.BLIF pos_clk_un7_clk_000_d0_1_n.BLIF N_213.BLIF un21_fpu_cs_1.BLIF \ +G_145.BLIF un22_berr_1_0.BLIF N_211.BLIF DTACK_c.BLIF N_116_1.BLIF G_143.BLIF \ +N_116_2.BLIF N_209.BLIF N_116_3.BLIF G_141.BLIF N_116_4.BLIF G_139.BLIF \ +VPA_c.BLIF pos_clk_un6_bg_030_1_n.BLIF N_205.BLIF N_115_0_1.BLIF G_137.BLIF \ +N_245_0_1.BLIF RESET_OUT_0_sqmuxa_1.BLIF RST_c.BLIF N_247_i_1.BLIF \ +RESET_OUT_0_sqmuxa.BLIF N_248_i_1.BLIF RESET_OUT_0_sqmuxa_7.BLIF \ +N_249_i_1.BLIF RESET_OUT_0_sqmuxa_5.BLIF RW_c.BLIF pos_clk_ipl_1_n.BLIF \ +un1_rst_dly_i_m_8__n.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ +un1_rst_dly_i_m_7__n.BLIF fc_c_0__n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n.BLIF un1_rst_dly_i_m_6__n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF un1_rst_dly_i_m_5__n.BLIF \ +fc_c_1__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF un1_rst_dly_i_m_4__n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n.BLIF un1_rst_dly_i_m_3__n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF un1_rst_dly_i_m_2__n.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF rw_000_dma_0_un3_n.BLIF N_86.BLIF \ +rw_000_dma_0_un1_n.BLIF N_93.BLIF rw_000_dma_0_un0_n.BLIF N_87.BLIF \ +bgack_030_int_0_un3_n.BLIF G_135.BLIF bgack_030_int_0_un1_n.BLIF \ AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \ UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \ VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \ -SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C \ -SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ -SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFF_0_reg.D \ -IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ -IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C \ -RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C \ -RST_DLY_6_.D RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ -CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ -CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ -CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ -CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ -CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ -CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ -CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ -CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_P_SYNC_0_.D \ -CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C \ -CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ -CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \ -inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ -inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUTreg.D \ -inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C BG_000DFFreg.D BG_000DFFreg.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ +IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D \ +RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D \ +RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D \ +RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ +CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ +CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ +CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ +CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ +CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ +CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \ +CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ +CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \ +CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C \ +inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_A0_DMA.D inst_A0_DMA.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_DS_030_D0.D inst_DS_030_D0.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \ inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \ inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \ -UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_193 cpu_est_0_1__un3_n N_190 RW_c \ -cpu_est_0_1__un1_n N_189 cpu_est_0_1__un0_n N_140 fc_c_0__n \ -bgack_030_int_0_un3_n pos_clk_un29_clk_000_ne_d0_n bgack_030_int_0_un1_n \ -pos_clk_un23_clk_000_ne_d0_n fc_c_1__n bgack_030_int_0_un0_n \ -pos_clk_un21_clk_000_ne_d0_n un1_amiga_bus_enable_dma_high_i_m4_0__un3_n \ -vcc_n_n pos_clk_un7_clk_000_pe_n un1_amiga_bus_enable_dma_high_i_m4_0__un1_n \ -N_18 AMIGA_BUS_DATA_DIR_c un1_amiga_bus_enable_dma_high_i_m4_0__un0_n N_22 \ -ds_000_enable_1_sqmuxa_1_i_m4_un3_n pos_clk_un11_clk_000_n_sync_n \ -ds_000_enable_1_sqmuxa_1_i_m4_un1_n gnd_n_n pos_clk_un9_clk_000_n_sync_n \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n un1_amiga_bus_enable_low \ -pos_clk_un14_clk_000_n_sync_n size_dma_0_0__un3_n un6_as_030 \ -pos_clk_un22_bgack_030_int_n N_6_i size_dma_0_0__un1_n un3_size N_48_0 \ -size_dma_0_0__un0_n un4_size N_220 N_3_i size_dma_0_1__un3_n un8_ciin N_49_0 \ -size_dma_0_1__un1_n un14_amiga_bus_data_dir pos_clk_un40_bgack_030_int_1_n \ -pos_clk_un29_bgack_030_int_i_n size_dma_0_1__un0_n un4_as_000 \ -CLK_030_H_0_sqmuxa pos_clk_un26_bgack_030_int_i_n ipl_030_0_0__un3_n \ -un21_fpu_cs AS_000_DMA_1_sqmuxa pos_clk_un27_bgack_030_int_0_n \ -ipl_030_0_0__un1_n un22_berr pos_clk_un24_bgack_030_int_n CLK_030_H_0_sqmuxa_i \ -ipl_030_0_0__un0_n un6_ds_030 pos_clk_un27_bgack_030_int_n N_7_i \ -ipl_030_0_1__un3_n un6_uds_000 N_176_1 N_47_0 ipl_030_0_1__un1_n un6_lds_000 \ -N_165 N_133_i ipl_030_0_1__un0_n N_133 N_176_i ipl_030_0_2__un3_n N_163 \ -N_175_i ipl_030_0_2__un1_n N_162 AMIGA_BUS_DATA_DIR_c_0 ipl_030_0_2__un0_n \ -N_164 pos_clk_ds_000_dma_4_f1_0_n dsack1_int_0_un3_n N_176 N_162_i \ -dsack1_int_0_un1_n DS_000_DMA_2_sqmuxa N_163_i dsack1_int_0_un0_n \ -pos_clk_ds_000_dma_4_n N_164_i as_000_int_0_un3_n DS_000_DMA_0_sqmuxa N_165_i \ -as_000_int_0_un1_n pos_clk_ds_000_dma_4_f1_n as_000_int_0_un0_n N_175 \ -pos_clk_un22_bgack_030_int_0_n ds_000_enable_0_un3_n N_47 \ -pos_clk_un9_clk_000_n_sync_i_n ds_000_enable_0_un1_n N_7 \ -clk_000_n_sync_i_10__n ds_000_enable_0_un0_n un1_rst_2 \ -pos_clk_un14_clk_000_n_sync_0_n as_030_000_sync_0_un3_n \ -pos_clk_un26_bgack_030_int_n N_22_i as_030_000_sync_0_un1_n \ -pos_clk_un29_bgack_030_int_n N_33_0 as_030_000_sync_0_un0_n N_3 N_18_i \ -lds_000_int_0_un3_n N_6 N_37_0 lds_000_int_0_un1_n un1_amiga_bus_enable_low_i \ -pos_clk_un9_clk_000_ne_i_n lds_000_int_0_un0_n un21_fpu_cs_i \ -pos_clk_un5_clk_000_pe_i_n rw_000_int_0_un3_n AS_000_i \ -pos_clk_un7_clk_000_pe_0_n rw_000_int_0_un1_n DS_000_DMA_i \ -pos_clk_un27_clk_000_ne_d0_i_n rw_000_int_0_un0_n \ -pos_clk_un24_bgack_030_int_i_n pos_clk_un21_clk_000_ne_d0_i_n \ -rw_000_dma_0_un3_n cycle_dma_i_1__n pos_clk_un23_clk_000_ne_d0_0_n \ -rw_000_dma_0_un1_n cycle_dma_i_0__n N_136_i rw_000_dma_0_un0_n AS_000_DMA_i \ -N_140_0 uds_000_int_0_un3_n CLK_EXP_i N_195_i uds_000_int_0_un1_n BERR_i \ -N_196_i uds_000_int_0_un0_n RW_000_i N_186_i amiga_bus_enable_dma_low_0_un3_n \ -DS_000_DMA_0_sqmuxa_i N_188_i amiga_bus_enable_dma_low_0_un1_n \ -pos_clk_un40_bgack_030_int_1_i_n N_189_i amiga_bus_enable_dma_low_0_un0_n \ -BGACK_030_INT_i N_190_i amiga_bus_enable_dma_high_0_un3_n nEXP_SPACE_D0_i \ -N_193_i amiga_bus_enable_dma_high_0_un1_n CLK_000_PE_i N_191_i \ -amiga_bus_enable_dma_high_0_un0_n CLK_000_NE_i N_192_i bg_000_0_un3_n \ -pos_clk_un6_bg_030_n sm_amiga_i_3__n N_194_i bg_000_0_un1_n sm_amiga_i_0__n \ -pos_clk_cpu_est_11_0_1__n bg_000_0_un0_n pos_clk_un7_clk_000_d0_i_n N_198_i \ -a0_dma_0_un3_n UDS_000_i N_197_i a0_dma_0_un1_n LDS_000_i N_199_i \ -a0_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n pos_clk_un11_clk_000_n_sync_i_n \ -pos_clk_cpu_est_11_0_3__n a_23__n pos_clk_ipl_n CLK_OUT_PRE_D_i N_151_i \ -pos_clk_un3_ds_030_d0_n DTACK_D0_i N_150_i a_22__n sm_amiga_i_2__n \ -AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa pos_clk_un29_clk_000_ne_d0_i_n N_135_i \ -a_21__n cpu_est_i_0__n N_252_0 cpu_est_i_3__n N_85_i a_20__n cpu_est_i_2__n \ -cpu_est_i_1__n N_38_0 a_15__n VPA_D_i un1_rst_dly_i_m_i_2__n VMA_INT_i a_14__n \ -sm_amiga_i_1__n un1_rst_dly_i_m_i_3__n RESET_OUT_0_sqmuxa_i a_13__n \ -pos_clk_un8_bg_030_n N_77_i_i un1_rst_dly_i_m_i_4__n un1_rst_dly_i_2__n \ -a_12__n un1_rst_dly_i_3__n un1_rst_dly_i_m_i_5__n un1_rst_dly_i_4__n a_11__n \ -un1_rst_dly_i_5__n un1_rst_dly_i_m_i_6__n un1_rst_dly_i_6__n a_10__n \ -un1_rst_dly_i_7__n un1_rst_dly_i_m_i_7__n un1_rst_dly_i_8__n a_9__n \ -RESET_OUT_i un1_rst_dly_i_m_i_8__n AS_030_D0_i a_8__n AS_030_i un3_as_030_i \ -A1_i N_76_i a_7__n CLK_000_D1_i N_83_i sm_amiga_i_i_7__n a_6__n N_248_i N_84_i \ -sm_amiga_i_5__n N_115_0 a_5__n RW_i N_86_i CLK_000_D0_i \ -pos_clk_size_dma_6_0_1__n a_4__n AS_030_000_SYNC_i N_87_i sm_amiga_i_6__n \ -pos_clk_size_dma_6_0_0__n a_3__n sm_amiga_i_4__n N_88_i \ -pos_clk_un5_bgack_030_int_d_n FPU_SENSE_i a_2__n size_dma_i_0__n N_241_0 \ -size_dma_i_1__n N_242_0 a_i_16__n N_243_0 a_i_18__n N_93_i a_i_19__n N_94_i \ -a_i_30__n N_244_0 a_i_31__n N_245_0 pos_clk_un3_as_030_d0_n a_i_28__n N_246_0 \ -a_i_29__n pos_clk_un3_as_030_d0_i_n a_i_26__n pos_clk_un5_bgack_030_int_d_i_n \ -a_i_27__n N_249_i pos_clk_a0_dma_3_n a_i_24__n N_251_0 a_i_25__n N_71_0 \ -LDS_000_INT_i N_104_i N_8 DS_030_i N_137_i N_9 UDS_000_INT_i N_10 N_224_i \ -N_160_i N_11 N_225_i N_161_i N_12 N_226_i N_13 N_159_i N_14 N_157_i N_15 \ -N_158_i N_16 N_91_i N_19 N_90_i N_155_i N_20 un14_amiga_bus_data_dir_i N_156_i \ -N_21 N_80_i N_23 un6_lds_000_i N_154_i N_24 un6_uds_000_i N_152_i N_25 \ -un6_ds_030_i N_153_i un4_as_000_i N_142_0 AS_000_INT_i N_141_0 un6_as_030_i \ -N_138_0 AMIGA_BUS_ENABLE_DMA_LOW_i N_132_i DS_030_D0_i un1_as_030_i AS_030_c \ -pos_clk_un11_ds_030_d0_i_n A0_c_i AS_000_c size_c_i_1__n N_25_i RW_000_c \ -N_32_0 N_24_i DS_030_c N_31_0 N_23_i UDS_000_c N_30_0 ipl_c_i_2__n LDS_000_c \ -N_54_0 ipl_c_i_1__n size_c_0__n N_53_0 ipl_c_i_0__n size_c_1__n N_52_0 \ -DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_8_i N_46_0 \ -N_9_i N_45_0 N_10_i N_44_0 N_115 N_12_i pos_clk_size_dma_6_0__n N_43_0 \ -pos_clk_size_dma_6_1__n N_13_i N_42_0 N_14_i N_41_0 un6_uds_000_1 N_15_i N_241 \ -N_40_0 N_242 N_16_i N_243 N_39_0 N_244 N_19_i N_245 N_36_0 N_246 N_20_i N_78 \ -N_35_0 N_80 N_21_i N_89 N_34_0 N_90 a_c_16__n BG_030_c_i N_91 \ -pos_clk_un6_bg_030_i_n N_98 a_c_17__n pos_clk_un8_bg_030_0_n N_99 N_251_0_1 \ -N_249 a_c_18__n N_121_i_1 N_248 pos_clk_cpu_est_11_0_1_3__n N_135 a_c_19__n \ -pos_clk_cpu_est_11_0_1_1__n N_136 pos_clk_cpu_est_11_0_2_1__n \ -pos_clk_un7_clk_000_d0_n N_131_i_1 un22_berr_1 N_131_i_2 N_152 N_131_i_3 N_153 \ -pos_clk_un11_ds_030_d0_i_1_n N_154 un8_ciin_1 N_155 un8_ciin_2 N_141 \ -un8_ciin_3 N_156 un8_ciin_4 N_157 a_c_24__n un8_ciin_5 N_138 un8_ciin_6 N_158 \ -a_c_25__n un8_ciin_7 N_159 un8_ciin_8 N_160 a_c_26__n N_116_1 N_142 N_116_2 \ -N_161 a_c_27__n N_116_3 N_132 N_116_4 N_104 a_c_28__n un22_berr_1_0 N_76 \ -un21_fpu_cs_1 N_71 a_c_29__n N_123_i_1 N_251 N_123_i_2 N_93 a_c_30__n \ -N_125_i_1 N_94 N_127_i_1 N_88 a_c_31__n N_127_i_2 N_87 N_129_i_1 N_86 A0_c \ -pos_clk_un6_bg_030_1_n N_84 pos_clk_un7_clk_000_d0_1_n N_83 A1_c \ -RESET_OUT_0_sqmuxa_7_1 N_116 RESET_OUT_0_sqmuxa_7_2 nEXP_SPACE_c \ -RESET_OUT_0_sqmuxa_7_3 RESET_OUT_0_sqmuxa_5_1 N_213 BERR_c N_135_i_1 \ -pos_clk_un27_clk_000_ne_d0_1_n N_211 BG_030_c pos_clk_un27_clk_000_ne_d0_2_n \ -pos_clk_un27_clk_000_ne_d0_3_n N_209 pos_clk_un5_clk_000_pe_1_n \ -pos_clk_un5_clk_000_pe_2_n pos_clk_un5_clk_000_pe_3_n N_205 BGACK_000_c \ -pos_clk_un9_clk_000_ne_1_n pos_clk_un9_clk_000_ne_2_n RESET_OUT_0_sqmuxa_1 \ -pos_clk_un9_clk_000_ne_3_n RESET_OUT_0_sqmuxa pos_clk_un9_clk_000_ne_4_n \ -RESET_OUT_0_sqmuxa_7 N_196_1 RESET_OUT_0_sqmuxa_5 CLK_OSZI_c N_195_1 \ -un1_rst_dly_i_m_8__n pos_clk_un24_bgack_030_int_1_n un1_rst_dly_i_m_7__n \ -N_165_1 un1_rst_dly_i_m_6__n CLK_EXP_c N_165_2 un1_rst_dly_i_m_5__n N_165_3 \ -un1_rst_dly_i_m_4__n N_163_1 un1_rst_dly_i_m_3__n FPU_SENSE_c N_162_1 \ -un1_rst_dly_i_m_2__n N_176_1_0 N_38 DS_000_DMA_2_sqmuxa_1 N_85 N_119_i_1 \ -N_115_0_1 N_252 pos_clk_ipl_1_n N_97 as_000_dma_0_un3_n \ -pos_clk_un27_clk_000_ne_d0_n as_000_dma_0_un1_n N_199_1 ipl_c_0__n \ -as_000_dma_0_un0_n pos_clk_un5_clk_000_pe_n ds_000_dma_0_un3_n \ -pos_clk_un9_clk_000_ne_n ipl_c_1__n ds_000_dma_0_un1_n N_150 \ -ds_000_dma_0_un0_n N_151 ipl_c_2__n vma_int_0_un3_n N_199 vma_int_0_un1_n \ -N_196 vma_int_0_un0_n N_195 DTACK_c sm_amiga_srsts_i_0_m2_1__un3_n N_188 \ -sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_cpu_est_11_3__n \ -sm_amiga_srsts_i_0_m2_1__un0_n N_197 cpu_est_0_3__un3_n N_198 VPA_c \ -cpu_est_0_3__un1_n pos_clk_cpu_est_11_1__n cpu_est_0_3__un0_n N_194 \ -cpu_est_0_2__un3_n N_192 RST_c cpu_est_0_2__un1_n N_191 cpu_est_0_2__un0_n \ -AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE G_161 G_159 \ -cpu_est_0_0_ G_165 G_166 G_167 G_149 G_147 G_145 G_143 G_141 G_139 G_137 \ -pos_clk_RST_DLY_5_iv_0_x2_0_ +UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_159 N_21_i bgack_030_int_0_un0_n N_157 \ +N_34_0 as_030_000_sync_0_un3_n N_158 N_20_i as_030_000_sync_0_un1_n \ +un1_rst_dly_i_m_1__n N_35_0 as_030_000_sync_0_un0_n N_138 N_16_i \ +ds_000_enable_0_un3_n N_88 N_39_0 ds_000_enable_0_un1_n N_256 N_13_i \ +ds_000_enable_0_un0_n vcc_n_n N_89 N_42_0 a0_dma_0_un3_n N_91 N_12_i \ +a0_dma_0_un1_n N_92 N_43_0 a0_dma_0_un0_n pos_clk_a0_dma_3_n N_8_i \ +size_dma_0_1__un3_n gnd_n_n N_96 N_46_0 size_dma_0_1__un1_n \ +un1_amiga_bus_enable_low N_72 N_76_i size_dma_0_1__un0_n un6_as_030 N_97 \ +N_72_0 size_dma_0_0__un3_n un3_size N_116 UDS_000_c_i size_dma_0_0__un1_n \ +un4_size N_104 LDS_000_c_i size_dma_0_0__un0_n un5_ciin N_76 N_256_i \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n un8_ciin pos_clk_size_dma_6_1__n \ +pos_clk_un5_bgack_030_int_d_i_n un1_amiga_bus_enable_dma_high_i_m2_0__un1_n \ +un4_as_000 pos_clk_size_dma_6_0__n pos_clk_un24_bgack_030_int_i_0_0_n \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n un1_SM_AMIGA_7 N_250 N_104_i \ +cpu_est_0_1__un3_n un21_fpu_cs pos_clk_un6_bgack_000_n N_252_0 \ +cpu_est_0_1__un1_n un22_berr N_251 N_251_0 cpu_est_0_1__un0_n un6_ds_030 N_252 \ +pos_clk_un6_bgack_000_0_n cpu_est_0_2__un3_n un6_uds_000 \ +pos_clk_un5_bgack_030_int_d_n N_97_i cpu_est_0_2__un1_n un6_lds_000 N_96_i \ +cpu_est_0_2__un0_n DS_000_ENABLE_1_sqmuxa_1 N_250_0 cpu_est_0_3__un3_n \ +un22_berr_1 N_89_i cpu_est_0_3__un1_n N_8 pos_clk_size_dma_6_0_0__n \ +cpu_est_0_3__un0_n N_12 N_88_i ipl_030_0_0__un3_n N_13 \ +pos_clk_size_dma_6_0_1__n ipl_030_0_0__un1_n N_16 N_138_0 ipl_030_0_0__un0_n \ +N_20 un1_rst_dly_i_m_i_1__n ipl_030_0_1__un3_n N_21 ipl_030_0_1__un1_n N_11 \ +N_157_i ipl_030_0_1__un0_n un1_amiga_bus_enable_low_i N_158_i \ +ipl_030_0_2__un3_n un21_fpu_cs_i N_159_i ipl_030_0_2__un1_n BGACK_030_INT_i \ +ipl_030_0_2__un0_n AMIGA_BUS_ENABLE_DMA_LOW_i N_257_0 dsack1_int_0_un3_n \ +AS_030_i un1_as_000_i dsack1_int_0_un1_n AS_000_INT_i N_93_i \ +dsack1_int_0_un0_n N_105_i as_000_int_0_un3_n N_91_i N_87_i as_000_int_0_un1_n \ +N_92_i N_86_i as_000_int_0_un0_n a_i_19__n AMIGA_BUS_DATA_DIR_c_0 \ +lds_000_int_0_un3_n a_i_18__n un1_rst_dly_i_m_i_2__n lds_000_int_0_un1_n \ +a_i_16__n lds_000_int_0_un0_n size_dma_i_1__n un1_rst_dly_i_m_i_3__n \ +rw_000_int_0_un3_n size_dma_i_0__n rw_000_int_0_un1_n FPU_SENSE_i \ +un1_rst_dly_i_m_i_4__n rw_000_int_0_un0_n CLK_000_D1_i uds_000_int_0_un3_n \ +CLK_000_D0_i un1_rst_dly_i_m_i_5__n uds_000_int_0_un1_n AS_030_000_SYNC_i \ +uds_000_int_0_un0_n AS_030_D0_i un1_rst_dly_i_m_i_6__n vma_int_0_un3_n \ +sm_amiga_i_i_7__n vma_int_0_un1_n AS_000_i un1_rst_dly_i_m_i_7__n \ +vma_int_0_un0_n CLK_000_PE_i bg_000_0_un3_n nEXP_SPACE_D0_i \ +un1_rst_dly_i_m_i_8__n bg_000_0_un1_n A1_i bg_000_0_un0_n sm_amiga_i_6__n \ +un3_as_030_i ds_000_dma_0_un3_n pos_clk_un6_bg_030_n BERR_i un1_as_030_i \ +ds_000_dma_0_un1_n sm_amiga_i_5__n clk_000_n_sync_i_10__n ds_000_dma_0_un0_n \ +RESET_OUT_0_sqmuxa_i pos_clk_un9_clk_000_n_sync_i_n as_000_dma_0_un3_n \ +un1_rst_dly_i_1__n pos_clk_un14_clk_000_n_sync_0_n as_000_dma_0_un1_n \ +RESET_OUT_i CLK_EXP_c_i as_000_dma_0_un0_n pos_clk_clk_000_n_sync_2_0__n \ +RW_000_i N_244_0 a_15__n pos_clk_ipl_n un1_rst_dly_i_2__n N_83_i \ +pos_clk_un3_ds_030_d0_n un1_rst_dly_i_3__n N_115_0 a_14__n un1_rst_dly_i_4__n \ +N_84_i un1_rst_dly_i_5__n N_245_0 a_13__n un1_rst_dly_i_6__n N_85_i \ +un1_rst_dly_i_7__n pos_clk_ds_000_dma_4_0_n a_12__n un1_rst_dly_i_8__n N_94_i \ +CLK_OUT_PRE_D_i a_11__n pos_clk_un11_clk_000_n_sync_i_n CLK_030_H_i a_10__n \ +AS_000_DMA_i N_73_0 pos_clk_un8_bg_030_n VMA_INT_i a_9__n VPA_D_i N_160_i \ +cpu_est_i_0__n N_161_i a_8__n cpu_est_i_1__n cpu_est_i_3__n N_155_i a_7__n \ +a_i_24__n N_156_i pos_clk_un7_clk_000_d0_i_n a_6__n sm_amiga_i_0__n N_154_i \ +sm_amiga_i_3__n N_152_i a_5__n CLK_000_NE_i N_153_i cpu_est_i_2__n a_4__n \ +sm_amiga_i_1__n N_150_i sm_amiga_i_4__n N_151_i a_3__n sm_amiga_i_2__n \ +pos_clk_un29_clk_000_ne_d0_i_n N_149_i a_2__n DSACK1_INT_0_sqmuxa_i N_147_i \ +RW_i N_148_i un5_ciin_i DTACK_D0_i N_164_i a_i_31__n N_165_i a_i_29__n N_163_i \ +a_i_30__n N_199_i a_i_27__n pos_clk_cpu_est_11_0_3__n pos_clk_un7_clk_000_pe_n \ +a_i_28__n N_197_i a_i_25__n N_198_i DS_000_ENABLE_1_sqmuxa a_i_26__n N_194_i \ +UDS_000_INT_i pos_clk_cpu_est_11_0_1__n LDS_000_INT_i N_192_i DS_030_i N_135_i \ +N_224_i N_162_i N_225_i N_191_i AS_000_INT_1_sqmuxa N_226_i N_193_i \ +DSACK1_INT_1_sqmuxa N_190_i pos_clk_ds_000_dma_4_n N_189_i N_3 \ +DS_000_ENABLE_1_sqmuxa_i N_188_i un6_lds_000_i N_195_i un6_uds_000_i N_196_i \ +N_6 un6_ds_030_i N_186_i N_9 DS_000_DMA_i N_143_0 N_10 un4_as_000_i N_142_0 \ +N_14 un8_ciin_i N_141_0 N_15 un6_as_030_i N_140_0 N_17 DS_030_D0_i N_139_0 \ +N_19 AS_030_c N_166_i N_22 N_137_i N_23 AS_000_c N_136_i N_24 N_133_i N_25 \ +RW_000_c N_132_i N_146_i DS_030_c N_144_i UDS_000_c un1_SM_AMIGA_7_i \ +pos_clk_un21_clk_000_ne_d0_i_n LDS_000_c pos_clk_un27_clk_000_ne_d0_i_n \ +pos_clk_un23_clk_000_ne_d0_0_n size_c_0__n pos_clk_un5_clk_000_pe_i_n \ +pos_clk_un9_clk_000_ne_i_n size_c_1__n pos_clk_un7_clk_000_pe_0_n \ +pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 \ +N_23_i N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 \ +DTACK_c_i N_57_0 VPA_c_i N_56_0 nEXP_SPACE_c_i N_55_0 N_115 N_50_0 \ +pos_clk_cpu_est_11_1__n N_3_i pos_clk_cpu_est_11_3__n N_49_0 N_220 N_6_i \ +N_48_0 N_9_i N_45_0 un6_uds_000_1 N_10_i pos_clk_un24_bgack_030_int_i_0_n \ +a_c_16__n N_44_0 N_244 N_14_i N_245 a_c_17__n N_41_0 N_15_i N_80 a_c_18__n \ +N_40_0 N_90 N_17_i N_100 a_c_19__n N_38_0 N_105 N_19_i \ +pos_clk_un11_clk_000_n_sync_n a_c_20__n N_36_0 N_22_i a_c_21__n N_33_0 N_135 \ +BG_030_c_i N_133 a_c_22__n pos_clk_un6_bg_030_i_n N_190 pos_clk_un8_bg_030_0_n \ +N_188 a_c_23__n N_127_i_1 N_189 N_127_i_2 N_136 a_c_24__n \ +pos_clk_un11_ds_030_d0_i_1_n pos_clk_un7_clk_000_d0_n N_135_i_1 \ +pos_clk_un29_clk_000_ne_d0_n a_c_25__n pos_clk_cpu_est_11_0_1_1__n \ +DSACK1_INT_0_sqmuxa pos_clk_cpu_est_11_0_2_1__n pos_clk_un21_clk_000_ne_d0_n \ +a_c_26__n pos_clk_cpu_est_11_0_1_3__n pos_clk_un5_clk_000_pe_n N_195_1 \ +pos_clk_un9_clk_000_ne_n a_c_27__n N_196_1 pos_clk_un23_clk_000_ne_d0_n \ +N_131_i_1 pos_clk_un27_clk_000_ne_d0_n a_c_28__n N_131_i_2 \ +pos_clk_un14_clk_000_n_sync_n N_131_i_3 N_144 a_c_29__n N_119_i_1 N_146 \ +N_119_i_2 N_143 a_c_30__n N_121_i_1 N_147 N_123_i_1 N_139 a_c_31__n N_123_i_2 \ +N_148 N_125_i_1 N_149 A0_c N_129_i_1 N_150 N_162_1 N_140 A1_c N_163_1 N_151 \ +N_165_1 N_152 nEXP_SPACE_c N_165_2 N_153 N_165_3 N_154 BERR_c un5_ciin_1 N_155 \ +un5_ciin_2 N_141 BG_030_c un5_ciin_3 N_156 un5_ciin_4 N_160 un5_ciin_5 N_142 \ +un5_ciin_6 N_161 un5_ciin_7 N_164 BGACK_000_c un5_ciin_8 N_166 un5_ciin_9 \ +N_132 un5_ciin_10 N_191 un5_ciin_11 N_192 pos_clk_un9_clk_000_ne_1_n N_193 \ +CLK_OSZI_c pos_clk_un9_clk_000_ne_2_n N_194 pos_clk_un9_clk_000_ne_3_n N_197 \ +pos_clk_un9_clk_000_ne_4_n N_198 CLK_EXP_c pos_clk_un5_clk_000_pe_1_n N_195 \ +pos_clk_un5_clk_000_pe_2_n N_196 pos_clk_un5_clk_000_pe_3_n N_162 FPU_SENSE_c \ +pos_clk_un27_clk_000_ne_d0_1_n N_199 pos_clk_un27_clk_000_ne_d0_2_n N_199_1 \ +pos_clk_un27_clk_000_ne_d0_3_n N_163 RESET_OUT_0_sqmuxa_7_1 N_165 \ +RESET_OUT_0_sqmuxa_7_2 N_73 RESET_OUT_0_sqmuxa_7_3 N_94 RESET_OUT_0_sqmuxa_5_1 \ +N_85 N_87_1 N_84 ipl_c_0__n N_87_2 N_83 pos_clk_un24_bgack_030_int_i_0_0_1_n \ +pos_clk_un9_clk_000_n_sync_n ipl_c_1__n pos_clk_un24_bgack_030_int_i_0_0_2_n \ +N_72_0_1 ipl_c_2__n pos_clk_un7_clk_000_d0_1_n N_213 un21_fpu_cs_1 \ +un22_berr_1_0 N_211 DTACK_c N_116_1 N_116_2 N_209 N_116_3 N_116_4 VPA_c \ +pos_clk_un6_bg_030_1_n N_205 N_115_0_1 N_245_0_1 RESET_OUT_0_sqmuxa_1 RST_c \ +N_247_i_1 RESET_OUT_0_sqmuxa N_248_i_1 RESET_OUT_0_sqmuxa_7 N_249_i_1 \ +RESET_OUT_0_sqmuxa_5 RW_c pos_clk_ipl_1_n un1_rst_dly_i_m_8__n \ +amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n fc_c_0__n \ +amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n \ +amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n fc_c_1__n \ +amiga_bus_enable_dma_low_0_un3_n un1_rst_dly_i_m_4__n \ +amiga_bus_enable_dma_low_0_un1_n un1_rst_dly_i_m_3__n \ +amiga_bus_enable_dma_low_0_un0_n un1_rst_dly_i_m_2__n AMIGA_BUS_DATA_DIR_c \ +rw_000_dma_0_un3_n N_86 rw_000_dma_0_un1_n N_93 rw_000_dma_0_un0_n N_87 \ +bgack_030_int_0_un3_n bgack_030_int_0_un1_n AS_030.OE AS_000.OE RW_000.OE \ +DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ +CLK_DIV_OUT.OE DSACK1.OE CIIN.OE pos_clk_un24_bgack_030_int_i_0_x2 \ +cpu_est_0_0_ G_165 G_166 G_167 pos_clk_CYCLE_DMA_5_1_i_x2 \ +pos_clk_CYCLE_DMA_5_0_i_x2 G_149 G_147 G_145 G_143 G_141 G_139 G_137 G_135 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_52_0.BLIF IPL_D0_0_.D +0 1 +.names N_53_0.BLIF IPL_D0_1_.D +0 1 .names N_54_0.BLIF IPL_D0_2_.D 0 1 .names N_131_i_3.BLIF N_165_i.BLIF SM_AMIGA_i_7_.D @@ -527,9 +516,9 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 11 1 .names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 -.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_119_i_1.BLIF N_119_i_2.BLIF SM_AMIGA_1_.D 11 1 -.names N_88_i.BLIF N_137_i.BLIF SM_AMIGA_0_.D +.names N_137_i.BLIF N_146_i.BLIF SM_AMIGA_0_.D 11 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 @@ -544,13 +533,7 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 0 1 .names N_31_0.BLIF IPL_030DFF_1_reg.D 0 1 -.names N_32_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names N_52_0.BLIF IPL_D0_0_.D -0 1 -.names N_53_0.BLIF IPL_D0_1_.D -0 1 -.names N_85_i.BLIF RST_c.BLIF RST_DLY_0_.D +.names RST_c.BLIF un1_rst_dly_i_m_i_1__n.BLIF RST_DLY_0_.D 11 1 .names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D 11 1 @@ -566,9 +549,9 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 11 1 .names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D 11 1 -.names G_159.BLIF un1_rst_2.BLIF CYCLE_DMA_0_.D +.names N_249_i_1.BLIF N_257_0.BLIF CYCLE_DMA_0_.D 11 1 -.names G_161.BLIF un1_rst_2.BLIF CYCLE_DMA_1_.D +.names N_248_i_1.BLIF N_257_0.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -578,7 +561,19 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ -1 1 .names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D 11 1 -.names N_42_0.BLIF inst_LDS_000_INT.D +.names N_247_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_93_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D +11 1 +.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_39_0.BLIF inst_RW_000_DMA.D +0 1 +.names N_40_0.BLIF inst_RW_000_INT.D +0 1 +.names N_41_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_42_0.BLIF inst_BGACK_030_INTreg.D 0 1 .names N_43_0.BLIF inst_AS_030_000_SYNC.D 0 1 @@ -594,7 +589,7 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 0 1 .names N_50_0.BLIF inst_DS_030_D0.D 0 1 -.names N_89.BLIF inst_AS_030_D0.D +.names N_90.BLIF inst_AS_030_D0.D 0 1 .names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D 0 1 @@ -602,741 +597,716 @@ pos_clk_RST_DLY_5_iv_0_x2_0_ 0 1 .names N_57_0.BLIF inst_DTACK_D0.D 0 1 -.names N_47.BLIF RST_c.BLIF inst_CLK_030_H.D -11 1 -.names N_38.BLIF RST_c.BLIF inst_RESET_OUTreg.D -11 1 -.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_33_0.BLIF inst_BGACK_030_INTreg.D +.names N_33_0.BLIF BG_000DFFreg.D 0 1 -.names N_34_0.BLIF BG_000DFFreg.D +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 -.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +.names N_36_0.BLIF inst_VMA_INTreg.D 0 1 -.names N_37_0.BLIF inst_VMA_INTreg.D +.names N_38_0.BLIF inst_UDS_000_INT.D 0 1 -.names N_39_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_40_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_41_0.BLIF inst_RW_000_INT.D -0 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D +.names N_257_0.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_189_i.BLIF cpu_est_0_.BLIF N_193 +.names CLK_000_PE_i.BLIF sm_amiga_i_5__n.BLIF N_159 11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +.names N_21.BLIF N_21_i 0 1 -.names N_190_i.BLIF N_190 -0 1 -.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n 11 1 -.names N_189_i.BLIF N_189 -0 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names N_138.BLIF sm_amiga_i_6__n.BLIF N_157 11 1 -.names N_140_0.BLIF N_140 -0 1 -.names N_97.BLIF bgack_030_int_0_un3_n -0 1 -.names inst_CLK_000_NE_D0.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF \ -pos_clk_un29_clk_000_ne_d0_n +.names N_21_i.BLIF RST_c.BLIF N_34_0 11 1 -.names inst_BGACK_030_INTreg.BLIF N_97.BLIF bgack_030_int_0_un1_n -11 1 -.names pos_clk_un23_clk_000_ne_d0_0_n.BLIF pos_clk_un23_clk_000_ne_d0_n +.names N_250.BLIF as_030_000_sync_0_un3_n 0 1 -.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_158 11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un21_clk_000_ne_d0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m4_0__un3_n +.names N_20.BLIF N_20_i 0 1 +.names inst_AS_030_000_SYNC.BLIF N_250.BLIF as_030_000_sync_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_1__n.BLIF un1_rst_dly_i_m_1__n +11 1 +.names N_20_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_105_i.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names N_138_0.BLIF N_138 +0 1 +.names N_16.BLIF N_16_i +0 1 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names BGACK_030_INT_i.BLIF N_256_i.BLIF N_88 +11 1 +.names N_16_i.BLIF RST_c.BLIF N_39_0 +11 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ +ds_000_enable_0_un1_n +11 1 +.names N_256_i.BLIF N_256 +0 1 +.names N_13.BLIF N_13_i +0 1 +.names un1_SM_AMIGA_7_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 .names vcc_n_n 1 -.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n -0 1 -.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un1_n +.names BGACK_030_INT_i.BLIF N_256.BLIF N_89 11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un0_n +.names N_13_i.BLIF RST_c.BLIF N_42_0 11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names SM_AMIGA_5_.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n -0 1 -.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n -11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un1_n -11 1 -.names gnd_n_n -.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \ -pos_clk_un9_clk_000_n_sync_n -11 1 -.names sm_amiga_i_3__n.BLIF ds_000_enable_1_sqmuxa_1_i_m4_un3_n.BLIF \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ -un1_amiga_bus_enable_low -11 1 -.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n -0 1 -.names N_246.BLIF size_dma_0_0__un3_n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 -11 1 -.names pos_clk_un22_bgack_030_int_0_n.BLIF pos_clk_un22_bgack_030_int_n -0 1 -.names N_6.BLIF N_6_i -0 1 -.names pos_clk_size_dma_6_0__n.BLIF N_246.BLIF size_dma_0_0__un1_n -11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names N_6_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 -11 1 -.names N_3.BLIF N_3_i -0 1 -.names N_246.BLIF size_dma_0_1__un3_n -0 1 -.names un8_ciin_8.BLIF un8_ciin_5.BLIF un8_ciin -11 1 -.names N_3_i.BLIF RST_c.BLIF N_49_0 -11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_246.BLIF size_dma_0_1__un1_n -11 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF un14_amiga_bus_data_dir -11 1 -.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF pos_clk_un40_bgack_030_int_1_n -11 1 -.names pos_clk_un29_bgack_030_int_n.BLIF pos_clk_un29_bgack_030_int_i_n -0 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names AS_000_DMA_1_sqmuxa.BLIF AS_000_DMA_i.BLIF CLK_030_H_0_sqmuxa -11 1 -.names pos_clk_un26_bgack_030_int_n.BLIF pos_clk_un26_bgack_030_int_i_n -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 -.names CLK_EXP_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa -11 1 -.names pos_clk_un26_bgack_030_int_i_n.BLIF pos_clk_un29_bgack_030_int_i_n.BLIF \ -pos_clk_un27_bgack_030_int_0_n -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names un22_berr_1_0.BLIF N_116.BLIF un22_berr -11 1 -.names pos_clk_un24_bgack_030_int_1_n.BLIF pos_clk_un27_bgack_030_int_n.BLIF \ -pos_clk_un24_bgack_030_int_n -11 1 -.names CLK_030_H_0_sqmuxa.BLIF CLK_030_H_0_sqmuxa_i -0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names pos_clk_un27_bgack_030_int_0_n.BLIF pos_clk_un27_bgack_030_int_n -0 1 -.names N_7.BLIF N_7_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_176_1 -11 1 -.names CLK_030_H_0_sqmuxa_i.BLIF N_7_i.BLIF N_47_0 -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 -11 1 -.names N_165_3.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_165 -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_133_i -11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_133_i.BLIF N_133 -0 1 -.names N_176.BLIF N_176_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names N_163_1.BLIF CLK_000_NE_i.BLIF N_163 -11 1 -.names N_175.BLIF N_175_i -0 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names N_162_1.BLIF CLK_000_PE_i.BLIF N_162 -11 1 -.names N_175_i.BLIF N_176_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names BERR_i.BLIF N_136_i.BLIF N_164 -11 1 -.names AS_000_DMA_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF \ -pos_clk_ds_000_dma_4_f1_0_n -11 1 -.names N_242.BLIF dsack1_int_0_un3_n -0 1 -.names N_176_1_0.BLIF nEXP_SPACE_D0_i.BLIF N_176 -11 1 -.names N_162.BLIF N_162_i -0 1 -.names N_80_i.BLIF N_242.BLIF dsack1_int_0_un1_n -11 1 -.names DS_000_DMA_2_sqmuxa_1.BLIF pos_clk_un40_bgack_030_int_1_i_n.BLIF \ -DS_000_DMA_2_sqmuxa -11 1 -.names N_163.BLIF N_163_i -0 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names DS_000_DMA_0_sqmuxa_i.BLIF pos_clk_ds_000_dma_4_f1_n.BLIF \ -pos_clk_ds_000_dma_4_n -11 1 -.names N_164.BLIF N_164_i -0 1 -.names N_243.BLIF as_000_int_0_un3_n -0 1 -.names RW_000_c.BLIF pos_clk_un24_bgack_030_int_n.BLIF DS_000_DMA_0_sqmuxa -11 1 -.names N_165.BLIF N_165_i -0 1 -.names sm_amiga_i_5__n.BLIF N_243.BLIF as_000_int_0_un1_n -11 1 -.names pos_clk_ds_000_dma_4_f1_0_n.BLIF pos_clk_ds_000_dma_4_f1_n -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_175 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_0_n -11 1 -.names N_241.BLIF ds_000_enable_0_un3_n -0 1 -.names N_47_0.BLIF N_47 -0 1 -.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n -0 1 -.names N_248_i.BLIF N_241.BLIF ds_000_enable_0_un1_n -11 1 -.names inst_CLK_030_H.BLIF pos_clk_un24_bgack_030_int_n.BLIF N_7 -11 1 -.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n -0 1 -.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ -ds_000_enable_0_un0_n -11 1 -.names N_176_1.BLIF RST_c.BLIF un1_rst_2 -11 1 -.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ -pos_clk_un14_clk_000_n_sync_0_n -11 1 -.names N_244.BLIF as_030_000_sync_0_un3_n -0 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_0__n.BLIF pos_clk_un26_bgack_030_int_n -11 1 -.names N_22.BLIF N_22_i -0 1 -.names inst_AS_030_000_SYNC.BLIF N_244.BLIF as_030_000_sync_0_un1_n -11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_1__n.BLIF pos_clk_un29_bgack_030_int_n -11 1 -.names N_22_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_18.BLIF N_18_i -0 1 -.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_18_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ -lds_000_int_0_un1_n -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names pos_clk_un9_clk_000_ne_n.BLIF pos_clk_un9_clk_000_ne_i_n -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names pos_clk_un5_clk_000_pe_n.BLIF pos_clk_un5_clk_000_pe_i_n -0 1 -.names N_115.BLIF rw_000_int_0_un3_n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ -pos_clk_un7_clk_000_pe_0_n -11 1 -.names N_245.BLIF N_115.BLIF rw_000_int_0_un1_n -11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names pos_clk_un27_clk_000_ne_d0_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n -0 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names pos_clk_un24_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_n -0 1 -.names pos_clk_un21_clk_000_ne_d0_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n -0 1 -.names pos_clk_un21_clk_000_ne_d0_i_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF \ -pos_clk_un23_clk_000_ne_d0_0_n -11 1 -.names un14_amiga_bus_data_dir_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -rw_000_dma_0_un1_n -11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names SM_AMIGA_3_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_136_i -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_132_i.BLIF SM_AMIGA_2_.BLIF N_140_0 -11 1 -.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n -0 1 -.names CLK_EXP_c.BLIF CLK_EXP_i -0 1 -.names N_195.BLIF N_195_i -0 1 -.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n -11 1 -.names BERR_c.BLIF BERR_i -0 1 -.names N_196.BLIF N_196_i -0 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_195_i.BLIF N_196_i.BLIF N_186_i -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names DS_000_DMA_0_sqmuxa.BLIF DS_000_DMA_0_sqmuxa_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_188_i -11 1 -.names N_90_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_low_0_un1_n -11 1 -.names pos_clk_un40_bgack_030_int_1_n.BLIF pos_clk_un40_bgack_030_int_1_i_n -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_189_i -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_190_i -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i -0 1 -.names N_193.BLIF N_193_i -0 1 -.names N_91_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -amiga_bus_enable_dma_high_0_un1_n -11 1 -.names inst_CLK_000_PE.BLIF CLK_000_PE_i -0 1 -.names N_191.BLIF N_191_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names inst_CLK_000_NE.BLIF CLK_000_NE_i -0 1 -.names N_192.BLIF N_192_i -0 1 -.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_194.BLIF N_194_i -0 1 -.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \ -pos_clk_cpu_est_11_0_1__n -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names pos_clk_un7_clk_000_d0_n.BLIF pos_clk_un7_clk_000_d0_i_n -0 1 -.names N_198.BLIF N_198_i -0 1 .names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n 0 1 -.names UDS_000_c.BLIF UDS_000_i -0 1 -.names N_197.BLIF N_197_i +.names A1_c.BLIF BGACK_030_INT_i.BLIF N_91 +11 1 +.names N_12.BLIF N_12_i 0 1 .names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ a0_dma_0_un1_n 11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names N_199.BLIF N_199_i -0 1 +.names A1_i.BLIF BGACK_030_INT_i.BLIF N_92 +11 1 +.names N_12_i.BLIF RST_c.BLIF N_43_0 +11 1 .names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF pos_clk_clk_000_n_sync_2_0__n +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 -.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +.names N_8.BLIF N_8_i 0 1 -.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_198_i.BLIF pos_clk_cpu_est_11_0_3__n +.names N_252.BLIF size_dma_0_1__un3_n +0 1 +.names gnd_n_n +.names N_72.BLIF N_105.BLIF N_96 11 1 -.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +.names N_8_i.BLIF RST_c.BLIF N_46_0 11 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names N_151.BLIF N_151_i -0 1 -.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +.names pos_clk_size_dma_6_1__n.BLIF N_252.BLIF size_dma_0_1__un1_n 11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_150.BLIF N_150_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ +un1_amiga_bus_enable_low 11 1 -.names pos_clk_un29_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_i_n +.names N_72_0.BLIF N_72 0 1 -.names N_135_i_1.BLIF sm_amiga_i_6__n.BLIF N_135_i +.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_76_i 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_252_0 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names N_85.BLIF N_85_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_38_0 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n -0 1 -.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i -0 1 -.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n -0 1 -.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_77_i_i -0 1 -.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n -0 1 -.names G_137.BLIF un1_rst_dly_i_2__n -0 1 -.names G_139.BLIF un1_rst_dly_i_3__n -0 1 -.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n -0 1 -.names G_141.BLIF un1_rst_dly_i_4__n -0 1 -.names G_143.BLIF un1_rst_dly_i_5__n -0 1 -.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n -0 1 -.names G_145.BLIF un1_rst_dly_i_6__n -0 1 -.names G_147.BLIF un1_rst_dly_i_7__n -0 1 -.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n -0 1 -.names G_149.BLIF un1_rst_dly_i_8__n -0 1 -.names inst_RESET_OUTreg.BLIF RESET_OUT_i -0 1 -.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names inst_RESET_OUTreg.BLIF un1_as_030_i.BLIF un3_as_030_i +.names N_105.BLIF N_116.BLIF N_97 11 1 -.names A1_c.BLIF A1_i -0 1 -.names N_76.BLIF N_76_i -0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names N_83.BLIF N_83_i -0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_248.BLIF N_248_i -0 1 -.names N_84.BLIF N_84_i -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +.names N_72_0_1.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_72_0 11 1 -.names RW_c.BLIF RW_i +.names N_252.BLIF size_dma_0_0__un3_n 0 1 -.names N_86.BLIF N_86_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names N_86_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_87.BLIF N_87_i -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_87_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +.names N_116_4.BLIF N_116_3.BLIF N_116 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names UDS_000_c.BLIF UDS_000_c_i 0 1 -.names N_88.BLIF N_88_i -0 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names N_248.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_241_0 +.names pos_clk_size_dma_6_0__n.BLIF N_252.BLIF size_dma_0_0__un1_n 11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names N_80_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_242_0 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size 11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_243_0 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_104 11 1 -.names a_c_18__n.BLIF a_i_18__n +.names LDS_000_c.BLIF LDS_000_c_i 0 1 -.names N_93.BLIF N_93_i -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names N_94.BLIF N_94_i -0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names N_93_i.BLIF N_94_i.BLIF N_244_0 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n 11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF N_245_0 +.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin 11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +.names N_76_i.BLIF N_76 0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_246_0 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_256_i 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF un8_ciin 11 1 -.names a_c_26__n.BLIF a_i_26__n +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n 0 1 .names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ pos_clk_un5_bgack_030_int_d_i_n 11 1 -.names a_c_27__n.BLIF a_i_27__n +.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un1_n +11 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 +11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n 0 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF N_249_i +.names pos_clk_un24_bgack_030_int_i_0_0_1_n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_0_2_n.BLIF pos_clk_un24_bgack_030_int_i_0_0_n 11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n 11 1 -.names a_c_24__n.BLIF a_i_24__n +.names un1_SM_AMIGA_7_i.BLIF un1_SM_AMIGA_7 0 1 -.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0 -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_71_0 -11 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i +.names N_250_0.BLIF N_250 0 1 .names N_104.BLIF N_104_i 0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_252_0 +11 1 +.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names un22_berr_1_0.BLIF N_116.BLIF un22_berr +11 1 +.names N_251_0.BLIF N_251 +0 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_251_0 +11 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_252_0.BLIF N_252 +0 1 +.names BGACK_000_c.BLIF N_76.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n +0 1 +.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000 +11 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names N_97.BLIF N_97_i +0 1 +.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +11 1 +.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000 +11 1 +.names N_96.BLIF N_96_i +0 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_105.BLIF un1_SM_AMIGA_7.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names N_96_i.BLIF N_97_i.BLIF N_250_0 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names N_89.BLIF N_89_i +0 1 +.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 .names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8 1- 1 -1 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names N_104_i.BLIF RST_c.BLIF N_137_i +.names N_89_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 -1- 1 --1 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 -1- 1 --1 1 -.names G_165.BLIF N_224_i -0 1 -.names N_160.BLIF N_160_i -0 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 -1- 1 --1 1 -.names G_166.BLIF N_225_i -0 1 -.names N_161.BLIF N_161_i -0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12 1- 1 -1 1 -.names G_167.BLIF N_226_i +.names N_88.BLIF N_88_i 0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names N_159.BLIF N_159_i +.names N_88_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_138_0 +11 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names un1_rst_dly_i_m_1__n.BLIF un1_rst_dly_i_m_i_1__n 0 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11 1- 1 -1 1 .names N_157.BLIF N_157_i 0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15 -1- 1 --1 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 .names N_158.BLIF N_158_i 0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16 -1- 1 --1 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names N_159.BLIF N_159_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_257_0 +11 1 +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n +0 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i +11 1 +.names inst_DSACK1_INTreg.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_93.BLIF N_93_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names N_105.BLIF N_105_i +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 .names N_91.BLIF N_91_i 0 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_90.BLIF N_90_i +.names N_87.BLIF N_87_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names N_92.BLIF N_92_i +0 1 +.names N_86.BLIF N_86_i +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names N_86_i.BLIF N_87_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n +0 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n +0 1 +.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \ +lds_000_int_0_un1_n +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n +0 1 +.names N_115.BLIF rw_000_int_0_un3_n +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_115.BLIF rw_000_int_0_un1_n +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n +0 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n +0 1 +.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n +0 1 +.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names inst_CLK_000_PE.BLIF CLK_000_PE_i +0 1 +.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i +0 1 +.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n +0 1 +.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names A1_c.BLIF A1_i +0 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names inst_RESET_OUTreg.BLIF un1_as_030_i.BLIF un3_as_030_i +11 1 +.names N_245.BLIF ds_000_dma_0_un3_n +0 1 +.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i +11 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_245.BLIF ds_000_dma_0_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n +0 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i +0 1 +.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n +0 1 +.names N_244.BLIF as_000_dma_0_un3_n +0 1 +.names G_135.BLIF un1_rst_dly_i_1__n +0 1 +.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \ +pos_clk_un14_clk_000_n_sync_0_n +11 1 +.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_244.BLIF as_000_dma_0_un1_n +11 1 +.names inst_RESET_OUTreg.BLIF RESET_OUT_i +0 1 +.names CLK_EXP_c.BLIF CLK_EXP_c_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF pos_clk_clk_000_n_sync_2_0__n +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF N_244_0 +11 1 +.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +11 1 +.names G_137.BLIF un1_rst_dly_i_2__n +0 1 +.names N_83.BLIF N_83_i +0 1 +.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n +11 1 +.names G_139.BLIF un1_rst_dly_i_3__n +0 1 +.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0 +11 1 +.names G_141.BLIF un1_rst_dly_i_4__n +0 1 +.names N_84.BLIF N_84_i +0 1 +.names G_143.BLIF un1_rst_dly_i_5__n +0 1 +.names N_245_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF N_245_0 +11 1 +.names G_145.BLIF un1_rst_dly_i_6__n +0 1 +.names N_85.BLIF N_85_i +0 1 +.names G_147.BLIF un1_rst_dly_i_7__n +0 1 +.names N_85_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names G_149.BLIF un1_rst_dly_i_8__n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_73_0 +11 1 +.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_160.BLIF N_160_i +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names N_161.BLIF N_161_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 .names N_155.BLIF N_155_i 0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names un14_amiga_bus_data_dir.BLIF un14_amiga_bus_data_dir_i +.names a_c_24__n.BLIF a_i_24__n 0 1 .names N_156.BLIF N_156_i 0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_80.BLIF N_80_i +.names pos_clk_un7_clk_000_d0_n.BLIF pos_clk_un7_clk_000_d0_i_n 0 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 -1- 1 --1 1 -.names un6_lds_000.BLIF un6_lds_000_i +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n 0 1 .names N_154.BLIF N_154_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 -1- 1 --1 1 -.names un6_uds_000.BLIF un6_uds_000_i +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 .names N_152.BLIF N_152_i 0 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +.names inst_CLK_000_NE.BLIF CLK_000_NE_i +0 1 +.names N_153.BLIF N_153_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_150.BLIF N_150_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_151.BLIF N_151_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names pos_clk_un29_clk_000_ne_d0_n.BLIF pos_clk_un29_clk_000_ne_d0_i_n +0 1 +.names N_149.BLIF N_149_i +0 1 +.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i +0 1 +.names N_147.BLIF N_147_i +0 1 +.names RW_c.BLIF RW_i +0 1 +.names N_148.BLIF N_148_i +0 1 +.names un5_ciin.BLIF un5_ciin_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_164.BLIF N_164_i +0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names N_165.BLIF N_165_i +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names N_163.BLIF N_163_i +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names N_199.BLIF N_199_i +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_198_i.BLIF pos_clk_cpu_est_11_0_3__n +11 1 +.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n +0 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names N_197.BLIF N_197_i +0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names N_198.BLIF N_198_i +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names N_194.BLIF N_194_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \ +pos_clk_cpu_est_11_0_1__n +11 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_192.BLIF N_192_i +0 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names N_135_i_1.BLIF sm_amiga_i_6__n.BLIF N_135_i +11 1 +.names G_165.BLIF N_224_i +0 1 +.names N_162.BLIF N_162_i +0 1 +.names G_166.BLIF N_225_i +0 1 +.names N_191.BLIF N_191_i +0 1 +.names N_105.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names G_167.BLIF N_226_i +0 1 +.names N_193.BLIF N_193_i +0 1 +.names DSACK1_INT_0_sqmuxa_i.BLIF N_105.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_190_i +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_189_i +11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i +0 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_188_i +11 1 +.names un6_lds_000.BLIF un6_lds_000_i +0 1 +.names N_195.BLIF N_195_i +0 1 +.names un6_uds_000.BLIF un6_uds_000_i +0 1 +.names N_196.BLIF N_196_i +0 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6 1- 1 -1 1 .names un6_ds_030.BLIF un6_ds_030_i 0 1 -.names N_153.BLIF N_153_i +.names N_195_i.BLIF N_196_i.BLIF N_186_i +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9 +1- 1 +-1 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i 0 1 +.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_143_0 +11 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 .names un4_as_000.BLIF un4_as_000_i 0 1 .names N_132_i.BLIF SM_AMIGA_6_.BLIF N_142_0 11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_14 +1- 1 +-1 1 +.names un8_ciin.BLIF un8_ciin_i 0 1 .names N_132_i.BLIF SM_AMIGA_4_.BLIF N_141_0 11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_15 +1- 1 +-1 1 .names un6_as_030.BLIF un6_as_030_i 0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_138_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names BERR_c.BLIF CLK_000_PE_i.BLIF N_132_i +.names N_132_i.BLIF SM_AMIGA_2_.BLIF N_140_0 11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 +1- 1 +-1 1 .names inst_DS_030_D0.BLIF DS_030_D0_i 0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i +.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_139_0 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names N_166.BLIF N_166_i +0 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_166_i.BLIF RST_c.BLIF N_137_i +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23 +1- 1 +-1 1 +.names SM_AMIGA_3_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_136_i +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24 +1- 1 +-1 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_133_i +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25 +1- 1 +-1 1 +.names BERR_c.BLIF CLK_000_PE_i.BLIF N_132_i +11 1 +.names N_146.BLIF N_146_i +0 1 +.names N_144.BLIF N_144_i +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_144_i.BLIF un1_SM_AMIGA_7_i +11 1 +.names pos_clk_un21_clk_000_ne_d0_n.BLIF pos_clk_un21_clk_000_ne_d0_i_n +0 1 +.names pos_clk_un27_clk_000_ne_d0_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n +0 1 +.names pos_clk_un21_clk_000_ne_d0_i_n.BLIF pos_clk_un27_clk_000_ne_d0_i_n.BLIF \ +pos_clk_un23_clk_000_ne_d0_0_n +11 1 +.names pos_clk_un5_clk_000_pe_n.BLIF pos_clk_un5_clk_000_pe_i_n +0 1 +.names pos_clk_un9_clk_000_ne_n.BLIF pos_clk_un9_clk_000_ne_i_n +0 1 +.names pos_clk_un5_clk_000_pe_i_n.BLIF pos_clk_un9_clk_000_ne_i_n.BLIF \ +pos_clk_un7_clk_000_pe_0_n 11 1 .names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF \ pos_clk_un11_ds_030_d0_i_n @@ -1381,399 +1351,402 @@ pos_clk_un11_ds_030_d0_i_n 0 1 .names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0 11 1 +.names N_115_0.BLIF N_115 +0 1 .names DS_030_i.BLIF RST_c.BLIF N_50_0 11 1 -.names N_8.BLIF N_8_i +.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n 0 1 -.names N_8_i.BLIF RST_c.BLIF N_46_0 +.names N_3.BLIF N_3_i +0 1 +.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n +0 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220 +11 1 +.names N_6.BLIF N_6_i +0 1 +.names N_6_i.BLIF RST_c.BLIF N_48_0 11 1 .names N_9.BLIF N_9_i 0 1 .names N_9_i.BLIF RST_c.BLIF N_45_0 11 1 +.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 +11 1 .names N_10.BLIF N_10_i 0 1 +.names pos_clk_un24_bgack_030_int_i_0_0_n.BLIF \ +pos_clk_un24_bgack_030_int_i_0_n +0 1 .names N_10_i.BLIF RST_c.BLIF N_44_0 11 1 -.names N_115_0.BLIF N_115 -0 1 -.names N_12.BLIF N_12_i -0 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names N_12_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names N_13.BLIF N_13_i -0 1 -.names N_13_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names N_14.BLIF N_14_i -0 1 -.names N_14_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1 -11 1 -.names N_15.BLIF N_15_i -0 1 -.names N_241_0.BLIF N_241 -0 1 -.names N_15_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names N_242_0.BLIF N_242 -0 1 -.names N_16.BLIF N_16_i -0 1 -.names N_243_0.BLIF N_243 -0 1 -.names N_16_i.BLIF RST_c.BLIF N_39_0 -11 1 .names N_244_0.BLIF N_244 0 1 -.names N_19.BLIF N_19_i +.names N_14.BLIF N_14_i 0 1 .names N_245_0.BLIF N_245 0 1 +.names N_14_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_15.BLIF N_15_i +0 1 +.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_80 +1- 1 +-1 1 +.names N_15_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_90 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_100 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF N_105 +11 1 +.names N_19.BLIF N_19_i +0 1 +.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n +11 1 .names N_19_i.BLIF RST_c.BLIF N_36_0 11 1 -.names N_246_0.BLIF N_246 +.names N_22.BLIF N_22_i 0 1 -.names N_20.BLIF N_20_i -0 1 -.names un1_amiga_bus_enable_dma_high_i_m4_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m4_0__un0_n.BLIF N_78 -1- 1 --1 1 -.names N_20_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_80 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_89 -11 1 -.names N_21_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names A1_c.BLIF BGACK_030_INT_i.BLIF N_90 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names A1_i.BLIF BGACK_030_INT_i.BLIF N_91 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF N_98 -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n -11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_99 -11 1 -.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_251_0_1 -11 1 -.names N_249_i.BLIF N_249 -0 1 -.names N_150_i.BLIF N_151_i.BLIF N_121_i_1 -11 1 -.names ds_000_enable_1_sqmuxa_1_i_m4_un1_n.BLIF \ -ds_000_enable_1_sqmuxa_1_i_m4_un0_n.BLIF N_248 -1- 1 --1 1 -.names N_199_i.BLIF N_197_i.BLIF pos_clk_cpu_est_11_0_1_3__n +.names N_22_i.BLIF RST_c.BLIF N_33_0 11 1 .names N_135_i.BLIF N_135 0 1 -.names N_194_i.BLIF N_192_i.BLIF pos_clk_cpu_est_11_0_1_1__n +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_133_i.BLIF N_133 +0 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names N_190_i.BLIF N_190 +0 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +11 1 +.names N_188_i.BLIF N_188 +0 1 +.names N_157_i.BLIF N_158_i.BLIF N_127_i_1 +11 1 +.names N_189_i.BLIF N_189 +0 1 +.names N_159_i.BLIF RST_c.BLIF N_127_i_2 11 1 .names N_136_i.BLIF N_136 0 1 -.names N_191_i.BLIF N_193_i.BLIF pos_clk_cpu_est_11_0_2_1__n +.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n 11 1 .names pos_clk_un7_clk_000_d0_1_n.BLIF inst_nEXP_SPACE_D0reg.BLIF \ pos_clk_un7_clk_000_d0_n 11 1 -.names N_163_i.BLIF N_137_i.BLIF N_131_i_1 -11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 -11 1 -.names N_162_i.BLIF N_164_i.BLIF N_131_i_2 -11 1 -.names N_136.BLIF sm_amiga_i_4__n.BLIF N_152 -11 1 -.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 -11 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_153 -11 1 -.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n -11 1 -.names CLK_000_PE_i.BLIF sm_amiga_i_3__n.BLIF N_154 -11 1 -.names a_i_31__n.BLIF inst_nEXP_SPACE_D0reg.BLIF un8_ciin_1 -11 1 -.names N_141.BLIF sm_amiga_i_5__n.BLIF N_155 -11 1 -.names AS_030_D0_i.BLIF a_i_24__n.BLIF un8_ciin_2 -11 1 -.names N_141_0.BLIF N_141 -0 1 -.names a_i_25__n.BLIF a_i_26__n.BLIF un8_ciin_3 -11 1 -.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_156 -11 1 -.names a_i_27__n.BLIF a_i_28__n.BLIF un8_ciin_4 -11 1 -.names N_138.BLIF sm_amiga_i_6__n.BLIF N_157 -11 1 -.names a_i_29__n.BLIF a_i_30__n.BLIF un8_ciin_5 -11 1 -.names N_138_0.BLIF N_138 -0 1 -.names un8_ciin_1.BLIF un8_ciin_2.BLIF un8_ciin_6 -11 1 -.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_158 -11 1 -.names un8_ciin_3.BLIF un8_ciin_4.BLIF un8_ciin_7 -11 1 -.names CLK_000_PE_i.BLIF sm_amiga_i_5__n.BLIF N_159 -11 1 -.names un8_ciin_6.BLIF un8_ciin_7.BLIF un8_ciin_8 -11 1 -.names N_142.BLIF SM_AMIGA_i_7_.BLIF N_160 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_116_1 -11 1 -.names N_142_0.BLIF N_142 -0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF N_116_2 -11 1 -.names sm_amiga_i_6__n.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_161 -11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF N_116_3 -11 1 -.names N_132_i.BLIF N_132 -0 1 -.names N_116_1.BLIF N_116_2.BLIF N_116_4 -11 1 -.names N_132.BLIF SM_AMIGA_0_.BLIF N_104 -11 1 -.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 -11 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_76 -1- 1 --1 1 -.names FPU_SENSE_i.BLIF N_116.BLIF un21_fpu_cs_1 -11 1 -.names N_71_0.BLIF N_71 -0 1 -.names N_152_i.BLIF N_153_i.BLIF N_123_i_1 -11 1 -.names N_251_0.BLIF N_251 -0 1 -.names N_154_i.BLIF RST_c.BLIF N_123_i_2 -11 1 -.names N_251.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_93 -11 1 -.names N_155_i.BLIF N_156_i.BLIF N_125_i_1 -11 1 -.names N_116.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_94 -11 1 -.names N_157_i.BLIF N_158_i.BLIF N_127_i_1 -11 1 -.names N_71.BLIF sm_amiga_i_0__n.BLIF N_88 -11 1 -.names N_159_i.BLIF RST_c.BLIF N_127_i_2 -11 1 -.names BGACK_030_INT_i.BLIF N_249.BLIF N_87 -11 1 -.names N_160_i.BLIF N_161_i.BLIF N_129_i_1 -11 1 -.names BGACK_030_INT_i.BLIF N_249_i.BLIF N_86 -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84 -11 1 -.names pos_clk_clk_000_n_sync_2_0__n.BLIF AS_030_000_SYNC_i.BLIF \ -pos_clk_un7_clk_000_d0_1_n -11 1 -.names N_252.BLIF sm_amiga_i_2__n.BLIF N_83 -11 1 -.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 -11 1 -.names N_116_4.BLIF N_116_3.BLIF N_116 -11 1 -.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 -11 1 -.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ -RESET_OUT_0_sqmuxa_7_3 -11 1 -.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 -11 1 -.names N_211.BLIF RST_DLY_5_.BLIF N_213 -11 1 .names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_135_i_1 11 1 -.names cpu_est_3_reg.BLIF N_199_1.BLIF pos_clk_un27_clk_000_ne_d0_1_n +.names inst_CLK_000_NE_D0.BLIF pos_clk_un23_clk_000_ne_d0_n.BLIF \ +pos_clk_un29_clk_000_ne_d0_n 11 1 -.names N_209.BLIF RST_DLY_4_.BLIF N_211 +.names N_191_i.BLIF N_192_i.BLIF pos_clk_cpu_est_11_0_1_1__n 11 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF pos_clk_un27_clk_000_ne_d0_2_n +.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF DSACK1_INT_0_sqmuxa 11 1 -.names pos_clk_un27_clk_000_ne_d0_1_n.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF \ -pos_clk_un27_clk_000_ne_d0_3_n +.names N_193_i.BLIF N_194_i.BLIF pos_clk_cpu_est_11_0_2_1__n 11 1 -.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un21_clk_000_ne_d0_n 11 1 -.names cpu_est_i_3__n.BLIF inst_CLK_000_PE.BLIF pos_clk_un5_clk_000_pe_1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF pos_clk_un5_clk_000_pe_2_n -11 1 -.names pos_clk_un5_clk_000_pe_1_n.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ -pos_clk_un5_clk_000_pe_3_n -11 1 -.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF pos_clk_un9_clk_000_ne_1_n -11 1 -.names inst_CLK_000_NE.BLIF VPA_D_i.BLIF pos_clk_un9_clk_000_ne_2_n -11 1 -.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF pos_clk_un9_clk_000_ne_3_n -11 1 -.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa -11 1 -.names pos_clk_un9_clk_000_ne_1_n.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF \ -pos_clk_un9_clk_000_ne_4_n -11 1 -.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_196_1 -11 1 -.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 -11 1 -.names N_188.BLIF cpu_est_0_.BLIF N_195_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n -11 1 -.names N_176_1.BLIF pos_clk_un22_bgack_030_int_n.BLIF \ -pos_clk_un24_bgack_030_int_1_n -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n -11 1 -.names N_133_i.BLIF N_135_i.BLIF N_165_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n -11 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_165_2 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n -11 1 -.names N_165_1.BLIF N_165_2.BLIF N_165_3 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n -11 1 -.names N_133.BLIF BERR_i.BLIF N_163_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n -11 1 -.names N_135.BLIF BERR_i.BLIF N_162_1 -11 1 -.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n -11 1 -.names N_176_1.BLIF RW_000_c.BLIF N_176_1_0 -11 1 -.names N_38_0.BLIF N_38 -0 1 -.names RW_000_i.BLIF pos_clk_un24_bgack_030_int_n.BLIF DS_000_DMA_2_sqmuxa_1 -11 1 -.names N_77_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_85 -11 1 -.names N_76_i.BLIF N_83_i.BLIF N_119_i_1 -11 1 -.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 -11 1 -.names N_252_0.BLIF N_252 -0 1 -.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n -11 1 -.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_97 -11 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names pos_clk_un27_clk_000_ne_d0_3_n.BLIF cpu_est_2_.BLIF \ -pos_clk_un27_clk_000_ne_d0_n -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_199_1 -11 1 -.names pos_clk_un24_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \ -as_000_dma_0_un0_n +.names N_199_i.BLIF N_197_i.BLIF pos_clk_cpu_est_11_0_1_3__n 11 1 .names pos_clk_un5_clk_000_pe_3_n.BLIF cpu_est_i_0__n.BLIF \ pos_clk_un5_clk_000_pe_n 11 1 -.names DS_000_DMA_2_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 +.names N_188.BLIF cpu_est_0_.BLIF N_195_1 +11 1 .names pos_clk_un9_clk_000_ne_4_n.BLIF pos_clk_un9_clk_000_ne_3_n.BLIF \ pos_clk_un9_clk_000_ne_n 11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_2_sqmuxa.BLIF ds_000_dma_0_un1_n +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_196_1 +11 1 +.names pos_clk_un23_clk_000_ne_d0_0_n.BLIF pos_clk_un23_clk_000_ne_d0_n +0 1 +.names N_137_i.BLIF N_162_i.BLIF N_131_i_1 +11 1 +.names pos_clk_un27_clk_000_ne_d0_3_n.BLIF cpu_est_2_.BLIF \ +pos_clk_un27_clk_000_ne_d0_n +11 1 +.names N_163_i.BLIF N_164_i.BLIF N_131_i_2 +11 1 +.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n +0 1 +.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3 +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_5__n.BLIF N_144 +11 1 +.names N_147_i.BLIF N_148_i.BLIF N_119_i_1 +11 1 +.names N_143.BLIF sm_amiga_i_0__n.BLIF N_146 +11 1 +.names N_149_i.BLIF RST_c.BLIF N_119_i_2 +11 1 +.names N_143_0.BLIF N_143 +0 1 +.names N_150_i.BLIF N_151_i.BLIF N_121_i_1 +11 1 +.names N_139.BLIF sm_amiga_i_2__n.BLIF N_147 +11 1 +.names N_152_i.BLIF N_153_i.BLIF N_123_i_1 +11 1 +.names N_139_0.BLIF N_139 +0 1 +.names N_154_i.BLIF RST_c.BLIF N_123_i_2 +11 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF N_148 +11 1 +.names N_155_i.BLIF N_156_i.BLIF N_125_i_1 +11 1 +.names CLK_000_PE_i.BLIF sm_amiga_i_1__n.BLIF N_149 +11 1 +.names N_160_i.BLIF N_161_i.BLIF N_129_i_1 11 1 .names N_140.BLIF sm_amiga_i_3__n.BLIF N_150 11 1 -.names pos_clk_ds_000_dma_4_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +.names N_135.BLIF BERR_i.BLIF N_162_1 +11 1 +.names N_140_0.BLIF N_140 +0 1 +.names N_133.BLIF BERR_i.BLIF N_163_1 11 1 .names sm_amiga_i_2__n.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF N_151 11 1 -.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n +.names N_133_i.BLIF N_135_i.BLIF N_165_1 +11 1 +.names N_136.BLIF sm_amiga_i_4__n.BLIF N_152 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_3__n.BLIF N_165_2 +11 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_153 +11 1 +.names N_165_1.BLIF N_165_2.BLIF N_165_3 +11 1 +.names CLK_000_PE_i.BLIF sm_amiga_i_3__n.BLIF N_154 +11 1 +.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 +11 1 +.names N_141.BLIF sm_amiga_i_5__n.BLIF N_155 +11 1 +.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 +11 1 +.names N_141_0.BLIF N_141 0 1 -.names N_199_1.BLIF cpu_est_i_2__n.BLIF N_199 +.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 11 1 -.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n +.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_156 11 1 -.names N_196_1.BLIF cpu_est_i_2__n.BLIF N_196 +.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names N_142.BLIF SM_AMIGA_i_7_.BLIF N_160 11 1 -.names N_195_1.BLIF cpu_est_i_3__n.BLIF N_195 +.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n +.names N_142_0.BLIF N_142 0 1 -.names N_188_i.BLIF N_188 +.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +11 1 +.names sm_amiga_i_6__n.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_161 +11 1 +.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +11 1 +.names BERR_i.BLIF N_136_i.BLIF N_164 +11 1 +.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +11 1 +.names N_132.BLIF SM_AMIGA_0_.BLIF N_166 +11 1 +.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +11 1 +.names N_132_i.BLIF N_132 0 1 -.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n -11 1 -.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n -0 1 -.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_190.BLIF cpu_est_3_reg.BLIF N_197 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names N_190_i.BLIF cpu_est_i_2__n.BLIF N_198 -11 1 -.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n -11 1 -.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n -0 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_188_i.BLIF cpu_est_3_reg.BLIF N_194 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_192 -11 1 -.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n +.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 11 1 .names N_189.BLIF cpu_est_i_0__n.BLIF N_191 11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +11 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_192 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF pos_clk_un9_clk_000_ne_1_n +11 1 +.names N_189_i.BLIF cpu_est_0_.BLIF N_193 +11 1 +.names inst_CLK_000_NE.BLIF VPA_D_i.BLIF pos_clk_un9_clk_000_ne_2_n +11 1 +.names N_188_i.BLIF cpu_est_3_reg.BLIF N_194 +11 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF pos_clk_un9_clk_000_ne_3_n +11 1 +.names N_190.BLIF cpu_est_3_reg.BLIF N_197 +11 1 +.names pos_clk_un9_clk_000_ne_1_n.BLIF pos_clk_un9_clk_000_ne_2_n.BLIF \ +pos_clk_un9_clk_000_ne_4_n +11 1 +.names N_190_i.BLIF cpu_est_i_2__n.BLIF N_198 +11 1 +.names cpu_est_i_3__n.BLIF inst_CLK_000_PE.BLIF pos_clk_un5_clk_000_pe_1_n +11 1 +.names N_195_1.BLIF cpu_est_i_3__n.BLIF N_195 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF pos_clk_un5_clk_000_pe_2_n +11 1 +.names N_196_1.BLIF cpu_est_i_2__n.BLIF N_196 +11 1 +.names pos_clk_un5_clk_000_pe_1_n.BLIF pos_clk_un5_clk_000_pe_2_n.BLIF \ +pos_clk_un5_clk_000_pe_3_n +11 1 +.names N_162_1.BLIF CLK_000_PE_i.BLIF N_162 +11 1 +.names cpu_est_3_reg.BLIF N_199_1.BLIF pos_clk_un27_clk_000_ne_d0_1_n +11 1 +.names N_199_1.BLIF cpu_est_i_2__n.BLIF N_199 +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF pos_clk_un27_clk_000_ne_d0_2_n +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_199_1 +11 1 +.names pos_clk_un27_clk_000_ne_d0_1_n.BLIF pos_clk_un27_clk_000_ne_d0_2_n.BLIF \ +pos_clk_un27_clk_000_ne_d0_3_n +11 1 +.names N_163_1.BLIF CLK_000_NE_i.BLIF N_163 +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1 +11 1 +.names N_165_3.BLIF pos_clk_un7_clk_000_d0_i_n.BLIF N_165 +11 1 +.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2 +11 1 +.names N_73_0.BLIF N_73 +0 1 +.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \ +RESET_OUT_0_sqmuxa_7_3 +11 1 +.names CLK_030_H_i.BLIF N_73.BLIF N_94 +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1 +11 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_85 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_87_1 +11 1 +.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_84 +11 1 +.names RW_000_c.BLIF nEXP_SPACE_D0_i.BLIF N_87_2 +11 1 +.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_83 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un24_bgack_030_int_i_0_0_1_n +11 1 +.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \ +pos_clk_un9_clk_000_n_sync_n +11 1 +.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_104_i.BLIF \ +pos_clk_un24_bgack_030_int_i_0_0_2_n +11 1 +.names sm_amiga_i_i_7__n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_72_0_1 +11 1 +.names pos_clk_clk_000_n_sync_2_0__n.BLIF AS_030_000_SYNC_i.BLIF \ +pos_clk_un7_clk_000_d0_1_n +11 1 +.names N_211.BLIF RST_DLY_5_.BLIF N_213 +11 1 +.names FPU_SENSE_i.BLIF N_116.BLIF un21_fpu_cs_1 +11 1 +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +11 1 +.names N_209.BLIF RST_DLY_4_.BLIF N_211 +11 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_116_1 +11 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF N_116_2 +11 1 +.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209 +11 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF N_116_3 +11 1 +.names N_116_1.BLIF N_116_2.BLIF N_116_4 +11 1 +.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205 +11 1 +.names N_83_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1 +11 1 +.names N_84_i.BLIF RW_000_i.BLIF N_245_0_1 +11 1 +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1 +11 1 +.names N_94_i.BLIF RST_c.BLIF N_247_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_248_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7 +11 1 +.names AS_000_i.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_249_i_1 +11 1 +.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5 +11 1 +.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n +11 1 +.names N_92_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n +11 1 +.names N_91_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_86 +11 1 +.names N_251.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_93 +11 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names N_87_1.BLIF N_87_2.BLIF N_87 +11 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 @@ -1817,10 +1790,10 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_78.BLIF AMIGA_BUS_ENABLE_HIGH +.names N_80.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 -.names vcc_n_n.BLIF CIIN +.names un5_ciin.BLIF CIIN 1 1 0 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ @@ -1829,6 +1802,15 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 @@ -1877,13 +1859,22 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +0 0 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_0_.C @@ -1922,6 +1913,24 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +0 0 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +0 0 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +0 0 .names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D 1 1 0 0 @@ -1988,24 +1997,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C 1 1 0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 -0 0 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -2033,27 +2024,27 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C 1 1 0 0 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C 1 1 0 0 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 0 0 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 @@ -2087,18 +2078,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF inst_DTACK_D0.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -2114,12 +2093,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -2195,27 +2168,6 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names un4_size.BLIF SIZE_0_ 1 1 0 0 -.names RW.PIN.BLIF RW_c -1 1 -0 0 -.names FC_0_.BLIF fc_c_0__n -1 1 -0 0 -.names FC_1_.BLIF fc_c_1__n -1 1 -0 0 -.names A_23_.BLIF a_23__n -1 1 -0 0 -.names A_22_.BLIF a_22__n -1 1 -0 0 -.names A_21_.BLIF a_21__n -1 1 -0 0 -.names A_20_.BLIF a_20__n -1 1 -0 0 .names A_15_.BLIF a_15__n 1 1 0 0 @@ -2294,6 +2246,18 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names A_19_.BLIF a_c_19__n 1 1 0 0 +.names A_20_.BLIF a_c_20__n +1 1 +0 0 +.names A_21_.BLIF a_c_21__n +1 1 +0 0 +.names A_22_.BLIF a_c_22__n +1 1 +0 0 +.names A_23_.BLIF a_c_23__n +1 1 +0 0 .names A_24_.BLIF a_c_24__n 1 1 0 0 @@ -2363,22 +2327,31 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names RST.BLIF RST_c 1 1 0 0 +.names RW.PIN.BLIF RW_c +1 1 +0 0 +.names FC_0_.BLIF fc_c_0__n +1 1 +0 0 +.names FC_1_.BLIF fc_c_1__n +1 1 +0 0 .names un3_as_030_i.BLIF AS_030.OE 1 1 0 0 -.names N_98.BLIF AS_000.OE +.names un1_as_000_i.BLIF AS_000.OE 1 1 0 0 -.names N_98.BLIF RW_000.OE +.names un1_as_000_i.BLIF RW_000.OE 1 1 0 0 .names un3_as_030_i.BLIF DS_030.OE 1 1 0 0 -.names N_98.BLIF UDS_000.OE +.names un1_as_000_i.BLIF UDS_000.OE 1 1 0 0 -.names N_98.BLIF LDS_000.OE +.names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 .names un1_as_030_i.BLIF SIZE_0_.OE @@ -2393,7 +2366,7 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names un22_berr.BLIF BERR.OE 1 1 0 0 -.names N_99.BLIF RW.OE +.names N_100.BLIF RW.OE 1 1 0 0 .names gnd_n_n.BLIF CLK_DIV_OUT.OE @@ -2402,15 +2375,10 @@ sm_amiga_srsts_i_0_m2_1__un0_n .names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE 1 1 0 0 -.names un8_ciin.BLIF CIIN.OE +.names un8_ciin_i.BLIF CIIN.OE 1 1 0 0 -.names N_220.BLIF CYCLE_DMA_1_.BLIF G_161 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF G_159 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2 01 1 10 1 11 0 @@ -2435,6 +2403,16 @@ sm_amiga_srsts_i_0_m2_1__un0_n 10 1 11 0 00 0 +.names CYCLE_DMA_1_.BLIF N_220.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +01 1 +10 1 +11 0 +00 0 +.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 +01 1 +10 1 +11 0 +00 0 .names RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa_7.BLIF G_149 01 1 10 1 @@ -2470,7 +2448,7 @@ sm_amiga_srsts_i_0_m2_1__un0_n 10 1 11 0 00 0 -.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_ +.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF G_135 01 1 10 1 11 0 diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd new file mode 100644 index 0000000..e7c37a0 --- /dev/null +++ b/Logic/BUS68030.cmd @@ -0,0 +1,8 @@ +STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 3ba2a70..21df811 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2015 7 9 18 48 54) + (timeStamp 2015 9 24 16 20 54) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -140,6 +140,12 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename IPL_030DFF_2 "IPL_030DFF[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_0 "IPL_D0[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -170,11 +176,11 @@ ) (instance (rename IPL_030DFF_1 "IPL_030DFF[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename IPL_030DFF_2 "IPL_030DFF[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename IPL_D0_0 "IPL_D0[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -200,6 +206,12 @@ ) (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -222,12 +234,6 @@ ) (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -238,14 +244,20 @@ ) (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) @@ -268,14 +280,6 @@ ) (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) @@ -286,10 +290,6 @@ ) (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach))) @@ -381,125 +381,131 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_0_0 "SM_AMIGA_nss_i_i_a6_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_1_0_0 "SM_AMIGA_nss_i_i_a6_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_0 "SM_AMIGA_nss_i_i_a6[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3_0_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i "pos_clk.CYCLE_DMA_5_1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_168_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_168 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_ne_2 "pos_clk.un9_clk_000_ne_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_ne_3 "pos_clk.un9_clk_000_ne_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_ne_4 "pos_clk.un9_clk_000_ne_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_ne "pos_clk.un9_clk_000_ne") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_a4_0_1_2 "pos_clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_a4_0_2 "pos_clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_a4_1_2 "pos_clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_a4_2 "pos_clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_1 "pos_clk.un24_bgack_030_int_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int "pos_clk.un24_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_2_1_0 "SM_AMIGA_nss_i_i_a6_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_2_2_0 "SM_AMIGA_nss_i_i_a6_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_2_3_0 "SM_AMIGA_nss_i_i_a6_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_2_0 "SM_AMIGA_nss_i_i_a6_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_0_1_0 "SM_AMIGA_nss_i_i_a6_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_7_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_5_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_o3_0_1_0 "SM_AMIGA_nss_i_i_o3_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_o3_0_0 "SM_AMIGA_nss_i_i_o3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un27_clk_000_ne_d0_1 "pos_clk.un27_clk_000_ne_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un27_clk_000_ne_d0_2_0 "pos_clk.un27_clk_000_ne_d0_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un27_clk_000_ne_d0_3 "pos_clk.un27_clk_000_ne_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un27_clk_000_ne_d0 "pos_clk.un27_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_clk_000_pe_1 "pos_clk.un5_clk_000_pe_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_clk_000_pe_2 "pos_clk.un5_clk_000_pe_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_clk_000_pe_3 "pos_clk.un5_clk_000_pe_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_clk_000_pe "pos_clk.un5_clk_000_pe") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_ne_1 "pos_clk.un9_clk_000_ne_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_2_3 "SM_AMIGA_srsts_i_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_3 "SM_AMIGA_srsts_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_4 "SM_AMIGA_srsts_i_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_4 "SM_AMIGA_srsts_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_5 "SM_AMIGA_srsts_i_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_2_5 "SM_AMIGA_srsts_i_2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_5 "SM_AMIGA_srsts_i[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_6 "SM_AMIGA_srsts_i_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_6 "SM_AMIGA_srsts_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_d0_1 "pos_clk.un7_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_d0 "pos_clk.un7_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_7_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_7_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_a2_1_1 "pos_clk.un37_as_030_d0_i_a2_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_a2_1_2 "pos_clk.un37_as_030_d0_i_a2_1_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_a2_1_3 "pos_clk.un37_as_030_d0_i_a2_1_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_a2_1_4 "pos_clk.un37_as_030_d0_i_a2_1_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_a2_1 "pos_clk.un37_as_030_d0_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a2_1 "pos_clk.un6_bg_030_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a2 "pos_clk.un6_bg_030_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_1 "pos_clk.CYCLE_DMA_5_1_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_5_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2_1 "pos_clk.un24_bgack_030_int_i_0_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2_2 "pos_clk.un24_bgack_030_int_i_0_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2 "pos_clk.un24_bgack_030_int_i_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_o2_1 "pos_clk.un37_as_030_d0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_o2 "pos_clk.un37_as_030_d0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_d0_1 "pos_clk.un7_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_d0 "pos_clk.un7_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un21_fpu_cs_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un21_fpu_cs_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_ne_3 "pos_clk.un9_clk_000_ne_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_ne_4 "pos_clk.un9_clk_000_ne_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_ne "pos_clk.un9_clk_000_ne") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un5_clk_000_pe_1 "pos_clk.un5_clk_000_pe_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un5_clk_000_pe_2 "pos_clk.un5_clk_000_pe_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un5_clk_000_pe_3 "pos_clk.un5_clk_000_pe_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un5_clk_000_pe "pos_clk.un5_clk_000_pe") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un27_clk_000_ne_d0_1 "pos_clk.un27_clk_000_ne_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un27_clk_000_ne_d0_2_0 "pos_clk.un27_clk_000_ne_d0_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un27_clk_000_ne_d0_3 "pos_clk.un27_clk_000_ne_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un27_clk_000_ne_d0 "pos_clk.un27_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_2_0 "SM_AMIGA_nss_i_i_a6_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_ne_1 "pos_clk.un9_clk_000_ne_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_ne_2 "pos_clk.un9_clk_000_ne_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_2 "SM_AMIGA_srsts_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_1_3 "SM_AMIGA_srsts_i_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_2_3 "SM_AMIGA_srsts_i_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_3 "SM_AMIGA_srsts_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_1_4 "SM_AMIGA_srsts_i_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_4 "SM_AMIGA_srsts_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_1_6 "SM_AMIGA_srsts_i_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_6 "SM_AMIGA_srsts_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_1_0_0 "SM_AMIGA_nss_i_i_a6_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_0 "SM_AMIGA_nss_i_i_a6[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_0_1_0 "SM_AMIGA_nss_i_i_a6_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_0_0 "SM_AMIGA_nss_i_i_a6_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_2_1_0 "SM_AMIGA_nss_i_i_a6_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_2_2_0 "SM_AMIGA_nss_i_i_a6_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_2_3_0 "SM_AMIGA_nss_i_i_a6_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_1 "pos_clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_cpu_est_11_0_1_3 "pos_clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_cpu_est_11_0_3 "pos_clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_1_1 "pos_clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_2_1 "pos_clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_1 "pos_clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_a4_1_2 "pos_clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_a4_2 "pos_clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_a4_0_1_2 "pos_clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_a4_0_2 "pos_clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_1_0 "SM_AMIGA_nss_i_i_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_2_0 "SM_AMIGA_nss_i_i_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_3_0 "SM_AMIGA_nss_i_i_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0 "SM_AMIGA_nss_i_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un11_ds_030_d0_1 "pos_clk.un11_ds_030_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un11_ds_030_d0 "pos_clk.un11_ds_030_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_1_1 "SM_AMIGA_srsts_i_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_2_1 "SM_AMIGA_srsts_i_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_1 "SM_AMIGA_srsts_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_1_2 "SM_AMIGA_srsts_i_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un8_bg_030_i "pos_clk.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_o4_1 "pos_clk.un37_as_030_d0_i_o4_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_o4 "pos_clk.un37_as_030_d0_i_o4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_2 "SM_AMIGA_srsts_i_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_2 "SM_AMIGA_srsts_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_030_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_1_5 "SM_AMIGA_srsts_i_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_2_5 "SM_AMIGA_srsts_i_2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_5 "SM_AMIGA_srsts_i[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un11_ds_030_d0_1 "pos_clk.un11_ds_030_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un11_ds_030_d0 "pos_clk.un11_ds_030_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_o3_0_1_0 "SM_AMIGA_nss_i_i_o3_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_o3_0_0 "SM_AMIGA_nss_i_i_o3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_1_1 "pos_clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_2_1 "pos_clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_6_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_9_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_10_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_13_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_14_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -514,240 +520,254 @@ (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance nEXP_SPACE_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance nEXP_SPACE_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_158_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_152_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_6 "SM_AMIGA_srsts_i_o3_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_4 "SM_AMIGA_srsts_i_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_5 "SM_AMIGA_srsts_i_o3_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_0_i_0 "SM_AMIGA_srsts_i_o3_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_7_i_0 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un21_clk_000_ne_d0_i "pos_clk.un21_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un27_clk_000_ne_d0_i "pos_clk.un27_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un23_clk_000_ne_d0_i "pos_clk.un23_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un5_clk_000_pe_i "pos_clk.un5_clk_000_pe_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_ne_i "pos_clk.un9_clk_000_ne_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe_i "pos_clk.un7_clk_000_pe_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_i "pos_clk.un37_as_030_d0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un3_as_030_d0_0_o2_i "pos_clk.un3_as_030_d0_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o4_i_0 "pos_clk.SIZE_DMA_6_0_0_o4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_o4_i "pos_clk.un37_as_030_d0_i_o4_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o4_i_0 "SM_AMIGA_srsts_i_0_o4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_160_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_159_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_157_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_m_i_6 "un1_RST_DLY_i_m_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_m_i_7 "un1_RST_DLY_i_m_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_m_i_8 "un1_RST_DLY_i_m_i[8]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_76_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_84_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_87_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_i_1 "pos_clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_197_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_193_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_o4_i_3 "pos_clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_o4_i_1 "pos_clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_o4_i_2 "pos_clk.cpu_est_11_i_o4_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_195_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_196_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_0 "SM_AMIGA_srsts_i_o3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_6 "SM_AMIGA_srsts_i_o3_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_4 "SM_AMIGA_srsts_i_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_2 "SM_AMIGA_srsts_i_o3_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_1 "SM_AMIGA_srsts_i_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_166_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_3 "SM_AMIGA_srsts_i_o3_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_o3_i_0 "SM_AMIGA_nss_i_i_o3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0_i_0 "SM_AMIGA_srsts_i_o3_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_199_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_cpu_est_11_0_i_3 "pos_clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_197_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_194_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_i_1 "pos_clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_192_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_o3_0_i_0 "SM_AMIGA_nss_i_i_o3_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o4_i_1 "SM_AMIGA_srsts_i_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_162_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_191_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_85_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_i "pos_clk.DS_000_DMA_4_f0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_160_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_152_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_149_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_i_2 "un1_RST_DLY_i_m_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_i_3 "un1_RST_DLY_i_m_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_i_4 "un1_RST_DLY_i_m_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_i_5 "un1_RST_DLY_i_m_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_i "pos_clk.un7_clk_000_pe_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un27_clk_000_ne_d0_i "pos_clk.un27_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un21_clk_000_ne_d0_i "pos_clk.un21_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un23_clk_000_ne_d0_i "pos_clk.un23_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_3 "SM_AMIGA_srsts_i_o3_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_2 "SM_AMIGA_srsts_i_o3_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_195_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_196_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_o4_i_2 "pos_clk.cpu_est_11_i_o4_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_o4_i_1 "pos_clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_o4_i_3 "pos_clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_193_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_191_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_192_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_194_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f1_i "pos_clk.DS_000_DMA_4_f1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_162_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un22_bgack_030_int_i "pos_clk.un22_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_n_sync_i "pos_clk.un9_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_6 "un1_RST_DLY_i_m_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_7 "un1_RST_DLY_i_m_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_8 "un1_RST_DLY_i_m_i[8]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_n_sync_i "pos_clk.un9_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un14_clk_000_n_sync_i "pos_clk.un14_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_EXP_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_84_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_i "pos_clk.un37_as_030_d0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_i_5 "SM_AMIGA_srsts_i_o3_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_i_1 "un1_RST_DLY_i_m_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_157_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_158_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_159_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_o2_i "pos_clk.CYCLE_DMA_5_1_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_87_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un4_bgack_000_i_o2_i "pos_clk.un4_bgack_000_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_o2_i "pos_clk.un37_as_030_d0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_o2_i "pos_clk.un24_bgack_030_int_i_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_i "pos_clk.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_13_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_ne_i "pos_clk.un9_clk_000_ne_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un5_clk_000_pe_i "pos_clk.un5_clk_000_pe_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_6_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un29_bgack_030_int_i "pos_clk.un29_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un26_bgack_030_int_i "pos_clk.un26_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un27_bgack_030_int_i "pos_clk.un27_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_7_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_o3_i_0 "SM_AMIGA_nss_i_i_o3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_176_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_175_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un26_bgack_030_int "pos_clk.un26_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un29_bgack_030_int "pos_clk.un29_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_160 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i "pos_clk.un24_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance I_234 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_o3_0 "SM_AMIGA_nss_i_i_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_235 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_a6_1_0 "SM_AMIGA_nss_i_i_a6_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0 "pos_clk.CYCLE_DMA_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_EXP_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rst_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un27_bgack_030_int "pos_clk.un27_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_d0_i "pos_clk.un7_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_PE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un40_bgack_030_int_1_i "pos_clk.un40_bgack_030_int_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0 "pos_clk.DS_000_DMA_4_f0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f1 "pos_clk.DS_000_DMA_4_f1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_236 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un11_clk_000_n_sync "pos_clk.un11_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un11_clk_000_n_sync_i "pos_clk.un11_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_n_sync "pos_clk.un9_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un14_clk_000_n_sync "pos_clk.un14_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_237 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_238 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un22_bgack_030_int "pos_clk.un22_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__r "SM_AMIGA_srsts_i_0_m2_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__m "SM_AMIGA_srsts_i_0_m2_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__n "SM_AMIGA_srsts_i_0_m2_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__p "SM_AMIGA_srsts_i_0_m2_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance G_161 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_159 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename pos_clk_un40_bgack_030_int_1 "pos_clk.un40_bgack_030_int_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un29_clk_000_ne_d0_i "pos_clk.un29_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a6_0_2 "SM_AMIGA_srsts_i_a6_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a6_2 "SM_AMIGA_srsts_i_a6[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un29_clk_000_ne_d0 "pos_clk.un29_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_clk_000_ne_d0 "pos_clk.un23_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un21_clk_000_ne_d0 "pos_clk.un21_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_92_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_o4_1 "pos_clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_o4_2 "pos_clk.cpu_est_11_i_o4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_i_2 "pos_clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_0_3 "pos_clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_3 "pos_clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_2_1 "pos_clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_1_1 "pos_clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_0_1 "pos_clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_1 "pos_clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_2 "SM_AMIGA_srsts_i_o3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_3 "SM_AMIGA_srsts_i_o3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance I_224 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_225 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_PE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un4_bgack_000_i_o2 "pos_clk.un4_bgack_000_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_i_a2 "pos_clk.un3_as_030_d0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_N_SYNC_2_0 "pos_clk.CLK_000_N_SYNC_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_P_SYNC_2_0 "pos_clk.CLK_000_P_SYNC_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2 "pos_clk.un37_as_030_d0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i_a2_0 "pos_clk.un37_as_030_d0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_a2 "pos_clk.un24_bgack_030_int_i_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_i "pos_clk.un37_as_030_d0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un24_bgack_030_int_i_0_x2 "pos_clk.un24_bgack_030_int_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_1_5 "SM_AMIGA_srsts_i_a6_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_226 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_0_5 "SM_AMIGA_srsts_i_a6_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_5 "SM_AMIGA_srsts_i_a6[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_146 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_144 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_142 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_138 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_136 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_1 "SM_AMIGA_srsts_i_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_bgack_000_i_a2 "pos_clk.un4_bgack_000_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o4_1 "SM_AMIGA_srsts_i_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un27_clk_000_ne_d0_2 "pos_clk.un27_clk_000_ne_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_a4_1_3 "pos_clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_cpu_est_11_0_o4_3 "pos_clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_227 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un2_rw_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_o2 "pos_clk.CYCLE_DMA_5_1_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_135 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_0 "pos_clk.RST_DLY_5_iv[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_1 "un1_RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_1 "un1_RST_DLY_i_m[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_5 "SM_AMIGA_srsts_i_o3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_5 "pos_clk.RST_DLY_5_iv[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_6 "un1_RST_DLY_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_6 "un1_RST_DLY_i_m[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_4 "pos_clk.RST_DLY_5_iv[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_5 "un1_RST_DLY_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_RST_DLY_i_m_5 "un1_RST_DLY_i_m[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RST_DLY_5_iv_3 "pos_clk.RST_DLY_5_iv[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_4 "un1_RST_DLY_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_4 "un1_RST_DLY_i_m[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_RST_DLY_5_iv_2 "pos_clk.RST_DLY_5_iv[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -756,13 +776,13 @@ (instance (rename pos_clk_RST_DLY_5_iv_1 "pos_clk.RST_DLY_5_iv[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_2 "un1_RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_2 "un1_RST_DLY_i_m[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_77_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RST_DLY_5_iv_0_a2_0 "pos_clk.RST_DLY_5_iv_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RST_DLY_5_iv_0_0 "pos_clk.RST_DLY_5_iv_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RST_DLY_5_iv_0_x2_0 "pos_clk.RST_DLY_5_iv_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance un3_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_149 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_147 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_145 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_143 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_141 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_139 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance G_137 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance RESET_OUT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_RST_DLY_5_iv_7 "pos_clk.RST_DLY_5_iv[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -771,118 +791,131 @@ (instance (rename pos_clk_RST_DLY_5_iv_6 "pos_clk.RST_DLY_5_iv[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_7 "un1_RST_DLY_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un1_RST_DLY_i_m_7 "un1_RST_DLY_i_m[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RST_DLY_5_iv_5 "pos_clk.RST_DLY_5_iv[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_6 "un1_RST_DLY_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_m_6 "un1_RST_DLY_i_m[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RST_DLY_5_iv_4 "pos_clk.RST_DLY_5_iv[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_5 "un1_RST_DLY_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_RST_DLY_i_m_5 "un1_RST_DLY_i_m[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RST_DLY_5_iv_3 "pos_clk.RST_DLY_5_iv[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_239 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0 "pos_clk.DS_000_DMA_4_f0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_as_030_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_a2 "pos_clk.DS_000_DMA_4_f0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_SM_AMIGA_5_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un3_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_149 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_147 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_145 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_143 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_141 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_139 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a2_0 "pos_clk.CLK_000_P_SYNC_2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un2_rw_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_000_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_a2_0 "pos_clk.un37_as_030_d0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_a2 "pos_clk.un37_as_030_d0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o6_0_a4_0 "SM_AMIGA_srsts_i_o6_0_a4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o4_0 "SM_AMIGA_srsts_i_0_o4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o4_0 "pos_clk.SIZE_DMA_6_0_0_o4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_240 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_r "DS_000_ENABLE_1_sqmuxa_1_i_m4.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_m "DS_000_ENABLE_1_sqmuxa_1_i_m4.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_n "DS_000_ENABLE_1_sqmuxa_1_i_m4.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_p "DS_000_ENABLE_1_sqmuxa_1_i_m4.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_un3_as_030_d0_0_o2 "pos_clk.un3_as_030_d0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i "pos_clk.un37_as_030_d0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_248_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a6_5 "SM_AMIGA_srsts_i_a6[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a6_0_5 "SM_AMIGA_srsts_i_a6_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a6_1_5 "SM_AMIGA_srsts_i_a6_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un14_clk_000_n_sync "pos_clk.un14_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un11_clk_000_n_sync_i "pos_clk.un11_clk_000_n_sync_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_n_sync "pos_clk.un9_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un11_clk_000_n_sync "pos_clk.un11_clk_000_n_sync") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_d0_i "pos_clk.un7_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un27_clk_000_ne_d0_2 "pos_clk.un27_clk_000_ne_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_x2 "pos_clk.CYCLE_DMA_5_0_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_6 "SM_AMIGA_srsts_i_o3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_0 "SM_AMIGA_srsts_i_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_1 "pos_clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_0_1 "pos_clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_1_1 "pos_clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_2_1 "pos_clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_3 "pos_clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_0_3 "pos_clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_2 "pos_clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_o4_2 "pos_clk.cpu_est_11_i_o4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_o4_1 "pos_clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_o4_3 "pos_clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_a4_1_3 "pos_clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_0_4 "SM_AMIGA_srsts_i_a6_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_a6_6 "SM_AMIGA_srsts_i_a6[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_a6_0_6 "SM_AMIGA_srsts_i_a6_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_a6_1_0 "SM_AMIGA_nss_i_i_a6_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a3_0 "SM_AMIGA_srsts_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0 "SM_AMIGA_srsts_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_o3_0_0 "SM_AMIGA_srsts_i_o3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_5 "SM_AMIGA_srsts_i_o3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_o3_0 "SM_AMIGA_nss_i_i_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_3 "SM_AMIGA_srsts_i_o3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o6_0 "SM_AMIGA_srsts_i_o6[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_1 "SM_AMIGA_srsts_i_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_o3_2 "SM_AMIGA_srsts_i_o3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_o3_4 "SM_AMIGA_srsts_i_o3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_6 "SM_AMIGA_srsts_i_o3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CLK_000_N_SYNC_2_0_a4_0 "pos_clk.CLK_000_N_SYNC_2_0_a4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o6_0_o2_0 "SM_AMIGA_srsts_i_o6_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_167 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_3_0_a6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_0 "SM_AMIGA_srsts_i_a6[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_1 "SM_AMIGA_srsts_i_a6[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_0_1 "SM_AMIGA_srsts_i_a6_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_1_1 "SM_AMIGA_srsts_i_a6_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_2 "SM_AMIGA_srsts_i_a6[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un29_clk_000_ne_d0_i "pos_clk.un29_clk_000_ne_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_a6_0_2 "SM_AMIGA_srsts_i_a6_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_a6_3 "SM_AMIGA_srsts_i_a6[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_a6_0_3 "SM_AMIGA_srsts_i_a6_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_a6_1_3 "SM_AMIGA_srsts_i_a6_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_a6_4 "SM_AMIGA_srsts_i_a6[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a6_0_4 "SM_AMIGA_srsts_i_a6_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_165 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_166 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_167 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un21_clk_000_ne_d0 "pos_clk.un21_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_clk_000_ne_d0 "pos_clk.un23_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un29_clk_000_ne_d0 "pos_clk.un29_clk_000_ne_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_228 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_230 (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un6_lds_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un6_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_165 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_166 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_242 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_160 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_030_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -890,14 +923,6 @@ (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -910,22 +935,6 @@ (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_030_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_80_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -934,97 +943,88 @@ (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un3_ds_030_d0 "pos_clk.un3_ds_030_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un6_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un4_as_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un6_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un6_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un6_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) + (portRef I0 (instanceRef un1_as_000_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__r)) - (portRef I0 (instanceRef un1_as_000_i_a2)) - (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) + (portRef I0 (instanceRef BGACK_030_INT_0_n)) (portRef I0 (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) (portRef I0 (instanceRef BGACK_030)) )) (net VCC (joined (portRef I0 (instanceRef AVEC)) - (portRef I0 (instanceRef CIIN)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_2_1)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_3)) (portRef I0 (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef cpu_est_i_3)) (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_1)) (portRef I0 (instanceRef E)) )) (net VMA_INT (joined (portRef Q (instanceRef VMA_INT)) - (portRef I0 (instanceRef VMA_INT_i)) (portRef I0 (instanceRef VMA_INT_0_n)) + (portRef I0 (instanceRef VMA_INT_i)) (portRef I0 (instanceRef VMA)) )) (net RESET_OUT (joined (portRef Q (instanceRef RESET_OUT)) - (portRef I1 (instanceRef un1_as_000_i_a2)) - (portRef I1 (instanceRef un2_rw_i_a2)) (portRef I0 (instanceRef un3_as_030)) + (portRef I1 (instanceRef un1_as_000_0)) (portRef I0 (instanceRef RESET_OUT_i)) + (portRef I1 (instanceRef un2_rw_i_a2)) (portRef I0 (instanceRef RESET)) )) (net GND (joined @@ -1038,7 +1038,7 @@ (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) )) (net un6_as_030 (joined - (portRef O (instanceRef un6_as_030)) + (portRef O (instanceRef un6_as_030_0_a2)) (portRef I0 (instanceRef un6_as_030_i)) )) (net un3_size (joined @@ -1049,18 +1049,23 @@ (portRef O (instanceRef un4_size)) (portRef I0 (instanceRef SIZE_0)) )) + (net un5_ciin (joined + (portRef O (instanceRef un5_ciin)) + (portRef I0 (instanceRef un5_ciin_i)) + (portRef I0 (instanceRef CIIN)) + )) (net un8_ciin (joined (portRef O (instanceRef un8_ciin)) - (portRef OE (instanceRef CIIN)) - )) - (net un14_amiga_bus_data_dir (joined - (portRef O (instanceRef un14_amiga_bus_data_dir)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir_i)) + (portRef I0 (instanceRef un8_ciin_i)) )) (net un4_as_000 (joined (portRef O (instanceRef un4_as_000)) (portRef I0 (instanceRef un4_as_000_i)) )) + (net un1_SM_AMIGA_7 (joined + (portRef O (instanceRef un1_SM_AMIGA_7_i_0)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1)) + )) (net un21_fpu_cs (joined (portRef O (instanceRef un21_fpu_cs_0_a2)) (portRef I0 (instanceRef un21_fpu_cs_i)) @@ -1084,53 +1089,50 @@ (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_1_1)) (portRef I1 (instanceRef cpu_est_0_0)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_1_1)) (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_1_2)) (portRef I0 (instanceRef pos_clk_un9_clk_000_ne_3)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef cpu_est_0_1__n)) (portRef I1 (instanceRef pos_clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef pos_clk_cpu_est_11_i_o4_2)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_2)) (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_2)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef AS_000_INT_0_m)) (portRef I0 (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef AS_000_INT_0_n)) )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_5)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_5)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) (portRef I0 (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_m)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_r)) )) (net AMIGA_BUS_ENABLE_DMA_LOW (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) (portRef I0 (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_1)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_1)) )) (net nEXP_SPACE_D0 (joined (portRef Q (instanceRef nEXP_SPACE_D0)) (portRef I0 (instanceRef nEXP_SPACE_D0_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o4)) - (portRef I1 (instanceRef un8_ciin_1)) (portRef I1 (instanceRef pos_clk_un7_clk_000_d0)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_1)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_1)) (portRef OE (instanceRef DSACK1)) )) (net DS_030_D0 (joined @@ -1139,8 +1141,8 @@ )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) @@ -1148,43 +1150,42 @@ )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) + (portRef I0 (instanceRef AS_000_DMA_0_n)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) (portRef I0 (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef AS_000_DMA_0_m)) )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) + (portRef I0 (instanceRef DS_000_DMA_0_n)) (portRef I0 (instanceRef DS_000_DMA_i)) - (portRef I0 (instanceRef DS_000_DMA_0_m)) )) (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) - (portRef I1 (instanceRef G_159)) (portRef I1 (instanceRef G_160)) - (portRef I0 (instanceRef pos_clk_un29_bgack_030_int)) - (portRef I0 (instanceRef CYCLE_DMA_i_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_x2)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I0 (instanceRef G_161)) - (portRef I0 (instanceRef CYCLE_DMA_i_1)) - (portRef I0 (instanceRef pos_clk_un26_bgack_030_int)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_x2)) )) (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined (portRef Q (instanceRef SIZE_DMA_0)) (portRef I0 (instanceRef SIZE_DMA_0_0__n)) - (portRef I0 (instanceRef SIZE_DMA_i_0)) (portRef I0 (instanceRef un4_size)) + (portRef I0 (instanceRef SIZE_DMA_i_0)) )) (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined (portRef Q (instanceRef SIZE_DMA_1)) (portRef I0 (instanceRef SIZE_DMA_0_1__n)) - (portRef I0 (instanceRef un3_size)) (portRef I0 (instanceRef SIZE_DMA_i_1)) + (portRef I0 (instanceRef un3_size)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) - (portRef I0 (instanceRef VPA_D_i)) (portRef I1 (instanceRef pos_clk_un21_clk_000_ne_d0)) + (portRef I0 (instanceRef VPA_D_i)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) @@ -1211,22 +1212,23 @@ )) (net CLK_000_D1 (joined (portRef Q (instanceRef CLK_000_D1)) - (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0)) (portRef I0 (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0)) )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) + (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0)) (portRef I0 (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2)) (portRef D (instanceRef CLK_000_D1)) )) (net CLK_000_PE (joined (portRef Q (instanceRef CLK_000_PE)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_a2)) - (portRef I0 (instanceRef G_159)) - (portRef I0 (instanceRef CLK_000_PE_i)) (portRef I0 (instanceRef G_160)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_a2)) + (portRef I1 (instanceRef pos_clk_un4_bgack_000_i_o2)) + (portRef I0 (instanceRef CLK_000_PE_i)) (portRef I1 (instanceRef pos_clk_un5_clk_000_pe_1)) )) (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined @@ -1235,10 +1237,10 @@ )) (net CLK_000_NE (joined (portRef Q (instanceRef CLK_000_NE)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_0)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0_x2_0)) - (portRef I0 (instanceRef G_136)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0)) (portRef I0 (instanceRef CLK_000_NE_i)) + (portRef I0 (instanceRef G_135)) + (portRef I0 (instanceRef G_136)) (portRef I0 (instanceRef pos_clk_un9_clk_000_ne_2)) (portRef D (instanceRef CLK_000_NE_D0)) )) @@ -1248,11 +1250,11 @@ )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) (portRef I0 (instanceRef cpu_est_i_2)) (portRef I1 (instanceRef pos_clk_cpu_est_11_i_o4_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef pos_clk_un5_clk_000_pe_2)) (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0)) + (portRef I1 (instanceRef pos_clk_un5_clk_000_pe_2)) (portRef I1 (instanceRef pos_clk_un9_clk_000_ne_3)) )) (net (rename IPL_D0_0 "IPL_D0[0]") (joined @@ -1275,41 +1277,41 @@ )) (net CLK_000_NE_D0 (joined (portRef Q (instanceRef CLK_000_NE_D0)) - (portRef I0 (instanceRef cpu_est_0_0)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) (portRef I1 (instanceRef cpu_est_0_3__m)) (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_d0)) + (portRef I0 (instanceRef cpu_est_0_0)) )) (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined - (portRef O (instanceRef pos_clk_un6_bg_030)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a2)) (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o6_0_a4_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0_a2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a3_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0_a2)) )) (net AMIGA_BUS_ENABLE_DMA_HIGH (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__n)) )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) - (portRef I0 (instanceRef DSACK1_INT_0_n)) + (portRef I0 (instanceRef DSACK1_INT_0_m)) (portRef I0 (instanceRef DSACK1)) )) (net (rename pos_clk_CLK_000_P_SYNC_2_0 "pos_clk.CLK_000_P_SYNC_2[0]") (joined - (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0)) (portRef D (instanceRef CLK_000_P_SYNC_0)) )) (net (rename pos_clk_CLK_000_N_SYNC_2_0 "pos_clk.CLK_000_N_SYNC_2[0]") (joined - (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0)) + (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0)) (portRef I0 (instanceRef pos_clk_un7_clk_000_d0_1)) (portRef D (instanceRef CLK_000_N_SYNC_0)) )) @@ -1335,13 +1337,9 @@ (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_6)) (portRef I0 (instanceRef SM_AMIGA_i_6)) )) - (net AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i)) - )) (net (rename RST_DLY_0 "RST_DLY[0]") (joined (portRef Q (instanceRef RST_DLY_0)) - (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_0_x2_0)) + (portRef I1 (instanceRef G_135)) (portRef I1 (instanceRef G_136)) )) (net (rename RST_DLY_1 "RST_DLY[1]") (joined @@ -1380,8 +1378,8 @@ )) (net (rename RST_DLY_7 "RST_DLY[7]") (joined (portRef Q (instanceRef RST_DLY_7)) - (portRef I1 (instanceRef G_149)) (portRef I1 (instanceRef RESET_OUT_0_sqmuxa)) + (portRef I1 (instanceRef G_149)) )) (net (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (joined (portRef O (instanceRef pos_clk_un8_bg_030_i)) @@ -1470,17 +1468,6 @@ (portRef I0 (instanceRef CLK_000_N_SYNC_i_10)) (portRef D (instanceRef CLK_000_N_SYNC_11)) )) - (net (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) - (portRef I1 (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_r)) - )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) (portRef I0 (instanceRef RW_000_INT_0_n)) @@ -1491,24 +1478,32 @@ (portRef I0 (instanceRef RW_000_DMA_0_n)) (portRef I0 (instanceRef RW)) )) + (net (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) (net A0_DMA (joined (portRef Q (instanceRef A0_DMA)) (portRef I0 (instanceRef A0_DMA_0_n)) (portRef I0 (instanceRef A0)) )) + (net DS_000_ENABLE_1_sqmuxa (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) - (portRef I0 (instanceRef pos_clk_un40_bgack_030_int_1)) - (portRef I0 (instanceRef CLK_030_H_0)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I0 (instanceRef CLK_030_H_i)) )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o4_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o4_1)) + (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_0)) (portRef I0 (instanceRef SM_AMIGA_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) @@ -1520,26 +1515,28 @@ (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_2)) (portRef I0 (instanceRef SM_AMIGA_i_2)) )) - (net (rename pos_clk_un3_as_030_d0 "pos_clk.un3_as_030_d0") (joined - (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) - )) (net DS_000_ENABLE (joined (portRef Q (instanceRef DS_000_ENABLE)) - (portRef I0 (instanceRef DS_000_ENABLE_0_n)) (portRef I0 (instanceRef un6_lds_000_1)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) )) - (net (rename pos_clk_CYCLE_DMA_5_0 "pos_clk.CYCLE_DMA_5[0]") (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0)) - (portRef D (instanceRef CYCLE_DMA_0)) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) )) - (net (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5[1]") (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1)) - (portRef D (instanceRef CYCLE_DMA_1)) + (net DSACK1_INT_1_sqmuxa (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) )) - (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined - (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I0 (instanceRef A0_DMA_0_m)) + (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) + )) + (net N_3 (joined + (portRef O (instanceRef DS_000_DMA_0_p)) + (portRef I0 (instanceRef N_3_i)) )) (net N_4 (joined (portRef O (instanceRef SIZE_DMA_0_0__p)) @@ -1549,9 +1546,9 @@ (portRef O (instanceRef SIZE_DMA_0_1__p)) (portRef D (instanceRef SIZE_DMA_1)) )) - (net N_8 (joined - (portRef O (instanceRef A0_DMA_0_p)) - (portRef I0 (instanceRef N_8_i)) + (net N_6 (joined + (portRef O (instanceRef AS_000_DMA_0_p)) + (portRef I0 (instanceRef N_6_i)) )) (net N_9 (joined (portRef O (instanceRef DSACK1_INT_0_p)) @@ -1561,41 +1558,25 @@ (portRef O (instanceRef AS_000_INT_0_p)) (portRef I0 (instanceRef N_10_i)) )) - (net N_11 (joined - (portRef O (instanceRef DS_000_ENABLE_0_p)) - (portRef I0 (instanceRef DS_000_ENABLE_1)) - )) - (net N_12 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_p)) - (portRef I0 (instanceRef N_12_i)) - )) - (net N_13 (joined - (portRef O (instanceRef LDS_000_INT_0_p)) - (portRef I0 (instanceRef N_13_i)) - )) (net N_14 (joined - (portRef O (instanceRef RW_000_INT_0_p)) + (portRef O (instanceRef LDS_000_INT_0_p)) (portRef I0 (instanceRef N_14_i)) )) (net N_15 (joined - (portRef O (instanceRef RW_000_DMA_0_p)) + (portRef O (instanceRef RW_000_INT_0_p)) (portRef I0 (instanceRef N_15_i)) )) - (net N_16 (joined + (net N_17 (joined (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef I0 (instanceRef N_16_i)) + (portRef I0 (instanceRef N_17_i)) )) (net N_19 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef O (instanceRef VMA_INT_0_p)) (portRef I0 (instanceRef N_19_i)) )) - (net N_20 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - (portRef I0 (instanceRef N_20_i)) - )) - (net N_21 (joined + (net N_22 (joined (portRef O (instanceRef BG_000_0_p)) - (portRef I0 (instanceRef N_21_i)) + (portRef I0 (instanceRef N_22_i)) )) (net N_23 (joined (portRef O (instanceRef IPL_030_0_0__p)) @@ -1638,41 +1619,41 @@ (portRef D (instanceRef IPL_030DFF_2)) )) (net N_33 (joined - (portRef O (instanceRef BGACK_030_INT_1_i)) - (portRef D (instanceRef BGACK_030_INT)) - )) - (net N_34 (joined (portRef O (instanceRef BG_000_1_i)) (portRef D (instanceRef BG_000DFF)) )) - (net N_35 (joined + (net N_34 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) )) - (net N_36 (joined + (net N_35 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) )) - (net N_37 (joined + (net N_36 (joined (portRef O (instanceRef VMA_INT_1_i)) (portRef D (instanceRef VMA_INT)) )) - (net N_39 (joined + (net N_38 (joined (portRef O (instanceRef UDS_000_INT_1_i)) (portRef D (instanceRef UDS_000_INT)) )) - (net N_40 (joined + (net N_39 (joined (portRef O (instanceRef RW_000_DMA_2_i)) (portRef D (instanceRef RW_000_DMA)) )) - (net N_41 (joined + (net N_40 (joined (portRef O (instanceRef RW_000_INT_2_i)) (portRef D (instanceRef RW_000_INT)) )) - (net N_42 (joined + (net N_41 (joined (portRef O (instanceRef LDS_000_INT_1_i)) (portRef D (instanceRef LDS_000_INT)) )) + (net N_42 (joined + (portRef O (instanceRef BGACK_030_INT_1_i)) + (portRef D (instanceRef BGACK_030_INT)) + )) (net N_43 (joined (portRef O (instanceRef AS_030_000_SYNC_1_i)) (portRef D (instanceRef AS_030_000_SYNC)) @@ -1725,14 +1706,6 @@ (portRef O (instanceRef DTACK_D0_0_i)) (portRef D (instanceRef DTACK_D0)) )) - (net N_58 (joined - (portRef O (instanceRef CLK_030_H_2)) - (portRef D (instanceRef CLK_030_H)) - )) - (net N_59 (joined - (portRef O (instanceRef RESET_OUT_2)) - (portRef D (instanceRef RESET_OUT)) - )) (net N_60 (joined (portRef O (instanceRef DS_000_ENABLE_1)) (portRef D (instanceRef DS_000_ENABLE)) @@ -1748,13 +1721,17 @@ (portRef I1 (instanceRef RW_000_INT_0_m)) (portRef I0 (instanceRef RW_000_INT_0_r)) )) - (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__m)) + (net (rename pos_clk_cpu_est_11_1 "pos_clk.cpu_est_11[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) )) - (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__m)) + (net (rename pos_clk_cpu_est_11_3 "pos_clk.cpu_est_11[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__m)) + )) + (net N_220 (joined + (portRef O (instanceRef G_160)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) )) (net N_224 (joined (portRef O (instanceRef G_165)) @@ -1773,81 +1750,77 @@ (portRef I1 (instanceRef un6_uds_000)) (portRef I1 (instanceRef un6_lds_000)) )) - (net N_241 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_i)) - (portRef I1 (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef DS_000_ENABLE_0_r)) - )) - (net N_242 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_i)) - (portRef I1 (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_r)) - )) - (net N_243 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_i)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) + (net (rename pos_clk_un24_bgack_030_int_i_0 "pos_clk.un24_bgack_030_int_i_0") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_i)) + (portRef I0 (instanceRef AS_000_DMA_0_m)) )) (net N_244 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_i)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) )) (net N_245 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + (portRef I1 (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_r)) )) - (net N_246 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_i)) - (portRef I1 (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__r)) - (portRef I1 (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_0_0__r)) - )) - (net N_78 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__p)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) + (net N_257 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_i)) + (portRef D (instanceRef BGACK_030_INT_D)) )) (net N_80 (joined - (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) - (portRef I0 (instanceRef N_80_i)) - )) - (net N_89 (joined - (portRef O (instanceRef AS_030_D0_0_i_a2)) - (portRef I0 (instanceRef N_89_i)) + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) )) (net N_90 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef O (instanceRef AS_030_D0_0_i_a2)) (portRef I0 (instanceRef N_90_i)) )) - (net N_91 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) - (portRef I0 (instanceRef N_91_i)) - )) - (net N_98 (joined - (portRef O (instanceRef un1_as_000_i_a2)) - (portRef OE (instanceRef AS_000)) - (portRef OE (instanceRef LDS_000)) - (portRef OE (instanceRef RW_000)) - (portRef OE (instanceRef UDS_000)) - )) - (net N_99 (joined + (net N_100 (joined (portRef O (instanceRef un2_rw_i_a2)) (portRef OE (instanceRef RW)) )) - (net N_249 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_i_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (net N_105 (joined + (portRef O (instanceRef pos_clk_un3_as_030_d0_i_a2)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1)) + (portRef I0 (instanceRef N_105_i)) )) - (net N_248 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_p)) - (portRef I0 (instanceRef N_248_i)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i)) + (net (rename pos_clk_un11_clk_000_n_sync "pos_clk.un11_clk_000_n_sync") (joined + (portRef O (instanceRef pos_clk_un11_clk_000_n_sync)) + (portRef I0 (instanceRef pos_clk_un11_clk_000_n_sync_i)) + )) + (net N_78_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + )) + (net N_79_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) )) (net N_135 (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0_i_0)) (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_1_0_0)) )) + (net N_133 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_0_1_0)) + )) + (net N_190 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_i_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_3)) + )) + (net N_188 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_o4_i_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_1_2)) + )) + (net N_189 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_i_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_1)) + )) (net N_136 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_3)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_3)) @@ -1856,10 +1829,77 @@ (portRef O (instanceRef pos_clk_un7_clk_000_d0)) (portRef I0 (instanceRef pos_clk_un7_clk_000_d0_i)) )) - (net un22_berr_1 (joined - (portRef O (instanceRef un22_berr_0_a2_1)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2)) - (portRef I0 (instanceRef un22_berr_0_a2_1_0)) + (net (rename pos_clk_un29_clk_000_ne_d0 "pos_clk.un29_clk_000_ne_d0") (joined + (portRef O (instanceRef pos_clk_un29_clk_000_ne_d0)) + (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_d0_i)) + )) + (net DSACK1_INT_0_sqmuxa (joined + (portRef O (instanceRef DSACK1_INT_0_sqmuxa)) + (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i)) + )) + (net (rename pos_clk_un21_clk_000_ne_d0 "pos_clk.un21_clk_000_ne_d0") (joined + (portRef O (instanceRef pos_clk_un21_clk_000_ne_d0)) + (portRef I0 (instanceRef pos_clk_un21_clk_000_ne_d0_i)) + )) + (net (rename pos_clk_un5_clk_000_pe "pos_clk.un5_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un5_clk_000_pe)) + (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_i)) + )) + (net (rename pos_clk_un9_clk_000_ne "pos_clk.un9_clk_000_ne") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_ne)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_ne_i)) + )) + (net (rename pos_clk_un23_clk_000_ne_d0 "pos_clk.un23_clk_000_ne_d0") (joined + (portRef O (instanceRef pos_clk_un23_clk_000_ne_d0_i)) + (portRef I1 (instanceRef pos_clk_un29_clk_000_ne_d0)) + )) + (net (rename pos_clk_un27_clk_000_ne_d0 "pos_clk.un27_clk_000_ne_d0") (joined + (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0)) + (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_i)) + )) + (net (rename pos_clk_un14_clk_000_n_sync "pos_clk.un14_clk_000_n_sync") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_n_sync_i)) + (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa)) + )) + (net N_144 (joined + (portRef O (instanceRef un1_SM_AMIGA_3_0_a6)) + (portRef I0 (instanceRef N_144_i)) + )) + (net N_146 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0)) + (portRef I0 (instanceRef N_146_i)) + )) + (net N_143 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0)) + )) + (net N_147 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_1)) + (portRef I0 (instanceRef N_147_i)) + )) + (net N_139 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_1)) + )) + (net N_148 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_1)) + (portRef I0 (instanceRef N_148_i)) + )) + (net N_149 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_1_1)) + (portRef I0 (instanceRef N_149_i)) + )) + (net N_150 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_2)) + (portRef I0 (instanceRef N_150_i)) + )) + (net N_140 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_2)) + )) + (net N_151 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_2)) + (portRef I0 (instanceRef N_151_i)) )) (net N_152 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_a6_3)) @@ -1885,22 +1925,6 @@ (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_4)) (portRef I0 (instanceRef N_156_i)) )) - (net N_157 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a6_5)) - (portRef I0 (instanceRef N_157_i)) - )) - (net N_138 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_5)) - )) - (net N_158 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_5)) - (portRef I0 (instanceRef N_158_i)) - )) - (net N_159 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a6_1_5)) - (portRef I0 (instanceRef N_159_i)) - )) (net N_160 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_a6_6)) (portRef I0 (instanceRef N_160_i)) @@ -1913,59 +1937,94 @@ (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_6)) (portRef I0 (instanceRef N_161_i)) )) + (net N_164 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_1_0)) + (portRef I0 (instanceRef N_164_i)) + )) + (net N_166 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a3_0)) + (portRef I0 (instanceRef N_166_i)) + )) (net N_132 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o6_0_a4_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a3_0)) )) - (net N_104 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o6_0_a4_0)) - (portRef I0 (instanceRef N_104_i)) + (net N_191 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_1)) + (portRef I0 (instanceRef N_191_i)) )) - (net N_76 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - (portRef I0 (instanceRef N_76_i)) + (net N_192 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_0_1)) + (portRef I0 (instanceRef N_192_i)) )) - (net N_71 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + (net N_193 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_1_1)) + (portRef I0 (instanceRef N_193_i)) )) - (net N_251 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o4_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2)) + (net N_194 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef N_194_i)) )) - (net N_93 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2)) - (portRef I0 (instanceRef N_93_i)) + (net N_197 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_3)) + (portRef I0 (instanceRef N_197_i)) + )) + (net N_198 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_0_3)) + (portRef I0 (instanceRef N_198_i)) + )) + (net N_195 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_2)) + (portRef I0 (instanceRef N_195_i)) + )) + (net N_196 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_0_2)) + (portRef I0 (instanceRef N_196_i)) + )) + (net N_162 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_0)) + (portRef I0 (instanceRef N_162_i)) + )) + (net N_199 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_1_3)) + (portRef I0 (instanceRef N_199_i)) + )) + (net N_199_1 (joined + (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_1_3)) + (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_1)) + )) + (net N_163 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_0_0)) + (portRef I0 (instanceRef N_163_i)) + )) + (net N_165 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_0)) + (portRef I0 (instanceRef N_165_i)) + )) + (net N_73 (joined + (portRef O (instanceRef CLK_030_H_2_i_o2_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_a2)) )) (net N_94 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef O (instanceRef CLK_030_H_2_i_a2)) (portRef I0 (instanceRef N_94_i)) )) - (net N_88 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - (portRef I0 (instanceRef N_88_i)) - )) - (net N_87 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) - (portRef I0 (instanceRef N_87_i)) - )) - (net N_86 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I0 (instanceRef N_86_i)) + (net N_85 (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I0 (instanceRef N_85_i)) )) (net N_84 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_i_0_a2)) + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) (portRef I0 (instanceRef N_84_i)) )) (net N_83 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + (portRef O (instanceRef un1_SM_AMIGA_5_i_0_a2)) (portRef I0 (instanceRef N_83_i)) )) - (net N_116 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) - (portRef I1 (instanceRef un22_berr_0_a2)) + (net (rename pos_clk_un9_clk_000_n_sync "pos_clk.un9_clk_000_n_sync") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_n_sync)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_n_sync_i)) )) (net (rename un1_RST_DLY_8 "un1_RST_DLY[8]") (joined (portRef O (instanceRef G_149)) @@ -2025,8 +2084,8 @@ )) (net RESET_OUT_0_sqmuxa_7 (joined (portRef O (instanceRef RESET_OUT_0_sqmuxa_7)) - (portRef I0 (instanceRef G_149)) (portRef I0 (instanceRef RESET_OUT_0_sqmuxa)) + (portRef I0 (instanceRef G_149)) )) (net RESET_OUT_0_sqmuxa_5 (joined (portRef O (instanceRef RESET_OUT_0_sqmuxa_5)) @@ -2062,271 +2121,173 @@ (portRef O (instanceRef un1_RST_DLY_i_m_2)) (portRef I0 (instanceRef un1_RST_DLY_i_m_i_2)) )) - (net N_38 (joined - (portRef O (instanceRef RESET_OUT_1_i)) - (portRef I0 (instanceRef RESET_OUT_2)) + (net N_86 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I0 (instanceRef N_86_i)) )) - (net N_85 (joined - (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0_a2_0)) - (portRef I0 (instanceRef N_85_i)) + (net N_93 (joined + (portRef O (instanceRef RESET_OUT_2_i_a2)) + (portRef I0 (instanceRef N_93_i)) )) - (net N_77_i (joined - (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0_x2_0)) - (portRef I0 (instanceRef N_77_i_i)) + (net N_87 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + (portRef I0 (instanceRef N_87_i)) )) - (net N_252 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + (net (rename un1_RST_DLY_1 "un1_RST_DLY[1]") (joined + (portRef O (instanceRef G_135)) + (portRef I0 (instanceRef un1_RST_DLY_i_1)) + )) + (net N_159 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_1_5)) + (portRef I0 (instanceRef N_159_i)) + )) + (net N_157 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_5)) + (portRef I0 (instanceRef N_157_i)) + )) + (net N_158 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_5)) + (portRef I0 (instanceRef N_158_i)) + )) + (net (rename un1_RST_DLY_i_m_1 "un1_RST_DLY_i_m[1]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_1)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_i_1)) + )) + (net N_138 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_5)) + )) + (net N_88 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef N_88_i)) + )) + (net N_256 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + )) + (net N_89 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (portRef I0 (instanceRef N_89_i)) + )) + (net N_91 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I0 (instanceRef N_91_i)) + )) + (net N_92 (joined + (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I0 (instanceRef N_92_i)) + )) + (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined + (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I0 (instanceRef A0_DMA_0_m)) + )) + (net N_96 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2)) + (portRef I0 (instanceRef N_96_i)) + )) + (net N_72 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o2_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2)) )) (net N_97 (joined - (portRef O (instanceRef pos_clk_un4_bgack_000_i_a2)) + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef I0 (instanceRef N_97_i)) + )) + (net N_116 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I1 (instanceRef un22_berr_0_a2)) + )) + (net N_104 (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_a2)) + (portRef I0 (instanceRef N_104_i)) + )) + (net N_76 (joined + (portRef O (instanceRef pos_clk_un4_bgack_000_i_o2_i)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__m)) + )) + (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__m)) + )) + (net N_250 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_i)) (portRef I1 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) - (net (rename pos_clk_un27_clk_000_ne_d0 "pos_clk.un27_clk_000_ne_d0") (joined - (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0)) - (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_i)) + (net N_251 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0_i)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) )) - (net N_199_1 (joined - (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_2)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_1_3)) - (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_1)) + (net N_252 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_i)) + (portRef I1 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__r)) )) - (net (rename pos_clk_un5_clk_000_pe "pos_clk.un5_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un5_clk_000_pe)) - (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_i)) + (net (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) )) - (net (rename pos_clk_un9_clk_000_ne "pos_clk.un9_clk_000_ne") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_ne)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_ne_i)) + (net N_63_i (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_x2)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_2)) )) - (net N_150 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a6_2)) - (portRef I0 (instanceRef N_150_i)) + (net DS_000_ENABLE_1_sqmuxa_1 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1)) + (portRef I1 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_r)) )) - (net N_151 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a6_0_2)) - (portRef I0 (instanceRef N_151_i)) + (net un22_berr_1 (joined + (portRef O (instanceRef un22_berr_0_a2_1)) + (portRef I0 (instanceRef un22_berr_0_a2_1_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2)) )) - (net N_199 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_1_3)) - (portRef I0 (instanceRef N_199_i)) + (net N_8 (joined + (portRef O (instanceRef A0_DMA_0_p)) + (portRef I0 (instanceRef N_8_i)) )) - (net N_196 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_0_2)) - (portRef I0 (instanceRef N_196_i)) + (net N_12 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_p)) + (portRef I0 (instanceRef N_12_i)) )) - (net N_195 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_2)) - (portRef I0 (instanceRef N_195_i)) - )) - (net N_188 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_o4_i_2)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_1_2)) - )) - (net (rename pos_clk_cpu_est_11_3 "pos_clk.cpu_est_11[3]") (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__m)) - )) - (net N_197 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_3)) - (portRef I0 (instanceRef N_197_i)) - )) - (net N_198 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef N_198_i)) - )) - (net (rename pos_clk_cpu_est_11_1 "pos_clk.cpu_est_11[1]") (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) - )) - (net N_194 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef N_194_i)) - )) - (net N_192 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_0_1)) - (portRef I0 (instanceRef N_192_i)) - )) - (net N_191 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_1)) - (portRef I0 (instanceRef N_191_i)) - )) - (net N_193 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef N_193_i)) - )) - (net N_190 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_i_3)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_3)) - )) - (net N_189 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_i_1)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_1)) - )) - (net N_140 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_2)) - )) - (net (rename pos_clk_un29_clk_000_ne_d0 "pos_clk.un29_clk_000_ne_d0") (joined - (portRef O (instanceRef pos_clk_un29_clk_000_ne_d0)) - (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_d0_i)) - )) - (net (rename pos_clk_un23_clk_000_ne_d0 "pos_clk.un23_clk_000_ne_d0") (joined - (portRef O (instanceRef pos_clk_un23_clk_000_ne_d0_i)) - (portRef I1 (instanceRef pos_clk_un29_clk_000_ne_d0)) - )) - (net (rename pos_clk_un21_clk_000_ne_d0 "pos_clk.un21_clk_000_ne_d0") (joined - (portRef O (instanceRef pos_clk_un21_clk_000_ne_d0)) - (portRef I0 (instanceRef pos_clk_un21_clk_000_ne_d0_i)) - )) - (net (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) - )) - (net N_18 (joined - (portRef O (instanceRef VMA_INT_0_p)) - (portRef I0 (instanceRef N_18_i)) - )) - (net N_22 (joined + (net N_13 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef I0 (instanceRef N_22_i)) + (portRef I0 (instanceRef N_13_i)) )) - (net (rename pos_clk_un11_clk_000_n_sync "pos_clk.un11_clk_000_n_sync") (joined - (portRef O (instanceRef pos_clk_un11_clk_000_n_sync)) - (portRef I0 (instanceRef pos_clk_un11_clk_000_n_sync_i)) + (net N_16 (joined + (portRef O (instanceRef RW_000_DMA_0_p)) + (portRef I0 (instanceRef N_16_i)) )) - (net (rename pos_clk_un9_clk_000_n_sync "pos_clk.un9_clk_000_n_sync") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_n_sync)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_n_sync_i)) + (net N_20 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef I0 (instanceRef N_20_i)) )) - (net (rename pos_clk_un14_clk_000_n_sync "pos_clk.un14_clk_000_n_sync") (joined - (portRef O (instanceRef pos_clk_un14_clk_000_n_sync_i)) - (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) + (net N_21 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (portRef I0 (instanceRef N_21_i)) )) - (net (rename pos_clk_un22_bgack_030_int "pos_clk.un22_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un22_bgack_030_int_i)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_1)) - )) - (net (rename un1_CYCLE_DMA_1_2 "un1_CYCLE_DMA_1[2]") (joined - (portRef O (instanceRef G_161)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1)) - )) - (net N_220 (joined - (portRef O (instanceRef G_160)) - (portRef I1 (instanceRef G_161)) - )) - (net (rename un1_CYCLE_DMA_1_1 "un1_CYCLE_DMA_1[1]") (joined - (portRef O (instanceRef G_159)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0)) - )) - (net (rename pos_clk_un40_bgack_030_int_1 "pos_clk.un40_bgack_030_int_1") (joined - (portRef O (instanceRef pos_clk_un40_bgack_030_int_1)) - (portRef I0 (instanceRef pos_clk_un40_bgack_030_int_1_i)) - )) - (net CLK_030_H_0_sqmuxa (joined - (portRef O (instanceRef CLK_030_H_0_sqmuxa)) - (portRef I0 (instanceRef CLK_030_H_0_sqmuxa_i)) - )) - (net AS_000_DMA_1_sqmuxa (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I0 (instanceRef CLK_030_H_0_sqmuxa)) - (portRef I1 (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_r)) - )) - (net (rename pos_clk_un24_bgack_030_int "pos_clk.un24_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f1)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I1 (instanceRef DS_000_DMA_0_sqmuxa)) - (portRef I1 (instanceRef CLK_030_H_0)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_1)) - )) - (net (rename pos_clk_un27_bgack_030_int "pos_clk.un27_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un27_bgack_030_int_i)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int)) - )) - (net N_176_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) - (portRef I0 (instanceRef un1_rst_2)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) - )) - (net N_165 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_0)) - (portRef I0 (instanceRef N_165_i)) - )) - (net N_133 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_0_1_0)) - )) - (net N_163 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_0_0)) - (portRef I0 (instanceRef N_163_i)) - )) - (net N_162 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_0)) - (portRef I0 (instanceRef N_162_i)) - )) - (net N_164 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_1_0)) - (portRef I0 (instanceRef N_164_i)) - )) - (net N_176 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) - (portRef I0 (instanceRef N_176_i)) - )) - (net DS_000_DMA_2_sqmuxa (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa)) - (portRef I1 (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_r)) - )) - (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0)) - (portRef I0 (instanceRef DS_000_DMA_0_n)) - )) - (net DS_000_DMA_0_sqmuxa (joined - (portRef O (instanceRef DS_000_DMA_0_sqmuxa)) - (portRef I0 (instanceRef DS_000_DMA_0_sqmuxa_i)) - )) - (net (rename pos_clk_DS_000_DMA_4_f1 "pos_clk.DS_000_DMA_4_f1") (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f1_i)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0)) - )) - (net N_175 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) - (portRef I0 (instanceRef N_175_i)) - )) - (net N_47 (joined - (portRef O (instanceRef CLK_030_H_1_i)) - (portRef I0 (instanceRef CLK_030_H_2)) - )) - (net N_7 (joined - (portRef O (instanceRef CLK_030_H_0)) - (portRef I0 (instanceRef N_7_i)) - )) - (net un1_rst_2 (joined - (portRef O (instanceRef un1_rst_2)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1)) - )) - (net (rename pos_clk_un26_bgack_030_int "pos_clk.un26_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un26_bgack_030_int)) - (portRef I0 (instanceRef pos_clk_un26_bgack_030_int_i)) - )) - (net (rename pos_clk_un29_bgack_030_int "pos_clk.un29_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un29_bgack_030_int)) - (portRef I0 (instanceRef pos_clk_un29_bgack_030_int_i)) - )) - (net N_3 (joined - (portRef O (instanceRef DS_000_DMA_0_p)) - (portRef I0 (instanceRef N_3_i)) - )) - (net N_6 (joined - (portRef O (instanceRef AS_000_DMA_0_p)) - (portRef I0 (instanceRef N_6_i)) + (net N_11 (joined + (portRef O (instanceRef DS_000_ENABLE_0_p)) + (portRef I0 (instanceRef DS_000_ENABLE_1)) )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) @@ -2336,200 +2297,171 @@ (portRef O (instanceRef un21_fpu_cs_i)) (portRef I0 (instanceRef FPU_CS)) )) - (net AS_000_i (joined - (portRef O (instanceRef I_234)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) - (portRef I0 (instanceRef un6_ds_030)) - (portRef I1 (instanceRef un6_as_030)) - )) - (net DS_000_DMA_i (joined - (portRef O (instanceRef DS_000_DMA_i)) - (portRef I1 (instanceRef un6_ds_030)) - )) - (net (rename pos_clk_un24_bgack_030_int_i "pos_clk.un24_bgack_030_int_i") (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i)) - (portRef I0 (instanceRef AS_000_DMA_0_n)) - )) - (net (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (joined - (portRef O (instanceRef CYCLE_DMA_i_1)) - (portRef I1 (instanceRef pos_clk_un29_bgack_030_int)) - )) - (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined - (portRef O (instanceRef CYCLE_DMA_i_0)) - (portRef I1 (instanceRef pos_clk_un26_bgack_030_int)) - )) - (net AS_000_DMA_i (joined - (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f1)) - (portRef I1 (instanceRef CLK_030_H_0_sqmuxa)) - (portRef I0 (instanceRef un6_as_030)) - )) - (net CLK_EXP_i (joined - (portRef O (instanceRef CLK_EXP_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa)) - )) - (net BERR_i (joined - (portRef O (instanceRef I_235)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_1_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_0_1_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_1_0_0)) - )) - (net RW_000_i (joined - (portRef O (instanceRef I_236)) - (portRef I1 (instanceRef un14_amiga_bus_data_dir)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_1)) - )) - (net DS_000_DMA_0_sqmuxa_i (joined - (portRef O (instanceRef DS_000_DMA_0_sqmuxa_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0)) - )) - (net (rename pos_clk_un40_bgack_030_int_1_i "pos_clk.un40_bgack_030_int_1_i") (joined - (portRef O (instanceRef pos_clk_un40_bgack_030_int_1_i)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa)) - )) (net BGACK_030_INT_i (joined (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir)) (portRef I0 (instanceRef un1_as_030)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) - (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) (portRef I0 (instanceRef un2_rw_i_a2)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I1 (instanceRef un1_amiga_bus_enable_low)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_1)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) )) - (net nEXP_SPACE_D0_i (joined - (portRef O (instanceRef nEXP_SPACE_D0_i)) - (portRef I1 (instanceRef un1_as_030)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) + (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef un1_amiga_bus_enable_low)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_224)) + (portRef I0 (instanceRef AS_030_D0_0_i_a2)) + (portRef I0 (instanceRef un22_berr_0_a2_1)) + (portRef I1 (instanceRef un4_as_000)) + )) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef un4_as_000)) + )) + (net N_105_i (joined + (portRef O (instanceRef N_105_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net N_91_i (joined + (portRef O (instanceRef N_91_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + )) + (net N_92_i (joined + (portRef O (instanceRef N_92_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + )) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + )) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + )) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) + )) + (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined + (portRef O (instanceRef SIZE_DMA_i_1)) + (portRef I1 (instanceRef un4_size)) + )) + (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined + (portRef O (instanceRef SIZE_DMA_i_0)) + (portRef I1 (instanceRef un3_size)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_1)) + )) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0)) + )) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_d0_1)) + )) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef pos_clk_un3_as_030_d0_i_a2)) + (portRef I0 (instanceRef un5_ciin_1)) + )) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_225)) + (portRef I0 (instanceRef un6_ds_030)) + (portRef I1 (instanceRef un6_as_030_0_a2)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) )) (net CLK_000_PE_i (joined (portRef O (instanceRef CLK_000_PE_i)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_1_1)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_0_0)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_1_5)) - (portRef I1 (instanceRef pos_clk_un4_bgack_000_i_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_0)) )) - (net CLK_000_NE_i (joined - (portRef O (instanceRef CLK_000_NE_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_1)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_0_0)) + (net nEXP_SPACE_D0_i (joined + (portRef O (instanceRef nEXP_SPACE_D0_i)) + (portRef I0 (instanceRef un8_ciin)) + (portRef I1 (instanceRef un1_as_030)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_2)) )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_1_3)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_n)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_2_0)) + (net A1_i (joined + (portRef O (instanceRef A1_i)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_2_0)) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_5)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_o3_0_0)) )) - (net (rename pos_clk_un7_clk_000_d0_i "pos_clk.un7_clk_000_d0_i") (joined - (portRef O (instanceRef pos_clk_un7_clk_000_d0_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_6)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_0)) + (net BERR_i (joined + (portRef O (instanceRef I_226)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_5)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_0_1_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_1_0_0)) )) - (net UDS_000_i (joined - (portRef O (instanceRef I_237)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_0)) - )) - (net LDS_000_i (joined - (portRef O (instanceRef I_238)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_0)) - )) - (net (rename pos_clk_un11_clk_000_n_sync_i "pos_clk.un11_clk_000_n_sync_i") (joined - (portRef O (instanceRef pos_clk_un11_clk_000_n_sync_i)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_n_sync)) - )) - (net CLK_OUT_PRE_D_i (joined - (portRef O (instanceRef CLK_OUT_PRE_D_i)) - (portRef I1 (instanceRef pos_clk_un11_clk_000_n_sync)) - )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef pos_clk_un21_clk_000_ne_d0)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_2)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0_1_0)) - )) - (net (rename pos_clk_un29_clk_000_ne_d0_i "pos_clk.un29_clk_000_ne_d0_i") (joined - (portRef O (instanceRef pos_clk_un29_clk_000_ne_d0_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_2)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_2)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_1)) - (portRef I1 (instanceRef pos_clk_un5_clk_000_pe)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_0_1_2)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_ne_1)) - (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_1)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_2)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_1_3)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_0_3)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_0_2)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_2)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_ne_1)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_2_0)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_ne_2)) - )) - (net VMA_INT_i (joined - (portRef O (instanceRef VMA_INT_i)) - (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_2_0)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0)) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_4)) + (portRef I1 (instanceRef un1_SM_AMIGA_3_0_a6)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_o3_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_1_5)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0_1)) )) (net RESET_OUT_0_sqmuxa_i (joined (portRef O (instanceRef RESET_OUT_0_sqmuxa_i)) - (portRef I0 (instanceRef un1_RST_DLY_i_m_5)) - (portRef I0 (instanceRef un1_RST_DLY_i_m_6)) (portRef I0 (instanceRef un1_RST_DLY_i_m_7)) (portRef I0 (instanceRef un1_RST_DLY_i_m_8)) - (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_0_a2_0)) - (portRef I0 (instanceRef RESET_OUT_1)) (portRef I0 (instanceRef un1_RST_DLY_i_m_2)) (portRef I0 (instanceRef un1_RST_DLY_i_m_3)) (portRef I0 (instanceRef un1_RST_DLY_i_m_4)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_5)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_6)) + (portRef I0 (instanceRef un1_RST_DLY_i_m_1)) + (portRef I0 (instanceRef RESET_OUT_2_i_a2)) )) - (net N_77_i_i (joined - (portRef O (instanceRef N_77_i_i)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0_a2_0)) + (net (rename un1_RST_DLY_i_1 "un1_RST_DLY_i[1]") (joined + (portRef O (instanceRef un1_RST_DLY_i_1)) + (portRef I1 (instanceRef un1_RST_DLY_i_m_1)) + )) + (net RESET_OUT_i (joined + (portRef O (instanceRef RESET_OUT_i)) + (portRef I1 (instanceRef RESET_OUT_2_i_a2)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_227)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I1 (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) )) (net (rename un1_RST_DLY_i_2 "un1_RST_DLY_i[2]") (joined (portRef O (instanceRef un1_RST_DLY_i_2)) @@ -2559,141 +2491,168 @@ (portRef O (instanceRef un1_RST_DLY_i_8)) (portRef I1 (instanceRef un1_RST_DLY_i_m_8)) )) - (net RESET_OUT_i (joined - (portRef O (instanceRef RESET_OUT_i)) - (portRef I1 (instanceRef RESET_OUT_1)) + (net CLK_OUT_PRE_D_i (joined + (portRef O (instanceRef CLK_OUT_PRE_D_i)) + (portRef I1 (instanceRef pos_clk_un11_clk_000_n_sync)) )) - (net AS_030_D0_i (joined - (portRef O (instanceRef AS_030_D0_i)) - (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2)) - (portRef I0 (instanceRef un8_ciin_2)) + (net (rename pos_clk_un11_clk_000_n_sync_i "pos_clk.un11_clk_000_n_sync_i") (joined + (portRef O (instanceRef pos_clk_un11_clk_000_n_sync_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_n_sync)) )) - (net AS_030_i (joined - (portRef O (instanceRef I_239)) - (portRef I1 (instanceRef un4_as_000)) - (portRef I0 (instanceRef un22_berr_0_a2_1)) - (portRef I0 (instanceRef AS_030_D0_0_i_a2)) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_a2)) )) - (net A1_i (joined - (portRef O (instanceRef A1_i)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef un6_as_030_0_a2)) )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_2_0)) )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__m)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o4_1)) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_ne_2)) + (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_2_0)) )) - (net N_248_i (joined - (portRef O (instanceRef N_248_i)) - (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_1)) + (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_0_1_2)) + (portRef I1 (instanceRef pos_clk_un5_clk_000_pe)) )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_1_5)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_o3_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_i_0_1)) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_1)) + (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_ne_1)) )) - (net RW_i (joined - (portRef O (instanceRef I_240)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_m)) - )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0)) - )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_d0_1)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_5)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_o3_0_0)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_o3_0_1_0)) - )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_1)) - )) - (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined - (portRef O (instanceRef SIZE_DMA_i_0)) - (portRef I1 (instanceRef un3_size)) - )) - (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined - (portRef O (instanceRef SIZE_DMA_i_1)) - (portRef I1 (instanceRef un4_size)) - )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) - )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) - )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) - )) - (net (rename A_i_30 "A_i[30]") (joined - (portRef O (instanceRef A_i_30)) - (portRef I1 (instanceRef un8_ciin_5)) - )) - (net (rename A_i_31 "A_i[31]") (joined - (portRef O (instanceRef A_i_31)) - (portRef I0 (instanceRef un8_ciin_1)) - )) - (net (rename A_i_28 "A_i[28]") (joined - (portRef O (instanceRef A_i_28)) - (portRef I1 (instanceRef un8_ciin_4)) - )) - (net (rename A_i_29 "A_i[29]") (joined - (portRef O (instanceRef A_i_29)) - (portRef I0 (instanceRef un8_ciin_5)) - )) - (net (rename A_i_26 "A_i[26]") (joined - (portRef O (instanceRef A_i_26)) - (portRef I1 (instanceRef un8_ciin_3)) - )) - (net (rename A_i_27 "A_i[27]") (joined - (portRef O (instanceRef A_i_27)) - (portRef I0 (instanceRef un8_ciin_4)) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_o4_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_ne_1)) + (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_1)) )) (net (rename A_i_24 "A_i[24]") (joined (portRef O (instanceRef A_i_24)) - (portRef I1 (instanceRef un8_ciin_2)) + (portRef I1 (instanceRef un5_ciin_3)) + )) + (net (rename pos_clk_un7_clk_000_d0_i "pos_clk.un7_clk_000_d0_i") (joined + (portRef O (instanceRef pos_clk_un7_clk_000_d0_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_0)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_2_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_1_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_2)) + (portRef I0 (instanceRef un1_SM_AMIGA_3_0_a6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_2_0)) + )) + (net CLK_000_NE_i (joined + (portRef O (instanceRef CLK_000_NE_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_5)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_0_0)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_1_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_a4_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_a4_0_2)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_1_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_4)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_o3_0_1_0)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_a6_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0_1_0)) + )) + (net (rename pos_clk_un29_clk_000_ne_d0_i "pos_clk.un29_clk_000_ne_d0_i") (joined + (portRef O (instanceRef pos_clk_un29_clk_000_ne_d0_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_a6_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_3)) + )) + (net DSACK1_INT_0_sqmuxa_i (joined + (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i)) + (portRef I0 (instanceRef DSACK1_INT_0_n)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa)) + )) + (net RW_i (joined + (portRef O (instanceRef I_228)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa)) + )) + (net un5_ciin_i (joined + (portRef O (instanceRef un5_ciin_i)) + (portRef I1 (instanceRef un8_ciin)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef pos_clk_un21_clk_000_ne_d0)) + )) + (net (rename A_i_31 "A_i[31]") (joined + (portRef O (instanceRef A_i_31)) + (portRef I0 (instanceRef un5_ciin_5)) + )) + (net (rename A_i_29 "A_i[29]") (joined + (portRef O (instanceRef A_i_29)) + (portRef I1 (instanceRef un5_ciin_6)) + )) + (net (rename A_i_30 "A_i[30]") (joined + (portRef O (instanceRef A_i_30)) + (portRef I1 (instanceRef un5_ciin_11)) + )) + (net (rename A_i_27 "A_i[27]") (joined + (portRef O (instanceRef A_i_27)) + (portRef I1 (instanceRef un5_ciin_5)) + )) + (net (rename A_i_28 "A_i[28]") (joined + (portRef O (instanceRef A_i_28)) + (portRef I0 (instanceRef un5_ciin_6)) )) (net (rename A_i_25 "A_i[25]") (joined (portRef O (instanceRef A_i_25)) - (portRef I0 (instanceRef un8_ciin_3)) + (portRef I0 (instanceRef un5_ciin_4)) + )) + (net (rename A_i_26 "A_i[26]") (joined + (portRef O (instanceRef A_i_26)) + (portRef I1 (instanceRef un5_ciin_4)) + )) + (net UDS_000_INT_i (joined + (portRef O (instanceRef UDS_000_INT_i)) + (portRef I0 (instanceRef un6_uds_000)) )) (net LDS_000_INT_i (joined (portRef O (instanceRef LDS_000_INT_i)) (portRef I0 (instanceRef un6_lds_000)) )) (net DS_030_i (joined - (portRef O (instanceRef I_242)) + (portRef O (instanceRef I_230)) (portRef I0 (instanceRef DS_030_D0_0)) (portRef I1 (instanceRef un6_lds_000_1)) )) - (net UDS_000_INT_i (joined - (portRef O (instanceRef UDS_000_INT_i)) - (portRef I0 (instanceRef un6_uds_000)) - )) (net N_224_i (joined (portRef O (instanceRef N_224_i)) (portRef I1 (instanceRef G_168_1)) @@ -2710,30 +2669,14 @@ (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i)) - (portRef D (instanceRef BGACK_030_INT_D)) - )) - (net N_89_i (joined - (portRef O (instanceRef N_89_i)) - (portRef D (instanceRef AS_030_D0)) - )) - (net N_91_i (joined - (portRef O (instanceRef N_91_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - )) (net N_90_i (joined (portRef O (instanceRef N_90_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef D (instanceRef AS_030_D0)) )) - (net un14_amiga_bus_data_dir_i (joined - (portRef O (instanceRef un14_amiga_bus_data_dir_i)) - (portRef I0 (instanceRef RW_000_DMA_0_m)) - )) - (net N_80_i (joined - (portRef O (instanceRef N_80_i)) - (portRef I0 (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i)) + (net DS_000_ENABLE_1_sqmuxa_i (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef un1_SM_AMIGA_7)) )) (net un6_lds_000_i (joined (portRef O (instanceRef un6_lds_000_i)) @@ -2747,29 +2690,29 @@ (portRef O (instanceRef un6_ds_030_i)) (portRef I0 (instanceRef DS_030)) )) + (net DS_000_DMA_i (joined + (portRef O (instanceRef DS_000_DMA_i)) + (portRef I1 (instanceRef un6_ds_030)) + )) (net un4_as_000_i (joined (portRef O (instanceRef un4_as_000_i)) (portRef I0 (instanceRef AS_000)) )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef un4_as_000)) + (net un8_ciin_i (joined + (portRef O (instanceRef un8_ciin_i)) + (portRef OE (instanceRef CIIN)) )) (net un6_as_030_i (joined (portRef O (instanceRef un6_as_030_i)) (portRef I0 (instanceRef AS_030)) )) - (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) - (portRef I0 (instanceRef un1_amiga_bus_enable_low)) - )) (net DS_030_D0_i (joined (portRef O (instanceRef DS_030_D0_i)) (portRef I0 (instanceRef pos_clk_un3_ds_030_d0)) )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef I_239)) + (portRef I0 (instanceRef I_224)) )) (net AS_030 (joined (portRef AS_030) @@ -2777,7 +2720,8 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef I_234)) + (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_o2)) + (portRef I0 (instanceRef I_225)) )) (net AS_000 (joined (portRef AS_000) @@ -2785,9 +2729,8 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_236)) - (portRef I0 (instanceRef DS_000_DMA_0_sqmuxa)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) + (portRef I0 (instanceRef I_227)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_2)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -2795,7 +2738,7 @@ )) (net DS_030_c (joined (portRef O (instanceRef DS_030)) - (portRef I0 (instanceRef I_242)) + (portRef I0 (instanceRef I_230)) )) (net DS_030 (joined (portRef DS_030) @@ -2803,9 +2746,9 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_a2)) (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I1 (instanceRef pos_clk_un22_bgack_030_int)) - (portRef I0 (instanceRef I_237)) + (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined (portRef IO (instanceRef UDS_000)) @@ -2813,8 +2756,8 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef pos_clk_un22_bgack_030_int)) - (portRef I0 (instanceRef I_238)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_a2)) + (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined (portRef IO (instanceRef LDS_000)) @@ -2968,6 +2911,7 @@ )) (net (rename A_c_20 "A_c[20]") (joined (portRef O (instanceRef A_20)) + (portRef I1 (instanceRef un5_ciin_1)) )) (net (rename A_20 "A[20]") (joined (portRef (member a 11)) @@ -2975,6 +2919,7 @@ )) (net (rename A_c_21 "A_c[21]") (joined (portRef O (instanceRef A_21)) + (portRef I0 (instanceRef un5_ciin_2)) )) (net (rename A_21 "A[21]") (joined (portRef (member a 10)) @@ -2982,6 +2927,7 @@ )) (net (rename A_c_22 "A_c[22]") (joined (portRef O (instanceRef A_22)) + (portRef I1 (instanceRef un5_ciin_2)) )) (net (rename A_22 "A[22]") (joined (portRef (member a 9)) @@ -2989,6 +2935,7 @@ )) (net (rename A_c_23 "A_c[23]") (joined (portRef O (instanceRef A_23)) + (portRef I0 (instanceRef un5_ciin_3)) )) (net (rename A_23 "A[23]") (joined (portRef (member a 8)) @@ -3087,8 +3034,8 @@ (net BERR_c (joined (portRef O (instanceRef BERR)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_0)) - (portRef I1 (instanceRef pos_clk_un3_as_030_d0_0_o2)) - (portRef I0 (instanceRef I_235)) + (portRef I0 (instanceRef I_226)) + (portRef I1 (instanceRef pos_clk_un3_as_030_d0_i_a2)) )) (net BERR (joined (portRef BERR) @@ -3118,9 +3065,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0)) (portRef I1 (instanceRef un22_berr_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_a2)) - (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef BGACK_030_INT_0_m)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -3234,9 +3181,9 @@ )) (net CLK_EXP_c (joined (portRef O (instanceRef CLK_030)) - (portRef I1 (instanceRef pos_clk_un40_bgack_030_int_1)) (portRef I0 (instanceRef pos_clk_un11_clk_000_n_sync)) - (portRef I0 (instanceRef CLK_EXP_i)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I0 (instanceRef CLK_EXP_c_i)) (portRef I0 (instanceRef CLK_EXP)) )) (net CLK_EXP (joined @@ -3347,21 +3294,13 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) - (portRef I0 (instanceRef VPA_D_0)) - (portRef I0 (instanceRef nEXP_SPACE_D0_0)) - (portRef I1 (instanceRef DS_030_D0_0)) - (portRef I1 (instanceRef A0_DMA_1)) (portRef I1 (instanceRef DSACK1_INT_1)) (portRef I1 (instanceRef AS_000_INT_1)) - (portRef I1 (instanceRef AS_030_000_SYNC_1)) (portRef I1 (instanceRef LDS_000_INT_1)) (portRef I1 (instanceRef RW_000_INT_2)) - (portRef I1 (instanceRef RW_000_DMA_2)) (portRef I1 (instanceRef UDS_000_INT_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I1 (instanceRef VMA_INT_1)) (portRef I1 (instanceRef BG_000_1)) - (portRef I1 (instanceRef DS_000_ENABLE_1)) (portRef I1 (instanceRef IPL_030_1_2)) (portRef I1 (instanceRef IPL_030_1_1)) (portRef I1 (instanceRef IPL_030_1_0)) @@ -3369,33 +3308,40 @@ (portRef I1 (instanceRef IPL_D0_0_1)) (portRef I1 (instanceRef IPL_D0_0_0)) (portRef I1 (instanceRef DTACK_D0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o6_0_o2_0)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I1 (instanceRef AS_030_D0_0_i_a2)) + (portRef I0 (instanceRef VPA_D_0)) + (portRef I0 (instanceRef nEXP_SPACE_D0_0)) + (portRef I1 (instanceRef DS_030_D0_0)) + (portRef I1 (instanceRef DS_000_DMA_1)) + (portRef I1 (instanceRef AS_000_DMA_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_o6_0)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_6)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_7)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_1)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_2)) (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_3)) (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_4)) (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_5)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_6)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_7)) - (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_0_0)) - (portRef I1 (instanceRef RESET_OUT_2)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_1)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_2)) + (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) + (portRef I1 (instanceRef RESET_OUT_2_i)) + (portRef I1 (instanceRef AS_030_D0_0_i_a2)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I1 (instanceRef RW_000_DMA_2)) (portRef I1 (instanceRef BGACK_030_INT_1)) - (portRef I1 (instanceRef VMA_INT_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_0_a2)) - (portRef I1 (instanceRef un1_rst_2)) - (portRef I1 (instanceRef CLK_030_H_2)) - (portRef I1 (instanceRef AS_000_DMA_1)) - (portRef I1 (instanceRef DS_000_DMA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_6)) + (portRef I1 (instanceRef AS_030_000_SYNC_1)) + (portRef I1 (instanceRef A0_DMA_1)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_2_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_6)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_4)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_2)) + (portRef I1 (instanceRef CLK_030_H_2_i_1)) )) (net RST (joined (portRef RST) @@ -3407,7 +3353,7 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I0 (instanceRef I_240)) + (portRef I0 (instanceRef I_228)) )) (net RW (joined (portRef IO (instanceRef RW)) @@ -3434,7 +3380,7 @@ (portRef AMIGA_ADDR_ENABLE) )) (net AMIGA_BUS_DATA_DIR_c (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) (net AMIGA_BUS_DATA_DIR (joined @@ -3453,247 +3399,193 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net N_6_i (joined - (portRef O (instanceRef N_6_i)) - (portRef I0 (instanceRef AS_000_DMA_1)) + (net N_21_i (joined + (portRef O (instanceRef N_21_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) )) - (net N_48_0 (joined - (portRef O (instanceRef AS_000_DMA_1)) - (portRef I0 (instanceRef AS_000_DMA_1_i)) + (net N_34_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) )) - (net N_3_i (joined - (portRef O (instanceRef N_3_i)) - (portRef I0 (instanceRef DS_000_DMA_1)) + (net N_20_i (joined + (portRef O (instanceRef N_20_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) )) - (net N_49_0 (joined - (portRef O (instanceRef DS_000_DMA_1)) - (portRef I0 (instanceRef DS_000_DMA_1_i)) + (net N_35_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) )) - (net (rename pos_clk_un29_bgack_030_int_i "pos_clk.un29_bgack_030_int_i") (joined - (portRef O (instanceRef pos_clk_un29_bgack_030_int_i)) - (portRef I1 (instanceRef pos_clk_un27_bgack_030_int)) + (net N_16_i (joined + (portRef O (instanceRef N_16_i)) + (portRef I0 (instanceRef RW_000_DMA_2)) )) - (net (rename pos_clk_un26_bgack_030_int_i "pos_clk.un26_bgack_030_int_i") (joined - (portRef O (instanceRef pos_clk_un26_bgack_030_int_i)) - (portRef I0 (instanceRef pos_clk_un27_bgack_030_int)) + (net N_39_0 (joined + (portRef O (instanceRef RW_000_DMA_2)) + (portRef I0 (instanceRef RW_000_DMA_2_i)) )) - (net (rename pos_clk_un27_bgack_030_int_0 "pos_clk.un27_bgack_030_int_0") (joined - (portRef O (instanceRef pos_clk_un27_bgack_030_int)) - (portRef I0 (instanceRef pos_clk_un27_bgack_030_int_i)) - )) - (net CLK_030_H_0_sqmuxa_i (joined - (portRef O (instanceRef CLK_030_H_0_sqmuxa_i)) - (portRef I0 (instanceRef CLK_030_H_1)) - )) - (net N_7_i (joined - (portRef O (instanceRef N_7_i)) - (portRef I1 (instanceRef CLK_030_H_1)) - )) - (net N_47_0 (joined - (portRef O (instanceRef CLK_030_H_1)) - (portRef I0 (instanceRef CLK_030_H_1_i)) - )) - (net N_133_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_1_0)) - )) - (net N_176_i (joined - (portRef O (instanceRef N_176_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0)) - )) - (net N_175_i (joined - (portRef O (instanceRef N_175_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0)) - )) - (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_i)) - )) - (net (rename pos_clk_DS_000_DMA_4_f1_0 "pos_clk.DS_000_DMA_4_f1_0") (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f1)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f1_i)) - )) - (net N_162_i (joined - (portRef O (instanceRef N_162_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_2_0)) - )) - (net N_163_i (joined - (portRef O (instanceRef N_163_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_1_0)) - )) - (net N_164_i (joined - (portRef O (instanceRef N_164_i)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_2_0)) - )) - (net N_165_i (joined - (portRef O (instanceRef N_165_i)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0)) - )) - (net N_131_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0)) - (portRef D (instanceRef SM_AMIGA_i_7)) - )) - (net (rename pos_clk_un22_bgack_030_int_0 "pos_clk.un22_bgack_030_int_0") (joined - (portRef O (instanceRef pos_clk_un22_bgack_030_int)) - (portRef I0 (instanceRef pos_clk_un22_bgack_030_int_i)) - )) - (net (rename pos_clk_un9_clk_000_n_sync_i "pos_clk.un9_clk_000_n_sync_i") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_n_sync_i)) - (portRef I1 (instanceRef pos_clk_un14_clk_000_n_sync)) - )) - (net (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (joined - (portRef O (instanceRef CLK_000_N_SYNC_i_10)) - (portRef I0 (instanceRef pos_clk_un14_clk_000_n_sync)) - )) - (net (rename pos_clk_un14_clk_000_n_sync_0 "pos_clk.un14_clk_000_n_sync_0") (joined - (portRef O (instanceRef pos_clk_un14_clk_000_n_sync)) - (portRef I0 (instanceRef pos_clk_un14_clk_000_n_sync_i)) - )) - (net N_22_i (joined - (portRef O (instanceRef N_22_i)) + (net N_13_i (joined + (portRef O (instanceRef N_13_i)) (portRef I0 (instanceRef BGACK_030_INT_1)) )) - (net N_33_0 (joined + (net N_42_0 (joined (portRef O (instanceRef BGACK_030_INT_1)) (portRef I0 (instanceRef BGACK_030_INT_1_i)) )) - (net N_18_i (joined - (portRef O (instanceRef N_18_i)) - (portRef I0 (instanceRef VMA_INT_1)) + (net N_12_i (joined + (portRef O (instanceRef N_12_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1)) )) - (net N_37_0 (joined - (portRef O (instanceRef VMA_INT_1)) - (portRef I0 (instanceRef VMA_INT_1_i)) + (net N_43_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) )) - (net (rename pos_clk_un9_clk_000_ne_i "pos_clk.un9_clk_000_ne_i") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_ne_i)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe)) + (net N_8_i (joined + (portRef O (instanceRef N_8_i)) + (portRef I0 (instanceRef A0_DMA_1)) )) - (net (rename pos_clk_un5_clk_000_pe_i "pos_clk.un5_clk_000_pe_i") (joined - (portRef O (instanceRef pos_clk_un5_clk_000_pe_i)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe)) + (net N_46_0 (joined + (portRef O (instanceRef A0_DMA_1)) + (portRef I0 (instanceRef A0_DMA_1_i)) )) - (net (rename pos_clk_un7_clk_000_pe_0 "pos_clk.un7_clk_000_pe_0") (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_i)) + (net N_76_i (joined + (portRef O (instanceRef pos_clk_un4_bgack_000_i_o2)) + (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_o2_i)) )) - (net (rename pos_clk_un27_clk_000_ne_d0_i "pos_clk.un27_clk_000_ne_d0_i") (joined - (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_i)) - (portRef I1 (instanceRef pos_clk_un23_clk_000_ne_d0)) + (net N_72_0 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o2)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2_i)) )) - (net (rename pos_clk_un21_clk_000_ne_d0_i "pos_clk.un21_clk_000_ne_d0_i") (joined - (portRef O (instanceRef pos_clk_un21_clk_000_ne_d0_i)) - (portRef I0 (instanceRef pos_clk_un23_clk_000_ne_d0)) + (net UDS_000_c_i (joined + (portRef O (instanceRef UDS_000_c_i)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) )) - (net (rename pos_clk_un23_clk_000_ne_d0_0 "pos_clk.un23_clk_000_ne_d0_0") (joined - (portRef O (instanceRef pos_clk_un23_clk_000_ne_d0)) - (portRef I0 (instanceRef pos_clk_un23_clk_000_ne_d0_i)) + (net LDS_000_c_i (joined + (portRef O (instanceRef LDS_000_c_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) )) - (net N_136_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_3)) + (net N_256_i (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) )) - (net N_140_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_2)) + (net (rename pos_clk_un5_bgack_030_int_d_i "pos_clk.un5_bgack_030_int_d_i") (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o2)) )) - (net N_195_i (joined - (portRef O (instanceRef N_195_i)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_i_2)) + (net (rename pos_clk_un24_bgack_030_int_i_0_0 "pos_clk.un24_bgack_030_int_i_0_0") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_i)) + (portRef I1 (instanceRef CLK_030_H_2_i)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i)) )) - (net N_196_i (joined - (portRef O (instanceRef N_196_i)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_i_2)) - )) - (net N_186_i (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) - )) - (net N_188_i (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_o4_2)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_i_o4_i_2)) - )) - (net N_189_i (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_1)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_i_1)) - )) - (net N_190_i (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_3)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_0_3)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_i_3)) - )) - (net N_193_i (joined - (portRef O (instanceRef N_193_i)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_2_1)) - )) - (net N_191_i (joined - (portRef O (instanceRef N_191_i)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_2_1)) - )) - (net N_192_i (joined - (portRef O (instanceRef N_192_i)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_1_1)) - )) - (net N_194_i (joined - (portRef O (instanceRef N_194_i)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_1_1)) - )) - (net (rename pos_clk_cpu_est_11_0_1 "pos_clk.cpu_est_11_0[1]") (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_1)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_i_1)) - )) - (net N_198_i (joined - (portRef O (instanceRef N_198_i)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_3)) - )) - (net N_197_i (joined - (portRef O (instanceRef N_197_i)) - (portRef I1 (instanceRef pos_clk_cpu_est_11_0_1_3)) - )) - (net N_199_i (joined - (portRef O (instanceRef N_199_i)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_1_3)) - )) - (net (rename pos_clk_cpu_est_11_0_3 "pos_clk.cpu_est_11_0[3]") (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_3)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_i_3)) - )) - (net N_151_i (joined - (portRef O (instanceRef N_151_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_2)) - )) - (net N_150_i (joined - (portRef O (instanceRef N_150_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_2)) - )) - (net N_121_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_2)) - (portRef D (instanceRef SM_AMIGA_2)) - )) - (net N_135_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0_i_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_1_0)) + (net N_104_i (joined + (portRef O (instanceRef N_104_i)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_2)) )) (net N_252_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_i_1)) + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i)) )) - (net N_85_i (joined - (portRef O (instanceRef N_85_i)) - (portRef I0 (instanceRef pos_clk_RST_DLY_5_iv_0_0)) + (net N_251_0 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_i)) + )) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_i)) + )) + (net N_97_i (joined + (portRef O (instanceRef N_97_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i)) + )) + (net N_96_i (joined + (portRef O (instanceRef N_96_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i)) + )) + (net N_250_0 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i)) + )) + (net N_89_i (joined + (portRef O (instanceRef N_89_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + )) + (net N_88_i (joined + (portRef O (instanceRef N_88_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + )) + (net N_138_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_5)) + )) + (net (rename un1_RST_DLY_i_m_i_1 "un1_RST_DLY_i_m_i[1]") (joined + (portRef O (instanceRef un1_RST_DLY_i_m_i_1)) + (portRef I1 (instanceRef pos_clk_RST_DLY_5_iv_0)) )) (net (rename pos_clk_RST_DLY_5_iv_i_0 "pos_clk.RST_DLY_5_iv_i[0]") (joined - (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0_0)) + (portRef O (instanceRef pos_clk_RST_DLY_5_iv_0)) (portRef D (instanceRef RST_DLY_0)) )) - (net N_38_0 (joined - (portRef O (instanceRef RESET_OUT_1)) - (portRef I0 (instanceRef RESET_OUT_1_i)) + (net N_157_i (joined + (portRef O (instanceRef N_157_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_5)) + )) + (net N_158_i (joined + (portRef O (instanceRef N_158_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_5)) + )) + (net N_159_i (joined + (portRef O (instanceRef N_159_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_2_5)) + )) + (net N_127_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_5)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_257_0 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_o2_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + )) + (net un1_as_000_i (joined + (portRef O (instanceRef un1_as_000_0)) + (portRef OE (instanceRef AS_000)) + (portRef OE (instanceRef LDS_000)) + (portRef OE (instanceRef RW_000)) + (portRef OE (instanceRef UDS_000)) + )) + (net N_93_i (joined + (portRef O (instanceRef N_93_i)) + (portRef I0 (instanceRef RESET_OUT_2_i)) + )) + (net N_246_i (joined + (portRef O (instanceRef RESET_OUT_2_i)) + (portRef D (instanceRef RESET_OUT)) + )) + (net N_87_i (joined + (portRef O (instanceRef N_87_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) + )) + (net N_86_i (joined + (portRef O (instanceRef N_86_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) )) (net (rename un1_RST_DLY_i_m_i_2 "un1_RST_DLY_i_m_i[2]") (joined (portRef O (instanceRef un1_RST_DLY_i_m_i_2)) @@ -3757,118 +3649,76 @@ (portRef OE (instanceRef AS_030)) (portRef OE (instanceRef DS_030)) )) - (net N_76_i (joined - (portRef O (instanceRef N_76_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (net un1_as_030_i (joined + (portRef O (instanceRef un1_as_030)) + (portRef I1 (instanceRef un3_as_030)) + (portRef OE (instanceRef SIZE_0)) + (portRef OE (instanceRef SIZE_1)) + )) + (net (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (joined + (portRef O (instanceRef CLK_000_N_SYNC_i_10)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_n_sync)) + )) + (net (rename pos_clk_un9_clk_000_n_sync_i "pos_clk.un9_clk_000_n_sync_i") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_n_sync_i)) + (portRef I1 (instanceRef pos_clk_un14_clk_000_n_sync)) + )) + (net (rename pos_clk_un14_clk_000_n_sync_0 "pos_clk.un14_clk_000_n_sync_0") (joined + (portRef O (instanceRef pos_clk_un14_clk_000_n_sync)) + (portRef I0 (instanceRef pos_clk_un14_clk_000_n_sync_i)) + )) + (net CLK_EXP_c_i (joined + (portRef O (instanceRef CLK_EXP_c_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i)) + )) + (net N_244_0 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i)) )) (net N_83_i (joined (portRef O (instanceRef N_83_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) - )) - (net N_119_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net N_84_i (joined - (portRef O (instanceRef N_84_i)) (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_1)) )) (net N_115_0 (joined (portRef O (instanceRef un1_SM_AMIGA_5_i_0)) (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0_i)) )) - (net N_86_i (joined - (portRef O (instanceRef N_86_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (net N_84_i (joined + (portRef O (instanceRef N_84_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) )) - (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + (net N_245_0 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_i)) )) - (net N_87_i (joined - (portRef O (instanceRef N_87_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (net N_85_i (joined + (portRef O (instanceRef N_85_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) )) - (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) - )) - (net N_88_i (joined - (portRef O (instanceRef N_88_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0)) - )) - (net N_117_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0)) - (portRef D (instanceRef SM_AMIGA_0)) - )) - (net N_241_0 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_i)) - )) - (net N_242_0 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_i)) - )) - (net N_243_0 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_i)) - )) - (net N_93_i (joined - (portRef O (instanceRef N_93_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i)) + (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) )) (net N_94_i (joined (portRef O (instanceRef N_94_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_1)) )) - (net N_244_0 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i)) + (net N_247_i (joined + (portRef O (instanceRef CLK_030_H_2_i)) + (portRef D (instanceRef CLK_030_H)) )) - (net N_245_0 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) - )) - (net N_246_0 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i)) - )) - (net (rename pos_clk_un3_as_030_d0_i "pos_clk.un3_as_030_d0_i") (joined - (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_0)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i)) - (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_i)) - )) - (net (rename pos_clk_un5_bgack_030_int_d_i "pos_clk.un5_bgack_030_int_d_i") (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o4_1)) + (net N_248_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + (portRef D (instanceRef CYCLE_DMA_1)) )) (net N_249_i (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o4_i_0)) + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + (portRef D (instanceRef CYCLE_DMA_0)) )) - (net N_251_0 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o4)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o4_i)) - )) - (net N_71_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o4_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o4_i_0)) - )) - (net N_104_i (joined - (portRef O (instanceRef N_104_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o6_0_o2_0)) - )) - (net N_137_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o6_0_o2_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_1_0)) + (net N_73_0 (joined + (portRef O (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2_i)) )) (net N_129_i (joined (portRef O (instanceRef SM_AMIGA_srsts_i_6)) @@ -3882,22 +3732,6 @@ (portRef O (instanceRef N_161_i)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_6)) )) - (net N_127_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_5)) - (portRef D (instanceRef SM_AMIGA_5)) - )) - (net N_159_i (joined - (portRef O (instanceRef N_159_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_2_5)) - )) - (net N_157_i (joined - (portRef O (instanceRef N_157_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_5)) - )) - (net N_158_i (joined - (portRef O (instanceRef N_158_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_5)) - )) (net N_125_i (joined (portRef O (instanceRef SM_AMIGA_srsts_i_4)) (portRef D (instanceRef SM_AMIGA_4)) @@ -3926,6 +3760,126 @@ (portRef O (instanceRef N_153_i)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_3)) )) + (net N_121_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_2)) + (portRef D (instanceRef SM_AMIGA_2)) + )) + (net N_150_i (joined + (portRef O (instanceRef N_150_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_2)) + )) + (net N_151_i (joined + (portRef O (instanceRef N_151_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_2)) + )) + (net N_119_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_149_i (joined + (portRef O (instanceRef N_149_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_2_1)) + )) + (net N_147_i (joined + (portRef O (instanceRef N_147_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_1)) + )) + (net N_148_i (joined + (portRef O (instanceRef N_148_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_1)) + )) + (net N_131_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0)) + (portRef D (instanceRef SM_AMIGA_i_7)) + )) + (net N_164_i (joined + (portRef O (instanceRef N_164_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_2_0)) + )) + (net N_165_i (joined + (portRef O (instanceRef N_165_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0)) + )) + (net N_163_i (joined + (portRef O (instanceRef N_163_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_2_0)) + )) + (net N_199_i (joined + (portRef O (instanceRef N_199_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_1_3)) + )) + (net (rename pos_clk_cpu_est_11_0_3 "pos_clk.cpu_est_11_0[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_i_3)) + )) + (net N_197_i (joined + (portRef O (instanceRef N_197_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_1_3)) + )) + (net N_198_i (joined + (portRef O (instanceRef N_198_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_3)) + )) + (net N_194_i (joined + (portRef O (instanceRef N_194_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_2_1)) + )) + (net (rename pos_clk_cpu_est_11_0_1 "pos_clk.cpu_est_11_0[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_i_1)) + )) + (net N_192_i (joined + (portRef O (instanceRef N_192_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_1_1)) + )) + (net N_135_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0_i_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_1_0)) + )) + (net N_162_i (joined + (portRef O (instanceRef N_162_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_1_0)) + )) + (net N_191_i (joined + (portRef O (instanceRef N_191_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_1_1)) + )) + (net N_193_i (joined + (portRef O (instanceRef N_193_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_2_1)) + )) + (net N_190_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_i_3)) + )) + (net N_189_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_o4_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_1_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_o4_i_1)) + )) + (net N_188_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_o4_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_o4_i_2)) + )) + (net N_195_i (joined + (portRef O (instanceRef N_195_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_2)) + )) + (net N_196_i (joined + (portRef O (instanceRef N_196_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_2)) + )) + (net N_186_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + )) + (net N_143_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_0)) + )) (net N_142_0 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_o3_6)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_6)) @@ -3934,22 +3888,80 @@ (portRef O (instanceRef SM_AMIGA_srsts_i_o3_4)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_4)) )) - (net N_138_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_5)) + (net N_140_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_2)) + )) + (net N_139_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_1)) + )) + (net N_166_i (joined + (portRef O (instanceRef N_166_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o6_0)) + )) + (net N_137_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o6_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_1_0)) + )) + (net N_136_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_o3_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_3)) + )) + (net N_133_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_1_0)) )) (net N_132_i (joined (portRef O (instanceRef SM_AMIGA_srsts_i_o3_0_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_6)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_4)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_6)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_0_i_0)) )) - (net un1_as_030_i (joined - (portRef O (instanceRef un1_as_030)) - (portRef I1 (instanceRef un3_as_030)) - (portRef OE (instanceRef SIZE_0)) - (portRef OE (instanceRef SIZE_1)) + (net N_146_i (joined + (portRef O (instanceRef N_146_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0)) + )) + (net N_117_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_144_i (joined + (portRef O (instanceRef N_144_i)) + (portRef I1 (instanceRef un1_SM_AMIGA_7)) + )) + (net un1_SM_AMIGA_7_i (joined + (portRef O (instanceRef un1_SM_AMIGA_7)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) + (portRef I0 (instanceRef un1_SM_AMIGA_7_i_0)) + )) + (net (rename pos_clk_un21_clk_000_ne_d0_i "pos_clk.un21_clk_000_ne_d0_i") (joined + (portRef O (instanceRef pos_clk_un21_clk_000_ne_d0_i)) + (portRef I0 (instanceRef pos_clk_un23_clk_000_ne_d0)) + )) + (net (rename pos_clk_un27_clk_000_ne_d0_i "pos_clk.un27_clk_000_ne_d0_i") (joined + (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_i)) + (portRef I1 (instanceRef pos_clk_un23_clk_000_ne_d0)) + )) + (net (rename pos_clk_un23_clk_000_ne_d0_0 "pos_clk.un23_clk_000_ne_d0_0") (joined + (portRef O (instanceRef pos_clk_un23_clk_000_ne_d0)) + (portRef I0 (instanceRef pos_clk_un23_clk_000_ne_d0_i)) + )) + (net (rename pos_clk_un5_clk_000_pe_i "pos_clk.un5_clk_000_pe_i") (joined + (portRef O (instanceRef pos_clk_un5_clk_000_pe_i)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe)) + )) + (net (rename pos_clk_un9_clk_000_ne_i "pos_clk.un9_clk_000_ne_i") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_ne_i)) + (portRef I1 (instanceRef pos_clk_un7_clk_000_pe)) + )) + (net (rename pos_clk_un7_clk_000_pe_0 "pos_clk.un7_clk_000_pe_0") (joined + (portRef O (instanceRef pos_clk_un7_clk_000_pe)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_i)) )) (net (rename pos_clk_un11_ds_030_d0_i "pos_clk.un11_ds_030_d0_i") (joined (portRef O (instanceRef pos_clk_un11_ds_030_d0)) @@ -4039,13 +4051,21 @@ (portRef O (instanceRef DS_030_D0_0)) (portRef I0 (instanceRef DS_030_D0_0_i)) )) - (net N_8_i (joined - (portRef O (instanceRef N_8_i)) - (portRef I0 (instanceRef A0_DMA_1)) + (net N_3_i (joined + (portRef O (instanceRef N_3_i)) + (portRef I0 (instanceRef DS_000_DMA_1)) )) - (net N_46_0 (joined - (portRef O (instanceRef A0_DMA_1)) - (portRef I0 (instanceRef A0_DMA_1_i)) + (net N_49_0 (joined + (portRef O (instanceRef DS_000_DMA_1)) + (portRef I0 (instanceRef DS_000_DMA_1_i)) + )) + (net N_6_i (joined + (portRef O (instanceRef N_6_i)) + (portRef I0 (instanceRef AS_000_DMA_1)) + )) + (net N_48_0 (joined + (portRef O (instanceRef AS_000_DMA_1)) + (portRef I0 (instanceRef AS_000_DMA_1_i)) )) (net N_9_i (joined (portRef O (instanceRef N_9_i)) @@ -4063,67 +4083,43 @@ (portRef O (instanceRef AS_000_INT_1)) (portRef I0 (instanceRef AS_000_INT_1_i)) )) - (net N_12_i (joined - (portRef O (instanceRef N_12_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_1)) - )) - (net N_43_0 (joined - (portRef O (instanceRef AS_030_000_SYNC_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) - )) - (net N_13_i (joined - (portRef O (instanceRef N_13_i)) + (net N_14_i (joined + (portRef O (instanceRef N_14_i)) (portRef I0 (instanceRef LDS_000_INT_1)) )) - (net N_42_0 (joined + (net N_41_0 (joined (portRef O (instanceRef LDS_000_INT_1)) (portRef I0 (instanceRef LDS_000_INT_1_i)) )) - (net N_14_i (joined - (portRef O (instanceRef N_14_i)) + (net N_15_i (joined + (portRef O (instanceRef N_15_i)) (portRef I0 (instanceRef RW_000_INT_2)) )) - (net N_41_0 (joined + (net N_40_0 (joined (portRef O (instanceRef RW_000_INT_2)) (portRef I0 (instanceRef RW_000_INT_2_i)) )) - (net N_15_i (joined - (portRef O (instanceRef N_15_i)) - (portRef I0 (instanceRef RW_000_DMA_2)) - )) - (net N_40_0 (joined - (portRef O (instanceRef RW_000_DMA_2)) - (portRef I0 (instanceRef RW_000_DMA_2_i)) - )) - (net N_16_i (joined - (portRef O (instanceRef N_16_i)) + (net N_17_i (joined + (portRef O (instanceRef N_17_i)) (portRef I0 (instanceRef UDS_000_INT_1)) )) - (net N_39_0 (joined + (net N_38_0 (joined (portRef O (instanceRef UDS_000_INT_1)) (portRef I0 (instanceRef UDS_000_INT_1_i)) )) (net N_19_i (joined (portRef O (instanceRef N_19_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I0 (instanceRef VMA_INT_1)) )) (net N_36_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) + (portRef O (instanceRef VMA_INT_1)) + (portRef I0 (instanceRef VMA_INT_1_i)) )) - (net N_20_i (joined - (portRef O (instanceRef N_20_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - )) - (net N_35_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) - )) - (net N_21_i (joined - (portRef O (instanceRef N_21_i)) + (net N_22_i (joined + (portRef O (instanceRef N_22_i)) (portRef I0 (instanceRef BG_000_1)) )) - (net N_34_0 (joined + (net N_33_0 (joined (portRef O (instanceRef BG_000_1)) (portRef I0 (instanceRef BG_000_1_i)) )) @@ -4139,17 +4135,21 @@ (portRef O (instanceRef pos_clk_un8_bg_030)) (portRef I0 (instanceRef pos_clk_un8_bg_030_i)) )) - (net N_251_0_1 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o4_1)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o4)) + (net N_127_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_5)) )) - (net N_121_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_2)) + (net N_127_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_2_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_5)) )) - (net (rename pos_clk_cpu_est_11_0_1_3 "pos_clk.cpu_est_11_0_1[3]") (joined - (portRef O (instanceRef pos_clk_cpu_est_11_0_1_3)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_0_3)) + (net (rename pos_clk_un11_ds_030_d0_i_1 "pos_clk.un11_ds_030_d0_i_1") (joined + (portRef O (instanceRef pos_clk_un11_ds_030_d0_1)) + (portRef I0 (instanceRef pos_clk_un11_ds_030_d0)) + )) + (net N_135_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0_0)) )) (net (rename pos_clk_cpu_est_11_0_1_1 "pos_clk.cpu_est_11_0_1[1]") (joined (portRef O (instanceRef pos_clk_cpu_est_11_0_1_1)) @@ -4159,6 +4159,18 @@ (portRef O (instanceRef pos_clk_cpu_est_11_0_2_1)) (portRef I1 (instanceRef pos_clk_cpu_est_11_0_1)) )) + (net (rename pos_clk_cpu_est_11_0_1_3 "pos_clk.cpu_est_11_0_1[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_1_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_3)) + )) + (net N_195_1 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_1_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_2)) + )) + (net N_196_1 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_0_2)) + )) (net N_131_i_1 (joined (portRef O (instanceRef SM_AMIGA_nss_i_i_1_0)) (portRef I0 (instanceRef SM_AMIGA_nss_i_i_3_0)) @@ -4171,65 +4183,17 @@ (portRef O (instanceRef SM_AMIGA_nss_i_i_3_0)) (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0)) )) - (net (rename pos_clk_un11_ds_030_d0_i_1 "pos_clk.un11_ds_030_d0_i_1") (joined - (portRef O (instanceRef pos_clk_un11_ds_030_d0_1)) - (portRef I0 (instanceRef pos_clk_un11_ds_030_d0)) + (net N_119_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_1)) )) - (net un8_ciin_1 (joined - (portRef O (instanceRef un8_ciin_1)) - (portRef I0 (instanceRef un8_ciin_6)) + (net N_119_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_1)) )) - (net un8_ciin_2 (joined - (portRef O (instanceRef un8_ciin_2)) - (portRef I1 (instanceRef un8_ciin_6)) - )) - (net un8_ciin_3 (joined - (portRef O (instanceRef un8_ciin_3)) - (portRef I0 (instanceRef un8_ciin_7)) - )) - (net un8_ciin_4 (joined - (portRef O (instanceRef un8_ciin_4)) - (portRef I1 (instanceRef un8_ciin_7)) - )) - (net un8_ciin_5 (joined - (portRef O (instanceRef un8_ciin_5)) - (portRef I1 (instanceRef un8_ciin)) - )) - (net un8_ciin_6 (joined - (portRef O (instanceRef un8_ciin_6)) - (portRef I0 (instanceRef un8_ciin_8)) - )) - (net un8_ciin_7 (joined - (portRef O (instanceRef un8_ciin_7)) - (portRef I1 (instanceRef un8_ciin_8)) - )) - (net un8_ciin_8 (joined - (portRef O (instanceRef un8_ciin_8)) - (portRef I0 (instanceRef un8_ciin)) - )) - (net N_116_1 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) - )) - (net N_116_2 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) - )) - (net N_116_3 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) - )) - (net N_116_4 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) - )) - (net un22_berr_1_0 (joined - (portRef O (instanceRef un22_berr_0_a2_1_0)) - (portRef I0 (instanceRef un22_berr_0_a2)) - )) - (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2)) + (net N_121_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_2)) )) (net N_123_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_1_3)) @@ -4243,69 +4207,73 @@ (portRef O (instanceRef SM_AMIGA_srsts_i_1_4)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_4)) )) - (net N_127_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_5)) - )) - (net N_127_i_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_2_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_5)) - )) (net N_129_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_1_6)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_6)) )) - (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030)) + (net N_162_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_1_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_0)) )) - (net (rename pos_clk_un7_clk_000_d0_1 "pos_clk.un7_clk_000_d0_1") (joined - (portRef O (instanceRef pos_clk_un7_clk_000_d0_1)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_d0)) + (net N_163_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_0_0)) )) - (net RESET_OUT_0_sqmuxa_7_1 (joined - (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_1)) - (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7_3)) + (net N_165_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_3_0)) )) - (net RESET_OUT_0_sqmuxa_7_2 (joined - (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_2)) - (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_7_3)) + (net N_165_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_3_0)) )) - (net RESET_OUT_0_sqmuxa_7_3 (joined - (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_3)) - (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7)) + (net N_165_3 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_0)) )) - (net RESET_OUT_0_sqmuxa_5_1 (joined - (portRef O (instanceRef RESET_OUT_0_sqmuxa_5_1)) - (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_5)) + (net un5_ciin_1 (joined + (portRef O (instanceRef un5_ciin_1)) + (portRef I0 (instanceRef un5_ciin_7)) )) - (net N_135_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_o3_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_o3_0_0)) + (net un5_ciin_2 (joined + (portRef O (instanceRef un5_ciin_2)) + (portRef I1 (instanceRef un5_ciin_7)) )) - (net (rename pos_clk_un27_clk_000_ne_d0_1 "pos_clk.un27_clk_000_ne_d0_1") (joined - (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_1)) - (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_3)) + (net un5_ciin_3 (joined + (portRef O (instanceRef un5_ciin_3)) + (portRef I0 (instanceRef un5_ciin_8)) )) - (net (rename pos_clk_un27_clk_000_ne_d0_2 "pos_clk.un27_clk_000_ne_d0_2") (joined - (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_2_0)) - (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_3)) + (net un5_ciin_4 (joined + (portRef O (instanceRef un5_ciin_4)) + (portRef I1 (instanceRef un5_ciin_8)) )) - (net (rename pos_clk_un27_clk_000_ne_d0_3 "pos_clk.un27_clk_000_ne_d0_3") (joined - (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_3)) - (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0)) + (net un5_ciin_5 (joined + (portRef O (instanceRef un5_ciin_5)) + (portRef I0 (instanceRef un5_ciin_9)) )) - (net (rename pos_clk_un5_clk_000_pe_1 "pos_clk.un5_clk_000_pe_1") (joined - (portRef O (instanceRef pos_clk_un5_clk_000_pe_1)) - (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_3)) + (net un5_ciin_6 (joined + (portRef O (instanceRef un5_ciin_6)) + (portRef I1 (instanceRef un5_ciin_9)) )) - (net (rename pos_clk_un5_clk_000_pe_2 "pos_clk.un5_clk_000_pe_2") (joined - (portRef O (instanceRef pos_clk_un5_clk_000_pe_2)) - (portRef I1 (instanceRef pos_clk_un5_clk_000_pe_3)) + (net un5_ciin_7 (joined + (portRef O (instanceRef un5_ciin_7)) + (portRef I0 (instanceRef un5_ciin_10)) )) - (net (rename pos_clk_un5_clk_000_pe_3 "pos_clk.un5_clk_000_pe_3") (joined - (portRef O (instanceRef pos_clk_un5_clk_000_pe_3)) - (portRef I0 (instanceRef pos_clk_un5_clk_000_pe)) + (net un5_ciin_8 (joined + (portRef O (instanceRef un5_ciin_8)) + (portRef I1 (instanceRef un5_ciin_10)) + )) + (net un5_ciin_9 (joined + (portRef O (instanceRef un5_ciin_9)) + (portRef I0 (instanceRef un5_ciin_11)) + )) + (net un5_ciin_10 (joined + (portRef O (instanceRef un5_ciin_10)) + (portRef I0 (instanceRef un5_ciin)) + )) + (net un5_ciin_11 (joined + (portRef O (instanceRef un5_ciin_11)) + (portRef I1 (instanceRef un5_ciin)) )) (net (rename pos_clk_un9_clk_000_ne_1 "pos_clk.un9_clk_000_ne_1") (joined (portRef O (instanceRef pos_clk_un9_clk_000_ne_1)) @@ -4323,141 +4291,157 @@ (portRef O (instanceRef pos_clk_un9_clk_000_ne_4)) (portRef I0 (instanceRef pos_clk_un9_clk_000_ne)) )) - (net N_196_1 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_0_1_2)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_0_2)) + (net (rename pos_clk_un5_clk_000_pe_1 "pos_clk.un5_clk_000_pe_1") (joined + (portRef O (instanceRef pos_clk_un5_clk_000_pe_1)) + (portRef I0 (instanceRef pos_clk_un5_clk_000_pe_3)) )) - (net N_195_1 (joined - (portRef O (instanceRef pos_clk_cpu_est_11_i_a4_1_2)) - (portRef I0 (instanceRef pos_clk_cpu_est_11_i_a4_2)) + (net (rename pos_clk_un5_clk_000_pe_2 "pos_clk.un5_clk_000_pe_2") (joined + (portRef O (instanceRef pos_clk_un5_clk_000_pe_2)) + (portRef I1 (instanceRef pos_clk_un5_clk_000_pe_3)) )) - (net (rename pos_clk_un24_bgack_030_int_1 "pos_clk.un24_bgack_030_int_1") (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_1)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int)) + (net (rename pos_clk_un5_clk_000_pe_3 "pos_clk.un5_clk_000_pe_3") (joined + (portRef O (instanceRef pos_clk_un5_clk_000_pe_3)) + (portRef I0 (instanceRef pos_clk_un5_clk_000_pe)) )) - (net N_165_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_3_0)) + (net (rename pos_clk_un27_clk_000_ne_d0_1 "pos_clk.un27_clk_000_ne_d0_1") (joined + (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_1)) + (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0_3)) )) - (net N_165_2 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_a6_2_3_0)) + (net (rename pos_clk_un27_clk_000_ne_d0_2 "pos_clk.un27_clk_000_ne_d0_2") (joined + (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_2_0)) + (portRef I1 (instanceRef pos_clk_un27_clk_000_ne_d0_3)) )) - (net N_165_3 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_2_3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_2_0)) + (net (rename pos_clk_un27_clk_000_ne_d0_3 "pos_clk.un27_clk_000_ne_d0_3") (joined + (portRef O (instanceRef pos_clk_un27_clk_000_ne_d0_3)) + (portRef I0 (instanceRef pos_clk_un27_clk_000_ne_d0)) )) - (net N_163_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_0_0)) + (net RESET_OUT_0_sqmuxa_7_1 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_1)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7_3)) )) - (net N_162_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_a6_1_0_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_a6_0)) + (net RESET_OUT_0_sqmuxa_7_2 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_2)) + (portRef I1 (instanceRef RESET_OUT_0_sqmuxa_7_3)) )) - (net N_176_1_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) + (net RESET_OUT_0_sqmuxa_7_3 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_7_3)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_7)) )) - (net DS_000_DMA_2_sqmuxa_1 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa)) + (net RESET_OUT_0_sqmuxa_5_1 (joined + (portRef O (instanceRef RESET_OUT_0_sqmuxa_5_1)) + (portRef I0 (instanceRef RESET_OUT_0_sqmuxa_5)) )) - (net N_119_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) + (net N_87_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + )) + (net N_87_2 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) + )) + (net (rename pos_clk_un24_bgack_030_int_i_0_0_1 "pos_clk.un24_bgack_030_int_i_0_0_1") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2)) + )) + (net (rename pos_clk_un24_bgack_030_int_i_0_0_2 "pos_clk.un24_bgack_030_int_i_0_0_2") (joined + (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_o2_2)) + (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_o2)) + )) + (net N_72_0_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2)) + )) + (net (rename pos_clk_un7_clk_000_d0_1 "pos_clk.un7_clk_000_d0_1") (joined + (portRef O (instanceRef pos_clk_un7_clk_000_d0_1)) + (portRef I0 (instanceRef pos_clk_un7_clk_000_d0)) + )) + (net un21_fpu_cs_1 (joined + (portRef O (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2)) + )) + (net un22_berr_1_0 (joined + (portRef O (instanceRef un22_berr_0_a2_1_0)) + (portRef I0 (instanceRef un22_berr_0_a2)) + )) + (net N_116_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + )) + (net N_116_2 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + )) + (net N_116_3 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + )) + (net N_116_4 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1)) + )) + (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined + (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2)) )) (net N_115_0_1 (joined (portRef O (instanceRef un1_SM_AMIGA_5_i_0_1)) (portRef I0 (instanceRef un1_SM_AMIGA_5_i_0)) )) + (net N_245_0_1 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i)) + )) + (net N_247_i_1 (joined + (portRef O (instanceRef CLK_030_H_2_i_1)) + (portRef I0 (instanceRef CLK_030_H_2_i)) + )) + (net N_248_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + )) + (net N_249_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + )) (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined (portRef O (instanceRef G_168_1)) (portRef I0 (instanceRef G_168)) )) - (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined - (portRef O (instanceRef AS_000_DMA_0_r)) - (portRef I1 (instanceRef AS_000_DMA_0_n)) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) )) - (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined - (portRef O (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) )) - (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined - (portRef O (instanceRef AS_000_DMA_0_n)) - (portRef I1 (instanceRef AS_000_DMA_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) )) - (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined - (portRef O (instanceRef DS_000_DMA_0_r)) - (portRef I1 (instanceRef DS_000_DMA_0_n)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) - (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined - (portRef O (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) - (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined - (portRef O (instanceRef DS_000_DMA_0_n)) - (portRef I1 (instanceRef DS_000_DMA_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un3 "SM_AMIGA_srsts_i_0_m2_1_.un3") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un1 "SM_AMIGA_srsts_i_0_m2_1_.un1") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un0 "SM_AMIGA_srsts_i_0_m2_1_.un0") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - )) - (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined - (portRef O (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_3__n)) - )) - (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined - (portRef O (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined - (portRef O (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) - )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) @@ -4471,29 +4455,53 @@ (portRef O (instanceRef BGACK_030_INT_0_n)) (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.un3") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__r)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__n)) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.un1") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__p)) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0_.un0") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__n)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m4_0__p)) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_un3 "DS_000_ENABLE_1_sqmuxa_1_i_m4.un3") (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_r)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_n)) + (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined + (portRef O (instanceRef DS_000_ENABLE_0_r)) + (portRef I1 (instanceRef DS_000_ENABLE_0_n)) )) - (net (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_un1 "DS_000_ENABLE_1_sqmuxa_1_i_m4.un1") (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_m)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_p)) + (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined + (portRef O (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_p)) )) - (net (rename DS_000_ENABLE_1_sqmuxa_1_i_m4_un0 "DS_000_ENABLE_1_sqmuxa_1_i_m4.un0") (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_n)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_i_m4_p)) + (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined + (portRef O (instanceRef DS_000_ENABLE_0_n)) + (portRef I1 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined + (portRef O (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_n)) + )) + (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined + (portRef O (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_p)) + )) + (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined + (portRef O (instanceRef A0_DMA_0_n)) + (portRef I1 (instanceRef A0_DMA_0_p)) + )) + (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + )) + (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_1__n)) + (portRef I1 (instanceRef SIZE_DMA_0_1__p)) )) (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined (portRef O (instanceRef SIZE_DMA_0_0__r)) @@ -4507,17 +4515,53 @@ (portRef O (instanceRef SIZE_DMA_0_0__n)) (portRef I1 (instanceRef SIZE_DMA_0_0__p)) )) - (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_1__r)) - (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un3") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) )) - (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un1") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) )) - (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_1__n)) - (portRef I1 (instanceRef SIZE_DMA_0_1__p)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un0") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) + )) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) + )) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined + (portRef O (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) )) (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined (portRef O (instanceRef IPL_030_0_0__r)) @@ -4579,30 +4623,6 @@ (portRef O (instanceRef AS_000_INT_0_n)) (portRef I1 (instanceRef AS_000_INT_0_p)) )) - (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined - (portRef O (instanceRef DS_000_ENABLE_0_r)) - (portRef I1 (instanceRef DS_000_ENABLE_0_n)) - )) - (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined - (portRef O (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef DS_000_ENABLE_0_p)) - )) - (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined - (portRef O (instanceRef DS_000_ENABLE_0_n)) - (portRef I1 (instanceRef DS_000_ENABLE_0_p)) - )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) - )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) - )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) - )) (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined (portRef O (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef LDS_000_INT_0_n)) @@ -4627,18 +4647,6 @@ (portRef O (instanceRef RW_000_INT_0_n)) (portRef I1 (instanceRef RW_000_INT_0_p)) )) - (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined - (portRef O (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_n)) - )) - (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined - (portRef O (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_p)) - )) - (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined - (portRef O (instanceRef RW_000_DMA_0_n)) - (portRef I1 (instanceRef RW_000_DMA_0_p)) - )) (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined (portRef O (instanceRef UDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_n)) @@ -4651,29 +4659,17 @@ (portRef O (instanceRef UDS_000_INT_0_n)) (portRef I1 (instanceRef UDS_000_INT_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) )) (net (rename BG_000_0_un3 "BG_000_0.un3") (joined (portRef O (instanceRef BG_000_0_r)) @@ -4687,17 +4683,29 @@ (portRef O (instanceRef BG_000_0_n)) (portRef I1 (instanceRef BG_000_0_p)) )) - (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined - (portRef O (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef A0_DMA_0_n)) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) )) - (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined - (portRef O (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_p)) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) )) - (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined - (portRef O (instanceRef A0_DMA_0_n)) - (portRef I1 (instanceRef A0_DMA_0_p)) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) )) ) (property orig_inst_of (string "BUS68030")) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index f475860..f5fad56 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Thu Jul 09 18:48:45 2015 +#-- Written on Thu Sep 24 16:20:44 2015 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 6e8a2ec..e73cf46 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -187,8 +187,8 @@ NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\F\8OCklM\0#\0oHE\kL\jnUd j0\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3DMCNk#b_0.Cb_l0HC3Rjj.d4j;jj -RNP3CODNbMk_C#0b04_HRlCj43j6jnjjN; +POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj +RNP3CODNbMk_C#0b04_HRlCj43j66n.jN; POR3F0M#N_M0sRCo"qAtBji_dQj_hua_)4 R"N; P#R30Dl0H0#0HRlCjj3jjjjj;P NRHFsoM_H#F0_VAR"zU1nj"dj;P @@ -202,8 +202,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#cRUj -j;N3PR#_$MD HMC8sHRq"{wwcgw-B(jAc -.cABq-g7.c-U4gc7d cA}Uc"N; +RNP3M#$_lMkOsEN#cRU( +.;N3PR#_$MD HMC8sHR7"{ U6jn-w67.4 -gc(7U-AjBq-B(nAUg dA}dd"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -340,299 +340,143 @@ MMRkdH_#x C;N3MR#CNP_0MC_NVDoR#4.;6n RoMk_Mc#CHx;M NRN3#PMC_CV0_D#No46R.no; -MMRkUH_OH +MMRk6H_OH M;N3MR#CNP_0MC_NVDoR#4.;6n -RoMkcM4_HNloLN_k8#_N_0N8;Hs -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRckM__N#j;jj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.kM4b_Vk#_O;M +RoMk_MUOMHH;M NRN3#PMC_CV0_D#No46R.no; -MMRk.L._C;ss -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRnkM__8#j;dj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRnkM_#k8_jjj;M +MMRkc#_N_jjj;M NRN3#PMC_CV0_D#No46R.no; -MMRkn8_D#j_jjN; +MMRk4v_1_Qqvt(q_;M +NRN3#PMC_CV0_D#No46R.no; +MMRk.V4_bOk_#N; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRM_..LsCs;M +NRN3#PMC_CV0_D#No46R.no; +MMRkn#_8_jjd;M +NRN3#PMC_CV0_D#No46R.no; +MMRkn8_k#j_jjN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRMDn_8j#_j +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_d +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRch_;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh6N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -c;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_6 +n;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_g RNM3P#NCC_M0D_VN4o#Rn.6;M -oRUh_;M -NRN3#PMC_CV0_D#No46R.no; -M_RhgN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4j -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_4N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4. -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_dN; +oR4h_jN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;4c RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4n +n;ohMR_;4( RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_gN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.j +n;ohMR_;.. RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_4N; +oR.h_dN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.d +n;ohMR_;.c RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_cN; +oR.h_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.6 +n;ohMR_;.n RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_nN; +oR.h_(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.( +n;ohMR_;.U RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_UN; +oR.h_gN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.g +n;ohMR_;dj RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_jN; +oRdh_4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;d4 +n;ohMR_;d. RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_.N; +oRdh_dN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;dd +n;ohMR_;dc RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_cN; +oRdh_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;d6 +n;ohMR_;dn RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_nN; +oRdh_UN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;d( +n;ohMR_;dg RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_gN; +oRch_jN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cj +n;ohMR_;c4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_4N; +oRch_.N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;c. +n;ohMR_;cd RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_dN; +oRch_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cc +n;ohMR_;c6 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_6N; +oRch_nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cn +n;ohMR_;cU RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_UN; +oRch_gN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cg +n;ohMR_;6j RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_jN; +oR6h_.N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;6. +n;ohMR_;6d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_dN; +oR6h_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;6c +n;ohMR_;66 RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_6N; +oR6h_nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;6n +n;ohMR_;6( RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_(N; 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@ diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 0d5da8e..9ec312d 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -1,12 +1,12 @@ #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 #install: C:\ispLever\synpbase -#OS: Windows 7 6.1 +#OS: Windows 7 6.2 #Hostname: DEEPTHOUGHT #Implementation: logic $ Start of Compile -#Thu Jul 09 18:48:52 2015 +#Thu Sep 24 16:20:52 2015 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -42,14 +42,13 @@ State machine has 8 reachable states with original encodings of: 110 111 @N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est -@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jul 09 18:48:52 2015 +# Thu Sep 24 16:20:52 2015 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -59,7 +58,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jul 09 18:48:53 2015 +# Thu Sep 24 16:20:53 2015 ###########################################################] Map & Optimize Report @@ -68,7 +67,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) +@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:16:498:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -90,10 +89,10 @@ BI_DIR 11 uses IBUF 46 uses OBUF 15 uses BUFTH 3 uses -AND2 304 uses -INV 263 uses -OR2 27 uses -XOR2 14 uses +AND2 308 uses +INV 261 uses +OR2 25 uses +XOR2 15 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -103,6 +102,6 @@ Mapper successful! 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zOv0M_2}Rm;*{a7De{9P0R5`0&oF|-GXz57s-WKx)o4L31d)|LNbq%q`PTBcYe2BZY z!c1@4wZ8vRm(%`W-C8WBvscp3c3jfAXUrc)%zYqk>)pF|BDR?L|Bk|M@=nno!QWi{ z=HmG~LUI~S-^brPeV<^4oQ_*u`>o!Wv@YK#=^D`LPuD|Uzxb`yFV~E$KmCu-iKs7K zS6TjdM6^%7|Bipl-#qDys6YJ;n=Ezzn|iYmU6uHh&^O)Ql+oUd$UB7%wz?lN*jGAc1d0P8(Y90T z56S3T`p#`UCM=FOTf!fi#~!X?oj*}^zCzxOKx^`MX@7rRC!c6C2nYVAV&n)JMURmq z{r4DeH}mr;dE}-3ZVW|D2yEhx9?v-{;L&87jN=S-4zqigvUnE2RZ+d+ASzo0-(FNX z2Qxd;hUdk&CfON7J)V=?uWM}GG5SNB?lCFa#H#zb1^ao^yDyQ;AU~Gv}PLu{025NyV z*eafJV3FzT@ovg?KGTa-pNnS<>(k|Vqf&lyItY*f(kp2i-mg-3-91gEy44*grMm0VD``zw!_xi0MgLyu zS^0Ov{(8#i7y0JDv*q_Y#rrtU`23pe*4lr$Rh!6I2={cO$1W;XVtr^vZlX!ZN4>(5nbOMZ^{l<}ZcWAnR zyjPk?yj5x6c#*FI<&td(q5{S_ff|R-zT#VvKEpjp=?nL}Daqv^=?lFO%Uf7apPc-z zaLEHOHonxWWV+O;NK%XuB-8DLiFa zOxQBBIST)qJZmyU2hlni(q*@jzt^ScA1lPhkvhuinDVp++@bKPHQ7=nA7mtMEVoJj z$Nvv+^={!c9y zSB8Cw^0Nksz(qybJ%C~@)!CbsJd3pj0z??<{-B_A7Puk)U(n=lF29d^mDDG2P3^Pq zQqPNpO#!x#5j59Zx+A>hJ|8aOIV=I~uN>S8?SkK1?5RkY!Bb z1?`9f*m>eGuEbMeR#?H~lw%P9F9}baMQ?mo<5$(+JN3-0>qnhDpWkVz$Hgq(Ynhd= z?zXI7Ct)pSs2r~?pOb>_Ab3OhS>IQ4S~;WCbat9o{XCLKaACJB#Rh*h20|WS{^;JW zJ7bIcIOy>A)Yr~rrPzs)eeV}zmWH)HRH%~&GX8nDHb>M!HdwX{?9UxK$o{GWiv1(uEW+?uK~LNG z`q`l7c(-LdnOsM8_hM>y8>$#4Iv!}K-Ki+sfp)99^tv`nTx5OS)w`6N?sL>_W_9UF zq3$9kvt&zFYeGKq24uS6|cnvC6nXc|L%#uLb;bY0Q6L9%l*K^dg*bqVA!r z=(b4zNs^C=7F$3tK*W|z>}DNTUqAm+$2}{rG|0W`+!cxQ*s8ltF8}tw4CLMtqm4w1 z*-(C0VfMVY>D=KRX%gpGmNB45A|3ND-=^omG#(=CDgIkwTdBnTsgoi5TSvcFQ|W+x zw{YJk&F|to*_VHU{$4)g_CkA#EW1``m-GgUCd6~fFi)ZG3+oSZp7A}b!)4~rH=*i} z;>#iEG^oc7-M8AB<&|~Ze_Q3tIDZ@WZDo%i`}Of$w7XjMHKN)wtXU(&F9VfESy*c~ zsk=M=g?1C!w??}O@~0I~c@X) new code 000 -> 00000000 @@ -90,10 +89,10 @@ BI_DIR 11 uses IBUF 46 uses OBUF 15 uses BUFTH 3 uses -AND2 304 uses -INV 263 uses -OR2 27 uses -XOR2 14 uses +AND2 308 uses +INV 261 uses +OR2 25 uses +XOR2 15 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -103,6 +102,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jul 09 18:48:54 2015 +# Thu Sep 24 16:20:54 2015 ###########################################################] diff --git a/Logic/dm/BUS68030_comp.xdm b/Logic/dm/BUS68030_comp.xdm index dcd2adc..456b443 100644 --- a/Logic/dm/BUS68030_comp.xdm +++ b/Logic/dm/BUS68030_comp.xdm @@ -26,8 +26,8 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S> SRSqS SRSqSSqSSqSSqSSqS"/ SR new code 000 -> 00000000 @@ -24,10 +24,10 @@ BI_DIR 11 uses IBUF 46 uses OBUF 15 uses BUFTH 3 uses -AND2 304 uses -INV 263 uses -OR2 27 uses -XOR2 14 uses +AND2 308 uses +INV 261 uses +OR2 25 uses +XOR2 15 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -37,6 +37,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Jul 09 18:48:54 2015 +# Thu Sep 24 16:20:54 2015 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 2ef452f..e979e5a 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 13 + 12 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1436460532 + 1443104452 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index edd0dee..e8538f3 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -9,6 +9,5 @@ @W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... @W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... @W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... -@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 606c35f..06057a0 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the 105MB -1436460534 +1443104454 diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt index 010fdf0..7041c8b 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt @@ -1,2 +1,2 @@ -@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) +@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:16:498:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) @W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE diff --git a/Logic/syntmp/BUS68030_srr.htm b/Logic/syntmp/BUS68030_srr.htm index 93d9849..6088e08 100644 --- a/Logic/syntmp/BUS68030_srr.htm +++ b/Logic/syntmp/BUS68030_srr.htm @@ -1,38 +1,38 @@ 
-
+
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: C:\ispLever\synpbase
-#OS: Windows 7 6.1
+#OS: Windows 7 6.2
 #Hostname: DEEPTHOUGHT
 
 #Implementation: logic
 
 $ Start of Compile
-#Thu Jul 09 18:48:52 2015
+#Thu Sep 24 16:20:52 2015
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
-@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
-@W:CD638 : 68030-68000-bus.vhd(126) | Signal clk_out_pre is undriven 
+@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
+@W:CD638 : 68030-68000-bus.vhd(126) | Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register AMIGA_BUS_ENABLE_INT_4  
-@W:CL169 : 68030-68000-bus.vhd(133) | Pruning register CLK_000_D4_2  
-@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register CLK_000_D3_2  
-@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_000_D2_2  
-@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_INT_2  
-@W:CL169 : 68030-68000-bus.vhd(124) | Pruning register CLK_OUT_PRE_50_D_2  
-@W:CL169 : 68030-68000-bus.vhd(155) | Pruning register CLK_030_D0_2  
-@W:CL265 : 68030-68000-bus.vhd(135) | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W:CL271 : 68030-68000-bus.vhd(134) | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@W:CL189 : 68030-68000-bus.vhd(139) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register SM_AMIGA
+@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W:CL169 : 68030-68000-bus.vhd(133) | Pruning register CLK_000_D4_2  
+@W:CL169 : 68030-68000-bus.vhd(132) | Pruning register CLK_000_D3_2  
+@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_000_D2_2  
+@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_INT_2  
+@W:CL169 : 68030-68000-bus.vhd(124) | Pruning register CLK_OUT_PRE_50_D_2  
+@W:CL169 : 68030-68000-bus.vhd(155) | Pruning register CLK_030_D0_2  
+@W:CL265 : 68030-68000-bus.vhd(135) | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W:CL271 : 68030-68000-bus.vhd(134) | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W:CL189 : 68030-68000-bus.vhd(139) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -43,25 +43,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register cpu_est
-@W:CL246 : 68030-68000-bus.vhd(23) | Input port bits 23 to 20 of a(31 downto 2) are unused 
-@W:CL246 : 68030-68000-bus.vhd(23) | Input port bits 15 to 2 of a(31 downto 2) are unused 
+@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register cpu_est
+@W:CL246 : 68030-68000-bus.vhd(23) | Input port bits 15 to 2 of a(31 downto 2) are unused 
 @END
 
 At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:52 2015
+# Thu Sep 24 16:20:52 2015
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:53 2015
+# Thu Sep 24 16:20:53 2015
 
 ###########################################################]
 Map & Optimize Report
@@ -69,8 +68,8 @@ Map & Optimize Report
 Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:MF248 :  | Running in 64-bit mode. 
-@W:MO111 : 68030-68000-bus.vhd(497) | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
+@N:MF248 :  | Running in 64-bit mode. 
+@W:MO111 : 68030-68000-bus.vhd(498) | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -81,8 +80,8 @@ original code -> new code
    101 -> 00100001
    110 -> 01000001
    111 -> 10000001
-@N:MO106 : 68030-68000-bus.vhd(190) | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
-@W:BN132 : 68030-68000-bus.vhd(134) | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
+@N:MO106 : 68030-68000-bus.vhd(190) | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
+@W:BN132 : 68030-68000-bus.vhd(134) | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
 ---------------------------------------
 Resource Usage Report
 
@@ -92,20 +91,20 @@ BI_DIR          11 uses
 IBUF            46 uses
 OBUF            15 uses
 BUFTH           3 uses
-AND2            304 uses
-INV             263 uses
-OR2             27 uses
-XOR2            14 uses
+AND2            308 uses
+INV             261 uses
+OR2             25 uses
+XOR2            15 uses
 
 
-@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Jul 09 18:48:54 2015
+# Thu Sep 24 16:20:54 2015
 
 ###########################################################]
 
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index 546cf16..3312219 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
 
  • Mapper Report  
 
    • 
-
  • Session Log (18:48 09-Jul)  
+
  • Session Log (16:20 24-Sep)  
 
      •          
         
    
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 1592d10..8d2901f 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Thu Jul 09 18:48:52 2015
+  Written on Thu Sep 24 16:20:52 2015
 
 
 --> 
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index 658e1f6..59bf772 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -33,12 +33,12 @@
   
   Compile InputComplete
  6
- 13
+ 12
 0
 -
 0m:00s
 -
-09.07.2015
      18:48:52
+24.09.2015
      16:20:52
  
 
  
@@ -49,12 +49,12 @@
 0m:00s
 0m:00s
 105MB
-09.07.2015
      18:48:54
+24.09.2015
      16:20:54
  
 
 
   Multi-srs Generator
-  Complete0m:00s09.07.2015
      18:48:53 		
+  Complete0m:00s24.09.2015
      16:20:53 		
      
   
  
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index ef67ba2..aa6837f 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -9,7 +9,7 @@
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1436460513
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1443104440
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index f27da99..95b8d80 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -9,7 +9,7 @@
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
 #CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1436460513
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1443104440
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
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diff --git a/Logic/synwork/BUS68030_comp.tlg b/Logic/synwork/BUS68030_comp.tlg
index 5f37a0f..6e1c810 100644
--- a/Logic/synwork/BUS68030_comp.tlg
+++ b/Logic/synwork/BUS68030_comp.tlg
@@ -23,5 +23,4 @@ State machine has 8 reachable states with original encodings of:
    110
    111
 @N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
-@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 23 to 20 of a(31 downto 2) are unused 
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
diff --git a/Logic/synwork/BUS68030_mult.srs b/Logic/synwork/BUS68030_mult.srs
index 844aca16f3b04ad2afb610c5a182ad8bea8f3562..6821e581beb3b63c8e71481401ffda0648d04b9a 100644
GIT binary patch
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diff --git a/Logic/synwork/BUS68030_s.srs b/Logic/synwork/BUS68030_s.srs
index 2ddc0b78b506b24cfe7a2ee3c8149cb0095238b2..652651eabd9ee681d241fb4da4ccf56ea43f0d5d 100644
GIT binary patch
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