diff --git a/Layout and PCB/68030-TK-9g.zip b/Layout and PCB/68030-TK-9g.zip deleted file mode 100644 index 4912b57..0000000 Binary files a/Layout and PCB/68030-TK-9g.zip and /dev/null differ diff --git a/Layout and PCB/68030-TK-V09g.brd b/Layout and PCB/68030-TK-V09g.brd index 332fcec..3f3c480 100644 --- a/Layout and PCB/68030-TK-V09g.brd +++ b/Layout and PCB/68030-TK-V09g.brd @@ -2568,7 +2568,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br> - + @@ -6357,11 +6357,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br> - - - - - + + + + + @@ -6614,13 +6614,13 @@ minimale Strichstärke: <b>0.2 mm</b><br><br> - + - + @@ -6704,11 +6704,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br> - - - - - + + + + + diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 7cbd345..9d5d2ee 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -105,6 +105,7 @@ signal RW_000_INT:STD_LOGIC := '1'; signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1'; signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1'; signal AS_030_D0:STD_LOGIC := '1'; +signal AS_030_D1:STD_LOGIC := '1'; signal nEXP_SPACE_D0:STD_LOGIC := '0'; signal DS_030_D0:STD_LOGIC := '1'; signal AS_030_000_SYNC:STD_LOGIC := '1'; @@ -140,6 +141,7 @@ signal CLK_030_D0: STD_LOGIC := '0'; signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000"; signal CLK_030_PE: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; signal AMIGA_DS: STD_LOGIC := '1'; +signal DTACK_DMA: STD_LOGIC := '1'; begin CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1); @@ -239,6 +241,7 @@ begin --buffering signals AS_030_D0 <= AS_030; + AS_030_D1 <= AS_030_D0; nEXP_SPACE_D0 <= nEXP_SPACE; DS_030_D0 <= DS_030; DTACK_D0 <= DTACK; @@ -285,7 +288,7 @@ begin DS_000_ENABLE <= '0'; --RW_000_INT <= '1'; elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks - AS_030_D0 = '0' AND --as set + AS_030_D1 = '0' AND --as set BGACK_030_INT='1' AND BGACK_030_INT_D='1' AND --no dma -cycle NOT (FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0') AND --FPU-Select @@ -409,7 +412,7 @@ begin AMIGA_BUS_ENABLE_DMA_HIGH <= A(1); AMIGA_BUS_ENABLE_DMA_LOW <= not A(1); - elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then + else RW_000_DMA <= '1'; SIZE_DMA <= "00"; A0_DMA <= '0'; @@ -422,7 +425,11 @@ begin if(CLK_000_NE='1' and CYCLE_DMA<"11")then CYCLE_DMA <= CYCLE_DMA+1; end if; + if(nEXP_SPACE ='0') then --presume that all expansion devices can provide a buscycle in 320ns! + DTACK_DMA <= '0'; + end if; else + DTACK_DMA <= '1'; CYCLE_DMA <= "00"; end if; @@ -437,21 +444,21 @@ begin --set AS_000 if( not(CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1')) then --sampled on rising edges, so we can set AS only if the next clock is not rising!! AS_000_DMA <= '0'; - if(RW_000='1') then + --if(RW_000='1') then DS_000_DMA <='0'; - end if; + --end if; end if; - if( CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1' and CLK_030_PE <"11" and AS_000_DMA = '0') then --sample rising edges - CLK_030_PE <= CLK_030_PE+1; - end if; + --if( CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1' and CLK_030_PE <"11" and AS_000_DMA = '0') then --sample rising edges + -- CLK_030_PE <= CLK_030_PE+1; + --end if; - if(RW_000='0' and CLK_030_PE="01" and CLK_030='1')then - DS_000_DMA <= '0'; -- write: one clock delayed! - end if; + --if(RW_000='0' and CLK_030_PE="01" and CLK_030='1')then + -- DS_000_DMA <= '0'; -- write: one clock delayed! + --end if; else - CLK_030_PE <= "00"; + --CLK_030_PE <= "00"; AS_000_DMA <= '1'; DS_000_DMA <= '1'; end if; @@ -489,22 +496,23 @@ begin --dma stuff - DTACK <= 'Z' when AS_000_DMA='1' else '0'; --DTACK will be generated by GARY! + DTACK <= 'Z';--DTACK will be generated by GARY! + --DTACK <= 'Z' when DTACK_DMA='1' else '0'; - AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else + AS_030 <= 'Z' when BGACK_030_INT ='1' else '0' when AS_000_DMA ='0' and AS_000 ='0' else '1'; - DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else + DS_030 <= 'Z' when BGACK_030_INT ='1' else '0' when DS_000_DMA ='0' and AS_000 ='0' else '1'; - A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' --tristate on CPU-Cycle + A(0) <= 'Z' when BGACK_030_INT ='1' --tristate on CPU-Cycle else A0_DMA; --drive on DMA-Cycle A(1) <= 'Z'; - AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR RESET = '0' else x"00"; - SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' else x"00"; + SIZE <= "ZZ" when BGACK_030_INT ='1' else SIZE_DMA; --rw - RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' --tristate on CPU cycle + RW <= 'Z' when BGACK_030_INT ='1' --tristate on CPU cycle else RW_000_DMA; --drive on DMA-Cycle BGACK_030 <= BGACK_030_INT; @@ -530,31 +538,32 @@ begin cpu_est = E9 or cpu_est = E10 else '0'; - VMA <= VMA_INT; + VMA <= 'Z' when BGACK_030_INT ='0' else VMA_INT; --AVEC AVEC <= '1'; --as and uds/lds - AS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else + AS_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' else '0' when AS_000_INT ='0' and AS_030 ='0' else '1'; - RW_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' --tristate on DMA-cycle + RW_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' --tristate on DMA-cycle else RW_000_INT; -- drive on CPU cycle - UDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle + UDS_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' else --tristate on DMA cycle --'1' when DS_000_ENABLE ='0' else UDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle else '1'; -- datastrobe not ready jet - LDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else --tristate on DMA cycle + LDS_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' else --tristate on DMA cycle --'1' when DS_000_ENABLE ='0' else LDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle else '1'; -- datastrobe not ready jet --dsack - DSACK1 <= 'Z' when nEXP_SPACE = '0' else --tristate on expansionboard cycle + DSACK1 <= 'Z' when nEXP_SPACE = '0' or BGACK_030_INT ='0' else --tristate on expansionboard cycle DSACK1_INT when AS_030 = '0' else -- output on amiga cycle + --'1' when AS_030 = '1' and AS_030_D0 = '0' else --pull high '1'; diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index a807e4b..b15bf23 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,6 +1,4 @@ [STRATEGY-LIST] Normal=True, 1412327082 -[TOUCHED-REPORT] -Design.tt4File=1475958360 [synthesis-type] tool=Synplify diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi index d4146cd..1d4d30c 100644 --- a/Logic/68030_TK.cmi +++ b/Logic/68030_TK.cmi @@ -1,8 +1,8 @@ [WINDOWS] -MAIN_WINDOW_POSITION=-8,-8,1928,1168 +MAIN_WINDOW_POSITION=0,0,1928,1168 LEFT_PANE_WIDTH=245 CHILD_FRAME_STATE=Maximal -CHILD_WINDOW_SIZE=1936,919 +CHILD_WINDOW_SIZE=1928,942 CHILD_WINDOW_POS=-8,-31 PV_FRAME_STATE=Normal PV_WINDOW_SIZE=473,867 @@ -10,9 +10,9 @@ PV_WINDOW_POS=0,0 [GUI SETTING] Remember_Setting=1 Open_PV_Opt=2 -Open_PV=1 +Open_PV=0 PV_IS_ACTIVE=0 -ACTIVE_SHEET=Global Constraints +ACTIVE_SHEET=Pin Attributes Show_Def_Opt=2 Show_Def_Val=1 Expand_All_Column=0 diff --git a/Logic/68030_TK.lci b/Logic/68030_TK.lci index b80db18..1912a34 100644 --- a/Logic/68030_TK.lci +++ b/Logic/68030_TK.lci @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 10/08/2016; -TIME = 22:26:00; +DATE = 02/16/2017; +TIME = 19:15:23; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -133,6 +133,7 @@ layer = OFF; [Power] Default = High; Low = H, G, F, E, D, C, B, A; +High = B; [Source Constraint Option] diff --git a/Logic/68030_TK.lct b/Logic/68030_TK.lct index b80db18..1912a34 100644 --- a/Logic/68030_TK.lct +++ b/Logic/68030_TK.lct @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 10/08/2016; -TIME = 22:26:00; +DATE = 02/16/2017; +TIME = 19:15:23; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -133,6 +133,7 @@ layer = OFF; [Power] Default = High; Low = H, G, F, E, D, C, B, A; +High = B; [Source Constraint Option] diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 0359930..eda62da 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -426941,3 +426941,6716 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 12/29/16 16:01:42 ########### + +########## Tcl recorder starts at 01/29/17 21:01:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/29/17 21:01:08 ########### + + +########## Tcl recorder starts at 01/29/17 21:01:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/29/17 21:01:09 ########### + + +########## Tcl recorder starts at 01/29/17 21:03:34 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/29/17 21:03:34 ########### + + +########## Tcl recorder starts at 01/29/17 21:03:34 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/29/17 21:03:34 ########### + + +########## Tcl recorder starts at 01/29/17 21:04:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/29/17 21:04:04 ########### + + +########## Tcl recorder starts at 01/29/17 21:04:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/29/17 21:04:04 ########### + + +########## Tcl recorder starts at 01/30/17 20:23:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:23:32 ########### + + +########## Tcl recorder starts at 01/30/17 20:23:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:23:33 ########### + + +########## Tcl recorder starts at 01/30/17 20:25:34 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:25:34 ########### + + +########## Tcl recorder starts at 01/30/17 20:25:34 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:25:34 ########### + + +########## Tcl recorder starts at 01/30/17 20:27:05 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:27:05 ########### + + +########## Tcl recorder starts at 01/30/17 20:27:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:27:05 ########### + + +########## Tcl recorder starts at 01/30/17 20:33:05 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:33:05 ########### + + +########## Tcl recorder starts at 01/30/17 20:33:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:33:05 ########### + + +########## Tcl recorder starts at 01/30/17 20:38:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:38:04 ########### + + +########## Tcl recorder starts at 01/30/17 20:38:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:38:04 ########### + + +########## Tcl recorder starts at 01/30/17 20:42:38 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:42:38 ########### + + +########## Tcl recorder starts at 01/30/17 20:42:38 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:42:38 ########### + + +########## Tcl recorder starts at 01/30/17 20:44:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:44:19 ########### + + +########## Tcl recorder starts at 01/30/17 20:44:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:44:19 ########### + + +########## Tcl recorder starts at 01/30/17 20:44:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:44:51 ########### + + +########## Tcl recorder starts at 01/30/17 20:44:51 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:44:51 ########### + + +########## Tcl recorder starts at 01/30/17 20:46:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:46:27 ########### + + +########## Tcl recorder starts at 01/30/17 20:46:28 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:46:28 ########### + + +########## Tcl recorder starts at 01/30/17 20:47:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:47:09 ########### + + +########## Tcl recorder starts at 01/30/17 20:47:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:47:09 ########### + + +########## Tcl recorder starts at 01/30/17 20:50:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:50:39 ########### + + +########## Tcl recorder starts at 01/30/17 20:50:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/30/17 20:50:40 ########### + + +########## Tcl recorder starts at 02/15/17 23:13:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/15/17 23:13:59 ########### + + +########## Tcl recorder starts at 02/15/17 23:14:00 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/15/17 23:14:00 ########### + + +########## Tcl recorder starts at 02/16/17 19:11:39 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:11:39 ########### + + +########## Tcl recorder starts at 02/16/17 19:12:43 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:12:43 ########### + + +########## Tcl recorder starts at 02/16/17 19:12:53 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:12:53 ########### + + +########## Tcl recorder starts at 02/16/17 19:13:23 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:13:23 ########### + + +########## Tcl recorder starts at 02/16/17 19:13:27 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:13:27 ########### + + +########## Tcl recorder starts at 02/16/17 19:14:30 ########## + +# Commands to make the Process: +# Optimization Constraint +# - none - +# Application to view the Process: +# Optimization Constraint +if [catch {open opt_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file opt_cmd.rs2: $rspFile" +} else { + puts $rspFile "-global -lci 68030_tk.lct -touch 68030_tk.imp +" + close $rspFile +} +if [runCmd "\"$cpld_bin/optedit\" @opt_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:14:30 ########### + + +########## Tcl recorder starts at 02/16/17 19:14:40 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:14:40 ########### + + +########## Tcl recorder starts at 02/16/17 19:15:27 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:15:27 ########### + + +########## Tcl recorder starts at 02/16/17 19:15:34 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 19:15:34 ########### + + +########## Tcl recorder starts at 02/16/17 20:07:33 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 20:07:33 ########### + + +########## Tcl recorder starts at 02/16/17 20:07:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/16/17 20:07:33 ########### + + +########## Tcl recorder starts at 02/24/17 20:04:00 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:04:00 ########### + + +########## Tcl recorder starts at 02/24/17 20:04:01 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:04:01 ########### + + +########## Tcl recorder starts at 02/24/17 20:05:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:05:52 ########### + + +########## Tcl recorder starts at 02/24/17 20:05:53 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:05:53 ########### + + +########## Tcl recorder starts at 02/24/17 20:15:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:15:44 ########### + + +########## Tcl recorder starts at 02/24/17 20:15:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:15:45 ########### + + +########## Tcl recorder starts at 02/24/17 20:26:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:26:26 ########### + + +########## Tcl recorder starts at 02/24/17 20:26:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:26:27 ########### + + +########## Tcl recorder starts at 02/24/17 20:27:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:27:04 ########### + + +########## Tcl recorder starts at 02/24/17 20:27:04 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:27:04 ########### + + +########## Tcl recorder starts at 02/24/17 20:36:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:36:36 ########### + + +########## Tcl recorder starts at 02/24/17 20:44:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:44:47 ########### + + +########## Tcl recorder starts at 02/24/17 20:44:48 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:44:48 ########### + + +########## Tcl recorder starts at 02/24/17 20:48:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:48:27 ########### + + +########## Tcl recorder starts at 02/24/17 20:48:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:48:27 ########### + + +########## Tcl recorder starts at 02/24/17 20:57:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:57:39 ########### + + +########## Tcl recorder starts at 02/24/17 20:57:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:57:39 ########### + + +########## Tcl recorder starts at 02/24/17 20:59:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:59:40 ########### + + +########## Tcl recorder starts at 02/24/17 20:59:41 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 20:59:41 ########### + + +########## Tcl recorder starts at 02/24/17 21:00:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 21:00:11 ########### + + +########## Tcl recorder starts at 02/24/17 21:00:11 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 02/24/17 21:00:11 ########### + + +########## Tcl recorder starts at 12/29/17 22:04:15 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:04:15 ########### + + +########## Tcl recorder starts at 12/29/17 22:04:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:04:16 ########### + + +########## Tcl recorder starts at 12/29/17 22:14:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:14:09 ########### + + +########## Tcl recorder starts at 12/29/17 22:14:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:14:10 ########### + + +########## Tcl recorder starts at 12/29/17 22:34:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:34:16 ########### + + +########## Tcl recorder starts at 12/29/17 22:34:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:34:17 ########### + + +########## Tcl recorder starts at 12/29/17 22:35:31 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:35:31 ########### + + +########## Tcl recorder starts at 12/29/17 22:35:32 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:35:32 ########### + + +########## Tcl recorder starts at 12/29/17 22:37:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:37:17 ########### + + +########## Tcl recorder starts at 12/29/17 22:37:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:37:17 ########### + + +########## Tcl recorder starts at 12/29/17 22:43:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:43:44 ########### + + +########## Tcl recorder starts at 12/29/17 22:43:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:43:45 ########### + + +########## Tcl recorder starts at 12/29/17 22:48:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:48:08 ########### + + +########## Tcl recorder starts at 12/29/17 22:48:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/29/17 22:48:08 ########### + + +########## Tcl recorder starts at 12/30/17 00:43:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/30/17 00:43:19 ########### + + +########## Tcl recorder starts at 12/30/17 00:43:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 12/30/17 00:43:20 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index af11c22..0e86964 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,1618 +1,1262 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE 68030_tk -#$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ \ -# A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI \ -# CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC SIZE_0_ E AHIGH_30_ VPA AHIGH_29_ \ -# VMA AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ RW AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ \ -# AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ \ -# AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ -# A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ A_DECODE_12_ A_DECODE_11_ \ -# A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ \ -# A_DECODE_3_ -#$ NODES 609 clk_000_d_i_1__n VPA_D_i N_125_i a_decode_2__n VMA_INT_i N_124_i \ -# sm_amiga_i_0__n N_53_0 rst_dly_i_2__n N_134_i rst_dly_i_1__n N_270_0 rst_dly_i_0__n \ -# N_77_i DSACK1_INT_i N_87_i inst_BGACK_030_INTreg N_137_i_0 N_112_i vcc_n_n DTACK_D0_i \ -# N_113_i inst_VMA_INTreg BGACK_030_INT_i N_114_i gnd_n_n nEXP_SPACE_i \ -# un1_amiga_bus_enable_low AS_000_DMA_i N_109_i un7_as_030 RW_000_i N_108_i \ -# un1_LDS_000_INT clk_030_pe_i_1__n N_111_i un1_UDS_000_INT DS_000_DMA_0_sqmuxa_i \ -# N_265_2_0 un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un4_rw_000_i_n un10_ciin AS_000_i \ -# un1_as_000_i un21_fpu_cs AMIGA_DS_i VPA_c_i un21_berr pos_clk_un3_clk_out_int_i_n \ -# N_52_0 un6_ds_030 cycle_dma_i_0__n DTACK_c_i un13_ciin cycle_dma_i_1__n N_48_0 \ -# cpu_est_1_ pos_clk_as_000_dma6_i_n un3_ahigh_i cpu_est_2_ DS_000_DMA_i \ -# pos_clk_un4_bgack_000_i_n cpu_est_3_ CLK_EXP_i pos_clk_un6_bgack_000_0_n \ -# cpu_est_0_ AMIGA_BUS_ENABLE_DMA_LOW_i N_7_i inst_AMIGA_BUS_ENABLE_DMA_HIGH \ -# ahigh_i_25__n N_41_0 inst_AMIGA_BUS_ENABLE_DMA_LOW ahigh_i_24__n \ -# pos_clk_un1_bgack_030_int_0_n inst_AS_030_D0 ahigh_i_27__n \ -# pos_clk_un12_clk_out_int_0_n inst_AS_030_000_SYNC ahigh_i_26__n pos_clk_un3_0_n \ -# inst_BGACK_030_INT_D ahigh_i_29__n pos_clk_un15_bgack_030_int_i_n inst_AS_000_DMA \ -# ahigh_i_28__n N_3_i inst_DS_000_DMA ahigh_i_31__n N_43_0 inst_VPA_D ahigh_i_30__n \ -# N_4_i CLK_000_D_3_ a_i_1__n N_42_0 inst_DTACK_D0 AMIGA_BUS_ENABLE_DMA_HIGH_i \ -# un6_amiga_bus_data_dir_i inst_RESET_OUT AS_030_D0_i un12_amiga_bus_data_dir_m_i \ -# CLK_030_PE_1_ un10_ciin_i AMIGA_BUS_DATA_DIR_c_0 inst_AMIGA_DS FPU_SENSE_i N_22_i \ -# CLK_000_D_1_ AS_030_000_SYNC_i N_31_0 CLK_000_D_0_ a_decode_i_16__n N_21_i \ -# inst_CLK_OUT_PRE_50 a_decode_i_18__n N_32_0 inst_CLK_OUT_PRE_D a_decode_i_19__n \ -# N_19_i IPL_D0_0_ N_224_i N_34_0 IPL_D0_1_ N_225_i N_18_i IPL_D0_2_ N_226_i N_35_0 \ -# CLK_000_D_2_ pos_clk_un5_bgack_030_int_d_i_n CLK_000_D_4_ \ -# pos_clk_amiga_bus_enable_dma_high_3_0_n pos_clk_un6_bg_030_n \ -# pos_clk_amiga_bus_enable_dma_low_3_0_n pos_clk_ipl_n pos_clk_rw_000_dma_3_0_n \ -# inst_LDS_000_INT un13_ciin_i UDS_000_c_i inst_DS_000_ENABLE un6_ds_030_i \ -# LDS_000_c_i inst_UDS_000_INT N_123_i N_86_i SM_AMIGA_6_ N_122_i N_129_i SM_AMIGA_4_ \ -# un7_as_030_i N_130_i SM_AMIGA_1_ AS_030_c un11_amiga_bus_enable_high_i SM_AMIGA_0_ \ -# N_117_i SIZE_DMA_0_ AS_000_c N_46_0 SIZE_DMA_1_ N_107_i CYCLE_DMA_0_ RW_000_c \ -# pos_clk_size_dma_6_0_0__n CYCLE_DMA_1_ N_106_i CLK_030_PE_0_ \ -# pos_clk_size_dma_6_0_1__n inst_RW_000_INT UDS_000_c N_16_i inst_RW_000_DMA N_254_i \ -# RST_DLY_0_ LDS_000_c N_263_i RST_DLY_1_ N_250_i RST_DLY_2_ size_c_0__n N_256_i \ -# inst_A0_DMA N_189_i pos_clk_rw_000_int_5_n size_c_1__n N_101_i inst_DSACK1_INT \ -# inst_AS_000_INT ahigh_c_24__n N_103_i SM_AMIGA_5_ N_104_i SM_AMIGA_3_ ahigh_c_25__n \ -# SM_AMIGA_2_ N_105_i ahigh_c_26__n N_115_i ahigh_c_27__n N_116_i ahigh_c_28__n N_131_i \ -# N_277_i ahigh_c_29__n N_64_0 N_91_0 ahigh_c_30__n N_159_0 N_14 N_85_i N_15 \ -# ahigh_c_31__n un1_SM_AMIGA_0_sqmuxa_1_0 N_24 RW_c_i N_25 pos_clk_rw_000_int_5_0_n \ -# clk_000_d_i_3__n N_25_i N_28_0 N_24_i N_27_0 ipl_c_i_1__n N_50_0 ipl_c_i_0__n N_49_0 \ -# N_14_i N_39_0 N_15_i N_38_0 N_91_0_1 N_91_0_2 N_91_0_3 N_265_i_1 N_266_i_1 N_266_i_2 \ -# N_138_i_1 N_148_i_1 N_144_i_1 N_142_i_1 N_140_i_1 SM_AMIGA_i_7_ \ -# pos_clk_un10_sm_amiga_i_1_n N_76 N_85_i_1 G_122 N_85_i_2 G_123 a_decode_c_16__n \ -# N_277_1 G_124 N_277_2 un1_rst_2_1 a_decode_c_17__n N_277_3 cpu_est_0_0_ N_277_4 N_64 \ -# a_decode_c_18__n N_277_5 N_122 un10_ciin_1 N_123 a_decode_c_19__n un10_ciin_2 N_132 \ -# un10_ciin_3 N_133 a_decode_c_20__n un10_ciin_4 N_274 un10_ciin_5 N_276 \ -# a_decode_c_21__n un10_ciin_6 N_77 un10_ciin_7 N_79 a_decode_c_22__n un10_ciin_8 N_78 \ -# un10_ciin_9 N_263 a_decode_c_23__n un10_ciin_10 N_108 un10_ciin_11 N_114 a_c_0__n \ -# un6_amiga_bus_data_dir_1 N_85 un6_amiga_bus_data_dir_2 N_104 a_c_1__n \ -# pos_clk_as_000_dma6_1_n N_91 pos_clk_as_000_dma6_2_n N_131 nEXP_SPACE_c \ -# DS_000_DMA_1_sqmuxa_1 N_277 pos_clk_un4_rw_000_1_n N_130 BERR_c \ -# pos_clk_un4_rw_000_2_n N_115 pos_clk_un13_clk_out_int_1_n N_116 BG_030_c N_125_1 \ -# N_105 N_116_1 N_103 BG_000DFFreg pos_clk_un29_clk_000_ne_1_1_n N_101 \ -# pos_clk_un29_clk_000_ne_1_2_n N_259 pos_clk_un29_clk_000_ne_1_3_n N_255 \ -# BGACK_000_c N_261_1 N_256 N_261_2 N_254 CLK_030_c N_262_1 N_16 N_262_2 N_106 \ -# DS_000_ENABLE_0_sqmuxa_1_1 N_86 N_259_1 N_107 CLK_OSZI_c N_250_i_1 N_117 N_189_i_1 \ -# pos_clk_a0_dma_3_n pos_clk_un6_bg_030_1_n N_129 CLK_OUT_INTreg N_108_1 \ -# pos_clk_size_dma_6_1__n N_114_1 pos_clk_size_dma_6_0__n un21_berr_1 \ -# pos_clk_rw_000_dma_3_n FPU_SENSE_c un21_fpu_cs_1 \ -# pos_clk_amiga_bus_enable_dma_low_3_n N_130_1 \ -# pos_clk_amiga_bus_enable_dma_high_3_n IPL_030DFF_0_reg N_136_i_1 \ -# SIZE_DMA_3_sqmuxa N_152_i_1 pos_clk_un5_bgack_030_int_d_n IPL_030DFF_1_reg \ -# N_146_i_1 N_18 N_267_i_1 N_19 IPL_030DFF_2_reg pos_clk_ipl_1_n N_21 bg_000_0_un3_n \ -# N_22 ipl_c_0__n bg_000_0_un1_n un6_amiga_bus_data_dir bg_000_0_un0_n \ -# un12_amiga_bus_data_dir_m ipl_c_1__n uds_000_int_0_un3_n \ -# pos_clk_un3_clk_out_int_n uds_000_int_0_un1_n N_3 ipl_c_2__n uds_000_int_0_un0_n \ -# pos_clk_as_000_dma6_n lds_000_int_0_un3_n DS_000_DMA_1_sqmuxa lds_000_int_0_un1_n \ -# N_4 DTACK_c lds_000_int_0_un0_n AS_000_DMA_1_sqmuxa ds_000_enable_0_un3_n un1_rst_2 \ -# ds_000_enable_0_un1_n G_97 ds_000_enable_0_un0_n N_199 VPA_c ipl_030_0_2__un3_n \ -# pos_clk_un13_bgack_030_int_n ipl_030_0_2__un1_n N_205 ipl_030_0_2__un0_n \ -# pos_clk_un13_clk_out_int_n RST_c vma_int_0_un3_n pos_clk_un15_bgack_030_int_n \ -# vma_int_0_un1_n pos_clk_un3_n RESET_c vma_int_0_un0_n pos_clk_un12_clk_out_int_n \ -# cpu_est_0_1__un3_n pos_clk_un1_bgack_030_int_n RW_c cpu_est_0_1__un1_n \ -# DS_000_DMA_0_sqmuxa cpu_est_0_1__un0_n un1_rst_3 fc_c_0__n cpu_est_0_2__un3_n G_95 \ -# cpu_est_0_2__un1_n G_101 fc_c_1__n cpu_est_0_2__un0_n G_103 cpu_est_0_3__un3_n \ -# pos_clk_un4_rw_000_n cpu_est_0_3__un1_n N_7 AMIGA_BUS_DATA_DIR_c \ -# cpu_est_0_3__un0_n pos_clk_un6_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un3_n \ -# pos_clk_un4_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un1_n N_265_2 \ -# pos_clk_un31_clk_000_ne_1_i_m2_un0_n N_111 bgack_030_int_0_un3_n N_109 BG_030_c_i \ -# bgack_030_int_0_un1_n N_113 pos_clk_un6_bg_030_i_n bgack_030_int_0_un0_n N_112 \ -# pos_clk_un9_bg_030_0_n ds_000_dma_0_un3_n N_98 UDS_000_INT_i ds_000_dma_0_un1_n \ -# pos_clk_un29_clk_000_ne_1_n un1_UDS_000_INT_0 ds_000_dma_0_un0_n N_87 \ -# LDS_000_INT_i as_000_dma_0_un3_n N_270 un1_LDS_000_INT_0 as_000_dma_0_un1_n N_134 \ -# N_23_i as_000_dma_0_un0_n N_125 N_30_0 size_dma_0_1__un3_n N_124 N_20_i \ -# size_dma_0_1__un1_n N_121 N_33_0 size_dma_0_1__un0_n N_120 N_13_i \ -# size_dma_0_0__un3_n N_137 N_40_0 size_dma_0_0__un1_n pos_clk_un31_clk_000_ne_n \ -# ipl_c_i_2__n size_dma_0_0__un0_n N_17 N_51_0 amiga_bus_enable_dma_high_0_un3_n \ -# pos_clk_un9_clk_000_pe_n N_26_i amiga_bus_enable_dma_high_0_un1_n cpu_est_2_1__n \ -# N_29_0 amiga_bus_enable_dma_high_0_un0_n cpu_est_2_2__n a_c_i_0__n \ -# amiga_bus_enable_dma_low_0_un3_n N_261 size_c_i_1__n \ -# amiga_bus_enable_dma_low_0_un1_n N_262 pos_clk_un10_sm_amiga_i_n \ -# amiga_bus_enable_dma_low_0_un0_n N_251 DS_000_ENABLE_0_sqmuxa_1_i a0_dma_0_un3_n \ -# N_252 un1_DS_000_ENABLE_0_sqmuxa_i a0_dma_0_un1_n N_258 N_157_i a0_dma_0_un0_n N_257 \ -# N_160_0 rw_000_dma_0_un3_n DS_000_ENABLE_1_sqmuxa N_161_0 rw_000_dma_0_un1_n \ -# un1_DS_000_ENABLE_0_sqmuxa N_162_0 rw_000_dma_0_un0_n N_102 N_165_i \ -# ipl_030_0_0__un3_n N_118 ipl_030_0_0__un1_n N_119 N_167_i ipl_030_0_0__un0_n N_264 \ -# N_166_i ipl_030_0_1__un3_n DS_000_ENABLE_0_sqmuxa_1 ipl_030_0_1__un1_n N_164 \ -# N_168_i ipl_030_0_1__un0_n N_170 as_030_000_sync_0_un3_n N_168 N_170_i \ -# as_030_000_sync_0_un1_n N_166 as_030_000_sync_0_un0_n N_167 N_164_i \ -# rw_000_int_0_un3_n N_165 rw_000_int_0_un1_n N_162 N_102_i rw_000_int_0_un0_n N_161 \ -# N_264_i a_decode_15__n N_160 N_79_i N_157 N_78_i a_decode_14__n N_26 N_119_i N_13 \ -# N_118_i a_decode_13__n N_20 N_23 N_255_i a_decode_12__n N_8 N_257_i \ -# pos_clk_un9_bg_030_n cpu_est_2_0_2__n a_decode_11__n un1_amiga_bus_enable_low_i \ -# N_258_i un21_fpu_cs_i N_259_i a_decode_10__n sm_amiga_i_2__n cpu_est_2_0_1__n \ -# sm_amiga_i_1__n N_262_i a_decode_9__n sm_amiga_i_3__n N_261_i sm_amiga_i_4__n \ -# pos_clk_un9_clk_000_pe_0_n a_decode_8__n sm_amiga_i_6__n N_251_i sm_amiga_i_5__n \ -# N_252_0 a_decode_7__n clk_000_d_i_0__n N_76_i AS_000_INT_i N_17_i a_decode_6__n \ -# sm_amiga_i_i_7__n N_36_0 AS_030_i N_98_i a_decode_5__n cpu_est_i_2__n \ -# pos_clk_un31_clk_000_ne_i_n cpu_est_i_0__n N_228_i a_decode_4__n cpu_est_i_3__n \ -# N_121_i cpu_est_i_1__n N_120_i a_decode_3__n +#$ PINS 75 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ \ +# A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ +# IPL_030_2_ A_DECODE_16_ A_DECODE_15_ IPL_2_ A_DECODE_14_ A_DECODE_13_ FC_1_ \ +# A_DECODE_12_ AS_030 A_DECODE_11_ AS_000 A_DECODE_10_ RW_000 A_DECODE_9_ DS_030 \ +# A_DECODE_8_ UDS_000 A_DECODE_7_ LDS_000 A_DECODE_6_ nEXP_SPACE A_DECODE_5_ BERR \ +# A_DECODE_4_ BG_030 A_DECODE_3_ BG_000 A_DECODE_2_ BGACK_030 A_0_ BGACK_000 IPL_030_1_ \ +# CLK_030 IPL_030_0_ CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS \ +# FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ \ +# AHIGH_28_ +#$ NODES 508 N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n \ +# ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n inst_BGACK_030_INTreg N_42_0 vcc_n_n \ +# ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n DTACK_c_i \ +# un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i un1_UDS_000_INT \ +# N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 \ +# un10_ciin ahigh_c_28__n LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr \ +# ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 cpu_est_0_ ahigh_c_30__n \ +# N_96_0_1 cpu_est_1_ N_96_0_2 cpu_est_2_ ahigh_c_31__n N_282_0_1 cpu_est_3_ N_282_0_2 \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_282_0_3 inst_AMIGA_BUS_ENABLE_DMA_LOW N_282_0_4 \ +# inst_AS_030_D0 pos_clk_un10_sm_amiga_i_1_n inst_AS_030_D1 un10_ciin_1 \ +# inst_AS_030_000_SYNC un10_ciin_2 inst_AS_000_DMA un10_ciin_3 inst_DS_000_DMA \ +# un10_ciin_4 inst_VMA_INTreg un10_ciin_5 inst_VPA_D un10_ciin_6 CLK_000_D_3_ \ +# un10_ciin_7 inst_DTACK_D0 un10_ciin_8 inst_AMIGA_DS un10_ciin_9 CLK_000_D_1_ \ +# un10_ciin_10 CLK_000_D_0_ un10_ciin_11 inst_CLK_OUT_PRE_50 N_201_1 \ +# inst_CLK_OUT_PRE_D N_201_2 IPL_D0_0_ N_131_i_1 IPL_D0_1_ N_134_0_1 IPL_D0_2_ \ +# N_113_i_1 CLK_000_D_2_ N_113_i_2 CLK_000_D_4_ N_144_1 pos_clk_ipl_n N_144_2 \ +# SIZE_DMA_0_ N_143_1 SIZE_DMA_1_ N_143_2 inst_A0_DMA N_163_1 inst_RW_000_DMA N_163_2 \ +# inst_UDS_000_INT N_163_3 inst_DS_000_ENABLE un21_fpu_cs_1 inst_LDS_000_INT \ +# a_decode_c_16__n un21_berr_1_0 inst_BGACK_030_INT_D pos_clk_cycle_dma_5_1_1__n \ +# SM_AMIGA_6_ a_decode_c_17__n N_199_1 inst_RW_000_INT AS_000_DMA_1_sqmuxa_1 \ +# SM_AMIGA_4_ a_decode_c_18__n N_140_1 SM_AMIGA_1_ N_66_i_1 SM_AMIGA_0_ \ +# a_decode_c_19__n N_66_i_2 CYCLE_DMA_0_ N_205_i_1 CYCLE_DMA_1_ a_decode_c_20__n \ +# N_205_i_2 inst_DSACK1_INT N_180_1 inst_AS_000_INT a_decode_c_21__n N_180_2 \ +# pos_clk_un9_clk_000_pe_n N_59_i_1 SM_AMIGA_5_ a_decode_c_22__n N_127_i_1 \ +# SM_AMIGA_3_ N_123_i_1 SM_AMIGA_2_ a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n \ +# N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 \ +# BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ +# ds_000_dma_0_un0_n BG_000DFFreg as_000_dma_0_un3_n as_000_dma_0_un1_n \ +# as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n \ +# uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c \ +# lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n CLK_OUT_INTreg \ +# as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c \ +# rw_000_int_0_un3_n rw_000_int_0_un1_n IPL_030DFF_0_reg rw_000_int_0_un0_n \ +# as_030_000_sync_0_un3_n IPL_030DFF_1_reg as_030_000_sync_0_un1_n SM_AMIGA_i_7_ \ +# as_030_000_sync_0_un0_n IPL_030DFF_2_reg bgack_030_int_0_un3_n \ +# bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n \ +# cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ +# G_105 cpu_est_0_1__un0_n G_106 ipl_c_2__n cpu_est_0_2__un3_n G_107 \ +# cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 \ +# cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ +# ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ +# ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ +# ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 \ +# fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n \ +# vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ +# AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ +# a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 \ +# a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i \ +# a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n a_decode_8__n N_181 \ +# N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 a_decode_6__n N_185 N_220_i \ +# N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 N_17_i \ +# a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 N_15_i \ +# a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 \ +# un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n \ +# un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i \ +# N_167 N_163_i N_168 N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n \ +# N_165_i N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i \ +# N_11 pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i \ +# N_17 N_167_i pos_clk_un9_bg_030_n G_91 N_170_i N_3 N_169_i N_205 AS_000_DMA_1_sqmuxa \ +# N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n \ +# N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i \ +# N_132_0 un21_fpu_cs_i AS_000_i N_142_i BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 \ +# cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ +# UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i \ +# AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i \ +# a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ +# N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i \ +# sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i \ +# sm_amiga_i_1__n N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n \ +# cpu_est_i_3__n N_266_i VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n \ +# cpu_est_i_1__n N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i \ +# cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i \ +# ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n \ +# ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ +# ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i \ +# cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i N_148_i \ +# N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c N_145_i N_35_0 \ +# AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ -BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF VPA.BLIF \ -RST.BLIF RESET.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ +BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF \ +RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF \ A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF \ A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF A_DECODE_8_.BLIF \ A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF \ A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF \ -LDS_000.BLIF BERR.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF \ -AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF \ -AHIGH_24_.BLIF A_0_.BLIF clk_000_d_i_1__n.BLIF VPA_D_i.BLIF N_125_i.BLIF \ -a_decode_2__n.BLIF VMA_INT_i.BLIF N_124_i.BLIF sm_amiga_i_0__n.BLIF \ -N_53_0.BLIF rst_dly_i_2__n.BLIF N_134_i.BLIF rst_dly_i_1__n.BLIF N_270_0.BLIF \ -rst_dly_i_0__n.BLIF N_77_i.BLIF DSACK1_INT_i.BLIF N_87_i.BLIF \ -inst_BGACK_030_INTreg.BLIF N_137_i_0.BLIF N_112_i.BLIF vcc_n_n.BLIF \ -DTACK_D0_i.BLIF N_113_i.BLIF inst_VMA_INTreg.BLIF BGACK_030_INT_i.BLIF \ -N_114_i.BLIF gnd_n_n.BLIF nEXP_SPACE_i.BLIF un1_amiga_bus_enable_low.BLIF \ -AS_000_DMA_i.BLIF N_109_i.BLIF un7_as_030.BLIF RW_000_i.BLIF N_108_i.BLIF \ -un1_LDS_000_INT.BLIF clk_030_pe_i_1__n.BLIF N_111_i.BLIF un1_UDS_000_INT.BLIF \ -DS_000_DMA_0_sqmuxa_i.BLIF N_265_2_0.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ -pos_clk_un4_rw_000_i_n.BLIF un10_ciin.BLIF AS_000_i.BLIF un1_as_000_i.BLIF \ -un21_fpu_cs.BLIF AMIGA_DS_i.BLIF VPA_c_i.BLIF un21_berr.BLIF \ -pos_clk_un3_clk_out_int_i_n.BLIF N_52_0.BLIF un6_ds_030.BLIF \ -cycle_dma_i_0__n.BLIF DTACK_c_i.BLIF un13_ciin.BLIF cycle_dma_i_1__n.BLIF \ -N_48_0.BLIF cpu_est_1_.BLIF pos_clk_as_000_dma6_i_n.BLIF un3_ahigh_i.BLIF \ -cpu_est_2_.BLIF DS_000_DMA_i.BLIF pos_clk_un4_bgack_000_i_n.BLIF \ -cpu_est_3_.BLIF CLK_EXP_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_7_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -ahigh_i_25__n.BLIF N_41_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -ahigh_i_24__n.BLIF pos_clk_un1_bgack_030_int_0_n.BLIF inst_AS_030_D0.BLIF \ -ahigh_i_27__n.BLIF pos_clk_un12_clk_out_int_0_n.BLIF inst_AS_030_000_SYNC.BLIF \ -ahigh_i_26__n.BLIF pos_clk_un3_0_n.BLIF inst_BGACK_030_INT_D.BLIF \ -ahigh_i_29__n.BLIF pos_clk_un15_bgack_030_int_i_n.BLIF inst_AS_000_DMA.BLIF \ -ahigh_i_28__n.BLIF N_3_i.BLIF inst_DS_000_DMA.BLIF ahigh_i_31__n.BLIF \ -N_43_0.BLIF inst_VPA_D.BLIF ahigh_i_30__n.BLIF N_4_i.BLIF CLK_000_D_3_.BLIF \ -a_i_1__n.BLIF N_42_0.BLIF inst_DTACK_D0.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ -un6_amiga_bus_data_dir_i.BLIF inst_RESET_OUT.BLIF AS_030_D0_i.BLIF \ -un12_amiga_bus_data_dir_m_i.BLIF CLK_030_PE_1_.BLIF un10_ciin_i.BLIF \ -AMIGA_BUS_DATA_DIR_c_0.BLIF inst_AMIGA_DS.BLIF FPU_SENSE_i.BLIF N_22_i.BLIF \ -CLK_000_D_1_.BLIF AS_030_000_SYNC_i.BLIF N_31_0.BLIF CLK_000_D_0_.BLIF \ -a_decode_i_16__n.BLIF N_21_i.BLIF inst_CLK_OUT_PRE_50.BLIF \ -a_decode_i_18__n.BLIF N_32_0.BLIF inst_CLK_OUT_PRE_D.BLIF \ -a_decode_i_19__n.BLIF N_19_i.BLIF IPL_D0_0_.BLIF N_224_i.BLIF N_34_0.BLIF \ -IPL_D0_1_.BLIF N_225_i.BLIF N_18_i.BLIF IPL_D0_2_.BLIF N_226_i.BLIF \ -N_35_0.BLIF CLK_000_D_2_.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \ -CLK_000_D_4_.BLIF pos_clk_amiga_bus_enable_dma_high_3_0_n.BLIF \ -pos_clk_un6_bg_030_n.BLIF pos_clk_amiga_bus_enable_dma_low_3_0_n.BLIF \ -pos_clk_ipl_n.BLIF pos_clk_rw_000_dma_3_0_n.BLIF inst_LDS_000_INT.BLIF \ -un13_ciin_i.BLIF UDS_000_c_i.BLIF inst_DS_000_ENABLE.BLIF un6_ds_030_i.BLIF \ -LDS_000_c_i.BLIF inst_UDS_000_INT.BLIF N_123_i.BLIF N_86_i.BLIF \ -SM_AMIGA_6_.BLIF N_122_i.BLIF N_129_i.BLIF SM_AMIGA_4_.BLIF un7_as_030_i.BLIF \ -N_130_i.BLIF SM_AMIGA_1_.BLIF AS_030_c.BLIF un11_amiga_bus_enable_high_i.BLIF \ -SM_AMIGA_0_.BLIF N_117_i.BLIF SIZE_DMA_0_.BLIF AS_000_c.BLIF N_46_0.BLIF \ -SIZE_DMA_1_.BLIF N_107_i.BLIF CYCLE_DMA_0_.BLIF RW_000_c.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF CYCLE_DMA_1_.BLIF N_106_i.BLIF \ -CLK_030_PE_0_.BLIF pos_clk_size_dma_6_0_1__n.BLIF inst_RW_000_INT.BLIF \ -UDS_000_c.BLIF N_16_i.BLIF inst_RW_000_DMA.BLIF N_254_i.BLIF RST_DLY_0_.BLIF \ -LDS_000_c.BLIF N_263_i.BLIF RST_DLY_1_.BLIF N_250_i.BLIF RST_DLY_2_.BLIF \ -size_c_0__n.BLIF N_256_i.BLIF inst_A0_DMA.BLIF N_189_i.BLIF \ -pos_clk_rw_000_int_5_n.BLIF size_c_1__n.BLIF N_101_i.BLIF inst_DSACK1_INT.BLIF \ -inst_AS_000_INT.BLIF ahigh_c_24__n.BLIF N_103_i.BLIF SM_AMIGA_5_.BLIF \ -N_104_i.BLIF SM_AMIGA_3_.BLIF ahigh_c_25__n.BLIF SM_AMIGA_2_.BLIF N_105_i.BLIF \ -ahigh_c_26__n.BLIF N_115_i.BLIF ahigh_c_27__n.BLIF N_116_i.BLIF \ -ahigh_c_28__n.BLIF N_131_i.BLIF N_277_i.BLIF ahigh_c_29__n.BLIF N_64_0.BLIF \ -N_91_0.BLIF ahigh_c_30__n.BLIF N_159_0.BLIF N_14.BLIF N_85_i.BLIF N_15.BLIF \ -ahigh_c_31__n.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_24.BLIF RW_c_i.BLIF \ -N_25.BLIF pos_clk_rw_000_int_5_0_n.BLIF clk_000_d_i_3__n.BLIF N_25_i.BLIF \ -N_28_0.BLIF N_24_i.BLIF N_27_0.BLIF ipl_c_i_1__n.BLIF N_50_0.BLIF \ -ipl_c_i_0__n.BLIF N_49_0.BLIF N_14_i.BLIF N_39_0.BLIF N_15_i.BLIF N_38_0.BLIF \ -N_91_0_1.BLIF N_91_0_2.BLIF N_91_0_3.BLIF N_265_i_1.BLIF N_266_i_1.BLIF \ -N_266_i_2.BLIF N_138_i_1.BLIF N_148_i_1.BLIF N_144_i_1.BLIF N_142_i_1.BLIF \ -N_140_i_1.BLIF SM_AMIGA_i_7_.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_76.BLIF \ -N_85_i_1.BLIF G_122.BLIF N_85_i_2.BLIF G_123.BLIF a_decode_c_16__n.BLIF \ -N_277_1.BLIF G_124.BLIF N_277_2.BLIF un1_rst_2_1.BLIF a_decode_c_17__n.BLIF \ -N_277_3.BLIF cpu_est_0_0_.BLIF N_277_4.BLIF N_64.BLIF a_decode_c_18__n.BLIF \ -N_277_5.BLIF N_122.BLIF un10_ciin_1.BLIF N_123.BLIF a_decode_c_19__n.BLIF \ -un10_ciin_2.BLIF N_132.BLIF un10_ciin_3.BLIF N_133.BLIF a_decode_c_20__n.BLIF \ -un10_ciin_4.BLIF N_274.BLIF un10_ciin_5.BLIF N_276.BLIF a_decode_c_21__n.BLIF \ -un10_ciin_6.BLIF N_77.BLIF un10_ciin_7.BLIF N_79.BLIF a_decode_c_22__n.BLIF \ -un10_ciin_8.BLIF N_78.BLIF un10_ciin_9.BLIF N_263.BLIF a_decode_c_23__n.BLIF \ -un10_ciin_10.BLIF N_108.BLIF un10_ciin_11.BLIF N_114.BLIF a_c_0__n.BLIF \ -un6_amiga_bus_data_dir_1.BLIF N_85.BLIF un6_amiga_bus_data_dir_2.BLIF \ -N_104.BLIF a_c_1__n.BLIF pos_clk_as_000_dma6_1_n.BLIF N_91.BLIF \ -pos_clk_as_000_dma6_2_n.BLIF N_131.BLIF nEXP_SPACE_c.BLIF \ -DS_000_DMA_1_sqmuxa_1.BLIF N_277.BLIF pos_clk_un4_rw_000_1_n.BLIF N_130.BLIF \ -BERR_c.BLIF pos_clk_un4_rw_000_2_n.BLIF N_115.BLIF \ -pos_clk_un13_clk_out_int_1_n.BLIF N_116.BLIF BG_030_c.BLIF N_125_1.BLIF \ -N_105.BLIF N_116_1.BLIF N_103.BLIF BG_000DFFreg.BLIF \ -pos_clk_un29_clk_000_ne_1_1_n.BLIF N_101.BLIF \ -pos_clk_un29_clk_000_ne_1_2_n.BLIF N_259.BLIF \ -pos_clk_un29_clk_000_ne_1_3_n.BLIF N_255.BLIF BGACK_000_c.BLIF N_261_1.BLIF \ -N_256.BLIF N_261_2.BLIF N_254.BLIF CLK_030_c.BLIF N_262_1.BLIF N_16.BLIF \ -N_262_2.BLIF N_106.BLIF DS_000_ENABLE_0_sqmuxa_1_1.BLIF N_86.BLIF N_259_1.BLIF \ -N_107.BLIF CLK_OSZI_c.BLIF N_250_i_1.BLIF N_117.BLIF N_189_i_1.BLIF \ -pos_clk_a0_dma_3_n.BLIF pos_clk_un6_bg_030_1_n.BLIF N_129.BLIF \ -CLK_OUT_INTreg.BLIF N_108_1.BLIF pos_clk_size_dma_6_1__n.BLIF N_114_1.BLIF \ -pos_clk_size_dma_6_0__n.BLIF un21_berr_1.BLIF pos_clk_rw_000_dma_3_n.BLIF \ -FPU_SENSE_c.BLIF un21_fpu_cs_1.BLIF pos_clk_amiga_bus_enable_dma_low_3_n.BLIF \ -N_130_1.BLIF pos_clk_amiga_bus_enable_dma_high_3_n.BLIF IPL_030DFF_0_reg.BLIF \ -N_136_i_1.BLIF SIZE_DMA_3_sqmuxa.BLIF N_152_i_1.BLIF \ -pos_clk_un5_bgack_030_int_d_n.BLIF IPL_030DFF_1_reg.BLIF N_146_i_1.BLIF \ -N_18.BLIF N_267_i_1.BLIF N_19.BLIF IPL_030DFF_2_reg.BLIF pos_clk_ipl_1_n.BLIF \ -N_21.BLIF bg_000_0_un3_n.BLIF N_22.BLIF ipl_c_0__n.BLIF bg_000_0_un1_n.BLIF \ -un6_amiga_bus_data_dir.BLIF bg_000_0_un0_n.BLIF un12_amiga_bus_data_dir_m.BLIF \ -ipl_c_1__n.BLIF uds_000_int_0_un3_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ -uds_000_int_0_un1_n.BLIF N_3.BLIF ipl_c_2__n.BLIF uds_000_int_0_un0_n.BLIF \ -pos_clk_as_000_dma6_n.BLIF lds_000_int_0_un3_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \ -lds_000_int_0_un1_n.BLIF N_4.BLIF DTACK_c.BLIF lds_000_int_0_un0_n.BLIF \ -AS_000_DMA_1_sqmuxa.BLIF ds_000_enable_0_un3_n.BLIF un1_rst_2.BLIF \ -ds_000_enable_0_un1_n.BLIF G_97.BLIF ds_000_enable_0_un0_n.BLIF N_199.BLIF \ -VPA_c.BLIF ipl_030_0_2__un3_n.BLIF pos_clk_un13_bgack_030_int_n.BLIF \ -ipl_030_0_2__un1_n.BLIF N_205.BLIF ipl_030_0_2__un0_n.BLIF \ -pos_clk_un13_clk_out_int_n.BLIF RST_c.BLIF vma_int_0_un3_n.BLIF \ -pos_clk_un15_bgack_030_int_n.BLIF vma_int_0_un1_n.BLIF pos_clk_un3_n.BLIF \ -RESET_c.BLIF vma_int_0_un0_n.BLIF pos_clk_un12_clk_out_int_n.BLIF \ -cpu_est_0_1__un3_n.BLIF pos_clk_un1_bgack_030_int_n.BLIF RW_c.BLIF \ -cpu_est_0_1__un1_n.BLIF DS_000_DMA_0_sqmuxa.BLIF cpu_est_0_1__un0_n.BLIF \ -un1_rst_3.BLIF fc_c_0__n.BLIF cpu_est_0_2__un3_n.BLIF G_95.BLIF \ -cpu_est_0_2__un1_n.BLIF G_101.BLIF fc_c_1__n.BLIF cpu_est_0_2__un0_n.BLIF \ -G_103.BLIF cpu_est_0_3__un3_n.BLIF pos_clk_un4_rw_000_n.BLIF \ -cpu_est_0_3__un1_n.BLIF N_7.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -cpu_est_0_3__un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un3_n.BLIF pos_clk_un4_bgack_000_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un1_n.BLIF N_265_2.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un0_n.BLIF N_111.BLIF \ -bgack_030_int_0_un3_n.BLIF N_109.BLIF BG_030_c_i.BLIF \ -bgack_030_int_0_un1_n.BLIF N_113.BLIF pos_clk_un6_bg_030_i_n.BLIF \ -bgack_030_int_0_un0_n.BLIF N_112.BLIF pos_clk_un9_bg_030_0_n.BLIF \ -ds_000_dma_0_un3_n.BLIF N_98.BLIF UDS_000_INT_i.BLIF ds_000_dma_0_un1_n.BLIF \ -pos_clk_un29_clk_000_ne_1_n.BLIF un1_UDS_000_INT_0.BLIF \ -ds_000_dma_0_un0_n.BLIF N_87.BLIF LDS_000_INT_i.BLIF as_000_dma_0_un3_n.BLIF \ -N_270.BLIF un1_LDS_000_INT_0.BLIF as_000_dma_0_un1_n.BLIF N_134.BLIF \ -N_23_i.BLIF as_000_dma_0_un0_n.BLIF N_125.BLIF N_30_0.BLIF \ -size_dma_0_1__un3_n.BLIF N_124.BLIF N_20_i.BLIF size_dma_0_1__un1_n.BLIF \ -N_121.BLIF N_33_0.BLIF size_dma_0_1__un0_n.BLIF N_120.BLIF N_13_i.BLIF \ -size_dma_0_0__un3_n.BLIF N_137.BLIF N_40_0.BLIF size_dma_0_0__un1_n.BLIF \ -pos_clk_un31_clk_000_ne_n.BLIF ipl_c_i_2__n.BLIF size_dma_0_0__un0_n.BLIF \ -N_17.BLIF N_51_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ -pos_clk_un9_clk_000_pe_n.BLIF N_26_i.BLIF \ -amiga_bus_enable_dma_high_0_un1_n.BLIF cpu_est_2_1__n.BLIF N_29_0.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF cpu_est_2_2__n.BLIF a_c_i_0__n.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF N_261.BLIF size_c_i_1__n.BLIF \ -amiga_bus_enable_dma_low_0_un1_n.BLIF N_262.BLIF \ -pos_clk_un10_sm_amiga_i_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF \ -N_251.BLIF DS_000_ENABLE_0_sqmuxa_1_i.BLIF a0_dma_0_un3_n.BLIF N_252.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa_i.BLIF a0_dma_0_un1_n.BLIF N_258.BLIF N_157_i.BLIF \ -a0_dma_0_un0_n.BLIF N_257.BLIF N_160_0.BLIF rw_000_dma_0_un3_n.BLIF \ -DS_000_ENABLE_1_sqmuxa.BLIF N_161_0.BLIF rw_000_dma_0_un1_n.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa.BLIF N_162_0.BLIF rw_000_dma_0_un0_n.BLIF \ -N_102.BLIF N_165_i.BLIF ipl_030_0_0__un3_n.BLIF N_118.BLIF \ -ipl_030_0_0__un1_n.BLIF N_119.BLIF N_167_i.BLIF ipl_030_0_0__un0_n.BLIF \ -N_264.BLIF N_166_i.BLIF ipl_030_0_1__un3_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF \ -ipl_030_0_1__un1_n.BLIF N_164.BLIF N_168_i.BLIF ipl_030_0_1__un0_n.BLIF \ -N_170.BLIF as_030_000_sync_0_un3_n.BLIF N_168.BLIF N_170_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_166.BLIF as_030_000_sync_0_un0_n.BLIF \ -N_167.BLIF N_164_i.BLIF rw_000_int_0_un3_n.BLIF N_165.BLIF \ -rw_000_int_0_un1_n.BLIF N_162.BLIF N_102_i.BLIF rw_000_int_0_un0_n.BLIF \ -N_161.BLIF N_264_i.BLIF a_decode_15__n.BLIF N_160.BLIF N_79_i.BLIF N_157.BLIF \ -N_78_i.BLIF a_decode_14__n.BLIF N_26.BLIF N_119_i.BLIF N_13.BLIF N_118_i.BLIF \ -a_decode_13__n.BLIF N_20.BLIF N_23.BLIF N_255_i.BLIF a_decode_12__n.BLIF \ -N_8.BLIF N_257_i.BLIF pos_clk_un9_bg_030_n.BLIF cpu_est_2_0_2__n.BLIF \ -a_decode_11__n.BLIF un1_amiga_bus_enable_low_i.BLIF N_258_i.BLIF \ -un21_fpu_cs_i.BLIF N_259_i.BLIF a_decode_10__n.BLIF sm_amiga_i_2__n.BLIF \ -cpu_est_2_0_1__n.BLIF sm_amiga_i_1__n.BLIF N_262_i.BLIF a_decode_9__n.BLIF \ -sm_amiga_i_3__n.BLIF N_261_i.BLIF sm_amiga_i_4__n.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF a_decode_8__n.BLIF sm_amiga_i_6__n.BLIF \ -N_251_i.BLIF sm_amiga_i_5__n.BLIF N_252_0.BLIF a_decode_7__n.BLIF \ -clk_000_d_i_0__n.BLIF N_76_i.BLIF AS_000_INT_i.BLIF N_17_i.BLIF \ -a_decode_6__n.BLIF sm_amiga_i_i_7__n.BLIF N_36_0.BLIF AS_030_i.BLIF \ -N_98_i.BLIF a_decode_5__n.BLIF cpu_est_i_2__n.BLIF \ -pos_clk_un31_clk_000_ne_i_n.BLIF cpu_est_i_0__n.BLIF N_228_i.BLIF \ -a_decode_4__n.BLIF cpu_est_i_3__n.BLIF N_121_i.BLIF cpu_est_i_1__n.BLIF \ -N_120_i.BLIF a_decode_3__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ +LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF \ +AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF \ +A_0_.BLIF N_23_0.BLIF UDS_000_c.BLIF N_19_i.BLIF N_22_0.BLIF LDS_000_c.BLIF \ +N_18_i.BLIF N_21_0.BLIF size_c_0__n.BLIF ipl_c_i_2__n.BLIF N_43_0.BLIF \ +size_c_1__n.BLIF ipl_c_i_1__n.BLIF inst_BGACK_030_INTreg.BLIF N_42_0.BLIF \ +vcc_n_n.BLIF ahigh_c_24__n.BLIF ipl_c_i_0__n.BLIF un5_e.BLIF N_41_0.BLIF \ +gnd_n_n.BLIF ahigh_c_25__n.BLIF DTACK_c_i.BLIF un1_amiga_bus_enable_low.BLIF \ +N_45_0.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF VPA_c_i.BLIF \ +un1_UDS_000_INT.BLIF N_44_0.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF \ +N_13_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_27_0.BLIF un10_ciin.BLIF \ +ahigh_c_28__n.BLIF LDS_000_INT_i.BLIF un21_fpu_cs.BLIF un1_LDS_000_INT_0.BLIF \ +un21_berr.BLIF ahigh_c_29__n.BLIF UDS_000_INT_i.BLIF un2_ds_030.BLIF \ +un1_UDS_000_INT_0.BLIF cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_96_0_1.BLIF \ +cpu_est_1_.BLIF N_96_0_2.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF \ +N_282_0_1.BLIF cpu_est_3_.BLIF N_282_0_2.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_282_0_3.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_282_0_4.BLIF inst_AS_030_D0.BLIF \ +pos_clk_un10_sm_amiga_i_1_n.BLIF inst_AS_030_D1.BLIF un10_ciin_1.BLIF \ +inst_AS_030_000_SYNC.BLIF un10_ciin_2.BLIF inst_AS_000_DMA.BLIF \ +un10_ciin_3.BLIF inst_DS_000_DMA.BLIF un10_ciin_4.BLIF inst_VMA_INTreg.BLIF \ +un10_ciin_5.BLIF inst_VPA_D.BLIF un10_ciin_6.BLIF CLK_000_D_3_.BLIF \ +un10_ciin_7.BLIF inst_DTACK_D0.BLIF un10_ciin_8.BLIF inst_AMIGA_DS.BLIF \ +un10_ciin_9.BLIF CLK_000_D_1_.BLIF un10_ciin_10.BLIF CLK_000_D_0_.BLIF \ +un10_ciin_11.BLIF inst_CLK_OUT_PRE_50.BLIF N_201_1.BLIF \ +inst_CLK_OUT_PRE_D.BLIF N_201_2.BLIF IPL_D0_0_.BLIF N_131_i_1.BLIF \ +IPL_D0_1_.BLIF N_134_0_1.BLIF IPL_D0_2_.BLIF N_113_i_1.BLIF CLK_000_D_2_.BLIF \ +N_113_i_2.BLIF CLK_000_D_4_.BLIF N_144_1.BLIF pos_clk_ipl_n.BLIF N_144_2.BLIF \ +SIZE_DMA_0_.BLIF N_143_1.BLIF SIZE_DMA_1_.BLIF N_143_2.BLIF inst_A0_DMA.BLIF \ +N_163_1.BLIF inst_RW_000_DMA.BLIF N_163_2.BLIF inst_UDS_000_INT.BLIF \ +N_163_3.BLIF inst_DS_000_ENABLE.BLIF un21_fpu_cs_1.BLIF inst_LDS_000_INT.BLIF \ +a_decode_c_16__n.BLIF un21_berr_1_0.BLIF inst_BGACK_030_INT_D.BLIF \ +pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_6_.BLIF a_decode_c_17__n.BLIF \ +N_199_1.BLIF inst_RW_000_INT.BLIF AS_000_DMA_1_sqmuxa_1.BLIF SM_AMIGA_4_.BLIF \ +a_decode_c_18__n.BLIF N_140_1.BLIF SM_AMIGA_1_.BLIF N_66_i_1.BLIF \ +SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.BLIF \ +N_205_i_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_205_i_2.BLIF \ +inst_DSACK1_INT.BLIF N_180_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF \ +N_180_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_59_i_1.BLIF SM_AMIGA_5_.BLIF \ +a_decode_c_22__n.BLIF N_127_i_1.BLIF SM_AMIGA_3_.BLIF N_123_i_1.BLIF \ +SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_121_i_1.BLIF N_119_i_1.BLIF N_6.BLIF \ +a_c_0__n.BLIF N_117_i_1.BLIF N_115_i_1.BLIF a_c_1__n.BLIF N_111_i_1.BLIF \ +N_165_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_162_1.BLIF N_148_1.BLIF N_18.BLIF \ +BERR_c.BLIF pos_clk_ipl_1_n.BLIF N_19.BLIF ds_000_dma_0_un3_n.BLIF N_20.BLIF \ +BG_030_c.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \ +BG_000DFFreg.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF \ +as_000_dma_0_un0_n.BLIF BGACK_000_c.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF \ +bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF CLK_OSZI_c.BLIF \ +lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ +CLK_OUT_INTreg.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un1_n.BLIF \ +as_030_d1_0_un0_n.BLIF FPU_SENSE_c.BLIF rw_000_int_0_un3_n.BLIF \ +rw_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF rw_000_int_0_un0_n.BLIF \ +as_030_000_sync_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF \ +as_030_000_sync_0_un1_n.BLIF SM_AMIGA_i_7_.BLIF as_030_000_sync_0_un0_n.BLIF \ +IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF \ +cpu_est_2_1__n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF \ +cpu_est_2_2__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_2_3__n.BLIF \ +ipl_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF G_105.BLIF cpu_est_0_1__un0_n.BLIF \ +G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_2__un3_n.BLIF G_107.BLIF \ +cpu_est_0_2__un1_n.BLIF N_60.BLIF cpu_est_0_2__un0_n.BLIF N_63.BLIF \ +DTACK_c.BLIF cpu_est_0_3__un3_n.BLIF N_126.BLIF cpu_est_0_3__un1_n.BLIF \ +N_150.BLIF cpu_est_0_3__un0_n.BLIF N_151.BLIF ipl_030_0_0__un3_n.BLIF \ +N_219.BLIF VPA_c.BLIF ipl_030_0_0__un1_n.BLIF N_175.BLIF \ +ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF N_59.BLIF RST_c.BLIF \ +ipl_030_0_1__un1_n.BLIF N_68.BLIF ipl_030_0_1__un0_n.BLIF N_72.BLIF \ +ipl_030_0_2__un3_n.BLIF N_80.BLIF ipl_030_0_2__un1_n.BLIF N_93.BLIF RW_c.BLIF \ +ipl_030_0_2__un0_n.BLIF N_98.BLIF ds_000_enable_0_un3_n.BLIF N_107.BLIF \ +fc_c_0__n.BLIF ds_000_enable_0_un1_n.BLIF N_128.BLIF \ +ds_000_enable_0_un0_n.BLIF N_131.BLIF fc_c_1__n.BLIF vma_int_0_un3_n.BLIF \ +N_134.BLIF vma_int_0_un1_n.BLIF N_135.BLIF vma_int_0_un0_n.BLIF N_141.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF a_decode_15__n.BLIF N_142.BLIF N_143.BLIF \ +a_decode_14__n.BLIF N_144.BLIF N_145.BLIF a_decode_13__n.BLIF N_146.BLIF \ +N_205_i.BLIF N_147.BLIF N_140_i.BLIF a_decode_12__n.BLIF N_148.BLIF \ +AMIGA_DS_i.BLIF N_149.BLIF a_decode_11__n.BLIF N_154.BLIF N_199_i.BLIF \ +N_155.BLIF N_198_i.BLIF a_decode_10__n.BLIF N_162.BLIF N_180_i.BLIF N_165.BLIF \ +N_262_i.BLIF a_decode_9__n.BLIF N_259.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ +N_260.BLIF pos_clk_un2_i_n.BLIF a_decode_8__n.BLIF N_181.BLIF N_3_i.BLIF \ +N_182.BLIF N_32_0.BLIF a_decode_7__n.BLIF N_183.BLIF N_4_i.BLIF N_184.BLIF \ +N_31_0.BLIF a_decode_6__n.BLIF N_185.BLIF N_220_i.BLIF N_186.BLIF \ +BG_030_c_i.BLIF a_decode_5__n.BLIF N_266.BLIF pos_clk_un9_bg_030_0_n.BLIF \ +N_267.BLIF N_17_i.BLIF a_decode_4__n.BLIF N_268.BLIF N_24_0.BLIF N_190.BLIF \ +N_16_i.BLIF a_decode_3__n.BLIF N_191.BLIF N_25_0.BLIF N_201.BLIF N_15_i.BLIF \ +a_decode_2__n.BLIF N_202.BLIF N_26_0.BLIF N_203.BLIF N_12_i.BLIF N_208.BLIF \ +N_28_0.BLIF N_163.BLIF N_11_i.BLIF N_282.BLIF N_29_0.BLIF un21_berr_1.BLIF \ +N_5_i.BLIF N_132.BLIF N_30_0.BLIF N_96.BLIF a_c_i_0__n.BLIF N_129.BLIF \ +size_c_i_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF pos_clk_un10_sm_amiga_i_n.BLIF \ +N_169.BLIF un1_dsack1_i.BLIF N_170.BLIF N_69_i.BLIF N_167.BLIF N_163_i.BLIF \ +N_168.BLIF N_244_0.BLIF pos_clk_rw_000_int_5_n.BLIF N_164_i.BLIF \ +pos_clk_un6_bgack_000_n.BLIF N_165_i.BLIF N_274.BLIF \ +un11_amiga_bus_enable_high_i.BLIF N_164.BLIF un10_ciin_i.BLIF N_244.BLIF \ +N_60_0.BLIF N_5.BLIF N_274_i.BLIF N_11.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ +N_12.BLIF RW_c_i.BLIF N_15.BLIF pos_clk_rw_000_int_5_0_n.BLIF N_16.BLIF \ +N_168_i.BLIF N_17.BLIF N_167_i.BLIF pos_clk_un9_bg_030_n.BLIF G_91.BLIF \ +N_170_i.BLIF N_3.BLIF N_169_i.BLIF N_205.BLIF AS_000_DMA_1_sqmuxa.BLIF \ +N_38_0.BLIF N_4.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_199.BLIF N_282_0.BLIF \ +pos_clk_un2_n.BLIF clk_000_d_i_3__n.BLIF N_140.BLIF N_96_0.BLIF N_262.BLIF \ +N_129_i.BLIF N_198.BLIF N_268_i.BLIF N_180.BLIF N_246_i.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_132_0.BLIF un21_fpu_cs_i.BLIF AS_000_i.BLIF \ +N_142_i.BLIF BGACK_030_INT_i.BLIF N_141_i.BLIF nEXP_SPACE_i.BLIF N_135_0.BLIF \ +cycle_dma_i_0__n.BLIF N_134_0.BLIF RW_000_i.BLIF N_131_i.BLIF CLK_EXP_i.BLIF \ +LDS_000_c_i.BLIF cycle_dma_i_1__n.BLIF UDS_000_c_i.BLIF DS_000_DMA_i.BLIF \ +N_128_i.BLIF AS_000_DMA_i.BLIF N_107_i.BLIF a_i_1__n.BLIF N_203_i.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF \ +a_decode_i_19__n.BLIF N_201_i.BLIF a_decode_i_18__n.BLIF N_202_i.BLIF \ +a_decode_i_16__n.BLIF VMA_INT_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ +N_98_i.BLIF sm_amiga_i_0__n.BLIF N_93_i.BLIF sm_amiga_i_5__n.BLIF N_82_i.BLIF \ +sm_amiga_i_6__n.BLIF N_80_i.BLIF sm_amiga_i_i_7__n.BLIF N_72_i.BLIF \ +AS_030_i.BLIF N_68_i.BLIF AS_000_INT_i.BLIF N_59_i.BLIF DSACK1_INT_i.BLIF \ +N_190_i.BLIF sm_amiga_i_1__n.BLIF N_191_i.BLIF FPU_SENSE_i.BLIF \ +AS_030_D1_i.BLIF N_267_i.BLIF cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ +N_266_i.BLIF VPA_D_i.BLIF sm_amiga_i_3__n.BLIF N_186_i.BLIF \ +sm_amiga_i_4__n.BLIF cpu_est_i_1__n.BLIF N_185_i.BLIF clk_000_d_i_0__n.BLIF \ +clk_000_d_i_1__n.BLIF N_183_i.BLIF AS_030_D0_i.BLIF N_184_i.BLIF \ +cpu_est_i_2__n.BLIF DTACK_D0_i.BLIF N_182_i.BLIF sm_amiga_i_2__n.BLIF \ +AS_030_000_SYNC_i.BLIF N_181_i.BLIF ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF \ +N_260_i.BLIF ahigh_i_28__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +ahigh_i_29__n.BLIF N_259_i.BLIF ahigh_i_26__n.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF ahigh_i_27__n.BLIF N_63_0.BLIF \ +ahigh_i_24__n.BLIF N_155_i.BLIF ahigh_i_25__n.BLIF N_162_i.BLIF N_187_i.BLIF \ +un5_e_0.BLIF N_188_i.BLIF N_154_i.BLIF N_189_i.BLIF cpu_est_2_0_3__n.BLIF \ +N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n.BLIF N_147_i.BLIF un2_ds_030_i.BLIF \ +N_148_i.BLIF N_219_i.BLIF cpu_est_2_0_1__n.BLIF N_175_i.BLIF N_146_i.BLIF \ +un3_as_030_i.BLIF N_36_0.BLIF AS_030_c.BLIF N_145_i.BLIF N_35_0.BLIF \ +AS_000_c.BLIF N_143_i.BLIF N_144_i.BLIF RW_000_c.BLIF \ +pos_clk_un9_clk_000_pe_0_n.BLIF N_20_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF +AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ -SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ -cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ +SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ -CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ -CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C \ -CLK_030_PE_0_.D CLK_030_PE_0_.C CLK_030_PE_1_.D CLK_030_PE_1_.C SIZE_DMA_0_.D \ -SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ -RST_DLY_2_.D RST_DLY_2_.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ +CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ +SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D \ +CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ +cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ -inst_AMIGA_DS.D inst_AMIGA_DS.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_VPA_D.D inst_VPA_D.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ -BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ -AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR DTACK RW SIZE_0_ AHIGH_30_ \ -AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \ -clk_000_d_i_1__n VPA_D_i N_125_i a_decode_2__n VMA_INT_i N_124_i \ -sm_amiga_i_0__n N_53_0 rst_dly_i_2__n N_134_i rst_dly_i_1__n N_270_0 \ -rst_dly_i_0__n N_77_i DSACK1_INT_i N_87_i N_137_i_0 N_112_i vcc_n_n DTACK_D0_i \ -N_113_i BGACK_030_INT_i N_114_i gnd_n_n nEXP_SPACE_i un1_amiga_bus_enable_low \ -AS_000_DMA_i N_109_i un7_as_030 RW_000_i N_108_i un1_LDS_000_INT \ -clk_030_pe_i_1__n N_111_i un1_UDS_000_INT DS_000_DMA_0_sqmuxa_i N_265_2_0 \ -un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un4_rw_000_i_n un10_ciin AS_000_i un1_as_000_i \ -un21_fpu_cs AMIGA_DS_i VPA_c_i un21_berr pos_clk_un3_clk_out_int_i_n N_52_0 \ -un6_ds_030 cycle_dma_i_0__n DTACK_c_i un13_ciin cycle_dma_i_1__n N_48_0 \ -pos_clk_as_000_dma6_i_n un3_ahigh_i DS_000_DMA_i pos_clk_un4_bgack_000_i_n \ -CLK_EXP_i pos_clk_un6_bgack_000_0_n AMIGA_BUS_ENABLE_DMA_LOW_i N_7_i \ -ahigh_i_25__n N_41_0 ahigh_i_24__n pos_clk_un1_bgack_030_int_0_n ahigh_i_27__n \ -pos_clk_un12_clk_out_int_0_n ahigh_i_26__n pos_clk_un3_0_n ahigh_i_29__n \ -pos_clk_un15_bgack_030_int_i_n ahigh_i_28__n N_3_i ahigh_i_31__n N_43_0 \ -ahigh_i_30__n N_4_i a_i_1__n N_42_0 AMIGA_BUS_ENABLE_DMA_HIGH_i \ -un6_amiga_bus_data_dir_i AS_030_D0_i un12_amiga_bus_data_dir_m_i un10_ciin_i \ -AMIGA_BUS_DATA_DIR_c_0 FPU_SENSE_i N_22_i AS_030_000_SYNC_i N_31_0 \ -a_decode_i_16__n N_21_i a_decode_i_18__n N_32_0 a_decode_i_19__n N_19_i \ -N_224_i N_34_0 N_225_i N_18_i N_226_i N_35_0 pos_clk_un5_bgack_030_int_d_i_n \ -pos_clk_amiga_bus_enable_dma_high_3_0_n pos_clk_un6_bg_030_n \ -pos_clk_amiga_bus_enable_dma_low_3_0_n pos_clk_ipl_n pos_clk_rw_000_dma_3_0_n \ -un13_ciin_i UDS_000_c_i un6_ds_030_i LDS_000_c_i N_123_i N_86_i N_122_i \ -N_129_i un7_as_030_i N_130_i AS_030_c un11_amiga_bus_enable_high_i N_117_i \ -AS_000_c N_46_0 N_107_i RW_000_c pos_clk_size_dma_6_0_0__n N_106_i \ -pos_clk_size_dma_6_0_1__n UDS_000_c N_16_i N_254_i LDS_000_c N_263_i N_250_i \ -size_c_0__n N_256_i N_189_i pos_clk_rw_000_int_5_n size_c_1__n N_101_i \ -ahigh_c_24__n N_103_i N_104_i ahigh_c_25__n N_105_i ahigh_c_26__n N_115_i \ -ahigh_c_27__n N_116_i ahigh_c_28__n N_131_i N_277_i ahigh_c_29__n N_64_0 \ -N_91_0 ahigh_c_30__n N_159_0 N_14 N_85_i N_15 ahigh_c_31__n \ -un1_SM_AMIGA_0_sqmuxa_1_0 N_24 RW_c_i N_25 pos_clk_rw_000_int_5_0_n \ -clk_000_d_i_3__n N_25_i N_28_0 N_24_i N_27_0 ipl_c_i_1__n N_50_0 ipl_c_i_0__n \ -N_49_0 N_14_i N_39_0 N_15_i N_38_0 N_91_0_1 N_91_0_2 N_91_0_3 N_265_i_1 \ -N_266_i_1 N_266_i_2 N_138_i_1 N_148_i_1 N_144_i_1 N_142_i_1 N_140_i_1 \ -pos_clk_un10_sm_amiga_i_1_n N_76 N_85_i_1 N_85_i_2 a_decode_c_16__n N_277_1 \ -N_277_2 un1_rst_2_1 a_decode_c_17__n N_277_3 N_277_4 N_64 a_decode_c_18__n \ -N_277_5 N_122 un10_ciin_1 N_123 a_decode_c_19__n un10_ciin_2 N_132 un10_ciin_3 \ -N_133 a_decode_c_20__n un10_ciin_4 N_274 un10_ciin_5 N_276 a_decode_c_21__n \ -un10_ciin_6 N_77 un10_ciin_7 N_79 a_decode_c_22__n un10_ciin_8 N_78 \ -un10_ciin_9 N_263 a_decode_c_23__n un10_ciin_10 N_108 un10_ciin_11 N_114 \ -a_c_0__n un6_amiga_bus_data_dir_1 N_85 un6_amiga_bus_data_dir_2 N_104 a_c_1__n \ -pos_clk_as_000_dma6_1_n N_91 pos_clk_as_000_dma6_2_n N_131 nEXP_SPACE_c \ -DS_000_DMA_1_sqmuxa_1 N_277 pos_clk_un4_rw_000_1_n N_130 BERR_c \ -pos_clk_un4_rw_000_2_n N_115 pos_clk_un13_clk_out_int_1_n N_116 BG_030_c \ -N_125_1 N_105 N_116_1 N_103 pos_clk_un29_clk_000_ne_1_1_n N_101 \ -pos_clk_un29_clk_000_ne_1_2_n N_259 pos_clk_un29_clk_000_ne_1_3_n N_255 \ -BGACK_000_c N_261_1 N_256 N_261_2 N_254 CLK_030_c N_262_1 N_16 N_262_2 N_106 \ -DS_000_ENABLE_0_sqmuxa_1_1 N_86 N_259_1 N_107 CLK_OSZI_c N_250_i_1 N_117 \ -N_189_i_1 pos_clk_a0_dma_3_n pos_clk_un6_bg_030_1_n N_129 N_108_1 \ -pos_clk_size_dma_6_1__n N_114_1 pos_clk_size_dma_6_0__n un21_berr_1 \ -pos_clk_rw_000_dma_3_n FPU_SENSE_c un21_fpu_cs_1 \ -pos_clk_amiga_bus_enable_dma_low_3_n N_130_1 \ -pos_clk_amiga_bus_enable_dma_high_3_n N_136_i_1 SIZE_DMA_3_sqmuxa N_152_i_1 \ -pos_clk_un5_bgack_030_int_d_n N_146_i_1 N_18 N_267_i_1 N_19 pos_clk_ipl_1_n \ -N_21 bg_000_0_un3_n N_22 ipl_c_0__n bg_000_0_un1_n un6_amiga_bus_data_dir \ -bg_000_0_un0_n un12_amiga_bus_data_dir_m ipl_c_1__n uds_000_int_0_un3_n \ -pos_clk_un3_clk_out_int_n uds_000_int_0_un1_n N_3 ipl_c_2__n \ -uds_000_int_0_un0_n pos_clk_as_000_dma6_n lds_000_int_0_un3_n \ -DS_000_DMA_1_sqmuxa lds_000_int_0_un1_n N_4 DTACK_c lds_000_int_0_un0_n \ -AS_000_DMA_1_sqmuxa ds_000_enable_0_un3_n un1_rst_2 ds_000_enable_0_un1_n \ -ds_000_enable_0_un0_n N_199 VPA_c ipl_030_0_2__un3_n \ -pos_clk_un13_bgack_030_int_n ipl_030_0_2__un1_n N_205 ipl_030_0_2__un0_n \ -pos_clk_un13_clk_out_int_n RST_c vma_int_0_un3_n pos_clk_un15_bgack_030_int_n \ -vma_int_0_un1_n pos_clk_un3_n RESET_c vma_int_0_un0_n \ -pos_clk_un12_clk_out_int_n cpu_est_0_1__un3_n pos_clk_un1_bgack_030_int_n RW_c \ -cpu_est_0_1__un1_n DS_000_DMA_0_sqmuxa cpu_est_0_1__un0_n un1_rst_3 fc_c_0__n \ -cpu_est_0_2__un3_n cpu_est_0_2__un1_n fc_c_1__n cpu_est_0_2__un0_n \ -cpu_est_0_3__un3_n pos_clk_un4_rw_000_n cpu_est_0_3__un1_n N_7 \ -AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un0_n pos_clk_un6_bgack_000_n \ -pos_clk_un31_clk_000_ne_1_i_m2_un3_n pos_clk_un4_bgack_000_n \ -pos_clk_un31_clk_000_ne_1_i_m2_un1_n N_265_2 \ -pos_clk_un31_clk_000_ne_1_i_m2_un0_n N_111 bgack_030_int_0_un3_n N_109 \ -BG_030_c_i bgack_030_int_0_un1_n N_113 pos_clk_un6_bg_030_i_n \ -bgack_030_int_0_un0_n N_112 pos_clk_un9_bg_030_0_n ds_000_dma_0_un3_n N_98 \ -UDS_000_INT_i ds_000_dma_0_un1_n pos_clk_un29_clk_000_ne_1_n un1_UDS_000_INT_0 \ -ds_000_dma_0_un0_n N_87 LDS_000_INT_i as_000_dma_0_un3_n N_270 \ -un1_LDS_000_INT_0 as_000_dma_0_un1_n N_134 N_23_i as_000_dma_0_un0_n N_125 \ -N_30_0 size_dma_0_1__un3_n N_124 N_20_i size_dma_0_1__un1_n N_121 N_33_0 \ -size_dma_0_1__un0_n N_120 N_13_i size_dma_0_0__un3_n N_137 N_40_0 \ -size_dma_0_0__un1_n pos_clk_un31_clk_000_ne_n ipl_c_i_2__n size_dma_0_0__un0_n \ -N_17 N_51_0 amiga_bus_enable_dma_high_0_un3_n pos_clk_un9_clk_000_pe_n N_26_i \ -amiga_bus_enable_dma_high_0_un1_n cpu_est_2_1__n N_29_0 \ -amiga_bus_enable_dma_high_0_un0_n cpu_est_2_2__n a_c_i_0__n \ -amiga_bus_enable_dma_low_0_un3_n N_261 size_c_i_1__n \ -amiga_bus_enable_dma_low_0_un1_n N_262 pos_clk_un10_sm_amiga_i_n \ -amiga_bus_enable_dma_low_0_un0_n N_251 DS_000_ENABLE_0_sqmuxa_1_i \ -a0_dma_0_un3_n N_252 un1_DS_000_ENABLE_0_sqmuxa_i a0_dma_0_un1_n N_258 N_157_i \ -a0_dma_0_un0_n N_257 N_160_0 rw_000_dma_0_un3_n DS_000_ENABLE_1_sqmuxa N_161_0 \ -rw_000_dma_0_un1_n un1_DS_000_ENABLE_0_sqmuxa N_162_0 rw_000_dma_0_un0_n N_102 \ -N_165_i ipl_030_0_0__un3_n N_118 ipl_030_0_0__un1_n N_119 N_167_i \ -ipl_030_0_0__un0_n N_264 N_166_i ipl_030_0_1__un3_n DS_000_ENABLE_0_sqmuxa_1 \ -ipl_030_0_1__un1_n N_164 N_168_i ipl_030_0_1__un0_n N_170 \ -as_030_000_sync_0_un3_n N_168 N_170_i as_030_000_sync_0_un1_n N_166 \ -as_030_000_sync_0_un0_n N_167 N_164_i rw_000_int_0_un3_n N_165 \ -rw_000_int_0_un1_n N_162 N_102_i rw_000_int_0_un0_n N_161 N_264_i \ -a_decode_15__n N_160 N_79_i N_157 N_78_i a_decode_14__n N_26 N_119_i N_13 \ -N_118_i a_decode_13__n N_20 N_23 N_255_i a_decode_12__n N_8 N_257_i \ -pos_clk_un9_bg_030_n cpu_est_2_0_2__n a_decode_11__n \ -un1_amiga_bus_enable_low_i N_258_i un21_fpu_cs_i N_259_i a_decode_10__n \ -sm_amiga_i_2__n cpu_est_2_0_1__n sm_amiga_i_1__n N_262_i a_decode_9__n \ -sm_amiga_i_3__n N_261_i sm_amiga_i_4__n pos_clk_un9_clk_000_pe_0_n \ -a_decode_8__n sm_amiga_i_6__n N_251_i sm_amiga_i_5__n N_252_0 a_decode_7__n \ -clk_000_d_i_0__n N_76_i AS_000_INT_i N_17_i a_decode_6__n sm_amiga_i_i_7__n \ -N_36_0 AS_030_i N_98_i a_decode_5__n cpu_est_i_2__n \ -pos_clk_un31_clk_000_ne_i_n cpu_est_i_0__n N_228_i a_decode_4__n \ -cpu_est_i_3__n N_121_i cpu_est_i_1__n N_120_i a_decode_3__n AS_030.OE \ -AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ -AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ -AHIGH_31_.OE A_0_.OE BERR.OE DTACK.OE RW.OE DS_030.OE DSACK1.OE CIIN.OE G_122 \ -G_123 G_124 cpu_est_0_0_ G_97 G_95 G_101 G_103 -.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ +inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ +RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c \ +N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n N_42_0 \ +vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n \ +DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i \ +un1_UDS_000_INT N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i \ +un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n LDS_000_INT_i \ +un21_fpu_cs un1_LDS_000_INT_0 un21_berr ahigh_c_29__n UDS_000_INT_i un2_ds_030 \ +un1_UDS_000_INT_0 ahigh_c_30__n N_96_0_1 N_96_0_2 ahigh_c_31__n N_282_0_1 \ +N_282_0_2 N_282_0_3 N_282_0_4 pos_clk_un10_sm_amiga_i_1_n un10_ciin_1 \ +un10_ciin_2 un10_ciin_3 un10_ciin_4 un10_ciin_5 un10_ciin_6 un10_ciin_7 \ +un10_ciin_8 un10_ciin_9 un10_ciin_10 un10_ciin_11 N_201_1 N_201_2 N_131_i_1 \ +N_134_0_1 N_113_i_1 N_113_i_2 N_144_1 pos_clk_ipl_n N_144_2 N_143_1 N_143_2 \ +N_163_1 N_163_2 N_163_3 un21_fpu_cs_1 a_decode_c_16__n un21_berr_1_0 \ +pos_clk_cycle_dma_5_1_1__n a_decode_c_17__n N_199_1 AS_000_DMA_1_sqmuxa_1 \ +a_decode_c_18__n N_140_1 N_66_i_1 a_decode_c_19__n N_66_i_2 N_205_i_1 \ +a_decode_c_20__n N_205_i_2 N_180_1 a_decode_c_21__n N_180_2 \ +pos_clk_un9_clk_000_pe_n N_59_i_1 a_decode_c_22__n N_127_i_1 N_123_i_1 \ +a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n \ +N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 BERR_c \ +pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ +ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ +BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c lds_000_int_0_un3_n \ +lds_000_int_0_un1_n lds_000_int_0_un0_n as_030_d1_0_un3_n as_030_d1_0_un1_n \ +as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n rw_000_int_0_un1_n \ +rw_000_int_0_un0_n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ +as_030_000_sync_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n \ +cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n \ +cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ +cpu_est_0_1__un0_n ipl_c_2__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n N_60 \ +cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 cpu_est_0_3__un1_n \ +N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ +ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ +ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ +ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n \ +N_107 fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 \ +fc_c_1__n vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ +AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ +a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i \ +N_149 a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i \ +N_165 N_262_i a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n \ +a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 \ +a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 \ +pos_clk_un9_bg_030_0_n N_267 N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i \ +a_decode_3__n N_191 N_25_0 N_201 N_15_i a_decode_2__n N_202 N_26_0 N_203 \ +N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 un21_berr_1 N_5_i N_132 N_30_0 \ +N_96 a_c_i_0__n N_129 size_c_i_1__n un1_SM_AMIGA_0_sqmuxa_1 \ +pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 \ +N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i N_274 \ +un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i N_11 \ +pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 \ +N_168_i N_17 N_167_i pos_clk_un9_bg_030_n N_170_i N_3 N_169_i N_205 \ +AS_000_DMA_1_sqmuxa N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 \ +pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 \ +N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i \ +BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i \ +N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n UDS_000_c_i DS_000_DMA_i \ +N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i \ +un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i a_decode_i_18__n N_202_i \ +a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n \ +N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i sm_amiga_i_i_7__n N_72_i \ +AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i sm_amiga_i_1__n \ +N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i \ +VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n N_185_i \ +clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i cpu_est_i_2__n \ +DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i ahigh_i_30__n \ +ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n ahigh_i_29__n \ +N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ +ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i \ +N_189_i cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i \ +N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c \ +N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n \ +N_20_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ +SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ +AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ +DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 -.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +.names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D 11 1 -.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +.names N_115_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 -.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +.names N_113_i_1.BLIF N_113_i_2.BLIF SM_AMIGA_1_.D 11 1 -.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +.names N_111_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D 11 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +.names N_21_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_22_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_23_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_41_0.BLIF IPL_D0_0_.D +0 1 +.names N_42_0.BLIF IPL_D0_1_.D +0 1 +.names N_43_0.BLIF IPL_D0_2_.D +0 1 +.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names N_136_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D +0 1 +.names N_66_i_1.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.D +11 1 +.names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D +11 1 +.names N_190_i.BLIF N_191_i.BLIF cpu_est_0_.D +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D 1- 1 -1 1 -.names N_27_0.BLIF IPL_030DFF_0_reg.D +.names N_151.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names N_28_0.BLIF IPL_030DFF_1_reg.D +.names N_44_0.BLIF inst_VPA_D.D 0 1 -.names N_29_0.BLIF IPL_030DFF_2_reg.D +.names N_45_0.BLIF inst_DTACK_D0.D 0 1 -.names N_49_0.BLIF IPL_D0_0_.D -0 1 -.names N_50_0.BLIF IPL_D0_1_.D -0 1 -.names N_51_0.BLIF IPL_D0_2_.D -0 1 -.names G_95.BLIF un1_rst_2.BLIF CYCLE_DMA_0_.D +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names G_97.BLIF un1_rst_2.BLIF CYCLE_DMA_1_.D +.names N_25_0.BLIF BG_000DFFreg.D +0 1 +.names N_26_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_27_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_28_0.BLIF inst_RW_000_INT.D +0 1 +.names N_29_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names N_30_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_31_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_32_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_167_i.BLIF N_168_i.BLIF inst_DSACK1_INT.D 11 1 -.names G_101.BLIF un1_rst_3.BLIF CLK_030_PE_0_.D +.names N_169_i.BLIF N_170_i.BLIF inst_AS_000_INT.D 11 1 -.names G_103.BLIF un1_rst_3.BLIF CLK_030_PE_1_.D -11 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +.names N_35_0.BLIF inst_AMIGA_DS.D +0 1 +.names N_36_0.BLIF inst_A0_DMA.D +0 1 +.names N_126.BLIF inst_RW_000_DMA.D +0 1 +.names N_38_0.BLIF inst_AS_030_D0.D +0 1 +.names N_150.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D 1- 1 -1 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D +.names N_24_0.BLIF inst_UDS_000_INT.D 0 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names N_267_i_1.BLIF RST_c.BLIF RST_DLY_0_.D -11 1 -.names N_266_i_1.BLIF N_266_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_265_i_1.BLIF N_265_2_0.BLIF RST_DLY_2_.D -11 1 -.names N_43_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_120_i.BLIF N_121_i.BLIF inst_DSACK1_INT.D -11 1 -.names N_118_i.BLIF N_119_i.BLIF inst_AS_000_INT.D -11 1 -.names N_46_0.BLIF inst_AMIGA_DS.D -0 1 -.names N_274.BLIF inst_AS_030_D0.D -0 1 -.names N_48_0.BLIF inst_DTACK_D0.D -0 1 -.names N_52_0.BLIF inst_VPA_D.D -0 1 -.names N_53_0.BLIF inst_RESET_OUT.D -0 1 -.names N_8.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_30_0.BLIF BG_000DFFreg.D -0 1 -.names N_31_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names N_33_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_34_0.BLIF inst_A0_DMA.D -0 1 -.names N_35_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_36_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_38_0.BLIF inst_RW_000_INT.D -0 1 -.names N_39_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_40_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_41_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names N_42_0.BLIF inst_AS_000_DMA.D -0 1 -.names un1_rst_2_1.BLIF inst_BGACK_030_INT_D.D +.names N_220_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_125.BLIF N_125_i -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_124.BLIF N_124_i -0 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_124_i.BLIF N_125_i.BLIF N_53_0 +.names N_20_i.BLIF RST_c.BLIF N_23_0 11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n +.names N_19.BLIF N_19_i 0 1 -.names N_134.BLIF N_134_i -0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names N_134_i.BLIF RST_c.BLIF N_270_0 +.names N_19_i.BLIF RST_c.BLIF N_22_0 11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n +.names N_18.BLIF N_18_i 0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_77_i +.names N_18_i.BLIF RST_c.BLIF N_21_0 11 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i +.names ipl_c_2__n.BLIF ipl_c_i_2__n 0 1 -.names N_76_i.BLIF SM_AMIGA_1_.BLIF N_87_i +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 11 1 -.names N_137.BLIF N_137_i_0 -0 1 -.names N_112.BLIF N_112_i +.names ipl_c_1__n.BLIF ipl_c_i_1__n 0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +11 1 .names vcc_n_n 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i +.names ipl_c_0__n.BLIF ipl_c_i_0__n 0 1 -.names N_113.BLIF N_113_i -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_114.BLIF N_114_i +.names un5_e_0.BLIF un5_e 0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 +11 1 .names gnd_n_n -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +.names DTACK_c.BLIF DTACK_c_i 0 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_109.BLIF N_109_i -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 +.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_108.BLIF N_108_i -0 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT -0 1 -.names CLK_030_PE_1_.BLIF clk_030_pe_i_1__n -0 1 -.names N_111.BLIF N_111_i +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 +11 1 +.names VPA_c.BLIF VPA_c_i 0 1 .names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names DS_000_DMA_0_sqmuxa.BLIF DS_000_DMA_0_sqmuxa_i -0 1 -.names N_111_i.BLIF RST_c.BLIF N_265_2_0 +.names RST_c.BLIF VPA_c_i.BLIF N_44_0 11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names pos_clk_un4_rw_000_n.BLIF pos_clk_un4_rw_000_i_n +.names N_13.BLIF N_13_i 0 1 +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa +0 1 +.names N_13_i.BLIF RST_c.BLIF N_27_0 +11 1 .names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names AS_000_c.BLIF AS_000_i +.names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +.names un21_fpu_cs_1.BLIF N_282_0.BLIF un21_fpu_cs 11 1 -.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names inst_AMIGA_DS.BLIF AMIGA_DS_i -0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +.names un21_berr_1_0.BLIF N_282_0.BLIF un21_berr 11 1 -.names pos_clk_un3_clk_out_int_n.BLIF pos_clk_un3_clk_out_int_i_n +.names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF un13_ciin +.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_96_0_1 11 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_48_0 +.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_96_0_2 11 1 -.names pos_clk_as_000_dma6_n.BLIF pos_clk_as_000_dma6_i_n -0 1 -.names N_276.BLIF RESET_c.BLIF un3_ahigh_i +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_282_0_1 11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names pos_clk_un4_bgack_000_n.BLIF pos_clk_un4_bgack_000_i_n -0 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP_i -0 1 -.names BGACK_000_c.BLIF pos_clk_un4_bgack_000_i_n.BLIF \ -pos_clk_un6_bgack_000_0_n +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_282_0_2 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_7.BLIF N_7_i -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_7_i.BLIF RST_c.BLIF N_41_0 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_282_0_3 11 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names RW_000_i.BLIF pos_clk_un15_bgack_030_int_i_n.BLIF \ -pos_clk_un1_bgack_030_int_0_n -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names CLK_030_PE_0_.BLIF CLK_030_PE_1_.BLIF pos_clk_un12_clk_out_int_0_n -11 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un3_0_n -11 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un15_bgack_030_int_i_n -11 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_3.BLIF N_3_i -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names N_3_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names N_4.BLIF N_4_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names N_4_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names un6_amiga_bus_data_dir.BLIF un6_amiga_bus_data_dir_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names un12_amiga_bus_data_dir_m.BLIF un12_amiga_bus_data_dir_m_i -0 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names un6_amiga_bus_data_dir_i.BLIF un12_amiga_bus_data_dir_m_i.BLIF \ -AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names N_22.BLIF N_22_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names N_21.BLIF N_21_i -0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_21_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_19.BLIF N_19_i -0 1 -.names G_122.BLIF N_224_i -0 1 -.names N_19_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names G_123.BLIF N_225_i -0 1 -.names N_18.BLIF N_18_i -0 1 -.names G_124.BLIF N_226_i -0 1 -.names N_18_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -pos_clk_un5_bgack_030_int_d_i_n -11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF \ -pos_clk_amiga_bus_enable_dma_high_3_0_n -11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF \ -pos_clk_amiga_bus_enable_dma_low_3_0_n -11 1 -.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n -11 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n -11 1 -.names un13_ciin.BLIF un13_ciin_i -0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names N_123.BLIF N_123_i -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_86_i -11 1 -.names N_122.BLIF N_122_i -0 1 -.names N_129.BLIF N_129_i -0 1 -.names un7_as_030.BLIF un7_as_030_i -0 1 -.names N_130.BLIF N_130_i -0 1 -.names N_129_i.BLIF N_130_i.BLIF un11_amiga_bus_enable_high_i -11 1 -.names N_117.BLIF N_117_i -0 1 -.names N_117_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_107.BLIF N_107_i -0 1 -.names N_107_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_106.BLIF N_106_i -0 1 -.names N_106_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names N_16.BLIF N_16_i -0 1 -.names N_254.BLIF N_254_i -0 1 -.names N_263.BLIF N_263_i -0 1 -.names N_250_i_1.BLIF N_263_i.BLIF N_250_i -11 1 -.names N_256.BLIF N_256_i -0 1 -.names N_189_i_1.BLIF N_263_i.BLIF N_189_i -11 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_101.BLIF N_101_i -0 1 -.names N_103.BLIF N_103_i -0 1 -.names N_104.BLIF N_104_i -0 1 -.names N_105.BLIF N_105_i -0 1 -.names N_115.BLIF N_115_i -0 1 -.names N_116.BLIF N_116_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names N_277.BLIF N_277_i -0 1 -.names N_131_i.BLIF N_277_i.BLIF N_64_0 -11 1 -.names N_91_0_3.BLIF nEXP_SPACE_c.BLIF N_91_0 -11 1 -.names N_104_i.BLIF SM_AMIGA_i_7_.BLIF N_159_0 -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_14 -1- 1 --1 1 -.names N_85_i_1.BLIF N_85_i_2.BLIF N_85_i -11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_15 -1- 1 --1 1 -.names N_79.BLIF N_159_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_24 -1- 1 --1 1 -.names RW_c.BLIF RW_c_i -0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_25 -1- 1 --1 1 -.names N_159_0.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n -11 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_3__n -0 1 -.names N_25.BLIF N_25_i -0 1 -.names N_25_i.BLIF RST_c.BLIF N_28_0 -11 1 -.names N_24.BLIF N_24_i -0 1 -.names N_24_i.BLIF RST_c.BLIF N_27_0 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 -11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 -11 1 -.names N_14.BLIF N_14_i -0 1 -.names N_14_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names N_15.BLIF N_15_i -0 1 -.names N_15_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names inst_BGACK_030_INT_D.BLIF inst_BGACK_030_INTreg.BLIF N_91_0_1 -11 1 -.names AS_030_D0_i.BLIF sm_amiga_i_i_7__n.BLIF N_91_0_2 -11 1 -.names N_91_0_1.BLIF N_91_0_2.BLIF N_91_0_3 -11 1 -.names N_108_i.BLIF N_109_i.BLIF N_265_i_1 -11 1 -.names N_112_i.BLIF RST_c.BLIF N_266_i_1 -11 1 -.names N_113_i.BLIF N_114_i.BLIF N_266_i_2 -11 1 -.names N_164_i.BLIF N_264.BLIF N_138_i_1 -11 1 -.names N_79.BLIF N_170_i.BLIF N_148_i_1 -11 1 -.names N_78.BLIF N_168_i.BLIF N_144_i_1 -11 1 -.names N_166_i.BLIF N_167_i.BLIF N_142_i_1 -11 1 -.names N_165_i.BLIF N_264_i.BLIF N_140_i_1 +.names N_282_0_1.BLIF N_282_0_2.BLIF N_282_0_4 11 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_76_i.BLIF N_76 -0 1 -.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF N_85_i_1 -11 1 -.names CLK_000_D_4_.BLIF clk_000_d_i_3__n.BLIF N_85_i_2 -11 1 -.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_277_1 -11 1 -.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_277_2 -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF un1_rst_2_1 -11 1 -.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_277_3 -11 1 -.names N_277_1.BLIF N_277_2.BLIF N_277_4 -11 1 -.names N_64_0.BLIF N_64 -0 1 -.names N_277_3.BLIF fc_c_0__n.BLIF N_277_5 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_122 -11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_123 -11 1 .names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names N_276.BLIF inst_RESET_OUT.BLIF N_132 -11 1 .names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_133 -11 1 .names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_274 -11 1 .names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_276 -11 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names N_77_i.BLIF N_77 -0 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names N_79_i.BLIF N_79 -0 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names N_78_i.BLIF N_78 -0 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_263 -11 1 .names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 -.names N_108_1.BLIF rst_dly_i_2__n.BLIF N_108 -11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names N_114_1.BLIF rst_dly_i_1__n.BLIF N_114 +.names N_80_i.BLIF N_82_i.BLIF N_201_1 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF un6_amiga_bus_data_dir_1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_201_2 11 1 -.names N_85_i.BLIF N_85 +.names BERR_c.BLIF N_201_i.BLIF N_131_i_1 +11 1 +.names N_68_i.BLIF N_131.BLIF N_134_0_1 +11 1 +.names N_68.BLIF N_141_i.BLIF N_113_i_1 +11 1 +.names N_142_i.BLIF RST_c.BLIF N_113_i_2 +11 1 +.names N_68_i.BLIF N_208.BLIF N_144_1 +11 1 +.names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n +11 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_144_2 +11 1 +.names N_72_i.BLIF N_82_i.BLIF N_143_1 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_143_2 +11 1 +.names AS_030_D1_i.BLIF inst_BGACK_030_INT_D.BLIF N_163_1 +11 1 +.names N_282.BLIF sm_amiga_i_i_7__n.BLIF N_163_2 +11 1 +.names N_163_1.BLIF N_163_2.BLIF N_163_3 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +11 1 +.names AS_000_i.BLIF N_220_i.BLIF pos_clk_cycle_dma_5_1_1__n +11 1 +.names N_68_i.BLIF CYCLE_DMA_0_.BLIF N_199_1 +11 1 +.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 +11 1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_140_1 +11 1 +.names AS_000_i.BLIF N_198_i.BLIF N_66_i_1 +11 1 +.names N_199_i.BLIF N_220_i.BLIF N_66_i_2 +11 1 +.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_205_i_1 +11 1 +.names N_140_i.BLIF pos_clk_un2_n.BLIF N_205_i_2 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_1 +11 1 +.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_180_2 +11 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF un6_amiga_bus_data_dir_2 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_59_i_1 11 1 -.names N_78_i.BLIF SM_AMIGA_0_.BLIF N_104 +.names N_267_i.BLIF N_268_i.BLIF N_127_i_1 11 1 -.names AMIGA_DS_i.BLIF AS_000_i.BLIF pos_clk_as_000_dma6_1_n +.names N_93.BLIF N_266_i.BLIF N_123_i_1 11 1 -.names N_91_0.BLIF N_91 -0 1 -.names pos_clk_un1_bgack_030_int_n.BLIF pos_clk_un3_n.BLIF \ -pos_clk_as_000_dma6_2_n +.names N_68.BLIF N_186_i.BLIF N_121_i_1 11 1 -.names AS_030_i.BLIF N_91.BLIF N_131 +.names N_72.BLIF N_185_i.BLIF N_119_i_1 11 1 -.names DS_000_DMA_0_sqmuxa_i.BLIF pos_clk_as_000_dma6_n.BLIF \ -DS_000_DMA_1_sqmuxa_1 -11 1 -.names N_277_4.BLIF N_277_5.BLIF N_277 -11 1 -.names CLK_030_PE_0_.BLIF clk_030_pe_i_1__n.BLIF pos_clk_un4_rw_000_1_n -11 1 -.names N_130_1.BLIF AS_030_i.BLIF N_130 -11 1 -.names CLK_030_c.BLIF RW_000_i.BLIF pos_clk_un4_rw_000_2_n -11 1 -.names N_270.BLIF RST_DLY_0_.BLIF N_115 -11 1 -.names pos_clk_un12_clk_out_int_n.BLIF AS_000_DMA_i.BLIF \ -pos_clk_un13_clk_out_int_1_n -11 1 -.names N_116_1.BLIF RST_c.BLIF N_116 -11 1 -.names N_76_i.BLIF N_137.BLIF N_125_1 -11 1 -.names N_79.BLIF sm_amiga_i_5__n.BLIF N_105 -11 1 -.names N_76.BLIF rst_dly_i_0__n.BLIF N_116_1 -11 1 -.names N_85.BLIF sm_amiga_i_i_7__n.BLIF N_103 -11 1 -.names cpu_est_i_2__n.BLIF VMA_INT_i.BLIF pos_clk_un29_clk_000_ne_1_1_n -11 1 -.names N_87.BLIF sm_amiga_i_0__n.BLIF N_101 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF pos_clk_un29_clk_000_ne_1_2_n -11 1 -.names N_259_1.BLIF cpu_est_i_3__n.BLIF N_259 -11 1 -.names pos_clk_un29_clk_000_ne_1_1_n.BLIF pos_clk_un29_clk_000_ne_1_2_n.BLIF \ -pos_clk_un29_clk_000_ne_1_3_n -11 1 -.names N_251.BLIF cpu_est_2_.BLIF N_255 -11 1 -.names N_78_i.BLIF N_263.BLIF N_261_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_2__n.BLIF N_256 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_261_2 -11 1 -.names N_252.BLIF cpu_est_2_.BLIF N_254 -11 1 -.names N_76_i.BLIF N_251_i.BLIF N_262_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_2__n.BLIF N_16 -11 1 -.names N_263.BLIF VPA_D_i.BLIF N_262_2 -11 1 -.names BGACK_030_INT_i.BLIF N_86_i.BLIF N_106 -11 1 -.names N_78_i.BLIF RW_c.BLIF DS_000_ENABLE_0_sqmuxa_1_1 -11 1 -.names N_86_i.BLIF N_86 -0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_259_1 -11 1 -.names BGACK_030_INT_i.BLIF N_86.BLIF N_107 -11 1 -.names N_16_i.BLIF N_254_i.BLIF N_250_i_1 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_117 -11 1 -.names N_255_i.BLIF N_256_i.BLIF N_189_i_1 -11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_129 -11 1 -.names N_77.BLIF N_228_i.BLIF N_108_1 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names N_228_i.BLIF rst_dly_i_0__n.BLIF N_114_1 -11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names N_277.BLIF BGACK_000_c.BLIF un21_berr_1 -11 1 -.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n -0 1 -.names N_277.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 -11 1 -.names pos_clk_amiga_bus_enable_dma_low_3_0_n.BLIF \ -pos_clk_amiga_bus_enable_dma_low_3_n -0 1 -.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_130_1 -11 1 -.names pos_clk_amiga_bus_enable_dma_high_3_0_n.BLIF \ -pos_clk_amiga_bus_enable_dma_high_3_n -0 1 -.names N_78.BLIF N_101_i.BLIF N_136_i_1 -11 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF SIZE_DMA_3_sqmuxa -11 1 -.names N_103_i.BLIF N_104_i.BLIF N_152_i_1 -11 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names N_76.BLIF N_105_i.BLIF N_146_i_1 -11 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_18 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_115_i.BLIF N_116_i.BLIF N_267_i_1 +.names N_183_i.BLIF N_184_i.BLIF N_117_i_1 11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_19 +.names N_72.BLIF N_182_i.BLIF N_115_i_1 +11 1 +.names N_72.BLIF N_181_i.BLIF N_111_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_165_1 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_162_1 11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_21 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_148_1 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_18 1- 1 -1 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_19 +1- 1 +-1 1 +.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n 0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_22 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_20 1- 1 -1 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +.names inst_DS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 -.names un6_amiga_bus_data_dir_1.BLIF un6_amiga_bus_data_dir_2.BLIF \ -un6_amiga_bus_data_dir +.names N_205.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF un12_amiga_bus_data_dir_m +.names N_205.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 .names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF pos_clk_un3_clk_out_int_n -11 1 .names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 .names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names pos_clk_as_000_dma6_1_n.BLIF pos_clk_as_000_dma6_2_n.BLIF \ -pos_clk_as_000_dma6_n +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 .names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names DS_000_DMA_1_sqmuxa_1.BLIF pos_clk_un4_rw_000_i_n.BLIF \ -DS_000_DMA_1_sqmuxa -11 1 .names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names pos_clk_as_000_dma6_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ -AS_000_DMA_1_sqmuxa -11 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF ds_000_enable_0_un3_n +.names RST_c.BLIF as_030_d1_0_un3_n 0 1 -.names AS_000_i.BLIF un1_rst_2_1.BLIF un1_rst_2 +.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n 11 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa.BLIF \ -ds_000_enable_0_un1_n +.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n 11 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF ds_000_enable_0_un3_n.BLIF \ -ds_000_enable_0_un0_n -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un13_bgack_030_int_n.BLIF N_199 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names N_76_i.BLIF pos_clk_un15_bgack_030_int_n.BLIF \ -pos_clk_un13_bgack_030_int_n +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +rw_000_int_0_un1_n 11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names CLK_030_PE_0_.BLIF pos_clk_un13_clk_out_int_n.BLIF N_205 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names pos_clk_un13_clk_out_int_1_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ -pos_clk_un13_clk_out_int_n -11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +.names N_244.BLIF as_030_000_sync_0_un3_n 0 1 -.names pos_clk_un15_bgack_030_int_i_n.BLIF pos_clk_un15_bgack_030_int_n -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +.names AS_030_c.BLIF N_244.BLIF as_030_000_sync_0_un1_n 11 1 -.names pos_clk_un3_0_n.BLIF pos_clk_un3_n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names pos_clk_un12_clk_out_int_0_n.BLIF pos_clk_un12_clk_out_int_n -0 1 -.names N_76.BLIF cpu_est_0_1__un3_n -0 1 -.names pos_clk_un1_bgack_030_int_0_n.BLIF pos_clk_un1_bgack_030_int_n -0 1 -.names cpu_est_1_.BLIF N_76.BLIF cpu_est_0_1__un1_n -11 1 -.names RW_000_c.BLIF pos_clk_un3_clk_out_int_i_n.BLIF DS_000_DMA_0_sqmuxa -11 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names RST_c.BLIF pos_clk_as_000_dma6_n.BLIF un1_rst_3 -11 1 -.names N_76.BLIF cpu_est_0_2__un3_n -0 1 -.names cpu_est_2_.BLIF N_76.BLIF cpu_est_0_2__un1_n -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_76.BLIF cpu_est_0_3__un3_n -0 1 -.names pos_clk_un4_rw_000_1_n.BLIF pos_clk_un4_rw_000_2_n.BLIF \ -pos_clk_un4_rw_000_n -11 1 -.names cpu_est_3_.BLIF N_76.BLIF cpu_est_0_3__un1_n -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_7 -1- 1 --1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_189_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names inst_VPA_D.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un3_n -0 1 -.names AS_000_c.BLIF N_76_i.BLIF pos_clk_un4_bgack_000_n -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un1_n -11 1 -.names N_265_2_0.BLIF N_265_2 -0 1 -.names pos_clk_un29_clk_000_ne_1_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un3_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un0_n -11 1 -.names N_76.BLIF rst_dly_i_2__n.BLIF N_111 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n 11 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_137.BLIF N_265_2.BLIF N_109 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names N_76.BLIF rst_dly_i_1__n.BLIF N_113 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names N_77_i.BLIF N_134.BLIF N_112 -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 -.names pos_clk_un31_clk_000_ne_1_i_m2_un1_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un0_n.BLIF N_98 -1- 1 --1 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n -11 1 -.names pos_clk_un29_clk_000_ne_1_3_n.BLIF cpu_est_i_1__n.BLIF \ -pos_clk_un29_clk_000_ne_1_n -11 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 -11 1 -.names pos_clk_as_000_dma6_i_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names N_87_i.BLIF N_87 -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names N_270_0.BLIF N_270 -0 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names N_76_i.BLIF N_137_i_0.BLIF N_134 -11 1 -.names N_23.BLIF N_23_i -0 1 -.names pos_clk_as_000_dma6_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names N_125_1.BLIF RST_c.BLIF N_125 -11 1 -.names N_23_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un3_n -0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_124 -11 1 -.names N_20.BLIF N_20_i -0 1 -.names SIZE_DMA_1_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un1_n -11 1 -.names N_87_i.BLIF RST_c.BLIF N_121 -11 1 -.names N_20_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ -size_dma_0_1__un0_n -11 1 -.names DSACK1_INT_i.BLIF N_274.BLIF N_120 -11 1 -.names N_13.BLIF N_13_i -0 1 -.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un3_n -0 1 -.names N_77_i.BLIF RST_DLY_2_.BLIF N_137 -11 1 -.names N_13_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names SIZE_DMA_0_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un1_n -11 1 -.names pos_clk_un31_clk_000_ne_i_n.BLIF pos_clk_un31_clk_000_ne_n -0 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \ -size_dma_0_0__un0_n -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n -0 1 -.names N_26.BLIF N_26_i -0 1 -.names pos_clk_amiga_bus_enable_dma_high_3_n.BLIF \ -pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names N_26_i.BLIF RST_c.BLIF N_29_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names N_68.BLIF cpu_est_0_1__un3_n 0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +.names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n 0 1 -.names N_261_1.BLIF N_261_2.BLIF N_261 +.names cpu_est_1_.BLIF N_68.BLIF cpu_est_0_1__un1_n 11 1 -.names size_c_1__n.BLIF size_c_i_1__n +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_68.BLIF cpu_est_0_2__un3_n 0 1 -.names pos_clk_amiga_bus_enable_dma_low_3_n.BLIF \ -pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n +.names cpu_est_2_.BLIF N_68.BLIF cpu_est_0_2__un1_n 11 1 -.names N_262_1.BLIF N_262_2.BLIF N_262 -11 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names N_251_i.BLIF N_251 +.names N_60_0.BLIF N_60 0 1 -.names DS_000_ENABLE_0_sqmuxa_1.BLIF DS_000_ENABLE_0_sqmuxa_1_i +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_63_0.BLIF N_63 0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +.names N_68.BLIF cpu_est_0_3__un3_n 0 1 -.names N_252_0.BLIF N_252 -0 1 -.names DS_000_ENABLE_0_sqmuxa_1_i.BLIF N_157.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names N_220_i.BLIF RW_000_i.BLIF N_126 11 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -a0_dma_0_un1_n +.names cpu_est_3_.BLIF N_68.BLIF cpu_est_0_3__un1_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_258 +.names a_c_1__n.BLIF N_220_i.BLIF N_150 11 1 -.names N_78_i.BLIF SM_AMIGA_4_.BLIF N_157_i +.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +.names a_i_1__n.BLIF N_220_i.BLIF N_151 11 1 -.names N_251_i.BLIF cpu_est_i_2__n.BLIF N_257 -11 1 -.names N_76_i.BLIF SM_AMIGA_5_.BLIF N_160_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names SM_AMIGA_3_.BLIF pos_clk_un31_clk_000_ne_n.BLIF N_161_0 -11 1 -.names pos_clk_rw_000_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -rw_000_dma_0_un1_n -11 1 -.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa -0 1 -.names N_85_i.BLIF sm_amiga_i_i_7__n.BLIF N_162_0 -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_76.BLIF sm_amiga_i_2__n.BLIF N_102 -11 1 -.names N_165.BLIF N_165_i -0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n 0 1 -.names AS_000_INT_i.BLIF N_274.BLIF N_118 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_219 11 1 .names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n 11 1 -.names N_79_i.BLIF RST_c.BLIF N_119 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_175 11 1 -.names N_167.BLIF N_167_i -0 1 .names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names N_264_i.BLIF N_264 -0 1 -.names N_166.BLIF N_166_i -0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n 0 1 -.names DS_000_ENABLE_0_sqmuxa_1_1.BLIF SM_AMIGA_6_.BLIF \ -DS_000_ENABLE_0_sqmuxa_1 -11 1 +.names N_59_i.BLIF N_59 +0 1 .names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n 11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_164 -11 1 -.names N_168.BLIF N_168_i +.names N_68_i.BLIF N_68 0 1 .names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names N_162.BLIF sm_amiga_i_6__n.BLIF N_170 -11 1 -.names N_64.BLIF as_030_000_sync_0_un3_n +.names N_72_i.BLIF N_72 0 1 -.names N_160.BLIF sm_amiga_i_4__n.BLIF N_168 -11 1 -.names N_170.BLIF N_170_i +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n 0 1 -.names inst_AS_030_000_SYNC.BLIF N_64.BLIF as_030_000_sync_0_un1_n +.names N_80_i.BLIF N_80 +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 -.names N_157.BLIF sm_amiga_i_3__n.BLIF N_166 +.names N_93_i.BLIF N_93 +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +.names N_98_i.BLIF N_98 +0 1 +.names N_63.BLIF ds_000_enable_0_un3_n +0 1 +.names N_107_i.BLIF N_107 +0 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_63.BLIF ds_000_enable_0_un1_n 11 1 -.names N_76_i.BLIF pos_clk_un31_clk_000_ne_n.BLIF N_167 +.names N_128_i.BLIF N_128 +0 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n 11 1 +.names N_131_i.BLIF N_131 +0 1 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names N_134_0.BLIF N_134 +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_135_0.BLIF N_135 +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_72.BLIF SM_AMIGA_2_.BLIF N_141 +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_142 +11 1 +.names N_143_1.BLIF N_143_2.BLIF N_143 +11 1 +.names N_144_1.BLIF N_144_2.BLIF N_144 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_145 +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_146 +11 1 +.names N_205_i_1.BLIF N_205_i_2.BLIF N_205_i +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_147 +11 1 +.names N_140.BLIF N_140_i +0 1 +.names N_148_1.BLIF cpu_est_i_3__n.BLIF N_148 +11 1 +.names inst_AMIGA_DS.BLIF AMIGA_DS_i +0 1 +.names N_98.BLIF cpu_est_2_.BLIF N_149 +11 1 +.names N_98_i.BLIF cpu_est_2_.BLIF N_154 +11 1 +.names N_199.BLIF N_199_i +0 1 +.names N_82_i.BLIF cpu_est_3_.BLIF N_155 +11 1 +.names N_198.BLIF N_198_i +0 1 +.names N_162_1.BLIF cpu_est_i_3__n.BLIF N_162 +11 1 +.names N_180.BLIF N_180_i +0 1 +.names N_165_1.BLIF AS_030_i.BLIF N_165 +11 1 +.names N_262.BLIF N_262_i +0 1 +.names BGACK_030_INT_i.BLIF N_128.BLIF N_259 +11 1 +.names N_180_i.BLIF N_262_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names BGACK_030_INT_i.BLIF N_128_i.BLIF N_260 +11 1 +.names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un2_i_n +11 1 +.names N_129.BLIF sm_amiga_i_0__n.BLIF N_181 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_134.BLIF sm_amiga_i_2__n.BLIF N_182 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names N_68_i.BLIF N_131.BLIF N_183 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_107.BLIF sm_amiga_i_3__n.BLIF N_184 +11 1 +.names N_4_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_135.BLIF sm_amiga_i_4__n.BLIF N_185 +11 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_220_i +11 1 +.names N_93.BLIF sm_amiga_i_5__n.BLIF N_186 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_132.BLIF sm_amiga_i_6__n.BLIF N_266 +11 1 +.names BG_030_c_i.BLIF N_59.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names N_96.BLIF sm_amiga_i_i_7__n.BLIF N_267 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names N_72_i.BLIF SM_AMIGA_0_.BLIF N_268 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_24_0 +11 1 +.names N_68.BLIF cpu_est_i_0__n.BLIF N_190 +11 1 +.names N_16.BLIF N_16_i +0 1 +.names N_68_i.BLIF cpu_est_0_.BLIF N_191 +11 1 +.names N_16_i.BLIF RST_c.BLIF N_25_0 +11 1 +.names N_201_1.BLIF N_201_2.BLIF N_201 +11 1 +.names N_15.BLIF N_15_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_202 +11 1 +.names N_15_i.BLIF RST_c.BLIF N_26_0 +11 1 +.names N_93_i.BLIF RW_c.BLIF N_203 +11 1 +.names N_12.BLIF N_12_i +0 1 +.names N_98_i.BLIF cpu_est_i_2__n.BLIF N_208 +11 1 +.names N_12_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names N_163_3.BLIF un1_dsack1_i.BLIF N_163 +11 1 +.names N_11.BLIF N_11_i +0 1 +.names N_282_0.BLIF N_282 +0 1 +.names N_11_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 +.names N_5.BLIF N_5_i +0 1 +.names N_132_0.BLIF N_132 +0 1 +.names N_5_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_96_0.BLIF N_96 +0 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names N_129_i.BLIF N_129 +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names N_175.BLIF RST_c.BLIF N_169 +11 1 +.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i +11 1 +.names N_93_i.BLIF RST_c.BLIF N_170 +11 1 +.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_69_i +11 1 +.names N_219.BLIF RST_c.BLIF N_167 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names N_129_i.BLIF RST_c.BLIF N_168 +11 1 +.names AS_030_i.BLIF N_163_i.BLIF N_244_0 +11 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 .names N_164.BLIF N_164_i 0 1 -.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names N_161.BLIF sm_amiga_i_2__n.BLIF N_165 -11 1 -.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ -rw_000_int_0_un1_n -11 1 -.names N_162_0.BLIF N_162 +.names N_165.BLIF N_165_i 0 1 -.names N_102.BLIF N_102_i -0 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +.names AS_000_c.BLIF N_68_i.BLIF N_274 11 1 -.names N_161_0.BLIF N_161 -0 1 -.names N_78.BLIF N_102_i.BLIF N_264_i +.names N_164_i.BLIF N_165_i.BLIF un11_amiga_bus_enable_high_i 11 1 -.names N_160_0.BLIF N_160 -0 1 -.names N_78_i.BLIF SM_AMIGA_6_.BLIF N_79_i +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_164 11 1 -.names N_157_i.BLIF N_157 +.names un10_ciin.BLIF un10_ciin_i 0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_78_i +.names N_244_0.BLIF N_244 +0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_60_0 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_26 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 1- 1 -1 1 -.names N_119.BLIF N_119_i +.names N_274.BLIF N_274_i 0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 1- 1 -1 1 -.names N_118.BLIF N_118_i +.names BGACK_000_c.BLIF N_274_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_12 +1- 1 +-1 1 +.names RW_c.BLIF RW_c_i 0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_20 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_15 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_23 +.names N_246_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_16 1- 1 -1 1 -.names N_255.BLIF N_255_i +.names N_168.BLIF N_168_i 0 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_8 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_257.BLIF N_257_i +.names N_167.BLIF N_167_i 0 1 .names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names N_255_i.BLIF N_257_i.BLIF cpu_est_2_0_2__n +.names N_170.BLIF N_170_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names N_169.BLIF N_169_i +0 1 +.names N_205_i.BLIF N_205 +0 1 +.names AS_000_DMA_1_sqmuxa_1.BLIF N_205_i.BLIF AS_000_DMA_1_sqmuxa +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_93.BLIF N_246_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names N_199_1.BLIF cycle_dma_i_1__n.BLIF N_199 +11 1 +.names N_282_0_4.BLIF N_282_0_3.BLIF N_282_0 +11 1 +.names pos_clk_un2_i_n.BLIF pos_clk_un2_n +0 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names N_140_1.BLIF RW_000_i.BLIF N_140 +11 1 +.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_262 +11 1 +.names N_68_i.BLIF SM_AMIGA_1_.BLIF N_129_i +11 1 +.names cycle_dma_i_0__n.BLIF N_68.BLIF N_198 +11 1 +.names N_268.BLIF N_268_i +0 1 +.names N_180_1.BLIF N_180_2.BLIF N_180 +11 1 +.names N_268_i.BLIF SM_AMIGA_i_7_.BLIF N_246_i 11 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names N_258.BLIF N_258_i -0 1 +.names N_96_0.BLIF sm_amiga_i_i_7__n.BLIF N_132_0 +11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names N_259.BLIF N_259_i +.names AS_000_c.BLIF AS_000_i 0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names N_142.BLIF N_142_i 0 1 -.names N_258_i.BLIF N_259_i.BLIF cpu_est_2_0_1__n +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_141.BLIF N_141_i +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_68_i.BLIF SM_AMIGA_5_.BLIF N_135_0 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 -.names N_262.BLIF N_262_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_261.BLIF N_261_i -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names N_261_i.BLIF N_262_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names N_134_0_1.BLIF SM_AMIGA_3_.BLIF N_134_0 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +.names RW_000_c.BLIF RW_000_i 0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_251_i +.names N_131_i_1.BLIF N_202_i.BLIF N_131_i +11 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP_i +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_128_i +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names N_72_i.BLIF SM_AMIGA_4_.BLIF N_107_i +11 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names N_203.BLIF N_203_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_107.BLIF N_203_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_201.BLIF N_201_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_202.BLIF N_202_i +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_98_i +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_72_i.BLIF SM_AMIGA_6_.BLIF N_93_i 11 1 .names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_252_0 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i 11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_76_i +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_80_i 11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_17.BLIF N_17_i -0 1 .names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n 0 1 -.names N_17_i.BLIF RST_c.BLIF N_36_0 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_72_i 11 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names N_98.BLIF N_98_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names BERR_c.BLIF N_98_i.BLIF pos_clk_un31_clk_000_ne_i_n +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_68_i 11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_59_i_1.BLIF nEXP_SPACE_c.BLIF N_59_i +11 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names N_190.BLIF N_190_i +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_191.BLIF N_191_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names inst_AS_030_D1.BLIF AS_030_D1_i +0 1 +.names N_267.BLIF N_267_i +0 1 .names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names N_137_i_0.BLIF RST_c.BLIF N_228_i -11 1 .names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 -.names N_121.BLIF N_121_i +.names N_266.BLIF N_266_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names N_186.BLIF N_186_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names N_120.BLIF N_120_i +.names N_185.BLIF N_185_i 0 1 -.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_122 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names N_183.BLIF N_183_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_184.BLIF N_184_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_182.BLIF N_182_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_181.BLIF N_181_i +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names N_260.BLIF N_260_i +0 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names N_260_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_259.BLIF N_259_i +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_259_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_63_0 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_155.BLIF N_155_i +0 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_162.BLIF N_162_i +0 1 +.names G_105.BLIF N_187_i +0 1 +.names N_155_i.BLIF N_162_i.BLIF un5_e_0 +11 1 +.names G_106.BLIF N_188_i +0 1 +.names N_154.BLIF N_154_i +0 1 +.names G_107.BLIF N_189_i +0 1 +.names N_80.BLIF N_154_i.BLIF cpu_est_2_0_3__n +11 1 +.names N_149.BLIF N_149_i +0 1 +.names N_208.BLIF N_208_i +0 1 +.names N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n +11 1 +.names N_147.BLIF N_147_i +0 1 +.names un2_ds_030.BLIF un2_ds_030_i +0 1 +.names N_148.BLIF N_148_i +0 1 +.names N_219.BLIF N_219_i +0 1 +.names N_147_i.BLIF N_148_i.BLIF cpu_est_2_0_1__n +11 1 +.names N_175.BLIF N_175_i +0 1 +.names N_146.BLIF N_146_i +0 1 +.names un3_as_030.BLIF un3_as_030_i +0 1 +.names N_146_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names N_145.BLIF N_145_i +0 1 +.names N_145_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_143.BLIF N_143_i +0 1 +.names N_144.BLIF N_144_i +0 1 +.names N_143_i.BLIF N_144_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names N_20.BLIF N_20_i +0 1 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_105 01 1 10 1 11 0 00 0 -.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_123 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_106 01 1 10 1 11 0 00 0 -.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_124 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_107 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF N_76.BLIF cpu_est_0_0_ -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_1_.BLIF N_199.BLIF G_97 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_0_.BLIF pos_clk_un13_bgack_030_int_n.BLIF G_95 -01 1 -10 1 -11 0 -00 0 -.names CLK_030_PE_0_.BLIF pos_clk_un13_clk_out_int_n.BLIF G_101 -01 1 -10 1 -11 0 -00 0 -.names CLK_030_PE_1_.BLIF N_205.BLIF G_103 +.names CYCLE_DMA_1_.BLIF N_199.BLIF G_91 01 1 10 1 11 0 @@ -1620,7 +1264,7 @@ rw_000_int_0_un1_n .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 -.names un6_ds_030_i.BLIF DS_030 +.names un2_ds_030_i.BLIF DS_030 1 1 0 0 .names BG_000DFFreg.BLIF BG_000 @@ -1638,13 +1282,13 @@ rw_000_int_0_un1_n .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names N_123_i.BLIF DSACK1 +.names N_219_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_250_i.BLIF E +.names un5_e.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1671,15 +1315,6 @@ rw_000_int_0_un1_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1695,12 +1330,6 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -1719,10 +1348,13 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_000.BLIF CLK_000_D_0_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 .names CLK_000_D_0_.BLIF CLK_000_D_1_.D @@ -1749,37 +1381,67 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_030_PE_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_030_PE_1_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C +.names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C @@ -1794,55 +1456,22 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF inst_AMIGA_DS.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF inst_AS_030_D1.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C @@ -1869,10 +1498,10 @@ rw_000_int_0_un1_n .names gnd_n_n.BLIF AHIGH_31_ 1 1 0 0 -.names un7_as_030_i.BLIF AS_030 +.names un3_as_030_i.BLIF AS_030 1 1 0 0 -.names N_122_i.BLIF AS_000 +.names N_175_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1887,9 +1516,6 @@ rw_000_int_0_un1_n .names gnd_n_n.BLIF BERR 1 1 0 0 -.names gnd_n_n.BLIF DTACK -1 1 -0 0 .names inst_RW_000_DMA.BLIF RW 1 1 0 0 @@ -1920,18 +1546,6 @@ rw_000_int_0_un1_n .names inst_A0_DMA.BLIF A_0_ 1 1 0 0 -.names A_DECODE_2_.BLIF a_decode_2__n -1 1 -0 0 -.names AS_030.PIN.BLIF AS_030_c -1 1 -0 0 -.names AS_000.PIN.BLIF AS_000_c -1 1 -0 0 -.names RW_000.PIN.BLIF RW_000_c -1 1 -0 0 .names UDS_000.PIN.BLIF UDS_000_c 1 1 0 0 @@ -2010,9 +1624,6 @@ rw_000_int_0_un1_n .names BGACK_000.BLIF BGACK_000_c 1 1 0 0 -.names CLK_030.BLIF CLK_030_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -2028,7 +1639,7 @@ rw_000_int_0_un1_n .names IPL_2_.BLIF ipl_c_2__n 1 1 0 0 -.names DTACK.PIN.BLIF DTACK_c +.names DTACK.BLIF DTACK_c 1 1 0 0 .names VPA.BLIF VPA_c @@ -2037,9 +1648,6 @@ rw_000_int_0_un1_n .names RST.BLIF RST_c 1 1 0 0 -.names RESET.BLIF RESET_c -1 1 -0 0 .names RW.PIN.BLIF RW_c 1 1 0 0 @@ -2088,70 +1696,82 @@ rw_000_int_0_un1_n .names A_DECODE_3_.BLIF a_decode_3__n 1 1 0 0 -.names N_132.BLIF AS_030.OE +.names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 -.names un1_as_000_i.BLIF AS_000.OE +.names AS_030.PIN.BLIF AS_030_c 1 1 0 0 -.names un1_as_000_i.BLIF RW_000.OE +.names AS_000.PIN.BLIF AS_000_c 1 1 0 0 -.names un1_as_000_i.BLIF UDS_000.OE +.names RW_000.PIN.BLIF RW_000_c 1 1 0 0 -.names un1_as_000_i.BLIF LDS_000.OE +.names BGACK_030_INT_i.BLIF AS_030.OE 1 1 0 0 -.names N_276.BLIF SIZE_0_.OE +.names N_69_i.BLIF AS_000.OE 1 1 0 0 -.names N_276.BLIF SIZE_1_.OE +.names N_69_i.BLIF RW_000.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_24_.OE +.names N_69_i.BLIF UDS_000.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_25_.OE +.names N_69_i.BLIF LDS_000.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_26_.OE +.names BGACK_030_INT_i.BLIF SIZE_0_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_27_.OE +.names BGACK_030_INT_i.BLIF SIZE_1_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_28_.OE +.names BGACK_030_INT_i.BLIF AHIGH_24_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_29_.OE +.names BGACK_030_INT_i.BLIF AHIGH_25_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_30_.OE +.names BGACK_030_INT_i.BLIF AHIGH_26_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_31_.OE +.names BGACK_030_INT_i.BLIF AHIGH_27_.OE 1 1 0 0 -.names N_132.BLIF A_0_.OE +.names BGACK_030_INT_i.BLIF AHIGH_28_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF AHIGH_29_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF AHIGH_30_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF AHIGH_31_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF A_0_.OE 1 1 0 0 .names un21_berr.BLIF BERR.OE 1 1 0 0 -.names AS_000_DMA_i.BLIF DTACK.OE +.names BGACK_030_INT_i.BLIF RW.OE 1 1 0 0 -.names N_133.BLIF RW.OE +.names BGACK_030_INT_i.BLIF DS_030.OE 1 1 0 0 -.names N_132.BLIF DS_030.OE +.names un1_dsack1_i.BLIF DSACK1.OE 1 1 0 0 -.names nEXP_SPACE_c.BLIF DSACK1.OE +.names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 0 0 -.names un13_ciin_i.BLIF CIIN.OE +.names N_60.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 2f15fc4..4899251 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,111 +1,84 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE 68030_tk -#$ PINS 61 A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ \ -# FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE \ -# BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP \ -# FPU_CS FPU_SENSE DSACK1 DTACK AVEC SIZE_0_ E AHIGH_30_ VPA AHIGH_29_ VMA AHIGH_28_ RST \ -# AHIGH_27_ RESET AHIGH_26_ RW AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR \ -# A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ \ -# CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ -#$ NODES 57 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_1_ cpu_est_2_ cpu_est_3_ \ -# cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW \ -# inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA \ -# inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ \ -# inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D \ -# IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT \ -# inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ \ -# SIZE_DMA_0_ SIZE_DMA_1_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ inst_RW_000_INT \ -# inst_RW_000_DMA RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_A0_DMA inst_DSACK1_INT \ -# inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg \ -# CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg +#$ PINS 59 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ \ +# A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ +# IPL_030_2_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 \ +# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 A_0_ BGACK_000 IPL_030_1_ IPL_030_0_ CLK_000 \ +# IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E \ +# VPA VMA RST RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ +#$ NODES 53 inst_BGACK_030_INTreg cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \ +# inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA \ +# inst_VMA_INTreg inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ \ +# CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \ +# CLK_000_D_2_ CLK_000_D_4_ SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA inst_RW_000_DMA \ +# inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D \ +# SM_AMIGA_6_ inst_RW_000_INT SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ \ +# CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ \ +# BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg SM_AMIGA_i_7_ \ +# IPL_030DFF_2_reg N_60 .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ -BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF VPA.BLIF \ -RST.BLIF RESET.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ +BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF \ +RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF \ IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_VMA_INTreg.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ -inst_DS_000_DMA.BLIF inst_VPA_D.BLIF CLK_000_D_3_.BLIF inst_DTACK_D0.BLIF \ -inst_RESET_OUT.BLIF CLK_030_PE_1_.BLIF inst_AMIGA_DS.BLIF CLK_000_D_1_.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +inst_AS_030_D0.BLIF inst_AS_030_D1.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF \ +CLK_000_D_3_.BLIF inst_DTACK_D0.BLIF inst_AMIGA_DS.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.BLIF \ IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF CLK_000_D_2_.BLIF \ -CLK_000_D_4_.BLIF inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \ -inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_0_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF CYCLE_DMA_0_.BLIF \ -CYCLE_DMA_1_.BLIF CLK_030_PE_0_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF \ -RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_A0_DMA.BLIF \ -inst_DSACK1_INT.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF \ -SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF \ -IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF \ -AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ -AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ -AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ -BERR.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF +CLK_000_D_4_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF \ +inst_RW_000_DMA.BLIF inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \ +inst_LDS_000_INT.BLIF inst_BGACK_030_INT_D.BLIF SM_AMIGA_6_.BLIF \ +inst_RW_000_INT.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ +CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_DSACK1_INT.BLIF inst_AS_000_INT.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BG_000DFFreg.BLIF \ +CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \ +SM_AMIGA_i_7_.BLIF IPL_030DFF_2_reg.BLIF N_60.BLIF AS_030.PIN.BLIF \ +AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ +AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ +AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ -SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ -IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ -IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \ -IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_0_.D CLK_000_D_0_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ +IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ +IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ +SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ -CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ -CYCLE_DMA_1_.D CYCLE_DMA_1_.C CLK_030_PE_0_.C CLK_030_PE_1_.D CLK_030_PE_1_.C \ -SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D \ -cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.C \ -RST_DLY_2_.D RST_DLY_2_.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ -inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ -inst_AMIGA_DS.D inst_AMIGA_DS.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_VPA_D.D inst_VPA_D.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ -BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ -AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR DTACK RW SIZE_0_ AHIGH_30_ \ -AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ AS_030.OE \ -AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ -AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ -AHIGH_31_.OE A_0_.OE BERR.OE DTACK.OE RW.OE DS_030.OE DSACK1.OE CIIN.OE \ -cpu_est_2_.D.X1 cpu_est_2_.D.X2 CLK_030_PE_0_.D.X1 CLK_030_PE_0_.D.X2 \ -RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 \ -SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_i_7_.BLIF SM_AMIGA_6_.D -1100--100 1 --1---0-1- 1 --1--1--1- 1 -----01-1- 0 -------00- 0 ----1---0- 0 ---1----0- 0 -0------0- 0 --0------- 0 --------01 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -1011- 1 -1-1-1 1 -10--1 1 --10-- 0 -0---- 0 ----00 0 ---0-0 0 --1--0 0 +CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ +SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_D_0_.D CLK_000_D_0_.C \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D \ +inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_DS_000_ENABLE.D \ +inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ +inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D \ +inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C inst_AMIGA_DS.D \ +inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ +inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ +RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_60 AS_030.OE AS_000.OE RW_000.OE \ +UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ +AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE \ +A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE cpu_est_2_.D.X1 \ +cpu_est_2_.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 \ +SM_AMIGA_i_7_.D.X2 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \ SM_AMIGA_5_.BLIF SM_AMIGA_4_.D 1-01- 1 @@ -116,8 +89,8 @@ SM_AMIGA_5_.BLIF SM_AMIGA_4_.D -0-0- 0 0---- 0 ---00 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ +.names RST.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ BERR.PIN.BLIF SM_AMIGA_2_.D 1000100-101-- 1 @@ -156,18 +129,6 @@ SM_AMIGA_0_.BLIF SM_AMIGA_0_.D ---00 0 --1-0 0 -0--0 0 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D -11-110 1 --010-- 1 ---1-0- 1 ---1--1 1 ---00-- 0 -01--10 0 --1-010 0 --0-110 0 ---0-0- 0 ---0--1 0 .names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D 0-01100- 1 @@ -249,6 +210,43 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D 1- 1 -0 1 01 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_i_7_.BLIF SM_AMIGA_6_.D +1100--100 1 +-1---0-1- 1 +-1--1--1- 1 +----01-1- 0 +------00- 0 +---1---0- 0 +--1----0- 0 +0------0- 0 +-0------- 0 +-------01 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +1011- 1 +1-1-1 1 +10--1 1 +-10-- 0 +0---- 0 +---00 0 +--0-0 0 +-1--0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_DMA_0_.D +-01- 1 +0--- 1 +-0-1 1 +1-00 0 +11-- 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_DMA_1_.D +-000 1 +0--- 1 +1-1- 0 +11-- 0 +1--1 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D 10--110 1 @@ -271,42 +269,6 @@ CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D -1----- 0 0------ 0 ------1 0 -.names RST.BLIF inst_AS_000_DMA.BLIF CLK_030_PE_1_.BLIF inst_AMIGA_DS.BLIF \ -inst_CLK_OUT_PRE_D.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF CLK_030_PE_0_.BLIF \ -CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF CLK_030_PE_1_.D -10-01-11001 1 -1-10--1--01 1 -10-0101100- 1 -10-0110100- 1 -1-10-01--0- 1 -1-10-10--0- 1 ------11---0 0 ------00---- 0 ---0-----1-- 0 ---0----0--- 0 ---0-0------ 0 --10-------- 0 ----------1- 0 ----1------- 0 -0---------- 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D --111-- 1 --0--1- 1 -0----- 1 --0---1 1 -10--00 0 -11-0-- 0 -110--- 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D --111-- 1 --0--00 1 -0----- 1 -10--1- 0 -11-0-- 0 -110--- 0 -10---1 0 .names cpu_est_0_.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_0_.D 010 1 10- 1 @@ -314,59 +276,172 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D 110 0 00- 0 0-1 0 -.names cpu_est_1_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF CLK_000_D_1_.BLIF \ +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF cpu_est_1_.D -00110 1 -1-0-- 1 -1--0- 1 -1---1 1 -01--- 0 -1-110 0 -0--0- 0 -0-0-- 0 -0---1 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_0_.D -1--111 1 -1100-- 1 -1-11-- 1 -10-1-- 1 --1010- 0 --101-0 0 ---10-- 0 --0-0-- 0 -0----- 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_2_.D -11011- 1 -1----1 1 -0----- 0 -----00 0 ----0-0 0 ---1--0 0 --0---0 0 -.names CLK_030.BLIF RST.BLIF inst_DS_000_DMA.BLIF CLK_030_PE_1_.BLIF \ -inst_AMIGA_DS.BLIF inst_CLK_OUT_PRE_D.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -CLK_030_PE_0_.BLIF CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ -inst_DS_000_DMA.D ---1--1---0-1 1 ---1-----0--0 1 ---11-------0 1 -0-1--------0 1 -------00---- 1 -------11---0 1 -----------1- 1 -----1------- 1 --0---------- 1 --10-0--1--01 0 -11-00-011-00 0 -11-00-101-00 0 --10-0-01--0- 0 --10-0-10--0- 0 --1--0--1-101 0 --1--0-1--101 0 --1--00-1--01 0 --1--001---01 0 +10010 1 +01--- 1 +-1-0- 1 +-1--1 1 +-01-- 0 +11-10 0 +-0-0- 0 +00--- 0 +-0--1 0 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D +111-10 1 +0--1-- 1 +---10- 1 +---1-1 1 +1-0-10 0 +10--10 0 +---00- 0 +0--0-- 0 +---0-1 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +-1- 1 +0-- 1 +--1 1 +100 0 +.names VPA.BLIF RST.BLIF inst_VPA_D.D +1- 1 +-0 1 +01 0 +.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D +1- 1 +-0 1 +01 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_DS_000_ENABLE.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF RW.PIN.BLIF \ +inst_DS_000_ENABLE.D +101--1-- 1 +101-1--1 1 +1--1--0- 1 +----001- 0 +---000-- 0 +-----010 0 +--0---1- 0 +-1----1- 0 +---0-0-0 0 +--00---- 0 +-1-0---- 0 +0------- 0 +.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ +CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D +----01 1 +---0-1 1 +0----1 1 +--0--- 1 +-1---- 1 +10111- 0 +-01--0 0 +.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D +--1100 1 +-10--- 1 +0----- 1 +100--- 0 +1-1-1- 0 +1-10-- 0 +1-1--1 0 +.names RST.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF inst_VMA_INTreg.D +-0000--01 1 +-----11-- 1 +-----1--1 1 +-----1-0- 1 +--0--1--- 1 +----11--- 1 +---1-1--- 1 +-0---1--- 1 +0-------- 1 +11100-010 0 +1---10--- 0 +1--1-0--- 0 +1----0-1- 0 +1-1--0--- 0 +11---0--- 0 +1----0--0 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +inst_RW_000_INT.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \ +inst_RW_000_INT.D +---01--- 1 +-01--1-- 1 +-011---1 1 +--0-1--- 1 +-1--1--- 1 +------0- 1 +0------- 1 +1011-010 0 +1--0001- 0 +1-0-0-1- 0 +11--0-1- 0 +.names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ +A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AS_030_D1.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ +SM_AMIGA_i_7_.BLIF AS_030.PIN.BLIF inst_AS_030_000_SYNC.D +1--00101--1--- 1 +----------1-1- 1 +----------10-- 1 +---------11--- 1 +--------0-1--- 1 +-0--------1--- 1 +--0----------- 1 +-------------1 1 +-11----010-100 0 +-11---1-10-100 0 +-11--0--10-100 0 +-11-1---10-100 0 +-111----10-100 0 +011-----10-100 0 +--1-------0--0 0 +.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D +1--101 1 +1-1--- 1 +-0---- 1 +-10-1- 0 +-100-- 0 +01---- 0 +-10--0 0 +.names RST.BLIF inst_AS_000_DMA.BLIF inst_AMIGA_DS.BLIF \ +inst_CLK_OUT_PRE_D.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF inst_AS_000_DMA.D +-1-1--0-- 1 +----11--0 1 +----00--- 1 +-------1- 1 +--1------ 1 +0-------- 1 +100--1-01 0 +1-00-1-01 0 +1-0--1101 0 +1-0-0110- 0 +1-0001-0- 0 +100-01-0- 0 +1-0-1010- 0 +1-0010-0- 0 +100-10-0- 0 +.names RST.BLIF inst_DS_000_DMA.BLIF inst_AMIGA_DS.BLIF \ +inst_CLK_OUT_PRE_D.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ +CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF inst_DS_000_DMA.D +-1-1--0-- 1 +----11--0 1 +----00--- 1 +-------1- 1 +--1------ 1 +0-------- 1 +100--1-01 0 +1-00-1-01 0 +1-0--1101 0 +1-0-0110- 0 +1-0001-0- 0 +100-01-0- 0 +1-0-1010- 0 +1-0010-0- 0 +100-10-0- 0 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D ---01- 1 @@ -394,70 +469,31 @@ inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D -11 1 10- 0 1-0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +0-- 1 +-01 1 +11- 0 +1-0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1- 1 +0-- 1 +--1 1 +100 0 .names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D 0- 1 -1 1 10 0 -.names RST.BLIF DTACK.PIN.BLIF inst_DTACK_D0.D -0- 1 --1 1 -10 0 -.names VPA.BLIF RST.BLIF inst_VPA_D.D -1- 1 --0 1 -01 0 -.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF \ -RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D -1-10111 1 -11----- 1 -0------ 0 --0---0- 0 --0--0-- 0 --0-1--- 0 --00---- 0 --0----0 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_DS_000_ENABLE.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF RW.PIN.BLIF \ -inst_DS_000_ENABLE.D -101--1-- 1 -101-1--1 1 -1--1--0- 1 -----001- 0 ----000-- 0 ------010 0 ---0---1- 0 --1----1- 0 ----0-0-0 0 ---00---- 0 --1-0---- 0 -0------- 0 -.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ -CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D ---0--- 1 --1---- 1 -----01 1 ----0-1 1 -0----1 1 -10111- 0 --01--0 0 .names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.D ---11- 1 --10-- 1 ---1-0 1 -0---- 1 -1-101 0 -100-- 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D ---11- 1 --00-- 1 ---1-0 1 -0---- 1 -1-101 0 -110-- 0 +-0- 1 +0-- 1 +--1 1 +110 0 +.names RST.BLIF inst_AS_030_D0.BLIF inst_AS_030_D1.BLIF inst_AS_030_D1.D +11- 1 +0-1 1 +10- 0 +0-0 0 .names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ inst_UDS_000_INT.D -10- 1 @@ -465,110 +501,6 @@ inst_UDS_000_INT.D --11 1 100- 0 1-10 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D --111- 1 -0---- 1 --0--1 1 -11-0- 0 -110-- 0 -10--0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1-1- 1 --10-- 1 -0---- 1 --0--1 1 -1110- 0 -10--0 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF inst_VMA_INTreg.D ---0000-01 1 --1----1-- 1 --1------1 1 --1-----0- 1 --1---0--- 1 --1--1---- 1 --1-1----- 1 --10------ 1 -0-------- 1 -1-1001010 0 -10--1---- 0 -10-1----- 0 -10-----1- 0 -10---1--- 0 -101------ 0 -10------0 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF \ -inst_RW_000_INT.D --01-1--- 1 --011---1 1 ----0-1-- 1 ---0--1-- 1 --1---1-- 1 -------0- 1 -0------- 1 -10110-10 0 -1--0001- 0 -1-0--01- 0 -11---01- 0 -.names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ -A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ -SM_AMIGA_i_7_.BLIF AS_030.PIN.BLIF inst_AS_030_000_SYNC.D -1--00101--1--- 1 -----------1-1- 1 -----------10-- 1 ----------11--- 1 ---------0-1--- 1 --0--------1--- 1 ---0----------- 1 --------------1 1 --11----010-100 0 --11---1-10-100 0 --11--0--10-100 0 --11-1---10-100 0 --111----10-100 0 -011-----10-100 0 ---1-------0--0 0 -.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D ---1100 1 --10--- 1 -0----- 1 -100--- 0 -1-1-1- 0 -1-10-- 0 -1-1--1 0 -.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D -1--101 1 -1-1--- 1 --0---- 1 --10-1- 0 --100-- 0 -01---- 0 --10--0 0 -.names RST.BLIF inst_AS_000_DMA.BLIF inst_AMIGA_DS.BLIF \ -inst_CLK_OUT_PRE_D.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF inst_AS_000_DMA.D --1-1--0-- 1 -----11--0 1 -----00--- 1 --------1- 1 ---1------ 1 -0-------- 1 -100--1-01 0 -1-00-1-01 0 -1-0--1101 0 -1-0-1010- 0 -1-0010-0- 0 -100-10-0- 0 -1-0-0110- 0 -1-0001-0- 0 -100-01-0- 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -576,6 +508,25 @@ CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF inst_AS_000_DMA.D .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 1 0 +.names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ +AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ +AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF N_60 +1-111000000000 1 +-1------------ 1 +-0----------1- 0 +-0---------1-- 0 +-0--------1--- 0 +-0-------1---- 0 +-0------1----- 0 +-0-----1------ 0 +-0----1------- 0 +-0---1-------- 0 +-0--0--------- 0 +-0-0---------- 0 +-00----------- 0 +00------------ 0 +-0-----------1 0 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -669,15 +620,6 @@ AHIGH_31_.PIN.BLIF CIIN .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C -1 1 -0 0 .names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -693,12 +635,6 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF SM_AMIGA_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_3_.C -1 1 -0 0 .names CLK_OSZI.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -717,10 +653,13 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_000.BLIF CLK_000_D_0_.D +.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C 1 1 0 0 -.names CLK_OSZI.BLIF CLK_000_D_0_.C +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_5_.C 1 1 0 0 .names CLK_000_D_0_.BLIF CLK_000_D_1_.D @@ -747,37 +686,67 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_D_4_.C 1 1 0 0 -.names CLK_OSZI.BLIF CYCLE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CYCLE_DMA_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_030_PE_0_.C -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_030_PE_1_.C -1 1 -0 0 .names CLK_OSZI.BLIF SIZE_DMA_0_.C 1 1 0 0 .names CLK_OSZI.BLIF SIZE_DMA_1_.C 1 1 0 0 +.names CLK_OSZI.BLIF CYCLE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF CYCLE_DMA_1_.C +1 1 +0 0 .names CLK_OSZI.BLIF cpu_est_0_.C 1 1 0 0 .names CLK_OSZI.BLIF cpu_est_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF RST_DLY_0_.C +.names CLK_OSZI.BLIF cpu_est_2_.C 1 1 0 0 -.names CLK_OSZI.BLIF RST_DLY_1_.C +.names CLK_OSZI.BLIF cpu_est_3_.C 1 1 0 0 -.names CLK_OSZI.BLIF RST_DLY_2_.C +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_0_.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 +.names CLK_OSZI.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_000_DMA.C 1 1 0 0 .names CLK_OSZI.BLIF inst_DS_000_DMA.C @@ -792,55 +761,22 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_AMIGA_DS.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DTACK_D0.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_VPA_D.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_RESET_OUT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C -1 1 -0 0 -.names CLK_OSZI.BLIF BG_000DFFreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_UDS_000_INT.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_A0_DMA.C 1 1 0 0 .names CLK_OSZI.BLIF inst_RW_000_DMA.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_VMA_INTreg.C +.names CLK_OSZI.BLIF inst_AS_030_D0.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_RW_000_INT.C +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI.BLIF inst_AS_030_D1.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_000_DMA.C +.names CLK_OSZI.BLIF inst_UDS_000_INT.C 1 1 0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C @@ -877,18 +813,16 @@ AHIGH_31_.PIN.BLIF CIIN .names inst_RW_000_INT.BLIF RW_000 1 1 0 0 -.names inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF UDS_000 -0- 1 --1 1 -10 0 -.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000 +.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000 1- 1 -0 1 01 0 +.names inst_DS_000_ENABLE.BLIF inst_LDS_000_INT.BLIF LDS_000 +0- 1 +-1 1 +10 0 .names BERR 0 -.names DTACK - 0 .names inst_RW_000_DMA.BLIF RW 1 1 0 0 @@ -912,81 +846,58 @@ AHIGH_31_.PIN.BLIF CIIN .names inst_A0_DMA.BLIF A_0_ 1 1 0 0 -.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ -AS_030.OE -001 1 --1- 0 -1-- 0 ---0 0 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF AS_000.OE +.names inst_BGACK_030_INTreg.BLIF AS_030.OE +0 1 +1 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF AS_000.OE 11 1 0- 0 -0 0 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW_000.OE +.names RST.BLIF inst_BGACK_030_INTreg.BLIF RW_000.OE 11 1 0- 0 -0 0 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF UDS_000.OE +.names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.OE 11 1 0- 0 -0 0 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF LDS_000.OE +.names RST.BLIF inst_BGACK_030_INTreg.BLIF LDS_000.OE 11 1 0- 0 -0 0 -.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_0_.OE -00 1 -1- 0 --1 0 -.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_1_.OE -00 1 -1- 0 --1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_24_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_25_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_26_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_27_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_28_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_29_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_30_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF RESET.BLIF inst_BGACK_030_INTreg.BLIF AHIGH_31_.OE -010 1 --0- 0 -1-- 0 ---1 0 -.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF A_0_.OE -001 1 --1- 0 -1-- 0 ---0 0 +.names inst_BGACK_030_INTreg.BLIF SIZE_0_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF SIZE_1_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_24_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_25_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_26_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_27_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_28_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_29_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_30_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF AHIGH_31_.OE +0 1 +1 0 +.names inst_BGACK_030_INTreg.BLIF A_0_.OE +0 1 +1 0 .names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_DECODE_19_.BLIF \ A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF \ AS_030.PIN.BLIF BERR.OE @@ -1000,105 +911,38 @@ AS_030.PIN.BLIF BERR.OE -0------- 0 0-------- 0 --------1 0 -.names inst_AS_000_DMA.BLIF DTACK.OE +.names inst_BGACK_030_INTreg.BLIF RW.OE 0 1 1 0 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW.OE -01 1 -1- 0 +.names inst_BGACK_030_INTreg.BLIF DS_030.OE +0 1 +1 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF DSACK1.OE +11 1 +0- 0 -0 0 -.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ -DS_030.OE -001 1 --1- 0 -1-- 0 ---0 0 -.names nEXP_SPACE.BLIF DSACK1.OE +.names inst_BGACK_030_INTreg.BLIF VMA.OE +1 1 +0 0 +.names N_60.BLIF CIIN.OE 1 1 0 0 -.names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ -A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ -AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ -AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE -1-111000000000 1 --1------------ 1 --0----------1- 0 --0---------1-- 0 --0--------1--- 0 --0-------1---- 0 --0------1----- 0 --0-----1------ 0 --0----1------- 0 --0---1-------- 0 --0--0--------- 0 --0-0---------- 0 --00----------- 0 -00------------ 0 --0-----------1 0 .names cpu_est_2_.BLIF cpu_est_2_.D.X1 1 1 0 0 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_0_.BLIF CLK_000_D_1_.BLIF \ +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF cpu_est_2_.D.X2 -1-110 1 +11-10 1 0---- 0 ---0-- 0 +-0--- 0 ---0- 0 ----1 0 -.names RST.BLIF inst_AMIGA_DS.BLIF AS_000.PIN.BLIF CLK_030_PE_0_.D.X1 -100 1 -0-- 0 --1- 0 ---1 0 -.names RST.BLIF inst_AS_000_DMA.BLIF CLK_030_PE_1_.BLIF inst_AMIGA_DS.BLIF \ -inst_CLK_OUT_PRE_D.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF CLK_030_PE_0_.BLIF \ -CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF CLK_030_PE_0_.D.X2 -11-0---0-0- 1 -1--00--0-0- 1 -1--0-00--0- 1 -1--0---010- 1 -1--0-11--00 1 -10001--100- 1 -0---------- 0 ----1------- 0 ----------1- 0 --1---011--- 0 ---1--011--- 0 -----0011--- 0 --1---101--- 0 ---1--101--- 0 -----0101--- 0 ------0111-- 0 ------1011-- 0 --1---1-1--1 0 ---1--1-1--1 0 -----01-1--1 0 ------1-11-1 0 --0--10100-- 0 --0--11000-- 0 --0--11-00-1 0 -.names RST_DLY_1_.BLIF RST_DLY_1_.D.X1 -1 1 -0 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_1_.D.X2 -11010- 1 -0---1- 1 --10110 1 -10---- 0 -1-1--- 0 -1--0-- 0 -0---0- 0 --0--0- 0 ---1-0- 0 ----00- 0 -1---11 0 .names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1 11 1 0- 0 -0 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ +.names RST.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ BERR.PIN.BLIF SM_AMIGA_3_.D.X2 1-------0110- 1 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 491c0f9..65c3b42 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Thu Dec 29 16:01:56 2016 +// Design '68030_tk' created Sat Dec 30 00:43:37 2017 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index fc3aa63..ad2f4c6 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,19 +2,27 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Thu Dec 29 16:01:56 2016 +Design bus68030 created Sat Dec 30 00:43:37 2017 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- + 0 0 1 Pin AHIGH_27_ + 1 1 1 Pin AHIGH_27_.OE + 0 0 1 Pin AHIGH_26_ + 1 1 1 Pin AHIGH_26_.OE + 0 0 1 Pin AHIGH_25_ + 1 1 1 Pin AHIGH_25_.OE + 0 0 1 Pin AHIGH_24_ + 1 1 1 Pin AHIGH_24_.OE 0 0 1 Pin AHIGH_31_ - 1 3 1 Pin AHIGH_31_.OE + 1 1 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- - 1 3 1 Pin AS_030.OE + 1 1 1 Pin AS_030.OE 1 2 1 Pin AS_000- 1 2 1 Pin AS_000.OE 1 2 1 Pin DS_030- - 1 3 1 Pin DS_030.OE + 1 1 1 Pin DS_030.OE 1 2 1 Pin UDS_000- 1 2 1 Pin UDS_000.OE 1 2 1 Pin LDS_000- @@ -25,41 +33,24 @@ Design bus68030 created Thu Dec 29 16:01:56 2016 1 1 1 Pin CLK_EXP 1 9 1 Pin FPU_CS- 1 2 1 Pin DSACK1- - 1 1 1 Pin DSACK1.OE - 0 0 1 Pin DTACK - 1 1 1 Pin DTACK.OE + 1 2 1 Pin DSACK1.OE 1 0 1 Pin AVEC 2 3 1 Pin E - 0 0 1 Pin AHIGH_30_ - 1 3 1 Pin AHIGH_30_.OE - 0 0 1 Pin AHIGH_29_ - 1 3 1 Pin AHIGH_29_.OE - 0 0 1 Pin AHIGH_28_ - 1 3 1 Pin AHIGH_28_.OE - 0 0 1 Pin AHIGH_27_ - 1 3 1 Pin AHIGH_27_.OE - 0 0 1 Pin AHIGH_26_ - 1 3 1 Pin AHIGH_26_.OE - 0 0 1 Pin AHIGH_25_ - 1 3 1 Pin AHIGH_25_.OE 0 0 1 Pin AMIGA_ADDR_ENABLE - 0 0 1 Pin AHIGH_24_ - 1 3 1 Pin AHIGH_24_.OE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE - 1 3 1 Pin A_0_.OE - 3 5 1 Pin A_0_.D - 1 1 1 Pin A_0_.C - 1 2 1 Pin SIZE_1_.OE - 3 6 1 Pin SIZE_1_.D + 0 0 1 Pin AHIGH_30_ + 1 1 1 Pin AHIGH_30_.OE + 0 0 1 Pin AHIGH_29_ + 1 1 1 Pin AHIGH_29_.OE + 0 0 1 Pin AHIGH_28_ + 1 1 1 Pin AHIGH_28_.OE + 1 1 1 Pin SIZE_1_.OE + 2 4 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C - 10 8 1 Pin IPL_030_1_.D- - 1 1 1 Pin IPL_030_1_.C - 10 8 1 Pin IPL_030_0_.D- - 1 1 1 Pin IPL_030_0_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -69,36 +60,44 @@ Design bus68030 created Thu Dec 29 16:01:56 2016 1 1 1 Pin BG_000.C 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C - 1 2 1 Pin SIZE_0_.OE - 3 6 1 Pin SIZE_0_.D- - 1 1 1 Pin SIZE_0_.C + 1 1 1 Pin A_0_.OE + 2 3 1 Pin A_0_.D + 1 1 1 Pin A_0_.C + 10 8 1 Pin IPL_030_1_.D- + 1 1 1 Pin IPL_030_1_.C + 10 8 1 Pin IPL_030_0_.D- + 1 1 1 Pin IPL_030_0_.C + 1 1 1 Pin VMA.OE 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C - 1 2 1 Pin RW.OE - 2 5 1 Pin RW.D- + 1 1 1 Pin RW.OE + 1 3 1 Pin RW.D- 1 1 1 Pin RW.C + 1 1 1 Pin SIZE_0_.OE + 2 4 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.C + 3 3 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 1 1 1 NodeX1 cpu_est_2_.D.X1 - 1 4 1 NodeX2 cpu_est_2_.D.X2 + 1 4 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C - 3 3 1 Node cpu_est_0_.D - 1 1 1 Node cpu_est_0_.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C + 2 3 1 Node inst_AS_030_D1.D + 1 1 1 Node inst_AS_030_D1.C 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C - 1 2 1 Node inst_BGACK_030_INT_D.D- - 1 1 1 Node inst_BGACK_030_INT_D.C 6 9 1 Node inst_AS_000_DMA.D 1 1 1 Node inst_AS_000_DMA.C - 9 12 1 Node inst_DS_000_DMA.D + 6 9 1 Node inst_DS_000_DMA.D 1 1 1 Node inst_DS_000_DMA.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C @@ -106,10 +105,6 @@ Design bus68030 created Thu Dec 29 16:01:56 2016 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C - 2 7 1 Node inst_RESET_OUT.D - 1 1 1 Node inst_RESET_OUT.C - 6 11 1 Node CLK_030_PE_1_.D - 1 1 1 Node CLK_030_PE_1_.C 2 3 1 Node inst_AMIGA_DS.D 1 1 1 Node inst_AMIGA_DS.C 1 1 1 Node CLK_000_D_1_.D @@ -130,12 +125,14 @@ Design bus68030 created Thu Dec 29 16:01:56 2016 1 1 1 Node CLK_000_D_2_.C 1 1 1 Node CLK_000_D_4_.D 1 1 1 Node CLK_000_D_4_.C - 3 6 1 Node inst_LDS_000_INT.D - 1 1 1 Node inst_LDS_000_INT.C - 3 8 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C 2 4 1 Node inst_UDS_000_INT.D- 1 1 1 Node inst_UDS_000_INT.C + 3 8 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 3 6 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.C + 1 2 1 Node inst_BGACK_030_INT_D.D- + 1 1 1 Node inst_BGACK_030_INT_D.C 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D @@ -148,15 +145,6 @@ Design bus68030 created Thu Dec 29 16:01:56 2016 1 1 1 Node CYCLE_DMA_0_.C 2 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C - 9 11 1 Node CLK_030_PE_0_.D- - 1 1 1 Node CLK_030_PE_0_.C - 4 6 1 Node RST_DLY_0_.D - 1 1 1 Node RST_DLY_0_.C - 2 6 1 NodeX1 RST_DLY_1_.D.X1 - 1 2 1 NodeX2 RST_DLY_1_.D.X2 - 1 1 1 Node RST_DLY_1_.C - 2 6 1 Node RST_DLY_2_.D - 1 1 1 Node RST_DLY_2_.C 2 6 1 Node inst_DSACK1_INT.D- 1 1 1 Node inst_DSACK1_INT.C 2 6 1 Node inst_AS_000_INT.D- @@ -167,44 +155,60 @@ Design bus68030 created Thu Dec 29 16:01:56 2016 1 1 1 Node SM_AMIGA_3_.C 5 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C + 1 1 1 Node CLK_OUT_INTreg.D + 1 1 1 Node CLK_OUT_INTreg.C 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C - 1 1 1 Node CLK_OUT_INTreg.D - 1 1 1 Node CLK_OUT_INTreg.C - 2 14 1 Node CIIN_0 + 2 14 1 Node N_60 ========= - 281 P-Term Total: 281 - Total Pins: 61 - Total Nodes: 47 + 243 P-Term Total: 243 + Total Pins: 59 + Total Nodes: 42 Average P-Term/Output: 2 Equations: +AHIGH_27_ = (0); + +AHIGH_27_.OE = (!BGACK_030.Q); + +AHIGH_26_ = (0); + +AHIGH_26_.OE = (!BGACK_030.Q); + +AHIGH_25_ = (0); + +AHIGH_25_.OE = (!BGACK_030.Q); + +AHIGH_24_ = (0); + +AHIGH_24_.OE = (!BGACK_030.Q); + AHIGH_31_ = (0); -AHIGH_31_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); +AHIGH_31_.OE = (!BGACK_030.Q); !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); -AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +AS_030.OE = (!BGACK_030.Q); !AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); -AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); +AS_000.OE = (RST & BGACK_030.Q); !DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); -DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +DS_030.OE = (!BGACK_030.Q); -!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); -UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); +UDS_000.OE = (RST & BGACK_030.Q); -!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); +!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); -LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); +LDS_000.OE = (RST & BGACK_030.Q); BERR = (0); @@ -218,47 +222,15 @@ CLK_EXP = (CLK_OUT_INTreg.Q); !DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); -DSACK1.OE = (nEXP_SPACE); - -DTACK = (0); - -DTACK.OE = (!inst_AS_000_DMA.Q); +DSACK1.OE = (nEXP_SPACE & BGACK_030.Q); AVEC = (1); E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q # cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q); -AHIGH_30_ = (0); - -AHIGH_30_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_29_ = (0); - -AHIGH_29_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_28_ = (0); - -AHIGH_28_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_27_ = (0); - -AHIGH_27_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_26_ = (0); - -AHIGH_26_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_25_ = (0); - -AHIGH_25_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - AMIGA_ADDR_ENABLE = (0); -AHIGH_24_ = (0); - -AHIGH_24_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); @@ -269,24 +241,67 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); -CIIN.OE = (CIIN_0); +CIIN.OE = (N_60); -A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +AHIGH_30_ = (0); -A_0_.D = (!RST - # !BGACK_030.Q & UDS_000.PIN - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q); +AHIGH_30_.OE = (!BGACK_030.Q); -A_0_.C = (CLK_OSZI); +AHIGH_29_ = (0); -SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); +AHIGH_29_.OE = (!BGACK_030.Q); + +AHIGH_28_ = (0); + +AHIGH_28_.OE = (!BGACK_030.Q); + +SIZE_1_.OE = (!BGACK_030.Q); SIZE_1_.D = (!RST - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_1_.Q # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); SIZE_1_.C = (CLK_OSZI); +!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q + # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q + # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q + # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_2_.C = (CLK_OSZI); + +RW_000.OE = (RST & BGACK_030.Q); + +!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_6_.Q & !RW_000.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); + +RW_000.C = (CLK_OSZI); + +!BG_000.D = (!BG_030 & RST & !BG_000.Q + # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); + +BG_000.C = (CLK_OSZI); + +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN); + +BGACK_030.C = (CLK_OSZI); + +A_0_.OE = (!BGACK_030.Q); + +A_0_.D = (!RST + # !BGACK_030.Q & UDS_000.PIN); + +A_0_.C = (CLK_OSZI); + !IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q @@ -313,79 +328,26 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q - # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q - # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q - # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q - # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); - -IPL_030_2_.C = (CLK_OSZI); - -RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); - -!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); - -RW_000.C = (CLK_OSZI); - -!BG_000.D = (!BG_030 & RST & !BG_000.Q - # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); - -BG_000.C = (CLK_OSZI); - -BGACK_030.D = (!RST - # BGACK_000 & BGACK_030.Q - # BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN); - -BGACK_030.C = (CLK_OSZI); - -SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); - -!SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q - # RST & BGACK_030.Q & !SIZE_0_.Q - # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_0_.C = (CLK_OSZI); +VMA.OE = (BGACK_030.Q); VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q - # RST & VMA.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !VMA.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q + # RST & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); VMA.C = (CLK_OSZI); -RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); +RW.OE = (!BGACK_030.Q); -!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); +!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN); RW.C = (CLK_OSZI); -cpu_est_1_.D = (cpu_est_1_.Q & !cpu_est_0_.Q - # cpu_est_1_.Q & !CLK_000_D_1_.Q - # cpu_est_1_.Q & CLK_000_D_0_.Q - # !cpu_est_1_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); +SIZE_0_.OE = (!BGACK_030.Q); -cpu_est_1_.C = (CLK_OSZI); +!SIZE_0_.D = (RST & BGACK_030.Q + # RST & !UDS_000.PIN & !LDS_000.PIN); -cpu_est_2_.D.X1 = (cpu_est_2_.Q); - -cpu_est_2_.D.X2 = (cpu_est_1_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -cpu_est_2_.C = (CLK_OSZI); - -cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q - # cpu_est_3_.Q & CLK_000_D_0_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q - # cpu_est_1_.Q & cpu_est_2_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -cpu_est_3_.C = (CLK_OSZI); +SIZE_0_.C = (CLK_OSZI); cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q # cpu_est_0_.Q & CLK_000_D_0_.Q @@ -393,13 +355,31 @@ cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q cpu_est_0_.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q - # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q & inst_BGACK_030_INT_D.Q); +cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q + # cpu_est_1_.Q & !CLK_000_D_1_.Q + # cpu_est_1_.Q & CLK_000_D_0_.Q + # cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_1_.C = (CLK_OSZI); + +cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.C = (CLK_OSZI); + +cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q + # cpu_est_3_.Q & !CLK_000_D_1_.Q + # cpu_est_3_.Q & CLK_000_D_0_.Q + # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_3_.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q - # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); @@ -407,20 +387,21 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); inst_AS_030_D0.C = (CLK_OSZI); +inst_AS_030_D1.D = (RST & inst_AS_030_D0.Q + # !RST & inst_AS_030_D1.Q); + +inst_AS_030_D1.C = (CLK_OSZI); + !inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_000_SYNC.Q & !AS_030.PIN - # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); + # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); -!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); - -inst_BGACK_030_INT_D.C = (CLK_OSZI); - inst_AS_000_DMA.D = (!RST # inst_AMIGA_DS.Q # AS_000.PIN @@ -434,11 +415,8 @@ inst_DS_000_DMA.D = (!RST # inst_AMIGA_DS.Q # AS_000.PIN # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q - # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN - # inst_DS_000_DMA.Q & CLK_030_PE_1_.Q & !RW_000.PIN - # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN - # inst_DS_000_DMA.Q & !CLK_030_PE_0_.Q & !RW_000.PIN - # inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q & RW_000.PIN); + # inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q + # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN); inst_DS_000_DMA.C = (CLK_OSZI); @@ -450,24 +428,10 @@ CLK_000_D_3_.D = (CLK_000_D_2_.Q); CLK_000_D_3_.C = (CLK_OSZI); -!inst_DTACK_D0.D = (RST & !DTACK.PIN); +!inst_DTACK_D0.D = (!DTACK & RST); inst_DTACK_D0.C = (CLK_OSZI); -inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); - -inst_RESET_OUT.C = (CLK_OSZI); - -CLK_030_PE_1_.D = (RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & RW_000.PIN - # RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN - # RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN - # RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN & RW_000.PIN); - -CLK_030_PE_1_.C = (CLK_OSZI); - inst_AMIGA_DS.D = (!RST # UDS_000.PIN & LDS_000.PIN); @@ -509,11 +473,10 @@ CLK_000_D_4_.D = (CLK_000_D_3_.Q); CLK_000_D_4_.C = (CLK_OSZI); -inst_LDS_000_INT.D = (!RST - # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q - # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); +!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); -inst_LDS_000_INT.C = (CLK_OSZI); +inst_UDS_000_INT.C = (CLK_OSZI); inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q @@ -521,10 +484,15 @@ inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN inst_DS_000_ENABLE.C = (CLK_OSZI); -!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A_0_.PIN); +inst_LDS_000_INT.D = (!RST + # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q + # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); -inst_UDS_000_INT.C = (CLK_OSZI); +inst_LDS_000_INT.C = (CLK_OSZI); + +!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q @@ -562,37 +530,6 @@ CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !AS_000.PIN CYCLE_DMA_1_.C = (CLK_OSZI); -!CLK_030_PE_0_.D = (!RST - # inst_AMIGA_DS.Q - # AS_000.PIN - # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q - # inst_AS_000_DMA.Q & !CLK_030_PE_0_.Q - # !inst_CLK_OUT_PRE_D.Q & !CLK_030_PE_0_.Q - # !CLK_030_PE_0_.Q & CLK_OUT_INTreg.Q - # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN - # !inst_AS_000_DMA.Q & !CLK_030_PE_1_.Q & inst_CLK_OUT_PRE_D.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q); - -CLK_030_PE_0_.C = (CLK_OSZI); - -RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q - # RST & CLK_000_D_0_.Q & RST_DLY_0_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q - # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); - -RST_DLY_0_.C = (CLK_OSZI); - -RST_DLY_1_.D.X1 = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_2_.Q); - -RST_DLY_1_.D.X2 = (RST & RST_DLY_1_.Q); - -RST_DLY_1_.C = (CLK_OSZI); - -RST_DLY_2_.D = (RST & RST_DLY_2_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); - -RST_DLY_2_.C = (CLK_OSZI); - !inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); @@ -613,7 +550,7 @@ SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q # CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN # inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); @@ -621,10 +558,14 @@ SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q - # RST & !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # RST & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); +CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_OUT_INTreg.C = (CLK_OSZI); + SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); @@ -633,11 +574,7 @@ SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_ SM_AMIGA_i_7_.C = (CLK_OSZI); -CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_OUT_INTreg.C = (CLK_OSZI); - -CIIN_0 = (nEXP_SPACE +N_60 = (nEXP_SPACE # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index ef0a635..7d82ad3 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -1,5 +1,5 @@ #PLAFILE 68030_tk.tt4 -#DATE 10/08/2016 +#DATE 02/16/2017 #DESIGN #DEVICE mach447a @@ -11,14 +11,14 @@ DATA LOCATION AHIGH_28_:C_0_15 // IO DATA LOCATION AHIGH_29_:B_8_6 // IO DATA LOCATION AHIGH_30_:B_0_5 // IO DATA LOCATION AHIGH_31_:B_12_4 // IO -DATA LOCATION AMIGA_ADDR_ENABLE:D_9_33 // OUT +DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48 // OUT -DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_5_34 // OUT +DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34 // OUT DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT DATA LOCATION AS_000:E_4_42 // IO DATA LOCATION AS_030:H_8_82 // IO DATA LOCATION AVEC:A_4_92 // OUT -DATA LOCATION A_0_:G_8_69 // IO {RN_A_0_} +DATA LOCATION A_0_:G_8_69 // IO DATA LOCATION A_1_:F_*_60 // INP DATA LOCATION A_DECODE_16_:A_*_96 // INP DATA LOCATION A_DECODE_17_:F_*_59 // INP @@ -34,25 +34,21 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT -DATA LOCATION CIIN_0:E_5 // NOD DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_D_0_:D_13 // NOD +DATA LOCATION CLK_000_D_0_:D_9 // NOD DATA LOCATION CLK_000_D_1_:H_5 // NOD DATA LOCATION CLK_000_D_2_:H_6 // NOD DATA LOCATION CLK_000_D_3_:F_13 // NOD -DATA LOCATION CLK_000_D_4_:C_14 // NOD -DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_030_PE_0_:A_9 // NOD -DATA LOCATION CLK_030_PE_1_:A_2 // NOD +DATA LOCATION CLK_000_D_4_:F_5 // NOD DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CLK_OUT_INTreg:D_10 // NOD -DATA LOCATION CYCLE_DMA_0_:A_6 // NOD -DATA LOCATION CYCLE_DMA_1_:A_10 // NOD +DATA LOCATION CLK_OUT_INTreg:A_1 // NOD +DATA LOCATION CYCLE_DMA_0_:B_13 // NOD +DATA LOCATION CYCLE_DMA_1_:B_2 // NOD DATA LOCATION DSACK1:H_9_81 // OUT DATA LOCATION DS_030:A_0_98 // OUT -DATA LOCATION DTACK:D_0_30 // IO +DATA LOCATION DTACK:D_*_30 // INP DATA LOCATION E:G_4_66 // OUT DATA LOCATION FC_0_:F_*_57 // INP DATA LOCATION FC_1_:F_*_58 // INP @@ -64,63 +60,56 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:B_10 // NOD -DATA LOCATION IPL_D0_1_:B_6 // NOD -DATA LOCATION IPL_D0_2_:B_2 // NOD +DATA LOCATION IPL_D0_0_:A_6 // NOD +DATA LOCATION IPL_D0_1_:D_6 // NOD +DATA LOCATION IPL_D0_2_:A_2 // NOD DATA LOCATION LDS_000:D_12_31 // IO -DATA LOCATION RESET:B_*_3 // INP -DATA LOCATION RN_A_0_:G_8 // NOD {A_0_} +DATA LOCATION N_60:E_9 // NOD DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} DATA LOCATION RN_IPL_030_0_:B_5 // NOD {IPL_030_0_} DATA LOCATION RN_IPL_030_1_:B_9 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} -DATA LOCATION RN_RW:G_0 // NOD {RW} DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} -DATA LOCATION RN_SIZE_0_:G_12 // NOD {SIZE_0_} -DATA LOCATION RN_SIZE_1_:H_12 // NOD {SIZE_1_} -DATA LOCATION RN_VMA:D_4 // NOD {VMA} +DATA LOCATION RN_VMA:D_0 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RST_DLY_0_:G_6 // NOD -DATA LOCATION RST_DLY_1_:G_14 // NOD -DATA LOCATION RST_DLY_2_:G_10 // NOD -DATA LOCATION RW:G_0_71 // IO {RN_RW} +DATA LOCATION RW:G_0_71 // IO DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} -DATA LOCATION SIZE_0_:G_12_70 // IO {RN_SIZE_0_} -DATA LOCATION SIZE_1_:H_12_79 // IO {RN_SIZE_1_} +DATA LOCATION SIZE_0_:G_12_70 // IO +DATA LOCATION SIZE_1_:H_12_79 // IO DATA LOCATION SM_AMIGA_0_:A_12 // NOD -DATA LOCATION SM_AMIGA_1_:F_8 // NOD -DATA LOCATION SM_AMIGA_2_:C_9 // NOD -DATA LOCATION SM_AMIGA_3_:C_6 // NOD -DATA LOCATION SM_AMIGA_4_:A_1 // NOD -DATA LOCATION SM_AMIGA_5_:G_13 // NOD +DATA LOCATION SM_AMIGA_1_:A_5 // NOD +DATA LOCATION SM_AMIGA_2_:A_9 // NOD +DATA LOCATION SM_AMIGA_3_:A_13 // NOD +DATA LOCATION SM_AMIGA_4_:G_5 // NOD +DATA LOCATION SM_AMIGA_5_:F_12 // NOD DATA LOCATION SM_AMIGA_6_:F_0 // NOD -DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD +DATA LOCATION SM_AMIGA_i_7_:F_8 // NOD DATA LOCATION UDS_000:D_8_32 // IO -DATA LOCATION VMA:D_4_35 // IO {RN_VMA} +DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP DATA LOCATION cpu_est_0_:G_9 // NOD -DATA LOCATION cpu_est_1_:D_6 // NOD -DATA LOCATION cpu_est_2_:D_14 // NOD -DATA LOCATION cpu_est_3_:D_2 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:F_9 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:F_5 // NOD -DATA LOCATION inst_AMIGA_DS:C_10 // NOD -DATA LOCATION inst_AS_000_DMA:A_8 // NOD -DATA LOCATION inst_AS_000_INT:C_2 // NOD -DATA LOCATION inst_AS_030_000_SYNC:B_13 // NOD -DATA LOCATION inst_AS_030_D0:H_2 // NOD -DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:G_2 // NOD -DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD -DATA LOCATION inst_DSACK1_INT:A_5 // NOD -DATA LOCATION inst_DS_000_DMA:A_13 // NOD -DATA LOCATION inst_DS_000_ENABLE:C_13 // NOD -DATA LOCATION inst_DTACK_D0:B_14 // NOD -DATA LOCATION inst_LDS_000_INT:F_12 // NOD -DATA LOCATION inst_RESET_OUT:G_5 // NOD -DATA LOCATION inst_UDS_000_INT:F_1 // NOD -DATA LOCATION inst_VPA_D:F_2 // NOD +DATA LOCATION cpu_est_1_:D_13 // NOD +DATA LOCATION cpu_est_2_:D_2 // NOD +DATA LOCATION cpu_est_3_:A_8 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:A_10 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_10 // NOD +DATA LOCATION inst_AMIGA_DS:H_2 // NOD +DATA LOCATION inst_AS_000_DMA:C_13 // NOD +DATA LOCATION inst_AS_000_INT:C_6 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_4 // NOD +DATA LOCATION inst_AS_030_D0:E_8 // NOD +DATA LOCATION inst_AS_030_D1:F_1 // NOD +DATA LOCATION inst_BGACK_030_INT_D:E_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:H_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:E_5 // NOD +DATA LOCATION inst_DSACK1_INT:G_2 // NOD +DATA LOCATION inst_DS_000_DMA:C_9 // NOD +DATA LOCATION inst_DS_000_ENABLE:C_2 // NOD +DATA LOCATION inst_DTACK_D0:F_9 // NOD +DATA LOCATION inst_LDS_000_INT:G_13 // NOD +DATA LOCATION inst_UDS_000_INT:B_6 // NOD +DATA LOCATION inst_VPA_D:G_6 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AHIGH_24_:BI DATA IO_DIR AHIGH_25_:BI @@ -154,13 +143,12 @@ DATA IO_DIR BG_000:OUT DATA IO_DIR BG_030:IN DATA IO_DIR CIIN:OUT DATA IO_DIR CLK_000:IN -DATA IO_DIR CLK_030:IN DATA IO_DIR CLK_DIV_OUT:OUT DATA IO_DIR CLK_EXP:OUT DATA IO_DIR CLK_OSZI:IN DATA IO_DIR DSACK1:OUT DATA IO_DIR DS_030:OUT -DATA IO_DIR DTACK:BI +DATA IO_DIR DTACK:IN DATA IO_DIR E:OUT DATA IO_DIR FC_0_:IN DATA IO_DIR FC_1_:IN @@ -173,7 +161,6 @@ DATA IO_DIR IPL_0_:IN DATA IO_DIR IPL_1_:IN DATA IO_DIR IPL_2_:IN DATA IO_DIR LDS_000:BI -DATA IO_DIR RESET:IN DATA IO_DIR RST:IN DATA IO_DIR RW:BI DATA IO_DIR RW_000:BI @@ -184,18 +171,32 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI +DATA PW_LEVEL AHIGH_27_:1 +DATA SLEW AHIGH_27_:0 +DATA PW_LEVEL AHIGH_26_:1 +DATA SLEW AHIGH_26_:0 +DATA PW_LEVEL AHIGH_25_:1 +DATA SLEW AHIGH_25_:0 +DATA PW_LEVEL AHIGH_24_:1 +DATA SLEW AHIGH_24_:0 DATA PW_LEVEL AHIGH_31_:1 DATA SLEW AHIGH_31_:0 -DATA PW_LEVEL IPL_1_:1 -DATA SLEW IPL_1_:1 -DATA PW_LEVEL IPL_0_:1 -DATA SLEW IPL_0_:1 +DATA PW_LEVEL A_DECODE_22_:1 +DATA SLEW A_DECODE_22_:1 +DATA PW_LEVEL A_DECODE_21_:1 +DATA SLEW A_DECODE_21_:1 DATA PW_LEVEL A_DECODE_23_:1 DATA SLEW A_DECODE_23_:1 -DATA PW_LEVEL FC_0_:1 -DATA SLEW FC_0_:1 -DATA PW_LEVEL A_1_:1 -DATA SLEW A_1_:1 +DATA PW_LEVEL A_DECODE_20_:1 +DATA SLEW A_DECODE_20_:1 +DATA PW_LEVEL A_DECODE_19_:1 +DATA SLEW A_DECODE_19_:1 +DATA PW_LEVEL A_DECODE_18_:1 +DATA SLEW A_DECODE_18_:1 +DATA PW_LEVEL A_DECODE_17_:1 +DATA SLEW A_DECODE_17_:1 +DATA PW_LEVEL A_DECODE_16_:1 +DATA SLEW A_DECODE_16_:1 DATA PW_LEVEL IPL_2_:1 DATA SLEW IPL_2_:1 DATA PW_LEVEL FC_1_:1 @@ -217,13 +218,20 @@ DATA PW_LEVEL BG_030:1 DATA SLEW BG_030:1 DATA PW_LEVEL BGACK_000:1 DATA SLEW BGACK_000:1 -DATA SLEW CLK_030:1 DATA SLEW CLK_000:1 +DATA PW_LEVEL IPL_1_:1 +DATA SLEW IPL_1_:1 DATA SLEW CLK_OSZI:1 +DATA PW_LEVEL IPL_0_:1 +DATA SLEW IPL_0_:1 DATA PW_LEVEL CLK_DIV_OUT:1 DATA SLEW CLK_DIV_OUT:0 +DATA PW_LEVEL FC_0_:1 +DATA SLEW FC_0_:1 DATA PW_LEVEL CLK_EXP:1 DATA SLEW CLK_EXP:0 +DATA PW_LEVEL A_1_:1 +DATA SLEW A_1_:1 DATA PW_LEVEL FPU_CS:1 DATA SLEW FPU_CS:0 DATA PW_LEVEL FPU_SENSE:1 @@ -236,56 +244,26 @@ DATA PW_LEVEL AVEC:1 DATA SLEW AVEC:0 DATA PW_LEVEL E:1 DATA SLEW E:0 +DATA SLEW VPA:1 +DATA SLEW RST:1 +DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 +DATA SLEW AMIGA_ADDR_ENABLE:0 +DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1 +DATA SLEW AMIGA_BUS_DATA_DIR:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1 +DATA SLEW AMIGA_BUS_ENABLE_LOW:0 +DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 +DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 +DATA PW_LEVEL CIIN:1 +DATA SLEW CIIN:0 DATA PW_LEVEL AHIGH_30_:1 DATA SLEW AHIGH_30_:0 -DATA SLEW VPA:1 DATA PW_LEVEL AHIGH_29_:1 DATA SLEW AHIGH_29_:0 DATA PW_LEVEL AHIGH_28_:1 DATA SLEW AHIGH_28_:0 -DATA SLEW RST:1 -DATA PW_LEVEL AHIGH_27_:1 -DATA SLEW AHIGH_27_:0 -DATA PW_LEVEL RESET:1 -DATA SLEW RESET:0 -DATA PW_LEVEL AHIGH_26_:1 -DATA SLEW AHIGH_26_:0 -DATA PW_LEVEL AHIGH_25_:1 -DATA SLEW AHIGH_25_:0 -DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 -DATA SLEW AMIGA_ADDR_ENABLE:0 -DATA PW_LEVEL AHIGH_24_:1 -DATA SLEW AHIGH_24_:0 -DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1 -DATA SLEW AMIGA_BUS_DATA_DIR:0 -DATA PW_LEVEL A_DECODE_22_:1 -DATA SLEW A_DECODE_22_:1 -DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1 -DATA SLEW AMIGA_BUS_ENABLE_LOW:0 -DATA PW_LEVEL A_DECODE_21_:1 -DATA SLEW A_DECODE_21_:1 -DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 -DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 -DATA PW_LEVEL A_DECODE_20_:1 -DATA SLEW A_DECODE_20_:1 -DATA PW_LEVEL CIIN:1 -DATA SLEW CIIN:0 -DATA PW_LEVEL A_DECODE_19_:1 -DATA SLEW A_DECODE_19_:1 -DATA PW_LEVEL A_DECODE_18_:1 -DATA SLEW A_DECODE_18_:1 -DATA PW_LEVEL A_DECODE_17_:1 -DATA SLEW A_DECODE_17_:1 -DATA PW_LEVEL A_DECODE_16_:1 -DATA SLEW A_DECODE_16_:1 -DATA PW_LEVEL A_0_:1 -DATA SLEW A_0_:0 DATA PW_LEVEL SIZE_1_:1 DATA SLEW SIZE_1_:0 -DATA PW_LEVEL IPL_030_1_:1 -DATA SLEW IPL_030_1_:0 -DATA PW_LEVEL IPL_030_0_:1 -DATA SLEW IPL_030_0_:0 DATA PW_LEVEL IPL_030_2_:1 DATA SLEW IPL_030_2_:0 DATA PW_LEVEL RW_000:1 @@ -294,30 +272,36 @@ DATA PW_LEVEL BG_000:1 DATA SLEW BG_000:0 DATA PW_LEVEL BGACK_030:1 DATA SLEW BGACK_030:0 -DATA PW_LEVEL SIZE_0_:1 -DATA SLEW SIZE_0_:0 +DATA PW_LEVEL A_0_:1 +DATA SLEW A_0_:0 +DATA PW_LEVEL IPL_030_1_:1 +DATA SLEW IPL_030_1_:0 +DATA PW_LEVEL IPL_030_0_:1 +DATA SLEW IPL_030_0_:0 DATA PW_LEVEL VMA:1 DATA SLEW VMA:0 DATA PW_LEVEL RW:1 DATA SLEW RW:0 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:0 +DATA PW_LEVEL cpu_est_0_:1 +DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:1 DATA SLEW cpu_est_1_:1 DATA PW_LEVEL cpu_est_2_:1 DATA SLEW cpu_est_2_:1 DATA PW_LEVEL cpu_est_3_:1 DATA SLEW cpu_est_3_:1 -DATA PW_LEVEL cpu_est_0_:1 -DATA SLEW cpu_est_0_:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA PW_LEVEL inst_AS_030_D0:1 DATA SLEW inst_AS_030_D0:1 +DATA PW_LEVEL inst_AS_030_D1:1 +DATA SLEW inst_AS_030_D1:1 DATA PW_LEVEL inst_AS_030_000_SYNC:1 DATA SLEW inst_AS_030_000_SYNC:1 -DATA PW_LEVEL inst_BGACK_030_INT_D:1 -DATA SLEW inst_BGACK_030_INT_D:1 DATA PW_LEVEL inst_AS_000_DMA:1 DATA SLEW inst_AS_000_DMA:1 DATA PW_LEVEL inst_DS_000_DMA:1 @@ -328,10 +312,6 @@ DATA PW_LEVEL CLK_000_D_3_:1 DATA SLEW CLK_000_D_3_:1 DATA PW_LEVEL inst_DTACK_D0:1 DATA SLEW inst_DTACK_D0:1 -DATA PW_LEVEL inst_RESET_OUT:1 -DATA SLEW inst_RESET_OUT:1 -DATA PW_LEVEL CLK_030_PE_1_:1 -DATA SLEW CLK_030_PE_1_:1 DATA PW_LEVEL inst_AMIGA_DS:1 DATA SLEW inst_AMIGA_DS:1 DATA PW_LEVEL CLK_000_D_1_:1 @@ -352,12 +332,14 @@ DATA PW_LEVEL CLK_000_D_2_:1 DATA SLEW CLK_000_D_2_:1 DATA PW_LEVEL CLK_000_D_4_:1 DATA SLEW CLK_000_D_4_:1 -DATA PW_LEVEL inst_LDS_000_INT:1 -DATA SLEW inst_LDS_000_INT:1 -DATA PW_LEVEL inst_DS_000_ENABLE:1 -DATA SLEW inst_DS_000_ENABLE:1 DATA PW_LEVEL inst_UDS_000_INT:1 DATA SLEW inst_UDS_000_INT:1 +DATA PW_LEVEL inst_DS_000_ENABLE:1 +DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL inst_LDS_000_INT:1 +DATA SLEW inst_LDS_000_INT:1 +DATA PW_LEVEL inst_BGACK_030_INT_D:1 +DATA SLEW inst_BGACK_030_INT_D:1 DATA PW_LEVEL SM_AMIGA_6_:1 DATA SLEW SM_AMIGA_6_:1 DATA PW_LEVEL SM_AMIGA_4_:1 @@ -370,14 +352,6 @@ DATA PW_LEVEL CYCLE_DMA_0_:1 DATA SLEW CYCLE_DMA_0_:1 DATA PW_LEVEL CYCLE_DMA_1_:1 DATA SLEW CYCLE_DMA_1_:1 -DATA PW_LEVEL CLK_030_PE_0_:1 -DATA SLEW CLK_030_PE_0_:1 -DATA PW_LEVEL RST_DLY_0_:1 -DATA SLEW RST_DLY_0_:1 -DATA PW_LEVEL RST_DLY_1_:1 -DATA SLEW RST_DLY_1_:1 -DATA PW_LEVEL RST_DLY_2_:1 -DATA SLEW RST_DLY_2_:1 DATA PW_LEVEL inst_DSACK1_INT:1 DATA SLEW inst_DSACK1_INT:1 DATA PW_LEVEL inst_AS_000_INT:1 @@ -388,21 +362,17 @@ DATA PW_LEVEL SM_AMIGA_3_:1 DATA SLEW SM_AMIGA_3_:1 DATA PW_LEVEL SM_AMIGA_2_:1 DATA SLEW SM_AMIGA_2_:1 -DATA PW_LEVEL SM_AMIGA_i_7_:1 -DATA SLEW SM_AMIGA_i_7_:1 DATA PW_LEVEL CLK_OUT_INTreg:1 DATA SLEW CLK_OUT_INTreg:1 -DATA PW_LEVEL CIIN_0:1 -DATA SLEW CIIN_0:1 -DATA PW_LEVEL RN_A_0_:1 -DATA PW_LEVEL RN_SIZE_1_:1 -DATA PW_LEVEL RN_IPL_030_1_:1 -DATA PW_LEVEL RN_IPL_030_0_:1 +DATA PW_LEVEL SM_AMIGA_i_7_:1 +DATA SLEW SM_AMIGA_i_7_:1 +DATA PW_LEVEL N_60:1 +DATA SLEW N_60:1 DATA PW_LEVEL RN_IPL_030_2_:1 DATA PW_LEVEL RN_RW_000:1 DATA PW_LEVEL RN_BG_000:1 DATA PW_LEVEL RN_BGACK_030:1 -DATA PW_LEVEL RN_SIZE_0_:1 +DATA PW_LEVEL RN_IPL_030_1_:1 +DATA PW_LEVEL RN_IPL_030_0_:1 DATA PW_LEVEL RN_VMA:1 -DATA PW_LEVEL RN_RW:1 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 6fb8d15..f3a8101 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,24 +1,22 @@ -GROUP MACH_SEG_A DS_030 AVEC inst_DS_000_DMA CLK_030_PE_1_ CLK_030_PE_0_ - inst_AS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT SM_AMIGA_4_ - SM_AMIGA_0_ -GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ AHIGH_31_ AHIGH_30_ AHIGH_29_ CLK_EXP inst_AS_030_000_SYNC - inst_DTACK_D0 IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ -GROUP MACH_SEG_C AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AMIGA_BUS_ENABLE_LOW - SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE inst_AS_000_INT inst_AMIGA_DS - CLK_000_D_4_ -GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 AMIGA_BUS_ENABLE_HIGH LDS_000 - UDS_000 DTACK AMIGA_ADDR_ENABLE cpu_est_3_ cpu_est_1_ cpu_est_2_ - CLK_000_D_0_ CLK_OUT_INTreg -GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 inst_CLK_OUT_PRE_D +GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ SM_AMIGA_3_ cpu_est_3_ SM_AMIGA_1_ + SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH IPL_D0_0_ IPL_D0_2_ CLK_OUT_INTreg -GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_6_ inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH - inst_AMIGA_BUS_ENABLE_DMA_LOW SM_AMIGA_1_ inst_UDS_000_INT inst_VPA_D - CLK_000_D_3_ -GROUP MACH_SEG_G SIZE_0_ RN_SIZE_0_ A_0_ RN_A_0_ RW RN_RW E CLK_DIV_OUT - inst_RESET_OUT RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ SM_AMIGA_5_ cpu_est_0_ - inst_CLK_OUT_PRE_50 -GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS SIZE_1_ RN_SIZE_1_ BGACK_030 RN_BGACK_030 - AS_030 DSACK1 inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_D_2_ CLK_000_D_1_ +GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ + RN_IPL_030_2_ CLK_EXP AHIGH_31_ AHIGH_30_ AHIGH_29_ CYCLE_DMA_0_ + CYCLE_DMA_1_ inst_UDS_000_INT +GROUP MACH_SEG_C AMIGA_BUS_ENABLE_LOW AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ + AHIGH_24_ inst_AS_000_DMA inst_DS_000_DMA inst_DS_000_ENABLE inst_AS_000_INT + inst_AMIGA_BUS_ENABLE_DMA_LOW +GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 AMIGA_BUS_ENABLE_HIGH LDS_000 + UDS_000 AMIGA_ADDR_ENABLE cpu_est_1_ cpu_est_2_ IPL_D0_1_ CLK_000_D_0_ + +GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 N_60 inst_AS_030_D0 + inst_BGACK_030_INT_D inst_CLK_OUT_PRE_D +GROUP MACH_SEG_F inst_AS_030_000_SYNC SM_AMIGA_i_7_ SM_AMIGA_6_ SM_AMIGA_5_ + inst_AS_030_D1 inst_DTACK_D0 CLK_000_D_3_ CLK_000_D_4_ +GROUP MACH_SEG_G SIZE_0_ E A_0_ RW CLK_DIV_OUT inst_LDS_000_INT inst_DSACK1_INT + SM_AMIGA_4_ cpu_est_0_ inst_VPA_D +GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS BGACK_030 RN_BGACK_030 SIZE_1_ + DSACK1 AS_030 inst_AMIGA_DS inst_CLK_OUT_PRE_50 CLK_000_D_2_ CLK_000_D_1_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 091112f..c99e83f 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -6050655){ N +7022=02GQV \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index a7544f4..72d0cd8 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Thu Dec 29 16:02:00 2016 +DATE: Sat Dec 30 00:43:46 2017 ABEL mach447a * @@ -31,75 +31,72 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS AHIGH_31_:4 IPL_1_:56 IPL_0_:67 A_DECODE_23_:85* -NOTE PINS FC_0_:57 A_1_:60 IPL_2_:68 FC_1_:58 AS_030:82 AS_000:42* -NOTE PINS DS_030:98 UDS_000:32 LDS_000:31 nEXP_SPACE:14 BERR:41* -NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* -NOTE PINS CLK_DIV_OUT:65 CLK_EXP:10 FPU_CS:78 FPU_SENSE:91* -NOTE PINS DSACK1:81 DTACK:30 AVEC:92 E:66 AHIGH_30_:5 VPA:36* -NOTE PINS AHIGH_29_:6 AHIGH_28_:15 RST:86 AHIGH_27_:16 RESET:3* -NOTE PINS AHIGH_26_:17 AHIGH_25_:18 AMIGA_ADDR_ENABLE:33* -NOTE PINS AHIGH_24_:19 AMIGA_BUS_DATA_DIR:48 A_DECODE_22_:84* -NOTE PINS AMIGA_BUS_ENABLE_LOW:20 A_DECODE_21_:94 AMIGA_BUS_ENABLE_HIGH:34* -NOTE PINS A_DECODE_20_:93 CIIN:47 A_DECODE_19_:97 A_DECODE_18_:95* -NOTE PINS A_DECODE_17_:59 A_DECODE_16_:96 A_0_:69 SIZE_1_:79* -NOTE PINS IPL_030_1_:7 IPL_030_0_:8 IPL_030_2_:9 RW_000:80* -NOTE PINS BG_000:29 BGACK_030:83 SIZE_0_:70 VMA:35 RW:71* +NOTE PINS AHIGH_27_:16 AHIGH_26_:17 AHIGH_25_:18 AHIGH_24_:19* +NOTE PINS AHIGH_31_:4 A_DECODE_22_:84 A_DECODE_21_:94 A_DECODE_23_:85* +NOTE PINS A_DECODE_20_:93 A_DECODE_19_:97 A_DECODE_18_:95* +NOTE PINS A_DECODE_17_:59 A_DECODE_16_:96 IPL_2_:68 FC_1_:58* +NOTE PINS AS_030:82 AS_000:42 DS_030:98 UDS_000:32 LDS_000:31* +NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28 CLK_000:11* +NOTE PINS IPL_1_:56 CLK_OSZI:61 IPL_0_:67 CLK_DIV_OUT:65* +NOTE PINS FC_0_:57 CLK_EXP:10 A_1_:60 FPU_CS:78 FPU_SENSE:91* +NOTE PINS DSACK1:81 DTACK:30 AVEC:92 E:66 VPA:36 RST:86 AMIGA_ADDR_ENABLE:33* +NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 AHIGH_30_:5 AHIGH_29_:6 AHIGH_28_:15 SIZE_1_:79* +NOTE PINS IPL_030_2_:9 RW_000:80 BG_000:29 BGACK_030:83 A_0_:69* +NOTE PINS IPL_030_1_:7 IPL_030_0_:8 VMA:35 RW:71 SIZE_0_:70* NOTE Table of node names and numbers* -NOTE NODES RN_AHIGH_31_:143 RN_AS_030:281 RN_AS_000:203 * -NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 RN_DTACK:173 * -NOTE NODES RN_AHIGH_30_:125 RN_AHIGH_29_:137 RN_AHIGH_28_:149 * NOTE NODES RN_AHIGH_27_:157 RN_AHIGH_26_:155 RN_AHIGH_25_:167 * -NOTE NODES RN_AHIGH_24_:161 RN_A_0_:257 RN_SIZE_1_:287 RN_IPL_030_1_:139 * -NOTE NODES RN_IPL_030_0_:133 RN_IPL_030_2_:131 RN_RW_000:269 * -NOTE NODES RN_BG_000:175 RN_BGACK_030:275 RN_SIZE_0_:263 * -NOTE NODES RN_VMA:179 RN_RW:245 cpu_est_1_:182 cpu_est_2_:194 * -NOTE NODES cpu_est_3_:176 cpu_est_0_:259 inst_AMIGA_BUS_ENABLE_DMA_HIGH:235 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_LOW:229 inst_AS_030_D0:272 * -NOTE NODES inst_AS_030_000_SYNC:145 inst_BGACK_030_INT_D:289 * -NOTE NODES inst_AS_000_DMA:113 inst_DS_000_DMA:121 inst_VPA_D:224 * -NOTE NODES CLK_000_D_3_:241 inst_DTACK_D0:146 inst_RESET_OUT:253 * -NOTE NODES CLK_030_PE_1_:104 inst_AMIGA_DS:164 CLK_000_D_1_:277 * -NOTE NODES CLK_000_D_0_:193 inst_CLK_OUT_PRE_50:248 inst_CLK_OUT_PRE_D:209 * -NOTE NODES IPL_D0_0_:140 IPL_D0_1_:134 IPL_D0_2_:128 CLK_000_D_2_:278 * -NOTE NODES CLK_000_D_4_:170 inst_LDS_000_INT:239 inst_DS_000_ENABLE:169 * -NOTE NODES inst_UDS_000_INT:223 SM_AMIGA_6_:221 SM_AMIGA_4_:103 * -NOTE NODES SM_AMIGA_1_:233 SM_AMIGA_0_:119 CYCLE_DMA_0_:110 * -NOTE NODES CYCLE_DMA_1_:116 CLK_030_PE_0_:115 RST_DLY_0_:254 * -NOTE NODES RST_DLY_1_:266 RST_DLY_2_:260 inst_DSACK1_INT:109 * -NOTE NODES inst_AS_000_INT:152 SM_AMIGA_5_:265 SM_AMIGA_3_:158 * -NOTE NODES SM_AMIGA_2_:163 SM_AMIGA_i_7_:227 CLK_OUT_INTreg:188 * -NOTE NODES CIIN_0:205 * +NOTE NODES RN_AHIGH_24_:161 RN_AHIGH_31_:143 RN_AS_030:281 * +NOTE NODES RN_AS_000:203 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * +NOTE NODES RN_AHIGH_30_:125 RN_AHIGH_29_:137 RN_AHIGH_28_:149 * +NOTE NODES RN_SIZE_1_:287 RN_IPL_030_2_:131 RN_RW_000:269 * +NOTE NODES RN_BG_000:175 RN_BGACK_030:275 RN_A_0_:257 RN_IPL_030_1_:139 * +NOTE NODES RN_IPL_030_0_:133 RN_VMA:173 RN_RW:245 RN_SIZE_0_:263 * +NOTE NODES cpu_est_0_:259 cpu_est_1_:193 cpu_est_2_:176 * +NOTE NODES cpu_est_3_:113 inst_AMIGA_BUS_ENABLE_DMA_HIGH:116 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_LOW:164 inst_AS_030_D0:209 * +NOTE NODES inst_AS_030_D1:223 inst_AS_030_000_SYNC:227 inst_AS_000_DMA:169 * +NOTE NODES inst_DS_000_DMA:163 inst_VPA_D:254 CLK_000_D_3_:241 * +NOTE NODES inst_DTACK_D0:235 inst_AMIGA_DS:272 CLK_000_D_1_:277 * +NOTE NODES CLK_000_D_0_:187 inst_CLK_OUT_PRE_50:289 inst_CLK_OUT_PRE_D:205 * +NOTE NODES IPL_D0_0_:110 IPL_D0_1_:182 IPL_D0_2_:104 CLK_000_D_2_:278 * +NOTE NODES CLK_000_D_4_:229 inst_UDS_000_INT:134 inst_DS_000_ENABLE:152 * +NOTE NODES inst_LDS_000_INT:265 inst_BGACK_030_INT_D:217 * +NOTE NODES SM_AMIGA_6_:221 SM_AMIGA_4_:253 SM_AMIGA_1_:109 * +NOTE NODES SM_AMIGA_0_:119 CYCLE_DMA_0_:145 CYCLE_DMA_1_:128 * +NOTE NODES inst_DSACK1_INT:248 inst_AS_000_INT:158 SM_AMIGA_5_:239 * +NOTE NODES SM_AMIGA_3_:121 SM_AMIGA_2_:115 CLK_OUT_INTreg:103 * +NOTE NODES SM_AMIGA_i_7_:233 N_60:211 * NOTE BLOCK 0 * L000000 - 111111111011111111111111101111111111111111111111111111111111111111 - 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111111111111110111111111111111111111111111010111111011101111111111* +L005610 111111111111111011111111111111111110111111111111110111011111111111* L005676 - 111111111110111111111111111111111111111111111110111111111111111101* -L005742 111111111111011111111111111111110111111111111111110111111111101111* -L005808 111111111011101111111111111111111111111111111111110111111111111111* -L005874 111111111111101111111111111111111111111111110111110111111111111111* -L005940 111110111111101111111111111111111111111111111111110111111111111111* -L006006 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111110111111111111111111111111* +L005742 111111111111111111111111111111111111111111111111111111111111111111* +L005808 111111111111111111111111111111111111111111111111111111111111111111* +L005874 111111111111111111111111111111111111111111111111111111111111111111* +L005940 111111111111111111111111111111111111111111111111111111111111111111* +L006006 111111111111111111111111111111111111111111111111111111111111111111* L006072 111111111111111111111111111111111111111111111111111111111111111111* L006138 111111111111111111111111111111111111111111111111111111111111111111* L006204 111111111111111111111111111111111111111111111111111111111111111111* @@ -182,32 +179,32 @@ L006402 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* L006538 01100011111000* -L006552 10100110010011* -L006566 10100110010101* +L006552 00100110010011* +L006566 01010110010101* L006580 11101011111111* -L006594 00000011111000* -L006608 11100110010010* -L006622 10100110010001* -L006636 11011011110011* +L006594 00110011111000* +L006608 10100110010010* +L006622 01010110010001* +L006636 11101011110011* L006650 10100110010000* -L006664 11100110010011* -L006678 10100110010001* -L006692 11000011110011* +L006664 10100110010011* +L006678 01010110010001* +L006692 11100011110011* L006706 10100110010000* -L006720 10100110010010* -L006734 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101111111111111111111111111111111111111011111111111111111111111111 - 111111111111111111111111111110111111111111101111111111111111111111* + 111111111111110111111111111111011111111111111111111111111111111111 + 111111110111111111111111111011111111111110111111111111111111111111 + 111111111111111111011111111111111111111111101111110110111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* L007422 000000000000000000000000000000000000000000000000000000000000000000* @@ -215,90 +212,90 @@ L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* L007686 000000000000000000000000000000000000000000000000000000000000000000* -L007752 111111111111111111111111111111111111111101111111111111111111111111* +L007752 111111111111111111011111111111111111111111111111111111111111111111* L007818 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111111111111111111111111111111110111111111011111101111101111111111* -L009006 111111101111111111111111111111111111111111011101111111101111111111* -L009072 111111011111111111111111111111111111111111011110111111101111111111* -L009138 111111111111111111111111111111111111101111011111111111101111111111* -L009204 111111101111111111111111111111111011011111010110101111111111111111* -L009270 111111101111111111111111111111111011101111011010101111111111111111* -L009336 111111011111111111111111111111111011011111010101101111111111111111* -L009402 111111011111111111111111111111111011101111011001101111111111111111* +L008874 111111111111111111111111111111011011111111011111111111101111111111* +L008940 111111111111111111111111111111100111111111011111111111101111111111* +L009006 111111100111111111111111111111111111111111011111111111101111111111* +L009072 111111011011111111111111111111111111111111011111111111101111111111* +L009138 111111111111111111111111111111111111111111011111111011101111111111* +L009204 111111010111111111111111111111101011111111011011111011111111111111* +L009270 111111101011111111111111111111101011111111011011111011111111111111* +L009336 111111101011111111111111111111101011111111010111110111111111111111* +L009402 111111010111111111111111111111101011111111010111110111111111111111* L009468 111111111111111111111111111111111011111111011111111111111011111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111101111111111111111111111111111111111011111111111111111111111* -L009666 111111111111111111111111111111111111111111011111101111111011111111* -L009732 111111101111111111111111111111111111111111011101111111111011111111* -L009798 111111011111111111111111111111111111111111011110111111111011111111* -L009864 111111111111111111111111111111111111011111011011111111111011111111* -L009930 111111111111111111111111111111111111101111010111111111111011111111* -L009996 000000000000000000000000000000000000000000000000000000000000000000* -L010062 000000000000000000000000000000000000000000000000000000000000000000* -L010128 000000000000000000000000000000000000000000000000000000000000000000* -L010194 000000000000000000000000000000000000000000000000000000000000000000* +L009600 111110111110111111111111111111111111111111011111111111111111111111* +L009666 101111111101111111111111111111111111111111011111111111111111111111* +L009732 000000000000000000000000000000000000000000000000000000000000000000* +L009798 000000000000000000000000000000000000000000000000000000000000000000* +L009864 000000000000000000000000000000000000000000000000000000000000000000* +L009930 111111111111111111111111111111101111111111011111111111111011111111* +L009996 111111100111111111111111111111111111111111011111111111111011111111* +L010062 111111011011111111111111111111111111111111011111111111111011111111* +L010128 111111111111111111111111111111111111111111011011110111111011111111* +L010194 111111111111111111111111111111111111111111010111111011111011111111* L010260 - 101101111110111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L010326 000000000000000000000000000000000000000000000000000000000000000000* L010392 111111111111111111111111111111111111111111111111111111111111111111* L010458 111111111111111111111111111111111111111111111111111111111111111111* L010524 111111111111111111111111111111111111111111111111111111111111111111* L010590 111111111111111111111111111111111111111111111111111111111111111111* -L010656 111111101111111111111111111111110111011111010110011111111111111111* -L010722 111111101111111111111111111111111011011111010110101111111111111111* -L010788 111111101111111111111111111111110111101111011010011111111111111111* -L010854 111111101111111111111111111111111011101111011010101111111111111111* +L010656 111111101011111111111111111111010111111111011011111011111111111111* +L010722 111111101011111111111111111111101011111111011011111011111111111111* +L010788 111111101011111111111111111111010111111111010111110111111111111111* +L010854 111111101011111111111111111111101011111111010111110111111111111111* L010920 111111101111101111111111111111111111111111011111111111111111111111* L010986 - 101101111110111111111111111111111111111111111111111111111111111111* -L011052 111111111111111111111111111111111011111111011111111111111111111111* -L011118 111111111111101111111111111111111011111111011111011111111111111111* -L011184 111111111111101111111111111111110111111111011111101111111111111111* -L011250 111111111111101111111111111111111111111111011110111111111111111111* -L011316 111111111111101111111111111111111111011111011011111111111111111111* -L011382 111111111111101111111111111111111111101111010111111111111111111111* -L011448 000000000000000000000000000000000000000000000000000000000000000000* -L011514 000000000000000000000000000000000000000000000000000000000000000000* -L011580 000000000000000000000000000000000000000000000000000000000000000000* -L011646 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111110111111111111111111111111* +L011052 111111111111101111111111111111011011111111011111111111111111111111* +L011118 111111111111101111111111111111100111111111011111111111111111111111* +L011184 111111111011101111111111111111111111111111011111111111111111111111* +L011250 111111111111101111111111111111111111111111011011110111111111111111* +L011316 111111111111101111111111111111111111111111010111111011111111111111* +L011382 111111111111111111111111111111111111111111111111111111111111111111* +L011448 111111111111111111111111111111111111111111111111111111111111111111* +L011514 111111111111111111111111111111111111111111111111111111111111111111* +L011580 111111111111111111111111111111111111111111111111111111111111111111* +L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 - 101101111110111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L011778 000000000000000000000000000000000000000000000000000000000000000000* L011844 111111111111111111111111111111111111111111111111111111111111111111* L011910 111111111111111111111111111111111111111111111111111111111111111111* L011976 111111111111111111111111111111111111111111111111111111111111111111* L012042 111111111111111111111111111111111111111111111111111111111111111111* -L012108 111111111111111111111011111111111111111011011111111111111111111111* -L012174 011011111101110111111111111110111111111011011111111111111110111111* -L012240 011111111101110111111111011110111111111011011111111111111110111111* -L012306 011111110101110111111111111110111111111011011111111111111110111111* -L012372 011111111101110110111111111110111111111011011111111111111110111111* +L012108 111111111111111111110111111011111111111110011111111110111111111111* +L012174 111111111111110111110111111111111111111110011111111110111111111111* +L012240 111111111111111011111011110111111111111110011111111110111111111111* +L012306 111111111111111111110111111111111111011110011111111110111111111111* +L012372 000000000000000000000000000000000000000000000000000000000000000000* L012438 000000000000000000000000000000000000000000000000000000000000000000* -L012504 111111111111111111101111111111111111111111011111111111111111111111* -L012570 011111111101110111111101111110111111111011011111111111111110111111* -L012636 011111111101110111111111111110111110111011011111111111111110111111* -L012702 000000000000000000000000000000000000000000000000000000000000000000* -L012768 000000000000000000000000000000000000000000000000000000000000000000* +L012504 111111111111111111111111111111111111111111111111111111111111111111* +L012570 111111111111111111111111111111111111111111111111111111111111111111* +L012636 111111111111111111111111111111111111111111111111111111111111111111* +L012702 111111111111111111111111111111111111111111111111111111111111111111* +L012768 111111111111111111111111111111111111111111111111111111111111111111* L012834 111111111111111111111111111111111111111111111111111111111111111111* L012900 111111111111111111111111111111111111111111111111111111111111111111* L012966 111111111111111111111111111111111111111111111111111111111111111111* @@ -310,48 +307,48 @@ L013164 L013296 0010* L013300 00100011111000* L013314 00101111111111* -L013328 01010110010100* +L013328 10100110010100* L013342 11011111111110* L013356 11100110011000* L013370 11100110011111* -L013384 01110110011100* +L013384 11100110011100* L013398 11001011111110* L013412 00110011110000* L013426 11100110010011* -L013440 01110110010111* -L013454 11001011110011* -L013468 00111111110000* -L013482 11100110010010* -L013496 01110110010001* -L013510 11100011110011* +L013440 11111011110111* +L013454 11111111110011* +L013468 00110011110000* +L013482 10100110010010* +L013496 11011011110001* +L013510 11111111111111* NOTE BLOCK 2 * L013524 - 011101111111101111111111111111111111111101111111111111111111111111 - 111111011101111111111110111111111111111111111111111111101111111111 - 111111111111111111101111111111111111011111111111111111111111111111 - 111111111111111111111111111111101111111111110111111111111111111111 - 111111111111111111110111111111111111111111111111111011111111111111 - 110111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111011111111111111111 - 111111110111111101111111111001111111111011111110111111111111111111 - 111111111111111111111111011111110110111111101111111111111111111111* + 111111111111111111111101111111111111111111011111111111111111111111 + 111111111111111101111111110111111111111111111111111011111111111111 + 111111111111111111011111111111111111111111111111111111111111111111 + 111101111111111111110111111111111111111111111011111111111111111111 + 111111101110111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111100111111111111111111111111111111111111111111111111111 + 111111111111111111111111111110111111111010111111111111101111111111 + 101111111011111111111111011111111011111111111111111111111111111111* L014118 - 111101111110111111111111111111111111111111111110111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L014184 000000000000000000000000000000000000000000000000000000000000000000* L014250 000000000000000000000000000000000000000000000000000000000000000000* L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 111111111111111111101111111111111111111111111110111111111111111111* +L014514 111111111111111110111111111111111111111110111111111111111111111111* L014580 000000000000000000000000000000000000000000000000000000000000000000* L014646 000000000000000000000000000000000000000000000000000000000000000000* L014712 000000000000000000000000000000000000000000000000000000000000000000* L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 - 111101111110111111111111111111111111111111111110111111111111111111* -L014910 110111111111111111111111111011111111111111011111110111111111111111* -L014976 111111111111111111111111111111111111111011011011111111111111111111* -L015042 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111110111111111111111111111111* +L014910 011111111111110111111111111111111111111111110111111111101111111111* +L014976 011101111111111111111111111111111111111011111111111111111111111111* +L015042 011111111101110111111111111111111111111111111111110111101111111111* L015108 000000000000000000000000000000000000000000000000000000000000000000* L015174 000000000000000000000000000000000000000000000000000000000000000000* L015240 111111111111111111111111111111111111111111111111111111111111111111* @@ -360,7 +357,7 @@ L015372 111111111111111111111111111111111111111111111111111111111111111111* L015438 111111111111111111111111111111111111111111111111111111111111111111* L015504 111111111111111111111111111111111111111111111111111111111111111111* L015570 - 111101111110111111111111111111111111111111111110111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L015636 000000000000000000000000000000000000000000000000000000000000000000* L015702 111111111111111111111111111111111111111111111111111111111111111111* L015768 111111111111111111111111111111111111111111111111111111111111111111* @@ -372,33 +369,33 @@ L016098 111111111111111111111111111111111111111111111111111111111111111111* L016164 111111111111111111111111111111111111111111111111111111111111111111* L016230 111111111111111111111111111111111111111111111111111111111111111111* L016296 - 111101111110111111111111111111111111111111111110111111111111111111* -L016362 111111111111111111111111111111111111011111101111111111111111111111* -L016428 111011111011111111111011110110100111011111111111111111101111111111* -L016494 111011111111111111111111110111011111011110111111111111111111111111* -L016560 110111111111111111111111011011111111101111011111111111111111111111* -L016626 111011111111111111111111110111111110011111111111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* +L016362 011111111101110111111111111111111111111111111111111111101111111111* +L016428 011111111111111111101111111111111111111011111111111111111111111111* +L016494 000000000000000000000000000000000000000000000000000000000000000000* +L016560 000000000000000000000000000000000000000000000000000000000000000000* +L016626 000000000000000000000000000000000000000000000000000000000000000000* L016692 111111111111111111111111111111111111111111111111111111111111111111* L016758 111111111111111111111111111111111111111111111111111111111111111111* L016824 111111111111111111111111111111111111111111111111111111111111111111* L016890 111111111111111111111111111111111111111111111111111111111111111111* L016956 111111111111111111111111111111111111111111111111111111111111111111* L017022 - 111101111110111111111111111111111111111111111110111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L017088 000000000000000000000000000000000000000000000000000000000000000000* L017154 111111111111111111111111111111111111111111111111111111111111111111* L017220 111111111111111111111111111111111111111111111111111111111111111111* L017286 111111111111111111111111111111111111111111111111111111111111111111* L017352 111111111111111111111111111111111111111111111111111111111111111111* -L017418 111011111011111111111011110110100111011111011111111111101111111111* -L017484 111011111111111111111111110111011111011110011111111111111111111111* -L017550 111111011111111111111111110111111111111111011111111111111111111111* -L017616 111011011111111111111111111111111111111111011111111111111111111111* -L017682 111011111111111111111111110111111110011111011111111111111111111111* +L017418 101111111111111111111111111111111111111111111111111111111111111111* +L017484 111111110111111111111111111111111111111111111111111111111111111111* +L017550 111111111111111111111011111111111111111111101111111111111111111111* +L017616 111111111111111111111111111111110111111111111111111111111111111111* +L017682 111111111111101111110111111111111111111111011111111111111111111111* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 111111111111111111111111111111111111111111101111111111111111111111* -L017880 111111111111111101111111111111111111111111111111011111111111111111* +L017814 011111011111111111111111111111111111111110111111111111111111111111* +L017880 111111111111111111111111100101111111111111111111111111111111111111* L017946 000000000000000000000000000000000000000000000000000000000000000000* L018012 000000000000000000000000000000000000000000000000000000000000000000* L018078 000000000000000000000000000000000000000000000000000000000000000000* @@ -414,18 +411,18 @@ L018606 111111111111111111111111111111111111111111111111111111111111111111* L018672 111111111111111111111111111111111111111111111111111111111111111111* L018738 111111111111111111111111111111111111111111111111111111111111111111* L018804 111111111111111111111111111111111111111111111111111111111111111111* -L018870 110111111111111111111111011011111111111111011111111111111111111111* -L018936 011111111111111111111111111111111111111011011111111111111111111111* -L019002 110111111111111111111101111011111111111111011111110111111111111111* -L019068 000000000000000000000000000000000000000000000000000000000000000000* -L019134 000000000000000000000000000000000000000000000000000000000000000000* +L018870 101111111111111111111111111111111111111111111111111111111111111111* +L018936 111111110111111111111111111111111111111111111111111111111111111111* +L019002 111111111111111111111011111111111111111111101111111111111111111111* +L019068 111111111111111111111101101101111111111111111111111111111111111111* +L019134 111111111111111111111111111111110111111111111111111111111111111111* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 111111111111011111111111111111111111111111111111111111111111111111* -L019332 111111111111111111111111111111111111111111111111111111111111111111* -L019398 111111111111111111111111111111111111111111111111111111111111111111* -L019464 111111111111111111111111111111111111111111111111111111111111111111* -L019530 111111111111111111111111111111111111111111111111111111111111111111* +L019266 111111111111101111110111111111111111111111011111111111111111111111* +L019332 000000000000000000000000000000000000000000000000000000000000000000* +L019398 000000000000000000000000000000000000000000000000000000000000000000* +L019464 000000000000000000000000000000000000000000000000000000000000000000* +L019530 000000000000000000000000000000000000000000000000000000000000000000* L019596 111111111111111111111111111111111111111111111111111111111111111111* L019662 111111111111111111111111111111111111111111111111111111111111111111* L019728 111111111111111111111111111111111111111111111111111111111111111111* @@ -437,49 +434,49 @@ L019926 L020058 0010* L020062 00100011110000* L020076 01101111110011* -L020090 11100110011100* +L020090 10100110011100* L020104 11101111110010* L020118 00111011110000* L020132 00000011110011* -L020146 10100111010110* +L020146 11100110010110* L020160 11100011110010* L020174 00111111110001* L020188 10100110010011* -L020202 10100110011110* +L020202 01110110011110* L020216 11100011111111* L020230 00111011111001* L020244 10100110010011* -L020258 00010110010000* -L020272 11101111111111* +L020258 11110111110000* +L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111111111111111111101111101111110111111011111111111111111111111 - 111011110101111111111111101111111111111111111111111111111111111111 + 111111011111111111101111111111111111111111111111111111111111111111 + 111111110101111111111111101111111111111111111111111111111111111111 + 111111111111111111111101111111111111111111101110111111111111111111 + 111111111111111111111011111111111111111111110111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111101111111111111111111111111011111111111111111111 - 111111111111111111111111111111101111111111111111011111111111111111 - 111111111111111111111111111111111111111111111111111111111101111111 - 111111111111111110111111111111111111011111111111111111111111111111 - 111111111111111111110111111011110111111010111111111111111111111111 - 101101011111111111111111111111111111111111111111111111111011111111* + 111111111111111101111111111111111111111111111111111111111101111111 + 111111111111110111111111111111111111011111111111111111111111101111 + 111111111111111111111111111011111111111010111111111111111111111111 + 100101111111111111111111111111110111111111111111111111111111111111* L020880 - 111111111111111111111111111111111111111111111111111111111111111111* -L020946 000000000000000000000000000000000000000000000000000000000000000000* -L021012 000000000000000000000000000000000000000000000000000000000000000000* -L021078 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111101111111111111111111111111* +L020946 101011111111111111111111111111111111111111111111111111111111111111* +L021012 111011111111110111111111101011111011101111111111111111111110111111* +L021078 010111111111111011111111010111111011101111111110111111111101111111* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 011111111001111111111111111111111111111111111111111111110101111111* +L021276 011111111001110111111111111111111111111111111111111111111111011111* L021342 011110111011111111111111111111111111111111111111111111111111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111011111111111111111101111111111111111111111101111111111111111* -L021738 111111011111111111111111111011111111111111111111111111111111111111* -L021804 111111011111111111111111111111111111111111111111111111111101111111* -L021870 111111111111111111111111010111110111111111111111011111111110111111* +L021672 111111111111111111111111111111110111111111111111111111111111111111* +L021738 111111111111111011111111010111111111111111111111111111111101111111* +L021804 000000000000000000000000000000000000000000000000000000000000000000* +L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* L022002 111111111111111111111111111111111111111111111111111111111111111111* L022068 111111111111111111111111111111111111111111111111111111111111111111* @@ -488,43 +485,43 @@ L022200 111111111111111111111111111111111111111111111111111111111111111111* L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 101111111111111111111011111111111111111111111111111111111111111111* -L022464 111111101111111111111011101011111011111111111111101111111101111111* -L022530 011111101111111111100111010111110111111111111111101111111110111111* +L022398 111111111111111110111111111111111111111110111111111111111111111111* +L022464 111111111111111111111011111111111111111001111111111111111111111111* +L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* -L022728 111011111111111111111111111111111111111110111111111111111111111111* -L022794 111111111111111111111111111111111111111001101111111111111111111111* -L022860 000000000000000000000000000000000000000000000000000000000000000000* -L022926 000000000000000000000000000000000000000000000000000000000000000000* -L022992 000000000000000000000000000000000000000000000000000000000000000000* +L022728 000000000000000000000000000000000000000000000000000000000000000000* +L022794 111111111111111111111111111111111111111111111111111111111111111111* +L022860 111111111111111111111111111111111111111111111111111111111111111111* +L022926 111111111111111111111111111111111111111111111111111111111111111111* +L022992 111111111111111111111111111111111111111111111111111111111111111111* L023058 - 111111111111111111111111111111111111111101110111111111111111111111* -L023124 111111111111111111111111101111110111111111111111111111111111111111* -L023190 111111111111111111111111111011110111111111111111111111111111111111* -L023256 111111111111111111111111111111110111111111111111111111111101111111* -L023322 111111101111111111111111010111111011111111111111111111111110111111* -L023388 000000000000000000000000000000000000000000000000000000000000000000* + 011111111111111111111111111111111111111101111111111111111111111111* +L023124 011111111111111111111111111111111111111111101111111111111111111111* +L023190 111111111111111111111111111111111111111111111111111111111111111111* +L023256 111111111111111111111111111111111111111111111111111111111111111111* +L023322 111111111111111111111111111111111111111111111111111111111111111111* +L023388 111111111111111111111111111111111111111111111111111111111111111111* L023454 111111111111111111111111111111111111111111111111111111111111111111* L023520 111111111111111111111111111111111111111111111111111111111111111111* L023586 111111111111111111111111111111111111111111111111111111111111111111* L023652 111111111111111111111111111111111111111111111111111111111111111111* L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 111111111111111111111111111111111111111101110111111111111111111111* -L023850 111111111111111111111101111111101111111111111111111111111111111111* + 011111111111111111111111111111111111111101111111111111111111111111* +L023850 111111111111111111111110111111111111111111110111111111111111111111* L023916 111111111111111111111111111111111111111111111111111111111111111111* L023982 111111111111111111111111111111111111111111111111111111111111111111* L024048 111111111111111111111111111111111111111111111111111111111111111111* L024114 111111111111111111111111111111111111111111111111111111111111111111* -L024180 000000000000000000000000000000000000000000000000000000000000000000* +L024180 111111011111111111111111111111111111111111111111111111111111111111* L024246 111111111111111111111111111111111111111111111111111111111111111111* L024312 111111111111111111111111111111111111111111111111111111111111111111* L024378 111111111111111111111111111111111111111111111111111111111111111111* L024444 111111111111111111111111111111111111111111111111111111111111111111* L024510 - 111111111111111111111111111111111111101111111111111111111111111111* -L024576 111111111111111101111111111111111111111111111111111111111111111111* + 000000000000000000000000000000000000000000000000000000000000000000* +L024576 111111111111111111111111111111111111111111111111111111111111111111* L024642 111111111111111111111111111111111111111111111111111111111111111111* L024708 111111111111111111111111111111111111111111111111111111111111111111* L024774 111111111111111111111111111111111111111111111111111111111111111111* @@ -536,23 +533,23 @@ L025104 111111111111111111111111111111111111111111111111111111111111111111* L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111111111111101111111111110111111111111111111111111111111* +L025302 111111111111111111101111111111111111111111110111111111111111111111* L025368 111111111111111111111111111111111111111111111111111111111111111111* L025434 111111111111111111111111111111111111111111111111111111111111111111* L025500 111111111111111111111111111111111111111111111111111111111111111111* L025566 111111111111111111111111111111111111111111111111111111111111111111* -L025632 111111111111111111111111111101111111111111111111111111111111111111* -L025698 111111111111111111111111111111111111111111111111111111111111111111* -L025764 111111111111111111111111111111111111111111111111111111111111111111* -L025830 111111111111111111111111111111111111111111111111111111111111111111* -L025896 111111111111111111111111111111111111111111111111111111111111111111* +L025632 111111111111111111111111101111111111111111111111111111111101111111* +L025698 111111111111111111111111111011111111111111111111111111111101111111* +L025764 111111111111110111111111111111111111111111111111111111111101111111* +L025830 111111111111111011111111010111111111101111111111111111111110111111* +L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111111111111111111010111110111111111111111111111111110111111* -L026094 111111111111111111111111111111111111111111111111011111111111111111* -L026160 000000000000000000000000000000000000000000000000000000000000000000* -L026226 000000000000000000000000000000000000000000000000000000000000000000* -L026292 000000000000000000000000000000000000000000000000000000000000000000* +L026028 111111111111111111111111111111111111111111111111111111111111111111* +L026094 111111111111111111111111111111111111111111111111111111111111111111* +L026160 111111111111111111111111111111111111111111111111111111111111111111* +L026226 111111111111111111111111111111111111111111111111111111111111111111* +L026292 111111111111111111111111111111111111111111111111111111111111111111* L026358 111111111111111111111111111111111111111111111111111111111111111111* L026424 111111111111111111111111111111111111111111111111111111111111111111* L026490 111111111111111111111111111111111111111111111111111111111111111111* @@ -562,47 +559,47 @@ L026688 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L026820 0010* -L026824 00100011110010* -L026838 11100110011111* -L026852 10100110011101* -L026866 11101011111111* -L026880 10100111011010* -L026894 11101011111110* -L026908 10100110010101* +L026824 10100111010000* +L026838 11100110011110* +L026852 00100110010100* +L026866 11100011111111* +L026880 11101111111001* +L026894 00001011111111* +L026908 01010110010100* L026922 11101011110011* L026936 01110011110010* -L026950 00001011110010* -L026964 00010110010111* -L026978 11101111110011* +L026950 00000110010010* +L026964 11011011110001* +L026978 11111111110011* L026992 01110011111010* -L027006 00000110011110* -L027020 00100110010001* -L027034 11101011110011* +L027006 10100110011110* +L027020 11011011110001* +L027034 11111111110011* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111011111110111111111110111111111111111 - 111111111101111111111111110111111111111111110111101111111111111111 - 111001111111111111111111111111111111111111011110111101101111111110 + 111111111101111111111111111111111111111111111111110111110111111111 + 111111110111111111111111111111111111111101110111101111011111111111 + 111011011111111111111111111011111111111111111111111101111111111111 111111111111110111111111111111111111111111111111111111111111111111 - 111111110111111111111111011111111111111111111111111111111111111111 - 111111111111101111111101111111111101111111111111111111111111111111 - 101111011111111111101111111110111111111111111111111111111111110111 - 111111111111111101111111111111111011101110111111111111111011111111* + 111111111111111111111111011111111111011011111111111111111111111111 + 111111111111011111111111111110111001111111101111111111111111111111 + 111111111111111111101111111111011111111111111110111111111101111111 + 101110111111111101111110111111111111111111111111111111111111111110* L027642 - 110111110111111101101110101111111110111111111111011111011111111111* + 110111111111101101101111100111111110011111111111011111111111111111* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 101111111111011111111111111111101011111111111111111111111111111111* -L028104 011111111111101111111111111111111111111111111111111111111111111111* +L028038 111110111110111111111111111111111111111111011110111111111111111111* +L028104 111111111111111111111111111111111111111111101101111111111111111111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 011111111111111111111111111111111111111111111111111111111111111101* + 011111111111111111111111111111111111111111111101111111111111111111* L028434 111111111111111111111111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* @@ -615,16 +612,16 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111110111111111111101111111111111111111111111111111111111111111111* +L029160 111111111111111111101111111111111111111111111111111111101111111111* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 111111111111111111111111111111011111111111111111111111111111111111* -L029556 111111011110111011111111111011111111011001101011111010111011110111* -L029622 000000000000000000000000000000000000000000000000000000000000000000* -L029688 000000000000000000000000000000000000000000000000000000000000000000* -L029754 000000000000000000000000000000000000000000000000000000000000000000* +L029490 111111111111111111111111111111111111110111111111111111111111111111* +L029556 111111111111111111111111111111111111111111111111111111111111111111* +L029622 111111111111111111111111111111111111111111111111111111111111111111* +L029688 111111111111111111111111111111111111111111111111111111111111111111* +L029754 111111111111111111111111111111111111111111111111111111111111111111* L029820 000000000000000000000000000000000000000000000000000000000000000000* L029886 111111111111111111111111111111111111111111111111111111111111111111* @@ -639,16 +636,16 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 111111111111111111111111111111111111111111111101111111111111111111* +L030612 011111111111111111101111111111111111111111111111111111111111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111111111111111111111111111111111111111111111111111111111111111111* -L031008 111111111111111111111111111111111111111111111111111111111111111111* -L031074 111111111111111111111111111111111111111111111111111111111111111111* -L031140 111111111111111111111111111111111111111111111111111111111111111111* -L031206 111111111111111111111111111111111111111111111111111111111111111111* +L030942 111111101011111011111101111111011011111110111011111010111001111101* +L031008 111111111101111111111111111111111111111111111111111111111111111111* +L031074 000000000000000000000000000000000000000000000000000000000000000000* +L031140 000000000000000000000000000000000000000000000000000000000000000000* +L031206 000000000000000000000000000000000000000000000000000000000000000000* L031272 000000000000000000000000000000000000000000000000000000000000000000* L031338 111111111111111111111111111111111111111111111111111111111111111111* @@ -663,12 +660,12 @@ L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 111111111111111111111111111101111111111111111111111111111111111111* -L032064 111111011110111011111111111011111111011001101011111010111011110111* +L032064 111111101011111011111101111111011011111110111011111010111001111101* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* L032328 111111111111111111111111111111111111111111111111111111111111111111* -L032394 111111111111111111111111111111111111111111111111111111111111111111* +L032394 011111111111111111111111111111111111111111111110111111111111111111* L032460 111111111111111111111111111111111111111111111111111111111111111111* L032526 111111111111111111111111111111111111111111111111111111111111111111* L032592 111111111111111111111111111111111111111111111111111111111111111111* @@ -692,45 +689,45 @@ L033582 0010* L033586 00100011110000* L033600 10101111110011* L033614 11011011110100* -L033628 11111111110010* -L033642 01111011111001* -L033656 10101111111110* -L033670 11011011110000* -L033684 11111111111110* -L033698 00110110010001* -L033712 11001011111110* -L033726 11110111110000* -L033740 11111111111110* -L033754 00110011110001* -L033768 11001011111110* -L033782 11110111111100* -L033796 11111111111110* +L033628 11110011110010* +L033642 01111111111001* +L033656 00000110011111* +L033670 11010111110000* +L033684 11110011111111* +L033698 01110110010000* +L033712 10100111111110* +L033726 11011111110000* +L033740 11110011111111* +L033754 00111011110001* +L033768 01000110011111* +L033782 11010111111100* +L033796 11111111111111* NOTE BLOCK 5 * L033810 - 111111111111100111111111111111111110111111011111111111111111111111 - 101111011101111111111111111111111111101111111111111111111111111111 - 111110111111111111111111111110101111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111110111111 - 111111111111111111111010111111111111111111111111111011111111111111 - 110111111111111111011111111111111111111011111111111111101111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111011111111111111111111111111111110111111111111111111101111 - 111111111111111111111111110111111111111111111111101111111111111111* + 111111111111111111111111111111101110111111111111111111111111111111 + 111111111101111111111111111111111111111111111111111111111111111111 + 111111111111101111111111111110111111111110111111111111111111111111 + 111011111111111110111111111111111111111111111111111111111110111111 + 111111111111111111111011111111111111111111111111111011111111111111 + 111110111111111111111111011111111111111111111111011111111111111111 + 111111110111110111011101111111111011111111111111111111111111111111 + 111111111111111111111111111011111111111011101110111111111111111111 + 101111111111111111111111111111111111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111110111111111111111111111111111111111111111010111111111111111* -L034536 111011111111111111111111111111111111111111111111010111111111111111* -L034602 111111111101100111111111111111111111111111101111011011111110111111* +L034470 011111111111111111111111110111111111111111111111110111111111111111* +L034536 011111111111111011111111111111111111111111111111110111111111111111* +L034602 011111111101111111111111111101101111111110111111111011111110111111* L034668 000000000000000000000000000000000000000000000000000000000000000000* L034734 000000000000000000000000000000000000000000000000000000000000000000* -L034800 111111111111111111111011111111111111111111111111011011111111111111* -L034866 111111111111111111111111111111101111111111111111010111111111111111* +L034800 011111111111111111111111111111110111111111111111111111111111111111* +L034866 101111111111111111110111111111111111111111111111111111111111111111* L034932 000000000000000000000000000000000000000000000000000000000000000000* L034998 000000000000000000000000000000000000000000000000000000000000000000* L035064 000000000000000000000000000000000000000000000000000000000000000000* L035130 000000000000000000000000000000000000000000000000000000000000000000* -L035196 111111111111111111111111111011111111111111111111011111111111111111* +L035196 111111111111111111111111111111111111111111111111111111111111111111* L035262 111111111111111111111111111111111111111111111111111111111111111111* L035328 111111111111111111111111111111111111111111111111111111111111111111* L035394 111111111111111111111111111111111111111111111111111111111111111111* @@ -742,14 +739,14 @@ L035724 111111111111111111111111111111111111111111111111111111111111111111* L035790 111111111111111111111111111111111111111111111111111111111111111111* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 110111111001100111011111111111111111111111101111011111111110111111* -L035988 111111111111111111111111111111111111111111111111101111111101111111* -L036054 110111111011111111011111111111111111111111111111011111111101111111* -L036120 111111111101100111111111111111111111111111101111011111111110111111* -L036186 000000000000000000000000000000000000000000000000000000000000000000* -L036252 111111111111111111111101111111111111111110111111011111111111111111* -L036318 111111111111111111111111111110111111110101111111011111111111111111* -L036384 000000000000000000000000000000000000000000000000000000000000000000* +L035922 011111111111111111111111111111111111111011111111111111111110111111* +L035988 011001111101111111111011111111111111111010111101111111111111111111* +L036054 011101111101111111111011011111111111111010111101111111111111111111* +L036120 011101110101111111111011111111111111111010111101111111111111111111* +L036186 011101111101111110111011111111111111111010111101111111111111111111* +L036252 111111111111111111111111111111011111111111111111111111111111111111* +L036318 011101111101111111111001111111111111111010111101111111111111111111* +L036384 011101111101101111111011111111111111111010111101111111111111111111* L036450 000000000000000000000000000000000000000000000000000000000000000000* L036516 000000000000000000000000000000000000000000000000000000000000000000* L036582 @@ -766,16 +763,16 @@ L037176 111111111111111111111111111111111111111111111111111111111111111111* L037242 111111111111111111111111111111111111111111111111111111111111111111* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 110111011011111111111111111111111111111111111111011111111111111111* -L037440 111101101011111111111111111111111111111111111111011111111111111111* -L037506 110101101111111111111111111111111111111111111111011111111111111111* -L037572 000000000000000000000000000000000000000000000000000000000000000000* +L037374 011111111101110111111111111001101111111110111111011111111110111111* +L037440 101111111111111111111111111111111111111101111111111111111111111111* +L037506 011111111111110111111111111011111111111101111111011111111111111111* +L037572 011111111101111111111111111101101111111110111111111111111110111111* L037638 000000000000000000000000000000000000000000000000000000000000000000* -L037704 111111111111111111111110111111111111111110111111011111111111111111* -L037770 111111111111111111111111111111111111100101111111011111111111111111* -L037836 000000000000000000000000000000000000000000000000000000000000000000* -L037902 000000000000000000000000000000000000000000000000000000000000000000* -L037968 000000000000000000000000000000000000000000000000000000000000000000* +L037704 011111111111111111101111111111111111111111111111111111111111111111* +L037770 111111111111111111111111111111111111111111111111111111111111111111* +L037836 111111111111111111111111111111111111111111111111111111111111111111* +L037902 111111111111111111111111111111111111111111111111111111111111111111* +L037968 111111111111111111111111111111111111111111111111111111111111111111* L038034 000000000000000000000000000000000000000000000000000000000000000000* L038100 111111111111111111111111111111111111111111111111111111111111111111* @@ -790,12 +787,12 @@ L038628 111111111111111111111111111111111111111111111111111111111111111111* L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 111111111111111111111111111111111111111111111111101111111111111111* -L038892 111111111111111111111111111111111101111111111111111011111111111111* -L038958 011111111111111111111111111111101111111111111111110111101111111111* +L038826 011111111111110111111111111011111111111111111111110111111111111111* +L038892 011111111111111111111111111011111101111111111111111111111111111111* +L038958 011111111111110111111111111111111101111111111111111111111111111111* L039024 000000000000000000000000000000000000000000000000000000000000000000* L039090 000000000000000000000000000000000000000000000000000000000000000000* -L039156 111111111111111111111111111111111111111111111111111111111111011111* +L039156 111111111111111111111111111111111111111111011111111111111111111111* L039222 111111111111111111111111111111111111111111111111111111111111111111* L039288 111111111111111111111111111111111111111111111111111111111111111111* L039354 111111111111111111111111111111111111111111111111111111111111111111* @@ -817,51 +814,51 @@ L040212 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* L040348 10100110011110* -L040362 11100110010010* -L040376 01010110011110* -L040390 11100011110011* -L040404 00100111011111* -L040418 11100110010011* -L040432 11011011111110* -L040446 11110011110011* -L040460 10100110011111* -L040474 11100110010011* -L040488 11011111111110* -L040502 11110011111110* -L040516 10100110011111* -L040530 00000110011111* -L040544 11011011111110* -L040558 11111111111111* +L040362 10100110010010* +L040376 11011111111110* +L040390 11111011110011* +L040404 11100110011110* +L040418 00110110010010* +L040432 11011111111111* +L040446 11111011110011* +L040460 00100111011110* +L040474 01000110010010* +L040488 11010011111110* +L040502 11111011111111* +L040516 10100110011110* +L040530 00000110011110* +L040544 11011111111111* +L040558 11110011111111* NOTE BLOCK 6 * L040572 - 111111111111111011101011111111111111111111111111111111111111111111 - 111111111101111111111111101111111111111111111011111111111111111111 - 111111111111111111111111111011111111111111111110111111111111111111 - 111111111011111111111111111111111111111111111111111111111111111110 - 111111111111111111111111111111111110111111111111011011111111111111 - 110101111111111111111111111111111111111011111111111111111111111111 - 011111111111101111111111111111111111111111111111111111111111111111 - 111111111111111101111111111111110111111110111111111111101111111111 - 111111011111111111111111111111111111111111101111111111111111111111* + 111011111111111111101111111111111111111111111111111111111111111111 + 111111111111111111111111111110111111111111111111111111101111111111 + 111111111111111111111111111111101111111111111111111111111111111111 + 111111111011111111111111111111111111111111111011111111111111111111 + 111111111110111111111111111111111111111111111111111111111111111111 + 111111111111101111111111111111111111111111011111111111111111111111 + 111111111111110111111111111111111111011111111111011111111011111111 + 111101111111111101111111111011111111111010111111111111111111111111 + 101111011111111111110111011111111111111111111111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 111111111111111111111111111111111110110101011111111111111111111111* -L041298 111111111111101111111111111111111111111110011111111111111111111111* +L041232 011111111111111111111111111111111111111110111111111111111011111111* +L041298 000000000000000000000000000000000000000000000000000000000000000000* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111101111111111111111111111111111111111111111111111111111111111111* +L041562 111111111111111111111111011111111111111111111111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111111111011111111111111111111111111111111111111111111111111111111* -L042024 111111111111111111111111111111111111111111111111111111111111111111* -L042090 111111111111111111111111111111111111111111111111111111111111111111* -L042156 111111111111111111111111111111111111111111111111111111111111111111* -L042222 111111111111111111111111111111111111111111111111111111111111111111* +L041958 011101111111111011111111110111111111111111111111111111111111111111* +L042024 011111111011111111111111111111111111111011111111111111111111111111* +L042090 000000000000000000000000000000000000000000000000000000000000000000* +L042156 000000000000000000000000000000000000000000000000000000000000000000* +L042222 000000000000000000000000000000000000000000000000000000000000000000* L042288 111111111111111111111111111111111111111111111111111111111111111111* L042354 111111111111111111111111111111111111111111111111111111111111111111* L042420 111111111111111111111111111111111111111111111111111111111111111111* @@ -869,71 +866,71 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111011111111111111111111111111011111111111111101111111111111111* -L042750 111111101111111111111111111111110111111111111111011111111111111111* +L042684 111111101111111111111111111111111111011111101111111111111111111111* +L042750 111111011111111111111111111111111111101111011111111111111111111111* L042816 000000000000000000000000000000000000000000000000000000000000000000* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111111111111111111111111111111111111111111011111111111111111111101* -L043080 111011111111111111110111111111111111111111010101111111011111111111* -L043146 000000000000000000000000000000000000000000000000000000000000000000* +L043014 011111111111111111111111110111111111111111110111111111111111111111* +L043080 011111111111111011111111111111111111111111110111111111111111111111* +L043146 010111111111111011111111110111111111111111111111111111111111111111* L043212 000000000000000000000000000000000000000000000000000000000000000000* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 111111111111111111111111111111111111111111011101111111101111111111* -L043476 110111111111111111111111111111111111111111011101111111111111111111* -L043542 111011111111111111111111111111111111111111011110111111011111111111* -L043608 111111111111111111110111111111111111111111010101111111111111111111* -L043674 000000000000000000000000000000000000000000000000000000000000000000* +L043410 011111111111111111111011111111111111111111111111111111111111111111* +L043476 111111111111111111111111111111111111111111111111111111111111111111* +L043542 111111111111111111111111111111111111111111111111111111111111111111* +L043608 111111111111111111111111111111111111111111111111111111111111111111* +L043674 111111111111111111111111111111111111111111111111111111111111111111* L043740 111111111111111111111111111111111111111111111111111111111111111111* L043806 111111111111111111111111111111111111111111111111111111111111111111* L043872 111111111111111111111111111111111111111111111111111111111111111111* L043938 111111111111111111111111111111111111111111111111111111111111111111* L044004 111111111111111111111111111111111111111111111111111111111111111111* L044070 - 111111111110111111111111111111111111111110111111111111111111111101* -L044136 111111111111111111111111111111111111111111101111111111111111111111* -L044202 111111111111111111111111110111111111110101111111111111111111111111* -L044268 111111111111111101111111111111111111111110111111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* +L044136 101111111111111111111111111111111111111111111111111111111111111111* +L044202 111111111111111101111111111111111111111110111111111111111111111111* +L044268 000000000000000000000000000000000000000000000000000000000000000000* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 111111111111111111111111011111111111111111111111111111101111111111* -L044532 110111111111111111111111011111111111111111111111111111111111111111* -L044598 111011111111111111111111101111111111111111111111111111011111111111* +L044466 111111111111111111111111111011111111111111111111111111011111111111* +L044532 111111111111110111111111111111111111111111111111111111011111111111* +L044598 111111111111111011111111110111111111111111111111111111101111111111* L044664 000000000000000000000000000000000000000000000000000000000000000000* L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 - 111111111110111111111111111111111111111110111111111111111111111111* -L044862 111011111111111111110111111111111111111111011101111111011111111111* -L044928 111111111111111111111111111111111111111111010111111111111111111111* -L044994 000000000000000000000000000000000000000000000000000000000000000000* -L045060 000000000000000000000000000000000000000000000000000000000000000000* -L045126 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111111111111110111111111111111111111111* +L044862 111111111111111111111111111111111111111111111111111111111111111111* +L044928 111111111111111111111111111111111111111111111111111111111111111111* +L044994 111111111111111111111111111111111111111111111111111111111111111111* +L045060 111111111111111111111111111111111111111111111111111111111111111111* +L045126 111111111111111111111111111111111111111111111111111111111111111111* L045192 111111111111111111111111111111111111111111111111111111111111111111* L045258 111111111111111111111111111111111111111111111111111111111111111111* L045324 111111111111111111111111111111111111111111111111111111111111111111* L045390 111111111111111111111111111111111111111111111111111111111111111111* L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 - 111111111111111111111111111111111111111110111111111111111111111101* -L045588 111111111111111111111111111111111111111001011111111111111111111111* -L045654 111111111111111011111111111111111111111101011111111111111111111111* -L045720 101111111111111110111111111111111111111110011111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* +L045588 011111111111111111111111111111111111111101111111111111111111111111* +L045654 011111111111111110111111111111111111111111111111101111111111111111* +L045720 000000000000000000000000000000000000000000000000000000000000000000* L045786 000000000000000000000000000000000000000000000000000000000000000000* L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 110111111111111111111111111111111111111111011111110111101111111111* -L045984 111111111111111111011111111111111111111111011111111111101111111111* -L046050 110111111111111111011111111111111111111111011111111111111111111111* +L045918 101111111111111111111111111111111111111111111111111111111111111111* +L045984 111111111110111111011111111111111111111111111111111111111111111111* +L046050 111111111101101111111111111101101111111111111111111111111111111111* L046116 000000000000000000000000000000000000000000000000000000000000000000* L046182 000000000000000000000000000000000000000000000000000000000000000000* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111110111111111111111111111011111111111111111111111* -L046380 111011111111111111111111111111111111111111011001111111011111111111* -L046446 111011111111111111111011111111111111111111011101111111011111111111* -L046512 000000000000000000000000000000000000000000000000000000000000000000* -L046578 000000000000000000000000000000000000000000000000000000000000000000* +L046314 111111111111111111111111111111111111111111111111111111111111111111* +L046380 111111111111111111111111111111111111111111111111111111111111111111* +L046446 111111111111111111111111111111111111111111111111111111111111111111* +L046512 111111111111111111111111111111111111111111111111111111111111111111* +L046578 111111111111111111111111111111111111111111111111111111111111111111* L046644 111111111111111111111111111111111111111111111111111111111111111111* L046710 111111111111111111111111111111111111111111111111111111111111111111* L046776 111111111111111111111111111111111111111111111111111111111111111111* @@ -943,52 +940,52 @@ L046974 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* -L047110 11100110011000* +L047110 01100110011000* L047124 00101011111110* -L047138 00010110010101* +L047138 11100110010101* L047152 11101011111111* L047166 10100011111000* L047180 10100110010010* -L047194 10100110010001* +L047194 01010110010001* L047208 11101011110011* L047222 10100110010000* L047236 10100110010011* -L047250 10100110010101* -L047264 11100011110011* +L047250 11010011110101* +L047264 11111011110011* L047278 11100110010010* L047292 10100110010010* -L047306 00100110010001* -L047320 11101011111111* +L047306 11011111110001* +L047320 11110011111111* NOTE BLOCK 7 * L047334 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111101111111111110111111111111111111111111111111111111111111 - 111111111111111111111111111111111110111111111111111111111111111111 - 111011111111111111111011111011111111111111111011111111111111111111 - 111111111111111111111111111111111111111111111111111011111111111111 - 111111111111111011111111011111011111011111011111111111111110111111 - 111111010111011111111111111111111111111111111111011111111111111111 - 111101111111111101101111111111111111111110111111111111101111111111 + 111111111111111111111111111111111111111111111111111111111111011111 + 111111111111111110111111111111011111111111111111111111111111111111 + 111110111111111111111111111111111110111111111111111111111111111111 + 111011111111111111111111111011111111111111111111111111111111111011 + 111111111110111111111111111111111111111111111111111111111111111111 + 111111111111011011011111111111111111011111111111111111111111111111 + 111111110111111111111101111111111111111111111111010111111111111111 + 111111111111111111111111011111111111111110111111111111101111111110 101111111111111111111111111111111011110111111110111111111111111111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 011111111111111111110111111111111111111111111110111111011111111111* -L048060 011111111111111111110111111111111111111111101110111111111111111111* -L048126 011111111111111111110111111111101111111111111110111011111111111111* -L048192 011111111111111111110110111111101111111111011111110111101111111111* +L047994 011101111111111111111111111111111111111111111110111111011111111111* +L048060 011101111111111111111111111111111111111111111110111011111111111111* +L048126 011101111110111111101111111111111111111111111110111111111111111111* +L048192 011101111101111110101111111111111111111111111111110111101111111111* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 110111111011101111101111100111111101011011111111111111111111111111* +L048324 110111111011101111111110110111111101011011111111111111111111111110* L048390 000000000000000000000000000000000000000000000000000000000000000000* L048456 000000000000000000000000000000000000000000000000000000000000000000* L048522 000000000000000000000000000000000000000000000000000000000000000000* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 011111111111111111101111111111111111111111111111111111111111111111* -L048786 111111111111111111111111111111111111111111111111111111111111111111* -L048852 111111111111111111111111111111111111111111111111111111111111111111* -L048918 111111111111111111111111111111111111111111111111111111111111111111* -L048984 111111111111111111111111111111111111111111111111111111111111111111* +L048720 101111111111111111111111111111111111111111111111111111111111111111* +L048786 111111111111111111111111011111111111111111111111011111111111111111* +L048852 000000000000000000000000000000000000000000000000000000000000000000* +L048918 000000000000000000000000000000000000000000000000000000000000000000* +L048984 000000000000000000000000000000000000000000000000000000000000000000* L049050 111111111111111111111111111111111111111111111111111111111111111111* L049116 111111111111111111111111111111111111111111111111111111111111111111* L049182 111111111111111111111111111111111111111111111111111111111111111111* @@ -998,16 +995,16 @@ L049380 111111111111111111111111111111111111111111111111111111111111111111* L049446 101111111111111111111111111111111111111111111111111111111111111111* L049512 111111111111111111111111111111111111011101111111111111111111111111* -L049578 111111111111111111111111111111110111011111101111111111011111111111* +L049578 111111111111111111111111111111110111011111111111111011011111111111* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111111111111111111111111111111111111011111111111111111111111* +L049776 111111111111111111111111111111111111111111111111110111111111111111* L049842 111111111111111111111111111111111111111111111111111111111111111111* L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 - 111111111110111111111111111111111111111110110111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L050172 111111111111111111111111111111111111111111111111111111011111111111* L050238 111111111111111111111111111111111111111111111111111111111111111111* L050304 111111111111111111111111111111111111111111111111111111111111111111* @@ -1019,19 +1016,19 @@ L050634 111111111111111111111111111111111111111111111111111111111111111111* L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 - 111111111101111111111111111111111111111111111111111111111111111111* -L050898 111111101111111111111111111111111011111111111111111111111111111111* + 111111111111111111111111111111011111111101111111111111111111111111* +L050898 111111111111111111111111111111111011111111111111111111111111101111* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111110111111111111101111111111111111111111111111111111111111111111* +L051228 111111111111111111111111111111111111111111111111111111111111111010* L051294 111111111111111111111111111111111111111111111111111111111111111111* L051360 111111111111111111111111111111111111111111111111111111111111111111* L051426 111111111111111111111111111111111111111111111111111111111111111111* L051492 111111111111111111111111111111111111111111111111111111111111111111* L051558 - 111111111111111111111111111111111111111101110111111111111111111111* + 011111111111111111111111111111111111111101111111111111111111111111* L051624 111111111111111111111111111111111111111111111111111111111111111111* L051690 111111111111111111111111111111111111111111111111111111111111111111* L051756 111111111111111111111111111111111111111111111111111111111111111111* @@ -1043,13 +1040,13 @@ L052086 111111111111111111111111111111111111111111111111111111111111111111* L052152 111111111111111111111111111111111111111111111111111111111111111111* L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 - 111111111110111111111111111111111111111110111111111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L052350 101111111111111111111111111111111111111111111111111111111111111111* -L052416 111111111111110111111111111111111111111101111111111111111101111111* -L052482 111111111111111110111111111111111111111110111111101111111111111111* +L052416 111111111111111111111111101111111111111110111111101111111111111111* +L052482 000000000000000000000000000000000000000000000000000000000000000000* L052548 000000000000000000000000000000000000000000000000000000000000000000* L052614 000000000000000000000000000000000000000000000000000000000000000000* -L052680 011111111111111111111111111111111111111110111111111111111111111111* +L052680 111111111111111011111111111111111111111111111111111111111111111111* L052746 111111111111111111111111111111111111111111111111111111111111111111* L052812 111111111111111111111111111111111111111111111111111111111111111111* L052878 111111111111111111111111111111111111111111111111111111111111111111* @@ -1072,7 +1069,7 @@ L053736 L053868 0010* L053872 11100110011100* L053886 01101011110010* -L053900 01010110010001* +L053900 10100110010001* L053914 11101011110011* L053928 10100110010000* L053942 00000110011110* @@ -1083,7 +1080,7 @@ L053998 01000011111110* L054012 11011011110110* L054026 11111111110011* L054040 10100110010001* -L054054 01000110010011* +L054054 00000110010011* L054068 11010011111100* L054082 11111011111111* E1 @@ -1096,7 +1093,7 @@ E1 1 00000000 1 -00100000 +00000000 1 00000000 1 @@ -1105,6 +1102,6 @@ E1 00000000 0 * -C55C9* +CFCEC* U00000000000000000000000000000000* -A829 +85B5 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 3e3384c..921e29e 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 12/29/16; -TIME = 16:02:00; +DATE = 12/30/17; +TIME = 00:43:46; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,12 +76,19 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; +AHIGH_27_ = pin,16,-,C,-; +AHIGH_26_ = pin,17,-,C,-; +AHIGH_25_ = pin,18,-,C,-; +AHIGH_24_ = pin,19,-,C,-; AHIGH_31_ = pin,4,-,B,-; -IPL_1_ = pin,56,-,F,-; -IPL_0_ = pin,67,-,G,-; +A_DECODE_22_ = pin,84,-,H,-; +A_DECODE_21_ = pin,94,-,A,-; A_DECODE_23_ = pin,85,-,H,-; -FC_0_ = pin,57,-,F,-; -A_1_ = pin,60,-,F,-; +A_DECODE_20_ = pin,93,-,A,-; +A_DECODE_19_ = pin,97,-,A,-; +A_DECODE_18_ = pin,95,-,A,-; +A_DECODE_17_ = pin,59,-,F,-; +A_DECODE_16_ = pin,96,-,A,-; IPL_2_ = pin,68,-,G,-; FC_1_ = pin,58,-,F,-; AS_030 = pin,82,-,H,-; @@ -93,97 +100,83 @@ nEXP_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; BGACK_000 = pin,28,-,D,-; -CLK_030 = pin,64,-,-,-; CLK_000 = pin,11,-,-,-; +IPL_1_ = pin,56,-,F,-; CLK_OSZI = pin,61,-,-,-; +IPL_0_ = pin,67,-,G,-; CLK_DIV_OUT = pin,65,-,G,-; +FC_0_ = pin,57,-,F,-; CLK_EXP = pin,10,-,B,-; +A_1_ = pin,60,-,F,-; FPU_CS = pin,78,-,H,-; FPU_SENSE = pin,91,-,A,-; DSACK1 = pin,81,-,H,-; DTACK = pin,30,-,D,-; AVEC = pin,92,-,A,-; E = pin,66,-,G,-; -AHIGH_30_ = pin,5,-,B,-; VPA = pin,36,-,-,-; +RST = pin,86,-,-,-; +AMIGA_ADDR_ENABLE = pin,33,-,D,-; +AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; +AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; +CIIN = pin,47,-,E,-; +AHIGH_30_ = pin,5,-,B,-; AHIGH_29_ = pin,6,-,B,-; AHIGH_28_ = pin,15,-,C,-; -RST = pin,86,-,-,-; -AHIGH_27_ = pin,16,-,C,-; -RESET = pin,3,-,B,-; -AHIGH_26_ = pin,17,-,C,-; -AHIGH_25_ = pin,18,-,C,-; -AMIGA_ADDR_ENABLE = pin,33,-,D,-; -AHIGH_24_ = pin,19,-,C,-; -AMIGA_BUS_DATA_DIR = pin,48,-,E,-; -A_DECODE_22_ = pin,84,-,H,-; -AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; -A_DECODE_21_ = pin,94,-,A,-; -AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; -A_DECODE_20_ = pin,93,-,A,-; -CIIN = pin,47,-,E,-; -A_DECODE_19_ = pin,97,-,A,-; -A_DECODE_18_ = pin,95,-,A,-; -A_DECODE_17_ = pin,59,-,F,-; -A_DECODE_16_ = pin,96,-,A,-; -A_0_ = pin,69,-,G,-; SIZE_1_ = pin,79,-,H,-; -IPL_030_1_ = pin,7,-,B,-; -IPL_030_0_ = pin,8,-,B,-; IPL_030_2_ = pin,9,-,B,-; RW_000 = pin,80,-,H,-; BG_000 = pin,29,-,D,-; BGACK_030 = pin,83,-,H,-; -SIZE_0_ = pin,70,-,G,-; +A_0_ = pin,69,-,G,-; +IPL_030_1_ = pin,7,-,B,-; +IPL_030_0_ = pin,8,-,B,-; VMA = pin,35,-,D,-; RW = pin,71,-,G,-; -cpu_est_1_ = node,-,-,D,6; -cpu_est_2_ = node,-,-,D,14; -cpu_est_3_ = node,-,-,D,2; +SIZE_0_ = pin,70,-,G,-; cpu_est_0_ = node,-,-,G,9; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,F,9; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,F,5; -inst_AS_030_D0 = node,-,-,H,2; -inst_AS_030_000_SYNC = node,-,-,B,13; -inst_BGACK_030_INT_D = node,-,-,H,13; -inst_AS_000_DMA = node,-,-,A,8; -inst_DS_000_DMA = node,-,-,A,13; -inst_VPA_D = node,-,-,F,2; +cpu_est_1_ = node,-,-,D,13; +cpu_est_2_ = node,-,-,D,2; +cpu_est_3_ = node,-,-,A,8; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,A,10; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,10; +inst_AS_030_D0 = node,-,-,E,8; +inst_AS_030_D1 = node,-,-,F,1; +inst_AS_030_000_SYNC = node,-,-,F,4; +inst_AS_000_DMA = node,-,-,C,13; +inst_DS_000_DMA = node,-,-,C,9; +inst_VPA_D = node,-,-,G,6; CLK_000_D_3_ = node,-,-,F,13; -inst_DTACK_D0 = node,-,-,B,14; -inst_RESET_OUT = node,-,-,G,5; -CLK_030_PE_1_ = node,-,-,A,2; -inst_AMIGA_DS = node,-,-,C,10; +inst_DTACK_D0 = node,-,-,F,9; +inst_AMIGA_DS = node,-,-,H,2; CLK_000_D_1_ = node,-,-,H,5; -CLK_000_D_0_ = node,-,-,D,13; -inst_CLK_OUT_PRE_50 = node,-,-,G,2; -inst_CLK_OUT_PRE_D = node,-,-,E,8; -IPL_D0_0_ = node,-,-,B,10; -IPL_D0_1_ = node,-,-,B,6; -IPL_D0_2_ = node,-,-,B,2; +CLK_000_D_0_ = node,-,-,D,9; +inst_CLK_OUT_PRE_50 = node,-,-,H,13; +inst_CLK_OUT_PRE_D = node,-,-,E,5; +IPL_D0_0_ = node,-,-,A,6; +IPL_D0_1_ = node,-,-,D,6; +IPL_D0_2_ = node,-,-,A,2; CLK_000_D_2_ = node,-,-,H,6; -CLK_000_D_4_ = node,-,-,C,14; -inst_LDS_000_INT = node,-,-,F,12; -inst_DS_000_ENABLE = node,-,-,C,13; -inst_UDS_000_INT = node,-,-,F,1; +CLK_000_D_4_ = node,-,-,F,5; +inst_UDS_000_INT = node,-,-,B,6; +inst_DS_000_ENABLE = node,-,-,C,2; +inst_LDS_000_INT = node,-,-,G,13; +inst_BGACK_030_INT_D = node,-,-,E,13; SM_AMIGA_6_ = node,-,-,F,0; -SM_AMIGA_4_ = node,-,-,A,1; -SM_AMIGA_1_ = node,-,-,F,8; +SM_AMIGA_4_ = node,-,-,G,5; +SM_AMIGA_1_ = node,-,-,A,5; SM_AMIGA_0_ = node,-,-,A,12; -CYCLE_DMA_0_ = node,-,-,A,6; -CYCLE_DMA_1_ = node,-,-,A,10; -CLK_030_PE_0_ = node,-,-,A,9; -RST_DLY_0_ = node,-,-,G,6; -RST_DLY_1_ = node,-,-,G,14; -RST_DLY_2_ = node,-,-,G,10; -inst_DSACK1_INT = node,-,-,A,5; -inst_AS_000_INT = node,-,-,C,2; -SM_AMIGA_5_ = node,-,-,G,13; -SM_AMIGA_3_ = node,-,-,C,6; -SM_AMIGA_2_ = node,-,-,C,9; -SM_AMIGA_i_7_ = node,-,-,F,4; -CLK_OUT_INTreg = node,-,-,D,10; -CIIN_0 = node,-,-,E,5; +CYCLE_DMA_0_ = node,-,-,B,13; +CYCLE_DMA_1_ = node,-,-,B,2; +inst_DSACK1_INT = node,-,-,G,2; +inst_AS_000_INT = node,-,-,C,6; +SM_AMIGA_5_ = node,-,-,F,12; +SM_AMIGA_3_ = node,-,-,A,13; +SM_AMIGA_2_ = node,-,-,A,9; +CLK_OUT_INTreg = node,-,-,A,1; +SM_AMIGA_i_7_ = node,-,-,F,8; +N_60 = node,-,-,E,9; [GROUP ASSIGNMENTS] Layer = OFF; @@ -222,6 +215,7 @@ Page_Break = Yes; [POWER] Powerlevel = Low,High; Default = High; +High = B; Low = H,G,F,E,D,C,B,A; Type = GLB; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index ab5d2b0..5c8093c 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -1,20 +1,21 @@ -116 "number of signals after reading design file" +122 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 4 0 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 2 4 6 79 -1 4 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21 + 70 RW 5 352 6 2 5 7 70 -1 2 0 21 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 78 SIZE_1_ 5 343 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 353 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 347 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -23,15 +24,15 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 + 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 350 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 10 0 21 + 82 BGACK_030 5 348 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 + 28 BG_000 5 346 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 80 DSACK1 0 7 0 80 -1 1 0 21 @@ -41,187 +42,70 @@ 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 - 307 CLK_000_D_3_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 - 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 306 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 319 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 6 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 3 5 68 -1 3 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 40 BERR 5 -1 4 2 0 5 40 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 5 2 3 5 6 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 4 0 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 4 0 3 5 6 -1 -1 4 0 21 - 300 inst_BGACK_030_INT_D 3 -1 6 4 1 2 6 7 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 4 0 3 5 6 -1 -1 1 1 21 - 343 RN_VMA 3 34 3 3 0 3 5 34 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 3 0 3 5 -1 -1 3 0 21 - 305 inst_VPA_D 3 -1 2 3 0 3 5 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 5 2 0 5 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 3 2 1 3 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 2 2 0 5 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 4 2 2 7 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 7 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 4 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 348 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 313 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 309 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 297 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 340 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 + 327 SM_AMIGA_1_ 3 -1 1 3 1 3 5 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 3 3 0 3 5 -1 -1 3 0 21 + 325 SM_AMIGA_6_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 341 CLK_OUT_INTreg 3 -1 2 3 0 1 6 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 + 339 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 + 332 RST_DLY_0_ 3 -1 2 2 2 6 -1 -1 4 0 21 + 329 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 337 SM_AMIGA_5_ 3 -1 5 2 3 5 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 336 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 335 inst_DSACK1_INT 3 -1 3 2 3 7 -1 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 6 2 2 6 -1 -1 2 0 21 + 333 RST_DLY_1_ 3 -1 6 2 2 6 -1 -1 2 1 21 + 330 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 324 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 inst_DTACK_DMA 3 -1 7 2 3 7 -1 -1 2 0 21 + 301 inst_AS_030_D1 3 -1 5 2 2 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 inst_CLK_OUT_PRE_D 3 -1 4 2 0 2 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 6 2 1 5 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 + 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 331 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 310 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 + 338 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 353 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 343 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 311 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 342 CIIN_0 3 -1 2 1 4 -1 -1 1 0 21 + 321 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 320 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 + 319 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21 + 318 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 317 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 + 293 un10_ciin_i 3 -1 4 1 2 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 @@ -230,5989 +114,17 @@ 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 67 IPL_2_ 1 -1 -1 2 1 7 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 344 6 2 2 6 68 -1 3 0 21 - 70 RW 5 343 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 339 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 342 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 321 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 333 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 - 325 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 4 0 21 - 342 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 1 2 1 2 -1 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 322 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 327 RST_DLY_2_ 3 -1 1 2 1 3 -1 -1 2 0 21 - 326 RST_DLY_1_ 3 -1 3 2 1 3 -1 -1 2 1 21 - 318 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 317 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 306 CLK_000_D_2_ 3 -1 7 2 1 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 328 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 343 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_3_ 3 -1 1 1 5 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 306 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 316 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 306 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 316 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 2 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 2 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 306 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 295 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_6_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 316 CLK_000_D_2_ 3 -1 7 3 1 2 5 -1 -1 1 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 7 2 3 7 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 1 2 0 2 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 0 1 2 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 10 CLK_000 1 -1 -1 3 0 6 7 10 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 1 2 4 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 0 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 0 68 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 306 CLK_000_D_1_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 316 CLK_000_D_2_ 3 -1 7 4 1 3 5 7 -1 -1 1 0 21 - 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 3 3 1 3 5 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 2 3 2 6 7 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 299 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 321 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 7 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 2 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 340 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 346 6 2 1 5 68 -1 3 0 21 - 70 RW 5 345 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 - 306 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_6_ 3 -1 1 5 0 1 2 5 7 -1 -1 3 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 326 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 1 1 21 - 301 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 344 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 325 SM_AMIGA_4_ 3 -1 6 2 2 6 -1 -1 3 0 21 - 323 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 320 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 319 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 316 CLK_000_D_2_ 3 -1 7 2 0 2 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 7 2 0 7 -1 -1 1 0 21 - 307 CLK_000_D_4_ 3 -1 0 2 1 7 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 335 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 N_262 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 318 CLK_000_D_5_ 3 -1 7 1 1 -1 -1 1 0 21 - 317 CLK_000_D_3_ 3 -1 2 1 0 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 6 0 2 3 5 6 7 -1 -1 1 0 21 - 306 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 316 CLK_000_D_2_ 3 -1 7 2 0 5 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_262 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 2 2 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 10 CLK_000 1 -1 -1 2 0 5 10 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 - 70 RW 5 344 6 2 3 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 1 5 0 1 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 6 3 1 6 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 2 3 2 3 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 6 2 5 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 5 2 5 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 5 6 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 0 2 1 6 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 10 CLK_000 1 -1 -1 3 0 3 6 10 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 2 3 68 -1 3 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 2 4 2 3 6 7 -1 -1 3 0 21 - 300 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 298 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 304 CYCLE_DMA_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 322 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 318 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 2 2 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 319 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 7 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 7 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 10 CLK_000 1 -1 -1 2 0 5 10 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 1 2 6 7 -1 -1 1 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 2 2 1 2 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 318 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 318 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 59 A_1_ 1 -1 -1 2 2 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 1 5 68 -1 3 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 1 2 6 7 -1 -1 1 0 21 - 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 305 CYCLE_DMA_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 2 2 1 2 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 318 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 318 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 59 A_1_ 1 -1 -1 2 2 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 340 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 343 6 1 2 69 -1 3 0 21 - 68 A_0_ 5 346 6 1 2 68 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 323 SM_AMIGA_6_ 3 -1 1 5 1 2 3 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 5 1 2 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 295 cpu_est_3_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 296 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 5 0 21 - 344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 326 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 324 SM_AMIGA_4_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 320 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 322 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_25 3 -1 0 2 0 2 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 314 inst_CLK_OUT_PRE_D 3 -1 2 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 2 2 1 7 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 343 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 319 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21 - 318 CLK_000_D_2_ 3 -1 0 1 2 -1 -1 1 0 21 - 317 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 59 A_1_ 1 -1 -1 2 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 318 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 59 A_1_ 1 -1 -1 2 2 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 0 2 68 -1 3 0 21 - 70 RW 5 344 6 2 3 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 322 SM_AMIGA_6_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 6 0 1 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 324 SM_AMIGA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 2 2 1 7 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 5 1 5 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -112 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 4 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 -1 6 2 1 2 68 -1 2 0 21 - 70 RW 5 -1 6 2 5 7 70 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 340 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 339 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 6 3 0 5 6 -1 -1 3 0 21 - 303 CYCLE_DMA_0_ 3 -1 0 3 0 1 2 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 301 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 6 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 6 2 3 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 332 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_147 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 321 inst_BGACK_030_INT_D 3 -1 3 1 5 -1 -1 1 0 21 - 317 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 3 1 2 -1 -1 1 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 3 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -112 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 4 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 -1 6 2 1 2 68 -1 2 0 21 - 70 RW 5 -1 6 2 5 7 70 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 - 69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 340 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 339 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 306 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 308 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 - 296 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_4_ 3 -1 6 3 0 5 6 -1 -1 3 0 21 - 316 CYCLE_DMA_0_ 3 -1 0 3 0 1 2 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 8 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 301 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 317 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 6 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 304 CLK_000_D_3_ 3 -1 6 2 3 5 -1 -1 1 0 21 - 303 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 inst_CLK_030_H 3 -1 2 1 2 -1 -1 4 1 21 - 332 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_235 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 321 inst_BGACK_030_INT_D 3 -1 3 1 5 -1 -1 1 0 21 - 315 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 314 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 313 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 309 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 305 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 3 1 2 -1 -1 1 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 3 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -112 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 6 7 41 -1 1 0 21 - 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 -1 6 2 2 6 68 -1 2 0 21 - 70 RW 5 -1 6 2 5 7 70 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 6 78 -1 2 0 21 - 69 SIZE_0_ 5 -1 6 1 6 69 -1 2 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 340 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 339 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 306 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 308 CLK_000_D_0_ 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 1 6 0 1 2 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 321 SM_AMIGA_4_ 3 -1 1 3 0 1 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 5 3 0 3 5 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 - 328 CYCLE_DMA_1_ 3 -1 6 2 2 6 -1 -1 4 0 21 - 301 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 317 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 316 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 318 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 - 309 inst_CLK_OUT_PRE_50 3 -1 7 2 6 7 -1 -1 1 0 21 - 304 CLK_000_D_3_ 3 -1 3 2 1 6 -1 -1 1 0 21 - 303 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 inst_CLK_030_H 3 -1 2 1 2 -1 -1 4 0 21 - 324 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 332 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 327 CYCLE_DMA_0_ 3 -1 6 1 6 -1 -1 3 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_235 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 319 inst_BGACK_030_INT_D 3 -1 4 1 5 -1 -1 1 0 21 - 315 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 313 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 312 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 311 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 305 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 1 2 -1 -1 1 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 59 A_1_ 1 -1 -1 2 3 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -110 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 1 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 5 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 79 RW_000 5 338 7 3 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 -1 6 2 5 6 68 -1 2 0 21 - 70 RW 5 -1 6 2 5 7 70 -1 1 0 21 - 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 - 69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 336 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 335 1 0 6 -1 9 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 341 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 306 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 308 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 307 CLK_000_D_1_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 2 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 3 1 2 3 -1 -1 7 0 21 - 301 inst_AS_000_DMA 3 -1 5 3 2 5 7 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 333 SM_AMIGA_i_7_ 3 -1 2 3 1 2 7 -1 -1 3 1 21 - 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 302 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 341 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 317 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 316 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 329 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 318 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 309 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 304 CLK_000_D_3_ 3 -1 6 2 2 6 -1 -1 1 0 21 - 303 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 335 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 331 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 inst_CLK_030_H 3 -1 2 1 2 -1 -1 4 0 21 - 324 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 330 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 N_72 3 -1 4 1 4 -1 -1 2 0 21 - 328 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 319 inst_BGACK_030_INT_D 3 -1 1 1 1 -1 -1 1 0 21 - 315 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 314 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 313 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 311 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 305 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 63 CLK_030 1 -1 -1 2 2 5 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 1 7 70 -1 2 0 21 - 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21 - 294 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 4 1 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 318 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 317 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 59 A_1_ 1 -1 -1 2 2 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 338 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 335 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 336 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 341 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 9 0 21 - 82 BGACK_030 5 340 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 339 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 2 RESET 0 1 0 2 -1 1 0 21 - 340 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 0 5 0 1 2 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 333 SM_AMIGA_i_7_ 3 -1 2 3 0 2 7 -1 -1 3 1 21 - 323 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 324 RST_DLY_0_ 3 -1 6 2 0 6 -1 -1 4 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 2 2 2 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 329 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 328 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 6 2 0 6 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 0 2 0 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 0 2 0 2 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 3 4 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 0 2 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 7 0 21 - 332 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 - 331 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 338 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 inst_CLK_030_H 3 -1 0 1 0 -1 -1 4 0 21 - 341 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 336 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 335 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 339 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 334 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 324 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 324 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 8 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 318 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 324 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_270 3 -1 4 1 4 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 325 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 318 CYCLE_DMA_0_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 8 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 326 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 304 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 324 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_270 3 -1 4 1 4 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 5 7 41 -1 1 0 21 - 79 RW_000 5 348 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 70 RW 5 355 6 2 5 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 5 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 351 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_6_ 3 -1 6 5 1 2 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 6 -1 -1 7 0 21 - 343 SM_AMIGA_i_7_ 3 -1 0 3 0 6 7 -1 -1 3 1 21 - 322 SM_AMIGA_4_ 3 -1 0 3 0 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 0 3 4 -1 -1 1 0 21 - 328 DMA_CYCLE_FINISHED_6_ 3 -1 2 2 2 5 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 333 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 2 5 -1 -1 9 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 5 2 2 5 -1 -1 8 0 21 - 332 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 8 1 21 - 331 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 2 5 -1 -1 8 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 2 3 -1 -1 5 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 2 2 5 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 339 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 0 2 0 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 0 2 0 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 1 1 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 330 DMA_CYCLE_FINISHED_4_ 3 -1 5 1 5 -1 -1 8 1 21 - 329 DMA_CYCLE_FINISHED_5_ 3 -1 2 1 2 -1 -1 8 1 21 - 334 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 7 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 325 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 327 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 326 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 316 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 3 1 3 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 5 7 41 -1 1 0 21 - 79 RW_000 5 348 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 70 RW 5 355 6 2 5 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 5 80 -1 1 0 21 - 78 SIZE_1_ 5 346 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 345 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 351 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_6_ 3 -1 6 5 1 2 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 6 -1 -1 7 0 21 - 343 SM_AMIGA_i_7_ 3 -1 0 3 0 6 7 -1 -1 3 1 21 - 322 SM_AMIGA_4_ 3 -1 0 3 0 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 0 3 4 -1 -1 1 0 21 - 328 DMA_CYCLE_FINISHED_6_ 3 -1 2 2 2 5 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 333 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 2 5 -1 -1 9 0 21 - 332 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 8 1 21 - 331 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 2 5 -1 -1 8 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 5 2 2 5 -1 -1 7 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 2 3 -1 -1 5 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 2 2 5 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 339 SM_AMIGA_5_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 0 2 0 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 0 2 0 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 1 1 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 330 DMA_CYCLE_FINISHED_4_ 3 -1 5 1 5 -1 -1 8 1 21 - 329 DMA_CYCLE_FINISHED_5_ 3 -1 2 1 2 -1 -1 8 1 21 - 334 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 7 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 325 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 327 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 326 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 316 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 3 1 3 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 347 7 4 0 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 0 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 5 6 7 30 -1 1 0 21 - 80 DSACK1 5 -1 7 3 0 5 6 80 -1 1 0 21 - 68 A_0_ 5 348 6 2 2 5 68 -1 3 0 21 - 70 RW 5 354 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 345 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 355 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 350 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 349 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 351 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 1 6 0 1 2 3 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 4 0 2 5 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 0 5 6 7 -1 -1 1 0 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 6 3 0 5 6 -1 -1 9 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 3 2 3 7 -1 -1 7 0 21 - 323 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 3 1 2 3 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 7 -1 -1 1 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 0 2 0 5 -1 -1 10 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 5 2 5 6 -1 -1 10 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 0 2 0 5 -1 -1 9 0 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 5 2 0 5 -1 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 0 5 -1 -1 8 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 0 2 0 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 324 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 322 SM_AMIGA_1_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 1 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 2 2 2 6 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 1 6 -1 -1 7 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 353 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 4 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 59 A_1_ 1 -1 -1 2 0 5 59 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 35 VPA 1 -1 -1 1 4 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 348 7 5 0 1 4 5 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 70 RW 5 354 6 2 5 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 1 5 80 -1 1 0 21 - 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 355 6 1 2 69 -1 3 0 21 - 68 A_0_ 5 347 6 1 2 68 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 350 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 349 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 351 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 5 3 0 5 7 -1 -1 6 0 21 - 335 CYCLE_DMA_1_ 3 -1 0 3 0 1 5 -1 -1 4 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 1 3 0 1 5 -1 -1 4 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 5 3 0 1 5 -1 -1 4 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 1 3 0 1 5 -1 -1 4 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 1 3 0 1 5 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 - 323 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 2 3 2 3 5 -1 -1 3 0 21 - 320 SM_AMIGA_6_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 2 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 2 3 2 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 341 SM_AMIGA_2_ 3 -1 0 2 0 7 -1 -1 5 0 21 - 340 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 5 2 1 5 -1 -1 4 1 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 1 2 1 5 -1 -1 4 1 21 - 353 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 2 0 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 1 1 1 -1 -1 4 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 4 1 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 1 1 1 -1 -1 4 1 21 - 324 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 1 1 3 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 63 CLK_030 1 -1 -1 2 0 5 63 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 1 3 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 5 7 41 -1 1 0 21 - 79 RW_000 5 347 7 4 2 4 5 6 79 -1 4 0 21 - 68 A_0_ 5 348 6 2 1 5 68 -1 3 0 21 - 70 RW 5 354 6 2 1 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 5 80 -1 1 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 355 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 351 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 349 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 350 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 5 6 0 1 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 3 3 5 7 -1 -1 7 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 7 3 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 1 3 0 1 6 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 3 3 0 1 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 7 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 5 2 2 5 -1 -1 8 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 5 2 2 5 -1 -1 8 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 2 2 2 5 -1 -1 8 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 2 2 2 5 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 325 CYCLE_DMA_1_ 3 -1 5 2 2 5 -1 -1 4 0 21 - 353 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 343 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 318 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 2 0 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 4 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 1 2 -1 -1 6 1 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 5 1 5 -1 -1 6 1 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 2 1 2 -1 -1 5 0 21 - 340 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 2 1 2 -1 -1 5 0 21 - 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 350 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 4 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 59 A_1_ 1 -1 -1 2 0 6 59 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 7 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 5 7 41 -1 1 0 21 - 79 RW_000 5 348 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 68 A_0_ 5 351 6 2 2 5 68 -1 3 0 21 - 70 RW 5 355 6 2 1 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 5 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 6 5 1 2 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 6 -1 -1 7 0 21 - 343 SM_AMIGA_i_7_ 3 -1 6 3 0 6 7 -1 -1 3 1 21 - 324 CYCLE_DMA_0_ 3 -1 7 3 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 6 3 1 3 6 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 0 3 4 -1 -1 1 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 13 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 2 5 -1 -1 13 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 2 5 -1 -1 11 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 2 2 5 -1 -1 9 1 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 5 2 2 5 -1 -1 8 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 325 CYCLE_DMA_1_ 3 -1 2 2 2 5 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 339 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 5 6 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 2 1 2 -1 -1 9 1 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 2 1 2 -1 -1 9 1 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 8 0 21 - 341 SM_AMIGA_2_ 3 -1 3 1 3 -1 -1 5 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 5 1 6 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 4 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 4 67 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 347 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 70 RW 5 352 6 2 5 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 6 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 3 78 -1 3 0 21 - 69 SIZE_0_ 5 350 6 1 3 69 -1 3 0 21 - 68 A_0_ 5 353 6 1 3 68 -1 3 0 21 - 40 BERR 5 -1 4 1 1 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 355 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 354 1 0 6 -1 9 0 21 - 82 BGACK_030 5 349 7 0 82 -1 3 0 21 - 34 VMA 5 351 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 348 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 349 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 4 0 2 5 6 -1 -1 3 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 2 3 5 7 -1 -1 3 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 6 3 2 5 6 -1 -1 11 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 6 3 2 5 6 -1 -1 10 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 2 3 -1 -1 7 0 21 - 325 CYCLE_DMA_1_ 3 -1 5 3 2 5 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 3 0 2 7 -1 -1 3 1 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 0 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 1 1 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 2 2 6 -1 -1 10 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 6 2 5 6 -1 -1 9 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 2 2 6 -1 -1 8 1 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 2 2 2 6 -1 -1 8 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 341 SM_AMIGA_2_ 3 -1 1 2 1 5 -1 -1 5 0 21 - 351 RN_VMA 3 34 3 2 1 3 34 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 2 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 2 1 2 -1 -1 12 0 21 - 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 340 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 - 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 350 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 - 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 59 A_1_ 1 -1 -1 2 0 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 347 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 70 RW 5 352 6 2 5 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 6 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 3 78 -1 3 0 21 - 69 SIZE_0_ 5 350 6 1 3 69 -1 3 0 21 - 68 A_0_ 5 353 6 1 3 68 -1 3 0 21 - 40 BERR 5 -1 4 1 1 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 355 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 354 1 0 6 -1 9 0 21 - 82 BGACK_030 5 349 7 0 82 -1 3 0 21 - 34 VMA 5 351 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 348 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 349 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 4 0 2 5 6 -1 -1 3 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 2 3 5 7 -1 -1 3 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 6 3 2 5 6 -1 -1 11 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 6 3 2 5 6 -1 -1 10 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 2 3 -1 -1 7 0 21 - 325 CYCLE_DMA_1_ 3 -1 5 3 2 5 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 3 0 2 7 -1 -1 3 1 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 0 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 1 1 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 2 2 6 -1 -1 10 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 6 2 5 6 -1 -1 9 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 2 2 6 -1 -1 8 1 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 2 2 2 6 -1 -1 8 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 341 SM_AMIGA_2_ 3 -1 1 2 1 5 -1 -1 5 0 21 - 351 RN_VMA 3 34 3 2 1 3 34 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 2 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 2 2 1 3 -1 -1 1 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 2 1 2 -1 -1 12 0 21 - 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 340 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 - 347 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 350 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 - 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 0 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 59 A_1_ 1 -1 -1 2 0 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 7 0 1 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 1 3 4 7 81 -1 1 0 21 - 79 RW_000 5 348 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 80 DSACK1 5 -1 7 3 2 5 6 80 -1 1 0 21 - 68 A_0_ 5 351 6 2 5 6 68 -1 3 0 21 - 70 RW 5 355 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 345 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 5 7 0 1 2 3 4 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_6_ 3 -1 2 6 0 1 2 5 6 7 -1 -1 3 0 21 - 309 CLK_000_D_1_ 3 -1 4 6 0 1 2 3 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 3 5 0 3 5 6 7 -1 -1 1 0 21 - 304 CYCLE_DMA_0_ 3 -1 1 4 1 2 5 6 -1 -1 3 0 21 - 325 CYCLE_DMA_1_ 3 -1 6 3 2 5 6 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 3 2 3 7 -1 -1 3 1 21 - 294 cpu_est_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 5 2 2 5 -1 -1 11 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 2 2 5 -1 -1 10 0 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 2 2 2 5 -1 -1 10 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 6 2 2 6 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 2 2 2 5 -1 -1 9 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 5 2 5 6 -1 -1 8 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 300 inst_AS_030_000_SYNC 3 -1 3 2 2 3 -1 -1 7 0 21 - 341 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 - 354 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_4_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 2 2 0 3 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 3 2 3 4 -1 -1 1 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 5 1 5 -1 -1 11 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 1 6 -1 -1 10 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 340 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 1 1 0 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 0 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 3 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 3 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 3 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 3 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 3 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 3 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 59 A_1_ 1 -1 -1 2 0 5 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 2 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 5 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 5 7 41 -1 1 0 21 - 79 RW_000 5 348 7 4 2 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 2 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 2 5 6 7 30 -1 1 0 21 - 68 A_0_ 5 353 6 2 2 5 68 -1 3 0 21 - 70 RW 5 352 6 2 1 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 5 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 347 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 346 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 355 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 354 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 351 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_6_ 3 -1 6 5 1 2 5 6 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 6 -1 -1 7 0 21 - 343 SM_AMIGA_i_7_ 3 -1 6 3 0 6 7 -1 -1 3 1 21 - 324 SM_AMIGA_0_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 3 3 0 2 3 -1 -1 3 0 21 - 322 SM_AMIGA_4_ 3 -1 6 3 1 3 6 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 7 3 2 5 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 0 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 0 3 4 -1 -1 1 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 13 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 2 5 -1 -1 13 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 2 5 -1 -1 11 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 10 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 2 2 5 -1 -1 9 1 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 5 2 2 5 -1 -1 8 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 8 0 21 - 325 CYCLE_DMA_1_ 3 -1 2 2 2 5 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 339 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 0 2 1 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 2 5 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 354 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 346 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 9 0 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 2 1 2 -1 -1 9 1 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 2 1 2 -1 -1 9 1 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 8 0 21 - 341 SM_AMIGA_2_ 3 -1 3 1 3 -1 -1 5 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 353 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 351 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 347 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 5 1 6 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 4 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 4 67 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 348 7 4 0 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 0 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 5 6 7 30 -1 1 0 21 - 80 DSACK1 5 -1 7 3 0 5 6 80 -1 1 0 21 - 68 A_0_ 5 351 6 2 2 5 68 -1 3 0 21 - 70 RW 5 355 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 346 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 345 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 1 6 0 1 2 3 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 4 0 2 5 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 0 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 3 2 3 7 -1 -1 7 0 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 6 3 0 5 6 -1 -1 6 1 21 - 323 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 3 1 2 3 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 7 -1 -1 1 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 0 2 0 5 -1 -1 7 1 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 5 2 0 5 -1 -1 7 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 0 2 0 5 -1 -1 6 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 0 5 -1 -1 6 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 0 2 0 5 -1 -1 6 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 5 2 5 6 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 324 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 322 SM_AMIGA_1_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 1 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 2 2 2 6 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 1 6 -1 -1 6 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 4 1 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 4 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 59 A_1_ 1 -1 -1 2 0 5 59 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 35 VPA 1 -1 -1 1 4 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 348 7 4 0 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 0 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 5 6 7 30 -1 1 0 21 - 80 DSACK1 5 -1 7 3 0 5 6 80 -1 1 0 21 - 68 A_0_ 5 351 6 2 2 5 68 -1 3 0 21 - 70 RW 5 355 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 346 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 345 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 1 6 0 1 2 3 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 4 0 2 5 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 0 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 3 2 3 7 -1 -1 7 0 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 6 3 0 5 6 -1 -1 6 1 21 - 323 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 3 1 2 3 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 7 -1 -1 1 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 0 2 0 5 -1 -1 7 1 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 5 2 0 5 -1 -1 7 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 0 2 0 5 -1 -1 6 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 0 5 -1 -1 6 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 0 2 0 5 -1 -1 6 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 5 2 5 6 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 324 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 322 SM_AMIGA_1_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 1 2 1 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 1 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 1 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 2 2 2 6 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 1 6 -1 -1 6 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 4 1 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 4 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 59 A_1_ 1 -1 -1 2 0 5 59 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 35 VPA 1 -1 -1 1 4 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 350 7 4 0 4 5 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 4 2 3 4 7 81 -1 1 0 21 - 70 RW 5 354 6 2 2 7 70 -1 2 0 21 - 68 A_0_ 5 346 6 2 0 2 68 -1 2 0 21 - 80 DSACK1 5 -1 7 2 0 5 80 -1 1 0 21 - 31 UDS_000 5 -1 3 2 0 5 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 0 5 30 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 0 78 -1 2 0 21 - 69 SIZE_0_ 5 355 6 1 0 69 -1 2 0 21 - 40 BERR 5 -1 4 1 6 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 349 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 351 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 3 6 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 1 6 1 2 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 7 3 2 3 7 -1 -1 7 0 21 - 335 CYCLE_DMA_1_ 3 -1 1 3 0 1 5 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 7 -1 -1 1 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 0 2 0 5 -1 -1 7 1 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 0 2 0 5 -1 -1 7 1 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 0 5 -1 -1 6 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 0 2 0 5 -1 -1 6 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 5 2 0 5 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 6 2 5 6 -1 -1 5 0 21 - 324 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 353 RN_VMA 3 34 3 2 3 6 34 -1 3 0 21 - 343 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 323 SM_AMIGA_0_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 2 2 2 6 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 3 6 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 0 1 0 -1 -1 6 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 6 0 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 0 1 0 -1 -1 6 1 21 - 340 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 5 0 21 - 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 4 1 21 - 339 SM_AMIGA_5_ 3 -1 2 1 2 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 1 1 1 -1 -1 3 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 4 1 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 4 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 350 7 4 0 2 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 70 RW 5 354 6 2 2 7 70 -1 2 0 21 - 68 A_0_ 5 346 6 2 0 1 68 -1 2 0 21 - 80 DSACK1 5 -1 7 2 0 2 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 0 78 -1 2 0 21 - 69 SIZE_0_ 5 355 6 1 0 69 -1 2 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 348 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 349 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 351 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 320 SM_AMIGA_6_ 3 -1 5 6 0 1 2 5 6 7 -1 -1 3 0 21 - 309 CLK_000_D_0_ 3 -1 6 6 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 3 6 1 2 3 5 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_4_ 3 -1 1 3 1 2 3 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 3 6 -1 -1 5 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 0 2 0 2 -1 -1 4 1 21 - 296 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 339 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 2 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 1 2 1 2 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 4 1 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 0 1 0 -1 -1 4 1 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 0 1 0 -1 -1 4 1 21 - 324 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 353 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 1 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 340 7 3 4 5 6 79 -1 4 0 21 - 70 RW 5 347 6 2 5 7 70 -1 2 0 21 - 68 A_0_ 5 344 6 2 3 5 68 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 2 0 21 - 69 SIZE_0_ 5 339 6 1 5 69 -1 2 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 2 5 0 2 3 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 1 2 6 7 -1 -1 1 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 299 inst_AS_030_D0 3 -1 3 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 3 -1 -1 5 0 21 - 318 CYCLE_DMA_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 4 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 3 2 3 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 350 7 3 4 5 6 79 -1 4 0 21 - 70 RW 5 354 6 2 0 7 70 -1 2 0 21 - 68 A_0_ 5 346 6 2 2 3 68 -1 2 0 21 - 80 DSACK1 5 -1 7 2 5 6 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 2 78 -1 2 0 21 - 69 SIZE_0_ 5 355 6 1 2 69 -1 2 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 349 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 351 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 321 SM_AMIGA_6_ 3 -1 1 6 0 1 2 3 5 7 -1 -1 3 0 21 - 310 CLK_000_D_0_ 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 295 cpu_est_1_ 3 -1 5 4 0 3 5 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 4 0 3 5 6 -1 -1 4 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 343 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 294 cpu_est_0_ 3 -1 3 3 0 3 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 333 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 5 6 -1 -1 5 0 21 - 332 DMA_CYCLE_FINISHED_2_ 3 -1 6 2 5 6 -1 -1 5 0 21 - 331 DMA_CYCLE_FINISHED_3_ 3 -1 6 2 5 6 -1 -1 5 0 21 - 335 CYCLE_DMA_1_ 3 -1 6 2 5 6 -1 -1 4 0 21 - 328 DMA_CYCLE_FINISHED_6_ 3 -1 6 2 5 6 -1 -1 4 1 21 - 353 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 - 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 341 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 1 6 -1 -1 4 0 21 - 334 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 4 0 21 - 330 DMA_CYCLE_FINISHED_4_ 3 -1 5 1 5 -1 -1 4 1 21 - 329 DMA_CYCLE_FINISHED_5_ 3 -1 6 1 6 -1 -1 4 1 21 - 325 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 322 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 3 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 327 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 326 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 320 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 2 1 1 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 350 7 4 0 2 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 70 RW 5 354 6 2 2 7 70 -1 2 0 21 - 68 A_0_ 5 346 6 2 0 1 68 -1 2 0 21 - 80 DSACK1 5 -1 7 2 0 2 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 0 78 -1 2 0 21 - 69 SIZE_0_ 5 355 6 1 0 69 -1 2 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 348 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 349 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 9 0 21 - 82 BGACK_030 5 352 7 0 82 -1 3 0 21 - 34 VMA 5 353 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 351 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 352 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 320 SM_AMIGA_6_ 3 -1 5 6 0 1 2 5 6 7 -1 -1 3 0 21 - 309 CLK_000_D_0_ 3 -1 6 6 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 3 6 1 2 3 5 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_4_ 3 -1 1 3 1 2 3 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 3 6 -1 -1 5 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 335 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 332 DMA_CYCLE_FINISHED_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 331 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 330 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 328 DMA_CYCLE_FINISHED_5_ 3 -1 0 2 0 2 -1 -1 4 1 21 - 296 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 339 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 3 0 21 - 334 CYCLE_DMA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 2 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 1 2 1 2 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 4 1 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 329 DMA_CYCLE_FINISHED_4_ 3 -1 0 1 0 -1 -1 4 1 21 - 327 DMA_CYCLE_FINISHED_6_ 3 -1 0 1 0 -1 -1 4 1 21 - 324 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 353 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 355 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 354 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 326 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 325 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 0 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 1 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -124 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 6 0 2 4 5 6 7 41 -1 1 0 21 - 81 AS_030 5 -1 7 5 0 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 348 7 4 2 4 5 6 79 -1 4 0 21 - 70 RW 5 353 6 2 0 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 2 5 80 -1 1 0 21 - 78 SIZE_1_ 5 346 7 1 5 78 -1 2 0 21 - 69 SIZE_0_ 5 349 6 1 5 69 -1 2 0 21 - 68 A_0_ 5 354 6 1 5 68 -1 2 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 356 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 355 1 0 6 -1 9 0 21 - 82 BGACK_030 5 351 7 0 82 -1 3 0 21 - 34 VMA 5 352 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 350 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 351 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 - 321 SM_AMIGA_6_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21 - 301 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 7 0 21 - 336 CYCLE_DMA_1_ 3 -1 6 3 2 5 6 -1 -1 4 0 21 - 324 SM_AMIGA_0_ 3 -1 6 3 0 6 7 -1 -1 3 0 21 - 302 inst_BGACK_030_INT_D 3 -1 2 3 1 6 7 -1 -1 1 0 21 - 300 inst_AS_030_D0 3 -1 4 3 3 4 7 -1 -1 1 0 21 - 304 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 8 0 21 - 343 DMA_CYCLE_FINISHED_i_7_ 3 -1 2 2 2 5 -1 -1 7 0 21 - 333 DMA_CYCLE_FINISHED_1_ 3 -1 5 2 2 5 -1 -1 7 0 21 - 332 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 2 5 -1 -1 7 0 21 - 331 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 2 5 -1 -1 7 0 21 - 328 DMA_CYCLE_FINISHED_6_ 3 -1 5 2 2 5 -1 -1 7 0 21 - 303 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 6 0 21 - 342 SM_AMIGA_2_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 344 SM_AMIGA_i_7_ 3 -1 0 2 0 7 -1 -1 3 1 21 - 335 CYCLE_DMA_0_ 3 -1 2 2 2 6 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 322 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 - 339 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 338 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 6 2 0 6 -1 -1 1 0 21 - 297 inst_AS_000_D0 3 -1 4 2 2 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 334 DMA_CYCLE_FINISHED_0_ 3 -1 5 1 5 -1 -1 8 0 21 - 330 DMA_CYCLE_FINISHED_4_ 3 -1 5 1 5 -1 -1 8 0 21 - 329 DMA_CYCLE_FINISHED_5_ 3 -1 2 1 2 -1 -1 8 0 21 - 337 inst_CLK_030_H 3 -1 5 1 5 -1 -1 7 0 21 - 341 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 325 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 352 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 340 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 354 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 353 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 350 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 349 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 346 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 327 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 326 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 6 1 0 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 1 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 2 4 7 56 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 59 A_1_ 1 -1 -1 1 1 59 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 79 RW_000 5 348 7 4 0 2 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 4 3 4 5 7 81 -1 1 0 21 - 70 RW 5 355 6 2 5 7 70 -1 2 0 21 - 68 A_0_ 5 351 6 2 2 6 68 -1 2 0 21 - 80 DSACK1 5 -1 7 2 0 2 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 6 78 -1 2 0 21 - 69 SIZE_0_ 5 346 6 1 6 69 -1 2 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 5 5 0 2 5 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 325 CYCLE_DMA_1_ 3 -1 1 3 0 1 2 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 2 3 0 1 2 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 3 1 3 5 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 2 2 0 2 -1 -1 10 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 2 2 0 2 -1 -1 10 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 0 2 0 2 -1 -1 6 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 2 2 0 2 -1 -1 6 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 - 296 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 339 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 7 2 6 7 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 3 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 0 1 0 -1 -1 10 0 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 2 1 2 -1 -1 10 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 2 1 2 -1 -1 10 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 336 inst_CLK_030_H 3 -1 0 1 0 -1 -1 7 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 2 1 2 -1 -1 6 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 1 3 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 3 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 1 1 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 1 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 1 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 1 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 4 5 6 7 41 -1 1 0 21 - 79 RW_000 5 348 7 3 0 4 6 79 -1 4 0 21 - 70 RW 5 355 6 2 3 7 70 -1 2 0 21 - 80 DSACK1 5 -1 7 2 0 6 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 1 78 -1 2 0 21 - 69 SIZE_0_ 5 346 6 1 1 69 -1 2 0 21 - 68 A_0_ 5 351 6 1 1 68 -1 2 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 5 0 1 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 5 0 1 3 5 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 3 5 7 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 3 0 6 7 -1 -1 6 0 21 - 324 CYCLE_DMA_0_ 3 -1 5 3 0 5 6 -1 -1 3 0 21 - 320 SM_AMIGA_6_ 3 -1 7 3 1 3 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 3 3 3 4 5 -1 -1 1 0 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 0 2 0 6 -1 -1 10 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 6 2 0 6 -1 -1 10 0 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 0 2 0 6 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 8 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 2 0 6 -1 -1 6 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 0 2 0 6 -1 -1 6 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 0 2 0 6 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 325 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 7 2 5 7 -1 -1 3 1 21 - 322 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 1 2 0 1 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 2 0 1 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 6 2 6 7 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 0 1 0 -1 -1 10 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 0 1 0 -1 -1 10 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 6 1 6 -1 -1 7 0 21 - 340 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 354 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 339 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 3 1 3 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 1 3 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 7 1 7 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 6 1 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 0 1 7 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 0 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 63 CLK_030 1 -1 -1 2 0 6 63 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -123 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 6 7 41 -1 1 0 21 - 79 RW_000 5 348 7 4 0 2 4 6 79 -1 4 0 21 - 70 RW 5 355 6 2 2 7 70 -1 2 0 21 - 68 A_0_ 5 351 6 2 3 5 68 -1 2 0 21 - 80 DSACK1 5 -1 7 2 0 6 80 -1 1 0 21 - 78 SIZE_1_ 5 345 7 1 5 78 -1 2 0 21 - 69 SIZE_0_ 5 346 6 1 5 69 -1 2 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 1 6 0 1 2 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 7 5 1 2 3 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 - 333 DMA_CYCLE_FINISHED_2_ 3 -1 6 3 0 2 6 -1 -1 10 0 21 - 300 inst_AS_030_000_SYNC 3 -1 0 3 0 3 7 -1 -1 7 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 0 3 0 2 6 -1 -1 6 0 21 - 332 DMA_CYCLE_FINISHED_3_ 3 -1 6 3 0 2 6 -1 -1 6 0 21 - 325 CYCLE_DMA_1_ 3 -1 2 3 0 2 6 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 3 0 2 6 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 3 3 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 3 3 0 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 1 1 21 - 335 DMA_CYCLE_FINISHED_0_ 3 -1 0 2 0 2 -1 -1 10 0 21 - 331 DMA_CYCLE_FINISHED_4_ 3 -1 6 2 0 6 -1 -1 10 0 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 8 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 - 326 RST_DLY_0_ 3 -1 1 2 1 5 -1 -1 4 0 21 - 354 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 343 SM_AMIGA_i_7_ 3 -1 7 2 0 7 -1 -1 3 1 21 - 339 SM_AMIGA_5_ 3 -1 7 2 3 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 5 2 1 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 1 2 1 5 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 - 330 DMA_CYCLE_FINISHED_5_ 3 -1 6 1 6 -1 -1 10 0 21 - 329 DMA_CYCLE_FINISHED_6_ 3 -1 6 1 6 -1 -1 10 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 336 inst_CLK_030_H 3 -1 2 1 2 -1 -1 7 0 21 - 342 DMA_CYCLE_FINISHED_i_7_ 3 -1 6 1 6 -1 -1 6 0 21 - 341 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 - 340 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 323 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 7 1 7 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 3 1 7 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 1 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 1 10 -1 121 "number of signals after reading design file" @@ -6221,15 +133,17 @@ "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21 - 79 RW_000 5 345 7 4 0 2 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 6 1 3 4 5 6 7 81 -1 1 0 21 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 70 RW 5 350 6 2 3 7 70 -1 2 0 21 - 78 SIZE_1_ 5 343 7 1 3 78 -1 2 0 21 - 69 SIZE_0_ 5 346 6 1 3 69 -1 2 0 21 - 68 A_0_ 5 351 6 1 3 68 -1 2 0 21 - 80 DSACK1 5 -1 7 1 2 80 -1 1 0 21 + 79 RW_000 5 344 7 3 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 347 6 2 1 2 68 -1 3 0 21 + 70 RW 5 351 6 2 1 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 342 7 1 2 78 -1 3 0 21 + 69 SIZE_0_ 5 352 6 1 2 69 -1 3 0 21 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -6238,9 +152,260 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 344 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 352 1 0 6 -1 9 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 348 1 0 6 -1 10 0 21 + 82 BGACK_030 5 346 7 0 82 -1 3 0 21 + 34 VMA 5 350 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 345 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 346 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 312 CLK_000_D_0_ 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 308 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 + 324 SM_AMIGA_6_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 4 2 5 6 7 -1 -1 1 0 21 + 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 326 SM_AMIGA_1_ 3 -1 0 3 0 5 6 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 6 3 0 1 6 -1 -1 3 0 21 + 340 CLK_OUT_INTreg 3 -1 2 3 1 2 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 328 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 350 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 339 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 336 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 322 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 + 321 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 335 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 334 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 329 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 323 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 314 inst_DTACK_DMA 3 -1 0 2 0 3 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 305 inst_VPA_D 3 -1 1 2 0 3 -1 -1 1 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 348 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 330 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 309 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 338 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 337 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 331 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 352 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 347 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 351 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 341 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 333 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 332 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 310 inst_AMIGA_DS 3 -1 6 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 4 1 2 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 3 4 5 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 59 A_1_ 1 -1 -1 2 2 5 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 2 RESET 1 -1 -1 2 1 2 2 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +120 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 344 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 351 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 342 7 1 1 78 -1 3 0 21 + 69 SIZE_0_ 5 352 6 1 1 69 -1 3 0 21 + 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 350 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 313 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 312 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 325 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 + 309 inst_RESET_OUT 3 -1 6 4 3 4 6 7 -1 -1 2 0 21 + 297 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 327 SM_AMIGA_1_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 1 3 0 1 2 -1 -1 3 0 21 + 341 CLK_OUT_INTreg 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 329 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 350 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 340 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 337 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 324 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 323 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 336 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 335 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 + 330 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 322 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 315 inst_DTACK_DMA 3 -1 0 2 0 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 316 inst_CLK_OUT_PRE_D 3 -1 6 2 2 7 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21 + 306 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 331 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 310 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 339 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 338 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 332 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 352 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 351 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 333 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 311 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 301 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 293 N_266_0 3 -1 4 1 4 -1 -1 2 0 21 + 321 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 320 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 319 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 317 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 307 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +119 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 346 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 350 6 2 5 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 351 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 342 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 1 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 82 BGACK_030 5 348 7 0 82 -1 3 0 21 34 VMA 5 349 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 @@ -6249,260 +414,6 @@ 28 BG_000 5 347 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 31 UDS_000 0 3 0 31 -1 1 0 21 - 30 LDS_000 0 3 0 30 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 348 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 5 4 3 5 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 296 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 325 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 1 3 1 2 6 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 1 3 0 1 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 - 340 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 - 318 DMA_CYCLE_FINISHED_5_ 3 -1 2 2 0 2 -1 -1 5 0 21 - 317 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 349 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 341 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 338 SM_AMIGA_5_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 326 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 6 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 0 2 0 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 5 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 337 DMA_CYCLE_FINISHED_4_ 3 -1 2 1 2 -1 -1 6 0 21 - 336 DMA_CYCLE_FINISHED_3_ 3 -1 2 1 2 -1 -1 6 0 21 - 335 DMA_CYCLE_FINISHED_2_ 3 -1 2 1 2 -1 -1 6 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 2 1 2 -1 -1 6 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 2 1 2 -1 -1 6 0 21 - 330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 6 0 21 - 339 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 5 0 21 - 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 320 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 2 0 21 - 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 2 0 21 - 343 RN_SIZE_1_ 3 78 7 1 7 78 -1 2 0 21 - 342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 321 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 7 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 59 A_1_ 1 -1 -1 2 2 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -121 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 79 RW_000 5 348 7 4 0 2 4 6 79 -1 4 0 21 - 81 AS_030 5 -1 7 4 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 4 0 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 2 6 7 30 -1 1 0 21 - 68 A_0_ 5 343 6 2 0 6 68 -1 3 0 21 - 70 RW 5 353 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 345 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 351 6 1 0 69 -1 3 0 21 - 80 DSACK1 5 -1 7 1 2 80 -1 1 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 344 1 0 6 -1 9 0 21 - 82 BGACK_030 5 350 7 0 82 -1 3 0 21 - 34 VMA 5 352 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 349 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 350 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 322 SM_AMIGA_6_ 3 -1 1 6 0 1 2 5 6 7 -1 -1 3 0 21 - 309 CLK_000_D_0_ 3 -1 6 6 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 - 341 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 323 SM_AMIGA_4_ 3 -1 6 3 3 5 6 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 334 DMA_CYCLE_FINISHED_1_ 3 -1 2 2 0 2 -1 -1 10 0 21 - 318 DMA_CYCLE_FINISHED_5_ 3 -1 0 2 0 2 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 6 0 21 - 340 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 - 317 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 296 cpu_est_3_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 338 SM_AMIGA_5_ 3 -1 2 2 2 6 -1 -1 3 0 21 - 326 CYCLE_DMA_0_ 3 -1 2 2 0 2 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 1 2 1 7 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 337 DMA_CYCLE_FINISHED_4_ 3 -1 0 1 0 -1 -1 10 0 21 - 336 DMA_CYCLE_FINISHED_3_ 3 -1 0 1 0 -1 -1 10 0 21 - 335 DMA_CYCLE_FINISHED_2_ 3 -1 0 1 0 -1 -1 10 0 21 - 333 DMA_CYCLE_FINISHED_0_ 3 -1 2 1 2 -1 -1 10 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 7 0 21 - 339 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 352 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 345 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 353 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 349 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 342 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 0 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 0 1 1 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 80 DSACK1 0 7 0 80 -1 1 0 21 77 FPU_CS 0 7 0 77 -1 1 0 21 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 @@ -6510,428 +421,321 @@ 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 0 5 6 7 -1 -1 1 0 21 - 324 SM_AMIGA_1_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 2 2 3 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 2 3 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 2 2 2 6 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 6 2 2 6 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 2 3 -1 -1 1 1 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 318 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 5 1 0 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 0 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 59 A_1_ 1 -1 -1 2 0 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 8 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21 - 326 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 325 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 322 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 2 3 5 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 4 1 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 N_67 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 2 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 6 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 1 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 70 RW 5 344 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 342 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 2 0 21 - 341 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 4 5 7 -1 -1 1 0 21 - 309 CLK_000_D_0_ 3 -1 6 6 0 1 2 3 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 - 296 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 5 2 3 5 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 324 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 3 2 3 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 3 2 3 5 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 5 2 1 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 6 2 5 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 6 2 2 7 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 1 1 1 -1 -1 6 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 325 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 342 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 7 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 4 1 6 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 1 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 - 79 RW_000 5 343 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 70 RW 5 348 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 3 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 3 69 -1 3 0 21 - 68 A_0_ 5 339 6 1 3 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 342 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 341 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 340 1 0 6 -1 9 0 21 - 82 BGACK_030 5 345 7 0 82 -1 3 0 21 - 34 VMA 5 347 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 344 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 345 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 5 5 1 2 3 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 0 5 6 7 -1 -1 1 0 21 - 328 RST_DLY_0_ 3 -1 2 3 0 1 2 -1 -1 4 0 21 - 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 3 1 3 5 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 2 3 0 1 2 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 1 3 0 1 2 -1 -1 2 1 21 - 311 inst_CLK_OUT_PRE_D 3 -1 5 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 5 0 21 - 347 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 333 SM_AMIGA_5_ 3 -1 1 2 1 6 -1 -1 3 0 21 - 324 CYCLE_DMA_0_ 3 -1 6 2 0 6 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 6 2 2 6 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 3 2 3 7 -1 -1 2 0 21 + 348 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 312 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 4 4 0 2 6 7 -1 -1 1 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 295 cpu_est_3_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 + 338 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 + 324 SM_AMIGA_4_ 3 -1 6 3 1 5 6 -1 -1 3 0 21 + 323 SM_AMIGA_6_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 5 3 1 3 5 -1 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 3 3 3 4 7 -1 -1 2 0 21 + 339 CLK_OUT_INTreg 3 -1 7 3 0 1 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 1 3 6 -1 -1 1 1 21 + 337 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 5 0 21 + 349 RN_VMA 3 34 3 2 1 3 34 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 334 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 + 333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 5 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 - 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 341 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 327 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 7 0 21 - 326 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 343 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 325 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 - 348 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 2 2 0 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 0 2 0 2 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21 + 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 309 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 + 303 inst_AS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 327 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 351 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 335 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21 + 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 328 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 + 310 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 2 1 2 -1 -1 2 0 21 + 319 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 318 CLK_000_D_2_ 3 -1 1 1 2 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 6 1 1 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 2 1 5 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 81 AS_030 1 -1 -1 6 2 3 4 5 6 7 81 -1 + 13 nEXP_SPACE 1 -1 -1 5 2 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +119 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 346 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 350 6 2 5 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 + 69 SIZE_0_ 5 351 6 1 5 69 -1 3 0 21 + 68 A_0_ 5 342 6 1 5 68 -1 3 0 21 + 40 BERR 5 -1 4 1 1 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 + 82 BGACK_030 5 348 7 0 82 -1 3 0 21 + 34 VMA 5 349 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 347 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 348 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 312 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 4 4 0 2 6 7 -1 -1 1 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 + 295 cpu_est_3_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 + 338 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 + 324 SM_AMIGA_4_ 3 -1 6 3 1 5 6 -1 -1 3 0 21 + 323 SM_AMIGA_6_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 5 3 1 3 5 -1 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 3 3 3 4 7 -1 -1 2 0 21 + 339 CLK_OUT_INTreg 3 -1 7 3 0 1 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 1 3 6 -1 -1 1 1 21 + 337 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 5 0 21 + 349 RN_VMA 3 34 3 2 1 3 34 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 6 2 5 6 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 334 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 + 333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 322 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 2 2 0 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 0 2 0 2 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 0 2 1 3 -1 -1 1 0 21 + 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 309 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 + 303 inst_AS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 5 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 + 327 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 351 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 342 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 335 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21 + 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 347 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 + 328 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 + 310 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 2 1 2 -1 -1 2 0 21 + 319 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 318 CLK_000_D_2_ 3 -1 1 1 2 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 6 1 1 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 2 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 81 AS_030 1 -1 -1 6 2 3 4 5 6 7 81 -1 + 13 nEXP_SPACE 1 -1 -1 5 2 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A_1_ 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +120 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 346 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 351 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 342 7 1 1 78 -1 3 0 21 + 69 SIZE_0_ 5 352 6 1 1 69 -1 3 0 21 + 68 A_0_ 5 344 6 1 1 68 -1 3 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 0 29 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 343 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 350 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 312 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 311 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 5 5 0 1 2 5 7 -1 -1 3 0 21 + 308 inst_RESET_OUT 3 -1 6 4 3 4 6 7 -1 -1 2 0 21 + 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 326 SM_AMIGA_1_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 1 3 0 1 2 -1 -1 3 0 21 + 340 CLK_OUT_INTreg 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 328 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 350 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 339 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 336 SM_AMIGA_5_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 323 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 322 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 314 inst_DTACK_DMA 3 -1 0 2 0 3 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 + 335 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 334 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 + 329 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 315 inst_CLK_OUT_PRE_D 3 -1 6 2 2 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_50 3 -1 1 2 1 6 -1 -1 1 0 21 + 305 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 330 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 309 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 338 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 337 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 331 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 352 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 + 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 342 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 + 351 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 341 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 333 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 332 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 + 310 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 320 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 307 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 306 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 5 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 @@ -6940,35 +744,35 @@ 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 0 59 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 7 10 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 116 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 5 1 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 6 7 41 -1 1 0 21 - 79 RW_000 5 343 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 339 6 2 0 3 68 -1 3 0 21 - 70 RW 5 348 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 0 69 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 81 AS_030 5 -1 7 6 2 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 4 5 7 41 -1 1 0 21 + 79 RW_000 5 343 7 3 1 4 6 79 -1 4 0 21 + 70 RW 5 -1 6 2 6 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21 + 68 A_0_ 5 -1 6 1 5 68 -1 2 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 29 DTACK 5 -1 3 1 3 29 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -6977,11 +781,11 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 342 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 341 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 340 1 0 6 -1 9 0 21 + 8 IPL_030_2_ 5 342 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 82 BGACK_030 5 345 7 0 82 -1 3 0 21 - 34 VMA 5 347 3 0 34 -1 3 0 21 + 34 VMA 5 346 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -6996,70 +800,70 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 345 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 6 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 5 5 0 1 3 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 6 3 0 2 6 -1 -1 3 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 0 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 5 0 21 - 325 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 347 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 0 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 - 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 341 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 327 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 7 0 21 - 326 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 311 CLK_000_D_0_ 3 -1 2 6 0 2 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 324 SM_AMIGA_6_ 3 -1 2 4 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 6 4 3 4 6 7 -1 -1 2 0 21 + 295 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 327 SM_AMIGA_0_ 3 -1 0 3 0 2 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 4 3 3 4 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21 + 331 RST_DLY_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 + 328 CYCLE_DMA_0_ 3 -1 5 2 1 5 -1 -1 4 0 21 + 346 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 339 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 + 326 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 322 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 321 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21 + 313 inst_DTACK_DMA 3 -1 5 2 3 5 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 335 inst_AS_000_INT 3 -1 7 2 4 7 -1 -1 2 0 21 + 334 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 + 333 RST_DLY_2_ 3 -1 0 2 0 6 -1 -1 2 0 21 + 332 RST_DLY_1_ 3 -1 6 2 0 6 -1 -1 2 1 21 + 329 CYCLE_DMA_1_ 3 -1 5 2 1 5 -1 -1 2 0 21 + 320 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 6 2 2 6 -1 -1 2 0 21 + 340 CLK_OUT_INTreg 3 -1 0 2 1 6 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 3 2 0 1 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 5 2 2 4 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 330 CLK_030_PE_0_ 3 -1 1 1 1 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 1 1 1 -1 -1 6 0 21 + 338 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 337 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 343 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 348 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 336 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 3 0 21 344 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 N_81 3 -1 4 1 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 5 1 0 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 0 1 5 -1 -1 1 0 21 + 341 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21 + 323 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21 + 319 CLK_000_D_4_ 3 -1 4 1 2 -1 -1 1 0 21 + 318 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 + 317 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 316 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 1 3 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 13 nEXP_SPACE 1 -1 -1 5 2 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 @@ -7068,150 +872,27 @@ 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 + 63 CLK_030 1 -1 -1 1 1 63 -1 59 A_1_ 1 -1 -1 1 2 59 -1 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 + 35 VPA 1 -1 -1 1 0 35 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -116 "number of signals after reading design file" + 10 CLK_000 1 -1 -1 1 2 10 -1 +115 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 5 1 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 2 4 6 7 41 -1 1 0 21 - 79 RW_000 5 343 7 3 0 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 339 6 2 0 3 68 -1 3 0 21 - 70 RW 5 348 6 2 1 7 70 -1 2 0 21 - 78 SIZE_1_ 5 338 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 0 69 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 342 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 341 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 340 1 0 6 -1 9 0 21 - 82 BGACK_030 5 345 7 0 82 -1 3 0 21 - 34 VMA 5 347 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 344 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 345 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 6 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 5 5 0 1 3 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21 - 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 6 3 0 2 6 -1 -1 3 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 0 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 5 0 21 - 325 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 347 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 323 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 0 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 - 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 341 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 327 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 7 0 21 - 326 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21 - 334 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 343 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 339 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 3 0 21 - 348 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 N_81 3 -1 4 1 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 5 1 0 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 0 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 4 2 3 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 - 79 RW_000 5 343 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 - 70 RW 5 348 6 2 3 7 70 -1 2 0 21 - 78 SIZE_1_ 5 341 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 346 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 349 6 1 1 68 -1 3 0 21 + 81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 -1 6 2 6 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21 + 68 A_0_ 5 -1 6 1 2 68 -1 2 0 21 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 @@ -7221,134 +902,11 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 342 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 340 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 339 1 0 6 -1 9 0 21 - 82 BGACK_030 5 345 7 0 82 -1 3 0 21 - 34 VMA 5 347 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 344 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 345 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 5 4 1 3 5 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 328 RST_DLY_0_ 3 -1 0 3 0 2 6 -1 -1 4 0 21 - 295 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 - 324 CYCLE_DMA_0_ 3 -1 0 3 0 5 6 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 3 0 3 5 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 - 330 RST_DLY_2_ 3 -1 6 3 0 2 6 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 2 3 0 2 6 -1 -1 2 1 21 - 337 CLK_OUT_INTreg 3 -1 3 3 1 5 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 1 1 21 - 327 CLK_030_PE_1_ 3 -1 6 2 5 6 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 6 0 21 - 302 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 5 0 21 - 325 CYCLE_DMA_1_ 3 -1 5 2 5 6 -1 -1 4 0 21 - 347 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 0 2 0 1 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 1 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 342 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 326 CLK_030_PE_0_ 3 -1 6 1 6 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 343 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 349 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 348 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 344 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 1 1 3 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 - 63 CLK_030 1 -1 -1 2 5 6 63 -1 - 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 7 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -117 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 342 7 4 0 2 4 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 4 0 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 2 6 7 30 -1 1 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 70 RW 5 347 6 2 5 7 70 -1 2 0 21 - 40 BERR 5 -1 4 2 0 3 40 -1 1 0 21 - 78 SIZE_1_ 5 340 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 345 6 1 2 69 -1 3 0 21 - 68 A_0_ 5 348 6 1 2 68 -1 3 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 341 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 339 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 349 1 0 6 -1 9 0 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 82 BGACK_030 5 344 7 0 82 -1 3 0 21 - 34 VMA 5 346 3 0 34 -1 3 0 21 + 34 VMA 5 345 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 @@ -7363,65 +921,63 @@ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 CLK_000_D_1_ 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 337 CLK_OUT_INTreg 3 -1 1 4 0 1 2 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 6 4 1 5 6 7 -1 -1 1 0 21 - 296 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 321 SM_AMIGA_6_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 0 3 0 1 2 -1 -1 1 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21 + 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 340 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 8 0 21 - 327 CLK_030_PE_0_ 3 -1 0 2 0 2 -1 -1 7 0 21 - 308 CLK_030_PE_1_ 3 -1 0 2 0 2 -1 -1 7 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 335 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 - 334 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 5 0 21 - 325 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 346 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 324 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 - 322 SM_AMIGA_4_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 326 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 - 306 inst_DTACK_D0 3 -1 5 2 0 3 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 339 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 + 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 + 330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21 + 328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 3 1 3 -1 -1 4 0 21 - 348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 345 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 340 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 333 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 3 1 3 -1 -1 2 1 21 - 317 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 4 1 1 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 1 5 -1 -1 1 0 21 + 339 N_280 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21 + 318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 @@ -7429,639 +985,36 @@ 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 59 A_1_ 1 -1 -1 2 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 63 CLK_030 1 -1 -1 1 2 63 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" +115 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 344 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21 - 68 A_0_ 5 340 6 2 1 5 68 -1 3 0 21 - 70 RW 5 349 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 339 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 347 6 1 5 69 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 343 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 342 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 341 1 0 6 -1 9 0 21 - 82 BGACK_030 5 346 7 0 82 -1 3 0 21 - 34 VMA 5 348 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 345 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 346 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 310 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 1 6 0 1 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 2 3 5 -1 -1 7 0 21 - 336 SM_AMIGA_i_7_ 3 -1 5 3 2 5 7 -1 -1 3 1 21 - 322 SM_AMIGA_4_ 3 -1 0 3 0 3 5 -1 -1 3 0 21 - 321 SM_AMIGA_6_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 - 337 CLK_OUT_INTreg 3 -1 2 3 0 1 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 335 SM_AMIGA_2_ 3 -1 3 2 3 5 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 5 0 21 - 296 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 333 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_1_ 3 -1 5 2 1 5 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 332 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 331 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 0 2 0 2 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 343 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 341 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 327 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 8 0 21 - 308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 8 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 8 0 21 - 334 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 344 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 328 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 325 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 348 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 347 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 293 cpu_est_0_ 3 -1 3 1 3 -1 -1 3 0 21 - 349 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 345 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 330 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 329 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 326 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 7 1 4 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 4 1 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 29 DTACK 1 -1 -1 1 2 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 344 6 2 1 5 68 -1 3 0 21 - 70 RW 5 347 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 339 6 1 1 69 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 323 SM_AMIGA_0_ 3 -1 0 3 0 2 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 5 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 325 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 336 CLK_OUT_INTreg 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 7 2 3 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 6 2 6 7 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 2 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 333 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 N_60 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 344 6 2 1 5 68 -1 3 0 21 - 70 RW 5 347 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 339 6 1 1 69 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 - 320 SM_AMIGA_6_ 3 -1 2 5 0 1 2 5 7 -1 -1 3 0 21 - 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 - 323 SM_AMIGA_0_ 3 -1 0 3 0 2 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 5 0 21 - 302 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 5 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 325 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 336 CLK_OUT_INTreg 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 7 2 3 6 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 6 2 6 7 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 1 2 2 6 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 333 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 N_60 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 316 CLK_000_D_4_ 3 -1 6 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 29 DTACK 1 -1 -1 1 3 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 0 2 3 4 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 70 RW 5 344 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 337 7 1 1 78 -1 3 0 21 - 69 SIZE_0_ 5 339 6 1 1 69 -1 3 0 21 - 68 A_0_ 5 345 6 1 1 68 -1 3 0 21 - 40 BERR 5 -1 4 1 5 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 309 CLK_000_D_0_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 295 cpu_est_3_ 3 -1 0 4 0 3 5 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 4 0 3 5 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 2 4 0 1 2 7 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 6 4 0 3 5 6 -1 -1 3 0 21 - 294 cpu_est_2_ 3 -1 3 4 0 3 5 6 -1 -1 1 1 21 - 323 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 3 3 0 3 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 6 0 21 - 302 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 6 0 21 - 326 RST_DLY_0_ 3 -1 5 2 1 5 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 1 2 1 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 2 1 5 -1 -1 2 1 21 - 325 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 336 CLK_OUT_INTreg 3 -1 7 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 5 2 6 7 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 3 2 3 5 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 6 2 0 2 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 333 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 - 332 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 N_243 3 -1 4 1 4 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 0 1 2 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 4 1 6 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 29 DTACK 1 -1 -1 1 5 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 0 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 3 4 5 7 81 -1 1 0 21 - 79 RW_000 5 339 7 4 0 3 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 4 0 3 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 4 0 3 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 4 0 3 6 7 30 -1 1 0 21 - 68 A_0_ 5 344 6 2 0 2 68 -1 3 0 21 - 70 RW 5 345 6 2 0 7 70 -1 2 0 21 - 29 DTACK 5 342 3 1 6 29 -1 6 0 21 - 78 SIZE_1_ 5 336 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 338 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 337 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 341 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 340 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 341 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 308 CLK_000_D_0_ 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 306 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 307 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 296 cpu_est_3_ 3 -1 5 4 2 3 5 6 -1 -1 4 0 21 - 294 cpu_est_1_ 3 -1 5 4 2 3 5 6 -1 -1 4 0 21 - 319 SM_AMIGA_6_ 3 -1 1 4 0 1 2 7 -1 -1 3 0 21 - 334 CLK_OUT_INTreg 3 -1 3 4 0 1 3 6 -1 -1 1 0 21 - 295 cpu_est_2_ 3 -1 2 4 2 3 5 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 - 333 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 322 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 - 320 SM_AMIGA_4_ 3 -1 6 3 0 2 6 -1 -1 3 0 21 - 293 cpu_est_0_ 3 -1 5 3 2 3 5 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 342 RN_DTACK 3 29 3 2 3 7 29 -1 6 0 21 - 332 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 325 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 4 0 21 - 323 CYCLE_DMA_0_ 3 -1 0 2 0 3 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 330 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 3 0 21 - 317 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 316 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 329 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 - 328 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 327 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 - 326 RST_DLY_1_ 3 -1 6 2 2 6 -1 -1 2 1 21 - 324 CYCLE_DMA_1_ 3 -1 3 2 0 3 -1 -1 2 0 21 - 318 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 310 inst_CLK_OUT_PRE_D 3 -1 7 2 0 3 -1 -1 1 0 21 - 304 CLK_000_D_3_ 3 -1 0 2 1 5 -1 -1 1 0 21 - 303 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 337 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 302 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 6 0 21 - 331 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 336 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 321 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 335 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 315 CLK_000_D_4_ 3 -1 5 1 1 -1 -1 1 0 21 - 314 CLK_000_D_2_ 3 -1 3 1 0 -1 -1 1 0 21 - 313 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 311 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 309 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 - 305 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 0 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 1 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 + 81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 343 6 2 2 3 68 -1 3 0 21 - 70 RW 5 347 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 338 6 1 2 69 -1 3 0 21 + 79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 -1 6 2 6 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21 + 68 A_0_ 5 -1 6 1 2 68 -1 2 0 21 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -8070,15 +1023,15 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 344 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 344 7 0 82 -1 3 0 21 34 VMA 5 345 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 + 28 BG_000 5 343 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 80 DSACK1 0 7 0 80 -1 1 0 21 @@ -8088,304 +1041,64 @@ 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 CLK_000_D_0_ 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 308 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 293 cpu_est_0_ 3 -1 7 5 0 1 3 6 7 -1 -1 3 0 21 - 294 cpu_est_1_ 3 -1 6 4 0 1 3 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 1 4 0 1 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 1 3 1 3 7 -1 -1 5 0 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 333 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 4 0 21 - 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 - 325 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 335 CLK_OUT_INTreg 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 6 2 1 3 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 0 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 0 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 7 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 7 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -114 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 343 6 2 2 3 68 -1 3 0 21 - 70 RW 5 347 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 338 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 346 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 345 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 CLK_000_D_0_ 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 308 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 293 cpu_est_0_ 3 -1 7 5 0 1 3 6 7 -1 -1 3 0 21 - 294 cpu_est_1_ 3 -1 6 4 0 1 3 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 3 0 21 - 295 cpu_est_2_ 3 -1 1 4 0 1 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 1 3 1 3 7 -1 -1 5 0 21 - 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 333 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 - 325 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 335 CLK_OUT_INTreg 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 6 2 1 3 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 0 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 - 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 0 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 7 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 7 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 344 6 2 2 3 68 -1 3 0 21 - 70 RW 5 345 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 339 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 309 CLK_000_D_0_ 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 308 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 294 cpu_est_0_ 3 -1 7 5 0 1 3 6 7 -1 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 0 5 0 3 4 6 7 -1 -1 2 0 21 - 295 cpu_est_1_ 3 -1 6 4 0 1 3 6 -1 -1 4 0 21 - 320 SM_AMIGA_6_ 3 -1 5 4 2 3 5 7 -1 -1 3 0 21 - 296 cpu_est_2_ 3 -1 1 4 0 1 3 6 -1 -1 1 1 21 - 302 inst_AS_000_DMA 3 -1 1 3 1 3 7 -1 -1 5 0 21 + 344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21 + 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 + 326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 339 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 - 333 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 5 0 21 - 326 RST_DLY_0_ 3 -1 2 2 0 2 -1 -1 4 0 21 - 324 CYCLE_DMA_0_ 3 -1 2 2 1 2 -1 -1 4 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 334 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 331 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 321 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 0 2 0 2 -1 -1 2 1 21 - 325 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 335 CLK_OUT_INTreg 3 -1 3 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 6 2 1 3 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 0 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 332 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 344 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 339 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 0 1 5 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 7 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 + 330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21 + 328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21 + 318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 @@ -8393,36 +1106,278 @@ 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 7 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 5 35 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 6 10 -1 115 "number of signals after reading design file" +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 -1 6 2 6 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21 + 68 A_0_ 5 -1 6 1 2 68 -1 2 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 346 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 345 1 0 6 -1 10 0 21 + 82 BGACK_030 5 344 7 0 82 -1 3 0 21 + 34 VMA 5 347 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 343 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21 + 295 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 339 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 + 330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 347 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21 + 328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 346 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 345 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 340 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21 + 318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +115 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 342 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 -1 6 2 6 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 2 0 21 + 68 A_0_ 5 -1 6 1 2 68 -1 2 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 341 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 347 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 346 1 0 6 -1 10 0 21 + 82 BGACK_030 5 344 7 0 82 -1 3 0 21 + 34 VMA 5 345 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 343 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 344 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21 + 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 + 323 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 0 4 0 3 4 7 -1 -1 2 0 21 + 296 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 326 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 340 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 337 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 5 0 21 + 330 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 327 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 338 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 335 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 325 SM_AMIGA_1_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 324 SM_AMIGA_4_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 320 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 334 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 333 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 331 RST_DLY_1_ 3 -1 3 2 0 3 -1 -1 2 1 21 + 328 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 2 2 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 341 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 329 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 + 308 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 + 336 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 339 N_154 3 -1 4 1 4 -1 -1 2 0 21 + 309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 322 inst_BGACK_030_INT_D 3 -1 7 1 5 -1 -1 1 0 21 + 318 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 7 1 6 -1 -1 1 0 21 + 316 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 63 CLK_030 1 -1 -1 1 2 63 -1 + 59 A_1_ 1 -1 -1 1 5 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +112 "number of signals after reading design file" + "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 1 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 1 6 7 30 -1 1 0 21 - 79 RW_000 5 340 7 2 4 6 79 -1 4 0 21 - 70 RW 5 347 6 2 5 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 338 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 343 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 6 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 3 29 -1 1 0 21 + 79 RW_000 5 341 7 3 1 4 6 79 -1 4 0 21 + 68 A_0_ 5 -1 6 2 0 5 68 -1 2 0 21 + 70 RW 5 -1 6 2 5 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -8432,14 +1387,14 @@ 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 345 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 344 1 0 6 -1 10 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 346 3 0 34 -1 3 0 21 + 7 IPL_030_0_ 5 342 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 340 1 0 6 -1 10 0 21 + 82 BGACK_030 5 344 7 0 82 -1 3 0 21 + 34 VMA 5 345 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 + 28 BG_000 5 343 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 80 DSACK1 0 7 0 80 -1 1 0 21 @@ -8449,64 +1404,62 @@ 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 307 inst_RESET_OUT 3 -1 5 6 0 3 4 5 6 7 -1 -1 2 0 21 - 308 CLK_000_D_1_ 3 -1 7 6 0 3 4 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_0_ 3 -1 6 5 0 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 0 2 3 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 1 3 1 3 7 -1 -1 5 0 21 - 334 SM_AMIGA_i_7_ 3 -1 0 3 0 2 7 -1 -1 3 1 21 - 321 SM_AMIGA_4_ 3 -1 0 3 0 5 6 -1 -1 3 0 21 - 320 SM_AMIGA_6_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 333 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 5 0 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 5 0 21 - 324 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 346 RN_VMA 3 34 3 2 3 6 34 -1 3 0 21 - 323 SM_AMIGA_0_ 3 -1 0 2 0 7 -1 -1 3 0 21 - 322 SM_AMIGA_1_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 318 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 317 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 - 330 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 329 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 325 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 2 0 21 - 319 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 335 CLK_OUT_INTreg 3 -1 0 2 1 6 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_D 3 -1 2 2 0 1 -1 -1 1 0 21 - 310 inst_CLK_OUT_PRE_50 3 -1 0 2 0 2 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 3 2 0 2 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 3 6 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 1 1 21 - 345 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 344 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 344 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 310 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 6 5 0 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 5 4 3 4 5 7 -1 -1 2 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 6 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 336 SM_AMIGA_i_7_ 3 -1 6 3 2 6 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 6 0 21 + 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 + 328 RST_DLY_0_ 3 -1 6 2 5 6 -1 -1 4 0 21 + 326 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 4 0 21 + 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 331 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 5 2 5 6 -1 -1 2 1 21 + 327 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 320 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 2 2 5 -1 -1 2 0 21 + 337 CLK_OUT_INTreg 3 -1 5 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 5 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 3 2 3 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 342 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 332 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 5 0 21 - 340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21 - 343 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 338 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 331 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 347 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 316 CLK_000_D_4_ 3 -1 2 1 0 -1 -1 1 0 21 - 315 CLK_000_D_2_ 3 -1 4 1 3 -1 -1 1 0 21 - 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 - 313 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 312 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 3 1 6 -1 -1 1 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 324 SM_AMIGA_1_ 3 -1 2 1 2 -1 -1 3 0 21 + 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 338 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 308 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21 + 321 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21 + 317 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21 + 316 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 13 nEXP_SPACE 1 -1 -1 5 2 3 4 6 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 @@ -8514,36 +1467,153 @@ 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 59 A_1_ 1 -1 -1 2 0 3 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -116 "number of signals after reading design file" + 10 CLK_000 1 -1 -1 1 3 10 -1 +112 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 79 RW_000 5 342 7 3 1 4 6 79 -1 4 0 21 + 68 A_0_ 5 -1 6 2 0 5 68 -1 2 0 21 + 70 RW 5 -1 6 2 5 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 2 0 21 + 40 BERR 5 -1 4 1 0 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 341 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 340 1 0 6 -1 10 0 21 + 82 BGACK_030 5 344 7 0 82 -1 3 0 21 + 34 VMA 5 345 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 343 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 344 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 310 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 309 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 322 SM_AMIGA_6_ 3 -1 6 5 0 2 5 6 7 -1 -1 3 0 21 + 307 inst_RESET_OUT 3 -1 5 4 3 4 5 7 -1 -1 2 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 3 2 3 6 -1 -1 7 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 336 SM_AMIGA_i_7_ 3 -1 6 3 2 6 7 -1 -1 3 1 21 + 325 SM_AMIGA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 294 cpu_est_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 6 0 21 + 302 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 6 0 21 + 335 SM_AMIGA_2_ 3 -1 0 2 0 2 -1 -1 5 0 21 + 328 RST_DLY_0_ 3 -1 6 2 5 6 -1 -1 4 0 21 + 326 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 4 0 21 + 345 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 333 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 323 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 + 320 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 + 332 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 331 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 6 2 5 6 -1 -1 2 0 21 + 329 RST_DLY_1_ 3 -1 5 2 5 6 -1 -1 2 1 21 + 327 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 318 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 2 2 5 -1 -1 2 0 21 + 338 CLK_OUT_INTreg 3 -1 5 2 1 6 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 2 1 5 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 3 2 3 6 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 341 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 340 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 334 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 342 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 324 SM_AMIGA_1_ 3 -1 2 1 2 -1 -1 3 0 21 + 343 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 337 N_242 3 -1 4 1 4 -1 -1 2 0 21 + 308 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21 + 321 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21 + 317 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21 + 316 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 315 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 314 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 313 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 59 A_1_ 1 -1 -1 2 0 3 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +108 "number of signals after reading design file" "sig sig sig pair blk fan PT xor sync" "num name type sig num out pin node cnt PT type" "--- ---- ---- ---- --- --- --- ---- --- --- ----" 81 AS_030 5 -1 7 6 2 3 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 - 79 RW_000 5 341 7 2 4 6 79 -1 4 0 21 - 68 A_0_ 5 346 6 2 5 6 68 -1 3 0 21 - 70 RW 5 345 6 2 5 7 70 -1 2 0 21 + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 336 7 3 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 -1 6 2 1 6 68 -1 2 0 21 + 70 RW 5 -1 6 2 2 7 70 -1 1 0 21 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 338 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 5 69 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 2 0 21 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 @@ -8552,15 +1622,15 @@ 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 340 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 339 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 341 3 0 34 -1 3 0 21 65 E 0 6 0 65 -1 2 0 21 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 97 DS_030 0 0 0 97 -1 1 0 21 91 AVEC 0 0 0 91 -1 1 0 21 80 DSACK1 0 7 0 80 -1 1 0 21 @@ -8570,1085 +1640,58 @@ 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 - 310 CLK_000_D_0_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 309 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 5 6 0 3 4 5 6 7 -1 -1 2 0 21 - 321 SM_AMIGA_6_ 3 -1 2 4 2 5 6 7 -1 -1 3 0 21 - 302 inst_AS_000_DMA 3 -1 1 3 1 3 7 -1 -1 5 0 21 - 296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 323 SM_AMIGA_1_ 3 -1 0 3 0 2 6 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 0 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 293 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 2 2 2 3 -1 -1 7 0 21 - 303 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 5 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 2 2 2 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 324 SM_AMIGA_0_ 3 -1 2 2 2 7 -1 -1 3 0 21 - 322 SM_AMIGA_4_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 319 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 318 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 295 cpu_est_0_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 - 320 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 - 336 CLK_OUT_INTreg 3 -1 0 2 1 6 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_D 3 -1 3 2 0 1 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 0 2 2 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 327 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21 - 325 CYCLE_DMA_0_ 3 -1 1 1 1 -1 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21 - 326 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 2 0 21 - 308 inst_AMIGA_DS 3 -1 7 1 1 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 317 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 - 316 CLK_000_D_2_ 3 -1 6 1 0 -1 -1 1 0 21 - 315 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 - 314 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 313 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 311 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 6 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 2 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 3 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 79 RW_000 5 341 7 3 2 4 6 79 -1 4 0 21 - 70 RW 5 345 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 338 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 - 68 A_0_ 5 346 6 1 2 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 3 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 339 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 348 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 347 1 0 6 -1 10 0 21 - 82 BGACK_030 5 343 7 0 82 -1 3 0 21 - 34 VMA 5 344 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 342 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 343 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 CLK_000_D_0_ 3 -1 6 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 322 SM_AMIGA_6_ 3 -1 5 5 0 2 3 5 7 -1 -1 3 0 21 - 308 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 - 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 - 295 cpu_est_3_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 296 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 - 336 CLK_OUT_INTreg 3 -1 5 3 1 2 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 6 3 3 4 5 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 300 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 CLK_000_D_0_ 3 -1 3 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 308 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 321 SM_AMIGA_6_ 3 -1 5 5 1 2 5 6 7 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 324 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 322 SM_AMIGA_4_ 3 -1 6 3 0 2 6 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 332 CLK_OUT_INTreg 3 -1 0 3 1 2 6 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 3 5 -1 -1 7 0 21 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 6 0 21 - 334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 - 327 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 4 0 21 - 304 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 - 344 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 335 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 1 2 0 1 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 5 2 5 7 -1 -1 2 0 21 - 329 RST_DLY_2_ 3 -1 1 2 1 6 -1 -1 2 0 21 - 328 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 2 1 21 - 326 CYCLE_DMA_1_ 3 -1 2 2 1 2 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 5 2 2 5 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 0 2 0 5 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 4 2 0 5 -1 -1 1 0 21 - 305 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 341 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 1 5 -1 -1 3 0 21 - 345 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 342 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 309 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 0 1 5 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 5 1 4 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 - 307 inst_DTACK_D0 3 -1 3 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 - 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -119 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 70 RW 5 350 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 347 7 0 82 -1 3 0 21 - 34 VMA 5 349 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 346 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 - 322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 - 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 - 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 - 335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 - 309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -115 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 5 2 3 4 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 - 79 RW_000 5 339 7 3 4 5 6 79 -1 4 0 21 - 31 UDS_000 5 -1 3 3 5 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 5 6 7 30 -1 1 0 21 - 68 A_0_ 5 345 6 2 0 2 68 -1 3 0 21 - 70 RW 5 344 6 2 3 7 70 -1 2 0 21 - 78 SIZE_1_ 5 337 7 1 2 78 -1 3 0 21 - 69 SIZE_0_ 5 340 6 1 2 69 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21 - 7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21 - 6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21 - 82 BGACK_030 5 342 7 0 82 -1 3 0 21 - 34 VMA 5 343 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 341 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 322 SM_AMIGA_6_ 3 -1 1 7 0 1 2 3 5 6 7 -1 -1 3 0 21 - 309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 - 311 CLK_000_D_0_ 3 -1 3 6 0 1 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 335 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21 - 324 SM_AMIGA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 2 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 2 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 5 2 0 5 -1 -1 9 0 21 - 302 inst_AS_000_DMA 3 -1 5 2 5 7 -1 -1 7 0 21 - 343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 332 SM_AMIGA_5_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 325 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 - 304 CYCLE_DMA_0_ 3 -1 0 2 0 5 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 331 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 330 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 - 307 CLK_000_D_3_ 3 -1 2 2 1 7 -1 -1 1 0 21 - 306 inst_VPA_D 3 -1 3 2 0 3 -1 -1 1 0 21 - 347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21 - 346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21 - 338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21 - 329 inst_CLK_030_H 3 -1 5 1 5 -1 -1 8 0 21 - 334 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 - 333 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 305 CYCLE_DMA_1_ 3 -1 5 1 5 -1 -1 4 0 21 - 345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 340 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21 - 344 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 2 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 - 308 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 - 59 A_1_ 1 -1 -1 2 2 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 63 CLK_030 1 -1 -1 1 5 63 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 29 DTACK 1 -1 -1 1 0 29 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -119 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 70 RW 5 350 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 347 7 0 82 -1 3 0 21 - 34 VMA 5 349 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 346 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 - 322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 - 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 - 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 - 335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 - 309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 5 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 -125 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 4 5 7 41 -1 1 0 21 - 79 RW_000 5 348 7 3 0 4 6 79 -1 4 0 21 - 70 RW 5 355 6 2 5 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 346 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 356 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 349 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 347 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 351 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 350 1 0 6 -1 10 0 21 - 82 BGACK_030 5 353 7 0 82 -1 3 0 21 - 34 VMA 5 354 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 352 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 353 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 314 CLK_000_D_0_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21 - 313 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 inst_RESET_OUT 3 -1 0 5 0 3 4 6 7 -1 -1 2 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 0 1 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 - 295 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 - 343 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 - 330 SM_AMIGA_0_ 3 -1 6 3 5 6 7 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 - 344 CLK_OUT_INTreg 3 -1 2 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 1 1 21 - 342 SM_AMIGA_2_ 3 -1 2 2 2 6 -1 -1 5 0 21 - 337 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 5 0 21 - 331 CYCLE_DMA_0_ 3 -1 5 2 0 5 -1 -1 4 0 21 - 354 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 339 SM_AMIGA_1_ 3 -1 6 2 2 6 -1 -1 3 0 21 - 329 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 - 328 SM_AMIGA_6_ 3 -1 5 2 5 7 -1 -1 3 0 21 - 326 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21 - 325 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 338 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 - 332 CYCLE_DMA_1_ 3 -1 5 2 0 5 -1 -1 2 0 21 - 327 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 1 2 1 5 -1 -1 1 0 21 - 315 inst_CLK_OUT_PRE_50 3 -1 3 2 2 3 -1 -1 1 0 21 - 307 CLK_000_D_8_ 3 -1 3 2 2 3 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 2 1 5 -1 -1 1 0 21 - 305 inst_CLK_OUT_PRE_D 3 -1 2 2 0 2 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 - 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 347 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 333 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 311 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 - 341 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 348 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 334 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 356 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 349 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 346 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 340 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 3 0 21 - 355 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 345 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 336 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 - 335 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 - 312 inst_AMIGA_DS 3 -1 7 1 0 -1 -1 2 0 21 - 324 CLK_000_D_10_ 3 -1 2 1 2 -1 -1 1 0 21 - 323 CLK_000_D_7_ 3 -1 6 1 3 -1 -1 1 0 21 - 322 CLK_000_D_6_ 3 -1 3 1 6 -1 -1 1 0 21 - 321 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21 - 319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 - 308 CLK_000_D_9_ 3 -1 3 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 63 CLK_030 1 -1 -1 2 0 2 63 -1 - 59 A_1_ 1 -1 -1 2 0 6 59 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 4 10 -1 -127 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 7 0 1 3 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 350 7 3 2 4 6 79 -1 4 0 21 - 70 RW 5 357 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 348 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 358 6 1 0 69 -1 3 0 21 - 68 A_0_ 5 351 6 1 0 68 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 - 82 BGACK_030 5 354 7 0 82 -1 3 0 21 - 34 VMA 5 356 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 352 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 314 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 313 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 310 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 - 345 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 330 SM_AMIGA_6_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 - 346 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 - 305 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 344 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 - 339 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 5 0 21 - 333 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 342 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 341 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 331 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 328 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 340 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 334 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 2 0 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 335 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 - 311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 - 343 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 358 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 356 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 348 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 - 326 CLK_000_D_12_ 3 -1 1 1 1 -1 -1 1 0 21 - 325 CLK_000_D_9_ 3 -1 5 1 2 -1 -1 1 0 21 - 324 CLK_000_D_8_ 3 -1 2 1 5 -1 -1 1 0 21 - 323 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21 - 322 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21 - 321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 - 320 CLK_000_D_4_ 3 -1 5 1 0 -1 -1 1 0 21 - 319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 308 CLK_000_D_11_ 3 -1 1 1 1 -1 -1 1 0 21 - 307 CLK_000_D_10_ 3 -1 2 1 1 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 1 3 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 63 CLK_030 1 -1 -1 2 1 2 63 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -126 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 2 3 4 5 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 - 79 RW_000 5 349 7 3 2 4 6 79 -1 4 0 21 - 70 RW 5 356 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 347 7 1 3 78 -1 3 0 21 - 69 SIZE_0_ 5 357 6 1 3 69 -1 3 0 21 - 68 A_0_ 5 350 6 1 3 68 -1 3 0 21 - 40 BERR 5 -1 4 1 0 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 348 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21 - 82 BGACK_030 5 354 7 0 82 -1 3 0 21 - 34 VMA 5 355 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 352 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 314 CLK_000_D_0_ 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 - 313 CLK_000_D_1_ 3 -1 4 7 0 1 2 3 5 6 7 -1 -1 1 0 21 - 310 inst_RESET_OUT 3 -1 5 6 0 3 4 5 6 7 -1 -1 2 0 21 - 329 SM_AMIGA_6_ 3 -1 1 4 0 1 3 7 -1 -1 3 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 - 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 - 344 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 - 340 SM_AMIGA_1_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 - 345 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 1 1 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 343 SM_AMIGA_2_ 3 -1 0 2 0 6 -1 -1 5 0 21 - 338 inst_DSACK1_INT 3 -1 2 2 2 7 -1 -1 5 0 21 - 332 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 - 355 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 - 331 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21 - 327 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 - 339 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 - 333 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 - 320 CLK_000_D_4_ 3 -1 5 2 0 1 -1 -1 1 0 21 - 315 inst_CLK_OUT_PRE_50 3 -1 0 2 0 1 -1 -1 1 0 21 - 308 CLK_000_D_10_ 3 -1 5 2 2 5 -1 -1 1 0 21 - 307 CLK_000_D_9_ 3 -1 2 2 2 5 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 - 305 inst_CLK_OUT_PRE_D 3 -1 1 2 2 6 -1 -1 1 0 21 + 302 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 6 0 21 + 325 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 341 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 333 SM_AMIGA_i_7_ 3 -1 5 2 5 7 -1 -1 3 1 21 + 329 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 323 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 318 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 + 328 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 327 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 326 CYCLE_DMA_1_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 317 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 4 2 0 2 -1 -1 1 0 21 + 310 inst_CLK_OUT_PRE_50 3 -1 7 2 4 7 -1 -1 1 0 21 304 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 - 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 334 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 - 311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 - 342 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 - 349 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 335 RST_DLY_0_ 3 -1 5 1 5 -1 -1 4 0 21 - 357 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 350 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 347 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 341 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 - 330 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 3 0 21 - 326 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 - 356 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 346 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 337 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 - 336 RST_DLY_1_ 3 -1 5 1 5 -1 -1 2 1 21 - 328 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 - 312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 - 325 CLK_000_D_11_ 3 -1 5 1 2 -1 -1 1 0 21 - 324 CLK_000_D_8_ 3 -1 6 1 2 -1 -1 1 0 21 - 323 CLK_000_D_7_ 3 -1 5 1 6 -1 -1 1 0 21 - 322 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21 - 321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 - 319 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 - 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 - 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 63 CLK_030 1 -1 -1 1 2 63 -1 - 59 A_1_ 1 -1 -1 1 6 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 6 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 6 10 -1 -127 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 7 0 1 3 4 5 6 7 81 -1 1 0 21 - 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 - 79 RW_000 5 350 7 3 2 4 6 79 -1 4 0 21 - 70 RW 5 357 6 2 0 7 70 -1 2 0 21 - 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 - 78 SIZE_1_ 5 348 7 1 0 78 -1 3 0 21 - 69 SIZE_0_ 5 358 6 1 0 69 -1 3 0 21 - 68 A_0_ 5 351 6 1 0 68 -1 3 0 21 - 40 BERR 5 -1 4 1 3 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 355 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 - 82 BGACK_030 5 354 7 0 82 -1 3 0 21 - 34 VMA 5 356 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 352 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 314 CLK_000_D_0_ 3 -1 2 6 0 1 3 5 6 7 -1 -1 1 0 21 - 313 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21 - 310 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 - 300 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 2 3 2 3 7 -1 -1 6 0 21 - 345 SM_AMIGA_i_7_ 3 -1 0 3 0 5 7 -1 -1 3 1 21 - 332 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 - 330 SM_AMIGA_6_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 - 346 CLK_OUT_INTreg 3 -1 6 3 1 2 6 -1 -1 1 0 21 - 305 inst_CLK_OUT_PRE_D 3 -1 6 3 1 2 6 -1 -1 1 0 21 - 301 inst_BGACK_030_INT_D 3 -1 4 3 5 6 7 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 3 4 5 -1 -1 1 0 21 - 303 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 - 344 SM_AMIGA_2_ 3 -1 3 2 1 3 -1 -1 5 0 21 - 339 inst_DSACK1_INT 3 -1 1 2 1 7 -1 -1 5 0 21 - 333 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 4 0 21 - 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_3_ 3 -1 3 2 3 6 -1 -1 4 0 21 - 342 SM_AMIGA_5_ 3 -1 7 2 0 7 -1 -1 3 0 21 - 341 SM_AMIGA_1_ 3 -1 1 2 1 5 -1 -1 3 0 21 - 331 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 3 0 21 - 328 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 - 327 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 - 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 3 0 21 - 340 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 - 334 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 2 0 21 - 329 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 315 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21 - 306 CLK_000_D_3_ 3 -1 1 2 0 5 -1 -1 1 0 21 - 296 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 1 1 21 - 355 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 335 CLK_030_PE_0_ 3 -1 2 1 2 -1 -1 9 0 21 - 311 CLK_030_PE_1_ 3 -1 2 1 2 -1 -1 6 0 21 - 343 SM_AMIGA_3_ 3 -1 3 1 3 -1 -1 5 0 21 - 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 358 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 356 RN_VMA 3 34 3 1 3 34 -1 3 0 21 - 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 348 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 312 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 - 326 CLK_000_D_12_ 3 -1 1 1 1 -1 -1 1 0 21 - 325 CLK_000_D_9_ 3 -1 5 1 2 -1 -1 1 0 21 - 324 CLK_000_D_8_ 3 -1 2 1 5 -1 -1 1 0 21 - 323 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21 - 322 CLK_000_D_6_ 3 -1 6 1 1 -1 -1 1 0 21 - 321 CLK_000_D_5_ 3 -1 0 1 6 -1 -1 1 0 21 - 320 CLK_000_D_4_ 3 -1 5 1 0 -1 -1 1 0 21 - 319 CLK_000_D_2_ 3 -1 7 1 1 -1 -1 1 0 21 - 318 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 - 317 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 316 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 - 309 inst_DTACK_D0 3 -1 2 1 3 -1 -1 1 0 21 - 308 CLK_000_D_11_ 3 -1 1 1 1 -1 -1 1 0 21 - 307 CLK_000_D_10_ 3 -1 2 1 1 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 3 1 3 -1 -1 1 0 21 + 340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 331 SM_AMIGA_2_ 3 -1 0 1 0 -1 -1 5 0 21 + 330 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_60 3 -1 4 1 4 -1 -1 2 0 21 + 307 inst_AMIGA_DS 3 -1 7 1 2 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 320 inst_BGACK_030_INT_D 3 -1 4 1 5 -1 -1 1 0 21 + 316 CLK_000_D_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 315 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 + 314 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 313 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 312 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 5 1 0 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 5 1 5 -1 -1 1 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 1 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 1 3 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 13 nEXP_SPACE 1 -1 -1 4 3 4 5 7 13 -1 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 @@ -9656,142 +1699,16 @@ 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 - 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 - 63 CLK_030 1 -1 -1 2 1 2 63 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 59 A_1_ 1 -1 -1 2 0 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 3 35 -1 - 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 2 10 -1 -119 "number of signals after reading design file" - -"sig sig sig pair blk fan PT xor sync" -"num name type sig num out pin node cnt PT type" -"--- ---- ---- ---- --- --- --- ---- --- --- ----" - - 81 AS_030 5 -1 7 6 0 1 2 3 4 7 81 -1 1 0 21 - 79 RW_000 5 345 7 3 0 4 6 79 -1 4 0 21 - 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 - 31 UDS_000 5 -1 3 3 2 6 7 31 -1 1 0 21 - 30 LDS_000 5 -1 3 3 2 6 7 30 -1 1 0 21 - 70 RW 5 350 6 2 2 7 70 -1 2 0 21 - 78 SIZE_1_ 5 341 7 1 5 78 -1 3 0 21 - 69 SIZE_0_ 5 348 6 1 5 69 -1 3 0 21 - 68 A_0_ 5 340 6 1 5 68 -1 3 0 21 - 40 BERR 5 -1 4 1 2 40 -1 1 0 21 - 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 - 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 - 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 - 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 - 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 - 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 - 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 - 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 - 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 - 8 IPL_030_2_ 5 344 1 0 8 -1 10 0 21 - 7 IPL_030_0_ 5 343 1 0 7 -1 10 0 21 - 6 IPL_030_1_ 5 342 1 0 6 -1 10 0 21 - 82 BGACK_030 5 347 7 0 82 -1 3 0 21 - 34 VMA 5 349 3 0 34 -1 3 0 21 - 65 E 0 6 0 65 -1 2 0 21 - 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 - 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 - 28 BG_000 5 346 3 0 28 -1 2 0 21 - 97 DS_030 0 0 0 97 -1 1 0 21 - 91 AVEC 0 0 0 91 -1 1 0 21 - 80 DSACK1 0 7 0 80 -1 1 0 21 - 77 FPU_CS 0 7 0 77 -1 1 0 21 - 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 - 46 CIIN 0 4 0 46 -1 1 0 21 - 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 - 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 - 9 CLK_EXP 0 1 0 9 -1 1 0 21 - 347 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 - 311 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 - 310 CLK_000_D_1_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 - 307 inst_RESET_OUT 3 -1 6 5 0 3 4 6 7 -1 -1 2 0 21 - 322 SM_AMIGA_6_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 - 301 inst_BGACK_030_INT_D 3 -1 7 4 1 5 6 7 -1 -1 1 0 21 - 300 inst_AS_030_000_SYNC 3 -1 1 3 1 3 5 -1 -1 7 0 21 - 302 inst_AS_000_DMA 3 -1 0 3 0 3 7 -1 -1 6 0 21 - 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 - 337 SM_AMIGA_i_7_ 3 -1 5 3 1 5 7 -1 -1 3 1 21 - 325 SM_AMIGA_0_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 - 296 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 - 338 CLK_OUT_INTreg 3 -1 3 3 0 1 6 -1 -1 1 0 21 - 299 inst_AS_030_D0 3 -1 7 3 1 3 4 -1 -1 1 0 21 - 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 - 336 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 5 0 21 - 349 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 - 334 SM_AMIGA_5_ 3 -1 6 2 0 6 -1 -1 3 0 21 - 324 SM_AMIGA_1_ 3 -1 5 2 0 5 -1 -1 3 0 21 - 323 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 - 320 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21 - 319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 - 333 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 - 332 inst_DSACK1_INT 3 -1 0 2 0 7 -1 -1 2 0 21 - 321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 - 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 - 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 - 313 inst_CLK_OUT_PRE_D 3 -1 4 2 0 3 -1 -1 1 0 21 - 312 inst_CLK_OUT_PRE_50 3 -1 6 2 4 6 -1 -1 1 0 21 - 305 CLK_000_D_3_ 3 -1 5 2 2 5 -1 -1 1 0 21 - 304 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 - 344 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 - 343 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 - 342 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 - 328 CLK_030_PE_0_ 3 -1 0 1 0 -1 -1 9 0 21 - 303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 - 308 CLK_030_PE_1_ 3 -1 0 1 0 -1 -1 6 0 21 - 335 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 - 345 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 - 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21 - 326 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 4 0 21 - 348 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21 - 341 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21 - 340 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 - 350 RN_RW 3 70 6 1 6 70 -1 2 0 21 - 346 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 - 339 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 - 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 - 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21 - 327 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 2 0 21 - 309 inst_AMIGA_DS 3 -1 2 1 0 -1 -1 2 0 21 - 318 CLK_000_D_4_ 3 -1 2 1 5 -1 -1 1 0 21 - 317 CLK_000_D_2_ 3 -1 7 1 5 -1 -1 1 0 21 - 316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 - 315 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 - 314 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 - 306 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 - 60 CLK_OSZI 9 -1 0 60 -1 - 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 - 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 - 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 - 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 - 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 - 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 - 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 - 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 - 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 - 27 BGACK_000 1 -1 -1 2 4 7 27 -1 - 2 RESET 1 -1 -1 2 1 2 2 -1 - 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 - 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 - 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 - 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 - 67 IPL_2_ 1 -1 -1 1 1 67 -1 - 66 IPL_0_ 1 -1 -1 1 1 66 -1 - 63 CLK_030 1 -1 -1 1 0 63 -1 - 59 A_1_ 1 -1 -1 1 5 59 -1 - 55 IPL_1_ 1 -1 -1 1 1 55 -1 - 35 VPA 1 -1 -1 1 5 35 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 10 CLK_000 1 -1 -1 1 3 10 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 1d59f16..0ace62c 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,15 +8,22 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Thu Dec 29 16:02:00 2016 +; DATE Sat Dec 30 00:43:46 2017 +Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157 +Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155 +Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 +Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 -Pin 56 IPL_1_ -Pin 67 IPL_0_ +Pin 84 A_DECODE_22_ +Pin 94 A_DECODE_21_ Pin 85 A_DECODE_23_ -Pin 57 FC_0_ -Pin 60 A_1_ +Pin 93 A_DECODE_20_ +Pin 97 A_DECODE_19_ +Pin 95 A_DECODE_18_ +Pin 59 A_DECODE_17_ +Pin 96 A_DECODE_16_ Pin 68 IPL_2_ Pin 58 FC_1_ Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 @@ -28,121 +35,106 @@ Pin 14 nEXP_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 Pin 21 BG_030 Pin 28 BGACK_000 -Pin 64 CLK_030 Pin 11 CLK_000 +Pin 56 IPL_1_ Pin 61 CLK_OSZI +Pin 67 IPL_0_ Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247 +Pin 57 FC_0_ Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127 +Pin 60 A_1_ Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 Pin 91 FPU_SENSE Pin 81 DSACK1 Comb ; S6=1 S9=1 Pair 283 -Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173 +Pin 30 DTACK Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 66 E Comb ; S6=1 S9=1 Pair 251 -Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 Pin 36 VPA +Pin 86 RST +Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 +Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 +Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151 +Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179 +Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 +Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137 Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 -Pin 86 RST -Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157 -Pin 3 RESET -Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155 -Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 -Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 187 -Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 -Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 -Pin 84 A_DECODE_22_ -Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151 -Pin 94 A_DECODE_21_ -Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 181 -Pin 93 A_DECODE_20_ -Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 -Pin 97 A_DECODE_19_ -Pin 95 A_DECODE_18_ -Pin 59 A_DECODE_17_ -Pin 96 A_DECODE_16_ -Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257 Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 287 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 -Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133 Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 -Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 -Pin 35 VMA Reg ; S6=1 S9=1 Pair 179 +Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133 +Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 +Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 +Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1 +Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1 +Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1 +Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1 Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1 Node 281 RN_AS_030 Comb ; S6=1 S9=1 Node 203 RN_AS_000 Comb ; S6=1 S9=1 Node 185 RN_UDS_000 Comb ; S6=1 S9=1 Node 191 RN_LDS_000 Comb ; S6=1 S9=1 Node 197 RN_BERR Comb ; S6=1 S9=1 -Node 173 RN_DTACK Comb ; S6=1 S9=1 Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1 Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1 Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1 -Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1 -Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1 -Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1 -Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1 -Node 257 RN_A_0_ Reg ; S6=1 S9=1 Node 287 RN_SIZE_1_ Reg ; S6=1 S9=1 -Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 269 RN_RW_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 -Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 -Node 179 RN_VMA Reg ; S6=1 S9=1 +Node 257 RN_A_0_ Reg ; S6=1 S9=1 +Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 173 RN_VMA Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 -Node 182 cpu_est_1_ Reg ; S6=1 S9=1 -Node 194 cpu_est_2_ Reg ; S6=1 S9=1 -Node 176 cpu_est_3_ Reg ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 Node 259 cpu_est_0_ Reg ; S6=1 S9=1 -Node 235 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 229 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 -Node 272 inst_AS_030_D0 Reg ; S6=1 S9=1 -Node 145 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 113 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 224 inst_VPA_D Reg ; S6=1 S9=1 +Node 193 cpu_est_1_ Reg ; S6=1 S9=1 +Node 176 cpu_est_2_ Reg ; S6=1 S9=1 +Node 113 cpu_est_3_ Reg ; S6=1 S9=1 +Node 116 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 164 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 209 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 223 inst_AS_030_D1 Reg ; S6=1 S9=1 +Node 227 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 169 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 163 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 254 inst_VPA_D Reg ; S6=1 S9=1 Node 241 CLK_000_D_3_ Reg ; S6=1 S9=1 -Node 146 inst_DTACK_D0 Reg ; S6=1 S9=1 -Node 253 inst_RESET_OUT Reg ; S6=1 S9=1 -Node 104 CLK_030_PE_1_ Reg ; S6=1 S9=1 -Node 164 inst_AMIGA_DS Reg ; S6=1 S9=1 +Node 235 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 272 inst_AMIGA_DS Reg ; S6=1 S9=1 Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1 -Node 193 CLK_000_D_0_ Reg ; S6=1 S9=1 -Node 248 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 140 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 134 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 128 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 187 CLK_000_D_0_ Reg ; S6=1 S9=1 +Node 289 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 205 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 110 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 182 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 104 IPL_D0_2_ Reg ; S6=1 S9=1 Node 278 CLK_000_D_2_ Reg ; S6=1 S9=1 -Node 170 CLK_000_D_4_ Reg ; S6=1 S9=1 -Node 239 inst_LDS_000_INT Reg ; S6=1 S9=1 -Node 169 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 223 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 229 CLK_000_D_4_ Reg ; S6=1 S9=1 +Node 134 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 152 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 265 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 217 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 Node 221 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 103 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 233 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 253 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 109 SM_AMIGA_1_ Reg ; S6=1 S9=1 Node 119 SM_AMIGA_0_ Reg ; S6=1 S9=1 -Node 110 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 116 CYCLE_DMA_1_ Reg ; S6=1 S9=1 -Node 115 CLK_030_PE_0_ Reg ; S6=1 S9=1 -Node 254 RST_DLY_0_ Reg ; S6=1 S9=1 -Node 266 RST_DLY_1_ Reg ; S6=1 S9=1 -Node 260 RST_DLY_2_ Reg ; S6=1 S9=1 -Node 109 inst_DSACK1_INT Reg ; S6=1 S9=1 -Node 152 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 265 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 158 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 163 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 -Node 188 CLK_OUT_INTreg Reg ; S6=1 S9=1 -Node 205 CIIN_0 Comb ; S6=1 S9=1 +Node 145 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 128 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 248 inst_DSACK1_INT Reg ; S6=1 S9=1 +Node 158 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 239 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 121 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 115 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 103 CLK_OUT_INTreg Reg ; S6=1 S9=1 +Node 233 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 211 N_60 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 1bcad98..6fc95fa 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Thu Dec 29 16:02:00 2016 -End : Thu Dec 29 16:02:00 2016 $$$ Elapsed time: 00:00:00 +Start: Sat Dec 30 00:43:46 2017 +End : Sat Dec 30 00:43:46 2017 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,33 +21,33 @@ Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 24 => 72% - 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 26 => 78% - 2 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 26 => 78% - 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 24 => 72% - 4 | 16 | 6 | 6 => 100% | 8 | 4 => 50% | 33 | 30 => 90% - 5 | 16 | 9 | 9 => 100% | 8 | 5 => 62% | 33 | 24 => 72% - 6 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 24 => 72% - 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 27 => 81% + 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 23 => 69% + 1 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 20 => 60% + 2 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 21 => 63% + 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 22 => 66% + 4 | 16 | 8 | 8 => 100% | 8 | 4 => 50% | 33 | 30 => 90% + 5 | 16 | 8 | 8 => 100% | 8 | 5 => 62% | 33 | 24 => 72% + 6 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 23 => 69% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 25 => 75% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 25.63 => 77% + | Avg number of array inputs in used blocks : 23.50 => 71% -* Input/Clock Signal count: 24 -> placed: 24 = 100% +* Input/Clock Signal count: 23 -> placed: 23 = 100% Resources Available Used ----------------------------------------------------------------- Input Pins : 2 2 => 100% - I/O Pins : 64 55 => 85% + I/O Pins : 64 54 => 84% Clock Only Pins : 0 0 => 0% - Clock/Input Pins : 4 4 => 100% + Clock/Input Pins : 4 3 => 75% Logic Blocks : 8 8 => 100% - Macrocells : 128 84 => 65% - PT Clusters : 128 56 => 43% - - Single PT Clusters : 128 38 => 29% + Macrocells : 128 78 => 60% + PT Clusters : 128 44 => 34% + - Single PT Clusters : 128 40 => 31% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 119] Route [ 0] +* Attempts: Place [ 108] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -69,21 +69,20 @@ ___|__|__|____|____________________________________________________________ 10| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 13| 4| IO| 42|=> 0...|4..7| AS_000 - 14| 7| IO| 82|=> 0123|4..7| AS_030 + 13| 4| IO| 42|=> 012.|4..7| AS_000 + 14| 7| IO| 82|=> ..23|4567| AS_030 15| 0|OUT| 92|=> ....|....| AVEC - 16| 6| IO| 69|=> ....|.5..| A_0_ - |=> Paired w/: RN_A_0_ - 17| 5|INP| 60|=> ....|.5..| A_1_ - 18| 0|INP| 96|=> .1..|4..7| A_DECODE_16_ - 19| 5|INP| 59|=> .1..|4..7| A_DECODE_17_ - 20| 0|INP| 95|=> .1..|4..7| A_DECODE_18_ - 21| 0|INP| 97|=> .1..|4..7| A_DECODE_19_ + 16| 6| IO| 69|=> .1..|..6.| A_0_ + 17| 5|INP| 60|=> 0.2.|....| A_1_ + 18| 0|INP| 96|=> ....|45.7| A_DECODE_16_ + 19| 5|INP| 59|=> ....|45.7| A_DECODE_17_ + 20| 0|INP| 95|=> ....|45.7| A_DECODE_18_ + 21| 0|INP| 97|=> ....|45.7| A_DECODE_19_ 22| 0|INP| 93|=> ....|4...| A_DECODE_20_ 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ - 26| 4| IO| 41|=> ..2.|....| BERR + 26| 4| IO| 41|=> 0...|....| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 @@ -91,113 +90,95 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_BG_000 30| 2|INP| 21|=> ...3|....| BG_030 31| 4|OUT| 47|=> ....|....| CIIN - 32| 4|NOD| . |=> ....|4...| CIIN_0 - 33| +|INP| 11|=> ...3|....| CLK_000 - 34| 3|NOD| . |=> 0.23|.567| CLK_000_D_0_ - 35| 7|NOD| . |=> 0.23|.567| CLK_000_D_1_ - 36| 7|NOD| . |=> ....|.5..| CLK_000_D_2_ - 37| 5|NOD| . |=> ..2.|.5..| CLK_000_D_3_ - 38| 2|NOD| . |=> ....|.5..| CLK_000_D_4_ - 39| +|INP| 64|=> 0...|....| CLK_030 - 40| 0|NOD| . |=> 0...|....| CLK_030_PE_0_ - 41| 0|NOD| . |=> 0...|....| CLK_030_PE_1_ - 42| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 43| 1|OUT| 10|=> ....|....| CLK_EXP - 44| +|Cin| 61|=> ....|....| CLK_OSZI - 45| 3|NOD| . |=> 01..|..6.| CLK_OUT_INTreg - 46| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ - 47| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ - 48| 7|OUT| 81|=> ....|....| DSACK1 - 49| 0|OUT| 98|=> ....|....| DS_030 - 50| 3| IO| 30|=> .1..|....| DTACK - 51| 6|OUT| 66|=> ....|....| E - 52| 5|INP| 57|=> .1..|4..7| FC_0_ - 53| 5|INP| 58|=> .1..|4..7| FC_1_ - 54| 7|OUT| 78|=> ....|....| FPU_CS - 55| 0|INP| 91|=> ....|4..7| FPU_SENSE - 56| 1| IO| 8|=> ....|....| IPL_030_0_ + 32| +|INP| 11|=> ...3|....| CLK_000 + 33| 3|NOD| . |=> 0123|.567| CLK_000_D_0_ + 34| 7|NOD| . |=> 0123|.567| CLK_000_D_1_ + 35| 7|NOD| . |=> ....|.5..| CLK_000_D_2_ + 36| 5|NOD| . |=> ....|.5..| CLK_000_D_3_ + 37| 5|NOD| . |=> ....|.5..| CLK_000_D_4_ + 38| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 39| 1|OUT| 10|=> ....|....| CLK_EXP + 40| +|Cin| 61|=> ....|....| CLK_OSZI + 41| 0|NOD| . |=> .12.|..6.| CLK_OUT_INTreg + 42| 1|NOD| . |=> .12.|....| CYCLE_DMA_0_ + 43| 1|NOD| . |=> .12.|....| CYCLE_DMA_1_ + 44| 7|OUT| 81|=> ....|....| DSACK1 + 45| 0|OUT| 98|=> ....|....| DS_030 + 46| 3|INP| 30|=> ....|.5..| DTACK + 47| 6|OUT| 66|=> ....|....| E + 48| 5|INP| 57|=> ....|45.7| FC_0_ + 49| 5|INP| 58|=> ....|45.7| FC_1_ + 50| 7|OUT| 78|=> ....|....| FPU_CS + 51| 0|INP| 91|=> ....|4..7| FPU_SENSE + 52| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 57| 1| IO| 7|=> ....|....| IPL_030_1_ + 53| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 58| 1| IO| 9|=> ....|....| IPL_030_2_ + 54| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 59| 6|INP| 67|=> .1..|....| IPL_0_ - 60| 5|INP| 56|=> .1..|....| IPL_1_ - 61| 6|INP| 68|=> .1..|....| IPL_2_ - 62| 1|NOD| . |=> .1..|....| IPL_D0_0_ - 63| 1|NOD| . |=> .1..|....| IPL_D0_1_ - 64| 1|NOD| . |=> .1..|....| IPL_D0_2_ - 65| 3| IO| 31|=> ..2.|..67| LDS_000 - 66| 1|INP| 3|=> .12.|....| RESET - 67| 6|NOD| . |=> ....|..6.| RN_A_0_ - |=> Paired w/: A_0_ - 68| 7|NOD| . |=> 0123|4567| RN_BGACK_030 + 55| 6|INP| 67|=> 01..|....| IPL_0_ + 56| 5|INP| 56|=> .1.3|....| IPL_1_ + 57| 6|INP| 68|=> 01..|....| IPL_2_ + 58| 0|NOD| . |=> .1..|....| IPL_D0_0_ + 59| 3|NOD| . |=> .1..|....| IPL_D0_1_ + 60| 0|NOD| . |=> .1..|....| IPL_D0_2_ + 61| 3| IO| 31|=> ....|..67| LDS_000 + 62| 4|NOD| . |=> ....|4...| N_60 + 63| 7|NOD| . |=> 0123|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 - 69| 3|NOD| . |=> ...3|....| RN_BG_000 + 64| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 70| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 65| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 71| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 66| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 72| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 67| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 73| 6|NOD| . |=> ....|..6.| RN_RW - |=> Paired w/: RW - 74| 7|NOD| . |=> ....|...7| RN_RW_000 + 68| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 75| 6|NOD| . |=> ....|..6.| RN_SIZE_0_ - |=> Paired w/: SIZE_0_ - 76| 7|NOD| . |=> ....|...7| RN_SIZE_1_ - |=> Paired w/: SIZE_1_ - 77| 3|NOD| . |=> ..23|....| RN_VMA + 69| 3|NOD| . |=> 0..3|....| RN_VMA |=> Paired w/: VMA - 78| +|INP| 86|=> 0123|.567| RST - 79| 6|NOD| . |=> ....|..6.| RST_DLY_0_ - 80| 6|NOD| . |=> ....|..6.| RST_DLY_1_ - 81| 6|NOD| . |=> ....|..6.| RST_DLY_2_ - 82| 6| IO| 71|=> ..2.|...7| RW - |=> Paired w/: RN_RW - 83| 7| IO| 80|=> 0...|4.6.| RW_000 + 70| +|INP| 86|=> 0123|4567| RST + 71| 6| IO| 71|=> ..2.|...7| RW + 72| 7| IO| 80|=> ..2.|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 84| 6| IO| 70|=> ....|.5..| SIZE_0_ - |=> Paired w/: RN_SIZE_0_ - 85| 7| IO| 79|=> ....|.5..| SIZE_1_ - |=> Paired w/: RN_SIZE_1_ - 86| 0|NOD| . |=> 0...|.5.7| SM_AMIGA_0_ - 87| 5|NOD| . |=> 0...|.5..| SM_AMIGA_1_ - 88| 2|NOD| . |=> ..2.|.5..| SM_AMIGA_2_ - 89| 2|NOD| . |=> ..2.|....| SM_AMIGA_3_ - 90| 0|NOD| . |=> 0.2.|....| SM_AMIGA_4_ - 91| 6|NOD| . |=> 0...|..6.| SM_AMIGA_5_ - 92| 5|NOD| . |=> ..2.|.567| SM_AMIGA_6_ - 93| 5|NOD| . |=> .1..|.5.7| SM_AMIGA_i_7_ - 94| 3| IO| 32|=> ..2.|..67| UDS_000 - 95| 3| IO| 35|=> ....|....| VMA + 73| 6| IO| 70|=> ....|..6.| SIZE_0_ + 74| 7| IO| 79|=> ....|..6.| SIZE_1_ + 75| 0|NOD| . |=> 0...|.5.7| SM_AMIGA_0_ + 76| 0|NOD| . |=> 0...|..6.| SM_AMIGA_1_ + 77| 0|NOD| . |=> 0...|....| SM_AMIGA_2_ + 78| 0|NOD| . |=> 0...|....| SM_AMIGA_3_ + 79| 6|NOD| . |=> 0.2.|..6.| SM_AMIGA_4_ + 80| 5|NOD| . |=> ....|.56.| SM_AMIGA_5_ + 81| 5|NOD| . |=> .12.|.567| SM_AMIGA_6_ + 82| 5|NOD| . |=> ....|.5.7| SM_AMIGA_i_7_ + 83| 3| IO| 32|=> ....|..67| UDS_000 + 84| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 96| +|INP| 36|=> ....|.5..| VPA - 97| 6|NOD| . |=> ..23|..6.| cpu_est_0_ - 98| 3|NOD| . |=> ..23|..6.| cpu_est_1_ - 99| 3|NOD| . |=> ..23|..6.| cpu_est_2_ - 100| 3|NOD| . |=> ..23|..6.| cpu_est_3_ - 101| 5|NOD| . |=> ...3|.5..| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 102| 5|NOD| . |=> ..2.|.5..| inst_AMIGA_BUS_ENABLE_DMA_LOW - 103| 2|NOD| . |=> 0...|....| inst_AMIGA_DS - 104| 0|NOD| . |=> 0..3|...7| inst_AS_000_DMA - 105| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT - 106| 1|NOD| . |=> .1.3|.5..| inst_AS_030_000_SYNC - 107| 7|NOD| . |=> .1.3|4...| inst_AS_030_D0 - 108| 7|NOD| . |=> .1..|.567| inst_BGACK_030_INT_D - 109| 6|NOD| . |=> ....|4.6.| inst_CLK_OUT_PRE_50 - 110| 4|NOD| . |=> 0..3|....| inst_CLK_OUT_PRE_D - 111| 0|NOD| . |=> 0...|...7| inst_DSACK1_INT - 112| 0|NOD| . |=> 0...|....| inst_DS_000_DMA - 113| 2|NOD| . |=> ..23|....| inst_DS_000_ENABLE - 114| 1|NOD| . |=> ..2.|....| inst_DTACK_D0 - 115| 5|NOD| . |=> ...3|.5..| inst_LDS_000_INT - 116| 6|NOD| . |=> 0..3|4.67| inst_RESET_OUT - 117| 5|NOD| . |=> ...3|.5..| inst_UDS_000_INT - 118| 5|NOD| . |=> ..23|....| inst_VPA_D - 119| +|INP| 14|=> 0123|4567| nEXP_SPACE + 85| +|INP| 36|=> ....|..6.| VPA + 86| 6|NOD| . |=> 0..3|..6.| cpu_est_0_ + 87| 3|NOD| . |=> 0..3|..6.| cpu_est_1_ + 88| 3|NOD| . |=> 0..3|..6.| cpu_est_2_ + 89| 0|NOD| . |=> 0..3|..6.| cpu_est_3_ + 90| 0|NOD| . |=> ...3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 91| 2|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 92| 7|NOD| . |=> ..2.|....| inst_AMIGA_DS + 93| 2|NOD| . |=> ..2.|...7| inst_AS_000_DMA + 94| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT + 95| 5|NOD| . |=> ...3|.5..| inst_AS_030_000_SYNC + 96| 4|NOD| . |=> ...3|45..| inst_AS_030_D0 + 97| 5|NOD| . |=> ....|.5..| inst_AS_030_D1 + 98| 4|NOD| . |=> ....|.5..| inst_BGACK_030_INT_D + 99| 7|NOD| . |=> ....|4..7| inst_CLK_OUT_PRE_50 + 100| 4|NOD| . |=> 0.2.|....| inst_CLK_OUT_PRE_D + 101| 6|NOD| . |=> ....|..67| inst_DSACK1_INT + 102| 2|NOD| . |=> 0.2.|....| inst_DS_000_DMA + 103| 2|NOD| . |=> ..23|....| inst_DS_000_ENABLE + 104| 5|NOD| . |=> 0...|....| inst_DTACK_D0 + 105| 6|NOD| . |=> ...3|..6.| inst_LDS_000_INT + 106| 1|NOD| . |=> .1.3|....| inst_UDS_000_INT + 107| 6|NOD| . |=> 0..3|....| inst_VPA_D + 108| +|INP| 14|=> ...3|45.7| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -208,7 +189,7 @@ ___|__|__|____|____________________________________________________________ ____|_____|_________|______________________________________________________ 1 | GND | | | (pwr/test) 2 | JTAG | | | (pwr/test) - 3 | I_O | 1_07|*| RESET + 3 | I_O | 1_07| | - 4 | I_O | 1_06|*| AHIGH_31_ 5 | I_O | 1_05|*| AHIGH_30_ 6 | I_O | 1_04|*| AHIGH_29_ @@ -269,7 +250,7 @@ ____|_____|_________|______________________________________________________ 61 | CkIn | |*| CLK_OSZI 62 | Vcc | | | (pwr/test) 63 | GND | | | (pwr/test) - 64 | CkIn | |*| CLK_030 + 64 | CkIn | | | - 65 | I_O | 6_00|*| CLK_DIV_OUT 66 | I_O | 6_01|*| E 67 | I_O | 6_02|*| IPL_0_ @@ -318,20 +299,20 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free - 2| CLK_030_PE_1_|NOD| | S | 6 | 4 to [ 2]| 1 XOR to [ 2] as logic PT + 1|CLK_OUT_INTreg|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free - 4| AVEC|OUT| | S | 1 | 4 to [ 2]| 1 XOR to [ 4] for 1 PT sig - 5|inst_DSACK1_INT|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6| CYCLE_DMA_0_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free - 7| | ? | | S | | 4 to [ 8]| 1 XOR free - 8|inst_AS_000_DMA|NOD| | S | 6 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| CLK_030_PE_0_|NOD| | S | 9 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| CYCLE_DMA_1_|NOD| | S | 2 | 4 to [10]| 1 XOR free -11| | ? | | S | | 4 to [ 9]| 1 XOR free + 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| cpu_est_3_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free + 9| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free 12| SM_AMIGA_0_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13|inst_DS_000_DMA|NOD| | S | 9 | 4 to [13]| 1 XOR to [13] as logic PT -14| | ? | | S | | 4 to [13]| 1 XOR free +13| SM_AMIGA_3_|NOD| | S | 5 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -344,22 +325,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DS_030|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) - 2| CLK_030_PE_1_|NOD| | S | 6 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 6] logic PT(s) - 5|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) - 6| CYCLE_DMA_0_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 7| | ? | | S | |=> can support up to [ 1] logic PT(s) - 8|inst_AS_000_DMA|NOD| | S | 6 |=> can support up to [ 10] logic PT(s) - 9| CLK_030_PE_0_|NOD| | S | 9 |=> can support up to [ 10] logic PT(s) -10| CYCLE_DMA_1_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) -11| | ? | | S | |=> can support up to [ 1] logic PT(s) -12| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) -13|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 6] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 0| DS_030|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 1|CLK_OUT_INTreg|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 2| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 6| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) + 9| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 14] logic PT(s) +10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Node-Pin Assignments @@ -370,19 +351,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1| SM_AMIGA_4_|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2| CLK_030_PE_1_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1|CLK_OUT_INTreg|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2| IPL_D0_2_|NOD| | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5|inst_DSACK1_INT|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6| CYCLE_DMA_0_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6| IPL_D0_0_|NOD| | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8|inst_AS_000_DMA|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9| CLK_030_PE_0_|NOD| | => | 1 2 3 4 | 92 93 94 95 -10| CYCLE_DMA_1_|NOD| | => | 2 3 4 5 | 93 94 95 96 + 8| cpu_est_3_|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 92 93 94 95 +10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 12| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 -13|inst_DS_000_DMA|NOD| | => | 3 4 5 6 | 94 95 96 97 +13| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- @@ -434,37 +415,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] - [MCell 1 |103|NOD SM_AMIGA_4_| |*] + [MCell 1 |103|NOD CLK_OUT_INTreg| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD CLK_030_PE_1_| |*] + [MCell 2 |104|NOD IPL_D0_2_| |*] [MCell 3 |106| -| | ] 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD inst_DSACK1_INT| |*] + [MCell 5 |109|NOD SM_AMIGA_1_| |*] 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD CYCLE_DMA_0_| |*] + [MCell 6 |110|NOD IPL_D0_0_| |*] [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113|NOD inst_AS_000_DMA| |*] - [MCell 9 |115|NOD CLK_030_PE_0_| |*] + [MCell 8 |113|NOD cpu_est_3_| |*] + [MCell 9 |115|NOD SM_AMIGA_2_| |*] 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116|NOD CYCLE_DMA_1_| |*] + [MCell 10 |116|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] [MCell 12 |119|NOD SM_AMIGA_0_| |*] - [MCell 13 |121|NOD inst_DS_000_DMA| |*] + [MCell 13 |121|NOD SM_AMIGA_3_| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] @@ -477,39 +458,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 13 ( 193)| CLK_000_D_0_ -Mux02| Mcel 0 9 ( 115)| CLK_030_PE_0_ -Mux03| Mcel 0 8 ( 113)| inst_AS_000_DMA -Mux04| Input Pin ( 64)| CLK_030 -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| ... | ... -Mux08| Mcel 2 10 ( 164)| inst_AMIGA_DS -Mux09| Mcel 0 1 ( 103)| SM_AMIGA_4_ -Mux10| Mcel 0 6 ( 110)| CYCLE_DMA_0_ +Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux01| Mcel 5 9 ( 235)| inst_DTACK_D0 +Mux02| IOPin 4 1 ( 42)| AS_000 +Mux03| IOPin 5 0 ( 60)| A_1_ +Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux05| Mcel 6 6 ( 254)| inst_VPA_D +Mux06| ... | ... +Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux08| ... | ... +Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux10| Mcel 6 9 ( 259)| cpu_est_0_ Mux11| ... | ... -Mux12| Mcel 6 13 ( 265)| SM_AMIGA_5_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 0 10 ( 116)| CYCLE_DMA_1_ -Mux15| Mcel 0 12 ( 119)| SM_AMIGA_0_ -Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D -Mux17| ... | ... -Mux18| Mcel 0 5 ( 109)| inst_DSACK1_INT -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 5 8 ( 233)| SM_AMIGA_1_ -Mux21| ... | ... -Mux22| Mcel 0 2 ( 104)| CLK_030_PE_1_ -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux12| ... | ... +Mux13| Mcel 2 9 ( 163)| inst_DS_000_DMA +Mux14| Mcel 4 5 ( 205)| inst_CLK_OUT_PRE_D +Mux15| ... | ... +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 0 5 ( 109)| SM_AMIGA_1_ +Mux19| Mcel 0 9 ( 115)| SM_AMIGA_2_ +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_4_ +Mux23| ... | ... Mux24| ... | ... -Mux25| Mcel 0 13 ( 121)| inst_DS_000_DMA -Mux26| IOPin 4 1 ( 42)| AS_000 -Mux27| ... | ... +Mux25| Mcel 0 13 ( 121)| SM_AMIGA_3_ +Mux26| Mcel 3 0 ( 173)| RN_VMA +Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... -Mux29| ... | ... -Mux30| Mcel 3 10 ( 188)| CLK_OUT_INTreg +Mux29| Mcel 3 13 ( 193)| cpu_est_1_ +Mux30| Mcel 0 8 ( 113)| cpu_est_3_ Mux31| ... | ... -Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Macrocell (MCell) Cluster Assignments @@ -523,19 +504,19 @@ Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_30_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2| CYCLE_DMA_1_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT 5| IPL_030_0_| IO| | S |10 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| IPL_D0_1_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 6] for 1 PT sig - 7| | ? | | S | | 4 to [ 5]| 1 XOR free + 6|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 7| | ? | | S | | 4 to [ 5]| 1 XOR to [ 5] as logic PT 8| AHIGH_29_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| IPL_030_1_| IO| | S |10 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| IPL_D0_0_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig -11| | ? | | S | | 4 to [ 9]| 1 XOR free +10| | ? | | S | | 4 to [ 9]| 1 XOR to [ 9] as logic PT +11| | ? | | S | | 4 free | 1 XOR free 12| AHIGH_31_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [13]| 1 XOR to [13] as logic PT -14| inst_DTACK_D0|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig +13| CYCLE_DMA_0_|NOD| | S | 4 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -548,22 +529,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) - 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 2| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 3| | ? | | S | |=> can support up to [ 4] logic PT(s) + 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 2| CYCLE_DMA_1_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 3| | ? | | S | |=> [ 0] PT capacity 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 10] logic PT(s) - 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 14] logic PT(s) - 6| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 10] logic PT(s) + 6|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 7| | ? | | S | |=> can support up to [ 4] logic PT(s) 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 18] logic PT(s) -10| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) -13|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 18] logic PT(s) -14| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 9] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) +13| CYCLE_DMA_0_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments @@ -575,19 +556,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_30_| IO| | => |( 5) 6 7 0 |( 5) 4 3 10 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) - 2| IPL_D0_2_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 2| CYCLE_DMA_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) - 6| IPL_D0_1_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 6|inst_UDS_000_INT|NOD| | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| AHIGH_29_| IO| | => | 1 2 3 ( 4)| 9 8 7 ( 6) 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 -10| IPL_D0_0_|NOD| | => | 2 3 4 5 | 8 7 6 5 +10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) -13|inst_AS_030_000_SYNC|NOD| | => | 3 4 5 6 | 7 6 5 4 -14| inst_DTACK_D0|NOD| | => | 4 5 6 7 | 6 5 4 3 +13| CYCLE_DMA_0_|NOD| | => | 3 4 5 6 | 7 6 5 4 +14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== @@ -606,7 +587,7 @@ _|_________________|__|___|_____|___________________________________________ 4| AHIGH_29_| IO|*| 6| => | ( 8) 9 10 11 12 13 14 15 5| AHIGH_30_| IO|*| 5| => | 10 11 12 13 14 15 ( 0) 1 6| AHIGH_31_| IO|*| 4| => | (12) 13 14 15 0 1 2 3 - 7| RESET|INP|*| 3| => | 14 15 0 1 2 3 4 5 + 7| | | | 3| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table @@ -627,7 +608,7 @@ _|_________________|__|___|_____|__________________________________________ 4| AHIGH_29_| IO|*| 6| => | Input macrocell [ -] 5| AHIGH_30_| IO|*| 5| => | Input macrocell [ -] 6| AHIGH_31_| IO|*| 4| => | Input macrocell [ -] - 7| RESET|INP|*| 3| => | Input macrocell [ -] + 7| | | | 3| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Input Multiplexer (IMX) Assignments @@ -645,7 +626,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD IPL_D0_2_| |*] + [MCell 2 |128|NOD CYCLE_DMA_1_| |*] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] @@ -655,7 +636,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD IPL_D0_1_| |*] + [MCell 6 |134|NOD inst_UDS_000_INT| |*] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] @@ -665,17 +646,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 5| IO AHIGH_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD IPL_D0_0_| |*] + [MCell 10 |140| -| | ] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143| IO AHIGH_31_| | ] - [MCell 13 |145|NOD inst_AS_030_000_SYNC| |*] + [MCell 13 |145|NOD CYCLE_DMA_0_| |*] - 7 [IOpin 7 | 3|INP RESET|*|*] + 7 [IOpin 7 | 3| -| | ] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD inst_DTACK_D0| |*] + [MCell 14 |146| -| | ] [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -684,36 +665,36 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| IOPin 1 7 ( 3)| RESET +Mux00| IOPin 6 4 ( 69)| A_0_ +Mux01| ... | ... +Mux02| Mcel 1 6 ( 134)| inst_UDS_000_INT Mux03| IOPin 5 4 ( 56)| IPL_1_ -Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux05| Input Pin ( 14)| nEXP_SPACE +Mux04| Mcel 3 6 ( 182)| IPL_D0_1_ +Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ -Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Mcel 1 13 ( 145)| inst_AS_030_000_SYNC -Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| ... | ... -Mux14| Mcel 7 2 ( 272)| inst_AS_030_D0 -Mux15| ... | ... +Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux08| ... | ... +Mux09| Mcel 0 1 ( 103)| CLK_OUT_INTreg +Mux10| Mcel 1 13 ( 145)| CYCLE_DMA_0_ +Mux11| ... | ... +Mux12| ... | ... +Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux14| ... | ... +Mux15| Mcel 0 6 ( 110)| IPL_D0_0_ Mux16| IOPin 6 2 ( 67)| IPL_0_ -Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| Mcel 1 2 ( 128)| IPL_D0_2_ -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 3 10 ( 188)| CLK_OUT_INTreg +Mux17| ... | ... +Mux18| Mcel 1 2 ( 128)| CYCLE_DMA_1_ +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST Mux22| IOPin 6 3 ( 68)| IPL_2_ -Mux23| Mcel 1 6 ( 134)| IPL_D0_1_ -Mux24| Mcel 1 10 ( 140)| IPL_D0_0_ -Mux25| ... | ... -Mux26| ... | ... +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 0 2 ( 104)| IPL_D0_2_ +Mux26| IOPin 4 1 ( 42)| AS_000 Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ Mux28| Mcel 1 5 ( 133)| RN_IPL_030_0_ -Mux29| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ +Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... @@ -730,19 +711,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 2|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 6]| 1 XOR to [ 6] as logic PT + 6|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| inst_AMIGA_DS|NOD| | S | 2 | 4 to [10]| 1 XOR free + 9|inst_DS_000_DMA|NOD| | S | 6 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +13|inst_AS_000_DMA|NOD| | S | 6 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 to [13]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -757,20 +738,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 2|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| AHIGH_26_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 6| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 18] logic PT(s) + 6|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 9] logic PT(s) 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) - 9| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 14] logic PT(s) -10| inst_AMIGA_DS|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 9|inst_DS_000_DMA|NOD| | S | 6 |=> can support up to [ 18] logic PT(s) +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) -13|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) -14| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) +13|inst_AS_000_DMA|NOD| | S | 6 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -782,19 +763,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2|inst_AS_000_INT|NOD| | => | 6 7 0 1 | 21 22 15 16 + 2|inst_DS_000_ENABLE|NOD| | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 4| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) 5| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 - 6| SM_AMIGA_3_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 6|inst_AS_000_INT|NOD| | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) - 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 16 17 18 19 -10| inst_AMIGA_DS|NOD| | => | 2 3 4 5 | 17 18 19 20 + 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 16 17 18 19 +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 -13|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 18 19 20 21 -14| CLK_000_D_4_|NOD| | => | 4 5 6 7 | 19 20 21 22 +13|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 18 19 20 21 +14| | | | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== @@ -849,7 +830,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD inst_AS_000_INT| |*] + [MCell 2 |152|NOD inst_DS_000_ENABLE| |*] [MCell 3 |154| -| | ] 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] @@ -859,27 +840,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158|NOD SM_AMIGA_3_| |*] + [MCell 6 |158|NOD inst_AS_000_INT| |*] [MCell 7 |160| -| | ] 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] [MCell 8 |161| IO AHIGH_24_| | ] - [MCell 9 |163|NOD SM_AMIGA_2_| |*] + [MCell 9 |163|NOD inst_DS_000_DMA| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164|NOD inst_AMIGA_DS| |*] + [MCell 10 |164|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] [MCell 11 |166| -| | ] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] [MCell 12 |167| IO AHIGH_25_| | ] - [MCell 13 |169|NOD inst_DS_000_ENABLE| |*] + [MCell 13 |169|NOD inst_AS_000_DMA| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] - [MCell 14 |170|NOD CLK_000_D_4_| |*] + [MCell 14 |170| -| | ] [MCell 15 |172| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -888,34 +869,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 2 13 ( 169)| inst_DS_000_ENABLE -Mux01| Mcel 3 13 ( 193)| CLK_000_D_0_ -Mux02| IOPin 1 7 ( 3)| RESET -Mux03| Mcel 2 9 ( 163)| SM_AMIGA_2_ -Mux04| Mcel 3 6 ( 182)| cpu_est_1_ -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| Mcel 5 13 ( 241)| CLK_000_D_3_ -Mux07| ... | ... -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 5 5 ( 229)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux10| Mcel 3 14 ( 194)| cpu_est_2_ -Mux11| IOPin 6 6 ( 71)| RW -Mux12| Mcel 0 1 ( 103)| SM_AMIGA_4_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 3 4 ( 179)| RN_VMA -Mux15| Mcel 5 2 ( 224)| inst_VPA_D -Mux16| Mcel 3 2 ( 176)| cpu_est_3_ -Mux17| IOPin 4 0 ( 41)| BERR -Mux18| Mcel 2 6 ( 158)| SM_AMIGA_3_ +Mux00| Input Pin ( 86)| RST +Mux01| ... | ... +Mux02| Mcel 2 2 ( 152)| inst_DS_000_ENABLE +Mux03| IOPin 5 0 ( 60)| A_1_ +Mux04| Mcel 7 2 ( 272)| inst_AMIGA_DS +Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux08| Mcel 2 10 ( 164)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux09| Mcel 2 6 ( 158)| inst_AS_000_INT +Mux10| Mcel 1 2 ( 128)| CYCLE_DMA_1_ +Mux11| Mcel 2 13 ( 169)| inst_AS_000_DMA +Mux12| Mcel 0 1 ( 103)| CLK_OUT_INTreg +Mux13| Mcel 2 9 ( 163)| inst_DS_000_DMA +Mux14| Mcel 4 5 ( 205)| inst_CLK_OUT_PRE_D +Mux15| ... | ... +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| ... | ... +Mux18| ... | ... Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 1 14 ( 146)| inst_DTACK_D0 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 2 2 ( 152)| inst_AS_000_INT -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Mcel 1 13 ( 145)| CYCLE_DMA_0_ +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_4_ +Mux23| ... | ... +Mux24| ... | ... +Mux25| IOPin 6 6 ( 71)| RW Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| cpu_est_0_ +Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... @@ -932,21 +913,21 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| cpu_est_3_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free + 2| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [ 2]| 1 XOR to [ 2] 3| | ? | | S | | 4 free | 1 XOR free - 4| VMA| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 5]| 1 XOR free - 6| cpu_est_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig -10|CLK_OUT_INTreg|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig + 9| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [14]| 1 XOR to [14] +13| cpu_est_1_|NOD| | S | 4 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -959,22 +940,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| BG_000| IO| | S | 2 |=> can support up to [ 14] logic PT(s) - 2| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4| VMA| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 5|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 10] logic PT(s) - 6| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) - 7| | ? | | S | |=> can support up to [ 13] logic PT(s) - 8| UDS_000| IO| | S | 1 |=> can support up to [ 18] logic PT(s) - 9|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 18] logic PT(s) -10|CLK_OUT_INTreg|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) -11| | ? | | S | |=> can support up to [ 17] logic PT(s) -12| LDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) -13| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) -14| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 13] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) + 1| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 2| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 9] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 18] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 6| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 17] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) + 9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) +13| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -984,21 +965,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 3] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 + 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2| cpu_est_3_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 - 4| VMA| IO| | => | 7 ( 0) 1 2 | 28 ( 35) 34 33 - 5|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 - 6| cpu_est_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 + 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) + 6| IPL_D0_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 - 9|AMIGA_ADDR_ENABLE|OUT| | => | 1 ( 2) 3 4 | 34 ( 33) 32 31 -10|CLK_OUT_INTreg|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10| | | | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13| CLK_000_D_0_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| cpu_est_2_|NOD| | => | 4 5 6 7 | 31 30 29 28 +13| cpu_est_1_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -1010,12 +991,12 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| VMA| IO|*| 35| => | 0 1 2 3 ( 4) 5 6 7 - 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | 2 3 4 ( 5) 6 7 8 9 - 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | 4 5 6 7 8 ( 9) 10 11 + 0| VMA| IO|*| 35| => | ( 0) 1 2 3 4 5 6 7 + 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | 2 3 ( 4) 5 6 7 8 9 + 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | 4 ( 5) 6 7 8 9 10 11 3| UDS_000| IO|*| 32| => | 6 7 ( 8) 9 10 11 12 13 4| LDS_000| IO|*| 31| => | 8 9 10 11 (12) 13 14 15 - 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 + 5| DTACK|INP|*| 30| => | 10 11 12 13 14 15 0 1 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- @@ -1034,7 +1015,7 @@ _|_________________|__|___|_____|__________________________________________ 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | Input macrocell [ -] 3| UDS_000| IO|*| 32| => | Input macrocell [ -] 4| LDS_000| IO|*| 31| => | Input macrocell [ -] - 5| DTACK| IO|*| 30| => | Input macrocell [ -] + 5| DTACK|INP|*| 30| => | Input macrocell [ -] 6| BG_000| IO|*| 29| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BG_000] 7| BGACK_000|INP|*| 28| => | Input macrocell [ -] @@ -1050,42 +1031,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 35| IO VMA|*| ] paired w/[ RN_VMA] [RegIn 0 |174| -| | ] - [MCell 0 |173| IO DTACK| | ] + [MCell 0 |173|NOD RN_VMA| |*] paired w/[ VMA] [MCell 1 |175|NOD RN_BG_000| |*] paired w/[ BG_000] 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD cpu_est_3_| |*] + [MCell 2 |176|NOD cpu_est_2_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] [RegIn 2 |180| -| | ] - [MCell 4 |179|NOD RN_VMA| |*] paired w/[ VMA] - [MCell 5 |181|OUT AMIGA_BUS_ENABLE_HIGH| | ] + [MCell 4 |179|OUT AMIGA_BUS_ENABLE_HIGH| | ] + [MCell 5 |181|OUT AMIGA_ADDR_ENABLE| | ] 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD cpu_est_1_| |*] + [MCell 6 |182|NOD IPL_D0_1_| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] - [MCell 9 |187|OUT AMIGA_ADDR_ENABLE| | ] + [MCell 9 |187|NOD CLK_000_D_0_| |*] - 5 [IOpin 5 | 30| IO DTACK|*|*] + 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD CLK_OUT_INTreg| |*] + [MCell 10 |188| -| | ] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD CLK_000_D_0_| |*] + [MCell 13 |193|NOD cpu_est_1_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD cpu_est_2_| |*] + [MCell 14 |194| -| | ] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1095,36 +1076,36 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| Mcel 5 9 ( 235)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux01| Mcel 3 0 ( 173)| RN_VMA Mux02| Mcel 3 1 ( 175)| RN_BG_000 -Mux03| Mcel 3 2 ( 176)| cpu_est_3_ +Mux03| Input Pin ( 11)| CLK_000 Mux04| IOPin 2 6 ( 21)| BG_030 Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| ... | ... -Mux07| ... | ... -Mux08| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D -Mux09| Mcel 5 2 ( 224)| inst_VPA_D -Mux10| Mcel 3 4 ( 179)| RN_VMA -Mux11| Mcel 2 13 ( 169)| inst_DS_000_ENABLE +Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux08| Mcel 0 10 ( 116)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux09| Mcel 6 13 ( 265)| inst_LDS_000_INT +Mux10| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC +Mux11| Mcel 1 6 ( 134)| inst_UDS_000_INT Mux12| Mcel 6 9 ( 259)| cpu_est_0_ Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Input Pin ( 11)| CLK_000 -Mux15| Mcel 5 1 ( 223)| inst_UDS_000_INT -Mux16| Mcel 3 6 ( 182)| cpu_est_1_ -Mux17| Mcel 5 12 ( 239)| inst_LDS_000_INT -Mux18| Mcel 0 8 ( 113)| inst_AS_000_DMA +Mux14| ... | ... +Mux15| ... | ... +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux17| ... | ... +Mux18| Mcel 0 8 ( 113)| cpu_est_3_ Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 1 13 ( 145)| inst_AS_030_000_SYNC -Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT -Mux23| ... | ... -Mux24| Mcel 3 14 ( 194)| cpu_est_2_ +Mux21| IOPin 5 4 ( 56)| IPL_1_ +Mux22| Mcel 2 2 ( 152)| inst_DS_000_ENABLE +Mux23| Mcel 6 6 ( 254)| inst_VPA_D +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... -Mux28| Mcel 7 2 ( 272)| inst_AS_030_D0 -Mux29| Mcel 3 13 ( 193)| CLK_000_D_0_ -Mux30| ... | ... +Mux28| ... | ... +Mux29| Mcel 3 13 ( 193)| cpu_est_1_ +Mux30| Mcel 4 8 ( 209)| inst_AS_030_D0 Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -1143,15 +1124,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| | ? | | S | | 4 free | 1 XOR free + 8|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| N_60|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| | ? | | S | | 4 free | 1 XOR free +13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1168,18 +1149,18 @@ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 14] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) - 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 14] logic PT(s) - 7| | ? | | S | |=> can support up to [ 19] logic PT(s) - 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 19] logic PT(s) -11| | ? | | S | |=> can support up to [ 19] logic PT(s) -12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) + 3| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) + 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 14] logic PT(s) + 8|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| N_60|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) +13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1195,15 +1176,15 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 + 5|inst_CLK_OUT_PRE_D|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8|inst_CLK_OUT_PRE_D|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9| | | | => | 1 2 3 4 | 42 43 44 45 + 8|inst_AS_030_D0|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9| N_60|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) -13| | | | => | 3 4 5 6 | 44 45 46 47 +13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 --------------------------------------------------------------------------- @@ -1265,7 +1246,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD CIIN_0| |*] + [MCell 5 |205|NOD inst_CLK_OUT_PRE_D| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1274,8 +1255,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD inst_CLK_OUT_PRE_D| |*] - [MCell 9 |211| -| | ] + [MCell 8 |209|NOD inst_AS_030_D0| |*] + [MCell 9 |211|NOD N_60| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1285,7 +1266,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] [MCell 12 |215|OUT CIIN| | ] - [MCell 13 |217| -| | ] + [MCell 13 |217|NOD inst_BGACK_030_INT_D| |*] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] [RegIn 7 |219| -| | ] @@ -1298,39 +1279,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 2 2 ( 152)| inst_AS_000_INT -Mux03| IOPin 0 2 ( 93)| A_DECODE_20_ -Mux04| IOPin 3 7 ( 28)| BGACK_000 -Mux05| IOPin 2 4 ( 19)| AHIGH_24_ -Mux06| IOPin 7 5 ( 80)| RW_000 +Mux02| IOPin 4 1 ( 42)| AS_000 +Mux03| IOPin 2 1 ( 16)| AHIGH_27_ +Mux04| IOPin 1 4 ( 6)| AHIGH_29_ +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ Mux07| IOPin 2 0 ( 15)| AHIGH_28_ Mux08| IOPin 0 0 ( 91)| FPU_SENSE Mux09| IOPin 7 3 ( 82)| AS_030 Mux10| ... | ... -Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux11| IOPin 7 1 ( 84)| A_DECODE_22_ Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| IOPin 1 4 ( 6)| AHIGH_29_ -Mux14| Mcel 4 5 ( 205)| CIIN_0 -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| IOPin 4 1 ( 42)| AS_000 +Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux14| Mcel 4 9 ( 211)| N_60 +Mux15| IOPin 0 3 ( 94)| A_DECODE_21_ +Mux16| Mcel 4 8 ( 209)| inst_AS_030_D0 Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux18| IOPin 7 0 ( 85)| A_DECODE_23_ -Mux19| IOPin 1 5 ( 5)| AHIGH_30_ -Mux20| IOPin 7 1 ( 84)| A_DECODE_22_ -Mux21| IOPin 2 1 ( 16)| AHIGH_27_ +Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux19| Mcel 7 13 ( 289)| inst_CLK_OUT_PRE_50 +Mux20| IOPin 2 4 ( 19)| AHIGH_24_ +Mux21| IOPin 7 5 ( 80)| RW_000 Mux22| IOPin 2 3 ( 18)| AHIGH_25_ -Mux23| Mcel 6 2 ( 248)| inst_CLK_OUT_PRE_50 +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| IOPin 5 3 ( 57)| FC_0_ Mux25| IOPin 1 6 ( 4)| AHIGH_31_ Mux26| IOPin 2 2 ( 17)| AHIGH_26_ -Mux27| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux28| Mcel 7 2 ( 272)| inst_AS_030_D0 -Mux29| ... | ... +Mux27| Mcel 2 6 ( 158)| inst_AS_000_INT +Mux28| IOPin 1 5 ( 5)| AHIGH_30_ +Mux29| IOPin 0 2 ( 93)| A_DECODE_20_ Mux30| ... | ... -Mux31| IOPin 0 3 ( 94)| A_DECODE_21_ -Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux31| ... | ... +Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Macrocell (MCell) Cluster Assignments @@ -1343,18 +1324,18 @@ Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 0]| 1 XOR free - 1|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 1]| 1 XOR free - 2| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 1|inst_AS_030_D1|NOD| | S | 2 | 4 to [ 1]| 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] - 5|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 4|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5| CLK_000_D_4_|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free - 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 9]| 1 XOR free + 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 8]| 1 XOR to [ 8] + 9| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12|inst_LDS_000_INT|NOD| | S | 3 | 4 to [12]| 1 XOR free +12| SM_AMIGA_5_|NOD| | S | 3 | 4 to [12]| 1 XOR free 13| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -1369,19 +1350,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 1|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) - 2| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 9] logic PT(s) - 4| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 14] logic PT(s) - 5|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 0| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) + 1|inst_AS_030_D1|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 19] logic PT(s) + 5| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 10] logic PT(s) - 8| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) - 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 14] logic PT(s) + 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 18] logic PT(s) + 9| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) +12| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) 13| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) @@ -1395,18 +1376,18 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| SM_AMIGA_6_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1|inst_UDS_000_INT|NOD| | => | 5 6 7 0 | 55 54 53 60 - 2| inst_VPA_D|NOD| | => | 6 7 0 1 | 54 53 60 59 + 1|inst_AS_030_D1|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2| | | | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 - 4| SM_AMIGA_i_7_|NOD| | => | 7 0 1 2 | 53 60 59 58 - 5|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 7 0 1 2 | 53 60 59 58 + 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5| CLK_000_D_4_|NOD| | => | 7 0 1 2 | 53 60 59 58 6| | | | => | 0 1 2 3 | 60 59 58 57 7| | | | => | 0 1 2 3 | 60 59 58 57 - 8| SM_AMIGA_1_|NOD| | => | 1 2 3 4 | 59 58 57 56 - 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 1 2 3 4 | 59 58 57 56 + 8| SM_AMIGA_i_7_|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9| inst_DTACK_D0|NOD| | => | 1 2 3 4 | 59 58 57 56 10| | | | => | 2 3 4 5 | 58 57 56 55 11| | | | => | 2 3 4 5 | 58 57 56 55 -12|inst_LDS_000_INT|NOD| | => | 3 4 5 6 | 57 56 55 54 +12| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 57 56 55 54 13| CLK_000_D_3_|NOD| | => | 3 4 5 6 | 57 56 55 54 14| | | | => | 4 5 6 7 | 56 55 54 53 15| | | | => | 4 5 6 7 | 56 55 54 53 @@ -1459,17 +1440,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] [MCell 0 |221|NOD SM_AMIGA_6_| |*] - [MCell 1 |223|NOD inst_UDS_000_INT| |*] + [MCell 1 |223|NOD inst_AS_030_D1| |*] 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] [RegIn 1 |225| -| | ] - [MCell 2 |224|NOD inst_VPA_D| |*] + [MCell 2 |224| -| | ] [MCell 3 |226| -| | ] 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD SM_AMIGA_i_7_| |*] - [MCell 5 |229|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 4 |227|NOD inst_AS_030_000_SYNC| |*] + [MCell 5 |229|NOD CLK_000_D_4_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] @@ -1478,8 +1459,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233|NOD SM_AMIGA_1_| |*] - [MCell 9 |235|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 8 |233|NOD SM_AMIGA_i_7_| |*] + [MCell 9 |235|NOD inst_DTACK_D0| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] @@ -1488,7 +1469,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD inst_LDS_000_INT| |*] + [MCell 12 |239|NOD SM_AMIGA_5_| |*] [MCell 13 |241|NOD CLK_000_D_3_| |*] 7 [IOpin 7 | 53| -| | ] @@ -1502,37 +1483,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 5 ( 70)| SIZE_0_ -Mux01| Mcel 3 13 ( 193)| CLK_000_D_0_ -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_1_ -Mux03| Mcel 2 9 ( 163)| SM_AMIGA_2_ -Mux04| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux00| Input Pin ( 86)| RST +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 4 13 ( 217)| inst_BGACK_030_INT_D +Mux03| ... | ... +Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| Mcel 5 13 ( 241)| CLK_000_D_3_ -Mux07| Mcel 2 14 ( 170)| CLK_000_D_4_ -Mux08| ... | ... -Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ -Mux10| Mcel 5 1 ( 223)| inst_UDS_000_INT -Mux11| IOPin 5 0 ( 60)| A_1_ -Mux12| ... | ... -Mux13| Input Pin ( 36)| VPA -Mux14| Mcel 5 5 ( 229)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux15| IOPin 6 4 ( 69)| A_0_ -Mux16| ... | ... -Mux17| Mcel 5 12 ( 239)| inst_LDS_000_INT -Mux18| Mcel 5 9 ( 235)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 1 13 ( 145)| inst_AS_030_000_SYNC +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux09| IOPin 3 5 ( 30)| DTACK +Mux10| Mcel 5 1 ( 223)| inst_AS_030_D1 +Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux14| Mcel 5 5 ( 229)| CLK_000_D_4_ +Mux15| Mcel 5 13 ( 241)| CLK_000_D_3_ +Mux16| Mcel 4 8 ( 209)| inst_AS_030_D0 +Mux17| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux18| ... | ... +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ +Mux21| Mcel 7 6 ( 278)| CLK_000_D_2_ Mux22| ... | ... -Mux23| ... | ... -Mux24| Input Pin ( 86)| RST +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Mcel 0 12 ( 119)| SM_AMIGA_0_ Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ Mux26| ... | ... -Mux27| IOPin 7 6 ( 79)| SIZE_1_ +Mux27| ... | ... Mux28| ... | ... -Mux29| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ -Mux30| Mcel 7 6 ( 278)| CLK_000_D_2_ +Mux29| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC +Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -1546,21 +1527,21 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free + 0| RW| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2|inst_DSACK1_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free - 5|inst_RESET_OUT|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6| RST_DLY_0_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 5| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free - 8| A_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free + 8| A_0_| IO| | S | 2 | 4 to [ 8]| 1 XOR free 9| cpu_est_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10| RST_DLY_2_|NOD| | S | 2 | 4 to [10]| 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SIZE_0_| IO| | S | 3 | 4 to [12]| 1 XOR free -13| SM_AMIGA_5_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| RST_DLY_1_|NOD| | S | 2 :+: 1| 4 to [14]| 1 XOR to [14] +12| SIZE_0_| IO| | S | 2 | 4 to [12]| 1 XOR free +13|inst_LDS_000_INT|NOD| | S | 3 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1573,22 +1554,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 0| RW| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 9] logic PT(s) - 4| E|OUT| | S | 2 |=> can support up to [ 10] logic PT(s) - 5|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) - 6| RST_DLY_0_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| A_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 9| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -10| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| SIZE_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) -13| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -14| RST_DLY_1_|NOD| | S | 2 :+: 1|=> can support up to [ 9] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 2|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| E|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 6| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| A_0_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) + 9| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| SIZE_0_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) +13|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1600,19 +1581,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 2|inst_CLK_OUT_PRE_50|NOD| | => | 6 7 0 1 | 71 72 65 66 + 2|inst_DSACK1_INT|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5|inst_RESET_OUT|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| RST_DLY_0_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6| inst_VPA_D|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) 9| cpu_est_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10| RST_DLY_2_|NOD| | => | 2 3 4 5 | 67 68 69 70 +10| | | | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 68 69 70 71 -14| RST_DLY_1_|NOD| | => | 4 5 6 7 | 69 70 71 72 +13|inst_LDS_000_INT|NOD| | => | 3 4 5 6 | 68 69 70 71 +14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== @@ -1647,11 +1628,8 @@ _|_________________|__|___|_____|__________________________________________ 2| IPL_0_|INP|*| 67| => | Input macrocell [ -] 3| IPL_2_|INP|*| 68| => | Input macrocell [ -] 4| A_0_| IO|*| 69| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_A_0_] 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_SIZE_0_] 6| RW| IO|*| 71| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_RW] 7| | | | 72| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -1665,42 +1643,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] - [MCell 0 |245|NOD RN_RW| |*] paired w/[ RW] + [MCell 0 |245| IO RW| | ] [MCell 1 |247|OUT CLK_DIV_OUT| | ] 1 [IOpin 1 | 66|OUT E|*| ] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 2 |248|NOD inst_DSACK1_INT| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|OUT E| | ] - [MCell 5 |253|NOD inst_RESET_OUT| |*] + [MCell 5 |253|NOD SM_AMIGA_4_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD RST_DLY_0_| |*] + [MCell 6 |254|NOD inst_VPA_D| |*] [MCell 7 |256| -| | ] - 4 [IOpin 4 | 69| IO A_0_|*|*] paired w/[ RN_A_0_] + 4 [IOpin 4 | 69| IO A_0_|*|*] [RegIn 4 |258| -| | ] - [MCell 8 |257|NOD RN_A_0_| |*] paired w/[ A_0_] + [MCell 8 |257| IO A_0_| | ] [MCell 9 |259|NOD cpu_est_0_| |*] - 5 [IOpin 5 | 70| IO SIZE_0_|*|*] paired w/[ RN_SIZE_0_] + 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD RST_DLY_2_| |*] + [MCell 10 |260| -| | ] [MCell 11 |262| -| | ] - 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] + 6 [IOpin 6 | 71| IO RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD RN_SIZE_0_| |*] paired w/[ SIZE_0_] - [MCell 13 |265|NOD SM_AMIGA_5_| |*] + [MCell 12 |263| IO SIZE_0_| | ] + [MCell 13 |265|NOD inst_LDS_000_INT| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] - [MCell 14 |266|NOD RST_DLY_1_| |*] + [MCell 14 |266| -| | ] [MCell 15 |268| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1709,39 +1687,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 3 4 ( 31)| LDS_000 -Mux01| Mcel 3 13 ( 193)| CLK_000_D_0_ -Mux02| Mcel 3 10 ( 188)| CLK_OUT_INTreg -Mux03| Mcel 3 2 ( 176)| cpu_est_3_ -Mux04| Mcel 6 2 ( 248)| inst_CLK_OUT_PRE_50 -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 6 12 ( 263)| RN_SIZE_0_ +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 5 12 ( 239)| SM_AMIGA_5_ +Mux02| Mcel 0 5 ( 109)| SM_AMIGA_1_ +Mux03| Mcel 3 2 ( 176)| cpu_est_2_ +Mux04| Mcel 6 2 ( 248)| inst_DSACK1_INT +Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux06| IOPin 7 6 ( 79)| SIZE_1_ +Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 6 13 ( 265)| SM_AMIGA_5_ -Mux10| Mcel 6 14 ( 266)| RST_DLY_1_ +Mux09| Mcel 6 13 ( 265)| inst_LDS_000_INT +Mux10| Input Pin ( 36)| VPA Mux11| ... | ... -Mux12| Mcel 6 9 ( 259)| cpu_est_0_ -Mux13| Mcel 6 8 ( 257)| RN_A_0_ -Mux14| ... | ... -Mux15| ... | ... -Mux16| Mcel 3 6 ( 182)| cpu_est_1_ -Mux17| Mcel 6 0 ( 245)| RN_RW -Mux18| ... | ... -Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux12| Mcel 0 1 ( 103)| CLK_OUT_INTreg +Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux15| IOPin 6 4 ( 69)| A_0_ +Mux16| ... | ... +Mux17| ... | ... +Mux18| Mcel 0 8 ( 113)| cpu_est_3_ +Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 10 ( 260)| RST_DLY_2_ -Mux23| Mcel 6 6 ( 254)| RST_DLY_0_ -Mux24| Mcel 3 14 ( 194)| cpu_est_2_ -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux21| Mcel 3 13 ( 193)| cpu_est_1_ +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_4_ +Mux23| ... | ... +Mux24| IOPin 3 4 ( 31)| LDS_000 +Mux25| ... | ... Mux26| ... | ... -Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux28| ... | ... +Mux27| Mcel 6 9 ( 259)| cpu_est_0_ +Mux28| IOPin 7 5 ( 80)| RW_000 Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... -Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1755,7 +1733,7 @@ Mux32| Mcel 6 5 ( 253)| inst_RESET_OUT _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW_000| IO| | S | 4 | 4 to [ 0]| 1 XOR free 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2| inst_AMIGA_DS|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free 5| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig @@ -1765,8 +1743,8 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 9| DSACK1|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SIZE_1_| IO| | S | 3 | 4 to [12]| 1 XOR free -13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +12| SIZE_1_| IO| | S | 2 | 4 to [12]| 1 XOR free +13|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1780,10 +1758,10 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW_000| IO| | S | 4 |=> can support up to [ 13] logic PT(s) - 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 0| RW_000| IO| | S | 4 |=> can support up to [ 9] logic PT(s) + 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 2| inst_AMIGA_DS|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) 5| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 6| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) @@ -1792,8 +1770,8 @@ _|_________________|__|__|___|_____|_______________________________________ 9| DSACK1|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12| SIZE_1_| IO| | S | 3 |=> can support up to [ 19] logic PT(s) -13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +12| SIZE_1_| IO| | S | 2 |=> can support up to [ 19] logic PT(s) +13|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -1807,7 +1785,7 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 2|inst_AS_030_D0|NOD| | => | 6 7 0 1 | 79 78 85 84 + 2| inst_AMIGA_DS|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) 5| CLK_000_D_1_|NOD| | => | 7 0 1 2 | 78 85 84 83 @@ -1818,7 +1796,7 @@ _|_________________|__|_____|____________________|________________________ 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) -13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 82 81 80 79 +13|inst_CLK_OUT_PRE_50|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1858,7 +1836,6 @@ _|_________________|__|___|_____|__________________________________________ 5| RW_000| IO|*| 80| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_RW_000] 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_SIZE_1_] 7| FPU_CS|OUT|*| 78| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -1877,7 +1854,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD inst_AS_030_D0| |*] + [MCell 2 |272|NOD inst_AMIGA_DS| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] @@ -1900,10 +1877,10 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 10 |284| -| | ] [MCell 11 |286| -| | ] - 6 [IOpin 6 | 79| IO SIZE_1_|*|*] paired w/[ RN_SIZE_1_] + 6 [IOpin 6 | 79| IO SIZE_1_|*|*] [RegIn 6 |288| -| | ] - [MCell 12 |287|NOD RN_SIZE_1_| |*] paired w/[ SIZE_1_] - [MCell 13 |289|NOD inst_BGACK_030_INT_D| |*] + [MCell 12 |287| IO SIZE_1_| | ] + [MCell 13 |289|NOD inst_CLK_OUT_PRE_50| |*] 7 [IOpin 7 | 78|OUT FPU_CS|*| ] [RegIn 7 |291| -| | ] @@ -1918,35 +1895,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 0 5 ( 109)| inst_DSACK1_INT -Mux03| Mcel 0 8 ( 113)| inst_AS_000_DMA +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ +Mux03| ... | ... Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ -Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 5 4 ( 227)| SM_AMIGA_i_7_ -Mux11| IOPin 6 6 ( 71)| RW -Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux07| Mcel 7 13 ( 289)| inst_CLK_OUT_PRE_50 +Mux08| IOPin 6 6 ( 71)| RW +Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux10| ... | ... +Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux12| IOPin 3 3 ( 32)| UDS_000 Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ Mux14| ... | ... -Mux15| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| IOPin 4 1 ( 42)| AS_000 Mux17| IOPin 5 3 ( 57)| FC_0_ Mux18| IOPin 3 7 ( 28)| BGACK_000 Mux19| IOPin 0 0 ( 91)| FPU_SENSE Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 3 13 ( 193)| CLK_000_D_0_ -Mux22| Mcel 6 5 ( 253)| inst_RESET_OUT +Mux21| ... | ... +Mux22| ... | ... Mux23| Mcel 7 0 ( 269)| RN_RW_000 Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux25| Mcel 3 9 ( 187)| CLK_000_D_0_ Mux26| ... | ... Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ Mux28| ... | ... -Mux29| Mcel 7 12 ( 287)| RN_SIZE_1_ -Mux30| ... | ... -Mux31| ... | ... -Mux32| ... | ... +Mux29| ... | ... +Mux30| Mcel 2 13 ( 169)| inst_AS_000_DMA +Mux31| Mcel 6 2 ( 248)| inst_DSACK1_INT +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index bd4efef..d64aec7 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic -Project Fitted on : Thu Dec 29 16:02:00 2016 +Project Fitted on : Sat Dec 30 00:43:46 2017 Device : M4A5-128/64 Package : 100TQFP @@ -37,11 +37,11 @@ Fitter 00:00:00 Design_Summary ~~~~~~~~~~~~~~ - Total Input Pins : 24 + Total Input Pins : 23 Total Output Pins : 18 - Total Bidir I/O Pins : 19 - Total Flip-Flops : 57 - Total Product Terms : 210 + Total Bidir I/O Pins : 18 + Total Flip-Flops : 52 + Total Product Terms : 177 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -52,15 +52,15 @@ Device_Resource_Summary Available Used Available Utilization Dedicated Pins Input-Only Pins 2 2 0 --> 100% - Clock/Input Pins 4 4 0 --> 100% -I/O Pins 64 55 9 --> 85% -Logic Macrocells 128 84 44 --> 65% + Clock/Input Pins 4 3 1 --> 75% +I/O Pins 64 54 10 --> 84% +Logic Macrocells 128 79 49 --> 61% Input Registers 64 0 64 --> 0% - Unusable Macrocells .. 0 .. + Unusable Macrocells .. 1 .. -CSM Outputs/Total Block Inputs 264 205 59 --> 77% -Logical Product Terms 640 213 427 --> 33% -Product Term Clusters 128 54 74 --> 42% +CSM Outputs/Total Block Inputs 264 188 76 --> 71% +Logical Product Terms 640 179 461 --> 27% +Product Term Clusters 128 44 84 --> 34%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 24 8 0 11 0 5 46 3 Lo -Block B 26 8 0 12 0 4 45 6 Lo -Block C 26 7 0 12 0 4 24 11 Lo -Block D 24 8 0 12 0 4 23 10 Lo -Block E 30 4 0 6 0 10 8 14 Lo -Block F 24 5 0 9 0 7 21 9 Lo -Block G 24 7 0 12 0 4 29 6 Lo -Block H 27 8 0 10 0 6 17 13 Lo +Block A 23 8 0 11 0 5 26 11 Lo +Block B 20 7 0 10 1 5 42 7 Lo +Block C 21 7 0 11 0 5 24 10 Lo +Block D 22 8 0 10 0 6 18 11 Lo +Block E 30 4 0 8 0 8 10 14 Lo +Block F 24 5 0 8 0 8 22 10 Lo +Block G 23 7 0 10 0 6 20 9 Lo +Block H 25 8 0 10 0 6 17 12 Lo --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -169,7 +169,7 @@ Pin No| Type |Pad |Pin | Signal name --------------------------------------------------------------- 1 | GND | | | 2 | JTAG | | | - 3 | I_O | B7 | * |RESET + 3 | I_O | B7 | | 4 | I_O | B6 | * |AHIGH_31_ 5 | I_O | B5 | * |AHIGH_30_ 6 | I_O | B4 | * |AHIGH_29_ @@ -230,7 +230,7 @@ Pin No| Type |Pad |Pin | Signal name 61 | CkIn | | * |CLK_OSZI 62 | Vcc | | | 63 | GND | | | -64 | CkIn | | * |CLK_030 +64 | CkIn | | | 65 | I_O | G0 | * |CLK_DIV_OUT 66 | I_O | G1 | * |E 67 | I_O | G2 | * |IPL_0_ @@ -287,30 +287,29 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O -----F-- Low Slow A_1_ - 96 A . I/O -B--E--H Low Slow A_DECODE_16_ - 59 F . I/O -B--E--H Low Slow A_DECODE_17_ - 95 A . I/O -B--E--H Low Slow A_DECODE_18_ - 97 A . I/O -B--E--H Low Slow A_DECODE_19_ + 60 F . I/O A-C----- Low Slow A_1_ + 96 A . I/O ----EF-H Low Slow A_DECODE_16_ + 59 F . I/O ----EF-H Low Slow A_DECODE_17_ + 95 A . I/O ----EF-H Low Slow A_DECODE_18_ + 97 A . I/O ----EF-H Low Slow A_DECODE_19_ 93 A . I/O ----E--- Low Slow A_DECODE_20_ 94 A . I/O ----E--- Low Slow A_DECODE_21_ 84 H . I/O ----E--- Low Slow A_DECODE_22_ 85 H . I/O ----E--- Low Slow A_DECODE_23_ 28 D . I/O ----E--H Low Slow BGACK_000 21 C . I/O ---D---- Low Slow BG_030 - 57 F . I/O -B--E--H Low Slow FC_0_ - 58 F . I/O -B--E--H Low Slow FC_1_ + 30 D . I/O -----F-- Low Slow DTACK + 57 F . I/O ----EF-H Low Slow FC_0_ + 58 F . I/O ----EF-H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O -B------ Low Slow IPL_0_ - 56 F . I/O -B------ Low Slow IPL_1_ - 68 G . I/O -B------ Low Slow IPL_2_ - 3 B . I/O -BC----- Low Fast RESET + 67 G . I/O AB------ Low Slow IPL_0_ + 56 F . I/O -B-D---- Low Slow IPL_1_ + 68 G . I/O AB------ Low Slow IPL_2_ 11 . . Ck/I ---D---- - Slow CLK_000 - 14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE - 36 . . Ded -----F-- - Slow VPA + 14 . . Ck/I ---DEF-H - Slow nEXP_SPACE + 36 . . Ded ------G- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI - 64 . . Ck/I A------- - Slow CLK_030 - 86 . . Ded ABCD-FGH - Slow RST + 86 . . Ded ABCDEFGH - Slow RST ---------------------------------------------------------------------- Power : Hi = High @@ -367,17 +366,16 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B 1 COM ----E--- Low Fast AHIGH_29_ 5 B 1 COM ----E--- Low Fast AHIGH_30_ 4 B 1 COM ----E--- Low Fast AHIGH_31_ - 42 E 1 COM A---E--H Low Fast AS_000 - 82 H 1 COM ABCDE--H Low Fast AS_030 - 69 G 3 DFF -----F-- Low Fast A_0_ - 41 E 1 COM --C----- Low Fast BERR - 30 D 1 COM -B------ Low Slow DTACK - 31 D 1 COM --C---GH Low Fast LDS_000 - 71 G 2 DFF --C----H Low Fast RW - 80 H 4 DFF A---E-G- Low Fast RW_000 - 70 G 3 DFF -----F-- Low Fast SIZE_0_ - 79 H 3 DFF -----F-- Low Fast SIZE_1_ - 32 D 1 COM --C---GH Low Fast UDS_000 + 42 E 1 COM ABC-E--H Low Fast AS_000 + 82 H 1 COM --CDEFGH Low Fast AS_030 + 69 G 2 DFF -B----G- Low Fast A_0_ + 41 E 1 COM A------- Low Fast BERR + 31 D 1 COM ------GH Low Fast LDS_000 + 71 G 1 DFF --C----H Low Fast RW + 80 H 4 DFF --C-E-G- Low Fast RW_000 + 70 G 2 DFF ------G- Low Fast SIZE_0_ + 79 H 2 DFF ------G- Low Fast SIZE_1_ + 32 D 1 COM ------GH Low Fast UDS_000 ---------------------------------------------------------------------- Power : Hi = High @@ -393,64 +391,55 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - E5 E 2 COM ----E--- Low Slow CIIN_0 - D13 D 1 DFF A-CD-FGH Low Slow CLK_000_D_0_ - H5 H 1 DFF A-CD-FGH Low Slow CLK_000_D_1_ + D9 D 1 DFF ABCD-FGH Low Slow CLK_000_D_0_ + H5 H 1 DFF ABCD-FGH Low Slow CLK_000_D_1_ H6 H 1 DFF -----F-- Low Slow CLK_000_D_2_ - F13 F 1 DFF --C--F-- Low Slow CLK_000_D_3_ - C14 C 1 DFF -----F-- Low Slow CLK_000_D_4_ - A9 A 9 DFF A------- Low Slow CLK_030_PE_0_ - A2 A 6 DFF A------- Low Slow CLK_030_PE_1_ - D10 D 1 DFF AB----G- Low Slow CLK_OUT_INTreg - A6 A 4 DFF A------- Low Slow CYCLE_DMA_0_ - A10 A 2 DFF A------- Low Slow CYCLE_DMA_1_ - B10 B 1 DFF -B------ Low Slow IPL_D0_0_ - B6 B 1 DFF -B------ Low Slow IPL_D0_1_ - B2 B 1 DFF -B------ Low Slow IPL_D0_2_ - G8 G 3 DFF ------G- Low - RN_A_0_ --> A_0_ + F13 F 1 DFF -----F-- Low Slow CLK_000_D_3_ + F5 F 1 DFF -----F-- Low Slow CLK_000_D_4_ + A1 A 1 DFF -BC---G- Low Slow CLK_OUT_INTreg + B13 B 4 DFF -BC----- Low Slow CYCLE_DMA_0_ + B2 B 2 DFF -BC----- Low Slow CYCLE_DMA_1_ + A6 A 1 DFF -B------ Low Slow IPL_D0_0_ + D6 D 1 DFF -B------ Low Slow IPL_D0_1_ + A2 A 1 DFF -B------ Low Slow IPL_D0_2_ + E9 E 2 COM ----E--- Low Slow N_60 H4 H 3 DFF ABCDEFGH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF ---D---- Low - RN_BG_000 --> BG_000 B5 B 10 DFF -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ B9 B 10 DFF -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ B4 B 10 DFF -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ - G0 G 2 DFF ------G- Low - RN_RW --> RW H0 H 4 DFF -------H Low - RN_RW_000 --> RW_000 - G12 G 3 DFF ------G- Low - RN_SIZE_0_ --> SIZE_0_ - H12 H 3 DFF -------H Low - RN_SIZE_1_ --> SIZE_1_ - D4 D 3 TFF --CD---- Low - RN_VMA --> VMA - G6 G 4 DFF ------G- Low Slow RST_DLY_0_ - G14 G 2 DFF ------G- Low Slow RST_DLY_1_ - G10 G 2 DFF ------G- Low Slow RST_DLY_2_ + D0 D 3 TFF A--D---- Low - RN_VMA --> VMA A12 A 3 DFF A----F-H Low Slow SM_AMIGA_0_ - F8 F 3 DFF A----F-- Low Slow SM_AMIGA_1_ - C9 C 5 DFF --C--F-- Low Slow SM_AMIGA_2_ - C6 C 5 TFF --C----- Low Slow SM_AMIGA_3_ - A1 A 3 DFF A-C----- Low Slow SM_AMIGA_4_ - G13 G 3 DFF A-----G- Low Slow SM_AMIGA_5_ - F0 F 3 DFF --C--FGH Low Slow SM_AMIGA_6_ - F4 F 3 TFF -B---F-H Low Slow SM_AMIGA_i_7_ - G9 G 3 DFF --CD--G- Low Slow cpu_est_0_ - D6 D 4 DFF --CD--G- Low Slow cpu_est_1_ - D14 D 1 DFF --CD--G- Low Slow cpu_est_2_ - D2 D 4 DFF --CD--G- Low Slow cpu_est_3_ - F9 F 2 DFF ---D-F-- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - F5 F 2 DFF --C--F-- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW - C10 C 2 DFF A------- Low Slow inst_AMIGA_DS - A8 A 6 DFF A--D---H Low Slow inst_AS_000_DMA - C2 C 2 DFF --C-E--- Low Slow inst_AS_000_INT - B13 B 7 DFF -B-D-F-- Low Slow inst_AS_030_000_SYNC - H2 H 1 DFF -B-DE--- Low Slow inst_AS_030_D0 - H13 H 1 DFF -B---FGH Low Slow inst_BGACK_030_INT_D - G2 G 1 DFF ----E-G- Low Slow inst_CLK_OUT_PRE_50 - E8 E 1 DFF A--D---- Low Slow inst_CLK_OUT_PRE_D - A5 A 2 DFF A------H Low Slow inst_DSACK1_INT - A13 A 9 DFF A------- Low Slow inst_DS_000_DMA - C13 C 3 DFF --CD---- Low Slow inst_DS_000_ENABLE - B14 B 1 DFF --C----- Low Slow inst_DTACK_D0 - F12 F 3 DFF ---D-F-- Low Slow inst_LDS_000_INT - G5 G 2 DFF A--DE-GH Low Slow inst_RESET_OUT - F1 F 2 DFF ---D-F-- Low Slow inst_UDS_000_INT - F2 F 1 DFF --CD---- Low Slow inst_VPA_D + A5 A 3 DFF A-----G- Low Slow SM_AMIGA_1_ + A9 A 5 DFF A------- Low Slow SM_AMIGA_2_ + A13 A 5 TFF A------- Low Slow SM_AMIGA_3_ + G5 G 3 DFF A-C---G- Low Slow SM_AMIGA_4_ + F12 F 3 DFF -----FG- Low Slow SM_AMIGA_5_ + F0 F 3 DFF -BC--FGH Low Slow SM_AMIGA_6_ + F8 F 3 TFF -----F-H Low Slow SM_AMIGA_i_7_ + G9 G 3 DFF A--D--G- Low Slow cpu_est_0_ + D13 D 4 DFF A--D--G- Low Slow cpu_est_1_ + D2 D 1 DFF A--D--G- Low Slow cpu_est_2_ + A8 A 4 DFF A--D--G- Low Slow cpu_est_3_ + A10 A 1 DFF ---D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + C10 C 1 DFF --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + H2 H 2 DFF --C----- Low Slow inst_AMIGA_DS + C13 C 6 DFF --C----H Low Slow inst_AS_000_DMA + C6 C 2 DFF --C-E--- Low Slow inst_AS_000_INT + F4 F 7 DFF ---D-F-- Low Slow inst_AS_030_000_SYNC + E8 E 1 DFF ---DEF-- Low Slow inst_AS_030_D0 + F1 F 2 DFF -----F-- Low Slow inst_AS_030_D1 + E13 E 1 DFF -----F-- Low Slow inst_BGACK_030_INT_D + H13 H 1 DFF ----E--H Low Slow inst_CLK_OUT_PRE_50 + E5 E 1 DFF A-C----- Low Slow inst_CLK_OUT_PRE_D + G2 G 2 DFF ------GH Low Slow inst_DSACK1_INT + C9 C 6 DFF A-C----- Low Slow inst_DS_000_DMA + C2 C 3 DFF --CD---- Low Slow inst_DS_000_ENABLE + F9 F 1 DFF A------- Low Slow inst_DTACK_D0 + G13 G 3 DFF ---D--G- Low Slow inst_LDS_000_INT + B6 B 2 DFF -B-D---- Low Slow inst_UDS_000_INT + G6 G 1 DFF A--D---- Low Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -465,188 +454,157 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E} - IPL_1_{ G}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} - : IPL_D0_1_{ B} - IPL_0_{ H}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} - : IPL_D0_0_{ B} -A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E} - FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ B} - A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} - IPL_2_{ H}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} - : IPL_D0_2_{ B} - FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ B} + AHIGH_27_{ D}: CIIN{ E} N_60{ E} + AHIGH_26_{ D}: CIIN{ E} N_60{ E} + AHIGH_25_{ D}: CIIN{ E} N_60{ E} + AHIGH_24_{ D}: CIIN{ E} N_60{ E} + AHIGH_31_{ C}: CIIN{ E} N_60{ E} +A_DECODE_22_{ I}: CIIN{ E} N_60{ E} +A_DECODE_21_{ B}: CIIN{ E} N_60{ E} +A_DECODE_23_{ I}: CIIN{ E} N_60{ E} +A_DECODE_20_{ B}: CIIN{ E} N_60{ E} +A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} +A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} +A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} +A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_2_{ A} + FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} - : DSACK1{ H}AMIGA_BUS_ENABLE_HIGH{ D} inst_AS_030_D0{ H} - :inst_AS_030_000_SYNC{ B}inst_DS_000_ENABLE{ C}inst_DSACK1_INT{ A} + : DSACK1{ H}AMIGA_BUS_ENABLE_HIGH{ D} inst_AS_030_D0{ E} + :inst_AS_030_000_SYNC{ F}inst_DS_000_ENABLE{ C}inst_DSACK1_INT{ G} :inst_AS_000_INT{ C} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} - : BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} - : CLK_030_PE_1_{ A} CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} - : CLK_030_PE_0_{ A} - UDS_000{ E}: A_0_{ G} SIZE_1_{ H} SIZE_0_{ G} - : inst_AMIGA_DS{ C} - LDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G} inst_AMIGA_DS{ C} - nEXP_SPACE{. }: AHIGH_31_{ B} AS_030{ H} DS_030{ A} - : DSACK1{ H} AHIGH_30_{ B} AHIGH_29_{ B} - : AHIGH_28_{ C} AHIGH_27_{ C} AHIGH_26_{ C} - : AHIGH_25_{ C} AHIGH_24_{ C}AMIGA_BUS_DATA_DIR{ E} - : A_0_{ G} SIZE_1_{ H} BG_000{ D} - : SIZE_0_{ G}inst_AS_030_000_SYNC{ B} SM_AMIGA_6_{ F} - : SM_AMIGA_i_7_{ F} CIIN_0{ E} - BERR{ F}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + : BGACK_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} + : CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ B} + UDS_000{ E}: SIZE_1_{ H} A_0_{ G} SIZE_0_{ G} + : inst_AMIGA_DS{ H} + LDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G} inst_AMIGA_DS{ H} + nEXP_SPACE{. }: DSACK1{ H}AMIGA_BUS_DATA_DIR{ E} BG_000{ D} + :inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} + : N_60{ E} + BERR{ F}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} BG_030{ D}: BG_000{ D} BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} - CLK_030{. }:inst_DS_000_DMA{ A} CLK_000{. }: CLK_000_D_0_{ D} + IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_1_{ D} + IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_0_{ A} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} - DTACK{ E}: inst_DTACK_D0{ B} - AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E} - VPA{. }: inst_VPA_D{ F} - AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E} - AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E} - RST{. }: A_0_{ G} SIZE_1_{ H} IPL_030_1_{ B} - : IPL_030_0_{ B} IPL_030_2_{ B} RW_000{ H} - : BG_000{ D} BGACK_030{ H} SIZE_0_{ G} - : VMA{ D} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F} - :inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ B} - :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} - : inst_VPA_D{ F} inst_DTACK_D0{ B} inst_RESET_OUT{ G} - : CLK_030_PE_1_{ A} inst_AMIGA_DS{ C} IPL_D0_0_{ B} - : IPL_D0_1_{ B} IPL_D0_2_{ B}inst_LDS_000_INT{ F} - :inst_DS_000_ENABLE{ C}inst_UDS_000_INT{ F} SM_AMIGA_6_{ F} - : SM_AMIGA_4_{ A} SM_AMIGA_1_{ F} SM_AMIGA_0_{ A} - : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} CLK_030_PE_0_{ A} - : RST_DLY_0_{ G} RST_DLY_1_{ G} RST_DLY_2_{ G} - :inst_DSACK1_INT{ A}inst_AS_000_INT{ C} SM_AMIGA_5_{ G} - : SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} SM_AMIGA_i_7_{ F} - AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E} - RESET{ C}: AHIGH_31_{ B} AHIGH_30_{ B} AHIGH_29_{ B} - : AHIGH_28_{ C} AHIGH_27_{ C} AHIGH_26_{ C} - : AHIGH_25_{ C} AHIGH_24_{ C} - AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E} - AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E} - AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E} -A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E} -A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E} -A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E} -A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ B} -A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ B} -A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ B} -A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ B} - A_0_{ H}:inst_LDS_000_INT{ F}inst_UDS_000_INT{ F} - RN_A_0_{ H}: A_0_{ G} - SIZE_1_{ I}:inst_LDS_000_INT{ F} - RN_SIZE_1_{ I}: SIZE_1_{ H} -RN_IPL_030_1_{ C}: IPL_030_1_{ B} -RN_IPL_030_0_{ C}: IPL_030_0_{ B} + DTACK{ E}: inst_DTACK_D0{ F} + VPA{. }: inst_VPA_D{ G} + RST{. }: AS_000{ E} UDS_000{ D} LDS_000{ D} + : SIZE_1_{ H} IPL_030_2_{ B} RW_000{ H} + : BG_000{ D} BGACK_030{ H} A_0_{ G} + : IPL_030_1_{ B} IPL_030_0_{ B} VMA{ D} + : RW{ G} SIZE_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} + :inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} inst_AS_030_D0{ E} inst_AS_030_D1{ F} + :inst_AS_030_000_SYNC{ F}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} + : inst_VPA_D{ G} inst_DTACK_D0{ F} inst_AMIGA_DS{ H} + : IPL_D0_0_{ A} IPL_D0_1_{ D} IPL_D0_2_{ A} + :inst_UDS_000_INT{ B}inst_DS_000_ENABLE{ C}inst_LDS_000_INT{ G} + :inst_BGACK_030_INT_D{ E} SM_AMIGA_6_{ F} SM_AMIGA_4_{ G} + : SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ B} + : CYCLE_DMA_1_{ B}inst_DSACK1_INT{ G}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ F} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + : SM_AMIGA_i_7_{ F} + AHIGH_30_{ C}: CIIN{ E} N_60{ E} + AHIGH_29_{ C}: CIIN{ E} N_60{ E} + AHIGH_28_{ D}: CIIN{ E} N_60{ E} + SIZE_1_{ I}:inst_LDS_000_INT{ G} RN_IPL_030_2_{ C}: IPL_030_2_{ B} - RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_AS_000_DMA{ A} - :inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} CLK_030_PE_0_{ A} + RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_AS_000_DMA{ C} + :inst_DS_000_DMA{ C} RN_RW_000{ I}: RW_000{ H} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} - : DS_030{ A} UDS_000{ D} LDS_000{ D} - : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} - : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} - : AHIGH_24_{ C}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} - :AMIGA_BUS_ENABLE_HIGH{ D} A_0_{ G} SIZE_1_{ H} - : RW_000{ H} BGACK_030{ H} SIZE_0_{ G} - : RW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} - :inst_AS_030_000_SYNC{ B}inst_BGACK_030_INT_D{ H} CYCLE_DMA_0_{ A} - : CYCLE_DMA_1_{ A} - SIZE_0_{ H}:inst_LDS_000_INT{ F} - RN_SIZE_0_{ H}: SIZE_0_{ G} - RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +RN_BGACK_030{ I}: AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} + : AHIGH_24_{ C} AHIGH_31_{ B} AS_030{ H} + : AS_000{ E} DS_030{ A} UDS_000{ D} + : LDS_000{ D} DSACK1{ H}AMIGA_BUS_DATA_DIR{ E} + :AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} AHIGH_30_{ B} + : AHIGH_29_{ B} AHIGH_28_{ C} SIZE_1_{ H} + : RW_000{ H} BGACK_030{ H} A_0_{ G} + : VMA{ D} RW{ G} SIZE_0_{ G} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}inst_AS_030_000_SYNC{ F} + :inst_BGACK_030_INT_D{ E} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ B} + A_0_{ H}:inst_UDS_000_INT{ B}inst_LDS_000_INT{ G} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C} - RN_RW{ H}: RW{ G} + SIZE_0_{ H}:inst_LDS_000_INT{ G} + cpu_est_0_{ H}: VMA{ D} cpu_est_0_{ G} cpu_est_1_{ D} + : cpu_est_2_{ D} cpu_est_3_{ A} SM_AMIGA_3_{ A} + : SM_AMIGA_2_{ A} cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} cpu_est_3_{ D} SM_AMIGA_3_{ C} - : SM_AMIGA_2_{ C} + : cpu_est_2_{ D} cpu_est_3_{ A} SM_AMIGA_3_{ A} + : SM_AMIGA_2_{ A} cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_2_{ D} - : cpu_est_3_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} - cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_3_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} - cpu_est_0_{ H}: VMA{ D} cpu_est_1_{ D} cpu_est_2_{ D} - : cpu_est_3_{ D} cpu_est_0_{ G} SM_AMIGA_3_{ C} - : SM_AMIGA_2_{ C} -inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F} -inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} -inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D}inst_AS_030_000_SYNC{ B} - : CIIN_0{ E} -inst_AS_030_000_SYNC{ C}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ B} SM_AMIGA_6_{ F} + : cpu_est_3_{ A} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + cpu_est_3_{ B}: E{ G} VMA{ D} cpu_est_1_{ D} + : cpu_est_3_{ A} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}:AMIGA_BUS_ENABLE_HIGH{ D} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C} +inst_AS_030_D0{ F}: CIIN{ E} BG_000{ D} inst_AS_030_D1{ F} + : N_60{ E} +inst_AS_030_D1{ G}: inst_AS_030_D1{ F}inst_AS_030_000_SYNC{ F} +inst_AS_030_000_SYNC{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} : SM_AMIGA_i_7_{ F} -inst_BGACK_030_INT_D{ I}: A_0_{ G} SIZE_1_{ H} SIZE_0_{ G} - : RW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ F} - :inst_AS_030_000_SYNC{ B} -inst_AS_000_DMA{ B}: AS_030{ H} DTACK{ D}inst_AS_000_DMA{ A} - : CLK_030_PE_1_{ A} CLK_030_PE_0_{ A} -inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A} - inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} -CLK_000_D_3_{ G}: CLK_000_D_4_{ C} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} -inst_DTACK_D0{ C}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} -inst_RESET_OUT{ H}: AS_030{ H} AS_000{ E} DS_030{ A} - : UDS_000{ D} LDS_000{ D} A_0_{ G} - : RW_000{ H} RW{ G} inst_RESET_OUT{ G} -CLK_030_PE_1_{ B}:inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} CLK_030_PE_0_{ A} -inst_AMIGA_DS{ D}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} - : CLK_030_PE_0_{ A} +inst_AS_000_DMA{ D}: AS_030{ H}inst_AS_000_DMA{ C} +inst_DS_000_DMA{ D}: DS_030{ A}inst_DS_000_DMA{ C} + inst_VPA_D{ H}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +CLK_000_D_3_{ G}: CLK_000_D_4_{ F} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} +inst_DTACK_D0{ G}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +inst_AMIGA_DS{ I}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} VMA{ D} - : cpu_est_1_{ D} cpu_est_2_{ D} cpu_est_3_{ D} - : cpu_est_0_{ G} inst_RESET_OUT{ G} CLK_000_D_2_{ H} - :inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} SM_AMIGA_4_{ A} - : SM_AMIGA_1_{ F} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ A} - : CYCLE_DMA_1_{ A} RST_DLY_0_{ G} RST_DLY_1_{ G} - : RST_DLY_2_{ G}inst_DSACK1_INT{ A}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ G} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} - : SM_AMIGA_i_7_{ F} + : cpu_est_0_{ G} cpu_est_1_{ D} cpu_est_2_{ D} + : cpu_est_3_{ A} CLK_000_D_2_{ H}inst_DS_000_ENABLE{ C} + : SM_AMIGA_6_{ F} SM_AMIGA_4_{ G} SM_AMIGA_1_{ A} + : SM_AMIGA_0_{ A} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ B} + :inst_DSACK1_INT{ G}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} + : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} SM_AMIGA_i_7_{ F} CLK_000_D_0_{ E}: RW_000{ H} BG_000{ D} BGACK_030{ H} - : VMA{ D} cpu_est_1_{ D} cpu_est_2_{ D} - : cpu_est_3_{ D} cpu_est_0_{ G} inst_RESET_OUT{ G} - : CLK_000_D_1_{ H}inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} - : SM_AMIGA_4_{ A} SM_AMIGA_1_{ F} SM_AMIGA_0_{ A} - : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} RST_DLY_0_{ G} - : RST_DLY_1_{ G} RST_DLY_2_{ G}inst_DSACK1_INT{ A} - :inst_AS_000_INT{ C} SM_AMIGA_5_{ G} SM_AMIGA_3_{ C} - : SM_AMIGA_2_{ C} SM_AMIGA_i_7_{ F} -inst_CLK_OUT_PRE_50{ H}:inst_CLK_OUT_PRE_50{ G}inst_CLK_OUT_PRE_D{ E} -inst_CLK_OUT_PRE_D{ F}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} - : CLK_030_PE_0_{ A} CLK_OUT_INTreg{ D} - IPL_D0_0_{ C}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} - IPL_D0_1_{ C}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} - IPL_D0_2_{ C}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} -CLK_000_D_2_{ I}: CLK_000_D_3_{ F} -CLK_000_D_4_{ D}: SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} -inst_LDS_000_INT{ G}: LDS_000{ D}inst_LDS_000_INT{ F} -inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C} -inst_UDS_000_INT{ G}: UDS_000{ D}inst_UDS_000_INT{ F} -SM_AMIGA_6_{ G}: RW_000{ H}inst_LDS_000_INT{ F}inst_DS_000_ENABLE{ C} - :inst_UDS_000_INT{ F} SM_AMIGA_6_{ F}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ G} -SM_AMIGA_4_{ B}:inst_DS_000_ENABLE{ C} SM_AMIGA_4_{ A} SM_AMIGA_3_{ C} -SM_AMIGA_1_{ G}: SM_AMIGA_1_{ F} SM_AMIGA_0_{ A}inst_DSACK1_INT{ A} -SM_AMIGA_0_{ B}: RW_000{ H} SM_AMIGA_0_{ A} SM_AMIGA_i_7_{ F} -CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} - : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} CLK_030_PE_0_{ A} -CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} - : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} CLK_030_PE_0_{ A} -CLK_030_PE_0_{ B}:inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} CLK_030_PE_0_{ A} - RST_DLY_0_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G} - : RST_DLY_2_{ G} - RST_DLY_1_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G} - : RST_DLY_2_{ G} - RST_DLY_2_{ H}: inst_RESET_OUT{ G} RST_DLY_0_{ G} RST_DLY_1_{ G} - : RST_DLY_2_{ G} -inst_DSACK1_INT{ B}: DSACK1{ H}inst_DSACK1_INT{ A} -inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} -SM_AMIGA_5_{ H}: SM_AMIGA_4_{ A} SM_AMIGA_5_{ G} -SM_AMIGA_3_{ D}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} -SM_AMIGA_2_{ D}: SM_AMIGA_1_{ F} SM_AMIGA_2_{ C} -SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ B} SM_AMIGA_6_{ F} + : VMA{ D} cpu_est_0_{ G} cpu_est_1_{ D} + : cpu_est_2_{ D} cpu_est_3_{ A} CLK_000_D_1_{ H} + :inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} SM_AMIGA_4_{ G} + : SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ B} + : CYCLE_DMA_1_{ B}inst_DSACK1_INT{ G}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ F} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} : SM_AMIGA_i_7_{ F} -CLK_OUT_INTreg{ E}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_AS_000_DMA{ A} - :inst_DS_000_DMA{ A} CLK_030_PE_1_{ A} CLK_030_PE_0_{ A} - CIIN_0{ F}: CIIN{ E} +inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_D{ E} +inst_CLK_OUT_PRE_D{ F}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CLK_OUT_INTreg{ A} + IPL_D0_0_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +CLK_000_D_2_{ I}: CLK_000_D_3_{ F} +CLK_000_D_4_{ G}: SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} +inst_UDS_000_INT{ C}: UDS_000{ D}inst_UDS_000_INT{ B} +inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C} +inst_LDS_000_INT{ H}: LDS_000{ D}inst_LDS_000_INT{ G} +inst_BGACK_030_INT_D{ F}:inst_AS_030_000_SYNC{ F} +SM_AMIGA_6_{ G}: RW_000{ H}inst_UDS_000_INT{ B}inst_DS_000_ENABLE{ C} + :inst_LDS_000_INT{ G} SM_AMIGA_6_{ F}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ F} +SM_AMIGA_4_{ H}:inst_DS_000_ENABLE{ C} SM_AMIGA_4_{ G} SM_AMIGA_3_{ A} +SM_AMIGA_1_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_0_{ A}inst_DSACK1_INT{ G} +SM_AMIGA_0_{ B}: RW_000{ H} SM_AMIGA_0_{ A} SM_AMIGA_i_7_{ F} +CYCLE_DMA_0_{ C}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ B} + : CYCLE_DMA_1_{ B} +CYCLE_DMA_1_{ C}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ B} + : CYCLE_DMA_1_{ B} +inst_DSACK1_INT{ H}: DSACK1{ H}inst_DSACK1_INT{ G} +inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} +SM_AMIGA_5_{ G}: SM_AMIGA_4_{ G} SM_AMIGA_5_{ F} +SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +SM_AMIGA_2_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_2_{ A} +CLK_OUT_INTreg{ B}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_AS_000_DMA{ C} + :inst_DS_000_DMA{ C} +SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_i_7_{ F} + N_60{ F}: CIIN{ E} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -664,15 +622,15 @@ Equations : +-----+-----+-----+-----+------------------------ | | | | | DS_030 | | | | | AVEC -| * | S | BS | BR | inst_AS_000_DMA +| * | S | BS | BR | cpu_est_3_ | * | S | BS | BR | SM_AMIGA_0_ -| * | S | BS | BR | SM_AMIGA_4_ -| * | S | BS | BR | inst_DSACK1_INT -| * | S | BS | BR | CLK_030_PE_0_ -| * | S | BS | BR | inst_DS_000_DMA -| * | S | BS | BR | CLK_030_PE_1_ -| * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | CYCLE_DMA_1_ +| * | S | BS | BR | CLK_OUT_INTreg +| * | S | BS | BR | SM_AMIGA_1_ +| * | S | BS | BR | SM_AMIGA_2_ +| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | IPL_D0_2_ +| * | S | BS | BR | IPL_D0_0_ +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH | | | | | A_DECODE_19_ | | | | | A_DECODE_16_ | | | | | A_DECODE_18_ @@ -695,15 +653,12 @@ Equations : | * | S | BS | BR | IPL_030_0_ | * | S | BS | BR | IPL_030_1_ | | | | | CLK_EXP -| * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | RN_IPL_030_2_ +| * | S | BS | BR | CYCLE_DMA_0_ +| * | S | BS | BR | CYCLE_DMA_1_ +| * | S | BS | BR | inst_UDS_000_INT | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ -| * | S | BS | BR | IPL_D0_2_ -| * | S | BS | BR | IPL_D0_1_ -| * | S | BS | BR | IPL_D0_0_ -| * | S | BS | BR | inst_DTACK_D0 -| | | | | RESET +| * | S | BS | BR | RN_IPL_030_2_ Block C @@ -719,12 +674,11 @@ Equations : | | | | | AHIGH_27_ | | | | | AHIGH_28_ | | | | | AMIGA_BUS_ENABLE_LOW -| * | S | BS | BR | SM_AMIGA_2_ +| * | S | BS | BR | inst_DS_000_DMA +| * | S | BS | BR | inst_AS_000_DMA | * | S | BS | BR | inst_DS_000_ENABLE | * | S | BS | BR | inst_AS_000_INT -| * | S | BS | BR | SM_AMIGA_3_ -| * | S | BS | BR | inst_AMIGA_DS -| * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | | | | | BG_030 @@ -737,19 +691,18 @@ Equations : +-----+-----+-----+-----+------------------------ | | | | | UDS_000 | | | | | LDS_000 -| | | | | DTACK | * | S | BS | BR | VMA | | | | | AMIGA_BUS_ENABLE_HIGH | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE | * | S | BS | BR | CLK_000_D_0_ -| * | S | BS | BR | cpu_est_3_ | * | S | BS | BR | cpu_est_1_ -| * | S | BS | BR | CLK_OUT_INTreg | * | S | BS | BR | cpu_est_2_ | * | S | BS | BR | RN_VMA | * | S | BS | BR | RN_BG_000 +| * | S | BS | BR | IPL_D0_1_ | | | | | BGACK_000 +| | | | | DTACK Block E @@ -763,8 +716,10 @@ Equations : | | | | | BERR | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN +| * | S | BS | BR | inst_AS_030_D0 | * | S | BS | BR | inst_CLK_OUT_PRE_D -| | | | | CIIN_0 +| | | | | N_60 +| * | S | BS | BR | inst_BGACK_030_INT_D Block F @@ -775,14 +730,13 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BS | BR | SM_AMIGA_i_7_ -| * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | inst_LDS_000_INT -| * | S | BS | BR | inst_UDS_000_INT -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BR | inst_AS_030_D1 +| * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | inst_DTACK_D0 | * | S | BS | BR | CLK_000_D_3_ -| * | S | BS | BR | inst_VPA_D | | | | | A_DECODE_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -797,21 +751,16 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | A_0_ | * | S | BS | BR | RW | * | S | BS | BR | SIZE_0_ -| * | S | BS | BR | A_0_ | | | | | E | | | | | CLK_DIV_OUT -| * | S | BS | BR | inst_RESET_OUT +| * | S | BS | BR | SM_AMIGA_4_ | * | S | BS | BR | cpu_est_0_ -| * | S | BS | BR | SM_AMIGA_5_ -| * | S | BS | BR | inst_CLK_OUT_PRE_50 -| * | S | BS | BR | RST_DLY_0_ -| * | S | BS | BR | RN_SIZE_0_ -| * | S | BS | BR | RN_A_0_ -| * | S | BS | BR | RN_RW -| * | S | BS | BR | RST_DLY_2_ -| * | S | BS | BR | RST_DLY_1_ +| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | inst_DSACK1_INT +| * | S | BS | BR | inst_VPA_D | | | | | IPL_2_ | | | | | IPL_0_ @@ -831,10 +780,9 @@ Equations : | | | | | FPU_CS | * | S | BS | BR | RN_BGACK_030 | * | S | BS | BR | CLK_000_D_1_ -| * | S | BS | BR | inst_BGACK_030_INT_D -| * | S | BS | BR | inst_AS_030_D0 +| * | S | BS | BR | inst_CLK_OUT_PRE_50 | * | S | BS | BR | RN_RW_000 -| * | S | BS | BR | RN_SIZE_1_ +| * | S | BS | BR | inst_AMIGA_DS | * | S | BS | BR | CLK_000_D_2_ | | | | | A_DECODE_23_ | | | | | A_DECODE_22_ @@ -854,23 +802,23 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 RST pin 86 mx A17 ... ... -mx A1 CLK_000_D_0_ mcell D13 mx A18 inst_DSACK1_INT mcell A5 -mx A2 CLK_030_PE_0_ mcell A9 mx A19 AS_030 pin 82 -mx A3 inst_AS_000_DMA mcell A8 mx A20 SM_AMIGA_1_ mcell F8 -mx A4 CLK_030 pin 64 mx A21 ... ... -mx A5 nEXP_SPACE pin 14 mx A22 CLK_030_PE_1_ mcell A2 -mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4 -mx A7 ... ... mx A24 ... ... -mx A8 inst_AMIGA_DS mcell C10 mx A25 inst_DS_000_DMA mcell A13 -mx A9 SM_AMIGA_4_ mcell A1 mx A26 AS_000 pin 42 -mx A10 CYCLE_DMA_0_ mcell A6 mx A27 ... ... +mx A0 IPL_0_ pin 67 mx A17 BERR pin 41 +mx A1 inst_DTACK_D0 mcell F9 mx A18 SM_AMIGA_1_ mcell A5 +mx A2 AS_000 pin 42 mx A19 SM_AMIGA_2_ mcell A9 +mx A3 A_1_ pin 60 mx A20 RN_BGACK_030 mcell H4 +mx A4 IPL_2_ pin 68 mx A21 RST pin 86 +mx A5 inst_VPA_D mcell G6 mx A22 SM_AMIGA_4_ mcell G5 +mx A6 ... ... mx A23 ... ... +mx A7 CLK_000_D_0_ mcell D9 mx A24 ... ... +mx A8 ... ... mx A25 SM_AMIGA_3_ mcell A13 +mx A9 SM_AMIGA_0_ mcell A12 mx A26 RN_VMA mcell D0 +mx A10 cpu_est_0_ mcell G9 mx A27 CLK_000_D_1_ mcell H5 mx A11 ... ... mx A28 ... ... -mx A12 SM_AMIGA_5_ mcell G13 mx A29 ... ... -mx A13 CLK_000_D_1_ mcell H5 mx A30 CLK_OUT_INTreg mcell D10 -mx A14 CYCLE_DMA_1_ mcell A10 mx A31 ... ... -mx A15 SM_AMIGA_0_ mcell A12 mx A32 inst_RESET_OUT mcell G5 -mx A16inst_CLK_OUT_PRE_D mcell E8 +mx A12 ... ... mx A29 cpu_est_1_ mcell D13 +mx A13 inst_DS_000_DMA mcell C9 mx A30 cpu_est_3_ mcell A8 +mx A14inst_CLK_OUT_PRE_D mcell E5 mx A31 ... ... +mx A15 ... ... mx A32 ... ... +mx A16 cpu_est_2_ mcell D2 ---------------------------------------------------------------------------- @@ -878,22 +826,22 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 RN_BGACK_030 mcell H4 mx B17 FC_0_ pin 57 -mx B1 FC_1_ pin 58 mx B18 IPL_D0_2_ mcell B2 -mx B2 RESET pin 3 mx B19 AS_030 pin 82 -mx B3 IPL_1_ pin 56 mx B20 CLK_OUT_INTreg mcell D10 -mx B4 A_DECODE_18_ pin 95 mx B21 RST pin 86 -mx B5 nEXP_SPACE pin 14 mx B22 IPL_2_ pin 68 -mx B6 RN_IPL_030_1_ mcell B9 mx B23 IPL_D0_1_ mcell B6 -mx B7inst_BGACK_030_INT_D mcell H13 mx B24 IPL_D0_0_ mcell B10 -mx B8 A_DECODE_17_ pin 59 mx B25 ... ... -mx B9 DTACK pin 30 mx B26 ... ... -mx B10inst_AS_030_000_SYNC mcell B13 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 A_DECODE_16_ pin 96 mx B28 RN_IPL_030_0_ mcell B5 -mx B12 A_DECODE_19_ pin 97 mx B29 SM_AMIGA_i_7_ mcell F4 -mx B13 ... ... mx B30 ... ... -mx B14 inst_AS_030_D0 mcell H2 mx B31 ... ... -mx B15 ... ... mx B32 ... ... +mx B0 A_0_ pin 69 mx B17 ... ... +mx B1 ... ... mx B18 CYCLE_DMA_1_ mcell B2 +mx B2inst_UDS_000_INT mcell B6 mx B19 ... ... +mx B3 IPL_1_ pin 56 mx B20 RN_BGACK_030 mcell H4 +mx B4 IPL_D0_1_ mcell D6 mx B21 RST pin 86 +mx B5 SM_AMIGA_6_ mcell F0 mx B22 IPL_2_ pin 68 +mx B6 RN_IPL_030_1_ mcell B9 mx B23 ... ... +mx B7 CLK_000_D_0_ mcell D9 mx B24 ... ... +mx B8 ... ... mx B25 IPL_D0_2_ mcell A2 +mx B9 CLK_OUT_INTreg mcell A1 mx B26 AS_000 pin 42 +mx B10 CYCLE_DMA_0_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 RN_IPL_030_0_ mcell B5 +mx B12 ... ... mx B29 ... ... +mx B13 CLK_000_D_1_ mcell H5 mx B30 ... ... +mx B14 ... ... mx B31 ... ... +mx B15 IPL_D0_0_ mcell A6 mx B32 ... ... mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -902,23 +850,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0inst_DS_000_ENABLE mcell C13 mx C17 BERR pin 41 -mx C1 CLK_000_D_0_ mcell D13 mx C18 SM_AMIGA_3_ mcell C6 -mx C2 RESET pin 3 mx C19 AS_030 pin 82 -mx C3 SM_AMIGA_2_ mcell C9 mx C20 inst_DTACK_D0 mcell B14 -mx C4 cpu_est_1_ mcell D6 mx C21 RST pin 86 -mx C5 nEXP_SPACE pin 14 mx C22 inst_AS_000_INT mcell C2 -mx C6 CLK_000_D_3_ mcell F13 mx C23 RN_BGACK_030 mcell H4 -mx C7 ... ... mx C24 LDS_000 pin 31 -mx C8 UDS_000 pin 32 mx C25 SM_AMIGA_6_ mcell F0 -mx C9inst_AMIGA_BUS_ENABLE_DMA_LOW mcell F5 mx C26 ... ... -mx C10 cpu_est_2_ mcell D14 mx C27 cpu_est_0_ mcell G9 -mx C11 RW pin 71 mx C28 ... ... -mx C12 SM_AMIGA_4_ mcell A1 mx C29 ... ... -mx C13 CLK_000_D_1_ mcell H5 mx C30 ... ... -mx C14 RN_VMA mcell D4 mx C31 ... ... -mx C15 inst_VPA_D mcell F2 mx C32 ... ... -mx C16 cpu_est_3_ mcell D2 +mx C0 RST pin 86 mx C17 ... ... +mx C1 ... ... mx C18 ... ... +mx C2inst_DS_000_ENABLE mcell C2 mx C19 AS_030 pin 82 +mx C3 A_1_ pin 60 mx C20 RN_BGACK_030 mcell H4 +mx C4 inst_AMIGA_DS mcell H2 mx C21 CYCLE_DMA_0_ mcell B13 +mx C5 SM_AMIGA_6_ mcell F0 mx C22 SM_AMIGA_4_ mcell G5 +mx C6 RW_000 pin 80 mx C23 ... ... +mx C7 CLK_000_D_0_ mcell D9 mx C24 ... ... +mx C8inst_AMIGA_BUS_ENABLE_DMA_LOW mcell C10 mx C25 RW pin 71 +mx C9 inst_AS_000_INT mcell C6 mx C26 ... ... +mx C10 CYCLE_DMA_1_ mcell B2 mx C27 CLK_000_D_1_ mcell H5 +mx C11 inst_AS_000_DMA mcell C13 mx C28 ... ... +mx C12 CLK_OUT_INTreg mcell A1 mx C29 ... ... +mx C13 inst_DS_000_DMA mcell C9 mx C30 ... ... +mx C14inst_CLK_OUT_PRE_D mcell E5 mx C31 ... ... +mx C15 ... ... mx C32 ... ... +mx C16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -926,23 +874,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RST pin 86 mx D17inst_LDS_000_INT mcell F12 -mx D1inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell F9 mx D18 inst_AS_000_DMA mcell A8 +mx D0 RST pin 86 mx D17 ... ... +mx D1 RN_VMA mcell D0 mx D18 cpu_est_3_ mcell A8 mx D2 RN_BG_000 mcell D1 mx D19 AS_030 pin 82 -mx D3 cpu_est_3_ mcell D2 mx D20 RN_BGACK_030 mcell H4 -mx D4 BG_030 pin 21 mx D21inst_AS_030_000_SYNC mcell B13 -mx D5 nEXP_SPACE pin 14 mx D22 inst_RESET_OUT mcell G5 -mx D6 ... ... mx D23 ... ... -mx D7 ... ... mx D24 cpu_est_2_ mcell D14 -mx D8inst_CLK_OUT_PRE_D mcell E8 mx D25 ... ... -mx D9 inst_VPA_D mcell F2 mx D26 ... ... -mx D10 RN_VMA mcell D4 mx D27 ... ... -mx D11inst_DS_000_ENABLE mcell C13 mx D28 inst_AS_030_D0 mcell H2 -mx D12 cpu_est_0_ mcell G9 mx D29 CLK_000_D_0_ mcell D13 -mx D13 CLK_000_D_1_ mcell H5 mx D30 ... ... -mx D14 CLK_000 pin 11 mx D31 ... ... -mx D15inst_UDS_000_INT mcell F1 mx D32 ... ... -mx D16 cpu_est_1_ mcell D6 +mx D3 CLK_000 pin 11 mx D20 RN_BGACK_030 mcell H4 +mx D4 BG_030 pin 21 mx D21 IPL_1_ pin 56 +mx D5 nEXP_SPACE pin 14 mx D22inst_DS_000_ENABLE mcell C2 +mx D6 ... ... mx D23 inst_VPA_D mcell G6 +mx D7 CLK_000_D_0_ mcell D9 mx D24 ... ... +mx D8inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell A10 mx D25 ... ... +mx D9inst_LDS_000_INT mcell G13 mx D26 ... ... +mx D10inst_AS_030_000_SYNC mcell F4 mx D27 ... ... +mx D11inst_UDS_000_INT mcell B6 mx D28 ... ... +mx D12 cpu_est_0_ mcell G9 mx D29 cpu_est_1_ mcell D13 +mx D13 CLK_000_D_1_ mcell H5 mx D30 inst_AS_030_D0 mcell E8 +mx D14 ... ... mx D31 ... ... +mx D15 ... ... mx D32 ... ... +mx D16 cpu_est_2_ mcell D2 ---------------------------------------------------------------------------- @@ -950,23 +898,23 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 RN_BGACK_030 mcell H4 mx E17 A_DECODE_18_ pin 95 -mx E1 FC_1_ pin 58 mx E18 A_DECODE_23_ pin 85 -mx E2 inst_AS_000_INT mcell C2 mx E19 AHIGH_30_ pin 5 -mx E3 A_DECODE_20_ pin 93 mx E20 A_DECODE_22_ pin 84 -mx E4 BGACK_000 pin 28 mx E21 AHIGH_27_ pin 16 -mx E5 AHIGH_24_ pin 19 mx E22 AHIGH_25_ pin 18 -mx E6 RW_000 pin 80 mx E23inst_CLK_OUT_PRE_50 mcell G2 +mx E0 RST pin 86 mx E17 A_DECODE_18_ pin 95 +mx E1 FC_1_ pin 58 mx E18 BGACK_000 pin 28 +mx E2 AS_000 pin 42 mx E19inst_CLK_OUT_PRE_50 mcell H13 +mx E3 AHIGH_27_ pin 16 mx E20 AHIGH_24_ pin 19 +mx E4 AHIGH_29_ pin 6 mx E21 RW_000 pin 80 +mx E5 nEXP_SPACE pin 14 mx E22 AHIGH_25_ pin 18 +mx E6 A_DECODE_16_ pin 96 mx E23 RN_BGACK_030 mcell H4 mx E7 AHIGH_28_ pin 15 mx E24 FC_0_ pin 57 mx E8 FPU_SENSE pin 91 mx E25 AHIGH_31_ pin 4 mx E9 AS_030 pin 82 mx E26 AHIGH_26_ pin 17 -mx E10 ... ... mx E27 A_DECODE_17_ pin 59 -mx E11 A_DECODE_16_ pin 96 mx E28 inst_AS_030_D0 mcell H2 -mx E12 A_DECODE_19_ pin 97 mx E29 ... ... -mx E13 AHIGH_29_ pin 6 mx E30 ... ... -mx E14 CIIN_0 mcell E5 mx E31 A_DECODE_21_ pin 94 -mx E15 nEXP_SPACE pin 14 mx E32 inst_RESET_OUT mcell G5 -mx E16 AS_000 pin 42 +mx E10 ... ... mx E27 inst_AS_000_INT mcell C6 +mx E11 A_DECODE_22_ pin 84 mx E28 AHIGH_30_ pin 5 +mx E12 A_DECODE_19_ pin 97 mx E29 A_DECODE_20_ pin 93 +mx E13 A_DECODE_17_ pin 59 mx E30 ... ... +mx E14 N_60 mcell E9 mx E31 ... ... +mx E15 A_DECODE_21_ pin 94 mx E32 A_DECODE_23_ pin 85 +mx E16 inst_AS_030_D0 mcell E8 ---------------------------------------------------------------------------- @@ -974,23 +922,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0 SIZE_0_ pin 70 mx F17inst_LDS_000_INT mcell F12 -mx F1 CLK_000_D_0_ mcell D13 mx F18inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell F9 -mx F2 SM_AMIGA_1_ mcell F8 mx F19inst_BGACK_030_INT_D mcell H13 -mx F3 SM_AMIGA_2_ mcell C9 mx F20 RN_BGACK_030 mcell H4 -mx F4 CLK_000_D_1_ mcell H5 mx F21inst_AS_030_000_SYNC mcell B13 +mx F0 RST pin 86 mx F17 SM_AMIGA_5_ mcell F12 +mx F1 FC_1_ pin 58 mx F18 ... ... +mx F2inst_BGACK_030_INT_D mcell E13 mx F19 AS_030 pin 82 +mx F3 ... ... mx F20 SM_AMIGA_i_7_ mcell F8 +mx F4 A_DECODE_18_ pin 95 mx F21 CLK_000_D_2_ mcell H6 mx F5 nEXP_SPACE pin 14 mx F22 ... ... -mx F6 CLK_000_D_3_ mcell F13 mx F23 ... ... -mx F7 CLK_000_D_4_ mcell C14 mx F24 RST pin 86 -mx F8 ... ... mx F25 SM_AMIGA_6_ mcell F0 -mx F9 SM_AMIGA_0_ mcell A12 mx F26 ... ... -mx F10inst_UDS_000_INT mcell F1 mx F27 SIZE_1_ pin 79 -mx F11 A_1_ pin 60 mx F28 ... ... -mx F12 ... ... mx F29 SM_AMIGA_i_7_ mcell F4 -mx F13 VPA pin 36 mx F30 CLK_000_D_2_ mcell H6 -mx F14inst_AMIGA_BUS_ENABLE_DMA_LOW mcell F5 mx F31 ... ... -mx F15 A_0_ pin 69 mx F32 ... ... -mx F16 ... ... +mx F6 FC_0_ pin 57 mx F23 RN_BGACK_030 mcell H4 +mx F7 CLK_000_D_0_ mcell D9 mx F24 SM_AMIGA_0_ mcell A12 +mx F8 A_DECODE_17_ pin 59 mx F25 SM_AMIGA_6_ mcell F0 +mx F9 DTACK pin 30 mx F26 ... ... +mx F10 inst_AS_030_D1 mcell F1 mx F27 ... ... +mx F11 A_DECODE_16_ pin 96 mx F28 ... ... +mx F12 A_DECODE_19_ pin 97 mx F29inst_AS_030_000_SYNC mcell F4 +mx F13 CLK_000_D_1_ mcell H5 mx F30 ... ... +mx F14 CLK_000_D_4_ mcell F5 mx F31 ... ... +mx F15 CLK_000_D_3_ mcell F13 mx F32 ... ... +mx F16 inst_AS_030_D0 mcell E8 ---------------------------------------------------------------------------- @@ -998,23 +946,23 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 LDS_000 pin 31 mx G17 RN_RW mcell G0 -mx G1 CLK_000_D_0_ mcell D13 mx G18 ... ... -mx G2 CLK_OUT_INTreg mcell D10 mx G19inst_BGACK_030_INT_D mcell H13 -mx G3 cpu_est_3_ mcell D2 mx G20 RN_BGACK_030 mcell H4 -mx G4inst_CLK_OUT_PRE_50 mcell G2 mx G21 RST pin 86 -mx G5 nEXP_SPACE pin 14 mx G22 RST_DLY_2_ mcell G10 -mx G6 RW_000 pin 80 mx G23 RST_DLY_0_ mcell G6 -mx G7 RN_SIZE_0_ mcell G12 mx G24 cpu_est_2_ mcell D14 -mx G8 UDS_000 pin 32 mx G25 SM_AMIGA_6_ mcell F0 -mx G9 SM_AMIGA_5_ mcell G13 mx G26 ... ... -mx G10 RST_DLY_1_ mcell G14 mx G27 CLK_000_D_1_ mcell H5 -mx G11 ... ... mx G28 ... ... -mx G12 cpu_est_0_ mcell G9 mx G29 ... ... -mx G13 RN_A_0_ mcell G8 mx G30 ... ... -mx G14 ... ... mx G31 ... ... -mx G15 ... ... mx G32 inst_RESET_OUT mcell G5 -mx G16 cpu_est_1_ mcell D6 +mx G0 RST pin 86 mx G17 ... ... +mx G1 SM_AMIGA_5_ mcell F12 mx G18 cpu_est_3_ mcell A8 +mx G2 SM_AMIGA_1_ mcell A5 mx G19 AS_030 pin 82 +mx G3 cpu_est_2_ mcell D2 mx G20 RN_BGACK_030 mcell H4 +mx G4 inst_DSACK1_INT mcell G2 mx G21 cpu_est_1_ mcell D13 +mx G5 SM_AMIGA_6_ mcell F0 mx G22 SM_AMIGA_4_ mcell G5 +mx G6 SIZE_1_ pin 79 mx G23 ... ... +mx G7 CLK_000_D_0_ mcell D9 mx G24 LDS_000 pin 31 +mx G8 UDS_000 pin 32 mx G25 ... ... +mx G9inst_LDS_000_INT mcell G13 mx G26 ... ... +mx G10 VPA pin 36 mx G27 cpu_est_0_ mcell G9 +mx G11 ... ... mx G28 RW_000 pin 80 +mx G12 CLK_OUT_INTreg mcell A1 mx G29 ... ... +mx G13 CLK_000_D_1_ mcell H5 mx G30 ... ... +mx G14 SIZE_0_ pin 70 mx G31 ... ... +mx G15 A_0_ pin 69 mx G32 ... ... +mx G16 ... ... ---------------------------------------------------------------------------- @@ -1024,20 +972,20 @@ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RST pin 86 mx H17 FC_0_ pin 57 mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 -mx H2 inst_DSACK1_INT mcell A5 mx H19 FPU_SENSE pin 91 -mx H3 inst_AS_000_DMA mcell A8 mx H20 RN_BGACK_030 mcell H4 -mx H4 A_DECODE_18_ pin 95 mx H21 CLK_000_D_0_ mcell D13 -mx H5 nEXP_SPACE pin 14 mx H22 inst_RESET_OUT mcell G5 -mx H6 A_DECODE_16_ pin 96 mx H23 RN_RW_000 mcell H0 -mx H7inst_BGACK_030_INT_D mcell H13 mx H24 LDS_000 pin 31 -mx H8 UDS_000 pin 32 mx H25 SM_AMIGA_6_ mcell F0 -mx H9 AS_030 pin 82 mx H26 ... ... -mx H10 SM_AMIGA_i_7_ mcell F4 mx H27 CLK_000_D_1_ mcell H5 -mx H11 RW pin 71 mx H28 ... ... -mx H12 A_DECODE_19_ pin 97 mx H29 RN_SIZE_1_ mcell H12 -mx H13 A_DECODE_17_ pin 59 mx H30 ... ... -mx H14 ... ... mx H31 ... ... -mx H15 SM_AMIGA_0_ mcell A12 mx H32 ... ... +mx H2 SM_AMIGA_i_7_ mcell F8 mx H19 FPU_SENSE pin 91 +mx H3 ... ... mx H20 RN_BGACK_030 mcell H4 +mx H4 A_DECODE_18_ pin 95 mx H21 ... ... +mx H5 SM_AMIGA_6_ mcell F0 mx H22 ... ... +mx H6 A_DECODE_19_ pin 97 mx H23 RN_RW_000 mcell H0 +mx H7inst_CLK_OUT_PRE_50 mcell H13 mx H24 LDS_000 pin 31 +mx H8 RW pin 71 mx H25 CLK_000_D_0_ mcell D9 +mx H9 SM_AMIGA_0_ mcell A12 mx H26 ... ... +mx H10 ... ... mx H27 CLK_000_D_1_ mcell H5 +mx H11 A_DECODE_16_ pin 96 mx H28 ... ... +mx H12 UDS_000 pin 32 mx H29 ... ... +mx H13 A_DECODE_17_ pin 59 mx H30 inst_AS_000_DMA mcell C13 +mx H14 ... ... mx H31 inst_DSACK1_INT mcell G2 +mx H15 nEXP_SPACE pin 14 mx H32 AS_030 pin 82 mx H16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -1053,14 +1001,22 @@ PostFit_Equations P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- + 0 0 1 Pin AHIGH_27_ + 1 1 1 Pin AHIGH_27_.OE + 0 0 1 Pin AHIGH_26_ + 1 1 1 Pin AHIGH_26_.OE + 0 0 1 Pin AHIGH_25_ + 1 1 1 Pin AHIGH_25_.OE + 0 0 1 Pin AHIGH_24_ + 1 1 1 Pin AHIGH_24_.OE 0 0 1 Pin AHIGH_31_ - 1 3 1 Pin AHIGH_31_.OE + 1 1 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- - 1 3 1 Pin AS_030.OE + 1 1 1 Pin AS_030.OE 1 2 1 Pin AS_000- 1 2 1 Pin AS_000.OE 1 2 1 Pin DS_030- - 1 3 1 Pin DS_030.OE + 1 1 1 Pin DS_030.OE 1 2 1 Pin UDS_000- 1 2 1 Pin UDS_000.OE 1 2 1 Pin LDS_000- @@ -1071,41 +1027,24 @@ PostFit_Equations 1 1 1 Pin CLK_EXP 1 9 1 Pin FPU_CS- 1 2 1 Pin DSACK1- - 1 1 1 Pin DSACK1.OE - 0 0 1 Pin DTACK - 1 1 1 Pin DTACK.OE + 1 2 1 Pin DSACK1.OE 1 0 1 Pin AVEC 2 3 1 Pin E - 0 0 1 Pin AHIGH_30_ - 1 3 1 Pin AHIGH_30_.OE - 0 0 1 Pin AHIGH_29_ - 1 3 1 Pin AHIGH_29_.OE - 0 0 1 Pin AHIGH_28_ - 1 3 1 Pin AHIGH_28_.OE - 0 0 1 Pin AHIGH_27_ - 1 3 1 Pin AHIGH_27_.OE - 0 0 1 Pin AHIGH_26_ - 1 3 1 Pin AHIGH_26_.OE - 0 0 1 Pin AHIGH_25_ - 1 3 1 Pin AHIGH_25_.OE 0 0 1 Pin AMIGA_ADDR_ENABLE - 0 0 1 Pin AHIGH_24_ - 1 3 1 Pin AHIGH_24_.OE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE - 1 3 1 Pin A_0_.OE - 3 5 1 Pin A_0_.D - 1 1 1 Pin A_0_.C - 1 2 1 Pin SIZE_1_.OE - 3 6 1 Pin SIZE_1_.D + 0 0 1 Pin AHIGH_30_ + 1 1 1 Pin AHIGH_30_.OE + 0 0 1 Pin AHIGH_29_ + 1 1 1 Pin AHIGH_29_.OE + 0 0 1 Pin AHIGH_28_ + 1 1 1 Pin AHIGH_28_.OE + 1 1 1 Pin SIZE_1_.OE + 2 4 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C - 10 8 1 Pin IPL_030_1_.D- - 1 1 1 Pin IPL_030_1_.C - 10 8 1 Pin IPL_030_0_.D- - 1 1 1 Pin IPL_030_0_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -1115,36 +1054,44 @@ PostFit_Equations 1 1 1 Pin BG_000.C 3 6 1 Pin BGACK_030.D 1 1 1 Pin BGACK_030.C - 1 2 1 Pin SIZE_0_.OE - 3 6 1 Pin SIZE_0_.D- - 1 1 1 Pin SIZE_0_.C + 1 1 1 Pin A_0_.OE + 2 3 1 Pin A_0_.D + 1 1 1 Pin A_0_.C + 10 8 1 Pin IPL_030_1_.D- + 1 1 1 Pin IPL_030_1_.C + 10 8 1 Pin IPL_030_0_.D- + 1 1 1 Pin IPL_030_0_.C + 1 1 1 Pin VMA.OE 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C - 1 2 1 Pin RW.OE - 2 5 1 Pin RW.D- + 1 1 1 Pin RW.OE + 1 3 1 Pin RW.D- 1 1 1 Pin RW.C + 1 1 1 Pin SIZE_0_.OE + 2 4 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.C + 3 3 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D 1 1 1 Node cpu_est_1_.C - 1 1 1 NodeX1 cpu_est_2_.D.X1 - 1 4 1 NodeX2 cpu_est_2_.D.X2 + 1 4 1 NodeX1 cpu_est_2_.D.X1 + 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C - 3 3 1 Node cpu_est_0_.D - 1 1 1 Node cpu_est_0_.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C + 2 3 1 Node inst_AS_030_D1.D + 1 1 1 Node inst_AS_030_D1.C 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C - 1 2 1 Node inst_BGACK_030_INT_D.D- - 1 1 1 Node inst_BGACK_030_INT_D.C 6 9 1 Node inst_AS_000_DMA.D 1 1 1 Node inst_AS_000_DMA.C - 9 12 1 Node inst_DS_000_DMA.D + 6 9 1 Node inst_DS_000_DMA.D 1 1 1 Node inst_DS_000_DMA.C 1 2 1 Node inst_VPA_D.D- 1 1 1 Node inst_VPA_D.C @@ -1152,10 +1099,6 @@ PostFit_Equations 1 1 1 Node CLK_000_D_3_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C - 2 7 1 Node inst_RESET_OUT.D - 1 1 1 Node inst_RESET_OUT.C - 6 11 1 Node CLK_030_PE_1_.D - 1 1 1 Node CLK_030_PE_1_.C 2 3 1 Node inst_AMIGA_DS.D 1 1 1 Node inst_AMIGA_DS.C 1 1 1 Node CLK_000_D_1_.D @@ -1176,12 +1119,14 @@ PostFit_Equations 1 1 1 Node CLK_000_D_2_.C 1 1 1 Node CLK_000_D_4_.D 1 1 1 Node CLK_000_D_4_.C - 3 6 1 Node inst_LDS_000_INT.D - 1 1 1 Node inst_LDS_000_INT.C - 3 8 1 Node inst_DS_000_ENABLE.D - 1 1 1 Node inst_DS_000_ENABLE.C 2 4 1 Node inst_UDS_000_INT.D- 1 1 1 Node inst_UDS_000_INT.C + 3 8 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 3 6 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.C + 1 2 1 Node inst_BGACK_030_INT_D.D- + 1 1 1 Node inst_BGACK_030_INT_D.C 3 9 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 3 5 1 Node SM_AMIGA_4_.D @@ -1194,15 +1139,6 @@ PostFit_Equations 1 1 1 Node CYCLE_DMA_0_.C 2 7 1 Node CYCLE_DMA_1_.D 1 1 1 Node CYCLE_DMA_1_.C - 9 11 1 Node CLK_030_PE_0_.D- - 1 1 1 Node CLK_030_PE_0_.C - 4 6 1 Node RST_DLY_0_.D - 1 1 1 Node RST_DLY_0_.C - 2 6 1 NodeX1 RST_DLY_1_.D.X1 - 1 2 1 NodeX2 RST_DLY_1_.D.X2 - 1 1 1 Node RST_DLY_1_.C - 2 6 1 Node RST_DLY_2_.D - 1 1 1 Node RST_DLY_2_.C 2 6 1 Node inst_DSACK1_INT.D- 1 1 1 Node inst_DSACK1_INT.C 2 6 1 Node inst_AS_000_INT.D- @@ -1213,44 +1149,60 @@ PostFit_Equations 1 1 1 Node SM_AMIGA_3_.C 5 13 1 Node SM_AMIGA_2_.D 1 1 1 Node SM_AMIGA_2_.C + 1 1 1 Node CLK_OUT_INTreg.D + 1 1 1 Node CLK_OUT_INTreg.C 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C - 1 1 1 Node CLK_OUT_INTreg.D - 1 1 1 Node CLK_OUT_INTreg.C - 2 14 1 Node CIIN_0 + 2 14 1 Node N_60 ========= - 281 P-Term Total: 281 - Total Pins: 61 - Total Nodes: 47 + 243 P-Term Total: 243 + Total Pins: 59 + Total Nodes: 42 Average P-Term/Output: 2 Equations: +AHIGH_27_ = (0); + +AHIGH_27_.OE = (!BGACK_030.Q); + +AHIGH_26_ = (0); + +AHIGH_26_.OE = (!BGACK_030.Q); + +AHIGH_25_ = (0); + +AHIGH_25_.OE = (!BGACK_030.Q); + +AHIGH_24_ = (0); + +AHIGH_24_.OE = (!BGACK_030.Q); + AHIGH_31_ = (0); -AHIGH_31_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); +AHIGH_31_.OE = (!BGACK_030.Q); !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); -AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +AS_030.OE = (!BGACK_030.Q); !AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); -AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); +AS_000.OE = (RST & BGACK_030.Q); !DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); -DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +DS_030.OE = (!BGACK_030.Q); -!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q); +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); -UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); +UDS_000.OE = (RST & BGACK_030.Q); -!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q); +!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q); -LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); +LDS_000.OE = (RST & BGACK_030.Q); BERR = (0); @@ -1264,47 +1216,15 @@ CLK_EXP = (CLK_OUT_INTreg.Q); !DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN); -DSACK1.OE = (nEXP_SPACE); - -DTACK = (0); - -DTACK.OE = (!inst_AS_000_DMA.Q); +DSACK1.OE = (nEXP_SPACE & BGACK_030.Q); AVEC = (1); E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q # cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q); -AHIGH_30_ = (0); - -AHIGH_30_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_29_ = (0); - -AHIGH_29_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_28_ = (0); - -AHIGH_28_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_27_ = (0); - -AHIGH_27_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_26_ = (0); - -AHIGH_26_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - -AHIGH_25_ = (0); - -AHIGH_25_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - AMIGA_ADDR_ENABLE = (0); -AHIGH_24_ = (0); - -AHIGH_24_.OE = (!nEXP_SPACE & RESET & !BGACK_030.Q); - AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); @@ -1315,24 +1235,67 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); -CIIN.OE = (CIIN_0); +CIIN.OE = (N_60); -A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); +AHIGH_30_ = (0); -A_0_.D = (!RST - # !BGACK_030.Q & UDS_000.PIN - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q); +AHIGH_30_.OE = (!BGACK_030.Q); -A_0_.C = (CLK_OSZI); +AHIGH_29_ = (0); -SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); +AHIGH_29_.OE = (!BGACK_030.Q); + +AHIGH_28_ = (0); + +AHIGH_28_.OE = (!BGACK_030.Q); + +SIZE_1_.OE = (!BGACK_030.Q); SIZE_1_.D = (!RST - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_1_.Q # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); SIZE_1_.C = (CLK_OSZI); +!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q + # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q + # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q + # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q + # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q + # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q + # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); + +IPL_030_2_.C = (CLK_OSZI); + +RW_000.OE = (RST & BGACK_030.Q); + +!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_6_.Q & !RW_000.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q + # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); + +RW_000.C = (CLK_OSZI); + +!BG_000.D = (!BG_030 & RST & !BG_000.Q + # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); + +BG_000.C = (CLK_OSZI); + +BGACK_030.D = (!RST + # BGACK_000 & BGACK_030.Q + # BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN); + +BGACK_030.C = (CLK_OSZI); + +A_0_.OE = (!BGACK_030.Q); + +A_0_.D = (!RST + # !BGACK_030.Q & UDS_000.PIN); + +A_0_.C = (CLK_OSZI); + !IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q @@ -1359,79 +1322,26 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q - # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q - # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q - # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q - # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q - # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q - # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q); - -IPL_030_2_.C = (CLK_OSZI); - -RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); - -!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN); - -RW_000.C = (CLK_OSZI); - -!BG_000.D = (!BG_030 & RST & !BG_000.Q - # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); - -BG_000.C = (CLK_OSZI); - -BGACK_030.D = (!RST - # BGACK_000 & BGACK_030.Q - # BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN); - -BGACK_030.C = (CLK_OSZI); - -SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); - -!SIZE_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q - # RST & BGACK_030.Q & !SIZE_0_.Q - # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_0_.C = (CLK_OSZI); +VMA.OE = (BGACK_030.Q); VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q - # RST & VMA.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !VMA.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q + # RST & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); VMA.C = (CLK_OSZI); -RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); +RW.OE = (!BGACK_030.Q); -!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q); +!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN); RW.C = (CLK_OSZI); -cpu_est_1_.D = (cpu_est_1_.Q & !cpu_est_0_.Q - # cpu_est_1_.Q & !CLK_000_D_1_.Q - # cpu_est_1_.Q & CLK_000_D_0_.Q - # !cpu_est_1_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); +SIZE_0_.OE = (!BGACK_030.Q); -cpu_est_1_.C = (CLK_OSZI); +!SIZE_0_.D = (RST & BGACK_030.Q + # RST & !UDS_000.PIN & !LDS_000.PIN); -cpu_est_2_.D.X1 = (cpu_est_2_.Q); - -cpu_est_2_.D.X2 = (cpu_est_1_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -cpu_est_2_.C = (CLK_OSZI); - -cpu_est_3_.D = (cpu_est_3_.Q & !CLK_000_D_1_.Q - # cpu_est_3_.Q & CLK_000_D_0_.Q - # !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q - # cpu_est_1_.Q & cpu_est_2_.Q & cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); - -cpu_est_3_.C = (CLK_OSZI); +SIZE_0_.C = (CLK_OSZI); cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q # cpu_est_0_.Q & CLK_000_D_0_.Q @@ -1439,13 +1349,31 @@ cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q cpu_est_0_.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q - # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q & inst_BGACK_030_INT_D.Q); +cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q + # cpu_est_1_.Q & !CLK_000_D_1_.Q + # cpu_est_1_.Q & CLK_000_D_0_.Q + # cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_1_.C = (CLK_OSZI); + +cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_2_.D.X2 = (cpu_est_2_.Q); + +cpu_est_2_.C = (CLK_OSZI); + +cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q + # cpu_est_3_.Q & !CLK_000_D_1_.Q + # cpu_est_3_.Q & CLK_000_D_0_.Q + # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); + +cpu_est_3_.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q - # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); @@ -1453,20 +1381,21 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); inst_AS_030_D0.C = (CLK_OSZI); +inst_AS_030_D1.D = (RST & inst_AS_030_D0.Q + # !RST & inst_AS_030_D1.Q); + +inst_AS_030_D1.C = (CLK_OSZI); + !inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_000_SYNC.Q & !AS_030.PIN - # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN - # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); + # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN + # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); -!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); - -inst_BGACK_030_INT_D.C = (CLK_OSZI); - inst_AS_000_DMA.D = (!RST # inst_AMIGA_DS.Q # AS_000.PIN @@ -1480,11 +1409,8 @@ inst_DS_000_DMA.D = (!RST # inst_AMIGA_DS.Q # AS_000.PIN # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q - # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN - # inst_DS_000_DMA.Q & CLK_030_PE_1_.Q & !RW_000.PIN - # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN - # inst_DS_000_DMA.Q & !CLK_030_PE_0_.Q & !RW_000.PIN - # inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q & RW_000.PIN); + # inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q + # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN); inst_DS_000_DMA.C = (CLK_OSZI); @@ -1496,24 +1422,10 @@ CLK_000_D_3_.D = (CLK_000_D_2_.Q); CLK_000_D_3_.C = (CLK_OSZI); -!inst_DTACK_D0.D = (RST & !DTACK.PIN); +!inst_DTACK_D0.D = (!DTACK & RST); inst_DTACK_D0.C = (CLK_OSZI); -inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); - -inst_RESET_OUT.C = (CLK_OSZI); - -CLK_030_PE_1_.D = (RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & CLK_030_PE_1_.Q & !inst_AMIGA_DS.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & RW_000.PIN - # RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN - # RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN - # RST & !inst_AS_000_DMA.Q & !inst_AMIGA_DS.Q & inst_CLK_OUT_PRE_D.Q & CYCLE_DMA_1_.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q & !AS_000.PIN & RW_000.PIN); - -CLK_030_PE_1_.C = (CLK_OSZI); - inst_AMIGA_DS.D = (!RST # UDS_000.PIN & LDS_000.PIN); @@ -1555,11 +1467,10 @@ CLK_000_D_4_.D = (CLK_000_D_3_.Q); CLK_000_D_4_.C = (CLK_OSZI); -inst_LDS_000_INT.D = (!RST - # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q - # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); +!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); -inst_LDS_000_INT.C = (CLK_OSZI); +inst_UDS_000_INT.C = (CLK_OSZI); inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q @@ -1567,10 +1478,15 @@ inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN inst_DS_000_ENABLE.C = (CLK_OSZI); -!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A_0_.PIN); +inst_LDS_000_INT.D = (!RST + # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q + # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); -inst_UDS_000_INT.C = (CLK_OSZI); +inst_LDS_000_INT.C = (CLK_OSZI); + +!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q @@ -1608,37 +1524,6 @@ CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !AS_000.PIN CYCLE_DMA_1_.C = (CLK_OSZI); -!CLK_030_PE_0_.D = (!RST - # inst_AMIGA_DS.Q - # AS_000.PIN - # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q - # inst_AS_000_DMA.Q & !CLK_030_PE_0_.Q - # !inst_CLK_OUT_PRE_D.Q & !CLK_030_PE_0_.Q - # !CLK_030_PE_0_.Q & CLK_OUT_INTreg.Q - # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN - # !inst_AS_000_DMA.Q & !CLK_030_PE_1_.Q & inst_CLK_OUT_PRE_D.Q & CLK_030_PE_0_.Q & !CLK_OUT_INTreg.Q); - -CLK_030_PE_0_.C = (CLK_OSZI); - -RST_DLY_0_.D = (RST & !CLK_000_D_1_.Q & RST_DLY_0_.Q - # RST & CLK_000_D_0_.Q & RST_DLY_0_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !RST_DLY_0_.Q - # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); - -RST_DLY_0_.C = (CLK_OSZI); - -RST_DLY_1_.D.X1 = (RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & !RST_DLY_2_.Q); - -RST_DLY_1_.D.X2 = (RST & RST_DLY_1_.Q); - -RST_DLY_1_.C = (CLK_OSZI); - -RST_DLY_2_.D = (RST & RST_DLY_2_.Q - # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); - -RST_DLY_2_.C = (CLK_OSZI); - !inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q); @@ -1659,7 +1544,7 @@ SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q # CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN # inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); @@ -1667,10 +1552,14 @@ SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q # RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q # RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q - # RST & !VMA.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); + # RST & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); +CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q); + +CLK_OUT_INTreg.C = (CLK_OSZI); + SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q # RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q); @@ -1679,11 +1568,7 @@ SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_ SM_AMIGA_i_7_.C = (CLK_OSZI); -CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q); - -CLK_OUT_INTreg.C = (CLK_OSZI); - -CIIN_0 = (nEXP_SPACE +N_60 = (nEXP_SPACE # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 36687be..37bb500 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -32,7 +32,7 @@ TCR, Clocked Output-to-Register Time, TSU TCO TPD TCR #passes #passes #passes #passes SIGNAL NAME min max min max min max min max - inst_AS_000_DMA 1 2 1 3 .. .. 1 3 + inst_AS_000_DMA 1 2 1 3 .. .. 2 3 inst_AS_000_INT 1 2 1 3 .. .. 2 3 DS_030 .. .. .. .. 1 2 .. .. FPU_CS .. .. .. .. 1 2 .. .. @@ -44,48 +44,41 @@ AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 2 .. .. inst_AS_030_D0 1 2 1 1 .. .. 1 1 inst_AS_030_000_SYNC 1 2 1 1 .. .. 1 1 inst_DS_000_DMA 1 2 1 1 .. .. .. .. - CLK_030_PE_1_ 1 2 .. .. .. .. 1 1 -inst_LDS_000_INT 1 1 1 1 .. .. 2 2 -inst_DS_000_ENABLE 1 2 1 1 .. .. 2 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 +inst_DS_000_ENABLE 1 2 1 1 .. .. 2 2 +inst_LDS_000_INT 1 1 1 1 .. .. 2 2 CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1 - CLK_030_PE_0_ 1 2 .. .. .. .. 1 1 inst_DSACK1_INT 1 2 1 1 .. .. .. .. AS_030 .. .. .. .. 1 1 .. .. AS_000 .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. - A_0_ 1 1 0 0 .. .. 1 1 - RN_A_0_ 1 1 0 0 .. .. 1 1 - SIZE_1_ 1 1 0 0 .. .. 1 1 - RN_SIZE_1_ 1 1 0 0 .. .. 1 1 - IPL_030_1_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 - IPL_030_0_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + SIZE_1_ 1 1 0 0 .. .. .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 RW_000 1 1 0 0 .. .. 1 1 RN_RW_000 1 1 0 0 .. .. 1 1 BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 - SIZE_0_ 1 1 0 0 .. .. 1 1 - RN_SIZE_0_ 1 1 0 0 .. .. 1 1 + A_0_ 1 1 0 0 .. .. .. .. + IPL_030_1_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 + IPL_030_0_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 VMA 1 1 0 0 .. .. 1 1 RN_VMA 1 1 0 0 .. .. 1 1 - RW 1 1 0 0 .. .. 1 1 - RN_RW 1 1 0 0 .. .. 1 1 + RW 1 1 0 0 .. .. .. .. + SIZE_0_ 1 1 0 0 .. .. .. .. + cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. 1 1 .. .. 1 1 cpu_est_2_ .. .. 1 1 .. .. 1 1 cpu_est_3_ .. .. 1 1 .. .. 1 1 - cpu_est_0_ .. .. .. .. .. .. 1 1 inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. -inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 + inst_AS_030_D1 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 CLK_000_D_3_ .. .. .. .. .. .. 1 1 inst_DTACK_D0 1 1 .. .. .. .. 1 1 - inst_RESET_OUT 1 1 .. .. .. .. .. .. inst_AMIGA_DS 1 1 .. .. .. .. 1 1 CLK_000_D_1_ .. .. .. .. .. .. 1 1 CLK_000_D_0_ 1 1 .. .. .. .. 1 1 @@ -96,16 +89,14 @@ inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 IPL_D0_2_ 1 1 .. .. .. .. 1 1 CLK_000_D_2_ .. .. .. .. .. .. 1 1 CLK_000_D_4_ .. .. .. .. .. .. 1 1 +inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 SM_AMIGA_4_ 1 1 .. .. .. .. 1 1 SM_AMIGA_1_ 1 1 .. .. .. .. 1 1 SM_AMIGA_0_ 1 1 .. .. .. .. 1 1 - RST_DLY_0_ 1 1 .. .. .. .. 1 1 - RST_DLY_1_ 1 1 .. .. .. .. 1 1 - RST_DLY_2_ 1 1 .. .. .. .. 1 1 SM_AMIGA_5_ 1 1 .. .. .. .. 1 1 SM_AMIGA_3_ 1 1 .. .. .. .. 1 1 SM_AMIGA_2_ 1 1 .. .. .. .. 1 1 - SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1 CLK_OUT_INTreg .. .. 1 1 .. .. 1 1 - CIIN_0 .. .. .. .. 1 1 .. .. \ No newline at end of file + SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1 + N_60 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index d37f5d5..60c0ec6 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,518 +1,433 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE 68030_tk -#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ VMA RW -#$ NODES 46 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CLK_OUT_INTreg +#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_ VMA RW SIZE_0_ +#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 .type fr -.i 100 -.o 162 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE VPA RST RESET A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_030_PE_1_.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q CLK_030_PE_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN -.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C CLK_030_PE_0_.C CLK_030_PE_1_.C SIZE_0_.C SIZE_1_.C cpu_est_0_.C cpu_est_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C inst_AS_030_D0.C inst_DTACK_D0.C inst_VPA_D.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR DTACK AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE DTACK.OE RW.OE DS_030.OE DSACK1.OE CIIN.OE BGACK_030.D VMA.T cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_030_PE_1_.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D CLK_030_PE_0_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 506 ----------------------------------------------------------------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1-------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------1-------------1-----------0------0----------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------1--------------1----------0------0----------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------1---------------1---------0------0----------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------1----------------0--------0------0----------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------1-----------------1-------0------0----------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------1-------------------------1-1----0----------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------------------1-----------0------------------------------------0----------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ---------------------------1----------0------------------------------------0----------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ----------------------------1---------0------------------------------------0----------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -----------------------------0--------0------------------------------------0----------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------------------------1-------0------------------------------------0----------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------1-1----------------------------------0----------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ ------------1--------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0--0------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------1-------------------------------01----------1--0----------------1-----------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ---------------------------------------------------------0------------------------1-----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 90 +.o 152 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C SIZE_0_.C SIZE_1_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.C inst_DTACK_D0.C inst_DS_000_ENABLE.C BG_000.C inst_LDS_000_INT.C VMA.C RW_000.C inst_AS_030_000_SYNC.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C A_0_.C RW.C inst_AS_030_D0.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D1.C inst_UDS_000_INT.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_60 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE BGACK_030.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_D1.D inst_AS_030_000_SYNC.D inst_AS_000_DMA.D inst_DS_000_DMA.D VMA.T inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D SIZE_0_.D SIZE_1_.D A_0_.D RW.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D inst_BGACK_030_INT_D.D SM_AMIGA_6_.D RW_000.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D SM_AMIGA_i_7_.T IPL_030_2_.D +.p 421 +------------------------------------------------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0--------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-------------------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------10---------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------1-1-------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------------0----0---------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------1----------------------------01-----------1---0-----------1-------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-------------------------------------------------------0----------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 9cfabe9..3ea4ce5 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,518 +1,433 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE 68030_tk -#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 SIZE_0_ VMA RW -#$ NODES 46 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CLK_OUT_INTreg +#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_ VMA RW SIZE_0_ +#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 .type fr -.i 100 -.o 162 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE VPA RST RESET A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q VMA.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q CLK_030_PE_1_.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q SIZE_0_.Q SIZE_1_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q CLK_030_PE_0_.Q RW_000.Q RW.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN -.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C CLK_030_PE_0_.C CLK_030_PE_1_.C SIZE_0_.C SIZE_1_.C cpu_est_0_.C cpu_est_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C inst_AS_030_D0.C inst_DTACK_D0.C inst_VPA_D.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.C A_0_.C RW.C VMA.C RW_000.C inst_AS_030_000_SYNC.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR DTACK AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE DTACK.OE RW.OE DS_030.OE DSACK1.OE CIIN.OE BGACK_030.D VMA.T cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_RESET_OUT.D CLK_030_PE_1_.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D inst_LDS_000_INT.D inst_DS_000_ENABLE.D inst_UDS_000_INT.D SM_AMIGA_6_.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D SIZE_0_.D SIZE_1_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D CLK_030_PE_0_.D RW_000.D RW.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D A_0_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.T BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 506 ----------------------------------------------------------------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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---------------------------------------------------------0------------------------1-----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 90 +.o 152 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C SIZE_0_.C SIZE_1_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.C inst_DTACK_D0.C inst_DS_000_ENABLE.C BG_000.C inst_LDS_000_INT.C VMA.C RW_000.C inst_AS_030_000_SYNC.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C A_0_.C RW.C inst_AS_030_D0.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D1.C inst_UDS_000_INT.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_60 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE BGACK_030.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_D1.D inst_AS_030_000_SYNC.D inst_AS_000_DMA.D inst_DS_000_DMA.D VMA.T inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D SIZE_0_.D SIZE_1_.D A_0_.D RW.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D inst_BGACK_030_INT_D.D SM_AMIGA_6_.D RW_000.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D SM_AMIGA_i_7_.T IPL_030_2_.D +.p 421 +------------------------------------------------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0--------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-----0------------------------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------1-----------------------10----0----------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +-----------1------------------------1-1--0----------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +------------------------1-----------0---------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-------------------------1----------0---------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------1---------0---------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------0--------0---------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------10---------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------1-1-------------------------0-----------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------------0----0---------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------1----------------------------01-----------1---0-----------1-------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-------------------------------------------------------0----------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 33a84d8..def45c3 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,265 +1,229 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE BUS68030 -#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 - AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 - CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA - AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE - AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ - AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ - A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 - BGACK_030 SIZE_0_ VMA RW -#$ NODES 47 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ +#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ + A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ + A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR + BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ + FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ + AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ + IPL_030_0_ VMA RW SIZE_0_ +#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 - inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA - inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS - CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ - IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT - inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ - SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ - RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ - SM_AMIGA_i_7_ CLK_OUT_INTreg CIIN_0 + inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D + CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ + inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ + CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT + inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ + CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ + SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 .type f -.i 101 -.o 166 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 - CLK_OSZI FPU_SENSE VPA RST RESET A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ - A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ - BGACK_030.Q VMA.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q +.i 90 +.o 154 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI + FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ + A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q + cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q - inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q - inst_DS_000_DMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q - CLK_030_PE_1_.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q - inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q - CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q - inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q - SIZE_0_.Q SIZE_1_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q CLK_030_PE_0_.Q RW_000.Q RW.Q - RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_DSACK1_INT.Q - inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q - BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN - AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN - AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN - AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN - CIIN_0 -.ob AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE - UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_EXP FPU_CS% - DSACK1% DSACK1.OE DTACK DTACK.OE AVEC E AHIGH_30_ AHIGH_30_.OE AHIGH_29_ - AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ - AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AMIGA_ADDR_ENABLE AHIGH_24_ AHIGH_24_.OE + inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q + inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q + inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q + CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q + inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q + SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q + SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q + IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN + AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN + AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE + AHIGH_24_ AHIGH_24_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% + AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE + CLK_DIV_OUT CLK_EXP FPU_CS% DSACK1% DSACK1.OE AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH% CIIN CIIN.OE - A_0_.D A_0_.C A_0_.OE SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_1_.D% IPL_030_1_.C - IPL_030_0_.D% IPL_030_0_.C IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C - RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D% SIZE_0_.C - SIZE_0_.OE VMA.T VMA.C RW.D% RW.C RW.OE cpu_est_1_.D cpu_est_1_.C - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C - cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% - inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% - inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C - inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% - inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D - inst_DS_000_DMA.C inst_VPA_D.D% inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C - inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C - CLK_030_PE_1_.D CLK_030_PE_1_.C inst_AMIGA_DS.D inst_AMIGA_DS.C CLK_000_D_1_.D - CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D - inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% - IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D - CLK_000_D_2_.C CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D - inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D% - inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CYCLE_DMA_0_.D - CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C CLK_030_PE_0_.D% CLK_030_PE_0_.C - RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C - RST_DLY_2_.D RST_DLY_2_.C inst_DSACK1_INT.D% inst_DSACK1_INT.C inst_AS_000_INT.D% - inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2 - SM_AMIGA_i_7_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C CIIN_0 -.phase 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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000 +-------------------------------------------1---------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-----------0---------------------------------------------------------1-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-----------1----------------------------01---------------1-----------1-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1-------1--------------------0----0----------1--------------------0-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1-------1--------------------0----0--01------1--------1-----------0-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +---1-------------------------------------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 0cfc5a1..5e7852b 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,265 +1,229 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE BUS68030 -#$ PINS 61 AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_2_ FC_1_ AS_030 - AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 - CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E AHIGH_30_ VPA - AHIGH_29_ AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ AHIGH_25_ AMIGA_ADDR_ENABLE - AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ - AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ - A_DECODE_16_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ IPL_030_2_ RW_000 BG_000 - BGACK_030 SIZE_0_ VMA RW -#$ NODES 47 cpu_est_1_ cpu_est_2_ cpu_est_3_ cpu_est_0_ +#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ + A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ + A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR + BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ + FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE + AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ + AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ + IPL_030_0_ VMA RW SIZE_0_ +#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 - inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA - inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_030_PE_1_ inst_AMIGA_DS - CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ - IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT - inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ - SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ CLK_030_PE_0_ RST_DLY_0_ RST_DLY_1_ - RST_DLY_2_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ - SM_AMIGA_i_7_ CLK_OUT_INTreg CIIN_0 + inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D + CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ + inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ + CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT + inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ + CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ + SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 .type f -.i 101 -.o 166 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 - CLK_OSZI FPU_SENSE VPA RST RESET A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ - A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ - BGACK_030.Q VMA.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q +.i 90 +.o 154 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI + FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ + A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q + cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q - inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q - inst_DS_000_DMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q - CLK_030_PE_1_.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q - inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q - CLK_000_D_2_.Q CLK_000_D_4_.Q inst_LDS_000_INT.Q inst_DS_000_ENABLE.Q - inst_UDS_000_INT.Q SM_AMIGA_6_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q - SIZE_0_.Q SIZE_1_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q CLK_030_PE_0_.Q RW_000.Q RW.Q - RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q A_0_.Q inst_DSACK1_INT.Q - inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q - BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN - AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN - AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN - AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN - CIIN_0 -.ob AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE - UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_EXP FPU_CS- - DSACK1- DSACK1.OE DTACK DTACK.OE AVEC E AHIGH_30_ AHIGH_30_.OE AHIGH_29_ - AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ - AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE AMIGA_ADDR_ENABLE AHIGH_24_ AHIGH_24_.OE + inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q + inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q + inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q + CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q + inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q + SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q + SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q + IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN + AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN + AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE + AHIGH_24_ AHIGH_24_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- + AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE + CLK_DIV_OUT CLK_EXP FPU_CS- DSACK1- DSACK1.OE AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH- CIIN CIIN.OE - A_0_.D A_0_.C A_0_.OE SIZE_1_.D SIZE_1_.C SIZE_1_.OE IPL_030_1_.D- IPL_030_1_.C - IPL_030_0_.D- IPL_030_0_.C IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C - RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C SIZE_0_.D- SIZE_0_.C - SIZE_0_.OE VMA.T VMA.C RW.D- RW.C RW.OE cpu_est_1_.D cpu_est_1_.C - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C - cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- - inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D- - inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C - inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- - inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D - inst_DS_000_DMA.C inst_VPA_D.D- inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C - inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C - CLK_030_PE_1_.D CLK_030_PE_1_.C inst_AMIGA_DS.D inst_AMIGA_DS.C CLK_000_D_1_.D - CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D - inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- - IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D - CLK_000_D_2_.C CLK_000_D_4_.D CLK_000_D_4_.C inst_LDS_000_INT.D - inst_LDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_UDS_000_INT.D- - inst_UDS_000_INT.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CYCLE_DMA_0_.D - CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C CLK_030_PE_0_.D- CLK_030_PE_0_.C - RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D.X1 RST_DLY_1_.D.X2 RST_DLY_1_.C - RST_DLY_2_.D RST_DLY_2_.C inst_DSACK1_INT.D- inst_DSACK1_INT.C inst_AS_000_INT.D- - inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.T.X1 SM_AMIGA_i_7_.T.X2 - SM_AMIGA_i_7_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C CIIN_0 -.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 187 ------------------------------------------------------------------------------------------------------ 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-----------------------------------------------1------------------------------------------------------ 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 + AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE SIZE_1_.D + SIZE_1_.C SIZE_1_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE + BG_000.D- BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE IPL_030_1_.D- + IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C VMA.T VMA.C VMA.OE RW.D- RW.C RW.OE + SIZE_0_.D- SIZE_0_.C SIZE_0_.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D + cpu_est_1_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D + cpu_est_3_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C + inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_D1.D inst_AS_030_D1.C + inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_AS_000_DMA.D + inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_VPA_D.D- inst_VPA_D.C + CLK_000_D_3_.D CLK_000_D_3_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_AMIGA_DS.D + inst_AMIGA_DS.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C + inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D + inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C + IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_4_.D + CLK_000_D_4_.C inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_DS_000_ENABLE.D + inst_DS_000_ENABLE.C inst_LDS_000_INT.D inst_LDS_000_INT.C + inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C SM_AMIGA_6_.D SM_AMIGA_6_.C + SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D + SM_AMIGA_0_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C + inst_DSACK1_INT.D- inst_DSACK1_INT.C inst_AS_000_INT.D- inst_AS_000_INT.C + SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D + SM_AMIGA_2_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C SM_AMIGA_i_7_.T.X1 + SM_AMIGA_i_7_.T.X2 SM_AMIGA_i_7_.C N_60 +.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +.p 156 +------------------------------------------------------------------------------------------ 0000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +-----------------------0------------------------------------------------------------------ 0101010101010001000000000000000000001010100100000000000100000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +---------------------------------0---------------------------------------0---------------- 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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-----------0---------------------------------------------------------1-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-----------1----------------------------01---------------1-----------1-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1-------1--------------------0----0----------1--------------------0-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +---1-------1--------------------0----0--01------1--------1-----------0-------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +---1-------------------------------------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index b72a354..c80ce69 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 12/29/16; -TIME = 16:02:00; +DATE = 12/30/17; +TIME = 00:43:46; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -117,6 +117,7 @@ Conf_Unused_IOs = OUT_LOW; [POWER] Powerlevel = Low, High; Default = High; +High = 1, B; Low = 8, H, G, F, E, D, C, B, A; Type = GLB; @@ -142,16 +143,15 @@ layer = OFF; Layer = OFF AS_030 = OUTPUT,82,7,-; -RW_000 = BIDIR,80,7,-; AS_000 = OUTPUT,42,4,-; +RW_000 = BIDIR,80,7,-; +A_0_ = OUTPUT,69,6,-; +RW = OUTPUT,71,6,-; UDS_000 = OUTPUT,32,3,-; LDS_000 = OUTPUT,31,3,-; -RW = BIDIR,71,6,-; -SIZE_1_ = BIDIR,79,7,-; -SIZE_0_ = BIDIR,70,6,-; -A_0_ = BIDIR,69,6,-; +SIZE_1_ = OUTPUT,79,7,-; +SIZE_0_ = OUTPUT,70,6,-; BERR = OUTPUT,41,4,-; -DTACK = OUTPUT,30,3,-; AHIGH_24_ = OUTPUT,19,2,-; AHIGH_25_ = OUTPUT,18,2,-; AHIGH_26_ = OUTPUT,17,2,-; @@ -181,59 +181,50 @@ CLK_EXP = OUTPUT,10,1,-; RN_BGACK_030 = NODE,-1,7,-; CLK_000_D_0_ = NODE,*,3,-; CLK_000_D_1_ = NODE,*,7,-; -inst_RESET_OUT = NODE,*,6,-; SM_AMIGA_6_ = NODE,*,5,-; -inst_BGACK_030_INT_D = NODE,*,7,-; -inst_AS_030_000_SYNC = NODE,*,1,-; -inst_AS_000_DMA = NODE,*,0,-; -cpu_est_3_ = NODE,*,3,-; +cpu_est_3_ = NODE,*,0,-; cpu_est_1_ = NODE,*,3,-; -SM_AMIGA_i_7_ = NODE,*,5,-; SM_AMIGA_0_ = NODE,*,0,-; +SM_AMIGA_4_ = NODE,*,6,-; cpu_est_0_ = NODE,*,6,-; -CLK_OUT_INTreg = NODE,*,3,-; -inst_AS_030_D0 = NODE,*,7,-; +CLK_OUT_INTreg = NODE,*,0,-; +inst_AS_030_D0 = NODE,*,4,-; cpu_est_2_ = NODE,*,3,-; -SM_AMIGA_2_ = NODE,*,2,-; +inst_AS_030_000_SYNC = NODE,*,5,-; +inst_DS_000_DMA = NODE,*,2,-; +inst_AS_000_DMA = NODE,*,2,-; +CYCLE_DMA_0_ = NODE,*,1,-; RN_VMA = NODE,-1,3,-; -SM_AMIGA_5_ = NODE,*,6,-; -SM_AMIGA_1_ = NODE,*,5,-; -SM_AMIGA_4_ = NODE,*,0,-; +SM_AMIGA_i_7_ = NODE,*,5,-; +SM_AMIGA_5_ = NODE,*,5,-; +SM_AMIGA_1_ = NODE,*,0,-; +inst_LDS_000_INT = NODE,*,6,-; inst_DS_000_ENABLE = NODE,*,2,-; -inst_LDS_000_INT = NODE,*,5,-; inst_AS_000_INT = NODE,*,2,-; -inst_DSACK1_INT = NODE,*,0,-; -inst_UDS_000_INT = NODE,*,5,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,5,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,5,-; +inst_DSACK1_INT = NODE,*,6,-; +CYCLE_DMA_1_ = NODE,*,1,-; +inst_UDS_000_INT = NODE,*,1,-; inst_CLK_OUT_PRE_D = NODE,*,4,-; -inst_CLK_OUT_PRE_50 = NODE,*,6,-; -CLK_000_D_3_ = NODE,*,5,-; -inst_VPA_D = NODE,*,5,-; -RN_IPL_030_2_ = NODE,-1,1,-; +inst_CLK_OUT_PRE_50 = NODE,*,7,-; +inst_VPA_D = NODE,*,6,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; -CLK_030_PE_0_ = NODE,*,0,-; -inst_DS_000_DMA = NODE,*,0,-; -CLK_030_PE_1_ = NODE,*,0,-; -SM_AMIGA_3_ = NODE,*,2,-; +RN_IPL_030_2_ = NODE,-1,1,-; +SM_AMIGA_2_ = NODE,*,0,-; +SM_AMIGA_3_ = NODE,*,0,-; RN_RW_000 = NODE,-1,7,-; -RST_DLY_0_ = NODE,*,6,-; -CYCLE_DMA_0_ = NODE,*,0,-; -RN_SIZE_0_ = NODE,-1,6,-; -RN_SIZE_1_ = NODE,-1,7,-; -RN_A_0_ = NODE,-1,6,-; -RN_RW = NODE,-1,6,-; RN_BG_000 = NODE,-1,3,-; -CIIN_0 = NODE,*,4,-; -RST_DLY_2_ = NODE,*,6,-; -RST_DLY_1_ = NODE,*,6,-; -CYCLE_DMA_1_ = NODE,*,0,-; -inst_AMIGA_DS = NODE,*,2,-; -CLK_000_D_4_ = NODE,*,2,-; +N_60 = NODE,*,4,-; +inst_AMIGA_DS = NODE,*,7,-; +inst_AS_030_D1 = NODE,*,5,-; +inst_BGACK_030_INT_D = NODE,*,4,-; +CLK_000_D_4_ = NODE,*,5,-; CLK_000_D_2_ = NODE,*,7,-; -IPL_D0_2_ = NODE,*,1,-; -IPL_D0_1_ = NODE,*,1,-; -IPL_D0_0_ = NODE,*,1,-; -inst_DTACK_D0 = NODE,*,1,-; +IPL_D0_2_ = NODE,*,0,-; +IPL_D0_1_ = NODE,*,3,-; +IPL_D0_0_ = NODE,*,0,-; +inst_DTACK_D0 = NODE,*,5,-; +CLK_000_D_3_ = NODE,*,5,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,0,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 05984ef..d5cbe9e 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 12/29/16; -TIME = 16:02:00; +DATE = 12/30/17; +TIME = 00:43:46; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -117,6 +117,7 @@ Conf_Unused_IOs = OUT_LOW; [POWER] Powerlevel = Low, High; Default = High; +High = 1, B; Low = 8, H, G, F, E, D, C, B, A; Type = GLB; @@ -141,12 +142,19 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; +AHIGH_27_ = BIDIR,16, C,-; +AHIGH_26_ = BIDIR,17, C,-; +AHIGH_25_ = BIDIR,18, C,-; +AHIGH_24_ = BIDIR,19, C,-; AHIGH_31_ = BIDIR,4, B,-; -IPL_1_ = INPUT,56, F,-; -IPL_0_ = INPUT,67, G,-; +A_DECODE_22_ = INPUT,84, H,-; +A_DECODE_21_ = INPUT,94, A,-; A_DECODE_23_ = INPUT,85, H,-; -FC_0_ = INPUT,57, F,-; -A_1_ = INPUT,60, F,-; +A_DECODE_20_ = INPUT,93, A,-; +A_DECODE_19_ = INPUT,97, A,-; +A_DECODE_18_ = INPUT,95, A,-; +A_DECODE_17_ = INPUT,59, F,-; +A_DECODE_16_ = INPUT,96, A,-; IPL_2_ = INPUT,68, G,-; FC_1_ = INPUT,58, F,-; AS_030 = BIDIR,82, H,-; @@ -158,94 +166,80 @@ nEXP_SPACE = INPUT,14,-,-; BERR = BIDIR,41, E,-; BG_030 = INPUT,21, C,-; BGACK_000 = INPUT,28, D,-; -CLK_030 = INPUT,64,-,-; CLK_000 = INPUT,11,-,-; +IPL_1_ = INPUT,56, F,-; CLK_OSZI = INPUT,61,-,-; +IPL_0_ = INPUT,67, G,-; CLK_DIV_OUT = OUTPUT,65, G,-; +FC_0_ = INPUT,57, F,-; CLK_EXP = OUTPUT,10, B,-; +A_1_ = INPUT,60, F,-; FPU_CS = OUTPUT,78, H,-; FPU_SENSE = INPUT,91, A,-; DSACK1 = OUTPUT,81, H,-; -DTACK = BIDIR,30, D,-; +DTACK = INPUT,30, D,-; AVEC = OUTPUT,92, A,-; E = OUTPUT,66, G,-; -AHIGH_30_ = BIDIR,5, B,-; VPA = INPUT,36,-,-; +RST = INPUT,86,-,-; +AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; +AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; +CIIN = OUTPUT,47, E,-; +AHIGH_30_ = BIDIR,5, B,-; AHIGH_29_ = BIDIR,6, B,-; AHIGH_28_ = BIDIR,15, C,-; -RST = INPUT,86,-,-; -AHIGH_27_ = BIDIR,16, C,-; -RESET = INPUT,3, B,-; -AHIGH_26_ = BIDIR,17, C,-; -AHIGH_25_ = BIDIR,18, C,-; -AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; -AHIGH_24_ = BIDIR,19, C,-; -AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; -A_DECODE_22_ = INPUT,84, H,-; -AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; -A_DECODE_21_ = INPUT,94, A,-; -AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; -A_DECODE_20_ = INPUT,93, A,-; -CIIN = OUTPUT,47, E,-; -A_DECODE_19_ = INPUT,97, A,-; -A_DECODE_18_ = INPUT,95, A,-; -A_DECODE_17_ = INPUT,59, F,-; -A_DECODE_16_ = INPUT,96, A,-; -A_0_ = BIDIR,69, G,-; SIZE_1_ = BIDIR,79, H,-; -IPL_030_1_ = OUTPUT,7, B,-; -IPL_030_0_ = OUTPUT,8, B,-; IPL_030_2_ = OUTPUT,9, B,-; RW_000 = BIDIR,80, H,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; -SIZE_0_ = BIDIR,70, G,-; +A_0_ = BIDIR,69, G,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; VMA = OUTPUT,35, D,-; RW = BIDIR,71, G,-; -cpu_est_1_ = NODE,6, D,-; -cpu_est_2_ = NODE,14, D,-; -cpu_est_3_ = NODE,2, D,-; +SIZE_0_ = BIDIR,70, G,-; cpu_est_0_ = NODE,9, G,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,9, F,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,5, F,-; -inst_AS_030_D0 = NODE,2, H,-; -inst_AS_030_000_SYNC = NODE,13, B,-; -inst_BGACK_030_INT_D = NODE,13, H,-; -inst_AS_000_DMA = NODE,8, A,-; -inst_DS_000_DMA = NODE,13, A,-; -inst_VPA_D = NODE,2, F,-; +cpu_est_1_ = NODE,13, D,-; +cpu_est_2_ = NODE,2, D,-; +cpu_est_3_ = NODE,8, A,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,10, A,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, C,-; +inst_AS_030_D0 = NODE,8, E,-; +inst_AS_030_D1 = NODE,1, F,-; +inst_AS_030_000_SYNC = NODE,4, F,-; +inst_AS_000_DMA = NODE,13, C,-; +inst_DS_000_DMA = NODE,9, C,-; +inst_VPA_D = NODE,6, G,-; CLK_000_D_3_ = NODE,13, F,-; -inst_DTACK_D0 = NODE,14, B,-; -inst_RESET_OUT = NODE,5, G,-; -CLK_030_PE_1_ = NODE,2, A,-; -inst_AMIGA_DS = NODE,10, C,-; +inst_DTACK_D0 = NODE,9, F,-; +inst_AMIGA_DS = NODE,2, H,-; CLK_000_D_1_ = NODE,5, H,-; -CLK_000_D_0_ = NODE,13, D,-; -inst_CLK_OUT_PRE_50 = NODE,2, G,-; -inst_CLK_OUT_PRE_D = NODE,8, E,-; -IPL_D0_0_ = NODE,10, B,-; -IPL_D0_1_ = NODE,6, B,-; -IPL_D0_2_ = NODE,2, B,-; +CLK_000_D_0_ = NODE,9, D,-; +inst_CLK_OUT_PRE_50 = NODE,13, H,-; +inst_CLK_OUT_PRE_D = NODE,5, E,-; +IPL_D0_0_ = NODE,6, A,-; +IPL_D0_1_ = NODE,6, D,-; +IPL_D0_2_ = NODE,2, A,-; CLK_000_D_2_ = NODE,6, H,-; -CLK_000_D_4_ = NODE,14, C,-; -inst_LDS_000_INT = NODE,12, F,-; -inst_DS_000_ENABLE = NODE,13, C,-; -inst_UDS_000_INT = NODE,1, F,-; +CLK_000_D_4_ = NODE,5, F,-; +inst_UDS_000_INT = NODE,6, B,-; +inst_DS_000_ENABLE = NODE,2, C,-; +inst_LDS_000_INT = NODE,13, G,-; +inst_BGACK_030_INT_D = NODE,13, E,-; SM_AMIGA_6_ = NODE,0, F,-; -SM_AMIGA_4_ = NODE,1, A,-; -SM_AMIGA_1_ = NODE,8, F,-; +SM_AMIGA_4_ = NODE,5, G,-; +SM_AMIGA_1_ = NODE,5, A,-; SM_AMIGA_0_ = NODE,12, A,-; -CYCLE_DMA_0_ = NODE,6, A,-; -CYCLE_DMA_1_ = NODE,10, A,-; -CLK_030_PE_0_ = NODE,9, A,-; -RST_DLY_0_ = NODE,6, G,-; -RST_DLY_1_ = NODE,14, G,-; -RST_DLY_2_ = NODE,10, G,-; -inst_DSACK1_INT = NODE,5, A,-; -inst_AS_000_INT = NODE,2, C,-; -SM_AMIGA_5_ = NODE,13, G,-; -SM_AMIGA_3_ = NODE,6, C,-; -SM_AMIGA_2_ = NODE,9, C,-; -SM_AMIGA_i_7_ = NODE,4, F,-; -CLK_OUT_INTreg = NODE,10, D,-; -CIIN_0 = NODE,5, E,-; +CYCLE_DMA_0_ = NODE,13, B,-; +CYCLE_DMA_1_ = NODE,2, B,-; +inst_DSACK1_INT = NODE,2, G,-; +inst_AS_000_INT = NODE,6, C,-; +SM_AMIGA_5_ = NODE,12, F,-; +SM_AMIGA_3_ = NODE,13, A,-; +SM_AMIGA_2_ = NODE,9, A,-; +CLK_OUT_INTreg = NODE,1, A,-; +SM_AMIGA_i_7_ = NODE,8, F,-; +N_60 = NODE,9, E,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct index 6b2c2e2..5c0b697 100644 --- a/Logic/68030_tk.vct +++ b/Logic/68030_tk.vct @@ -15,8 +15,8 @@ Voltage = 5.0; RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; -DATE = 10/08/2016; -TIME = 22:26:00; +DATE = 02/16/2017; +TIME = 19:15:23; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -224,6 +224,7 @@ Page_Break = Yes; [POWER] Powerlevel = Low,High; Default = High; +High = 1,B; Low = 8,H,G,F,E,D,C,B,A; Type = GLB; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 548fe7d..65e32ff 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Thu Dec 29 16:01:56 2016 +Design '68030_tk' created Sat Dec 30 00:43:37 2017 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index df6413b..cb9b713 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,304 +1,273 @@ -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC SIZE_0_ E AHIGH_30_ VPA AHIGH_29_ VMA AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ RW AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ A_DECODE_12_ A_DECODE_11_ A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ -#$ NODES 609 clk_000_d_i_1__n VPA_D_i N_125_i a_decode_2__n VMA_INT_i N_124_i sm_amiga_i_0__n N_53_0 rst_dly_i_2__n N_134_i \ -# rst_dly_i_1__n N_270_0 rst_dly_i_0__n N_77_i DSACK1_INT_i N_87_i inst_BGACK_030_INTreg N_137_i_0 N_112_i vcc_n_n \ -# DTACK_D0_i N_113_i inst_VMA_INTreg BGACK_030_INT_i N_114_i gnd_n_n nEXP_SPACE_i un1_amiga_bus_enable_low AS_000_DMA_i N_109_i \ -# un7_as_030 RW_000_i N_108_i un1_LDS_000_INT clk_030_pe_i_1__n N_111_i un1_UDS_000_INT DS_000_DMA_0_sqmuxa_i N_265_2_0 un1_SM_AMIGA_0_sqmuxa_1 \ -# pos_clk_un4_rw_000_i_n un10_ciin AS_000_i un1_as_000_i un21_fpu_cs AMIGA_DS_i VPA_c_i un21_berr pos_clk_un3_clk_out_int_i_n N_52_0 \ -# un6_ds_030 cycle_dma_i_0__n DTACK_c_i un13_ciin cycle_dma_i_1__n N_48_0 cpu_est_1_ pos_clk_as_000_dma6_i_n un3_ahigh_i cpu_est_2_ \ -# DS_000_DMA_i pos_clk_un4_bgack_000_i_n cpu_est_3_ CLK_EXP_i pos_clk_un6_bgack_000_0_n cpu_est_0_ AMIGA_BUS_ENABLE_DMA_LOW_i N_7_i inst_AMIGA_BUS_ENABLE_DMA_HIGH ahigh_i_25__n \ -# N_41_0 inst_AMIGA_BUS_ENABLE_DMA_LOW ahigh_i_24__n pos_clk_un1_bgack_030_int_0_n inst_AS_030_D0 ahigh_i_27__n pos_clk_un12_clk_out_int_0_n inst_AS_030_000_SYNC ahigh_i_26__n pos_clk_un3_0_n \ -# inst_BGACK_030_INT_D ahigh_i_29__n pos_clk_un15_bgack_030_int_i_n inst_AS_000_DMA ahigh_i_28__n N_3_i inst_DS_000_DMA ahigh_i_31__n N_43_0 inst_VPA_D \ -# ahigh_i_30__n N_4_i CLK_000_D_3_ a_i_1__n N_42_0 inst_DTACK_D0 AMIGA_BUS_ENABLE_DMA_HIGH_i un6_amiga_bus_data_dir_i inst_RESET_OUT AS_030_D0_i \ -# un12_amiga_bus_data_dir_m_i CLK_030_PE_1_ un10_ciin_i AMIGA_BUS_DATA_DIR_c_0 inst_AMIGA_DS FPU_SENSE_i N_22_i CLK_000_D_1_ AS_030_000_SYNC_i N_31_0 \ -# CLK_000_D_0_ a_decode_i_16__n N_21_i inst_CLK_OUT_PRE_50 a_decode_i_18__n N_32_0 inst_CLK_OUT_PRE_D a_decode_i_19__n N_19_i IPL_D0_0_ \ -# N_224_i N_34_0 IPL_D0_1_ N_225_i N_18_i IPL_D0_2_ N_226_i N_35_0 CLK_000_D_2_ pos_clk_un5_bgack_030_int_d_i_n \ -# CLK_000_D_4_ pos_clk_amiga_bus_enable_dma_high_3_0_n pos_clk_un6_bg_030_n pos_clk_amiga_bus_enable_dma_low_3_0_n pos_clk_ipl_n pos_clk_rw_000_dma_3_0_n inst_LDS_000_INT un13_ciin_i UDS_000_c_i inst_DS_000_ENABLE \ -# un6_ds_030_i LDS_000_c_i inst_UDS_000_INT N_123_i N_86_i SM_AMIGA_6_ N_122_i N_129_i SM_AMIGA_4_ un7_as_030_i \ -# N_130_i SM_AMIGA_1_ AS_030_c un11_amiga_bus_enable_high_i SM_AMIGA_0_ N_117_i SIZE_DMA_0_ AS_000_c N_46_0 SIZE_DMA_1_ \ -# N_107_i CYCLE_DMA_0_ RW_000_c pos_clk_size_dma_6_0_0__n CYCLE_DMA_1_ N_106_i CLK_030_PE_0_ pos_clk_size_dma_6_0_1__n inst_RW_000_INT UDS_000_c \ -# N_16_i inst_RW_000_DMA N_254_i RST_DLY_0_ LDS_000_c N_263_i RST_DLY_1_ N_250_i RST_DLY_2_ size_c_0__n \ -# N_256_i inst_A0_DMA N_189_i pos_clk_rw_000_int_5_n size_c_1__n N_101_i inst_DSACK1_INT inst_AS_000_INT ahigh_c_24__n N_103_i \ -# SM_AMIGA_5_ N_104_i SM_AMIGA_3_ ahigh_c_25__n SM_AMIGA_2_ N_105_i ahigh_c_26__n N_115_i ahigh_c_27__n N_116_i \ -# ahigh_c_28__n N_131_i N_277_i ahigh_c_29__n N_64_0 N_91_0 ahigh_c_30__n N_159_0 N_14 N_85_i \ -# N_15 ahigh_c_31__n un1_SM_AMIGA_0_sqmuxa_1_0 N_24 RW_c_i N_25 pos_clk_rw_000_int_5_0_n clk_000_d_i_3__n N_25_i N_28_0 \ -# N_24_i N_27_0 ipl_c_i_1__n N_50_0 ipl_c_i_0__n N_49_0 N_14_i N_39_0 N_15_i N_38_0 \ -# N_91_0_1 N_91_0_2 N_91_0_3 N_265_i_1 N_266_i_1 N_266_i_2 N_138_i_1 N_148_i_1 N_144_i_1 N_142_i_1 \ -# N_140_i_1 SM_AMIGA_i_7_ pos_clk_un10_sm_amiga_i_1_n N_76 N_85_i_1 G_122 N_85_i_2 G_123 a_decode_c_16__n N_277_1 \ -# G_124 N_277_2 un1_rst_2_1 a_decode_c_17__n N_277_3 cpu_est_0_0_ N_277_4 N_64 a_decode_c_18__n N_277_5 \ -# N_122 un10_ciin_1 N_123 a_decode_c_19__n un10_ciin_2 N_132 un10_ciin_3 N_133 a_decode_c_20__n un10_ciin_4 \ -# N_274 un10_ciin_5 N_276 a_decode_c_21__n un10_ciin_6 N_77 un10_ciin_7 N_79 a_decode_c_22__n un10_ciin_8 \ -# N_78 un10_ciin_9 N_263 a_decode_c_23__n un10_ciin_10 N_108 un10_ciin_11 N_114 a_c_0__n un6_amiga_bus_data_dir_1 \ -# N_85 un6_amiga_bus_data_dir_2 N_104 a_c_1__n pos_clk_as_000_dma6_1_n N_91 pos_clk_as_000_dma6_2_n N_131 nEXP_SPACE_c DS_000_DMA_1_sqmuxa_1 \ -# N_277 pos_clk_un4_rw_000_1_n N_130 BERR_c pos_clk_un4_rw_000_2_n N_115 pos_clk_un13_clk_out_int_1_n N_116 BG_030_c N_125_1 \ -# N_105 N_116_1 N_103 BG_000DFFreg pos_clk_un29_clk_000_ne_1_1_n N_101 pos_clk_un29_clk_000_ne_1_2_n N_259 pos_clk_un29_clk_000_ne_1_3_n N_255 \ -# BGACK_000_c N_261_1 N_256 N_261_2 N_254 CLK_030_c N_262_1 N_16 N_262_2 N_106 \ -# DS_000_ENABLE_0_sqmuxa_1_1 N_86 N_259_1 N_107 CLK_OSZI_c N_250_i_1 N_117 N_189_i_1 pos_clk_a0_dma_3_n pos_clk_un6_bg_030_1_n \ -# N_129 CLK_OUT_INTreg N_108_1 pos_clk_size_dma_6_1__n N_114_1 pos_clk_size_dma_6_0__n un21_berr_1 pos_clk_rw_000_dma_3_n FPU_SENSE_c un21_fpu_cs_1 \ -# pos_clk_amiga_bus_enable_dma_low_3_n N_130_1 pos_clk_amiga_bus_enable_dma_high_3_n IPL_030DFF_0_reg N_136_i_1 SIZE_DMA_3_sqmuxa N_152_i_1 pos_clk_un5_bgack_030_int_d_n IPL_030DFF_1_reg N_146_i_1 \ -# N_18 N_267_i_1 N_19 IPL_030DFF_2_reg pos_clk_ipl_1_n N_21 bg_000_0_un3_n N_22 ipl_c_0__n bg_000_0_un1_n \ -# un6_amiga_bus_data_dir bg_000_0_un0_n un12_amiga_bus_data_dir_m ipl_c_1__n uds_000_int_0_un3_n pos_clk_un3_clk_out_int_n uds_000_int_0_un1_n N_3 ipl_c_2__n uds_000_int_0_un0_n \ -# pos_clk_as_000_dma6_n lds_000_int_0_un3_n DS_000_DMA_1_sqmuxa lds_000_int_0_un1_n N_4 DTACK_c lds_000_int_0_un0_n AS_000_DMA_1_sqmuxa ds_000_enable_0_un3_n un1_rst_2 \ -# ds_000_enable_0_un1_n G_97 ds_000_enable_0_un0_n N_199 VPA_c ipl_030_0_2__un3_n pos_clk_un13_bgack_030_int_n ipl_030_0_2__un1_n N_205 ipl_030_0_2__un0_n \ -# pos_clk_un13_clk_out_int_n RST_c vma_int_0_un3_n pos_clk_un15_bgack_030_int_n vma_int_0_un1_n pos_clk_un3_n RESET_c vma_int_0_un0_n pos_clk_un12_clk_out_int_n cpu_est_0_1__un3_n \ -# pos_clk_un1_bgack_030_int_n RW_c cpu_est_0_1__un1_n DS_000_DMA_0_sqmuxa cpu_est_0_1__un0_n un1_rst_3 fc_c_0__n cpu_est_0_2__un3_n G_95 cpu_est_0_2__un1_n \ -# G_101 fc_c_1__n cpu_est_0_2__un0_n G_103 cpu_est_0_3__un3_n pos_clk_un4_rw_000_n cpu_est_0_3__un1_n N_7 AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un0_n \ -# pos_clk_un6_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un3_n pos_clk_un4_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un1_n N_265_2 pos_clk_un31_clk_000_ne_1_i_m2_un0_n N_111 bgack_030_int_0_un3_n N_109 BG_030_c_i \ -# bgack_030_int_0_un1_n N_113 pos_clk_un6_bg_030_i_n bgack_030_int_0_un0_n N_112 pos_clk_un9_bg_030_0_n ds_000_dma_0_un3_n N_98 UDS_000_INT_i ds_000_dma_0_un1_n \ -# pos_clk_un29_clk_000_ne_1_n un1_UDS_000_INT_0 ds_000_dma_0_un0_n N_87 LDS_000_INT_i as_000_dma_0_un3_n N_270 un1_LDS_000_INT_0 as_000_dma_0_un1_n N_134 \ -# N_23_i as_000_dma_0_un0_n N_125 N_30_0 size_dma_0_1__un3_n N_124 N_20_i size_dma_0_1__un1_n N_121 N_33_0 \ -# size_dma_0_1__un0_n N_120 N_13_i size_dma_0_0__un3_n N_137 N_40_0 size_dma_0_0__un1_n pos_clk_un31_clk_000_ne_n ipl_c_i_2__n size_dma_0_0__un0_n \ -# N_17 N_51_0 amiga_bus_enable_dma_high_0_un3_n pos_clk_un9_clk_000_pe_n N_26_i amiga_bus_enable_dma_high_0_un1_n cpu_est_2_1__n N_29_0 amiga_bus_enable_dma_high_0_un0_n cpu_est_2_2__n \ -# a_c_i_0__n amiga_bus_enable_dma_low_0_un3_n N_261 size_c_i_1__n amiga_bus_enable_dma_low_0_un1_n N_262 pos_clk_un10_sm_amiga_i_n amiga_bus_enable_dma_low_0_un0_n N_251 DS_000_ENABLE_0_sqmuxa_1_i \ -# a0_dma_0_un3_n N_252 un1_DS_000_ENABLE_0_sqmuxa_i a0_dma_0_un1_n N_258 N_157_i a0_dma_0_un0_n N_257 N_160_0 rw_000_dma_0_un3_n \ -# DS_000_ENABLE_1_sqmuxa N_161_0 rw_000_dma_0_un1_n un1_DS_000_ENABLE_0_sqmuxa N_162_0 rw_000_dma_0_un0_n N_102 N_165_i ipl_030_0_0__un3_n N_118 \ -# ipl_030_0_0__un1_n N_119 N_167_i ipl_030_0_0__un0_n N_264 N_166_i ipl_030_0_1__un3_n DS_000_ENABLE_0_sqmuxa_1 ipl_030_0_1__un1_n N_164 \ -# N_168_i ipl_030_0_1__un0_n N_170 as_030_000_sync_0_un3_n N_168 N_170_i as_030_000_sync_0_un1_n N_166 as_030_000_sync_0_un0_n N_167 \ -# N_164_i rw_000_int_0_un3_n N_165 rw_000_int_0_un1_n N_162 N_102_i rw_000_int_0_un0_n N_161 N_264_i a_decode_15__n \ -# N_160 N_79_i N_157 N_78_i a_decode_14__n N_26 N_119_i N_13 N_118_i a_decode_13__n \ -# N_20 N_23 N_255_i a_decode_12__n N_8 N_257_i pos_clk_un9_bg_030_n cpu_est_2_0_2__n a_decode_11__n un1_amiga_bus_enable_low_i \ -# N_258_i un21_fpu_cs_i N_259_i a_decode_10__n sm_amiga_i_2__n cpu_est_2_0_1__n sm_amiga_i_1__n N_262_i a_decode_9__n sm_amiga_i_3__n \ -# N_261_i sm_amiga_i_4__n pos_clk_un9_clk_000_pe_0_n a_decode_8__n sm_amiga_i_6__n N_251_i sm_amiga_i_5__n N_252_0 a_decode_7__n clk_000_d_i_0__n \ -# N_76_i AS_000_INT_i N_17_i a_decode_6__n sm_amiga_i_i_7__n N_36_0 AS_030_i N_98_i a_decode_5__n cpu_est_i_2__n \ -# pos_clk_un31_clk_000_ne_i_n cpu_est_i_0__n N_228_i a_decode_4__n cpu_est_i_3__n N_121_i cpu_est_i_1__n N_120_i a_decode_3__n +#$ PINS 75 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ IPL_030_2_ A_DECODE_16_ A_DECODE_15_ IPL_2_ A_DECODE_14_ A_DECODE_13_ FC_1_ A_DECODE_12_ AS_030 A_DECODE_11_ AS_000 A_DECODE_10_ RW_000 A_DECODE_9_ DS_030 A_DECODE_8_ UDS_000 A_DECODE_7_ LDS_000 A_DECODE_6_ nEXP_SPACE A_DECODE_5_ BERR A_DECODE_4_ BG_030 A_DECODE_3_ BG_000 A_DECODE_2_ BGACK_030 A_0_ BGACK_000 IPL_030_1_ CLK_030 IPL_030_0_ CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ +#$ NODES 508 N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 \ +# size_c_1__n ipl_c_i_1__n inst_BGACK_030_INTreg N_42_0 vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n \ +# ahigh_c_25__n DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i un1_UDS_000_INT N_44_0 un1_LDS_000_INT \ +# ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr \ +# ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 cpu_est_0_ ahigh_c_30__n N_96_0_1 cpu_est_1_ N_96_0_2 cpu_est_2_ \ +# ahigh_c_31__n N_282_0_1 cpu_est_3_ N_282_0_2 inst_AMIGA_BUS_ENABLE_DMA_HIGH N_282_0_3 inst_AMIGA_BUS_ENABLE_DMA_LOW N_282_0_4 inst_AS_030_D0 pos_clk_un10_sm_amiga_i_1_n \ +# inst_AS_030_D1 un10_ciin_1 inst_AS_030_000_SYNC un10_ciin_2 inst_AS_000_DMA un10_ciin_3 inst_DS_000_DMA un10_ciin_4 inst_VMA_INTreg un10_ciin_5 \ +# inst_VPA_D un10_ciin_6 CLK_000_D_3_ un10_ciin_7 inst_DTACK_D0 un10_ciin_8 inst_AMIGA_DS un10_ciin_9 CLK_000_D_1_ un10_ciin_10 \ +# CLK_000_D_0_ un10_ciin_11 inst_CLK_OUT_PRE_50 N_201_1 inst_CLK_OUT_PRE_D N_201_2 IPL_D0_0_ N_131_i_1 IPL_D0_1_ N_134_0_1 \ +# IPL_D0_2_ N_113_i_1 CLK_000_D_2_ N_113_i_2 CLK_000_D_4_ N_144_1 pos_clk_ipl_n N_144_2 SIZE_DMA_0_ N_143_1 \ +# SIZE_DMA_1_ N_143_2 inst_A0_DMA N_163_1 inst_RW_000_DMA N_163_2 inst_UDS_000_INT N_163_3 inst_DS_000_ENABLE un21_fpu_cs_1 \ +# inst_LDS_000_INT a_decode_c_16__n un21_berr_1_0 inst_BGACK_030_INT_D pos_clk_cycle_dma_5_1_1__n SM_AMIGA_6_ a_decode_c_17__n N_199_1 inst_RW_000_INT AS_000_DMA_1_sqmuxa_1 \ +# SM_AMIGA_4_ a_decode_c_18__n N_140_1 SM_AMIGA_1_ N_66_i_1 SM_AMIGA_0_ a_decode_c_19__n N_66_i_2 CYCLE_DMA_0_ N_205_i_1 \ +# CYCLE_DMA_1_ a_decode_c_20__n N_205_i_2 inst_DSACK1_INT N_180_1 inst_AS_000_INT a_decode_c_21__n N_180_2 pos_clk_un9_clk_000_pe_n N_59_i_1 \ +# SM_AMIGA_5_ a_decode_c_22__n N_127_i_1 SM_AMIGA_3_ N_123_i_1 SM_AMIGA_2_ a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 \ +# a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 \ +# N_18 BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n ds_000_dma_0_un0_n BG_000DFFreg \ +# as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n \ +# CLK_OSZI_c lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n CLK_OUT_INTreg as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n \ +# rw_000_int_0_un1_n IPL_030DFF_0_reg rw_000_int_0_un0_n as_030_000_sync_0_un3_n IPL_030DFF_1_reg as_030_000_sync_0_un1_n SM_AMIGA_i_7_ as_030_000_sync_0_un0_n IPL_030DFF_2_reg bgack_030_int_0_un3_n \ +# bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n G_105 \ +# cpu_est_0_1__un0_n G_106 ipl_c_2__n cpu_est_0_2__un3_n G_107 cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c \ +# cpu_est_0_3__un3_n N_126 cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c ipl_030_0_0__un1_n \ +# N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n \ +# N_80 ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 fc_c_0__n ds_000_enable_0_un1_n \ +# N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ +# AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 a_decode_13__n N_146 N_205_i \ +# N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 a_decode_11__n N_154 N_199_i N_155 \ +# N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 \ +# pos_clk_un2_i_n a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 \ +# N_31_0 a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 \ +# N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 \ +# N_15_i a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i \ +# N_282 N_29_0 un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n \ +# un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 N_244_0 \ +# pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 \ +# N_5 N_274_i N_11 pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i \ +# N_17 N_167_i pos_clk_un9_bg_030_n G_91 N_170_i N_3 N_169_i N_205 AS_000_DMA_1_sqmuxa N_38_0 \ +# N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 N_262 N_129_i \ +# N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i BGACK_030_INT_i \ +# N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ +# UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n \ +# N_201_i a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n \ +# N_82_i sm_amiga_i_6__n N_80_i sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i \ +# N_190_i sm_amiga_i_1__n N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i VPA_D_i \ +# sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i \ +# cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n \ +# pos_clk_size_dma_6_0_1__n ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 ahigh_i_24__n N_155_i ahigh_i_25__n \ +# N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n \ +# N_147_i un2_ds_030_i N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c \ +# N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i .model bus68030 -.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ - FPU_SENSE.BLIF VPA.BLIF RST.BLIF RESET.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ - A_DECODE_17_.BLIF A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ - A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ - FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF clk_000_d_i_1__n.BLIF VPA_D_i.BLIF N_125_i.BLIF a_decode_2__n.BLIF VMA_INT_i.BLIF N_124_i.BLIF sm_amiga_i_0__n.BLIF \ - N_53_0.BLIF rst_dly_i_2__n.BLIF N_134_i.BLIF rst_dly_i_1__n.BLIF N_270_0.BLIF rst_dly_i_0__n.BLIF N_77_i.BLIF DSACK1_INT_i.BLIF N_87_i.BLIF \ - inst_BGACK_030_INTreg.BLIF N_137_i_0.BLIF N_112_i.BLIF vcc_n_n.BLIF DTACK_D0_i.BLIF N_113_i.BLIF inst_VMA_INTreg.BLIF BGACK_030_INT_i.BLIF N_114_i.BLIF \ - gnd_n_n.BLIF nEXP_SPACE_i.BLIF un1_amiga_bus_enable_low.BLIF AS_000_DMA_i.BLIF N_109_i.BLIF un7_as_030.BLIF RW_000_i.BLIF N_108_i.BLIF un1_LDS_000_INT.BLIF \ - clk_030_pe_i_1__n.BLIF N_111_i.BLIF un1_UDS_000_INT.BLIF DS_000_DMA_0_sqmuxa_i.BLIF N_265_2_0.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF pos_clk_un4_rw_000_i_n.BLIF un10_ciin.BLIF AS_000_i.BLIF \ - un1_as_000_i.BLIF un21_fpu_cs.BLIF AMIGA_DS_i.BLIF VPA_c_i.BLIF un21_berr.BLIF pos_clk_un3_clk_out_int_i_n.BLIF N_52_0.BLIF un6_ds_030.BLIF cycle_dma_i_0__n.BLIF \ - DTACK_c_i.BLIF un13_ciin.BLIF cycle_dma_i_1__n.BLIF N_48_0.BLIF cpu_est_1_.BLIF pos_clk_as_000_dma6_i_n.BLIF un3_ahigh_i.BLIF cpu_est_2_.BLIF DS_000_DMA_i.BLIF \ - pos_clk_un4_bgack_000_i_n.BLIF cpu_est_3_.BLIF CLK_EXP_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_7_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF ahigh_i_25__n.BLIF \ - N_41_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF ahigh_i_24__n.BLIF pos_clk_un1_bgack_030_int_0_n.BLIF inst_AS_030_D0.BLIF ahigh_i_27__n.BLIF pos_clk_un12_clk_out_int_0_n.BLIF inst_AS_030_000_SYNC.BLIF ahigh_i_26__n.BLIF \ - pos_clk_un3_0_n.BLIF inst_BGACK_030_INT_D.BLIF ahigh_i_29__n.BLIF pos_clk_un15_bgack_030_int_i_n.BLIF inst_AS_000_DMA.BLIF ahigh_i_28__n.BLIF N_3_i.BLIF inst_DS_000_DMA.BLIF ahigh_i_31__n.BLIF \ - N_43_0.BLIF inst_VPA_D.BLIF ahigh_i_30__n.BLIF N_4_i.BLIF CLK_000_D_3_.BLIF a_i_1__n.BLIF N_42_0.BLIF inst_DTACK_D0.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ - un6_amiga_bus_data_dir_i.BLIF inst_RESET_OUT.BLIF AS_030_D0_i.BLIF un12_amiga_bus_data_dir_m_i.BLIF CLK_030_PE_1_.BLIF un10_ciin_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF inst_AMIGA_DS.BLIF FPU_SENSE_i.BLIF \ - N_22_i.BLIF CLK_000_D_1_.BLIF AS_030_000_SYNC_i.BLIF N_31_0.BLIF CLK_000_D_0_.BLIF a_decode_i_16__n.BLIF N_21_i.BLIF inst_CLK_OUT_PRE_50.BLIF a_decode_i_18__n.BLIF \ - N_32_0.BLIF inst_CLK_OUT_PRE_D.BLIF a_decode_i_19__n.BLIF N_19_i.BLIF IPL_D0_0_.BLIF N_224_i.BLIF N_34_0.BLIF IPL_D0_1_.BLIF N_225_i.BLIF \ - N_18_i.BLIF IPL_D0_2_.BLIF N_226_i.BLIF N_35_0.BLIF CLK_000_D_2_.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF CLK_000_D_4_.BLIF pos_clk_amiga_bus_enable_dma_high_3_0_n.BLIF pos_clk_un6_bg_030_n.BLIF \ - pos_clk_amiga_bus_enable_dma_low_3_0_n.BLIF pos_clk_ipl_n.BLIF pos_clk_rw_000_dma_3_0_n.BLIF inst_LDS_000_INT.BLIF un13_ciin_i.BLIF UDS_000_c_i.BLIF inst_DS_000_ENABLE.BLIF un6_ds_030_i.BLIF LDS_000_c_i.BLIF \ - inst_UDS_000_INT.BLIF N_123_i.BLIF N_86_i.BLIF SM_AMIGA_6_.BLIF N_122_i.BLIF N_129_i.BLIF SM_AMIGA_4_.BLIF un7_as_030_i.BLIF N_130_i.BLIF \ - SM_AMIGA_1_.BLIF AS_030_c.BLIF un11_amiga_bus_enable_high_i.BLIF SM_AMIGA_0_.BLIF N_117_i.BLIF SIZE_DMA_0_.BLIF AS_000_c.BLIF N_46_0.BLIF SIZE_DMA_1_.BLIF \ - N_107_i.BLIF CYCLE_DMA_0_.BLIF RW_000_c.BLIF pos_clk_size_dma_6_0_0__n.BLIF CYCLE_DMA_1_.BLIF N_106_i.BLIF CLK_030_PE_0_.BLIF pos_clk_size_dma_6_0_1__n.BLIF inst_RW_000_INT.BLIF \ - UDS_000_c.BLIF N_16_i.BLIF inst_RW_000_DMA.BLIF N_254_i.BLIF RST_DLY_0_.BLIF LDS_000_c.BLIF N_263_i.BLIF RST_DLY_1_.BLIF N_250_i.BLIF \ - RST_DLY_2_.BLIF size_c_0__n.BLIF N_256_i.BLIF inst_A0_DMA.BLIF N_189_i.BLIF pos_clk_rw_000_int_5_n.BLIF size_c_1__n.BLIF N_101_i.BLIF inst_DSACK1_INT.BLIF \ - inst_AS_000_INT.BLIF ahigh_c_24__n.BLIF N_103_i.BLIF SM_AMIGA_5_.BLIF N_104_i.BLIF SM_AMIGA_3_.BLIF ahigh_c_25__n.BLIF SM_AMIGA_2_.BLIF N_105_i.BLIF \ - ahigh_c_26__n.BLIF N_115_i.BLIF ahigh_c_27__n.BLIF N_116_i.BLIF ahigh_c_28__n.BLIF N_131_i.BLIF N_277_i.BLIF ahigh_c_29__n.BLIF N_64_0.BLIF \ - N_91_0.BLIF ahigh_c_30__n.BLIF N_159_0.BLIF N_14.BLIF N_85_i.BLIF N_15.BLIF ahigh_c_31__n.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_24.BLIF \ - RW_c_i.BLIF N_25.BLIF pos_clk_rw_000_int_5_0_n.BLIF clk_000_d_i_3__n.BLIF N_25_i.BLIF N_28_0.BLIF N_24_i.BLIF N_27_0.BLIF ipl_c_i_1__n.BLIF \ - N_50_0.BLIF ipl_c_i_0__n.BLIF N_49_0.BLIF N_14_i.BLIF N_39_0.BLIF N_15_i.BLIF N_38_0.BLIF N_91_0_1.BLIF N_91_0_2.BLIF \ - N_91_0_3.BLIF N_265_i_1.BLIF N_266_i_1.BLIF N_266_i_2.BLIF N_138_i_1.BLIF N_148_i_1.BLIF N_144_i_1.BLIF N_142_i_1.BLIF N_140_i_1.BLIF \ - SM_AMIGA_i_7_.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_76.BLIF N_85_i_1.BLIF G_122.BLIF N_85_i_2.BLIF G_123.BLIF a_decode_c_16__n.BLIF N_277_1.BLIF \ - G_124.BLIF N_277_2.BLIF un1_rst_2_1.BLIF a_decode_c_17__n.BLIF N_277_3.BLIF cpu_est_0_0_.BLIF N_277_4.BLIF N_64.BLIF a_decode_c_18__n.BLIF \ - N_277_5.BLIF N_122.BLIF un10_ciin_1.BLIF N_123.BLIF a_decode_c_19__n.BLIF un10_ciin_2.BLIF N_132.BLIF un10_ciin_3.BLIF N_133.BLIF \ - a_decode_c_20__n.BLIF un10_ciin_4.BLIF N_274.BLIF un10_ciin_5.BLIF N_276.BLIF a_decode_c_21__n.BLIF un10_ciin_6.BLIF N_77.BLIF un10_ciin_7.BLIF \ - N_79.BLIF a_decode_c_22__n.BLIF un10_ciin_8.BLIF N_78.BLIF un10_ciin_9.BLIF N_263.BLIF a_decode_c_23__n.BLIF un10_ciin_10.BLIF N_108.BLIF \ - un10_ciin_11.BLIF N_114.BLIF a_c_0__n.BLIF un6_amiga_bus_data_dir_1.BLIF N_85.BLIF un6_amiga_bus_data_dir_2.BLIF N_104.BLIF a_c_1__n.BLIF pos_clk_as_000_dma6_1_n.BLIF \ - N_91.BLIF pos_clk_as_000_dma6_2_n.BLIF N_131.BLIF nEXP_SPACE_c.BLIF DS_000_DMA_1_sqmuxa_1.BLIF N_277.BLIF pos_clk_un4_rw_000_1_n.BLIF N_130.BLIF BERR_c.BLIF \ - pos_clk_un4_rw_000_2_n.BLIF N_115.BLIF pos_clk_un13_clk_out_int_1_n.BLIF N_116.BLIF BG_030_c.BLIF N_125_1.BLIF N_105.BLIF N_116_1.BLIF N_103.BLIF \ - BG_000DFFreg.BLIF pos_clk_un29_clk_000_ne_1_1_n.BLIF N_101.BLIF pos_clk_un29_clk_000_ne_1_2_n.BLIF N_259.BLIF pos_clk_un29_clk_000_ne_1_3_n.BLIF N_255.BLIF BGACK_000_c.BLIF N_261_1.BLIF \ - N_256.BLIF N_261_2.BLIF N_254.BLIF CLK_030_c.BLIF N_262_1.BLIF N_16.BLIF N_262_2.BLIF N_106.BLIF DS_000_ENABLE_0_sqmuxa_1_1.BLIF \ - N_86.BLIF N_259_1.BLIF N_107.BLIF CLK_OSZI_c.BLIF N_250_i_1.BLIF N_117.BLIF N_189_i_1.BLIF pos_clk_a0_dma_3_n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ - N_129.BLIF CLK_OUT_INTreg.BLIF N_108_1.BLIF pos_clk_size_dma_6_1__n.BLIF N_114_1.BLIF pos_clk_size_dma_6_0__n.BLIF un21_berr_1.BLIF pos_clk_rw_000_dma_3_n.BLIF FPU_SENSE_c.BLIF \ - un21_fpu_cs_1.BLIF pos_clk_amiga_bus_enable_dma_low_3_n.BLIF N_130_1.BLIF pos_clk_amiga_bus_enable_dma_high_3_n.BLIF IPL_030DFF_0_reg.BLIF N_136_i_1.BLIF SIZE_DMA_3_sqmuxa.BLIF N_152_i_1.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ - IPL_030DFF_1_reg.BLIF N_146_i_1.BLIF N_18.BLIF N_267_i_1.BLIF N_19.BLIF IPL_030DFF_2_reg.BLIF pos_clk_ipl_1_n.BLIF N_21.BLIF bg_000_0_un3_n.BLIF \ - N_22.BLIF ipl_c_0__n.BLIF bg_000_0_un1_n.BLIF un6_amiga_bus_data_dir.BLIF bg_000_0_un0_n.BLIF un12_amiga_bus_data_dir_m.BLIF ipl_c_1__n.BLIF uds_000_int_0_un3_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ - uds_000_int_0_un1_n.BLIF N_3.BLIF ipl_c_2__n.BLIF uds_000_int_0_un0_n.BLIF pos_clk_as_000_dma6_n.BLIF lds_000_int_0_un3_n.BLIF DS_000_DMA_1_sqmuxa.BLIF lds_000_int_0_un1_n.BLIF N_4.BLIF \ - DTACK_c.BLIF lds_000_int_0_un0_n.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_enable_0_un3_n.BLIF un1_rst_2.BLIF ds_000_enable_0_un1_n.BLIF G_97.BLIF ds_000_enable_0_un0_n.BLIF N_199.BLIF \ - VPA_c.BLIF ipl_030_0_2__un3_n.BLIF pos_clk_un13_bgack_030_int_n.BLIF ipl_030_0_2__un1_n.BLIF N_205.BLIF ipl_030_0_2__un0_n.BLIF pos_clk_un13_clk_out_int_n.BLIF RST_c.BLIF vma_int_0_un3_n.BLIF \ - pos_clk_un15_bgack_030_int_n.BLIF vma_int_0_un1_n.BLIF pos_clk_un3_n.BLIF RESET_c.BLIF vma_int_0_un0_n.BLIF pos_clk_un12_clk_out_int_n.BLIF cpu_est_0_1__un3_n.BLIF pos_clk_un1_bgack_030_int_n.BLIF RW_c.BLIF \ - cpu_est_0_1__un1_n.BLIF DS_000_DMA_0_sqmuxa.BLIF cpu_est_0_1__un0_n.BLIF un1_rst_3.BLIF fc_c_0__n.BLIF cpu_est_0_2__un3_n.BLIF G_95.BLIF cpu_est_0_2__un1_n.BLIF G_101.BLIF \ - fc_c_1__n.BLIF cpu_est_0_2__un0_n.BLIF G_103.BLIF cpu_est_0_3__un3_n.BLIF pos_clk_un4_rw_000_n.BLIF cpu_est_0_3__un1_n.BLIF N_7.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_3__un0_n.BLIF \ - pos_clk_un6_bgack_000_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un3_n.BLIF pos_clk_un4_bgack_000_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un1_n.BLIF N_265_2.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un0_n.BLIF N_111.BLIF bgack_030_int_0_un3_n.BLIF N_109.BLIF \ - BG_030_c_i.BLIF bgack_030_int_0_un1_n.BLIF N_113.BLIF pos_clk_un6_bg_030_i_n.BLIF bgack_030_int_0_un0_n.BLIF N_112.BLIF pos_clk_un9_bg_030_0_n.BLIF ds_000_dma_0_un3_n.BLIF N_98.BLIF \ - UDS_000_INT_i.BLIF ds_000_dma_0_un1_n.BLIF pos_clk_un29_clk_000_ne_1_n.BLIF un1_UDS_000_INT_0.BLIF ds_000_dma_0_un0_n.BLIF N_87.BLIF LDS_000_INT_i.BLIF as_000_dma_0_un3_n.BLIF N_270.BLIF \ - un1_LDS_000_INT_0.BLIF as_000_dma_0_un1_n.BLIF N_134.BLIF N_23_i.BLIF as_000_dma_0_un0_n.BLIF N_125.BLIF N_30_0.BLIF size_dma_0_1__un3_n.BLIF N_124.BLIF \ - N_20_i.BLIF size_dma_0_1__un1_n.BLIF N_121.BLIF N_33_0.BLIF size_dma_0_1__un0_n.BLIF N_120.BLIF N_13_i.BLIF size_dma_0_0__un3_n.BLIF N_137.BLIF \ - N_40_0.BLIF size_dma_0_0__un1_n.BLIF pos_clk_un31_clk_000_ne_n.BLIF ipl_c_i_2__n.BLIF size_dma_0_0__un0_n.BLIF N_17.BLIF N_51_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ - N_26_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF cpu_est_2_1__n.BLIF N_29_0.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF cpu_est_2_2__n.BLIF a_c_i_0__n.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF N_261.BLIF \ - size_c_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_262.BLIF pos_clk_un10_sm_amiga_i_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_251.BLIF DS_000_ENABLE_0_sqmuxa_1_i.BLIF a0_dma_0_un3_n.BLIF N_252.BLIF \ - un1_DS_000_ENABLE_0_sqmuxa_i.BLIF a0_dma_0_un1_n.BLIF N_258.BLIF N_157_i.BLIF a0_dma_0_un0_n.BLIF N_257.BLIF N_160_0.BLIF rw_000_dma_0_un3_n.BLIF DS_000_ENABLE_1_sqmuxa.BLIF \ - N_161_0.BLIF rw_000_dma_0_un1_n.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_162_0.BLIF rw_000_dma_0_un0_n.BLIF N_102.BLIF N_165_i.BLIF ipl_030_0_0__un3_n.BLIF N_118.BLIF \ - ipl_030_0_0__un1_n.BLIF N_119.BLIF N_167_i.BLIF ipl_030_0_0__un0_n.BLIF N_264.BLIF N_166_i.BLIF ipl_030_0_1__un3_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF ipl_030_0_1__un1_n.BLIF \ - N_164.BLIF N_168_i.BLIF ipl_030_0_1__un0_n.BLIF N_170.BLIF as_030_000_sync_0_un3_n.BLIF N_168.BLIF N_170_i.BLIF as_030_000_sync_0_un1_n.BLIF N_166.BLIF \ - as_030_000_sync_0_un0_n.BLIF N_167.BLIF N_164_i.BLIF rw_000_int_0_un3_n.BLIF N_165.BLIF rw_000_int_0_un1_n.BLIF N_162.BLIF N_102_i.BLIF rw_000_int_0_un0_n.BLIF \ - N_161.BLIF N_264_i.BLIF a_decode_15__n.BLIF N_160.BLIF N_79_i.BLIF N_157.BLIF N_78_i.BLIF a_decode_14__n.BLIF N_26.BLIF \ - N_119_i.BLIF N_13.BLIF N_118_i.BLIF a_decode_13__n.BLIF N_20.BLIF N_23.BLIF N_255_i.BLIF a_decode_12__n.BLIF N_8.BLIF \ - N_257_i.BLIF pos_clk_un9_bg_030_n.BLIF cpu_est_2_0_2__n.BLIF a_decode_11__n.BLIF un1_amiga_bus_enable_low_i.BLIF N_258_i.BLIF un21_fpu_cs_i.BLIF N_259_i.BLIF a_decode_10__n.BLIF \ - sm_amiga_i_2__n.BLIF cpu_est_2_0_1__n.BLIF sm_amiga_i_1__n.BLIF N_262_i.BLIF a_decode_9__n.BLIF sm_amiga_i_3__n.BLIF N_261_i.BLIF sm_amiga_i_4__n.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF \ - a_decode_8__n.BLIF sm_amiga_i_6__n.BLIF N_251_i.BLIF sm_amiga_i_5__n.BLIF N_252_0.BLIF a_decode_7__n.BLIF clk_000_d_i_0__n.BLIF N_76_i.BLIF AS_000_INT_i.BLIF \ - N_17_i.BLIF a_decode_6__n.BLIF sm_amiga_i_i_7__n.BLIF N_36_0.BLIF AS_030_i.BLIF N_98_i.BLIF a_decode_5__n.BLIF cpu_est_i_2__n.BLIF pos_clk_un31_clk_000_ne_i_n.BLIF \ - cpu_est_i_0__n.BLIF N_228_i.BLIF a_decode_4__n.BLIF cpu_est_i_3__n.BLIF N_121_i.BLIF cpu_est_i_1__n.BLIF N_120_i.BLIF a_decode_3__n.BLIF AS_030.PIN \ - AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN \ - AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN DTACK.PIN RW.PIN +.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ + DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ + A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF A_DECODE_8_.BLIF \ + A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ + A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_23_0.BLIF UDS_000_c.BLIF N_19_i.BLIF N_22_0.BLIF LDS_000_c.BLIF N_18_i.BLIF N_21_0.BLIF size_c_0__n.BLIF \ + ipl_c_i_2__n.BLIF N_43_0.BLIF size_c_1__n.BLIF ipl_c_i_1__n.BLIF inst_BGACK_030_INTreg.BLIF N_42_0.BLIF vcc_n_n.BLIF ahigh_c_24__n.BLIF ipl_c_i_0__n.BLIF \ + un5_e.BLIF N_41_0.BLIF gnd_n_n.BLIF ahigh_c_25__n.BLIF DTACK_c_i.BLIF un1_amiga_bus_enable_low.BLIF N_45_0.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF \ + VPA_c_i.BLIF un1_UDS_000_INT.BLIF N_44_0.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF N_13_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_27_0.BLIF un10_ciin.BLIF \ + ahigh_c_28__n.BLIF LDS_000_INT_i.BLIF un21_fpu_cs.BLIF un1_LDS_000_INT_0.BLIF un21_berr.BLIF ahigh_c_29__n.BLIF UDS_000_INT_i.BLIF un2_ds_030.BLIF un1_UDS_000_INT_0.BLIF \ + cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_96_0_1.BLIF cpu_est_1_.BLIF N_96_0_2.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF N_282_0_1.BLIF cpu_est_3_.BLIF \ + N_282_0_2.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_282_0_3.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_282_0_4.BLIF inst_AS_030_D0.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF inst_AS_030_D1.BLIF un10_ciin_1.BLIF \ + inst_AS_030_000_SYNC.BLIF un10_ciin_2.BLIF inst_AS_000_DMA.BLIF un10_ciin_3.BLIF inst_DS_000_DMA.BLIF un10_ciin_4.BLIF inst_VMA_INTreg.BLIF un10_ciin_5.BLIF inst_VPA_D.BLIF \ + un10_ciin_6.BLIF CLK_000_D_3_.BLIF un10_ciin_7.BLIF inst_DTACK_D0.BLIF un10_ciin_8.BLIF inst_AMIGA_DS.BLIF un10_ciin_9.BLIF CLK_000_D_1_.BLIF un10_ciin_10.BLIF \ + CLK_000_D_0_.BLIF un10_ciin_11.BLIF inst_CLK_OUT_PRE_50.BLIF N_201_1.BLIF inst_CLK_OUT_PRE_D.BLIF N_201_2.BLIF IPL_D0_0_.BLIF N_131_i_1.BLIF IPL_D0_1_.BLIF \ + N_134_0_1.BLIF IPL_D0_2_.BLIF N_113_i_1.BLIF CLK_000_D_2_.BLIF N_113_i_2.BLIF CLK_000_D_4_.BLIF N_144_1.BLIF pos_clk_ipl_n.BLIF N_144_2.BLIF \ + SIZE_DMA_0_.BLIF N_143_1.BLIF SIZE_DMA_1_.BLIF N_143_2.BLIF inst_A0_DMA.BLIF N_163_1.BLIF inst_RW_000_DMA.BLIF N_163_2.BLIF inst_UDS_000_INT.BLIF \ + N_163_3.BLIF inst_DS_000_ENABLE.BLIF un21_fpu_cs_1.BLIF inst_LDS_000_INT.BLIF a_decode_c_16__n.BLIF un21_berr_1_0.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_6_.BLIF \ + a_decode_c_17__n.BLIF N_199_1.BLIF inst_RW_000_INT.BLIF AS_000_DMA_1_sqmuxa_1.BLIF SM_AMIGA_4_.BLIF a_decode_c_18__n.BLIF N_140_1.BLIF SM_AMIGA_1_.BLIF N_66_i_1.BLIF \ + SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.BLIF N_205_i_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_205_i_2.BLIF inst_DSACK1_INT.BLIF \ + N_180_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF N_180_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_59_i_1.BLIF SM_AMIGA_5_.BLIF a_decode_c_22__n.BLIF N_127_i_1.BLIF \ + SM_AMIGA_3_.BLIF N_123_i_1.BLIF SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_121_i_1.BLIF N_119_i_1.BLIF N_6.BLIF a_c_0__n.BLIF N_117_i_1.BLIF \ + N_115_i_1.BLIF a_c_1__n.BLIF N_111_i_1.BLIF N_165_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_162_1.BLIF N_148_1.BLIF N_18.BLIF \ + BERR_c.BLIF pos_clk_ipl_1_n.BLIF N_19.BLIF ds_000_dma_0_un3_n.BLIF N_20.BLIF BG_030_c.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF BG_000DFFreg.BLIF \ + as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF BGACK_000_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \ + bg_000_0_un0_n.BLIF CLK_OSZI_c.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF CLK_OUT_INTreg.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF \ + FPU_SENSE_c.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF rw_000_int_0_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF as_030_000_sync_0_un1_n.BLIF SM_AMIGA_i_7_.BLIF \ + as_030_000_sync_0_un0_n.BLIF IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF cpu_est_2_1__n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF cpu_est_2_2__n.BLIF cpu_est_0_1__un3_n.BLIF \ + cpu_est_2_3__n.BLIF ipl_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF G_105.BLIF cpu_est_0_1__un0_n.BLIF G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_2__un3_n.BLIF G_107.BLIF \ + cpu_est_0_2__un1_n.BLIF N_60.BLIF cpu_est_0_2__un0_n.BLIF N_63.BLIF DTACK_c.BLIF cpu_est_0_3__un3_n.BLIF N_126.BLIF cpu_est_0_3__un1_n.BLIF N_150.BLIF \ + cpu_est_0_3__un0_n.BLIF N_151.BLIF ipl_030_0_0__un3_n.BLIF N_219.BLIF VPA_c.BLIF ipl_030_0_0__un1_n.BLIF N_175.BLIF ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF \ + N_59.BLIF RST_c.BLIF ipl_030_0_1__un1_n.BLIF N_68.BLIF ipl_030_0_1__un0_n.BLIF N_72.BLIF ipl_030_0_2__un3_n.BLIF N_80.BLIF ipl_030_0_2__un1_n.BLIF \ + N_93.BLIF RW_c.BLIF ipl_030_0_2__un0_n.BLIF N_98.BLIF ds_000_enable_0_un3_n.BLIF N_107.BLIF fc_c_0__n.BLIF ds_000_enable_0_un1_n.BLIF N_128.BLIF \ + ds_000_enable_0_un0_n.BLIF N_131.BLIF fc_c_1__n.BLIF vma_int_0_un3_n.BLIF N_134.BLIF vma_int_0_un1_n.BLIF N_135.BLIF vma_int_0_un0_n.BLIF N_141.BLIF \ + AMIGA_BUS_DATA_DIR_c.BLIF a_decode_15__n.BLIF N_142.BLIF N_143.BLIF a_decode_14__n.BLIF N_144.BLIF N_145.BLIF a_decode_13__n.BLIF N_146.BLIF \ + N_205_i.BLIF N_147.BLIF N_140_i.BLIF a_decode_12__n.BLIF N_148.BLIF AMIGA_DS_i.BLIF N_149.BLIF a_decode_11__n.BLIF N_154.BLIF \ + N_199_i.BLIF N_155.BLIF N_198_i.BLIF a_decode_10__n.BLIF N_162.BLIF N_180_i.BLIF N_165.BLIF N_262_i.BLIF a_decode_9__n.BLIF \ + N_259.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_260.BLIF pos_clk_un2_i_n.BLIF a_decode_8__n.BLIF N_181.BLIF N_3_i.BLIF N_182.BLIF N_32_0.BLIF \ + a_decode_7__n.BLIF N_183.BLIF N_4_i.BLIF N_184.BLIF N_31_0.BLIF a_decode_6__n.BLIF N_185.BLIF N_220_i.BLIF N_186.BLIF \ + BG_030_c_i.BLIF a_decode_5__n.BLIF N_266.BLIF pos_clk_un9_bg_030_0_n.BLIF N_267.BLIF N_17_i.BLIF a_decode_4__n.BLIF N_268.BLIF N_24_0.BLIF \ + N_190.BLIF N_16_i.BLIF a_decode_3__n.BLIF N_191.BLIF N_25_0.BLIF N_201.BLIF N_15_i.BLIF a_decode_2__n.BLIF N_202.BLIF \ + N_26_0.BLIF N_203.BLIF N_12_i.BLIF N_208.BLIF N_28_0.BLIF N_163.BLIF N_11_i.BLIF N_282.BLIF N_29_0.BLIF \ + un21_berr_1.BLIF N_5_i.BLIF N_132.BLIF N_30_0.BLIF N_96.BLIF a_c_i_0__n.BLIF N_129.BLIF size_c_i_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ + pos_clk_un10_sm_amiga_i_n.BLIF N_169.BLIF un1_dsack1_i.BLIF N_170.BLIF N_69_i.BLIF N_167.BLIF N_163_i.BLIF N_168.BLIF N_244_0.BLIF \ + pos_clk_rw_000_int_5_n.BLIF N_164_i.BLIF pos_clk_un6_bgack_000_n.BLIF N_165_i.BLIF N_274.BLIF un11_amiga_bus_enable_high_i.BLIF N_164.BLIF un10_ciin_i.BLIF N_244.BLIF \ + N_60_0.BLIF N_5.BLIF N_274_i.BLIF N_11.BLIF pos_clk_un6_bgack_000_0_n.BLIF N_12.BLIF RW_c_i.BLIF N_15.BLIF pos_clk_rw_000_int_5_0_n.BLIF \ + N_16.BLIF N_168_i.BLIF N_17.BLIF N_167_i.BLIF pos_clk_un9_bg_030_n.BLIF G_91.BLIF N_170_i.BLIF N_3.BLIF N_169_i.BLIF \ + N_205.BLIF AS_000_DMA_1_sqmuxa.BLIF N_38_0.BLIF N_4.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_199.BLIF N_282_0.BLIF pos_clk_un2_n.BLIF clk_000_d_i_3__n.BLIF \ + N_140.BLIF N_96_0.BLIF N_262.BLIF N_129_i.BLIF N_198.BLIF N_268_i.BLIF N_180.BLIF N_246_i.BLIF un1_amiga_bus_enable_low_i.BLIF \ + N_132_0.BLIF un21_fpu_cs_i.BLIF AS_000_i.BLIF N_142_i.BLIF BGACK_030_INT_i.BLIF N_141_i.BLIF nEXP_SPACE_i.BLIF N_135_0.BLIF cycle_dma_i_0__n.BLIF \ + N_134_0.BLIF RW_000_i.BLIF N_131_i.BLIF CLK_EXP_i.BLIF LDS_000_c_i.BLIF cycle_dma_i_1__n.BLIF UDS_000_c_i.BLIF DS_000_DMA_i.BLIF N_128_i.BLIF \ + AS_000_DMA_i.BLIF N_107_i.BLIF a_i_1__n.BLIF N_203_i.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF a_decode_i_19__n.BLIF N_201_i.BLIF a_decode_i_18__n.BLIF \ + N_202_i.BLIF a_decode_i_16__n.BLIF VMA_INT_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_98_i.BLIF sm_amiga_i_0__n.BLIF N_93_i.BLIF sm_amiga_i_5__n.BLIF N_82_i.BLIF \ + sm_amiga_i_6__n.BLIF N_80_i.BLIF sm_amiga_i_i_7__n.BLIF N_72_i.BLIF AS_030_i.BLIF N_68_i.BLIF AS_000_INT_i.BLIF N_59_i.BLIF DSACK1_INT_i.BLIF \ + N_190_i.BLIF sm_amiga_i_1__n.BLIF N_191_i.BLIF FPU_SENSE_i.BLIF AS_030_D1_i.BLIF N_267_i.BLIF cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_266_i.BLIF \ + VPA_D_i.BLIF sm_amiga_i_3__n.BLIF N_186_i.BLIF sm_amiga_i_4__n.BLIF cpu_est_i_1__n.BLIF N_185_i.BLIF clk_000_d_i_0__n.BLIF clk_000_d_i_1__n.BLIF N_183_i.BLIF \ + AS_030_D0_i.BLIF N_184_i.BLIF cpu_est_i_2__n.BLIF DTACK_D0_i.BLIF N_182_i.BLIF sm_amiga_i_2__n.BLIF AS_030_000_SYNC_i.BLIF N_181_i.BLIF ahigh_i_30__n.BLIF \ + ahigh_i_31__n.BLIF N_260_i.BLIF ahigh_i_28__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF ahigh_i_29__n.BLIF N_259_i.BLIF ahigh_i_26__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF ahigh_i_27__n.BLIF \ + N_63_0.BLIF ahigh_i_24__n.BLIF N_155_i.BLIF ahigh_i_25__n.BLIF N_162_i.BLIF N_187_i.BLIF un5_e_0.BLIF N_188_i.BLIF N_154_i.BLIF \ + N_189_i.BLIF cpu_est_2_0_3__n.BLIF N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n.BLIF N_147_i.BLIF un2_ds_030_i.BLIF N_148_i.BLIF N_219_i.BLIF \ + cpu_est_2_0_1__n.BLIF N_175_i.BLIF N_146_i.BLIF un3_as_030_i.BLIF N_36_0.BLIF AS_030_c.BLIF N_145_i.BLIF N_35_0.BLIF AS_000_c.BLIF \ + N_143_i.BLIF N_144_i.BLIF RW_000_c.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF N_20_i.BLIF AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN \ + LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN \ + AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ - SM_AMIGA_0_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ - IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ - CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C CLK_030_PE_0_.D CLK_030_PE_0_.C \ - CLK_030_PE_1_.D CLK_030_PE_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C RST_DLY_0_.D \ - RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ - inst_AMIGA_DS.D inst_AMIGA_DS.C inst_AS_030_D0.D inst_AS_030_D0.C inst_DTACK_D0.D inst_DTACK_D0.C inst_VPA_D.D inst_VPA_D.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D \ - inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ - inst_RW_000_DMA.D inst_RW_000_DMA.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ - inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ - G_95.X1 G_95.X2 G_101.X1 G_101.X2 G_103.X1 G_103.X2 G_97.X1 G_97.X2 G_122.X1 G_122.X2 G_123.X1 \ - G_123.X2 G_124.X1 G_124.X2 cpu_est_0_0_.X1 cpu_est_0_0_.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR DTACK RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ clk_000_d_i_1__n VPA_D_i N_125_i a_decode_2__n VMA_INT_i N_124_i \ - sm_amiga_i_0__n N_53_0 rst_dly_i_2__n N_134_i rst_dly_i_1__n N_270_0 rst_dly_i_0__n N_77_i DSACK1_INT_i N_87_i N_137_i_0 \ - N_112_i vcc_n_n DTACK_D0_i N_113_i BGACK_030_INT_i N_114_i gnd_n_n nEXP_SPACE_i un1_amiga_bus_enable_low AS_000_DMA_i N_109_i \ - un7_as_030 RW_000_i N_108_i un1_LDS_000_INT clk_030_pe_i_1__n N_111_i un1_UDS_000_INT DS_000_DMA_0_sqmuxa_i N_265_2_0 un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un4_rw_000_i_n \ - un10_ciin AS_000_i un1_as_000_i un21_fpu_cs AMIGA_DS_i VPA_c_i un21_berr pos_clk_un3_clk_out_int_i_n N_52_0 un6_ds_030 cycle_dma_i_0__n \ - DTACK_c_i un13_ciin cycle_dma_i_1__n N_48_0 pos_clk_as_000_dma6_i_n un3_ahigh_i DS_000_DMA_i pos_clk_un4_bgack_000_i_n CLK_EXP_i pos_clk_un6_bgack_000_0_n AMIGA_BUS_ENABLE_DMA_LOW_i \ - N_7_i ahigh_i_25__n N_41_0 ahigh_i_24__n pos_clk_un1_bgack_030_int_0_n ahigh_i_27__n pos_clk_un12_clk_out_int_0_n ahigh_i_26__n pos_clk_un3_0_n ahigh_i_29__n pos_clk_un15_bgack_030_int_i_n \ - ahigh_i_28__n N_3_i ahigh_i_31__n N_43_0 ahigh_i_30__n N_4_i a_i_1__n N_42_0 AMIGA_BUS_ENABLE_DMA_HIGH_i un6_amiga_bus_data_dir_i AS_030_D0_i \ - un12_amiga_bus_data_dir_m_i un10_ciin_i AMIGA_BUS_DATA_DIR_c_0 FPU_SENSE_i N_22_i AS_030_000_SYNC_i N_31_0 a_decode_i_16__n N_21_i a_decode_i_18__n N_32_0 \ - a_decode_i_19__n N_19_i N_224_i N_34_0 N_225_i N_18_i N_226_i N_35_0 pos_clk_un5_bgack_030_int_d_i_n pos_clk_amiga_bus_enable_dma_high_3_0_n pos_clk_un6_bg_030_n \ - pos_clk_amiga_bus_enable_dma_low_3_0_n pos_clk_ipl_n pos_clk_rw_000_dma_3_0_n un13_ciin_i UDS_000_c_i un6_ds_030_i LDS_000_c_i N_123_i N_86_i N_122_i N_129_i \ - un7_as_030_i N_130_i AS_030_c un11_amiga_bus_enable_high_i N_117_i AS_000_c N_46_0 N_107_i RW_000_c pos_clk_size_dma_6_0_0__n N_106_i \ - pos_clk_size_dma_6_0_1__n UDS_000_c N_16_i N_254_i LDS_000_c N_263_i N_250_i size_c_0__n N_256_i N_189_i pos_clk_rw_000_int_5_n \ - size_c_1__n N_101_i ahigh_c_24__n N_103_i N_104_i ahigh_c_25__n N_105_i ahigh_c_26__n N_115_i ahigh_c_27__n N_116_i \ - ahigh_c_28__n N_131_i N_277_i ahigh_c_29__n N_64_0 N_91_0 ahigh_c_30__n N_159_0 N_14 N_85_i N_15 \ - ahigh_c_31__n un1_SM_AMIGA_0_sqmuxa_1_0 N_24 RW_c_i N_25 pos_clk_rw_000_int_5_0_n clk_000_d_i_3__n N_25_i N_28_0 N_24_i N_27_0 \ - ipl_c_i_1__n N_50_0 ipl_c_i_0__n N_49_0 N_14_i N_39_0 N_15_i N_38_0 N_91_0_1 N_91_0_2 N_91_0_3 \ - N_265_i_1 N_266_i_1 N_266_i_2 N_138_i_1 N_148_i_1 N_144_i_1 N_142_i_1 N_140_i_1 pos_clk_un10_sm_amiga_i_1_n N_76 N_85_i_1 \ - N_85_i_2 a_decode_c_16__n N_277_1 N_277_2 un1_rst_2_1 a_decode_c_17__n N_277_3 N_277_4 N_64 a_decode_c_18__n N_277_5 \ - N_122 un10_ciin_1 N_123 a_decode_c_19__n un10_ciin_2 N_132 un10_ciin_3 N_133 a_decode_c_20__n un10_ciin_4 N_274 \ - un10_ciin_5 N_276 a_decode_c_21__n un10_ciin_6 N_77 un10_ciin_7 N_79 a_decode_c_22__n un10_ciin_8 N_78 un10_ciin_9 \ - N_263 a_decode_c_23__n un10_ciin_10 N_108 un10_ciin_11 N_114 a_c_0__n un6_amiga_bus_data_dir_1 N_85 un6_amiga_bus_data_dir_2 N_104 \ - a_c_1__n pos_clk_as_000_dma6_1_n N_91 pos_clk_as_000_dma6_2_n N_131 nEXP_SPACE_c DS_000_DMA_1_sqmuxa_1 N_277 pos_clk_un4_rw_000_1_n N_130 BERR_c \ - pos_clk_un4_rw_000_2_n N_115 pos_clk_un13_clk_out_int_1_n N_116 BG_030_c N_125_1 N_105 N_116_1 N_103 pos_clk_un29_clk_000_ne_1_1_n N_101 \ - pos_clk_un29_clk_000_ne_1_2_n N_259 pos_clk_un29_clk_000_ne_1_3_n N_255 BGACK_000_c N_261_1 N_256 N_261_2 N_254 CLK_030_c N_262_1 \ - N_16 N_262_2 N_106 DS_000_ENABLE_0_sqmuxa_1_1 N_86 N_259_1 N_107 CLK_OSZI_c N_250_i_1 N_117 N_189_i_1 \ - pos_clk_a0_dma_3_n pos_clk_un6_bg_030_1_n N_129 N_108_1 pos_clk_size_dma_6_1__n N_114_1 pos_clk_size_dma_6_0__n un21_berr_1 pos_clk_rw_000_dma_3_n FPU_SENSE_c un21_fpu_cs_1 \ - pos_clk_amiga_bus_enable_dma_low_3_n N_130_1 pos_clk_amiga_bus_enable_dma_high_3_n N_136_i_1 SIZE_DMA_3_sqmuxa N_152_i_1 pos_clk_un5_bgack_030_int_d_n N_146_i_1 N_18 N_267_i_1 N_19 \ - pos_clk_ipl_1_n N_21 bg_000_0_un3_n N_22 ipl_c_0__n bg_000_0_un1_n un6_amiga_bus_data_dir bg_000_0_un0_n un12_amiga_bus_data_dir_m ipl_c_1__n uds_000_int_0_un3_n \ - pos_clk_un3_clk_out_int_n uds_000_int_0_un1_n N_3 ipl_c_2__n uds_000_int_0_un0_n pos_clk_as_000_dma6_n lds_000_int_0_un3_n DS_000_DMA_1_sqmuxa lds_000_int_0_un1_n N_4 DTACK_c \ - lds_000_int_0_un0_n AS_000_DMA_1_sqmuxa ds_000_enable_0_un3_n un1_rst_2 ds_000_enable_0_un1_n ds_000_enable_0_un0_n N_199 VPA_c ipl_030_0_2__un3_n pos_clk_un13_bgack_030_int_n ipl_030_0_2__un1_n \ - N_205 ipl_030_0_2__un0_n pos_clk_un13_clk_out_int_n RST_c vma_int_0_un3_n pos_clk_un15_bgack_030_int_n vma_int_0_un1_n pos_clk_un3_n RESET_c vma_int_0_un0_n pos_clk_un12_clk_out_int_n \ - cpu_est_0_1__un3_n pos_clk_un1_bgack_030_int_n RW_c cpu_est_0_1__un1_n DS_000_DMA_0_sqmuxa cpu_est_0_1__un0_n un1_rst_3 fc_c_0__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n fc_c_1__n \ - cpu_est_0_2__un0_n cpu_est_0_3__un3_n pos_clk_un4_rw_000_n cpu_est_0_3__un1_n N_7 AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un0_n pos_clk_un6_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un3_n pos_clk_un4_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un1_n \ - N_265_2 pos_clk_un31_clk_000_ne_1_i_m2_un0_n N_111 bgack_030_int_0_un3_n N_109 BG_030_c_i bgack_030_int_0_un1_n N_113 pos_clk_un6_bg_030_i_n bgack_030_int_0_un0_n N_112 \ - pos_clk_un9_bg_030_0_n ds_000_dma_0_un3_n N_98 UDS_000_INT_i ds_000_dma_0_un1_n pos_clk_un29_clk_000_ne_1_n un1_UDS_000_INT_0 ds_000_dma_0_un0_n N_87 LDS_000_INT_i as_000_dma_0_un3_n \ - N_270 un1_LDS_000_INT_0 as_000_dma_0_un1_n N_134 N_23_i as_000_dma_0_un0_n N_125 N_30_0 size_dma_0_1__un3_n N_124 N_20_i \ - size_dma_0_1__un1_n N_121 N_33_0 size_dma_0_1__un0_n N_120 N_13_i size_dma_0_0__un3_n N_137 N_40_0 size_dma_0_0__un1_n pos_clk_un31_clk_000_ne_n \ - ipl_c_i_2__n size_dma_0_0__un0_n N_17 N_51_0 amiga_bus_enable_dma_high_0_un3_n pos_clk_un9_clk_000_pe_n N_26_i amiga_bus_enable_dma_high_0_un1_n cpu_est_2_1__n N_29_0 amiga_bus_enable_dma_high_0_un0_n \ - cpu_est_2_2__n a_c_i_0__n amiga_bus_enable_dma_low_0_un3_n N_261 size_c_i_1__n amiga_bus_enable_dma_low_0_un1_n N_262 pos_clk_un10_sm_amiga_i_n amiga_bus_enable_dma_low_0_un0_n N_251 DS_000_ENABLE_0_sqmuxa_1_i \ - a0_dma_0_un3_n N_252 un1_DS_000_ENABLE_0_sqmuxa_i a0_dma_0_un1_n N_258 N_157_i a0_dma_0_un0_n N_257 N_160_0 rw_000_dma_0_un3_n DS_000_ENABLE_1_sqmuxa \ - N_161_0 rw_000_dma_0_un1_n un1_DS_000_ENABLE_0_sqmuxa N_162_0 rw_000_dma_0_un0_n N_102 N_165_i ipl_030_0_0__un3_n N_118 ipl_030_0_0__un1_n N_119 \ - N_167_i ipl_030_0_0__un0_n N_264 N_166_i ipl_030_0_1__un3_n DS_000_ENABLE_0_sqmuxa_1 ipl_030_0_1__un1_n N_164 N_168_i ipl_030_0_1__un0_n N_170 \ - as_030_000_sync_0_un3_n N_168 N_170_i as_030_000_sync_0_un1_n N_166 as_030_000_sync_0_un0_n N_167 N_164_i rw_000_int_0_un3_n N_165 rw_000_int_0_un1_n \ - N_162 N_102_i rw_000_int_0_un0_n N_161 N_264_i a_decode_15__n N_160 N_79_i N_157 N_78_i a_decode_14__n \ - N_26 N_119_i N_13 N_118_i a_decode_13__n N_20 N_23 N_255_i a_decode_12__n N_8 N_257_i \ - pos_clk_un9_bg_030_n cpu_est_2_0_2__n a_decode_11__n un1_amiga_bus_enable_low_i N_258_i un21_fpu_cs_i N_259_i a_decode_10__n sm_amiga_i_2__n cpu_est_2_0_1__n sm_amiga_i_1__n \ - N_262_i a_decode_9__n sm_amiga_i_3__n N_261_i sm_amiga_i_4__n pos_clk_un9_clk_000_pe_0_n a_decode_8__n sm_amiga_i_6__n N_251_i sm_amiga_i_5__n N_252_0 \ - a_decode_7__n clk_000_d_i_0__n N_76_i AS_000_INT_i N_17_i a_decode_6__n sm_amiga_i_i_7__n N_36_0 AS_030_i N_98_i a_decode_5__n \ - cpu_est_i_2__n pos_clk_un31_clk_000_ne_i_n cpu_est_i_0__n N_228_i a_decode_4__n cpu_est_i_3__n N_121_i cpu_est_i_1__n N_120_i a_decode_3__n \ + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C \ + SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ + IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ + SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D \ + SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ + cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ + inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ + inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D \ + inst_AS_000_INT.C inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ + inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D \ + inst_CLK_OUT_PRE_D.C G_105.X1 G_105.X2 G_106.X1 G_106.X2 G_107.X1 G_107.X2 G_91.X1 G_91.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_23_0 UDS_000_c \ + N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n N_42_0 \ + vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 \ + ahigh_c_26__n VPA_c_i un1_UDS_000_INT N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n \ + LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 ahigh_c_30__n N_96_0_1 N_96_0_2 \ + ahigh_c_31__n N_282_0_1 N_282_0_2 N_282_0_3 N_282_0_4 pos_clk_un10_sm_amiga_i_1_n un10_ciin_1 un10_ciin_2 un10_ciin_3 un10_ciin_4 un10_ciin_5 \ + un10_ciin_6 un10_ciin_7 un10_ciin_8 un10_ciin_9 un10_ciin_10 un10_ciin_11 N_201_1 N_201_2 N_131_i_1 N_134_0_1 N_113_i_1 \ + N_113_i_2 N_144_1 pos_clk_ipl_n N_144_2 N_143_1 N_143_2 N_163_1 N_163_2 N_163_3 un21_fpu_cs_1 a_decode_c_16__n \ + un21_berr_1_0 pos_clk_cycle_dma_5_1_1__n a_decode_c_17__n N_199_1 AS_000_DMA_1_sqmuxa_1 a_decode_c_18__n N_140_1 N_66_i_1 a_decode_c_19__n N_66_i_2 N_205_i_1 \ + a_decode_c_20__n N_205_i_2 N_180_1 a_decode_c_21__n N_180_2 pos_clk_un9_clk_000_pe_n N_59_i_1 a_decode_c_22__n N_127_i_1 N_123_i_1 a_decode_c_23__n \ + N_121_i_1 N_119_i_1 N_6 a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c \ + N_162_1 N_148_1 N_18 BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n ds_000_dma_0_un0_n \ + as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c \ + lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n rw_000_int_0_un1_n rw_000_int_0_un0_n as_030_000_sync_0_un3_n \ + as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n \ + cpu_est_0_1__un1_n cpu_est_0_1__un0_n ipl_c_2__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 \ + cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n \ + N_59 RST_c ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 ipl_030_0_2__un1_n N_93 RW_c \ + ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n vma_int_0_un3_n \ + N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 \ + N_145 a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 a_decode_11__n \ + N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i a_decode_9__n N_259 \ + AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i \ + N_184 N_31_0 a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 \ + N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 N_15_i \ + a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 \ + un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 \ + un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i \ + N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i N_11 pos_clk_un6_bgack_000_0_n N_12 \ + RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i N_17 N_167_i pos_clk_un9_bg_030_n N_170_i N_3 N_169_i \ + N_205 AS_000_DMA_1_sqmuxa N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 \ + N_262 N_129_i N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i \ + BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ + UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i \ + a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n \ + N_80_i sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i sm_amiga_i_1__n N_191_i \ + FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n \ + N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i \ + N_181_i ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n \ + N_63_0 ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i cpu_est_2_0_3__n \ + N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i \ + N_36_0 AS_030_c N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i \ AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ - AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE DTACK.OE \ - RW.OE DS_030.OE DSACK1.OE CIIN.OE -.names un7_as_030_i.BLIF AS_030 + AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE \ + DS_030.OE DSACK1.OE VMA.OE CIIN.OE +.names un3_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c 1 1 -.names N_132.BLIF AS_030.OE +.names BGACK_030_INT_i.BLIF AS_030.OE 1 1 -.names N_122_i.BLIF AS_000 +.names N_175_i.BLIF AS_000 1 1 .names AS_000.PIN AS_000_c 1 1 -.names un1_as_000_i.BLIF AS_000.OE +.names N_69_i.BLIF AS_000.OE 1 1 .names inst_RW_000_INT.BLIF RW_000 1 1 .names RW_000.PIN RW_000_c 1 1 -.names un1_as_000_i.BLIF RW_000.OE +.names N_69_i.BLIF RW_000.OE 1 1 .names un1_UDS_000_INT.BLIF UDS_000 1 1 .names UDS_000.PIN UDS_000_c 1 1 -.names un1_as_000_i.BLIF UDS_000.OE +.names N_69_i.BLIF UDS_000.OE 1 1 .names un1_LDS_000_INT.BLIF LDS_000 1 1 .names LDS_000.PIN LDS_000_c 1 1 -.names un1_as_000_i.BLIF LDS_000.OE +.names N_69_i.BLIF LDS_000.OE 1 1 .names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 .names SIZE_0_.PIN size_c_0__n 1 1 -.names N_276.BLIF SIZE_0_.OE +.names BGACK_030_INT_i.BLIF SIZE_0_.OE 1 1 .names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 .names SIZE_1_.PIN size_c_1__n 1 1 -.names N_276.BLIF SIZE_1_.OE +.names BGACK_030_INT_i.BLIF SIZE_1_.OE 1 1 .names gnd_n_n.BLIF AHIGH_24_ 1 1 .names AHIGH_24_.PIN ahigh_c_24__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_24_.OE +.names BGACK_030_INT_i.BLIF AHIGH_24_.OE 1 1 .names gnd_n_n.BLIF AHIGH_25_ 1 1 .names AHIGH_25_.PIN ahigh_c_25__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_25_.OE +.names BGACK_030_INT_i.BLIF AHIGH_25_.OE 1 1 .names gnd_n_n.BLIF AHIGH_26_ 1 1 .names AHIGH_26_.PIN ahigh_c_26__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_26_.OE +.names BGACK_030_INT_i.BLIF AHIGH_26_.OE 1 1 .names gnd_n_n.BLIF AHIGH_27_ 1 1 .names AHIGH_27_.PIN ahigh_c_27__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_27_.OE +.names BGACK_030_INT_i.BLIF AHIGH_27_.OE 1 1 .names gnd_n_n.BLIF AHIGH_28_ 1 1 .names AHIGH_28_.PIN ahigh_c_28__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_28_.OE +.names BGACK_030_INT_i.BLIF AHIGH_28_.OE 1 1 .names gnd_n_n.BLIF AHIGH_29_ 1 1 .names AHIGH_29_.PIN ahigh_c_29__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_29_.OE +.names BGACK_030_INT_i.BLIF AHIGH_29_.OE 1 1 .names gnd_n_n.BLIF AHIGH_30_ 1 1 .names AHIGH_30_.PIN ahigh_c_30__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_30_.OE +.names BGACK_030_INT_i.BLIF AHIGH_30_.OE 1 1 .names gnd_n_n.BLIF AHIGH_31_ 1 1 .names AHIGH_31_.PIN ahigh_c_31__n 1 1 -.names un3_ahigh_i.BLIF AHIGH_31_.OE +.names BGACK_030_INT_i.BLIF AHIGH_31_.OE 1 1 .names inst_A0_DMA.BLIF A_0_ 1 1 .names A_0_.PIN a_c_0__n 1 1 -.names N_132.BLIF A_0_.OE +.names BGACK_030_INT_i.BLIF A_0_.OE 1 1 .names gnd_n_n.BLIF BERR 1 1 @@ -306,1390 +275,1162 @@ 1 1 .names un21_berr.BLIF BERR.OE 1 1 -.names gnd_n_n.BLIF DTACK -1 1 -.names DTACK.PIN DTACK_c -1 1 -.names AS_000_DMA_i.BLIF DTACK.OE -1 1 .names inst_RW_000_DMA.BLIF RW 1 1 .names RW.PIN RW_c 1 1 -.names N_133.BLIF RW.OE +.names BGACK_030_INT_i.BLIF RW.OE 1 1 -.names un6_ds_030_i.BLIF DS_030 +.names un2_ds_030_i.BLIF DS_030 1 1 -.names N_132.BLIF DS_030.OE +.names BGACK_030_INT_i.BLIF DS_030.OE 1 1 -.names N_123_i.BLIF DSACK1 +.names N_219_i.BLIF DSACK1 1 1 -.names nEXP_SPACE_c.BLIF DSACK1.OE +.names un1_dsack1_i.BLIF DSACK1.OE +1 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 .names un10_ciin.BLIF CIIN 1 1 -.names un13_ciin_i.BLIF CIIN.OE +.names N_60.BLIF CIIN.OE 1 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n -11 1 -.names N_87.BLIF sm_amiga_i_0__n.BLIF N_101 -11 1 -.names CYCLE_DMA_1_.BLIF G_97.X1 -1 1 -.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF N_85_i_1 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names CLK_000_D_4_.BLIF clk_000_d_i_3__n.BLIF N_85_i_2 -11 1 -.names BERR_c.BLIF N_98_i.BLIF pos_clk_un31_clk_000_ne_i_n -11 1 -.names N_199.BLIF G_97.X2 -1 1 -.names N_85_i_1.BLIF N_85_i_2.BLIF N_85_i -11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_277_1 -11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_277_2 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names IPL_D0_0_.BLIF G_122.X1 -1 1 -.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_277_3 -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names N_277_1.BLIF N_277_2.BLIF N_277_4 -11 1 -.names N_17_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names ipl_c_0__n.BLIF G_122.X2 -1 1 -.names N_277_3.BLIF fc_c_0__n.BLIF N_277_5 -11 1 -.names N_76.BLIF cpu_est_0_1__un3_n -0 1 -.names N_38_0.BLIF inst_RW_000_INT.D -0 1 -.names cpu_est_1_.BLIF N_76.BLIF cpu_est_0_1__un1_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -.names inst_BGACK_030_INT_D.BLIF inst_BGACK_030_INTreg.BLIF N_91_0_1 -11 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names IPL_D0_1_.BLIF G_123.X1 -1 1 -.names AS_030_D0_i.BLIF sm_amiga_i_i_7__n.BLIF N_91_0_2 -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names N_91_0_1.BLIF N_91_0_2.BLIF N_91_0_3 -11 1 -.names N_76.BLIF cpu_est_0_2__un3_n -0 1 -.names ipl_c_1__n.BLIF G_123.X2 -1 1 -.names N_91_0_3.BLIF nEXP_SPACE_c.BLIF N_91_0 -11 1 -.names cpu_est_2_.BLIF N_76.BLIF cpu_est_0_2__un1_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names N_108_i.BLIF N_109_i.BLIF N_265_i_1 -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_265_i_1.BLIF N_265_2_0.BLIF RST_DLY_2_.D -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names IPL_D0_2_.BLIF G_124.X1 -1 1 -.names N_112_i.BLIF RST_c.BLIF N_266_i_1 -11 1 -.names N_76.BLIF cpu_est_0_3__un3_n -0 1 -.names N_113_i.BLIF N_114_i.BLIF N_266_i_2 -11 1 -.names cpu_est_3_.BLIF N_76.BLIF cpu_est_0_3__un1_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names ipl_c_2__n.BLIF G_124.X2 -1 1 -.names N_266_i_1.BLIF N_266_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_189_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names N_164_i.BLIF N_264.BLIF N_138_i_1 -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D -11 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_77_i -11 1 -.names N_76.BLIF cpu_est_0_0_.X1 -1 1 -.names N_79.BLIF N_170_i.BLIF N_148_i_1 -11 1 -.names N_134_i.BLIF RST_c.BLIF N_270_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names N_124_i.BLIF N_125_i.BLIF N_53_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_0_0_.X2 -1 1 -.names N_78.BLIF N_168_i.BLIF N_144_i_1 -11 1 -.names N_120_i.BLIF N_121_i.BLIF inst_DSACK1_INT.D -11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names N_137_i_0.BLIF RST_c.BLIF N_228_i -11 1 -.names RW_c.BLIF RW_c_i -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_274 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D -1 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_77_i.BLIF RST_DLY_2_.BLIF N_137 -11 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_3__n -0 1 -.names N_137.BLIF N_137_i_0 -0 1 -.names N_25.BLIF N_25_i -0 1 -.names N_76_i.BLIF N_137_i_0.BLIF N_134 -11 1 -.names N_28_0.BLIF IPL_030DFF_1_reg.D -0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_124 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names N_24.BLIF N_24_i -0 1 -.names N_87_i.BLIF RST_c.BLIF N_121 -11 1 -.names N_27_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names DSACK1_INT_i.BLIF N_274.BLIF N_120 -11 1 -.names N_50_0.BLIF IPL_D0_1_.D -0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names N_270.BLIF RST_DLY_0_.BLIF N_115 -11 1 -.names N_49_0.BLIF IPL_D0_0_.D -0 1 -.names BGACK_000_c.BLIF pos_clk_un4_bgack_000_i_n.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names N_14.BLIF N_14_i -0 1 -.names AS_000_c.BLIF N_76_i.BLIF pos_clk_un4_bgack_000_n -11 1 -.names N_39_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_276.BLIF RESET_c.BLIF un3_ahigh_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names N_15.BLIF N_15_i -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names N_16.BLIF N_16_i -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_52_0 -11 1 -.names N_254.BLIF N_254_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i -11 1 -.names N_263.BLIF N_263_i -0 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names N_256.BLIF N_256_i -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_276 -11 1 -.names N_101.BLIF N_101_i -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_103.BLIF N_103_i -0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_133 -11 1 -.names N_104.BLIF N_104_i -0 1 -.names N_276.BLIF inst_RESET_OUT.BLIF N_132 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -.names N_105.BLIF N_105_i -0 1 -.names N_111_i.BLIF RST_c.BLIF N_265_2_0 -11 1 -.names N_115.BLIF N_115_i -0 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_116.BLIF N_116_i -0 1 -.names inst_VPA_D.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un3_n -0 1 -.names N_131.BLIF N_131_i -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un1_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names N_277.BLIF N_277_i -0 1 -.names pos_clk_un29_clk_000_ne_1_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un3_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un0_n -11 1 -.names N_64_0.BLIF N_64 -0 1 -.names pos_clk_un31_clk_000_ne_1_i_m2_un1_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un0_n.BLIF N_98 -1- 1 --1 1 -.names N_91_0.BLIF N_91 -0 1 -.names N_76_i.BLIF SM_AMIGA_1_.BLIF N_87_i -11 1 -.names N_85_i.BLIF N_85 -0 1 -.names G_103.BLIF un1_rst_3.BLIF CLK_030_PE_1_.D -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C -1 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF un1_rst_2_1 -11 1 -.names pos_clk_amiga_bus_enable_dma_high_3_0_n.BLIF pos_clk_amiga_bus_enable_dma_high_3_n -0 1 -.names AS_000_i.BLIF un1_rst_2_1.BLIF un1_rst_2 -11 1 -.names pos_clk_amiga_bus_enable_dma_low_3_0_n.BLIF pos_clk_amiga_bus_enable_dma_low_3_n -0 1 -.names inst_AMIGA_DS.BLIF AMIGA_DS_i -0 1 -.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C -1 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names pos_clk_un4_rw_000_n.BLIF pos_clk_un4_rw_000_i_n -0 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names DS_000_DMA_0_sqmuxa.BLIF DS_000_DMA_0_sqmuxa_i -0 1 -.names N_86_i.BLIF N_86 -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_129.BLIF N_129_i -0 1 -.names CLK_030_PE_1_.BLIF clk_030_pe_i_1__n -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -.names N_130.BLIF N_130_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_117.BLIF N_117_i -0 1 -.names N_46_0.BLIF inst_AMIGA_DS.D -0 1 -.names N_107.BLIF N_107_i -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C -1 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_106.BLIF N_106_i -0 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names N_3.BLIF N_3_i -0 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_7 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C -1 1 -.names N_43_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_7_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names N_4.BLIF N_4_i -0 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names N_42_0.BLIF inst_AS_000_DMA.D -0 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n -0 1 -.names un6_amiga_bus_data_dir.BLIF un6_amiga_bus_data_dir_i -0 1 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un15_bgack_030_int_i_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -.names un12_amiga_bus_data_dir_m.BLIF un12_amiga_bus_data_dir_m_i -0 1 -.names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un3_0_n -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names CLK_030_PE_0_.BLIF CLK_030_PE_1_.BLIF pos_clk_un12_clk_out_int_0_n -11 1 -.names N_22.BLIF N_22_i -0 1 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -.names N_31_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 -11 1 -.names N_21.BLIF N_21_i -0 1 -.names N_76_i.BLIF pos_clk_un15_bgack_030_int_n.BLIF pos_clk_un13_bgack_030_int_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names RW_000_i.BLIF pos_clk_un15_bgack_030_int_i_n.BLIF pos_clk_un1_bgack_030_int_0_n -11 1 -.names N_19.BLIF N_19_i -0 1 -.names pos_clk_un3_clk_out_int_n.BLIF pos_clk_un3_clk_out_int_i_n -0 1 -.names N_34_0.BLIF inst_A0_DMA.D -0 1 -.names RW_000_c.BLIF pos_clk_un3_clk_out_int_i_n.BLIF DS_000_DMA_0_sqmuxa -11 1 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -.names N_18.BLIF N_18_i -0 1 -.names RST_c.BLIF pos_clk_as_000_dma6_n.BLIF un1_rst_3 -11 1 -.names N_35_0.BLIF inst_RW_000_DMA.D -0 1 -.names pos_clk_as_000_dma6_n.BLIF pos_clk_un3_clk_out_int_n.BLIF AS_000_DMA_1_sqmuxa -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -.names N_108.BLIF N_108_i -0 1 -.names G_95.BLIF un1_rst_2.BLIF CYCLE_DMA_0_.D -11 1 -.names N_111.BLIF N_111_i -0 1 -.names G_101.BLIF un1_rst_3.BLIF CLK_030_PE_0_.D -11 1 -.names N_265_2_0.BLIF N_265_2 -0 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low -11 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names un6_amiga_bus_data_dir_i.BLIF un12_amiga_bus_data_dir_m_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_3_.C -1 1 -.names N_52_0.BLIF inst_VPA_D.D -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF un12_amiga_bus_data_dir_m -11 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP_i -0 1 -.names N_48_0.BLIF inst_DTACK_D0.D -0 1 -.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF pos_clk_un3_clk_out_int_n -11 1 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D -1 1 -.names pos_clk_un4_bgack_000_n.BLIF pos_clk_un4_bgack_000_i_n -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_4_.C -1 1 -.names N_7.BLIF N_7_i -0 1 -.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 -.names N_41_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n -11 1 -.names pos_clk_un1_bgack_030_int_0_n.BLIF pos_clk_un1_bgack_030_int_n -0 1 -.names pos_clk_as_000_dma6_i_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names pos_clk_un12_clk_out_int_0_n.BLIF pos_clk_un12_clk_out_int_n -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -.names pos_clk_un3_0_n.BLIF pos_clk_un3_n -0 1 -.names pos_clk_as_000_dma6_n.BLIF pos_clk_as_000_dma6_i_n -0 1 -.names pos_clk_un15_bgack_030_int_i_n.BLIF pos_clk_un15_bgack_030_int_n -0 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names N_98.BLIF N_98_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names pos_clk_un31_clk_000_ne_i_n.BLIF pos_clk_un31_clk_000_ne_n -0 1 -.names pos_clk_as_000_dma6_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -.names N_121.BLIF N_121_i -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_120.BLIF N_120_i -0 1 -.names G_97.BLIF un1_rst_2.BLIF CYCLE_DMA_1_.D -11 1 -.names N_125.BLIF N_125_i -0 1 -.names N_4_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names N_124.BLIF N_124_i -0 1 -.names N_3_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_030_PE_0_.C -1 1 -.names N_53_0.BLIF inst_RESET_OUT.D -0 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un13_bgack_030_int_n.BLIF N_199 -11 1 -.names N_134.BLIF N_134_i -0 1 -.names CLK_030_PE_0_.BLIF pos_clk_un13_clk_out_int_n.BLIF N_205 -11 1 -.names N_270_0.BLIF N_270 -0 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names N_77_i.BLIF N_77 -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names CLK_OSZI_c.BLIF CLK_030_PE_1_.C -1 1 -.names N_87_i.BLIF N_87 -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_112.BLIF N_112_i -0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_113.BLIF N_113_i -0 1 -.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un3_n -0 1 -.names N_114.BLIF N_114_i -0 1 -.names SIZE_DMA_1_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un1_n -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names N_109.BLIF N_109_i -0 1 -.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names N_118.BLIF N_118_i -0 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names N_255.BLIF N_255_i -0 1 -.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un3_n -0 1 -.names N_257.BLIF N_257_i -0 1 -.names SIZE_DMA_0_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un1_n -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n -0 1 -.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n -11 1 -.names N_258.BLIF N_258_i -0 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D -1- 1 --1 1 -.names N_259.BLIF N_259_i -0 1 -.names N_18_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names N_19_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names N_262.BLIF N_262_i -0 1 -.names N_21_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names N_261.BLIF N_261_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names N_251_i.BLIF N_251 -0 1 -.names pos_clk_amiga_bus_enable_dma_high_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names N_252_0.BLIF N_252 -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names N_76_i.BLIF N_76 -0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names N_17.BLIF N_17_i -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_36_0.BLIF inst_VMA_INTreg.D -0 1 -.names pos_clk_amiga_bus_enable_dma_low_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C -1 1 -.names N_157_i.BLIF N_157 -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names N_160_0.BLIF N_160 -0 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_161_0.BLIF N_161 -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n -0 1 -.names N_162_0.BLIF N_162 -0 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C -1 1 -.names N_165.BLIF N_165_i -0 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names N_167.BLIF N_167_i -0 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names A_DECODE_16_.BLIF a_decode_c_16__n -1 1 -.names N_166.BLIF N_166_i -0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names A_DECODE_17_.BLIF a_decode_c_17__n -1 1 -.names N_168.BLIF N_168_i -0 1 -.names pos_clk_rw_000_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -.names A_DECODE_18_.BLIF a_decode_c_18__n -1 1 -.names N_170.BLIF N_170_i -0 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names A_DECODE_19_.BLIF a_decode_c_19__n -1 1 -.names N_164.BLIF N_164_i -0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names A_DECODE_20_.BLIF a_decode_c_20__n -1 1 -.names N_102.BLIF N_102_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names A_DECODE_21_.BLIF a_decode_c_21__n -1 1 -.names N_264_i.BLIF N_264 -0 1 -.names N_106_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names A_DECODE_22_.BLIF a_decode_c_22__n -1 1 -.names N_79_i.BLIF N_79 -0 1 -.names N_107_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names A_DECODE_23_.BLIF a_decode_c_23__n -1 1 -.names N_78_i.BLIF N_78 -0 1 -.names N_117_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_119.BLIF N_119_i -0 1 -.names N_129_i.BLIF N_130_i.BLIF un11_amiga_bus_enable_high_i -11 1 -.names A_1_.BLIF a_c_1__n -1 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_86_i -11 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names N_23.BLIF N_23_i -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n -11 1 -.names N_30_0.BLIF BG_000DFFreg.D -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names BG_030.BLIF BG_030_c -1 1 -.names N_20.BLIF N_20_i -0 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF pos_clk_amiga_bus_enable_dma_low_3_0_n -11 1 -.names BG_000DFFreg.BLIF BG_000 -1 1 -.names N_33_0.BLIF inst_UDS_000_INT.D -0 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF pos_clk_amiga_bus_enable_dma_high_3_0_n -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names N_13.BLIF N_13_i -0 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF SIZE_DMA_3_sqmuxa -11 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names N_40_0.BLIF inst_LDS_000_INT.D -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_un5_bgack_030_int_d_i_n -11 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -.names N_51_0.BLIF IPL_D0_2_.D -0 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C -1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names N_26.BLIF N_26_i -0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names N_29_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names N_131_i.BLIF N_277_i.BLIF N_64_0 -11 1 -.names un21_fpu_cs_i.BLIF FPU_CS -1 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names AS_030_i.BLIF N_91.BLIF N_131 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -.names FPU_SENSE.BLIF FPU_SENSE_c -1 1 -.names DS_000_ENABLE_0_sqmuxa_1.BLIF DS_000_ENABLE_0_sqmuxa_1_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ -1 1 -.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ -1 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ -1 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF un13_ciin -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names BGACK_030_INT_i.BLIF N_86_i.BLIF N_106 -11 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT -0 1 -.names BGACK_030_INT_i.BLIF N_86.BLIF N_107 -11 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_117 -11 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_122 -11 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names N_8.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_123 -11 1 -.names N_250_i.BLIF E -1 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names VPA.BLIF VPA_c -1 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_129 -11 1 -.names RST.BLIF RST_c -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_23 -1- 1 --1 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D -0 1 -.names RESET.BLIF RESET_c -1 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 -.names G_122.BLIF N_224_i -0 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names G_123.BLIF N_225_i -0 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names G_124.BLIF N_226_i -0 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE -1 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n -0 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names un11_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH -1 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 -1- 1 --1 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF ds_000_enable_0_un3_n -0 1 -.names N_159_0.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n -11 1 -.names N_78.BLIF N_101_i.BLIF N_136_i_1 -11 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa.BLIF ds_000_enable_0_un1_n -11 1 -.names N_79.BLIF N_159_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 -11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -.names N_136_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D -11 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names N_104_i.BLIF SM_AMIGA_i_7_.BLIF N_159_0 -11 1 -.names N_103_i.BLIF N_104_i.BLIF N_152_i_1 -11 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names un1_rst_2_1.BLIF inst_BGACK_030_INT_D.D -0 1 -.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -0 1 -.names N_76.BLIF N_105_i.BLIF N_146_i_1 -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names N_274.BLIF inst_AS_030_D0.D -0 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names N_115_i.BLIF N_116_i.BLIF N_267_i_1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_282_0_3 11 1 .names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names N_267_i_1.BLIF RST_c.BLIF RST_DLY_0_.D -11 1 -.names N_157.BLIF sm_amiga_i_3__n.BLIF N_166 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_161.BLIF sm_amiga_i_2__n.BLIF N_165 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_24 -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +.names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 -.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n +.names N_282_0_1.BLIF N_282_0_2.BLIF N_282_0_4 11 1 +.names N_68_i.BLIF SM_AMIGA_5_.BLIF N_135_0 +11 1 +.names N_282_0_4.BLIF N_282_0_3.BLIF N_282_0 +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n +11 1 +.names N_98_i.BLIF cpu_est_i_2__n.BLIF N_208 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 +11 1 +.names N_143_i.BLIF N_144_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 +11 1 +.names N_145_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 +11 1 +.names N_146_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names N_21_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_147_i.BLIF N_148_i.BLIF cpu_est_2_0_1__n +11 1 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n +11 1 +.names N_43_0.BLIF IPL_D0_2_.D +0 1 +.names N_80.BLIF N_154_i.BLIF cpu_est_2_0_3__n +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names N_155_i.BLIF N_162_i.BLIF un5_e_0 +11 1 +.names N_42_0.BLIF IPL_D0_1_.D +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_63_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names N_259_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_41_0.BLIF IPL_D0_0_.D +0 1 +.names N_260_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names N_190_i.BLIF N_191_i.BLIF cpu_est_0_.D +11 1 +.names N_45_0.BLIF inst_DTACK_D0.D +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names N_44_0.BLIF inst_VPA_D.D +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_68_i +11 1 +.names N_13.BLIF N_13_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_27_0.BLIF inst_VMA_INTreg.D +0 1 +.names BGACK_030_INT_i.BLIF N_128.BLIF N_259 +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names BGACK_030_INT_i.BLIF N_128_i.BLIF N_260 +11 1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT +0 1 .names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names N_147.BLIF N_147_i 0 1 -.names N_250_i_1.BLIF N_263_i.BLIF N_250_i +.names N_134.BLIF sm_amiga_i_2__n.BLIF N_182 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names N_148.BLIF N_148_i 0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names N_68_i.BLIF N_131.BLIF N_183 11 1 -.names N_255_i.BLIF N_256_i.BLIF N_189_i_1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names N_107.BLIF sm_amiga_i_3__n.BLIF N_184 11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_164 +.names N_146.BLIF N_146_i +0 1 +.names N_135.BLIF sm_amiga_i_4__n.BLIF N_185 11 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_36_0.BLIF inst_A0_DMA.D +0 1 +.names N_72_i.BLIF SM_AMIGA_0_.BLIF N_268 11 1 -.names N_189_i_1.BLIF N_263_i.BLIF N_189_i +.names N_145.BLIF N_145_i +0 1 +.names N_68.BLIF cpu_est_i_0__n.BLIF N_190 11 1 -.names DS_000_ENABLE_0_sqmuxa_1_i.BLIF N_157.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names N_35_0.BLIF inst_AMIGA_DS.D +0 1 +.names N_68_i.BLIF cpu_est_0_.BLIF N_191 11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_25 +.names N_143.BLIF N_143_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_144.BLIF N_144_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_202 +11 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n +0 1 +.names N_93_i.BLIF RW_c.BLIF N_203 +11 1 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names N_20.BLIF N_20_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_23_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names N_19.BLIF N_19_i +0 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_22_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_18.BLIF N_18_i +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names N_182.BLIF N_182_i +0 1 +.names N_181.BLIF N_181_i +0 1 +.names N_260.BLIF N_260_i +0 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D +0 1 +.names N_72.BLIF SM_AMIGA_2_.BLIF N_141 +11 1 +.names N_259.BLIF N_259_i +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_142 +11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_145 +11 1 +.names N_63_0.BLIF N_63 +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_146 +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names N_155.BLIF N_155_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_147 +11 1 +.names N_162.BLIF N_162_i +0 1 +.names N_98.BLIF cpu_est_2_.BLIF N_149 +11 1 +.names un5_e_0.BLIF un5_e +0 1 +.names N_98_i.BLIF cpu_est_2_.BLIF N_154 +11 1 +.names N_154.BLIF N_154_i +0 1 +.names N_82_i.BLIF cpu_est_3_.BLIF N_155 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names N_149.BLIF N_149_i +0 1 +.names G_105.BLIF N_187_i +0 1 +.names N_208.BLIF N_208_i +0 1 +.names G_106.BLIF N_188_i +0 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +0 1 +.names G_107.BLIF N_189_i +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_98_i.BLIF N_98 +0 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_93_i.BLIF N_93 +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_80_i.BLIF N_80 +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names N_72_i.BLIF N_72 +0 1 +.names N_126.BLIF inst_RW_000_DMA.D +0 1 +.names N_68_i.BLIF N_68 +0 1 +.names N_150.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_59_i.BLIF N_59 +0 1 +.names N_151.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_190.BLIF N_190_i +0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names N_191.BLIF N_191_i +0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 +11 1 +.names N_267.BLIF N_267_i +0 1 +.names N_18_i.BLIF RST_c.BLIF N_21_0 +11 1 +.names N_266.BLIF N_266_i +0 1 +.names N_19_i.BLIF RST_c.BLIF N_22_0 +11 1 +.names N_186.BLIF N_186_i +0 1 +.names N_20_i.BLIF RST_c.BLIF N_23_0 +11 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names N_185.BLIF N_185_i +0 1 +.names N_68.BLIF cpu_est_0_1__un3_n +0 1 +.names N_183.BLIF N_183_i +0 1 +.names cpu_est_1_.BLIF N_68.BLIF cpu_est_0_1__un1_n +11 1 +.names N_184.BLIF N_184_i +0 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_268.BLIF N_268_i +0 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names N_132_0.BLIF N_132 +0 1 +.names N_68.BLIF cpu_est_0_2__un3_n +0 1 +.names N_142.BLIF N_142_i +0 1 +.names cpu_est_2_.BLIF N_68.BLIF cpu_est_0_2__un1_n +11 1 +.names N_141.BLIF N_141_i +0 1 +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_135_0.BLIF N_135 +0 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C +1 1 +.names N_134_0.BLIF N_134 +0 1 +.names N_68.BLIF cpu_est_0_3__un3_n +0 1 +.names N_131_i.BLIF N_131 +0 1 +.names cpu_est_3_.BLIF N_68.BLIF cpu_est_0_3__un1_n +11 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D 1- 1 -1 1 .names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names un7_as_030.BLIF un7_as_030_i +.names N_128_i.BLIF N_128 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n 0 1 -.names N_122.BLIF N_122_i +.names N_107_i.BLIF N_107 0 1 -.names N_77.BLIF N_228_i.BLIF N_108_1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n 11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names N_123.BLIF N_123_i +.names N_203.BLIF N_203_i 0 1 -.names N_108_1.BLIF rst_dly_i_2__n.BLIF N_108 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names un6_ds_030.BLIF un6_ds_030_i +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_18 +1- 1 +-1 1 .names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 -.names N_228_i.BLIF rst_dly_i_0__n.BLIF N_114_1 +.names N_201.BLIF N_201_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_202.BLIF N_202_i +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_26 +.names N_60_0.BLIF N_60 +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_274.BLIF N_274_i +0 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_19 1- 1 -1 1 -.names un13_ciin.BLIF un13_ciin_i -0 1 -.names N_114_1.BLIF rst_dly_i_1__n.BLIF N_114 -11 1 -.names N_26_i.BLIF RST_c.BLIF N_29_0 -11 1 -.names N_64.BLIF as_030_000_sync_0_un3_n -0 1 -.names N_277.BLIF BGACK_000_c.BLIF un21_berr_1 -11 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names inst_AS_030_000_SYNC.BLIF N_64.BLIF as_030_000_sync_0_un1_n -11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr -11 1 -.names N_13_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C 1 1 -.names N_277.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names RW_c.BLIF RW_c_i +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 -.names N_20_i.BLIF RST_c.BLIF N_33_0 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_14 +.names N_168.BLIF N_168_i +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_20 1- 1 -1 1 -.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs -11 1 -.names N_23_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n -0 1 -.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_130_1 -11 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 -11 1 -.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n -11 1 -.names N_130_1.BLIF AS_030_i.BLIF N_130 -11 1 -.names N_118_i.BLIF N_119_i.BLIF inst_AS_000_INT.D -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 -.names cpu_est_i_2__n.BLIF VMA_INT_i.BLIF pos_clk_un29_clk_000_ne_1_1_n -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +.names N_167.BLIF N_167_i 0 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_15 +.names un3_as_030.BLIF un3_as_030_i +0 1 +.names N_170.BLIF N_170_i +0 1 +.names N_175.BLIF N_175_i +0 1 +.names N_169.BLIF N_169_i +0 1 +.names N_219.BLIF N_219_i +0 1 +.names N_38_0.BLIF inst_AS_030_D0.D +0 1 +.names un2_ds_030.BLIF un2_ds_030_i +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D1.C +1 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names N_63.BLIF ds_000_enable_0_un3_n +0 1 +.names N_282_0.BLIF N_282 +0 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_63.BLIF ds_000_enable_0_un1_n +11 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names N_96_0.BLIF N_96 +0 1 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF pos_clk_un29_clk_000_ne_1_2_n -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_78_i -11 1 -.names N_15_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names pos_clk_un29_clk_000_ne_1_1_n.BLIF pos_clk_un29_clk_000_ne_1_2_n.BLIF pos_clk_un29_clk_000_ne_1_3_n -11 1 -.names N_78_i.BLIF SM_AMIGA_6_.BLIF N_79_i -11 1 -.names N_14_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names pos_clk_un29_clk_000_ne_1_3_n.BLIF cpu_est_i_1__n.BLIF pos_clk_un29_clk_000_ne_1_n -11 1 -.names N_78.BLIF N_102_i.BLIF N_264_i -11 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 -.names N_78_i.BLIF N_263.BLIF N_261_1 -11 1 -.names N_85_i.BLIF sm_amiga_i_i_7__n.BLIF N_162_0 -11 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_261_2 -11 1 -.names SM_AMIGA_3_.BLIF pos_clk_un31_clk_000_ne_n.BLIF N_161_0 -11 1 -.names N_24_i.BLIF RST_c.BLIF N_27_0 -11 1 -.names N_261_1.BLIF N_261_2.BLIF N_261 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names N_129_i.BLIF N_129 0 1 -.names N_25_i.BLIF RST_c.BLIF N_28_0 -11 1 -.names N_76_i.BLIF N_251_i.BLIF N_262_1 -11 1 -.names N_76_i.BLIF SM_AMIGA_5_.BLIF N_160_0 -11 1 -.names vcc_n_n -1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names N_263.BLIF VPA_D_i.BLIF N_262_2 -11 1 -.names N_78_i.BLIF SM_AMIGA_4_.BLIF N_157_i -11 1 -.names gnd_n_n -.names N_262_1.BLIF N_262_2.BLIF N_262 -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names A_DECODE_15_.BLIF a_decode_15__n -1 1 -.names N_78_i.BLIF RW_c.BLIF DS_000_ENABLE_0_sqmuxa_1_1 -11 1 -.names N_162.BLIF sm_amiga_i_6__n.BLIF N_170 -11 1 -.names A_DECODE_14_.BLIF a_decode_14__n -1 1 -.names DS_000_ENABLE_0_sqmuxa_1_1.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa_1 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names N_15.BLIF N_15_i 0 1 -.names A_DECODE_13_.BLIF a_decode_13__n -1 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_259_1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 -.names N_160.BLIF sm_amiga_i_4__n.BLIF N_168 -11 1 -.names A_DECODE_12_.BLIF a_decode_12__n -1 1 -.names N_259_1.BLIF cpu_est_i_3__n.BLIF N_259 -11 1 -.names N_76_i.BLIF pos_clk_un31_clk_000_ne_n.BLIF N_167 -11 1 -.names A_DECODE_11_.BLIF a_decode_11__n -1 1 -.names N_16_i.BLIF N_254_i.BLIF N_250_i_1 -11 1 -.names N_251.BLIF cpu_est_2_.BLIF N_255 -11 1 -.names A_DECODE_10_.BLIF a_decode_10__n -1 1 -.names un6_amiga_bus_data_dir_1.BLIF un6_amiga_bus_data_dir_2.BLIF un6_amiga_bus_data_dir -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n +.names N_26_0.BLIF inst_LDS_000_INT.D 0 1 -.names A_DECODE_9_.BLIF a_decode_9__n -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names AMIGA_DS_i.BLIF AS_000_i.BLIF pos_clk_as_000_dma6_1_n +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_2__n.BLIF N_16 -11 1 -.names A_DECODE_8_.BLIF a_decode_8__n -1 1 -.names pos_clk_un1_bgack_030_int_n.BLIF pos_clk_un3_n.BLIF pos_clk_as_000_dma6_2_n -11 1 -.names N_252.BLIF cpu_est_2_.BLIF N_254 -11 1 -.names A_DECODE_7_.BLIF a_decode_7__n -1 1 -.names pos_clk_as_000_dma6_1_n.BLIF pos_clk_as_000_dma6_2_n.BLIF pos_clk_as_000_dma6_n -11 1 -.names A_DECODE_6_.BLIF a_decode_6__n -1 1 -.names DS_000_DMA_0_sqmuxa_i.BLIF pos_clk_as_000_dma6_n.BLIF DS_000_DMA_1_sqmuxa_1 -11 1 -.names AS_030_c.BLIF AS_030_i +.names N_12.BLIF N_12_i 0 1 -.names A_DECODE_5_.BLIF a_decode_5__n -1 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_13 +1- 1 +-1 1 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 -.names DS_000_DMA_1_sqmuxa_1.BLIF pos_clk_un4_rw_000_i_n.BLIF DS_000_DMA_1_sqmuxa -11 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names A_DECODE_4_.BLIF a_decode_4__n -1 1 -.names CLK_030_PE_0_.BLIF clk_030_pe_i_1__n.BLIF pos_clk_un4_rw_000_1_n -11 1 -.names N_76.BLIF sm_amiga_i_2__n.BLIF N_102 -11 1 -.names A_DECODE_3_.BLIF a_decode_3__n -1 1 -.names CLK_030_c.BLIF RW_000_i.BLIF pos_clk_un4_rw_000_2_n -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +.names N_28_0.BLIF inst_RW_000_INT.D 0 1 -.names A_DECODE_2_.BLIF a_decode_2__n -1 1 +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D +11 1 +.names N_11.BLIF N_11_i +0 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 +11 1 +.names N_29_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 +11 1 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 -.names pos_clk_un4_rw_000_1_n.BLIF pos_clk_un4_rw_000_2_n.BLIF pos_clk_un4_rw_000_n +.names N_5.BLIF N_5_i +0 1 +.names N_13_i.BLIF RST_c.BLIF N_27_0 11 1 -.names N_85.BLIF sm_amiga_i_i_7__n.BLIF N_103 -11 1 -.names pos_clk_un12_clk_out_int_n.BLIF AS_000_DMA_i.BLIF pos_clk_un13_clk_out_int_1_n -11 1 -.names N_78_i.BLIF SM_AMIGA_0_.BLIF N_104 +.names N_30_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_44_0 11 1 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 -.names pos_clk_un13_clk_out_int_1_n.BLIF pos_clk_un3_clk_out_int_n.BLIF pos_clk_un13_clk_out_int_n -11 1 -.names N_79.BLIF sm_amiga_i_5__n.BLIF N_105 -11 1 -.names N_76_i.BLIF N_137.BLIF N_125_1 -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i +.names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_125_1.BLIF RST_c.BLIF N_125 +.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 11 1 -.names AS_000_INT_i.BLIF N_274.BLIF N_118 -11 1 -.names N_76.BLIF rst_dly_i_0__n.BLIF N_116_1 -11 1 -.names N_79_i.BLIF RST_c.BLIF N_119 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 11 1 +.names N_163.BLIF N_163_i +0 1 +.names vcc_n_n +1 +.names N_244_0.BLIF N_244 +0 1 +.names gnd_n_n .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 -.names N_116_1.BLIF RST_c.BLIF N_116 -11 1 -.names inst_VPA_D.BLIF VPA_D_i +.names N_164.BLIF N_164_i 0 1 -.names N_277_4.BLIF N_277_5.BLIF N_277 -11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +.names A_DECODE_15_.BLIF a_decode_15__n +1 1 +.names N_165.BLIF N_165_i 0 1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 -11 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_76_i -11 1 +.names A_DECODE_14_.BLIF a_decode_14__n +1 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names A_DECODE_13_.BLIF a_decode_13__n +1 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D 1 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_252_0 -11 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names N_180.BLIF N_180_i 0 1 +.names A_DECODE_12_.BLIF a_decode_12__n +1 1 +.names N_262.BLIF N_262_i +0 1 +.names A_DECODE_11_.BLIF a_decode_11__n +1 1 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C 1 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 -11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_251_i -11 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 -11 1 -.names N_261_i.BLIF N_262_i.BLIF pos_clk_un9_clk_000_pe_0_n -11 1 -.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 -11 1 -.names N_258_i.BLIF N_259_i.BLIF cpu_est_2_0_1__n -11 1 -.names CYCLE_DMA_0_.BLIF G_95.X1 -1 1 -.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 -11 1 -.names N_255_i.BLIF N_257_i.BLIF cpu_est_2_0_2__n -11 1 -.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names pos_clk_un13_bgack_030_int_n.BLIF G_95.X2 +.names A_DECODE_10_.BLIF a_decode_10__n 1 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_263 -11 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n +.names pos_clk_un2_i_n.BLIF pos_clk_un2_n 0 1 -.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_258 -11 1 -.names CLK_030_PE_0_.BLIF G_101.X1 +.names A_DECODE_9_.BLIF a_decode_9__n 1 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names N_251_i.BLIF cpu_est_i_2__n.BLIF N_257 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF un6_amiga_bus_data_dir_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_2__n.BLIF N_256 -11 1 -.names pos_clk_un13_clk_out_int_n.BLIF G_101.X2 -1 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF un6_amiga_bus_data_dir_2 -11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n +.names N_3.BLIF N_3_i 0 1 -.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D -11 1 -.names N_76.BLIF rst_dly_i_1__n.BLIF N_113 -11 1 -.names N_166_i.BLIF N_167_i.BLIF N_142_i_1 -11 1 -.names N_77_i.BLIF N_134.BLIF N_112 -11 1 -.names CLK_030_PE_1_.BLIF G_103.X1 +.names A_DECODE_8_.BLIF a_decode_8__n 1 1 -.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D -11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n +.names IPL_D0_0_.BLIF G_105.X1 +1 1 +.names N_32_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_165_i.BLIF N_264_i.BLIF N_140_i_1 -11 1 -.names N_76.BLIF rst_dly_i_2__n.BLIF N_111 -11 1 -.names N_205.BLIF G_103.X2 +.names A_DECODE_7_.BLIF a_decode_7__n 1 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +.names N_4.BLIF N_4_i +0 1 +.names A_DECODE_6_.BLIF a_decode_6__n +1 1 +.names ipl_c_0__n.BLIF G_105.X2 +1 1 +.names N_31_0.BLIF inst_AS_000_DMA.D +0 1 +.names A_DECODE_5_.BLIF a_decode_5__n +1 1 +.names N_220_i.BLIF inst_BGACK_030_INT_D.D +0 1 +.names A_DECODE_4_.BLIF a_decode_4__n +1 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names A_DECODE_3_.BLIF a_decode_3__n +1 1 +.names IPL_D0_1_.BLIF G_106.X1 +1 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 +.names A_DECODE_2_.BLIF a_decode_2__n +1 1 +.names N_17.BLIF N_17_i +0 1 +.names ipl_c_1__n.BLIF G_106.X2 +1 1 +.names N_24_0.BLIF inst_UDS_000_INT.D +0 1 +.names N_16.BLIF N_16_i +0 1 +.names N_25_0.BLIF BG_000DFFreg.D +0 1 +.names IPL_D0_2_.BLIF G_107.X1 +1 1 +.names N_205_i.BLIF N_205 +0 1 +.names N_140.BLIF N_140_i +0 1 +.names ipl_c_2__n.BLIF G_107.X2 +1 1 +.names A_DECODE_16_.BLIF a_decode_c_16__n +1 1 +.names inst_AMIGA_DS.BLIF AMIGA_DS_i +0 1 +.names A_DECODE_17_.BLIF a_decode_c_17__n +1 1 +.names N_199.BLIF N_199_i +0 1 +.names A_DECODE_18_.BLIF a_decode_c_18__n +1 1 +.names N_198.BLIF N_198_i +0 1 +.names CYCLE_DMA_1_.BLIF G_91.X1 +1 1 +.names A_DECODE_19_.BLIF a_decode_c_19__n +1 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names A_DECODE_20_.BLIF a_decode_c_20__n +1 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_262 11 1 -.names N_137.BLIF N_265_2.BLIF N_109 +.names N_199.BLIF G_91.X2 +1 1 +.names A_DECODE_21_.BLIF a_decode_c_21__n +1 1 +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n +0 1 +.names A_DECODE_22_.BLIF a_decode_c_22__n +1 1 +.names cycle_dma_i_0__n.BLIF N_68.BLIF N_198 11 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +.names A_DECODE_23_.BLIF a_decode_c_23__n +1 1 +.names N_180_i.BLIF N_262_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names A_1_.BLIF a_c_1__n +1 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 +.names BG_030.BLIF BG_030_c +1 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names a_c_1__n.BLIF N_220_i.BLIF N_150 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names a_i_1__n.BLIF N_220_i.BLIF N_151 +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 +11 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 +11 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names inst_DS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n +11 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names N_205.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n +0 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n +11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names N_205.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names N_4_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names DTACK.BLIF DTACK_c +1 1 +.names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un2_i_n +11 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names un5_e.BLIF E +1 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP_i +0 1 +.names VPA.BLIF VPA_c +1 1 +.names N_15_i.BLIF RST_c.BLIF N_26_0 +11 1 +.names RST.BLIF RST_c +1 1 +.names N_16_i.BLIF RST_c.BLIF N_25_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names N_17_i.BLIF RST_c.BLIF N_24_0 +11 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +0 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 +1- 1 +-1 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names un11_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_16 +1- 1 +-1 1 +.names N_183_i.BLIF N_184_i.BLIF N_117_i_1 +11 1 +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +0 1 +.names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +11 1 +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n +11 1 +.names N_72.BLIF N_182_i.BLIF N_115_i_1 +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names N_115_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_15 +1- 1 +-1 1 +.names N_72.BLIF N_181_i.BLIF N_111_i_1 +11 1 +.names RST_c.BLIF as_030_d1_0_un3_n +0 1 +.names N_111_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +11 1 +.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_165_1 +11 1 +.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names N_165_1.BLIF AS_030_i.BLIF N_165 +11 1 +.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D +1- 1 +-1 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_162_1 +11 1 +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +0 1 +.names N_162_1.BLIF cpu_est_i_3__n.BLIF N_162 +11 1 +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_148_1 +11 1 +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names N_148_1.BLIF cpu_est_i_3__n.BLIF N_148 +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_12 +1- 1 +-1 1 +.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_244.BLIF as_030_000_sync_0_un3_n +0 1 +.names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n +11 1 +.names AS_030_c.BLIF N_244.BLIF as_030_000_sync_0_un1_n +11 1 +.names N_140_i.BLIF pos_clk_un2_n.BLIF N_205_i_2 +11 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names N_205_i_1.BLIF N_205_i_2.BLIF N_205_i +11 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 +1- 1 +-1 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_1 +11 1 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_180_2 +11 1 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names N_180_1.BLIF N_180_2.BLIF N_180 +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_59_i_1 +11 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 +1- 1 +-1 1 +.names N_59_i_1.BLIF nEXP_SPACE_c.BLIF N_59_i +11 1 +.names BG_030_c_i.BLIF N_59.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names N_267_i.BLIF N_268_i.BLIF N_127_i_1 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names N_93.BLIF N_266_i.BLIF N_123_i_1 +11 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_220_i +11 1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names N_220_i.BLIF RW_000_i.BLIF N_126 +11 1 +.names N_68.BLIF N_186_i.BLIF N_121_i_1 +11 1 +.names N_93.BLIF sm_amiga_i_5__n.BLIF N_186 +11 1 +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 .names SM_AMIGA_0_.BLIF sm_amiga_i_0__n 0 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +.names N_72.BLIF N_185_i.BLIF N_119_i_1 +11 1 +.names N_129.BLIF sm_amiga_i_0__n.BLIF N_181 +11 1 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_93_i.BLIF RST_c.BLIF N_170 +11 1 +.names un21_fpu_cs_1.BLIF N_282_0.BLIF un21_fpu_cs +11 1 +.names N_175.BLIF RST_c.BLIF N_169 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +11 1 +.names N_129_i.BLIF RST_c.BLIF N_168 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +.names un21_berr_1_0.BLIF N_282_0.BLIF un21_berr +11 1 +.names N_219.BLIF RST_c.BLIF N_167 +11 1 +.names AS_000_i.BLIF N_220_i.BLIF pos_clk_cycle_dma_5_1_1__n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D +11 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_164 +11 1 +.names N_68_i.BLIF CYCLE_DMA_0_.BLIF N_199_1 +11 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names N_199_1.BLIF cycle_dma_i_1__n.BLIF N_199 +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 +11 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names AS_000_DMA_1_sqmuxa_1.BLIF N_205_i.BLIF AS_000_DMA_1_sqmuxa +11 1 +.names N_5_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_140_1 +11 1 +.names N_11_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_140_1.BLIF RW_000_i.BLIF N_140 +11 1 +.names N_12_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names AS_000_i.BLIF N_198_i.BLIF N_66_i_1 +11 1 +.names N_164_i.BLIF N_165_i.BLIF un11_amiga_bus_enable_high_i +11 1 +.names N_199_i.BLIF N_220_i.BLIF N_66_i_2 +11 1 +.names AS_030_i.BLIF N_163_i.BLIF N_244_0 +11 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +.names N_66_i_1.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.D +11 1 +.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_69_i +11 1 +.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_205_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +.names N_134_0_1.BLIF SM_AMIGA_3_.BLIF N_134_0 +11 1 +.names AS_000_c.BLIF N_68_i.BLIF N_274 +11 1 +.names N_68.BLIF N_141_i.BLIF N_113_i_1 +11 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names N_142_i.BLIF RST_c.BLIF N_113_i_2 +11 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_219 +11 1 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +.names N_113_i_1.BLIF N_113_i_2.BLIF SM_AMIGA_1_.D +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_68_i.BLIF N_208.BLIF N_144_1 +11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_144_2 +11 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_175 +11 1 +.names N_144_1.BLIF N_144_2.BLIF N_144 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names N_72_i.BLIF N_82_i.BLIF N_143_1 +11 1 +.names N_96.BLIF sm_amiga_i_i_7__n.BLIF N_267 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_143_2 +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +.names N_143_1.BLIF N_143_2.BLIF N_143 +11 1 +.names N_132.BLIF sm_amiga_i_6__n.BLIF N_266 +11 1 +.names AS_030_D1_i.BLIF inst_BGACK_030_INT_D.BLIF N_163_1 +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_282.BLIF sm_amiga_i_i_7__n.BLIF N_163_2 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +.names N_163_1.BLIF N_163_2.BLIF N_163_3 +11 1 +.names inst_AS_030_D1.BLIF AS_030_D1_i +0 1 +.names N_163_3.BLIF un1_dsack1_i.BLIF N_163 +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +11 1 +.names N_96_0.BLIF sm_amiga_i_i_7__n.BLIF N_132_0 +11 1 +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 +11 1 +.names N_268_i.BLIF SM_AMIGA_i_7_.BLIF N_246_i +11 1 +.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +11 1 +.names N_68_i.BLIF SM_AMIGA_1_.BLIF N_129_i +11 1 +.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +11 1 +.names N_93.BLIF N_246_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +11 1 +.names N_169_i.BLIF N_170_i.BLIF inst_AS_000_INT.D +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 +11 1 +.names N_167_i.BLIF N_168_i.BLIF inst_DSACK1_INT.D +11 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names N_246_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names N_80_i.BLIF N_82_i.BLIF N_201_1 +11 1 +.names BGACK_000_c.BLIF N_274_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_201_2 +11 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_60_0 +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +.names N_201_1.BLIF N_201_2.BLIF N_201 +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names BERR_c.BLIF N_201_i.BLIF N_131_i_1 +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_72_i +11 1 +.names N_131_i_1.BLIF N_202_i.BLIF N_131_i +11 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_80_i +11 1 +.names N_68_i.BLIF N_131.BLIF N_134_0_1 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names N_72_i.BLIF SM_AMIGA_6_.BLIF N_93_i +11 1 +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_96_0_1 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_98_i +11 1 +.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_96_0_2 +11 1 +.names N_107.BLIF N_203_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0 +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_282_0_1 +11 1 +.names N_72_i.BLIF SM_AMIGA_4_.BLIF N_107_i +11 1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_282_0_2 +11 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_128_i +11 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 1860a37..4b3d549 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,1586 +1,1250 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Thu Dec 29 16:01:56 2016 +#$ DATE Sat Dec 30 00:43:37 2017 #$ MODULE bus68030 -#$ PINS 75 A_DECODE_2_ A_0_ SIZE_1_ IPL_030_1_ IPL_030_0_ AHIGH_31_ IPL_1_ IPL_0_ \ -# A_DECODE_23_ FC_0_ A_1_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \ -# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI \ -# CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC SIZE_0_ E AHIGH_30_ VPA AHIGH_29_ \ -# VMA AHIGH_28_ RST AHIGH_27_ RESET AHIGH_26_ RW AHIGH_25_ AMIGA_ADDR_ENABLE AHIGH_24_ \ -# AMIGA_BUS_DATA_DIR A_DECODE_22_ AMIGA_BUS_ENABLE_LOW A_DECODE_21_ \ -# AMIGA_BUS_ENABLE_HIGH A_DECODE_20_ CIIN A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ -# A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ A_DECODE_12_ A_DECODE_11_ \ -# A_DECODE_10_ A_DECODE_9_ A_DECODE_8_ A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ \ -# A_DECODE_3_ -#$ NODES 609 clk_000_d_i_1__n VPA_D_i N_125_i a_decode_2__n VMA_INT_i N_124_i \ -# sm_amiga_i_0__n N_53_0 rst_dly_i_2__n N_134_i rst_dly_i_1__n N_270_0 rst_dly_i_0__n \ -# N_77_i DSACK1_INT_i N_87_i inst_BGACK_030_INTreg N_137_i_0 N_112_i vcc_n_n DTACK_D0_i \ -# N_113_i inst_VMA_INTreg BGACK_030_INT_i N_114_i gnd_n_n nEXP_SPACE_i \ -# un1_amiga_bus_enable_low AS_000_DMA_i N_109_i un7_as_030 RW_000_i N_108_i \ -# un1_LDS_000_INT clk_030_pe_i_1__n N_111_i un1_UDS_000_INT DS_000_DMA_0_sqmuxa_i \ -# N_265_2_0 un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un4_rw_000_i_n un10_ciin AS_000_i \ -# un1_as_000_i un21_fpu_cs AMIGA_DS_i VPA_c_i un21_berr pos_clk_un3_clk_out_int_i_n \ -# N_52_0 un6_ds_030 cycle_dma_i_0__n DTACK_c_i un13_ciin cycle_dma_i_1__n N_48_0 \ -# cpu_est_1_ pos_clk_as_000_dma6_i_n un3_ahigh_i cpu_est_2_ DS_000_DMA_i \ -# pos_clk_un4_bgack_000_i_n cpu_est_3_ CLK_EXP_i pos_clk_un6_bgack_000_0_n \ -# cpu_est_0_ AMIGA_BUS_ENABLE_DMA_LOW_i N_7_i inst_AMIGA_BUS_ENABLE_DMA_HIGH \ -# ahigh_i_25__n N_41_0 inst_AMIGA_BUS_ENABLE_DMA_LOW ahigh_i_24__n \ -# pos_clk_un1_bgack_030_int_0_n inst_AS_030_D0 ahigh_i_27__n \ -# pos_clk_un12_clk_out_int_0_n inst_AS_030_000_SYNC ahigh_i_26__n pos_clk_un3_0_n \ -# inst_BGACK_030_INT_D ahigh_i_29__n pos_clk_un15_bgack_030_int_i_n inst_AS_000_DMA \ -# ahigh_i_28__n N_3_i inst_DS_000_DMA ahigh_i_31__n N_43_0 inst_VPA_D ahigh_i_30__n \ -# N_4_i CLK_000_D_3_ a_i_1__n N_42_0 inst_DTACK_D0 AMIGA_BUS_ENABLE_DMA_HIGH_i \ -# un6_amiga_bus_data_dir_i inst_RESET_OUT AS_030_D0_i un12_amiga_bus_data_dir_m_i \ -# CLK_030_PE_1_ un10_ciin_i AMIGA_BUS_DATA_DIR_c_0 inst_AMIGA_DS FPU_SENSE_i N_22_i \ -# CLK_000_D_1_ AS_030_000_SYNC_i N_31_0 CLK_000_D_0_ a_decode_i_16__n N_21_i \ -# inst_CLK_OUT_PRE_50 a_decode_i_18__n N_32_0 inst_CLK_OUT_PRE_D a_decode_i_19__n \ -# N_19_i IPL_D0_0_ N_224_i N_34_0 IPL_D0_1_ N_225_i N_18_i IPL_D0_2_ N_226_i N_35_0 \ -# CLK_000_D_2_ pos_clk_un5_bgack_030_int_d_i_n CLK_000_D_4_ \ -# pos_clk_amiga_bus_enable_dma_high_3_0_n pos_clk_un6_bg_030_n \ -# pos_clk_amiga_bus_enable_dma_low_3_0_n pos_clk_ipl_n pos_clk_rw_000_dma_3_0_n \ -# inst_LDS_000_INT un13_ciin_i UDS_000_c_i inst_DS_000_ENABLE un6_ds_030_i \ -# LDS_000_c_i inst_UDS_000_INT N_123_i N_86_i SM_AMIGA_6_ N_122_i N_129_i SM_AMIGA_4_ \ -# un7_as_030_i N_130_i SM_AMIGA_1_ AS_030_c un11_amiga_bus_enable_high_i SM_AMIGA_0_ \ -# N_117_i SIZE_DMA_0_ AS_000_c N_46_0 SIZE_DMA_1_ N_107_i CYCLE_DMA_0_ RW_000_c \ -# pos_clk_size_dma_6_0_0__n CYCLE_DMA_1_ N_106_i CLK_030_PE_0_ \ -# pos_clk_size_dma_6_0_1__n inst_RW_000_INT UDS_000_c N_16_i inst_RW_000_DMA N_254_i \ -# RST_DLY_0_ LDS_000_c N_263_i RST_DLY_1_ N_250_i RST_DLY_2_ size_c_0__n N_256_i \ -# inst_A0_DMA N_189_i pos_clk_rw_000_int_5_n size_c_1__n N_101_i inst_DSACK1_INT \ -# inst_AS_000_INT ahigh_c_24__n N_103_i SM_AMIGA_5_ N_104_i SM_AMIGA_3_ ahigh_c_25__n \ -# SM_AMIGA_2_ N_105_i ahigh_c_26__n N_115_i ahigh_c_27__n N_116_i ahigh_c_28__n N_131_i \ -# N_277_i ahigh_c_29__n N_64_0 N_91_0 ahigh_c_30__n N_159_0 N_14 N_85_i N_15 \ -# ahigh_c_31__n un1_SM_AMIGA_0_sqmuxa_1_0 N_24 RW_c_i N_25 pos_clk_rw_000_int_5_0_n \ -# clk_000_d_i_3__n N_25_i N_28_0 N_24_i N_27_0 ipl_c_i_1__n N_50_0 ipl_c_i_0__n N_49_0 \ -# N_14_i N_39_0 N_15_i N_38_0 N_91_0_1 N_91_0_2 N_91_0_3 N_265_i_1 N_266_i_1 N_266_i_2 \ -# N_138_i_1 N_148_i_1 N_144_i_1 N_142_i_1 N_140_i_1 SM_AMIGA_i_7_ \ -# pos_clk_un10_sm_amiga_i_1_n N_76 N_85_i_1 G_122 N_85_i_2 G_123 a_decode_c_16__n \ -# N_277_1 G_124 N_277_2 un1_rst_2_1 a_decode_c_17__n N_277_3 cpu_est_0_0_ N_277_4 N_64 \ -# a_decode_c_18__n N_277_5 N_122 un10_ciin_1 N_123 a_decode_c_19__n un10_ciin_2 N_132 \ -# un10_ciin_3 N_133 a_decode_c_20__n un10_ciin_4 N_274 un10_ciin_5 N_276 \ -# a_decode_c_21__n un10_ciin_6 N_77 un10_ciin_7 N_79 a_decode_c_22__n un10_ciin_8 N_78 \ -# un10_ciin_9 N_263 a_decode_c_23__n un10_ciin_10 N_108 un10_ciin_11 N_114 a_c_0__n \ -# un6_amiga_bus_data_dir_1 N_85 un6_amiga_bus_data_dir_2 N_104 a_c_1__n \ -# pos_clk_as_000_dma6_1_n N_91 pos_clk_as_000_dma6_2_n N_131 nEXP_SPACE_c \ -# DS_000_DMA_1_sqmuxa_1 N_277 pos_clk_un4_rw_000_1_n N_130 BERR_c \ -# pos_clk_un4_rw_000_2_n N_115 pos_clk_un13_clk_out_int_1_n N_116 BG_030_c N_125_1 \ -# N_105 N_116_1 N_103 BG_000DFFreg pos_clk_un29_clk_000_ne_1_1_n N_101 \ -# pos_clk_un29_clk_000_ne_1_2_n N_259 pos_clk_un29_clk_000_ne_1_3_n N_255 \ -# BGACK_000_c N_261_1 N_256 N_261_2 N_254 CLK_030_c N_262_1 N_16 N_262_2 N_106 \ -# DS_000_ENABLE_0_sqmuxa_1_1 N_86 N_259_1 N_107 CLK_OSZI_c N_250_i_1 N_117 N_189_i_1 \ -# pos_clk_a0_dma_3_n pos_clk_un6_bg_030_1_n N_129 CLK_OUT_INTreg N_108_1 \ -# pos_clk_size_dma_6_1__n N_114_1 pos_clk_size_dma_6_0__n un21_berr_1 \ -# pos_clk_rw_000_dma_3_n FPU_SENSE_c un21_fpu_cs_1 \ -# pos_clk_amiga_bus_enable_dma_low_3_n N_130_1 \ -# pos_clk_amiga_bus_enable_dma_high_3_n IPL_030DFF_0_reg N_136_i_1 \ -# SIZE_DMA_3_sqmuxa N_152_i_1 pos_clk_un5_bgack_030_int_d_n IPL_030DFF_1_reg \ -# N_146_i_1 N_18 N_267_i_1 N_19 IPL_030DFF_2_reg pos_clk_ipl_1_n N_21 bg_000_0_un3_n \ -# N_22 ipl_c_0__n bg_000_0_un1_n un6_amiga_bus_data_dir bg_000_0_un0_n \ -# un12_amiga_bus_data_dir_m ipl_c_1__n uds_000_int_0_un3_n \ -# pos_clk_un3_clk_out_int_n uds_000_int_0_un1_n N_3 ipl_c_2__n uds_000_int_0_un0_n \ -# pos_clk_as_000_dma6_n lds_000_int_0_un3_n DS_000_DMA_1_sqmuxa lds_000_int_0_un1_n \ -# N_4 DTACK_c lds_000_int_0_un0_n AS_000_DMA_1_sqmuxa ds_000_enable_0_un3_n un1_rst_2 \ -# ds_000_enable_0_un1_n G_97 ds_000_enable_0_un0_n N_199 VPA_c ipl_030_0_2__un3_n \ -# pos_clk_un13_bgack_030_int_n ipl_030_0_2__un1_n N_205 ipl_030_0_2__un0_n \ -# pos_clk_un13_clk_out_int_n RST_c vma_int_0_un3_n pos_clk_un15_bgack_030_int_n \ -# vma_int_0_un1_n pos_clk_un3_n RESET_c vma_int_0_un0_n pos_clk_un12_clk_out_int_n \ -# cpu_est_0_1__un3_n pos_clk_un1_bgack_030_int_n RW_c cpu_est_0_1__un1_n \ -# DS_000_DMA_0_sqmuxa cpu_est_0_1__un0_n un1_rst_3 fc_c_0__n cpu_est_0_2__un3_n G_95 \ -# cpu_est_0_2__un1_n G_101 fc_c_1__n cpu_est_0_2__un0_n G_103 cpu_est_0_3__un3_n \ -# pos_clk_un4_rw_000_n cpu_est_0_3__un1_n N_7 AMIGA_BUS_DATA_DIR_c \ -# cpu_est_0_3__un0_n pos_clk_un6_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un3_n \ -# pos_clk_un4_bgack_000_n pos_clk_un31_clk_000_ne_1_i_m2_un1_n N_265_2 \ -# pos_clk_un31_clk_000_ne_1_i_m2_un0_n N_111 bgack_030_int_0_un3_n N_109 BG_030_c_i \ -# bgack_030_int_0_un1_n N_113 pos_clk_un6_bg_030_i_n bgack_030_int_0_un0_n N_112 \ -# pos_clk_un9_bg_030_0_n ds_000_dma_0_un3_n N_98 UDS_000_INT_i ds_000_dma_0_un1_n \ -# pos_clk_un29_clk_000_ne_1_n un1_UDS_000_INT_0 ds_000_dma_0_un0_n N_87 \ -# LDS_000_INT_i as_000_dma_0_un3_n N_270 un1_LDS_000_INT_0 as_000_dma_0_un1_n N_134 \ -# N_23_i as_000_dma_0_un0_n N_125 N_30_0 size_dma_0_1__un3_n N_124 N_20_i \ -# size_dma_0_1__un1_n N_121 N_33_0 size_dma_0_1__un0_n N_120 N_13_i \ -# size_dma_0_0__un3_n N_137 N_40_0 size_dma_0_0__un1_n pos_clk_un31_clk_000_ne_n \ -# ipl_c_i_2__n size_dma_0_0__un0_n N_17 N_51_0 amiga_bus_enable_dma_high_0_un3_n \ -# pos_clk_un9_clk_000_pe_n N_26_i amiga_bus_enable_dma_high_0_un1_n cpu_est_2_1__n \ -# N_29_0 amiga_bus_enable_dma_high_0_un0_n cpu_est_2_2__n a_c_i_0__n \ -# amiga_bus_enable_dma_low_0_un3_n N_261 size_c_i_1__n \ -# amiga_bus_enable_dma_low_0_un1_n N_262 pos_clk_un10_sm_amiga_i_n \ -# amiga_bus_enable_dma_low_0_un0_n N_251 DS_000_ENABLE_0_sqmuxa_1_i a0_dma_0_un3_n \ -# N_252 un1_DS_000_ENABLE_0_sqmuxa_i a0_dma_0_un1_n N_258 N_157_i a0_dma_0_un0_n N_257 \ -# N_160_0 rw_000_dma_0_un3_n DS_000_ENABLE_1_sqmuxa N_161_0 rw_000_dma_0_un1_n \ -# un1_DS_000_ENABLE_0_sqmuxa N_162_0 rw_000_dma_0_un0_n N_102 N_165_i \ -# ipl_030_0_0__un3_n N_118 ipl_030_0_0__un1_n N_119 N_167_i ipl_030_0_0__un0_n N_264 \ -# N_166_i ipl_030_0_1__un3_n DS_000_ENABLE_0_sqmuxa_1 ipl_030_0_1__un1_n N_164 \ -# N_168_i ipl_030_0_1__un0_n N_170 as_030_000_sync_0_un3_n N_168 N_170_i \ -# as_030_000_sync_0_un1_n N_166 as_030_000_sync_0_un0_n N_167 N_164_i \ -# rw_000_int_0_un3_n N_165 rw_000_int_0_un1_n N_162 N_102_i rw_000_int_0_un0_n N_161 \ -# N_264_i a_decode_15__n N_160 N_79_i N_157 N_78_i a_decode_14__n N_26 N_119_i N_13 \ -# N_118_i a_decode_13__n N_20 N_23 N_255_i a_decode_12__n N_8 N_257_i \ -# pos_clk_un9_bg_030_n cpu_est_2_0_2__n a_decode_11__n un1_amiga_bus_enable_low_i \ -# N_258_i un21_fpu_cs_i N_259_i a_decode_10__n sm_amiga_i_2__n cpu_est_2_0_1__n \ -# sm_amiga_i_1__n N_262_i a_decode_9__n sm_amiga_i_3__n N_261_i sm_amiga_i_4__n \ -# pos_clk_un9_clk_000_pe_0_n a_decode_8__n sm_amiga_i_6__n N_251_i sm_amiga_i_5__n \ -# N_252_0 a_decode_7__n clk_000_d_i_0__n N_76_i AS_000_INT_i N_17_i a_decode_6__n \ -# sm_amiga_i_i_7__n N_36_0 AS_030_i N_98_i a_decode_5__n cpu_est_i_2__n \ -# pos_clk_un31_clk_000_ne_i_n cpu_est_i_0__n N_228_i a_decode_4__n cpu_est_i_3__n \ -# N_121_i cpu_est_i_1__n N_120_i a_decode_3__n +#$ PINS 75 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ \ +# A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ +# IPL_030_2_ A_DECODE_16_ A_DECODE_15_ IPL_2_ A_DECODE_14_ A_DECODE_13_ FC_1_ \ +# A_DECODE_12_ AS_030 A_DECODE_11_ AS_000 A_DECODE_10_ RW_000 A_DECODE_9_ DS_030 \ +# A_DECODE_8_ UDS_000 A_DECODE_7_ LDS_000 A_DECODE_6_ nEXP_SPACE A_DECODE_5_ BERR \ +# A_DECODE_4_ BG_030 A_DECODE_3_ BG_000 A_DECODE_2_ BGACK_030 A_0_ BGACK_000 IPL_030_1_ \ +# CLK_030 IPL_030_0_ CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS \ +# FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ \ +# AHIGH_28_ +#$ NODES 508 N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n \ +# ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n inst_BGACK_030_INTreg N_42_0 vcc_n_n \ +# ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n DTACK_c_i \ +# un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i un1_UDS_000_INT \ +# N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 \ +# un10_ciin ahigh_c_28__n LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr \ +# ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 cpu_est_0_ ahigh_c_30__n \ +# N_96_0_1 cpu_est_1_ N_96_0_2 cpu_est_2_ ahigh_c_31__n N_282_0_1 cpu_est_3_ N_282_0_2 \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_282_0_3 inst_AMIGA_BUS_ENABLE_DMA_LOW N_282_0_4 \ +# inst_AS_030_D0 pos_clk_un10_sm_amiga_i_1_n inst_AS_030_D1 un10_ciin_1 \ +# inst_AS_030_000_SYNC un10_ciin_2 inst_AS_000_DMA un10_ciin_3 inst_DS_000_DMA \ +# un10_ciin_4 inst_VMA_INTreg un10_ciin_5 inst_VPA_D un10_ciin_6 CLK_000_D_3_ \ +# un10_ciin_7 inst_DTACK_D0 un10_ciin_8 inst_AMIGA_DS un10_ciin_9 CLK_000_D_1_ \ +# un10_ciin_10 CLK_000_D_0_ un10_ciin_11 inst_CLK_OUT_PRE_50 N_201_1 \ +# inst_CLK_OUT_PRE_D N_201_2 IPL_D0_0_ N_131_i_1 IPL_D0_1_ N_134_0_1 IPL_D0_2_ \ +# N_113_i_1 CLK_000_D_2_ N_113_i_2 CLK_000_D_4_ N_144_1 pos_clk_ipl_n N_144_2 \ +# SIZE_DMA_0_ N_143_1 SIZE_DMA_1_ N_143_2 inst_A0_DMA N_163_1 inst_RW_000_DMA N_163_2 \ +# inst_UDS_000_INT N_163_3 inst_DS_000_ENABLE un21_fpu_cs_1 inst_LDS_000_INT \ +# a_decode_c_16__n un21_berr_1_0 inst_BGACK_030_INT_D pos_clk_cycle_dma_5_1_1__n \ +# SM_AMIGA_6_ a_decode_c_17__n N_199_1 inst_RW_000_INT AS_000_DMA_1_sqmuxa_1 \ +# SM_AMIGA_4_ a_decode_c_18__n N_140_1 SM_AMIGA_1_ N_66_i_1 SM_AMIGA_0_ \ +# a_decode_c_19__n N_66_i_2 CYCLE_DMA_0_ N_205_i_1 CYCLE_DMA_1_ a_decode_c_20__n \ +# N_205_i_2 inst_DSACK1_INT N_180_1 inst_AS_000_INT a_decode_c_21__n N_180_2 \ +# pos_clk_un9_clk_000_pe_n N_59_i_1 SM_AMIGA_5_ a_decode_c_22__n N_127_i_1 \ +# SM_AMIGA_3_ N_123_i_1 SM_AMIGA_2_ a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n \ +# N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 \ +# BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ +# ds_000_dma_0_un0_n BG_000DFFreg as_000_dma_0_un3_n as_000_dma_0_un1_n \ +# as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n \ +# uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c \ +# lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n CLK_OUT_INTreg \ +# as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c \ +# rw_000_int_0_un3_n rw_000_int_0_un1_n IPL_030DFF_0_reg rw_000_int_0_un0_n \ +# as_030_000_sync_0_un3_n IPL_030DFF_1_reg as_030_000_sync_0_un1_n SM_AMIGA_i_7_ \ +# as_030_000_sync_0_un0_n IPL_030DFF_2_reg bgack_030_int_0_un3_n \ +# bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n \ +# cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ +# G_105 cpu_est_0_1__un0_n G_106 ipl_c_2__n cpu_est_0_2__un3_n G_107 \ +# cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 \ +# cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ +# ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ +# ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ +# ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 \ +# fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n \ +# vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ +# AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ +# a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 \ +# a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i \ +# a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n a_decode_8__n N_181 \ +# N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 a_decode_6__n N_185 N_220_i \ +# N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 N_17_i \ +# a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 N_15_i \ +# a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 \ +# un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n \ +# un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i \ +# N_167 N_163_i N_168 N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n \ +# N_165_i N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i \ +# N_11 pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i \ +# N_17 N_167_i pos_clk_un9_bg_030_n G_91 N_170_i N_3 N_169_i N_205 AS_000_DMA_1_sqmuxa \ +# N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n \ +# N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i \ +# N_132_0 un21_fpu_cs_i AS_000_i N_142_i BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 \ +# cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ +# UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i \ +# AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i \ +# a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ +# N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i \ +# sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i \ +# sm_amiga_i_1__n N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n \ +# cpu_est_i_3__n N_266_i VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n \ +# cpu_est_i_1__n N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i \ +# cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i \ +# ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n \ +# ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ +# ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i \ +# cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i N_148_i \ +# N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c N_145_i N_35_0 \ +# AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ -BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF VPA.BLIF \ -RST.BLIF RESET.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ +BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF \ +RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF \ A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF \ A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF A_DECODE_8_.BLIF \ A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF \ A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF \ -LDS_000.BLIF BERR.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF \ -AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF \ -AHIGH_24_.BLIF A_0_.BLIF clk_000_d_i_1__n.BLIF VPA_D_i.BLIF N_125_i.BLIF \ -a_decode_2__n.BLIF VMA_INT_i.BLIF N_124_i.BLIF sm_amiga_i_0__n.BLIF \ -N_53_0.BLIF rst_dly_i_2__n.BLIF N_134_i.BLIF rst_dly_i_1__n.BLIF N_270_0.BLIF \ -rst_dly_i_0__n.BLIF N_77_i.BLIF DSACK1_INT_i.BLIF N_87_i.BLIF \ -inst_BGACK_030_INTreg.BLIF N_137_i_0.BLIF N_112_i.BLIF vcc_n_n.BLIF \ -DTACK_D0_i.BLIF N_113_i.BLIF inst_VMA_INTreg.BLIF BGACK_030_INT_i.BLIF \ -N_114_i.BLIF gnd_n_n.BLIF nEXP_SPACE_i.BLIF un1_amiga_bus_enable_low.BLIF \ -AS_000_DMA_i.BLIF N_109_i.BLIF un7_as_030.BLIF RW_000_i.BLIF N_108_i.BLIF \ -un1_LDS_000_INT.BLIF clk_030_pe_i_1__n.BLIF N_111_i.BLIF un1_UDS_000_INT.BLIF \ -DS_000_DMA_0_sqmuxa_i.BLIF N_265_2_0.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ -pos_clk_un4_rw_000_i_n.BLIF un10_ciin.BLIF AS_000_i.BLIF un1_as_000_i.BLIF \ -un21_fpu_cs.BLIF AMIGA_DS_i.BLIF VPA_c_i.BLIF un21_berr.BLIF \ -pos_clk_un3_clk_out_int_i_n.BLIF N_52_0.BLIF un6_ds_030.BLIF \ -cycle_dma_i_0__n.BLIF DTACK_c_i.BLIF un13_ciin.BLIF cycle_dma_i_1__n.BLIF \ -N_48_0.BLIF cpu_est_1_.BLIF pos_clk_as_000_dma6_i_n.BLIF un3_ahigh_i.BLIF \ -cpu_est_2_.BLIF DS_000_DMA_i.BLIF pos_clk_un4_bgack_000_i_n.BLIF \ -cpu_est_3_.BLIF CLK_EXP_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_7_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -ahigh_i_25__n.BLIF N_41_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -ahigh_i_24__n.BLIF pos_clk_un1_bgack_030_int_0_n.BLIF inst_AS_030_D0.BLIF \ -ahigh_i_27__n.BLIF pos_clk_un12_clk_out_int_0_n.BLIF inst_AS_030_000_SYNC.BLIF \ -ahigh_i_26__n.BLIF pos_clk_un3_0_n.BLIF inst_BGACK_030_INT_D.BLIF \ -ahigh_i_29__n.BLIF pos_clk_un15_bgack_030_int_i_n.BLIF inst_AS_000_DMA.BLIF \ -ahigh_i_28__n.BLIF N_3_i.BLIF inst_DS_000_DMA.BLIF ahigh_i_31__n.BLIF \ -N_43_0.BLIF inst_VPA_D.BLIF ahigh_i_30__n.BLIF N_4_i.BLIF CLK_000_D_3_.BLIF \ -a_i_1__n.BLIF N_42_0.BLIF inst_DTACK_D0.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ -un6_amiga_bus_data_dir_i.BLIF inst_RESET_OUT.BLIF AS_030_D0_i.BLIF \ -un12_amiga_bus_data_dir_m_i.BLIF CLK_030_PE_1_.BLIF un10_ciin_i.BLIF \ -AMIGA_BUS_DATA_DIR_c_0.BLIF inst_AMIGA_DS.BLIF FPU_SENSE_i.BLIF N_22_i.BLIF \ -CLK_000_D_1_.BLIF AS_030_000_SYNC_i.BLIF N_31_0.BLIF CLK_000_D_0_.BLIF \ -a_decode_i_16__n.BLIF N_21_i.BLIF inst_CLK_OUT_PRE_50.BLIF \ -a_decode_i_18__n.BLIF N_32_0.BLIF inst_CLK_OUT_PRE_D.BLIF \ -a_decode_i_19__n.BLIF N_19_i.BLIF IPL_D0_0_.BLIF N_224_i.BLIF N_34_0.BLIF \ -IPL_D0_1_.BLIF N_225_i.BLIF N_18_i.BLIF IPL_D0_2_.BLIF N_226_i.BLIF \ -N_35_0.BLIF CLK_000_D_2_.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \ -CLK_000_D_4_.BLIF pos_clk_amiga_bus_enable_dma_high_3_0_n.BLIF \ -pos_clk_un6_bg_030_n.BLIF pos_clk_amiga_bus_enable_dma_low_3_0_n.BLIF \ -pos_clk_ipl_n.BLIF pos_clk_rw_000_dma_3_0_n.BLIF inst_LDS_000_INT.BLIF \ -un13_ciin_i.BLIF UDS_000_c_i.BLIF inst_DS_000_ENABLE.BLIF un6_ds_030_i.BLIF \ -LDS_000_c_i.BLIF inst_UDS_000_INT.BLIF N_123_i.BLIF N_86_i.BLIF \ -SM_AMIGA_6_.BLIF N_122_i.BLIF N_129_i.BLIF SM_AMIGA_4_.BLIF un7_as_030_i.BLIF \ -N_130_i.BLIF SM_AMIGA_1_.BLIF AS_030_c.BLIF un11_amiga_bus_enable_high_i.BLIF \ -SM_AMIGA_0_.BLIF N_117_i.BLIF SIZE_DMA_0_.BLIF AS_000_c.BLIF N_46_0.BLIF \ -SIZE_DMA_1_.BLIF N_107_i.BLIF CYCLE_DMA_0_.BLIF RW_000_c.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF CYCLE_DMA_1_.BLIF N_106_i.BLIF \ -CLK_030_PE_0_.BLIF pos_clk_size_dma_6_0_1__n.BLIF inst_RW_000_INT.BLIF \ -UDS_000_c.BLIF N_16_i.BLIF inst_RW_000_DMA.BLIF N_254_i.BLIF RST_DLY_0_.BLIF \ -LDS_000_c.BLIF N_263_i.BLIF RST_DLY_1_.BLIF N_250_i.BLIF RST_DLY_2_.BLIF \ -size_c_0__n.BLIF N_256_i.BLIF inst_A0_DMA.BLIF N_189_i.BLIF \ -pos_clk_rw_000_int_5_n.BLIF size_c_1__n.BLIF N_101_i.BLIF inst_DSACK1_INT.BLIF \ -inst_AS_000_INT.BLIF ahigh_c_24__n.BLIF N_103_i.BLIF SM_AMIGA_5_.BLIF \ -N_104_i.BLIF SM_AMIGA_3_.BLIF ahigh_c_25__n.BLIF SM_AMIGA_2_.BLIF N_105_i.BLIF \ -ahigh_c_26__n.BLIF N_115_i.BLIF ahigh_c_27__n.BLIF N_116_i.BLIF \ -ahigh_c_28__n.BLIF N_131_i.BLIF N_277_i.BLIF ahigh_c_29__n.BLIF N_64_0.BLIF \ -N_91_0.BLIF ahigh_c_30__n.BLIF N_159_0.BLIF N_14.BLIF N_85_i.BLIF N_15.BLIF \ -ahigh_c_31__n.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_24.BLIF RW_c_i.BLIF \ -N_25.BLIF pos_clk_rw_000_int_5_0_n.BLIF clk_000_d_i_3__n.BLIF N_25_i.BLIF \ -N_28_0.BLIF N_24_i.BLIF N_27_0.BLIF ipl_c_i_1__n.BLIF N_50_0.BLIF \ -ipl_c_i_0__n.BLIF N_49_0.BLIF N_14_i.BLIF N_39_0.BLIF N_15_i.BLIF N_38_0.BLIF \ -N_91_0_1.BLIF N_91_0_2.BLIF N_91_0_3.BLIF N_265_i_1.BLIF N_266_i_1.BLIF \ -N_266_i_2.BLIF N_138_i_1.BLIF N_148_i_1.BLIF N_144_i_1.BLIF N_142_i_1.BLIF \ -N_140_i_1.BLIF SM_AMIGA_i_7_.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_76.BLIF \ -N_85_i_1.BLIF G_122.BLIF N_85_i_2.BLIF G_123.BLIF a_decode_c_16__n.BLIF \ -N_277_1.BLIF G_124.BLIF N_277_2.BLIF un1_rst_2_1.BLIF a_decode_c_17__n.BLIF \ -N_277_3.BLIF cpu_est_0_0_.BLIF N_277_4.BLIF N_64.BLIF a_decode_c_18__n.BLIF \ -N_277_5.BLIF N_122.BLIF un10_ciin_1.BLIF N_123.BLIF a_decode_c_19__n.BLIF \ -un10_ciin_2.BLIF N_132.BLIF un10_ciin_3.BLIF N_133.BLIF a_decode_c_20__n.BLIF \ -un10_ciin_4.BLIF N_274.BLIF un10_ciin_5.BLIF N_276.BLIF a_decode_c_21__n.BLIF \ -un10_ciin_6.BLIF N_77.BLIF un10_ciin_7.BLIF N_79.BLIF a_decode_c_22__n.BLIF \ -un10_ciin_8.BLIF N_78.BLIF un10_ciin_9.BLIF N_263.BLIF a_decode_c_23__n.BLIF \ -un10_ciin_10.BLIF N_108.BLIF un10_ciin_11.BLIF N_114.BLIF a_c_0__n.BLIF \ -un6_amiga_bus_data_dir_1.BLIF N_85.BLIF un6_amiga_bus_data_dir_2.BLIF \ -N_104.BLIF a_c_1__n.BLIF pos_clk_as_000_dma6_1_n.BLIF N_91.BLIF \ -pos_clk_as_000_dma6_2_n.BLIF N_131.BLIF nEXP_SPACE_c.BLIF \ -DS_000_DMA_1_sqmuxa_1.BLIF N_277.BLIF pos_clk_un4_rw_000_1_n.BLIF N_130.BLIF \ -BERR_c.BLIF pos_clk_un4_rw_000_2_n.BLIF N_115.BLIF \ -pos_clk_un13_clk_out_int_1_n.BLIF N_116.BLIF BG_030_c.BLIF N_125_1.BLIF \ -N_105.BLIF N_116_1.BLIF N_103.BLIF BG_000DFFreg.BLIF \ -pos_clk_un29_clk_000_ne_1_1_n.BLIF N_101.BLIF \ -pos_clk_un29_clk_000_ne_1_2_n.BLIF N_259.BLIF \ -pos_clk_un29_clk_000_ne_1_3_n.BLIF N_255.BLIF BGACK_000_c.BLIF N_261_1.BLIF \ -N_256.BLIF N_261_2.BLIF N_254.BLIF CLK_030_c.BLIF N_262_1.BLIF N_16.BLIF \ -N_262_2.BLIF N_106.BLIF DS_000_ENABLE_0_sqmuxa_1_1.BLIF N_86.BLIF N_259_1.BLIF \ -N_107.BLIF CLK_OSZI_c.BLIF N_250_i_1.BLIF N_117.BLIF N_189_i_1.BLIF \ -pos_clk_a0_dma_3_n.BLIF pos_clk_un6_bg_030_1_n.BLIF N_129.BLIF \ -CLK_OUT_INTreg.BLIF N_108_1.BLIF pos_clk_size_dma_6_1__n.BLIF N_114_1.BLIF \ -pos_clk_size_dma_6_0__n.BLIF un21_berr_1.BLIF pos_clk_rw_000_dma_3_n.BLIF \ -FPU_SENSE_c.BLIF un21_fpu_cs_1.BLIF pos_clk_amiga_bus_enable_dma_low_3_n.BLIF \ -N_130_1.BLIF pos_clk_amiga_bus_enable_dma_high_3_n.BLIF IPL_030DFF_0_reg.BLIF \ -N_136_i_1.BLIF SIZE_DMA_3_sqmuxa.BLIF N_152_i_1.BLIF \ -pos_clk_un5_bgack_030_int_d_n.BLIF IPL_030DFF_1_reg.BLIF N_146_i_1.BLIF \ -N_18.BLIF N_267_i_1.BLIF N_19.BLIF IPL_030DFF_2_reg.BLIF pos_clk_ipl_1_n.BLIF \ -N_21.BLIF bg_000_0_un3_n.BLIF N_22.BLIF ipl_c_0__n.BLIF bg_000_0_un1_n.BLIF \ -un6_amiga_bus_data_dir.BLIF bg_000_0_un0_n.BLIF un12_amiga_bus_data_dir_m.BLIF \ -ipl_c_1__n.BLIF uds_000_int_0_un3_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ -uds_000_int_0_un1_n.BLIF N_3.BLIF ipl_c_2__n.BLIF uds_000_int_0_un0_n.BLIF \ -pos_clk_as_000_dma6_n.BLIF lds_000_int_0_un3_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \ -lds_000_int_0_un1_n.BLIF N_4.BLIF DTACK_c.BLIF lds_000_int_0_un0_n.BLIF \ -AS_000_DMA_1_sqmuxa.BLIF ds_000_enable_0_un3_n.BLIF un1_rst_2.BLIF \ -ds_000_enable_0_un1_n.BLIF G_97.BLIF ds_000_enable_0_un0_n.BLIF N_199.BLIF \ -VPA_c.BLIF ipl_030_0_2__un3_n.BLIF pos_clk_un13_bgack_030_int_n.BLIF \ -ipl_030_0_2__un1_n.BLIF N_205.BLIF ipl_030_0_2__un0_n.BLIF \ -pos_clk_un13_clk_out_int_n.BLIF RST_c.BLIF vma_int_0_un3_n.BLIF \ -pos_clk_un15_bgack_030_int_n.BLIF vma_int_0_un1_n.BLIF pos_clk_un3_n.BLIF \ -RESET_c.BLIF vma_int_0_un0_n.BLIF pos_clk_un12_clk_out_int_n.BLIF \ -cpu_est_0_1__un3_n.BLIF pos_clk_un1_bgack_030_int_n.BLIF RW_c.BLIF \ -cpu_est_0_1__un1_n.BLIF DS_000_DMA_0_sqmuxa.BLIF cpu_est_0_1__un0_n.BLIF \ -un1_rst_3.BLIF fc_c_0__n.BLIF cpu_est_0_2__un3_n.BLIF G_95.BLIF \ -cpu_est_0_2__un1_n.BLIF G_101.BLIF fc_c_1__n.BLIF cpu_est_0_2__un0_n.BLIF \ -G_103.BLIF cpu_est_0_3__un3_n.BLIF pos_clk_un4_rw_000_n.BLIF \ -cpu_est_0_3__un1_n.BLIF N_7.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -cpu_est_0_3__un0_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un3_n.BLIF pos_clk_un4_bgack_000_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un1_n.BLIF N_265_2.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un0_n.BLIF N_111.BLIF \ -bgack_030_int_0_un3_n.BLIF N_109.BLIF BG_030_c_i.BLIF \ -bgack_030_int_0_un1_n.BLIF N_113.BLIF pos_clk_un6_bg_030_i_n.BLIF \ -bgack_030_int_0_un0_n.BLIF N_112.BLIF pos_clk_un9_bg_030_0_n.BLIF \ -ds_000_dma_0_un3_n.BLIF N_98.BLIF UDS_000_INT_i.BLIF ds_000_dma_0_un1_n.BLIF \ -pos_clk_un29_clk_000_ne_1_n.BLIF un1_UDS_000_INT_0.BLIF \ -ds_000_dma_0_un0_n.BLIF N_87.BLIF LDS_000_INT_i.BLIF as_000_dma_0_un3_n.BLIF \ -N_270.BLIF un1_LDS_000_INT_0.BLIF as_000_dma_0_un1_n.BLIF N_134.BLIF \ -N_23_i.BLIF as_000_dma_0_un0_n.BLIF N_125.BLIF N_30_0.BLIF \ -size_dma_0_1__un3_n.BLIF N_124.BLIF N_20_i.BLIF size_dma_0_1__un1_n.BLIF \ -N_121.BLIF N_33_0.BLIF size_dma_0_1__un0_n.BLIF N_120.BLIF N_13_i.BLIF \ -size_dma_0_0__un3_n.BLIF N_137.BLIF N_40_0.BLIF size_dma_0_0__un1_n.BLIF \ -pos_clk_un31_clk_000_ne_n.BLIF ipl_c_i_2__n.BLIF size_dma_0_0__un0_n.BLIF \ -N_17.BLIF N_51_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \ -pos_clk_un9_clk_000_pe_n.BLIF N_26_i.BLIF \ -amiga_bus_enable_dma_high_0_un1_n.BLIF cpu_est_2_1__n.BLIF N_29_0.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF cpu_est_2_2__n.BLIF a_c_i_0__n.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF N_261.BLIF size_c_i_1__n.BLIF \ -amiga_bus_enable_dma_low_0_un1_n.BLIF N_262.BLIF \ -pos_clk_un10_sm_amiga_i_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF \ -N_251.BLIF DS_000_ENABLE_0_sqmuxa_1_i.BLIF a0_dma_0_un3_n.BLIF N_252.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa_i.BLIF a0_dma_0_un1_n.BLIF N_258.BLIF N_157_i.BLIF \ -a0_dma_0_un0_n.BLIF N_257.BLIF N_160_0.BLIF rw_000_dma_0_un3_n.BLIF \ -DS_000_ENABLE_1_sqmuxa.BLIF N_161_0.BLIF rw_000_dma_0_un1_n.BLIF \ -un1_DS_000_ENABLE_0_sqmuxa.BLIF N_162_0.BLIF rw_000_dma_0_un0_n.BLIF \ -N_102.BLIF N_165_i.BLIF ipl_030_0_0__un3_n.BLIF N_118.BLIF \ -ipl_030_0_0__un1_n.BLIF N_119.BLIF N_167_i.BLIF ipl_030_0_0__un0_n.BLIF \ -N_264.BLIF N_166_i.BLIF ipl_030_0_1__un3_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF \ -ipl_030_0_1__un1_n.BLIF N_164.BLIF N_168_i.BLIF ipl_030_0_1__un0_n.BLIF \ -N_170.BLIF as_030_000_sync_0_un3_n.BLIF N_168.BLIF N_170_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_166.BLIF as_030_000_sync_0_un0_n.BLIF \ -N_167.BLIF N_164_i.BLIF rw_000_int_0_un3_n.BLIF N_165.BLIF \ -rw_000_int_0_un1_n.BLIF N_162.BLIF N_102_i.BLIF rw_000_int_0_un0_n.BLIF \ -N_161.BLIF N_264_i.BLIF a_decode_15__n.BLIF N_160.BLIF N_79_i.BLIF N_157.BLIF \ -N_78_i.BLIF a_decode_14__n.BLIF N_26.BLIF N_119_i.BLIF N_13.BLIF N_118_i.BLIF \ -a_decode_13__n.BLIF N_20.BLIF N_23.BLIF N_255_i.BLIF a_decode_12__n.BLIF \ -N_8.BLIF N_257_i.BLIF pos_clk_un9_bg_030_n.BLIF cpu_est_2_0_2__n.BLIF \ -a_decode_11__n.BLIF un1_amiga_bus_enable_low_i.BLIF N_258_i.BLIF \ -un21_fpu_cs_i.BLIF N_259_i.BLIF a_decode_10__n.BLIF sm_amiga_i_2__n.BLIF \ -cpu_est_2_0_1__n.BLIF sm_amiga_i_1__n.BLIF N_262_i.BLIF a_decode_9__n.BLIF \ -sm_amiga_i_3__n.BLIF N_261_i.BLIF sm_amiga_i_4__n.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF a_decode_8__n.BLIF sm_amiga_i_6__n.BLIF \ -N_251_i.BLIF sm_amiga_i_5__n.BLIF N_252_0.BLIF a_decode_7__n.BLIF \ -clk_000_d_i_0__n.BLIF N_76_i.BLIF AS_000_INT_i.BLIF N_17_i.BLIF \ -a_decode_6__n.BLIF sm_amiga_i_i_7__n.BLIF N_36_0.BLIF AS_030_i.BLIF \ -N_98_i.BLIF a_decode_5__n.BLIF cpu_est_i_2__n.BLIF \ -pos_clk_un31_clk_000_ne_i_n.BLIF cpu_est_i_0__n.BLIF N_228_i.BLIF \ -a_decode_4__n.BLIF cpu_est_i_3__n.BLIF N_121_i.BLIF cpu_est_i_1__n.BLIF \ -N_120_i.BLIF a_decode_3__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ +LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF \ +AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF \ +A_0_.BLIF N_23_0.BLIF UDS_000_c.BLIF N_19_i.BLIF N_22_0.BLIF LDS_000_c.BLIF \ +N_18_i.BLIF N_21_0.BLIF size_c_0__n.BLIF ipl_c_i_2__n.BLIF N_43_0.BLIF \ +size_c_1__n.BLIF ipl_c_i_1__n.BLIF inst_BGACK_030_INTreg.BLIF N_42_0.BLIF \ +vcc_n_n.BLIF ahigh_c_24__n.BLIF ipl_c_i_0__n.BLIF un5_e.BLIF N_41_0.BLIF \ +gnd_n_n.BLIF ahigh_c_25__n.BLIF DTACK_c_i.BLIF un1_amiga_bus_enable_low.BLIF \ +N_45_0.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF VPA_c_i.BLIF \ +un1_UDS_000_INT.BLIF N_44_0.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF \ +N_13_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_27_0.BLIF un10_ciin.BLIF \ +ahigh_c_28__n.BLIF LDS_000_INT_i.BLIF un21_fpu_cs.BLIF un1_LDS_000_INT_0.BLIF \ +un21_berr.BLIF ahigh_c_29__n.BLIF UDS_000_INT_i.BLIF un2_ds_030.BLIF \ +un1_UDS_000_INT_0.BLIF cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_96_0_1.BLIF \ +cpu_est_1_.BLIF N_96_0_2.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF \ +N_282_0_1.BLIF cpu_est_3_.BLIF N_282_0_2.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_282_0_3.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_282_0_4.BLIF inst_AS_030_D0.BLIF \ +pos_clk_un10_sm_amiga_i_1_n.BLIF inst_AS_030_D1.BLIF un10_ciin_1.BLIF \ +inst_AS_030_000_SYNC.BLIF un10_ciin_2.BLIF inst_AS_000_DMA.BLIF \ +un10_ciin_3.BLIF inst_DS_000_DMA.BLIF un10_ciin_4.BLIF inst_VMA_INTreg.BLIF \ +un10_ciin_5.BLIF inst_VPA_D.BLIF un10_ciin_6.BLIF CLK_000_D_3_.BLIF \ +un10_ciin_7.BLIF inst_DTACK_D0.BLIF un10_ciin_8.BLIF inst_AMIGA_DS.BLIF \ +un10_ciin_9.BLIF CLK_000_D_1_.BLIF un10_ciin_10.BLIF CLK_000_D_0_.BLIF \ +un10_ciin_11.BLIF inst_CLK_OUT_PRE_50.BLIF N_201_1.BLIF \ +inst_CLK_OUT_PRE_D.BLIF N_201_2.BLIF IPL_D0_0_.BLIF N_131_i_1.BLIF \ +IPL_D0_1_.BLIF N_134_0_1.BLIF IPL_D0_2_.BLIF N_113_i_1.BLIF CLK_000_D_2_.BLIF \ +N_113_i_2.BLIF CLK_000_D_4_.BLIF N_144_1.BLIF pos_clk_ipl_n.BLIF N_144_2.BLIF \ +SIZE_DMA_0_.BLIF N_143_1.BLIF SIZE_DMA_1_.BLIF N_143_2.BLIF inst_A0_DMA.BLIF \ +N_163_1.BLIF inst_RW_000_DMA.BLIF N_163_2.BLIF inst_UDS_000_INT.BLIF \ +N_163_3.BLIF inst_DS_000_ENABLE.BLIF un21_fpu_cs_1.BLIF inst_LDS_000_INT.BLIF \ +a_decode_c_16__n.BLIF un21_berr_1_0.BLIF inst_BGACK_030_INT_D.BLIF \ +pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_6_.BLIF a_decode_c_17__n.BLIF \ +N_199_1.BLIF inst_RW_000_INT.BLIF AS_000_DMA_1_sqmuxa_1.BLIF SM_AMIGA_4_.BLIF \ +a_decode_c_18__n.BLIF N_140_1.BLIF SM_AMIGA_1_.BLIF N_66_i_1.BLIF \ +SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.BLIF \ +N_205_i_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_205_i_2.BLIF \ +inst_DSACK1_INT.BLIF N_180_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF \ +N_180_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_59_i_1.BLIF SM_AMIGA_5_.BLIF \ +a_decode_c_22__n.BLIF N_127_i_1.BLIF SM_AMIGA_3_.BLIF N_123_i_1.BLIF \ +SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_121_i_1.BLIF N_119_i_1.BLIF N_6.BLIF \ +a_c_0__n.BLIF N_117_i_1.BLIF N_115_i_1.BLIF a_c_1__n.BLIF N_111_i_1.BLIF \ +N_165_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_162_1.BLIF N_148_1.BLIF N_18.BLIF \ +BERR_c.BLIF pos_clk_ipl_1_n.BLIF N_19.BLIF ds_000_dma_0_un3_n.BLIF N_20.BLIF \ +BG_030_c.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \ +BG_000DFFreg.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF \ +as_000_dma_0_un0_n.BLIF BGACK_000_c.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF \ +bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF CLK_OSZI_c.BLIF \ +lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ +CLK_OUT_INTreg.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un1_n.BLIF \ +as_030_d1_0_un0_n.BLIF FPU_SENSE_c.BLIF rw_000_int_0_un3_n.BLIF \ +rw_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF rw_000_int_0_un0_n.BLIF \ +as_030_000_sync_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF \ +as_030_000_sync_0_un1_n.BLIF SM_AMIGA_i_7_.BLIF as_030_000_sync_0_un0_n.BLIF \ +IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF \ +cpu_est_2_1__n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF \ +cpu_est_2_2__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_2_3__n.BLIF \ +ipl_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF G_105.BLIF cpu_est_0_1__un0_n.BLIF \ +G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_2__un3_n.BLIF G_107.BLIF \ +cpu_est_0_2__un1_n.BLIF N_60.BLIF cpu_est_0_2__un0_n.BLIF N_63.BLIF \ +DTACK_c.BLIF cpu_est_0_3__un3_n.BLIF N_126.BLIF cpu_est_0_3__un1_n.BLIF \ +N_150.BLIF cpu_est_0_3__un0_n.BLIF N_151.BLIF ipl_030_0_0__un3_n.BLIF \ +N_219.BLIF VPA_c.BLIF ipl_030_0_0__un1_n.BLIF N_175.BLIF \ +ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF N_59.BLIF RST_c.BLIF \ +ipl_030_0_1__un1_n.BLIF N_68.BLIF ipl_030_0_1__un0_n.BLIF N_72.BLIF \ +ipl_030_0_2__un3_n.BLIF N_80.BLIF ipl_030_0_2__un1_n.BLIF N_93.BLIF RW_c.BLIF \ +ipl_030_0_2__un0_n.BLIF N_98.BLIF ds_000_enable_0_un3_n.BLIF N_107.BLIF \ +fc_c_0__n.BLIF ds_000_enable_0_un1_n.BLIF N_128.BLIF \ +ds_000_enable_0_un0_n.BLIF N_131.BLIF fc_c_1__n.BLIF vma_int_0_un3_n.BLIF \ +N_134.BLIF vma_int_0_un1_n.BLIF N_135.BLIF vma_int_0_un0_n.BLIF N_141.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF a_decode_15__n.BLIF N_142.BLIF N_143.BLIF \ +a_decode_14__n.BLIF N_144.BLIF N_145.BLIF a_decode_13__n.BLIF N_146.BLIF \ +N_205_i.BLIF N_147.BLIF N_140_i.BLIF a_decode_12__n.BLIF N_148.BLIF \ +AMIGA_DS_i.BLIF N_149.BLIF a_decode_11__n.BLIF N_154.BLIF N_199_i.BLIF \ +N_155.BLIF N_198_i.BLIF a_decode_10__n.BLIF N_162.BLIF N_180_i.BLIF N_165.BLIF \ +N_262_i.BLIF a_decode_9__n.BLIF N_259.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ +N_260.BLIF pos_clk_un2_i_n.BLIF a_decode_8__n.BLIF N_181.BLIF N_3_i.BLIF \ +N_182.BLIF N_32_0.BLIF a_decode_7__n.BLIF N_183.BLIF N_4_i.BLIF N_184.BLIF \ +N_31_0.BLIF a_decode_6__n.BLIF N_185.BLIF N_220_i.BLIF N_186.BLIF \ +BG_030_c_i.BLIF a_decode_5__n.BLIF N_266.BLIF pos_clk_un9_bg_030_0_n.BLIF \ +N_267.BLIF N_17_i.BLIF a_decode_4__n.BLIF N_268.BLIF N_24_0.BLIF N_190.BLIF \ +N_16_i.BLIF a_decode_3__n.BLIF N_191.BLIF N_25_0.BLIF N_201.BLIF N_15_i.BLIF \ +a_decode_2__n.BLIF N_202.BLIF N_26_0.BLIF N_203.BLIF N_12_i.BLIF N_208.BLIF \ +N_28_0.BLIF N_163.BLIF N_11_i.BLIF N_282.BLIF N_29_0.BLIF un21_berr_1.BLIF \ +N_5_i.BLIF N_132.BLIF N_30_0.BLIF N_96.BLIF a_c_i_0__n.BLIF N_129.BLIF \ +size_c_i_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF pos_clk_un10_sm_amiga_i_n.BLIF \ +N_169.BLIF un1_dsack1_i.BLIF N_170.BLIF N_69_i.BLIF N_167.BLIF N_163_i.BLIF \ +N_168.BLIF N_244_0.BLIF pos_clk_rw_000_int_5_n.BLIF N_164_i.BLIF \ +pos_clk_un6_bgack_000_n.BLIF N_165_i.BLIF N_274.BLIF \ +un11_amiga_bus_enable_high_i.BLIF N_164.BLIF un10_ciin_i.BLIF N_244.BLIF \ +N_60_0.BLIF N_5.BLIF N_274_i.BLIF N_11.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ +N_12.BLIF RW_c_i.BLIF N_15.BLIF pos_clk_rw_000_int_5_0_n.BLIF N_16.BLIF \ +N_168_i.BLIF N_17.BLIF N_167_i.BLIF pos_clk_un9_bg_030_n.BLIF G_91.BLIF \ +N_170_i.BLIF N_3.BLIF N_169_i.BLIF N_205.BLIF AS_000_DMA_1_sqmuxa.BLIF \ +N_38_0.BLIF N_4.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_199.BLIF N_282_0.BLIF \ +pos_clk_un2_n.BLIF clk_000_d_i_3__n.BLIF N_140.BLIF N_96_0.BLIF N_262.BLIF \ +N_129_i.BLIF N_198.BLIF N_268_i.BLIF N_180.BLIF N_246_i.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_132_0.BLIF un21_fpu_cs_i.BLIF AS_000_i.BLIF \ +N_142_i.BLIF BGACK_030_INT_i.BLIF N_141_i.BLIF nEXP_SPACE_i.BLIF N_135_0.BLIF \ +cycle_dma_i_0__n.BLIF N_134_0.BLIF RW_000_i.BLIF N_131_i.BLIF CLK_EXP_i.BLIF \ +LDS_000_c_i.BLIF cycle_dma_i_1__n.BLIF UDS_000_c_i.BLIF DS_000_DMA_i.BLIF \ +N_128_i.BLIF AS_000_DMA_i.BLIF N_107_i.BLIF a_i_1__n.BLIF N_203_i.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF \ +a_decode_i_19__n.BLIF N_201_i.BLIF a_decode_i_18__n.BLIF N_202_i.BLIF \ +a_decode_i_16__n.BLIF VMA_INT_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ +N_98_i.BLIF sm_amiga_i_0__n.BLIF N_93_i.BLIF sm_amiga_i_5__n.BLIF N_82_i.BLIF \ +sm_amiga_i_6__n.BLIF N_80_i.BLIF sm_amiga_i_i_7__n.BLIF N_72_i.BLIF \ +AS_030_i.BLIF N_68_i.BLIF AS_000_INT_i.BLIF N_59_i.BLIF DSACK1_INT_i.BLIF \ +N_190_i.BLIF sm_amiga_i_1__n.BLIF N_191_i.BLIF FPU_SENSE_i.BLIF \ +AS_030_D1_i.BLIF N_267_i.BLIF cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ +N_266_i.BLIF VPA_D_i.BLIF sm_amiga_i_3__n.BLIF N_186_i.BLIF \ +sm_amiga_i_4__n.BLIF cpu_est_i_1__n.BLIF N_185_i.BLIF clk_000_d_i_0__n.BLIF \ +clk_000_d_i_1__n.BLIF N_183_i.BLIF AS_030_D0_i.BLIF N_184_i.BLIF \ +cpu_est_i_2__n.BLIF DTACK_D0_i.BLIF N_182_i.BLIF sm_amiga_i_2__n.BLIF \ +AS_030_000_SYNC_i.BLIF N_181_i.BLIF ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF \ +N_260_i.BLIF ahigh_i_28__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ +ahigh_i_29__n.BLIF N_259_i.BLIF ahigh_i_26__n.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF ahigh_i_27__n.BLIF N_63_0.BLIF \ +ahigh_i_24__n.BLIF N_155_i.BLIF ahigh_i_25__n.BLIF N_162_i.BLIF N_187_i.BLIF \ +un5_e_0.BLIF N_188_i.BLIF N_154_i.BLIF N_189_i.BLIF cpu_est_2_0_3__n.BLIF \ +N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n.BLIF N_147_i.BLIF un2_ds_030_i.BLIF \ +N_148_i.BLIF N_219_i.BLIF cpu_est_2_0_1__n.BLIF N_175_i.BLIF N_146_i.BLIF \ +un3_as_030_i.BLIF N_36_0.BLIF AS_030_c.BLIF N_145_i.BLIF N_35_0.BLIF \ +AS_000_c.BLIF N_143_i.BLIF N_144_i.BLIF RW_000_c.BLIF \ +pos_clk_un9_clk_000_pe_0_n.BLIF N_20_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF +AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ -SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ -cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ +SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ -CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D \ -CLK_000_D_4_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C \ -CLK_030_PE_0_.D CLK_030_PE_0_.C CLK_030_PE_1_.D CLK_030_PE_1_.C SIZE_DMA_0_.D \ -SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ -RST_DLY_2_.D RST_DLY_2_.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ +CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ +SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D \ +CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ +cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ -inst_AMIGA_DS.D inst_AMIGA_DS.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_VPA_D.D inst_VPA_D.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ -BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ \ -AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR DTACK RW SIZE_0_ AHIGH_30_ \ -AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \ -clk_000_d_i_1__n VPA_D_i N_125_i a_decode_2__n VMA_INT_i N_124_i \ -sm_amiga_i_0__n N_53_0 rst_dly_i_2__n N_134_i rst_dly_i_1__n N_270_0 \ -rst_dly_i_0__n N_77_i DSACK1_INT_i N_87_i N_137_i_0 N_112_i vcc_n_n DTACK_D0_i \ -N_113_i BGACK_030_INT_i N_114_i gnd_n_n nEXP_SPACE_i un1_amiga_bus_enable_low \ -AS_000_DMA_i N_109_i un7_as_030 RW_000_i N_108_i un1_LDS_000_INT \ -clk_030_pe_i_1__n N_111_i un1_UDS_000_INT DS_000_DMA_0_sqmuxa_i N_265_2_0 \ -un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un4_rw_000_i_n un10_ciin AS_000_i un1_as_000_i \ -un21_fpu_cs AMIGA_DS_i VPA_c_i un21_berr pos_clk_un3_clk_out_int_i_n N_52_0 \ -un6_ds_030 cycle_dma_i_0__n DTACK_c_i un13_ciin cycle_dma_i_1__n N_48_0 \ -pos_clk_as_000_dma6_i_n un3_ahigh_i DS_000_DMA_i pos_clk_un4_bgack_000_i_n \ -CLK_EXP_i pos_clk_un6_bgack_000_0_n AMIGA_BUS_ENABLE_DMA_LOW_i N_7_i \ -ahigh_i_25__n N_41_0 ahigh_i_24__n pos_clk_un1_bgack_030_int_0_n ahigh_i_27__n \ -pos_clk_un12_clk_out_int_0_n ahigh_i_26__n pos_clk_un3_0_n ahigh_i_29__n \ -pos_clk_un15_bgack_030_int_i_n ahigh_i_28__n N_3_i ahigh_i_31__n N_43_0 \ -ahigh_i_30__n N_4_i a_i_1__n N_42_0 AMIGA_BUS_ENABLE_DMA_HIGH_i \ -un6_amiga_bus_data_dir_i AS_030_D0_i un12_amiga_bus_data_dir_m_i un10_ciin_i \ -AMIGA_BUS_DATA_DIR_c_0 FPU_SENSE_i N_22_i AS_030_000_SYNC_i N_31_0 \ -a_decode_i_16__n N_21_i a_decode_i_18__n N_32_0 a_decode_i_19__n N_19_i \ -N_224_i N_34_0 N_225_i N_18_i N_226_i N_35_0 pos_clk_un5_bgack_030_int_d_i_n \ -pos_clk_amiga_bus_enable_dma_high_3_0_n pos_clk_un6_bg_030_n \ -pos_clk_amiga_bus_enable_dma_low_3_0_n pos_clk_ipl_n pos_clk_rw_000_dma_3_0_n \ -un13_ciin_i UDS_000_c_i un6_ds_030_i LDS_000_c_i N_123_i N_86_i N_122_i \ -N_129_i un7_as_030_i N_130_i AS_030_c un11_amiga_bus_enable_high_i N_117_i \ -AS_000_c N_46_0 N_107_i RW_000_c pos_clk_size_dma_6_0_0__n N_106_i \ -pos_clk_size_dma_6_0_1__n UDS_000_c N_16_i N_254_i LDS_000_c N_263_i N_250_i \ -size_c_0__n N_256_i N_189_i pos_clk_rw_000_int_5_n size_c_1__n N_101_i \ -ahigh_c_24__n N_103_i N_104_i ahigh_c_25__n N_105_i ahigh_c_26__n N_115_i \ -ahigh_c_27__n N_116_i ahigh_c_28__n N_131_i N_277_i ahigh_c_29__n N_64_0 \ -N_91_0 ahigh_c_30__n N_159_0 N_14 N_85_i N_15 ahigh_c_31__n \ -un1_SM_AMIGA_0_sqmuxa_1_0 N_24 RW_c_i N_25 pos_clk_rw_000_int_5_0_n \ -clk_000_d_i_3__n N_25_i N_28_0 N_24_i N_27_0 ipl_c_i_1__n N_50_0 ipl_c_i_0__n \ -N_49_0 N_14_i N_39_0 N_15_i N_38_0 N_91_0_1 N_91_0_2 N_91_0_3 N_265_i_1 \ -N_266_i_1 N_266_i_2 N_138_i_1 N_148_i_1 N_144_i_1 N_142_i_1 N_140_i_1 \ -pos_clk_un10_sm_amiga_i_1_n N_76 N_85_i_1 N_85_i_2 a_decode_c_16__n N_277_1 \ -N_277_2 un1_rst_2_1 a_decode_c_17__n N_277_3 N_277_4 N_64 a_decode_c_18__n \ -N_277_5 N_122 un10_ciin_1 N_123 a_decode_c_19__n un10_ciin_2 N_132 un10_ciin_3 \ -N_133 a_decode_c_20__n un10_ciin_4 N_274 un10_ciin_5 N_276 a_decode_c_21__n \ -un10_ciin_6 N_77 un10_ciin_7 N_79 a_decode_c_22__n un10_ciin_8 N_78 \ -un10_ciin_9 N_263 a_decode_c_23__n un10_ciin_10 N_108 un10_ciin_11 N_114 \ -a_c_0__n un6_amiga_bus_data_dir_1 N_85 un6_amiga_bus_data_dir_2 N_104 a_c_1__n \ -pos_clk_as_000_dma6_1_n N_91 pos_clk_as_000_dma6_2_n N_131 nEXP_SPACE_c \ -DS_000_DMA_1_sqmuxa_1 N_277 pos_clk_un4_rw_000_1_n N_130 BERR_c \ -pos_clk_un4_rw_000_2_n N_115 pos_clk_un13_clk_out_int_1_n N_116 BG_030_c \ -N_125_1 N_105 N_116_1 N_103 pos_clk_un29_clk_000_ne_1_1_n N_101 \ -pos_clk_un29_clk_000_ne_1_2_n N_259 pos_clk_un29_clk_000_ne_1_3_n N_255 \ -BGACK_000_c N_261_1 N_256 N_261_2 N_254 CLK_030_c N_262_1 N_16 N_262_2 N_106 \ -DS_000_ENABLE_0_sqmuxa_1_1 N_86 N_259_1 N_107 CLK_OSZI_c N_250_i_1 N_117 \ -N_189_i_1 pos_clk_a0_dma_3_n pos_clk_un6_bg_030_1_n N_129 N_108_1 \ -pos_clk_size_dma_6_1__n N_114_1 pos_clk_size_dma_6_0__n un21_berr_1 \ -pos_clk_rw_000_dma_3_n FPU_SENSE_c un21_fpu_cs_1 \ -pos_clk_amiga_bus_enable_dma_low_3_n N_130_1 \ -pos_clk_amiga_bus_enable_dma_high_3_n N_136_i_1 SIZE_DMA_3_sqmuxa N_152_i_1 \ -pos_clk_un5_bgack_030_int_d_n N_146_i_1 N_18 N_267_i_1 N_19 pos_clk_ipl_1_n \ -N_21 bg_000_0_un3_n N_22 ipl_c_0__n bg_000_0_un1_n un6_amiga_bus_data_dir \ -bg_000_0_un0_n un12_amiga_bus_data_dir_m ipl_c_1__n uds_000_int_0_un3_n \ -pos_clk_un3_clk_out_int_n uds_000_int_0_un1_n N_3 ipl_c_2__n \ -uds_000_int_0_un0_n pos_clk_as_000_dma6_n lds_000_int_0_un3_n \ -DS_000_DMA_1_sqmuxa lds_000_int_0_un1_n N_4 DTACK_c lds_000_int_0_un0_n \ -AS_000_DMA_1_sqmuxa ds_000_enable_0_un3_n un1_rst_2 ds_000_enable_0_un1_n \ -ds_000_enable_0_un0_n N_199 VPA_c ipl_030_0_2__un3_n \ -pos_clk_un13_bgack_030_int_n ipl_030_0_2__un1_n N_205 ipl_030_0_2__un0_n \ -pos_clk_un13_clk_out_int_n RST_c vma_int_0_un3_n pos_clk_un15_bgack_030_int_n \ -vma_int_0_un1_n pos_clk_un3_n RESET_c vma_int_0_un0_n \ -pos_clk_un12_clk_out_int_n cpu_est_0_1__un3_n pos_clk_un1_bgack_030_int_n RW_c \ -cpu_est_0_1__un1_n DS_000_DMA_0_sqmuxa cpu_est_0_1__un0_n un1_rst_3 fc_c_0__n \ -cpu_est_0_2__un3_n cpu_est_0_2__un1_n fc_c_1__n cpu_est_0_2__un0_n \ -cpu_est_0_3__un3_n pos_clk_un4_rw_000_n cpu_est_0_3__un1_n N_7 \ -AMIGA_BUS_DATA_DIR_c cpu_est_0_3__un0_n pos_clk_un6_bgack_000_n \ -pos_clk_un31_clk_000_ne_1_i_m2_un3_n pos_clk_un4_bgack_000_n \ -pos_clk_un31_clk_000_ne_1_i_m2_un1_n N_265_2 \ -pos_clk_un31_clk_000_ne_1_i_m2_un0_n N_111 bgack_030_int_0_un3_n N_109 \ -BG_030_c_i bgack_030_int_0_un1_n N_113 pos_clk_un6_bg_030_i_n \ -bgack_030_int_0_un0_n N_112 pos_clk_un9_bg_030_0_n ds_000_dma_0_un3_n N_98 \ -UDS_000_INT_i ds_000_dma_0_un1_n pos_clk_un29_clk_000_ne_1_n un1_UDS_000_INT_0 \ -ds_000_dma_0_un0_n N_87 LDS_000_INT_i as_000_dma_0_un3_n N_270 \ -un1_LDS_000_INT_0 as_000_dma_0_un1_n N_134 N_23_i as_000_dma_0_un0_n N_125 \ -N_30_0 size_dma_0_1__un3_n N_124 N_20_i size_dma_0_1__un1_n N_121 N_33_0 \ -size_dma_0_1__un0_n N_120 N_13_i size_dma_0_0__un3_n N_137 N_40_0 \ -size_dma_0_0__un1_n pos_clk_un31_clk_000_ne_n ipl_c_i_2__n size_dma_0_0__un0_n \ -N_17 N_51_0 amiga_bus_enable_dma_high_0_un3_n pos_clk_un9_clk_000_pe_n N_26_i \ -amiga_bus_enable_dma_high_0_un1_n cpu_est_2_1__n N_29_0 \ -amiga_bus_enable_dma_high_0_un0_n cpu_est_2_2__n a_c_i_0__n \ -amiga_bus_enable_dma_low_0_un3_n N_261 size_c_i_1__n \ -amiga_bus_enable_dma_low_0_un1_n N_262 pos_clk_un10_sm_amiga_i_n \ -amiga_bus_enable_dma_low_0_un0_n N_251 DS_000_ENABLE_0_sqmuxa_1_i \ -a0_dma_0_un3_n N_252 un1_DS_000_ENABLE_0_sqmuxa_i a0_dma_0_un1_n N_258 N_157_i \ -a0_dma_0_un0_n N_257 N_160_0 rw_000_dma_0_un3_n DS_000_ENABLE_1_sqmuxa N_161_0 \ -rw_000_dma_0_un1_n un1_DS_000_ENABLE_0_sqmuxa N_162_0 rw_000_dma_0_un0_n N_102 \ -N_165_i ipl_030_0_0__un3_n N_118 ipl_030_0_0__un1_n N_119 N_167_i \ -ipl_030_0_0__un0_n N_264 N_166_i ipl_030_0_1__un3_n DS_000_ENABLE_0_sqmuxa_1 \ -ipl_030_0_1__un1_n N_164 N_168_i ipl_030_0_1__un0_n N_170 \ -as_030_000_sync_0_un3_n N_168 N_170_i as_030_000_sync_0_un1_n N_166 \ -as_030_000_sync_0_un0_n N_167 N_164_i rw_000_int_0_un3_n N_165 \ -rw_000_int_0_un1_n N_162 N_102_i rw_000_int_0_un0_n N_161 N_264_i \ -a_decode_15__n N_160 N_79_i N_157 N_78_i a_decode_14__n N_26 N_119_i N_13 \ -N_118_i a_decode_13__n N_20 N_23 N_255_i a_decode_12__n N_8 N_257_i \ -pos_clk_un9_bg_030_n cpu_est_2_0_2__n a_decode_11__n \ -un1_amiga_bus_enable_low_i N_258_i un21_fpu_cs_i N_259_i a_decode_10__n \ -sm_amiga_i_2__n cpu_est_2_0_1__n sm_amiga_i_1__n N_262_i a_decode_9__n \ -sm_amiga_i_3__n N_261_i sm_amiga_i_4__n pos_clk_un9_clk_000_pe_0_n \ -a_decode_8__n sm_amiga_i_6__n N_251_i sm_amiga_i_5__n N_252_0 a_decode_7__n \ -clk_000_d_i_0__n N_76_i AS_000_INT_i N_17_i a_decode_6__n sm_amiga_i_i_7__n \ -N_36_0 AS_030_i N_98_i a_decode_5__n cpu_est_i_2__n \ -pos_clk_un31_clk_000_ne_i_n cpu_est_i_0__n N_228_i a_decode_4__n \ -cpu_est_i_3__n N_121_i cpu_est_i_1__n N_120_i a_decode_3__n AS_030.OE \ -AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ -AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ -AHIGH_31_.OE A_0_.OE BERR.OE DTACK.OE RW.OE DS_030.OE DSACK1.OE CIIN.OE G_122 \ -G_123 G_124 cpu_est_0_0_ G_97 G_95 G_101 G_103 -.names N_152_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ +inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ +RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c \ +N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n N_42_0 \ +vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n \ +DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i \ +un1_UDS_000_INT N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i \ +un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n LDS_000_INT_i \ +un21_fpu_cs un1_LDS_000_INT_0 un21_berr ahigh_c_29__n UDS_000_INT_i un2_ds_030 \ +un1_UDS_000_INT_0 ahigh_c_30__n N_96_0_1 N_96_0_2 ahigh_c_31__n N_282_0_1 \ +N_282_0_2 N_282_0_3 N_282_0_4 pos_clk_un10_sm_amiga_i_1_n un10_ciin_1 \ +un10_ciin_2 un10_ciin_3 un10_ciin_4 un10_ciin_5 un10_ciin_6 un10_ciin_7 \ +un10_ciin_8 un10_ciin_9 un10_ciin_10 un10_ciin_11 N_201_1 N_201_2 N_131_i_1 \ +N_134_0_1 N_113_i_1 N_113_i_2 N_144_1 pos_clk_ipl_n N_144_2 N_143_1 N_143_2 \ +N_163_1 N_163_2 N_163_3 un21_fpu_cs_1 a_decode_c_16__n un21_berr_1_0 \ +pos_clk_cycle_dma_5_1_1__n a_decode_c_17__n N_199_1 AS_000_DMA_1_sqmuxa_1 \ +a_decode_c_18__n N_140_1 N_66_i_1 a_decode_c_19__n N_66_i_2 N_205_i_1 \ +a_decode_c_20__n N_205_i_2 N_180_1 a_decode_c_21__n N_180_2 \ +pos_clk_un9_clk_000_pe_n N_59_i_1 a_decode_c_22__n N_127_i_1 N_123_i_1 \ +a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n \ +N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 BERR_c \ +pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ +ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ +BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c lds_000_int_0_un3_n \ +lds_000_int_0_un1_n lds_000_int_0_un0_n as_030_d1_0_un3_n as_030_d1_0_un1_n \ +as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n rw_000_int_0_un1_n \ +rw_000_int_0_un0_n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ +as_030_000_sync_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n \ +cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n \ +cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ +cpu_est_0_1__un0_n ipl_c_2__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n N_60 \ +cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 cpu_est_0_3__un1_n \ +N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ +ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ +ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ +ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n \ +N_107 fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 \ +fc_c_1__n vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ +AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ +a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i \ +N_149 a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i \ +N_165 N_262_i a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n \ +a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 \ +a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 \ +pos_clk_un9_bg_030_0_n N_267 N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i \ +a_decode_3__n N_191 N_25_0 N_201 N_15_i a_decode_2__n N_202 N_26_0 N_203 \ +N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 un21_berr_1 N_5_i N_132 N_30_0 \ +N_96 a_c_i_0__n N_129 size_c_i_1__n un1_SM_AMIGA_0_sqmuxa_1 \ +pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 \ +N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i N_274 \ +un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i N_11 \ +pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 \ +N_168_i N_17 N_167_i pos_clk_un9_bg_030_n N_170_i N_3 N_169_i N_205 \ +AS_000_DMA_1_sqmuxa N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 \ +pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 \ +N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i \ +BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i \ +N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n UDS_000_c_i DS_000_DMA_i \ +N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i \ +un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i a_decode_i_18__n N_202_i \ +a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n \ +N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i sm_amiga_i_i_7__n N_72_i \ +AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i sm_amiga_i_1__n \ +N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i \ +VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n N_185_i \ +clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i cpu_est_i_2__n \ +DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i ahigh_i_30__n \ +ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n ahigh_i_29__n \ +N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ +ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i \ +N_189_i cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i \ +N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c \ +N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n \ +N_20_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ +SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ +AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ +DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 -.names N_148_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +.names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D 11 1 -.names N_146_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +.names N_115_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 -.names N_144_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +.names N_113_i_1.BLIF N_113_i_2.BLIF SM_AMIGA_1_.D 11 1 -.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +.names N_111_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D 11 1 -.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +.names N_21_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_22_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names N_23_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_41_0.BLIF IPL_D0_0_.D +0 1 +.names N_42_0.BLIF IPL_D0_1_.D +0 1 +.names N_43_0.BLIF IPL_D0_2_.D +0 1 +.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 -.names N_136_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D +0 1 +.names N_66_i_1.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.D +11 1 +.names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D +11 1 +.names N_190_i.BLIF N_191_i.BLIF cpu_est_0_.D +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D 1- 1 -1 1 -.names N_27_0.BLIF IPL_030DFF_0_reg.D +.names N_151.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D 0 1 -.names N_28_0.BLIF IPL_030DFF_1_reg.D +.names N_44_0.BLIF inst_VPA_D.D 0 1 -.names N_29_0.BLIF IPL_030DFF_2_reg.D +.names N_45_0.BLIF inst_DTACK_D0.D 0 1 -.names N_49_0.BLIF IPL_D0_0_.D -0 1 -.names N_50_0.BLIF IPL_D0_1_.D -0 1 -.names N_51_0.BLIF IPL_D0_2_.D -0 1 -.names G_95.BLIF un1_rst_2.BLIF CYCLE_DMA_0_.D +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names G_97.BLIF un1_rst_2.BLIF CYCLE_DMA_1_.D +.names N_25_0.BLIF BG_000DFFreg.D +0 1 +.names N_26_0.BLIF inst_LDS_000_INT.D +0 1 +.names N_27_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_28_0.BLIF inst_RW_000_INT.D +0 1 +.names N_29_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names N_30_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names N_31_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_32_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_167_i.BLIF N_168_i.BLIF inst_DSACK1_INT.D 11 1 -.names G_101.BLIF un1_rst_3.BLIF CLK_030_PE_0_.D +.names N_169_i.BLIF N_170_i.BLIF inst_AS_000_INT.D 11 1 -.names G_103.BLIF un1_rst_3.BLIF CLK_030_PE_1_.D -11 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +.names N_35_0.BLIF inst_AMIGA_DS.D +0 1 +.names N_36_0.BLIF inst_A0_DMA.D +0 1 +.names N_126.BLIF inst_RW_000_DMA.D +0 1 +.names N_38_0.BLIF inst_AS_030_D0.D +0 1 +.names N_150.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D 1- 1 -1 1 -.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D -1- 1 --1 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D +.names N_24_0.BLIF inst_UDS_000_INT.D 0 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names N_267_i_1.BLIF RST_c.BLIF RST_DLY_0_.D -11 1 -.names N_266_i_1.BLIF N_266_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_265_i_1.BLIF N_265_2_0.BLIF RST_DLY_2_.D -11 1 -.names N_43_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_120_i.BLIF N_121_i.BLIF inst_DSACK1_INT.D -11 1 -.names N_118_i.BLIF N_119_i.BLIF inst_AS_000_INT.D -11 1 -.names N_46_0.BLIF inst_AMIGA_DS.D -0 1 -.names N_274.BLIF inst_AS_030_D0.D -0 1 -.names N_48_0.BLIF inst_DTACK_D0.D -0 1 -.names N_52_0.BLIF inst_VPA_D.D -0 1 -.names N_53_0.BLIF inst_RESET_OUT.D -0 1 -.names N_8.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_30_0.BLIF BG_000DFFreg.D -0 1 -.names N_31_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_32_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names N_33_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_34_0.BLIF inst_A0_DMA.D -0 1 -.names N_35_0.BLIF inst_RW_000_DMA.D -0 1 -.names N_36_0.BLIF inst_VMA_INTreg.D -0 1 -.names N_38_0.BLIF inst_RW_000_INT.D -0 1 -.names N_39_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names N_40_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_41_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names N_42_0.BLIF inst_AS_000_DMA.D -0 1 -.names un1_rst_2_1.BLIF inst_BGACK_030_INT_D.D +.names N_220_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_125.BLIF N_125_i -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_124.BLIF N_124_i -0 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_124_i.BLIF N_125_i.BLIF N_53_0 +.names N_20_i.BLIF RST_c.BLIF N_23_0 11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n +.names N_19.BLIF N_19_i 0 1 -.names N_134.BLIF N_134_i -0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names N_134_i.BLIF RST_c.BLIF N_270_0 +.names N_19_i.BLIF RST_c.BLIF N_22_0 11 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n +.names N_18.BLIF N_18_i 0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_77_i +.names N_18_i.BLIF RST_c.BLIF N_21_0 11 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i +.names ipl_c_2__n.BLIF ipl_c_i_2__n 0 1 -.names N_76_i.BLIF SM_AMIGA_1_.BLIF N_87_i +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 11 1 -.names N_137.BLIF N_137_i_0 -0 1 -.names N_112.BLIF N_112_i +.names ipl_c_1__n.BLIF ipl_c_i_1__n 0 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +11 1 .names vcc_n_n 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i +.names ipl_c_0__n.BLIF ipl_c_i_0__n 0 1 -.names N_113.BLIF N_113_i -0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_114.BLIF N_114_i +.names un5_e_0.BLIF un5_e 0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 +11 1 .names gnd_n_n -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +.names DTACK_c.BLIF DTACK_c_i 0 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_109.BLIF N_109_i -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un7_as_030 +.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_108.BLIF N_108_i -0 1 -.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT -0 1 -.names CLK_030_PE_1_.BLIF clk_030_pe_i_1__n -0 1 -.names N_111.BLIF N_111_i +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 +11 1 +.names VPA_c.BLIF VPA_c_i 0 1 .names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names DS_000_DMA_0_sqmuxa.BLIF DS_000_DMA_0_sqmuxa_i -0 1 -.names N_111_i.BLIF RST_c.BLIF N_265_2_0 +.names RST_c.BLIF VPA_c_i.BLIF N_44_0 11 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names pos_clk_un4_rw_000_n.BLIF pos_clk_un4_rw_000_i_n +.names N_13.BLIF N_13_i 0 1 +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa +0 1 +.names N_13_i.BLIF RST_c.BLIF N_27_0 +11 1 .names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin 11 1 -.names AS_000_c.BLIF AS_000_i +.names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +.names un21_fpu_cs_1.BLIF N_282_0.BLIF un21_fpu_cs 11 1 -.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names inst_AMIGA_DS.BLIF AMIGA_DS_i -0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +.names un21_berr_1_0.BLIF N_282_0.BLIF un21_berr 11 1 -.names pos_clk_un3_clk_out_int_n.BLIF pos_clk_un3_clk_out_int_i_n +.names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_52_0 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF un13_ciin +.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_96_0_1 11 1 -.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_48_0 +.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_96_0_2 11 1 -.names pos_clk_as_000_dma6_n.BLIF pos_clk_as_000_dma6_i_n -0 1 -.names N_276.BLIF RESET_c.BLIF un3_ahigh_i +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_282_0_1 11 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names pos_clk_un4_bgack_000_n.BLIF pos_clk_un4_bgack_000_i_n -0 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP_i -0 1 -.names BGACK_000_c.BLIF pos_clk_un4_bgack_000_i_n.BLIF \ -pos_clk_un6_bgack_000_0_n +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_282_0_2 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_7.BLIF N_7_i -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_7_i.BLIF RST_c.BLIF N_41_0 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_282_0_3 11 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names RW_000_i.BLIF pos_clk_un15_bgack_030_int_i_n.BLIF \ -pos_clk_un1_bgack_030_int_0_n -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names CLK_030_PE_0_.BLIF CLK_030_PE_1_.BLIF pos_clk_un12_clk_out_int_0_n -11 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un3_0_n -11 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un15_bgack_030_int_i_n -11 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_3.BLIF N_3_i -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names N_3_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names N_4.BLIF N_4_i -0 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names N_4_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names un6_amiga_bus_data_dir.BLIF un6_amiga_bus_data_dir_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names un12_amiga_bus_data_dir_m.BLIF un12_amiga_bus_data_dir_m_i -0 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names un6_amiga_bus_data_dir_i.BLIF un12_amiga_bus_data_dir_m_i.BLIF \ -AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names N_22.BLIF N_22_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_22_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names N_21.BLIF N_21_i -0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_21_i.BLIF RST_c.BLIF N_32_0 -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_19.BLIF N_19_i -0 1 -.names G_122.BLIF N_224_i -0 1 -.names N_19_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names G_123.BLIF N_225_i -0 1 -.names N_18.BLIF N_18_i -0 1 -.names G_124.BLIF N_226_i -0 1 -.names N_18_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -pos_clk_un5_bgack_030_int_d_i_n -11 1 -.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF \ -pos_clk_amiga_bus_enable_dma_high_3_0_n -11 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF \ -pos_clk_amiga_bus_enable_dma_low_3_0_n -11 1 -.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n -11 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF pos_clk_rw_000_dma_3_0_n -11 1 -.names un13_ciin.BLIF un13_ciin_i -0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names N_123.BLIF N_123_i -0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_86_i -11 1 -.names N_122.BLIF N_122_i -0 1 -.names N_129.BLIF N_129_i -0 1 -.names un7_as_030.BLIF un7_as_030_i -0 1 -.names N_130.BLIF N_130_i -0 1 -.names N_129_i.BLIF N_130_i.BLIF un11_amiga_bus_enable_high_i -11 1 -.names N_117.BLIF N_117_i -0 1 -.names N_117_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names N_107.BLIF N_107_i -0 1 -.names N_107_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_106.BLIF N_106_i -0 1 -.names N_106_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names N_16.BLIF N_16_i -0 1 -.names N_254.BLIF N_254_i -0 1 -.names N_263.BLIF N_263_i -0 1 -.names N_250_i_1.BLIF N_263_i.BLIF N_250_i -11 1 -.names N_256.BLIF N_256_i -0 1 -.names N_189_i_1.BLIF N_263_i.BLIF N_189_i -11 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_101.BLIF N_101_i -0 1 -.names N_103.BLIF N_103_i -0 1 -.names N_104.BLIF N_104_i -0 1 -.names N_105.BLIF N_105_i -0 1 -.names N_115.BLIF N_115_i -0 1 -.names N_116.BLIF N_116_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names N_277.BLIF N_277_i -0 1 -.names N_131_i.BLIF N_277_i.BLIF N_64_0 -11 1 -.names N_91_0_3.BLIF nEXP_SPACE_c.BLIF N_91_0 -11 1 -.names N_104_i.BLIF SM_AMIGA_i_7_.BLIF N_159_0 -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_14 -1- 1 --1 1 -.names N_85_i_1.BLIF N_85_i_2.BLIF N_85_i -11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_15 -1- 1 --1 1 -.names N_79.BLIF N_159_0.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_24 -1- 1 --1 1 -.names RW_c.BLIF RW_c_i -0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_25 -1- 1 --1 1 -.names N_159_0.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n -11 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_3__n -0 1 -.names N_25.BLIF N_25_i -0 1 -.names N_25_i.BLIF RST_c.BLIF N_28_0 -11 1 -.names N_24.BLIF N_24_i -0 1 -.names N_24_i.BLIF RST_c.BLIF N_27_0 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_50_0 -11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_49_0 -11 1 -.names N_14.BLIF N_14_i -0 1 -.names N_14_i.BLIF RST_c.BLIF N_39_0 -11 1 -.names N_15.BLIF N_15_i -0 1 -.names N_15_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names inst_BGACK_030_INT_D.BLIF inst_BGACK_030_INTreg.BLIF N_91_0_1 -11 1 -.names AS_030_D0_i.BLIF sm_amiga_i_i_7__n.BLIF N_91_0_2 -11 1 -.names N_91_0_1.BLIF N_91_0_2.BLIF N_91_0_3 -11 1 -.names N_108_i.BLIF N_109_i.BLIF N_265_i_1 -11 1 -.names N_112_i.BLIF RST_c.BLIF N_266_i_1 -11 1 -.names N_113_i.BLIF N_114_i.BLIF N_266_i_2 -11 1 -.names N_164_i.BLIF N_264.BLIF N_138_i_1 -11 1 -.names N_79.BLIF N_170_i.BLIF N_148_i_1 -11 1 -.names N_78.BLIF N_168_i.BLIF N_144_i_1 -11 1 -.names N_166_i.BLIF N_167_i.BLIF N_142_i_1 -11 1 -.names N_165_i.BLIF N_264_i.BLIF N_140_i_1 +.names N_282_0_1.BLIF N_282_0_2.BLIF N_282_0_4 11 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names N_76_i.BLIF N_76 -0 1 -.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF N_85_i_1 -11 1 -.names CLK_000_D_4_.BLIF clk_000_d_i_3__n.BLIF N_85_i_2 -11 1 -.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_277_1 -11 1 -.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_277_2 -11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF un1_rst_2_1 -11 1 -.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_277_3 -11 1 -.names N_277_1.BLIF N_277_2.BLIF N_277_4 -11 1 -.names N_64_0.BLIF N_64 -0 1 -.names N_277_3.BLIF fc_c_0__n.BLIF N_277_5 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_122 -11 1 .names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_123 -11 1 .names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names N_276.BLIF inst_RESET_OUT.BLIF N_132 -11 1 .names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_133 -11 1 .names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_274 -11 1 .names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_276 -11 1 .names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names N_77_i.BLIF N_77 -0 1 .names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 11 1 -.names N_79_i.BLIF N_79 -0 1 .names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 11 1 -.names N_78_i.BLIF N_78 -0 1 .names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_263 -11 1 .names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 11 1 -.names N_108_1.BLIF rst_dly_i_2__n.BLIF N_108 -11 1 .names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names N_114_1.BLIF rst_dly_i_1__n.BLIF N_114 +.names N_80_i.BLIF N_82_i.BLIF N_201_1 11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF un6_amiga_bus_data_dir_1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_201_2 11 1 -.names N_85_i.BLIF N_85 +.names BERR_c.BLIF N_201_i.BLIF N_131_i_1 +11 1 +.names N_68_i.BLIF N_131.BLIF N_134_0_1 +11 1 +.names N_68.BLIF N_141_i.BLIF N_113_i_1 +11 1 +.names N_142_i.BLIF RST_c.BLIF N_113_i_2 +11 1 +.names N_68_i.BLIF N_208.BLIF N_144_1 +11 1 +.names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n +11 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_144_2 +11 1 +.names N_72_i.BLIF N_82_i.BLIF N_143_1 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_143_2 +11 1 +.names AS_030_D1_i.BLIF inst_BGACK_030_INT_D.BLIF N_163_1 +11 1 +.names N_282.BLIF sm_amiga_i_i_7__n.BLIF N_163_2 +11 1 +.names N_163_1.BLIF N_163_2.BLIF N_163_3 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +11 1 +.names AS_000_i.BLIF N_220_i.BLIF pos_clk_cycle_dma_5_1_1__n +11 1 +.names N_68_i.BLIF CYCLE_DMA_0_.BLIF N_199_1 +11 1 +.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 +11 1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_140_1 +11 1 +.names AS_000_i.BLIF N_198_i.BLIF N_66_i_1 +11 1 +.names N_199_i.BLIF N_220_i.BLIF N_66_i_2 +11 1 +.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_205_i_1 +11 1 +.names N_140_i.BLIF pos_clk_un2_n.BLIF N_205_i_2 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_1 +11 1 +.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_180_2 +11 1 +.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF un6_amiga_bus_data_dir_2 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_59_i_1 11 1 -.names N_78_i.BLIF SM_AMIGA_0_.BLIF N_104 +.names N_267_i.BLIF N_268_i.BLIF N_127_i_1 11 1 -.names AMIGA_DS_i.BLIF AS_000_i.BLIF pos_clk_as_000_dma6_1_n +.names N_93.BLIF N_266_i.BLIF N_123_i_1 11 1 -.names N_91_0.BLIF N_91 -0 1 -.names pos_clk_un1_bgack_030_int_n.BLIF pos_clk_un3_n.BLIF \ -pos_clk_as_000_dma6_2_n +.names N_68.BLIF N_186_i.BLIF N_121_i_1 11 1 -.names AS_030_i.BLIF N_91.BLIF N_131 +.names N_72.BLIF N_185_i.BLIF N_119_i_1 11 1 -.names DS_000_DMA_0_sqmuxa_i.BLIF pos_clk_as_000_dma6_n.BLIF \ -DS_000_DMA_1_sqmuxa_1 -11 1 -.names N_277_4.BLIF N_277_5.BLIF N_277 -11 1 -.names CLK_030_PE_0_.BLIF clk_030_pe_i_1__n.BLIF pos_clk_un4_rw_000_1_n -11 1 -.names N_130_1.BLIF AS_030_i.BLIF N_130 -11 1 -.names CLK_030_c.BLIF RW_000_i.BLIF pos_clk_un4_rw_000_2_n -11 1 -.names N_270.BLIF RST_DLY_0_.BLIF N_115 -11 1 -.names pos_clk_un12_clk_out_int_n.BLIF AS_000_DMA_i.BLIF \ -pos_clk_un13_clk_out_int_1_n -11 1 -.names N_116_1.BLIF RST_c.BLIF N_116 -11 1 -.names N_76_i.BLIF N_137.BLIF N_125_1 -11 1 -.names N_79.BLIF sm_amiga_i_5__n.BLIF N_105 -11 1 -.names N_76.BLIF rst_dly_i_0__n.BLIF N_116_1 -11 1 -.names N_85.BLIF sm_amiga_i_i_7__n.BLIF N_103 -11 1 -.names cpu_est_i_2__n.BLIF VMA_INT_i.BLIF pos_clk_un29_clk_000_ne_1_1_n -11 1 -.names N_87.BLIF sm_amiga_i_0__n.BLIF N_101 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF pos_clk_un29_clk_000_ne_1_2_n -11 1 -.names N_259_1.BLIF cpu_est_i_3__n.BLIF N_259 -11 1 -.names pos_clk_un29_clk_000_ne_1_1_n.BLIF pos_clk_un29_clk_000_ne_1_2_n.BLIF \ -pos_clk_un29_clk_000_ne_1_3_n -11 1 -.names N_251.BLIF cpu_est_2_.BLIF N_255 -11 1 -.names N_78_i.BLIF N_263.BLIF N_261_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_2__n.BLIF N_256 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_261_2 -11 1 -.names N_252.BLIF cpu_est_2_.BLIF N_254 -11 1 -.names N_76_i.BLIF N_251_i.BLIF N_262_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_2__n.BLIF N_16 -11 1 -.names N_263.BLIF VPA_D_i.BLIF N_262_2 -11 1 -.names BGACK_030_INT_i.BLIF N_86_i.BLIF N_106 -11 1 -.names N_78_i.BLIF RW_c.BLIF DS_000_ENABLE_0_sqmuxa_1_1 -11 1 -.names N_86_i.BLIF N_86 -0 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_259_1 -11 1 -.names BGACK_030_INT_i.BLIF N_86.BLIF N_107 -11 1 -.names N_16_i.BLIF N_254_i.BLIF N_250_i_1 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_117 -11 1 -.names N_255_i.BLIF N_256_i.BLIF N_189_i_1 -11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_129 -11 1 -.names N_77.BLIF N_228_i.BLIF N_108_1 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n -0 1 -.names N_228_i.BLIF rst_dly_i_0__n.BLIF N_114_1 -11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n -0 1 -.names N_277.BLIF BGACK_000_c.BLIF un21_berr_1 -11 1 -.names pos_clk_rw_000_dma_3_0_n.BLIF pos_clk_rw_000_dma_3_n -0 1 -.names N_277.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 -11 1 -.names pos_clk_amiga_bus_enable_dma_low_3_0_n.BLIF \ -pos_clk_amiga_bus_enable_dma_low_3_n -0 1 -.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_130_1 -11 1 -.names pos_clk_amiga_bus_enable_dma_high_3_0_n.BLIF \ -pos_clk_amiga_bus_enable_dma_high_3_n -0 1 -.names N_78.BLIF N_101_i.BLIF N_136_i_1 -11 1 -.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF SIZE_DMA_3_sqmuxa -11 1 -.names N_103_i.BLIF N_104_i.BLIF N_152_i_1 -11 1 -.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n -0 1 -.names N_76.BLIF N_105_i.BLIF N_146_i_1 -11 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_18 +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_115_i.BLIF N_116_i.BLIF N_267_i_1 +.names N_183_i.BLIF N_184_i.BLIF N_117_i_1 11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_19 +.names N_72.BLIF N_182_i.BLIF N_115_i_1 +11 1 +.names N_72.BLIF N_181_i.BLIF N_111_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_165_1 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_162_1 11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_21 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_148_1 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_18 1- 1 -1 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_19 +1- 1 +-1 1 +.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n 0 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_22 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_20 1- 1 -1 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +.names inst_DS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 -.names un6_amiga_bus_data_dir_1.BLIF un6_amiga_bus_data_dir_2.BLIF \ -un6_amiga_bus_data_dir +.names N_205.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF un12_amiga_bus_data_dir_m +.names N_205.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 .names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF pos_clk_un3_clk_out_int_n -11 1 .names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 .names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names pos_clk_as_000_dma6_1_n.BLIF pos_clk_as_000_dma6_2_n.BLIF \ -pos_clk_as_000_dma6_n +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 .names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names DS_000_DMA_1_sqmuxa_1.BLIF pos_clk_un4_rw_000_i_n.BLIF \ -DS_000_DMA_1_sqmuxa -11 1 .names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 -1- 1 --1 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names pos_clk_as_000_dma6_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ -AS_000_DMA_1_sqmuxa -11 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF ds_000_enable_0_un3_n +.names RST_c.BLIF as_030_d1_0_un3_n 0 1 -.names AS_000_i.BLIF un1_rst_2_1.BLIF un1_rst_2 +.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n 11 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa.BLIF \ -ds_000_enable_0_un1_n +.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n 11 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF ds_000_enable_0_un3_n.BLIF \ -ds_000_enable_0_un0_n -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un13_bgack_030_int_n.BLIF N_199 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names N_76_i.BLIF pos_clk_un15_bgack_030_int_n.BLIF \ -pos_clk_un13_bgack_030_int_n +.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ +rw_000_int_0_un1_n 11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names CLK_030_PE_0_.BLIF pos_clk_un13_clk_out_int_n.BLIF N_205 -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names pos_clk_un13_clk_out_int_1_n.BLIF pos_clk_un3_clk_out_int_n.BLIF \ -pos_clk_un13_clk_out_int_n -11 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +.names N_244.BLIF as_030_000_sync_0_un3_n 0 1 -.names pos_clk_un15_bgack_030_int_i_n.BLIF pos_clk_un15_bgack_030_int_n -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +.names AS_030_c.BLIF N_244.BLIF as_030_000_sync_0_un1_n 11 1 -.names pos_clk_un3_0_n.BLIF pos_clk_un3_n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names pos_clk_un12_clk_out_int_0_n.BLIF pos_clk_un12_clk_out_int_n -0 1 -.names N_76.BLIF cpu_est_0_1__un3_n -0 1 -.names pos_clk_un1_bgack_030_int_0_n.BLIF pos_clk_un1_bgack_030_int_n -0 1 -.names cpu_est_1_.BLIF N_76.BLIF cpu_est_0_1__un1_n -11 1 -.names RW_000_c.BLIF pos_clk_un3_clk_out_int_i_n.BLIF DS_000_DMA_0_sqmuxa -11 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names RST_c.BLIF pos_clk_as_000_dma6_n.BLIF un1_rst_3 -11 1 -.names N_76.BLIF cpu_est_0_2__un3_n -0 1 -.names cpu_est_2_.BLIF N_76.BLIF cpu_est_0_2__un1_n -11 1 -.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names N_76.BLIF cpu_est_0_3__un3_n -0 1 -.names pos_clk_un4_rw_000_1_n.BLIF pos_clk_un4_rw_000_2_n.BLIF \ -pos_clk_un4_rw_000_n -11 1 -.names cpu_est_3_.BLIF N_76.BLIF cpu_est_0_3__un1_n -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_7 -1- 1 --1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_189_i.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names inst_VPA_D.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un3_n -0 1 -.names AS_000_c.BLIF N_76_i.BLIF pos_clk_un4_bgack_000_n -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un1_n -11 1 -.names N_265_2_0.BLIF N_265_2 -0 1 -.names pos_clk_un29_clk_000_ne_1_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un3_n.BLIF pos_clk_un31_clk_000_ne_1_i_m2_un0_n -11 1 -.names N_76.BLIF rst_dly_i_2__n.BLIF N_111 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n 11 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names N_137.BLIF N_265_2.BLIF N_109 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names N_76.BLIF rst_dly_i_1__n.BLIF N_113 -11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names N_77_i.BLIF N_134.BLIF N_112 -11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n -11 1 -.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 -.names pos_clk_un31_clk_000_ne_1_i_m2_un1_n.BLIF \ -pos_clk_un31_clk_000_ne_1_i_m2_un0_n.BLIF N_98 -1- 1 --1 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n -11 1 -.names pos_clk_un29_clk_000_ne_1_3_n.BLIF cpu_est_i_1__n.BLIF \ -pos_clk_un29_clk_000_ne_1_n -11 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 -11 1 -.names pos_clk_as_000_dma6_i_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names N_87_i.BLIF N_87 -0 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n -0 1 -.names N_270_0.BLIF N_270 -0 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n -11 1 -.names N_76_i.BLIF N_137_i_0.BLIF N_134 -11 1 -.names N_23.BLIF N_23_i -0 1 -.names pos_clk_as_000_dma6_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names N_125_1.BLIF RST_c.BLIF N_125 -11 1 -.names N_23_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un3_n -0 1 -.names inst_RESET_OUT.BLIF RST_c.BLIF N_124 -11 1 -.names N_20.BLIF N_20_i -0 1 -.names SIZE_DMA_1_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_1__un1_n -11 1 -.names N_87_i.BLIF RST_c.BLIF N_121 -11 1 -.names N_20_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \ -size_dma_0_1__un0_n -11 1 -.names DSACK1_INT_i.BLIF N_274.BLIF N_120 -11 1 -.names N_13.BLIF N_13_i -0 1 -.names SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un3_n -0 1 -.names N_77_i.BLIF RST_DLY_2_.BLIF N_137 -11 1 -.names N_13_i.BLIF RST_c.BLIF N_40_0 -11 1 -.names SIZE_DMA_0_.BLIF SIZE_DMA_3_sqmuxa.BLIF size_dma_0_0__un1_n -11 1 -.names pos_clk_un31_clk_000_ne_i_n.BLIF pos_clk_un31_clk_000_ne_n -0 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \ -size_dma_0_0__un0_n -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n -0 1 -.names N_26.BLIF N_26_i -0 1 -.names pos_clk_amiga_bus_enable_dma_high_3_n.BLIF \ -pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names N_26_i.BLIF RST_c.BLIF N_29_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names a_c_0__n.BLIF a_c_i_0__n +.names N_68.BLIF cpu_est_0_1__un3_n 0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +.names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n 0 1 -.names N_261_1.BLIF N_261_2.BLIF N_261 +.names cpu_est_1_.BLIF N_68.BLIF cpu_est_0_1__un1_n 11 1 -.names size_c_1__n.BLIF size_c_i_1__n +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names N_68.BLIF cpu_est_0_2__un3_n 0 1 -.names pos_clk_amiga_bus_enable_dma_low_3_n.BLIF \ -pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n +.names cpu_est_2_.BLIF N_68.BLIF cpu_est_0_2__un1_n 11 1 -.names N_262_1.BLIF N_262_2.BLIF N_262 -11 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names N_251_i.BLIF N_251 +.names N_60_0.BLIF N_60 0 1 -.names DS_000_ENABLE_0_sqmuxa_1.BLIF DS_000_ENABLE_0_sqmuxa_1_i +.names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_63_0.BLIF N_63 0 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +.names N_68.BLIF cpu_est_0_3__un3_n 0 1 -.names N_252_0.BLIF N_252 -0 1 -.names DS_000_ENABLE_0_sqmuxa_1_i.BLIF N_157.BLIF un1_DS_000_ENABLE_0_sqmuxa_i +.names N_220_i.BLIF RW_000_i.BLIF N_126 11 1 -.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -a0_dma_0_un1_n +.names cpu_est_3_.BLIF N_68.BLIF cpu_est_0_3__un1_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_258 +.names a_c_1__n.BLIF N_220_i.BLIF N_150 11 1 -.names N_78_i.BLIF SM_AMIGA_4_.BLIF N_157_i +.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +.names a_i_1__n.BLIF N_220_i.BLIF N_151 11 1 -.names N_251_i.BLIF cpu_est_i_2__n.BLIF N_257 -11 1 -.names N_76_i.BLIF SM_AMIGA_5_.BLIF N_160_0 -11 1 -.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_i.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names SM_AMIGA_3_.BLIF pos_clk_un31_clk_000_ne_n.BLIF N_161_0 -11 1 -.names pos_clk_rw_000_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ -rw_000_dma_0_un1_n -11 1 -.names un1_DS_000_ENABLE_0_sqmuxa_i.BLIF un1_DS_000_ENABLE_0_sqmuxa -0 1 -.names N_85_i.BLIF sm_amiga_i_i_7__n.BLIF N_162_0 -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names N_76.BLIF sm_amiga_i_2__n.BLIF N_102 -11 1 -.names N_165.BLIF N_165_i -0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n 0 1 -.names AS_000_INT_i.BLIF N_274.BLIF N_118 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_219 11 1 .names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n 11 1 -.names N_79_i.BLIF RST_c.BLIF N_119 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_175 11 1 -.names N_167.BLIF N_167_i -0 1 .names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names N_264_i.BLIF N_264 -0 1 -.names N_166.BLIF N_166_i -0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n 0 1 -.names DS_000_ENABLE_0_sqmuxa_1_1.BLIF SM_AMIGA_6_.BLIF \ -DS_000_ENABLE_0_sqmuxa_1 -11 1 +.names N_59_i.BLIF N_59 +0 1 .names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n 11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_164 -11 1 -.names N_168.BLIF N_168_i +.names N_68_i.BLIF N_68 0 1 .names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names N_162.BLIF sm_amiga_i_6__n.BLIF N_170 -11 1 -.names N_64.BLIF as_030_000_sync_0_un3_n +.names N_72_i.BLIF N_72 0 1 -.names N_160.BLIF sm_amiga_i_4__n.BLIF N_168 -11 1 -.names N_170.BLIF N_170_i +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n 0 1 -.names inst_AS_030_000_SYNC.BLIF N_64.BLIF as_030_000_sync_0_un1_n +.names N_80_i.BLIF N_80 +0 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 -.names N_157.BLIF sm_amiga_i_3__n.BLIF N_166 +.names N_93_i.BLIF N_93 +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +.names N_98_i.BLIF N_98 +0 1 +.names N_63.BLIF ds_000_enable_0_un3_n +0 1 +.names N_107_i.BLIF N_107 +0 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_63.BLIF ds_000_enable_0_un1_n 11 1 -.names N_76_i.BLIF pos_clk_un31_clk_000_ne_n.BLIF N_167 +.names N_128_i.BLIF N_128 +0 1 +.names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ +ds_000_enable_0_un0_n 11 1 +.names N_131_i.BLIF N_131 +0 1 +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names N_134_0.BLIF N_134 +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_135_0.BLIF N_135 +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_72.BLIF SM_AMIGA_2_.BLIF N_141 +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_142 +11 1 +.names N_143_1.BLIF N_143_2.BLIF N_143 +11 1 +.names N_144_1.BLIF N_144_2.BLIF N_144 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_145 +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_146 +11 1 +.names N_205_i_1.BLIF N_205_i_2.BLIF N_205_i +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_147 +11 1 +.names N_140.BLIF N_140_i +0 1 +.names N_148_1.BLIF cpu_est_i_3__n.BLIF N_148 +11 1 +.names inst_AMIGA_DS.BLIF AMIGA_DS_i +0 1 +.names N_98.BLIF cpu_est_2_.BLIF N_149 +11 1 +.names N_98_i.BLIF cpu_est_2_.BLIF N_154 +11 1 +.names N_199.BLIF N_199_i +0 1 +.names N_82_i.BLIF cpu_est_3_.BLIF N_155 +11 1 +.names N_198.BLIF N_198_i +0 1 +.names N_162_1.BLIF cpu_est_i_3__n.BLIF N_162 +11 1 +.names N_180.BLIF N_180_i +0 1 +.names N_165_1.BLIF AS_030_i.BLIF N_165 +11 1 +.names N_262.BLIF N_262_i +0 1 +.names BGACK_030_INT_i.BLIF N_128.BLIF N_259 +11 1 +.names N_180_i.BLIF N_262_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names BGACK_030_INT_i.BLIF N_128_i.BLIF N_260 +11 1 +.names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un2_i_n +11 1 +.names N_129.BLIF sm_amiga_i_0__n.BLIF N_181 +11 1 +.names N_3.BLIF N_3_i +0 1 +.names N_134.BLIF sm_amiga_i_2__n.BLIF N_182 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_32_0 +11 1 +.names N_68_i.BLIF N_131.BLIF N_183 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names N_107.BLIF sm_amiga_i_3__n.BLIF N_184 +11 1 +.names N_4_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names N_135.BLIF sm_amiga_i_4__n.BLIF N_185 +11 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_220_i +11 1 +.names N_93.BLIF sm_amiga_i_5__n.BLIF N_186 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_132.BLIF sm_amiga_i_6__n.BLIF N_266 +11 1 +.names BG_030_c_i.BLIF N_59.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names N_96.BLIF sm_amiga_i_i_7__n.BLIF N_267 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names N_72_i.BLIF SM_AMIGA_0_.BLIF N_268 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_24_0 +11 1 +.names N_68.BLIF cpu_est_i_0__n.BLIF N_190 +11 1 +.names N_16.BLIF N_16_i +0 1 +.names N_68_i.BLIF cpu_est_0_.BLIF N_191 +11 1 +.names N_16_i.BLIF RST_c.BLIF N_25_0 +11 1 +.names N_201_1.BLIF N_201_2.BLIF N_201 +11 1 +.names N_15.BLIF N_15_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_202 +11 1 +.names N_15_i.BLIF RST_c.BLIF N_26_0 +11 1 +.names N_93_i.BLIF RW_c.BLIF N_203 +11 1 +.names N_12.BLIF N_12_i +0 1 +.names N_98_i.BLIF cpu_est_i_2__n.BLIF N_208 +11 1 +.names N_12_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names N_163_3.BLIF un1_dsack1_i.BLIF N_163 +11 1 +.names N_11.BLIF N_11_i +0 1 +.names N_282_0.BLIF N_282 +0 1 +.names N_11_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 +.names N_5.BLIF N_5_i +0 1 +.names N_132_0.BLIF N_132 +0 1 +.names N_5_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names N_96_0.BLIF N_96 +0 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names N_129_i.BLIF N_129 +0 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names N_175.BLIF RST_c.BLIF N_169 +11 1 +.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i +11 1 +.names N_93_i.BLIF RST_c.BLIF N_170 +11 1 +.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_69_i +11 1 +.names N_219.BLIF RST_c.BLIF N_167 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names N_129_i.BLIF RST_c.BLIF N_168 +11 1 +.names AS_030_i.BLIF N_163_i.BLIF N_244_0 +11 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 .names N_164.BLIF N_164_i 0 1 -.names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names N_161.BLIF sm_amiga_i_2__n.BLIF N_165 -11 1 -.names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ -rw_000_int_0_un1_n -11 1 -.names N_162_0.BLIF N_162 +.names N_165.BLIF N_165_i 0 1 -.names N_102.BLIF N_102_i -0 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +.names AS_000_c.BLIF N_68_i.BLIF N_274 11 1 -.names N_161_0.BLIF N_161 -0 1 -.names N_78.BLIF N_102_i.BLIF N_264_i +.names N_164_i.BLIF N_165_i.BLIF un11_amiga_bus_enable_high_i 11 1 -.names N_160_0.BLIF N_160 -0 1 -.names N_78_i.BLIF SM_AMIGA_6_.BLIF N_79_i +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_164 11 1 -.names N_157_i.BLIF N_157 +.names un10_ciin.BLIF un10_ciin_i 0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_78_i +.names N_244_0.BLIF N_244 +0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_60_0 11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_26 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 1- 1 -1 1 -.names N_119.BLIF N_119_i +.names N_274.BLIF N_274_i 0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 1- 1 -1 1 -.names N_118.BLIF N_118_i +.names BGACK_000_c.BLIF N_274_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_12 +1- 1 +-1 1 +.names RW_c.BLIF RW_c_i 0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_20 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_15 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_23 +.names N_246_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_16 1- 1 -1 1 -.names N_255.BLIF N_255_i +.names N_168.BLIF N_168_i 0 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_8 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_257.BLIF N_257_i +.names N_167.BLIF N_167_i 0 1 .names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names N_255_i.BLIF N_257_i.BLIF cpu_est_2_0_2__n +.names N_170.BLIF N_170_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names N_169.BLIF N_169_i +0 1 +.names N_205_i.BLIF N_205 +0 1 +.names AS_000_DMA_1_sqmuxa_1.BLIF N_205_i.BLIF AS_000_DMA_1_sqmuxa +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 +1- 1 +-1 1 +.names N_93.BLIF N_246_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names N_199_1.BLIF cycle_dma_i_1__n.BLIF N_199 +11 1 +.names N_282_0_4.BLIF N_282_0_3.BLIF N_282_0 +11 1 +.names pos_clk_un2_i_n.BLIF pos_clk_un2_n +0 1 +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +0 1 +.names N_140_1.BLIF RW_000_i.BLIF N_140 +11 1 +.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0 +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_262 +11 1 +.names N_68_i.BLIF SM_AMIGA_1_.BLIF N_129_i +11 1 +.names cycle_dma_i_0__n.BLIF N_68.BLIF N_198 +11 1 +.names N_268.BLIF N_268_i +0 1 +.names N_180_1.BLIF N_180_2.BLIF N_180 +11 1 +.names N_268_i.BLIF SM_AMIGA_i_7_.BLIF N_246_i 11 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names N_258.BLIF N_258_i -0 1 +.names N_96_0.BLIF sm_amiga_i_i_7__n.BLIF N_132_0 +11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names N_259.BLIF N_259_i +.names AS_000_c.BLIF AS_000_i 0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names N_142.BLIF N_142_i 0 1 -.names N_258_i.BLIF N_259_i.BLIF cpu_est_2_0_1__n +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_141.BLIF N_141_i +0 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_68_i.BLIF SM_AMIGA_5_.BLIF N_135_0 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 -.names N_262.BLIF N_262_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_261.BLIF N_261_i -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names N_261_i.BLIF N_262_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names N_134_0_1.BLIF SM_AMIGA_3_.BLIF N_134_0 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +.names RW_000_c.BLIF RW_000_i 0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_251_i +.names N_131_i_1.BLIF N_202_i.BLIF N_131_i +11 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP_i +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_128_i +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names N_72_i.BLIF SM_AMIGA_4_.BLIF N_107_i +11 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names N_203.BLIF N_203_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_107.BLIF N_203_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_201.BLIF N_201_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_202.BLIF N_202_i +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_98_i +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_72_i.BLIF SM_AMIGA_6_.BLIF N_93_i 11 1 .names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_3__n.BLIF N_252_0 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i 11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_76_i +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_80_i 11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_17.BLIF N_17_i -0 1 .names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n 0 1 -.names N_17_i.BLIF RST_c.BLIF N_36_0 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_72_i 11 1 .names AS_030_c.BLIF AS_030_i 0 1 -.names N_98.BLIF N_98_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names BERR_c.BLIF N_98_i.BLIF pos_clk_un31_clk_000_ne_i_n +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_68_i 11 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_59_i_1.BLIF nEXP_SPACE_c.BLIF N_59_i +11 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names N_190.BLIF N_190_i +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_191.BLIF N_191_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names inst_AS_030_D1.BLIF AS_030_D1_i +0 1 +.names N_267.BLIF N_267_i +0 1 .names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names N_137_i_0.BLIF RST_c.BLIF N_228_i -11 1 .names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 -.names N_121.BLIF N_121_i +.names N_266.BLIF N_266_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names N_186.BLIF N_186_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names N_120.BLIF N_120_i +.names N_185.BLIF N_185_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names N_183.BLIF N_183_i +0 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_184.BLIF N_184_i +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_182.BLIF N_182_i +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_181.BLIF N_181_i +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names N_260.BLIF N_260_i +0 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names N_260_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_259.BLIF N_259_i +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_259_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_63_0 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names N_155.BLIF N_155_i +0 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_162.BLIF N_162_i +0 1 +.names G_105.BLIF N_187_i +0 1 +.names N_155_i.BLIF N_162_i.BLIF un5_e_0 +11 1 +.names G_106.BLIF N_188_i +0 1 +.names N_154.BLIF N_154_i +0 1 +.names G_107.BLIF N_189_i +0 1 +.names N_80.BLIF N_154_i.BLIF cpu_est_2_0_3__n +11 1 +.names N_149.BLIF N_149_i +0 1 +.names N_208.BLIF N_208_i +0 1 +.names N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n +11 1 +.names N_147.BLIF N_147_i +0 1 +.names un2_ds_030.BLIF un2_ds_030_i +0 1 +.names N_148.BLIF N_148_i +0 1 +.names N_219.BLIF N_219_i +0 1 +.names N_147_i.BLIF N_148_i.BLIF cpu_est_2_0_1__n +11 1 +.names N_175.BLIF N_175_i +0 1 +.names N_146.BLIF N_146_i +0 1 +.names un3_as_030.BLIF un3_as_030_i +0 1 +.names N_146_i.BLIF RST_c.BLIF N_36_0 +11 1 +.names N_145.BLIF N_145_i +0 1 +.names N_145_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names N_143.BLIF N_143_i +0 1 +.names N_144.BLIF N_144_i +0 1 +.names N_143_i.BLIF N_144_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names N_20.BLIF N_20_i 0 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 -.names un6_ds_030_i.BLIF DS_030 +.names un2_ds_030_i.BLIF DS_030 1 1 0 0 .names BG_000DFFreg.BLIF BG_000 @@ -1598,13 +1262,13 @@ rw_000_int_0_un1_n .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names N_123_i.BLIF DSACK1 +.names N_219_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_250_i.BLIF E +.names un5_e.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1631,15 +1295,6 @@ rw_000_int_0_un1_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1655,12 +1310,6 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -1679,10 +1328,13 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_000.BLIF CLK_000_D_0_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 .names CLK_000_D_0_.BLIF CLK_000_D_1_.D @@ -1709,37 +1361,67 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_030_PE_0_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_030_PE_1_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C +.names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C @@ -1754,55 +1436,22 @@ rw_000_int_0_un1_n .names CLK_OSZI_c.BLIF inst_AMIGA_DS.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF inst_AS_030_D1.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C @@ -1829,10 +1478,10 @@ rw_000_int_0_un1_n .names gnd_n_n.BLIF AHIGH_31_ 1 1 0 0 -.names un7_as_030_i.BLIF AS_030 +.names un3_as_030_i.BLIF AS_030 1 1 0 0 -.names N_122_i.BLIF AS_000 +.names N_175_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1847,9 +1496,6 @@ rw_000_int_0_un1_n .names gnd_n_n.BLIF BERR 1 1 0 0 -.names gnd_n_n.BLIF DTACK -1 1 -0 0 .names inst_RW_000_DMA.BLIF RW 1 1 0 0 @@ -1880,18 +1526,6 @@ rw_000_int_0_un1_n .names inst_A0_DMA.BLIF A_0_ 1 1 0 0 -.names A_DECODE_2_.BLIF a_decode_2__n -1 1 -0 0 -.names AS_030.PIN.BLIF AS_030_c -1 1 -0 0 -.names AS_000.PIN.BLIF AS_000_c -1 1 -0 0 -.names RW_000.PIN.BLIF RW_000_c -1 1 -0 0 .names UDS_000.PIN.BLIF UDS_000_c 1 1 0 0 @@ -1970,9 +1604,6 @@ rw_000_int_0_un1_n .names BGACK_000.BLIF BGACK_000_c 1 1 0 0 -.names CLK_030.BLIF CLK_030_c -1 1 -0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -1988,7 +1619,7 @@ rw_000_int_0_un1_n .names IPL_2_.BLIF ipl_c_2__n 1 1 0 0 -.names DTACK.PIN.BLIF DTACK_c +.names DTACK.BLIF DTACK_c 1 1 0 0 .names VPA.BLIF VPA_c @@ -1997,9 +1628,6 @@ rw_000_int_0_un1_n .names RST.BLIF RST_c 1 1 0 0 -.names RESET.BLIF RESET_c -1 1 -0 0 .names RW.PIN.BLIF RW_c 1 1 0 0 @@ -2048,108 +1676,100 @@ rw_000_int_0_un1_n .names A_DECODE_3_.BLIF a_decode_3__n 1 1 0 0 -.names N_132.BLIF AS_030.OE +.names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 -.names un1_as_000_i.BLIF AS_000.OE +.names AS_030.PIN.BLIF AS_030_c 1 1 0 0 -.names un1_as_000_i.BLIF RW_000.OE +.names AS_000.PIN.BLIF AS_000_c 1 1 0 0 -.names un1_as_000_i.BLIF UDS_000.OE +.names RW_000.PIN.BLIF RW_000_c 1 1 0 0 -.names un1_as_000_i.BLIF LDS_000.OE +.names BGACK_030_INT_i.BLIF AS_030.OE 1 1 0 0 -.names N_276.BLIF SIZE_0_.OE +.names N_69_i.BLIF AS_000.OE 1 1 0 0 -.names N_276.BLIF SIZE_1_.OE +.names N_69_i.BLIF RW_000.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_24_.OE +.names N_69_i.BLIF UDS_000.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_25_.OE +.names N_69_i.BLIF LDS_000.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_26_.OE +.names BGACK_030_INT_i.BLIF SIZE_0_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_27_.OE +.names BGACK_030_INT_i.BLIF SIZE_1_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_28_.OE +.names BGACK_030_INT_i.BLIF AHIGH_24_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_29_.OE +.names BGACK_030_INT_i.BLIF AHIGH_25_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_30_.OE +.names BGACK_030_INT_i.BLIF AHIGH_26_.OE 1 1 0 0 -.names un3_ahigh_i.BLIF AHIGH_31_.OE +.names BGACK_030_INT_i.BLIF AHIGH_27_.OE 1 1 0 0 -.names N_132.BLIF A_0_.OE +.names BGACK_030_INT_i.BLIF AHIGH_28_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF AHIGH_29_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF AHIGH_30_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF AHIGH_31_.OE +1 1 +0 0 +.names BGACK_030_INT_i.BLIF A_0_.OE 1 1 0 0 .names un21_berr.BLIF BERR.OE 1 1 0 0 -.names AS_000_DMA_i.BLIF DTACK.OE +.names BGACK_030_INT_i.BLIF RW.OE 1 1 0 0 -.names N_133.BLIF RW.OE +.names BGACK_030_INT_i.BLIF DS_030.OE 1 1 0 0 -.names N_132.BLIF DS_030.OE +.names un1_dsack1_i.BLIF DSACK1.OE 1 1 0 0 -.names nEXP_SPACE_c.BLIF DSACK1.OE +.names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 0 0 -.names un13_ciin_i.BLIF CIIN.OE +.names N_60.BLIF CIIN.OE 1 1 0 0 -.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_122 +.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_105 01 1 10 1 11 0 00 0 -.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_123 +.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_106 01 1 10 1 11 0 00 0 -.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_124 +.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_107 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF N_76.BLIF cpu_est_0_0_ -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_1_.BLIF N_199.BLIF G_97 -01 1 -10 1 -11 0 -00 0 -.names CYCLE_DMA_0_.BLIF pos_clk_un13_bgack_030_int_n.BLIF G_95 -01 1 -10 1 -11 0 -00 0 -.names CLK_030_PE_0_.BLIF pos_clk_un13_clk_out_int_n.BLIF G_101 -01 1 -10 1 -11 0 -00 0 -.names CLK_030_PE_1_.BLIF N_205.BLIF G_103 +.names CYCLE_DMA_1_.BLIF N_199.BLIF G_91 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 64d4f60..c1387ce 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 12 29 16 1 51) + (timeStamp 2017 12 30 0 43 31) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -125,7 +125,7 @@ (port FPU_CS (direction OUTPUT)) (port FPU_SENSE (direction INPUT)) (port DSACK1 (direction OUTPUT)) - (port DTACK (direction INOUT)) + (port DTACK (direction INPUT)) (port AVEC (direction OUTPUT)) (port E (direction OUTPUT)) (port VPA (direction INPUT)) @@ -140,12 +140,6 @@ (port CIIN (direction OUTPUT)) ) (contents - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -156,10 +150,6 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename IPL_030DFF_0 "IPL_030DFF[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename IPL_030DFF_1 "IPL_030DFF[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -172,7 +162,11 @@ ) (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -182,27 +176,45 @@ ) (instance (rename CLK_000_D_4 "CLK_000_D[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_030_PE_0 "CLK_030_PE[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_030_PE_1 "CLK_030_PE[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -212,39 +224,17 @@ ) (instance AMIGA_DS (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) + (instance AS_030_D1 (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -314,11 +304,11 @@ (instance (rename IPL_1 "IPL[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance (rename IPL_2 "IPL[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance DSACK1 (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance DTACK (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance DTACK (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance AVEC (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance E (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance VPA (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance VMA (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance VMA (viewRef prim (cellRef BUFTH (libraryRef mach))) ) (instance RST (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance RESET (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance RW (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) @@ -329,346 +319,408 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_0 "SM_AMIGA_srsts_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_1_0 "SM_AMIGA_nss_i_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0 "SM_AMIGA_nss_i_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_5 "SM_AMIGA_srsts_i_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_5 "SM_AMIGA_srsts_i_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_125_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_125 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_1_3 "cpu_est_2_i_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_3 "cpu_est_2_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_1 "pos_clk.un6_bg_030_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2 "pos_clk.un6_bg_030_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_a2_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un29_clk_000_ne_1_1 "pos_clk.un29_clk_000_ne_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un29_clk_000_ne_1_2 "pos_clk.un29_clk_000_ne_1_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un29_clk_000_ne_1_3 "pos_clk.un29_clk_000_ne_1_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un29_clk_000_ne_1 "pos_clk.un29_clk_000_ne_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_a3_1 "pos_clk.un9_clk_000_pe_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_a3_2 "pos_clk.un9_clk_000_pe_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_a3 "pos_clk.un9_clk_000_pe_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_a3_0_1 "pos_clk.un9_clk_000_pe_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_a3_0_2 "pos_clk.un9_clk_000_pe_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_a3_0 "pos_clk.un9_clk_000_pe_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a3_0_1_1 "cpu_est_2_0_0_a3_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a3_0_1 "cpu_est_2_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un6_amiga_bus_data_dir (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_1 "pos_clk.as_000_dma6_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_2 "pos_clk.as_000_dma6_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6 "pos_clk.as_000_dma6") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_rw_000_1 "pos_clk.un4_rw_000_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_rw_000_2 "pos_clk.un4_rw_000_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_rw_000 "pos_clk.un4_rw_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un13_clk_out_int_1 "pos_clk.un13_clk_out_int_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un13_clk_out_int "pos_clk.un13_clk_out_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2_0 "pos_clk.un34_as_030_d0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un10_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un6_amiga_bus_data_dir_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un6_amiga_bus_data_dir_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_4 "SM_AMIGA_srsts_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_3 "SM_AMIGA_srsts_i_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_3 "SM_AMIGA_srsts_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_2 "SM_AMIGA_srsts_i_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_2 "SM_AMIGA_srsts_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_2 "SM_AMIGA_srsts_i_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_2 "SM_AMIGA_srsts_i_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_0 "SM_AMIGA_srsts_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_0 "SM_AMIGA_srsts_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_0_1_1 "cpu_est_2_0_0_a2_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_0_1 "cpu_est_2_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_108_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_108 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_0_2 "pos_clk.as_000_dma6_i_0_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_0 "pos_clk.as_000_dma6_i_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a3_i_1 "pos_clk.un6_bg_030_0_a3_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a3_i "pos_clk.un6_bg_030_0_a3_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_6 "SM_AMIGA_srsts_i_0_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_6 "SM_AMIGA_srsts_i_0_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_5 "SM_AMIGA_srsts_i_0_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a3_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_1 "pos_clk.CYCLE_DMA_5_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_90_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_90 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_0_a2_1 "pos_clk.as_000_dma6_i_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_0_a2 "pos_clk.as_000_dma6_i_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_2 "pos_clk.CYCLE_DMA_5_0_i_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_0_1 "pos_clk.as_000_dma6_i_0_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_2 "SM_AMIGA_srsts_i_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_1 "SM_AMIGA_srsts_i_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_2_1 "SM_AMIGA_srsts_i_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1 "SM_AMIGA_srsts_i_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0_1 "pos_clk.un9_clk_000_pe_0_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0_2 "pos_clk.un9_clk_000_pe_0_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0 "pos_clk.un9_clk_000_pe_0_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_1 "pos_clk.un9_clk_000_pe_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_2 "pos_clk.un9_clk_000_pe_0_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_a2 "pos_clk.un9_clk_000_pe_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_a2_1 "pos_clk.un34_as_030_d1_i_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_a2_2 "pos_clk.un34_as_030_d1_i_i_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_a2_3 "pos_clk.un34_as_030_d1_i_i_a2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_a2 "pos_clk.un34_as_030_d1_i_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a3_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_1_3 "SM_AMIGA_srsts_i_0_0_a2_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_2_3 "SM_AMIGA_srsts_i_0_0_a2_1_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_1_3 "SM_AMIGA_srsts_i_0_0_o2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_1_2 "SM_AMIGA_srsts_i_0_0_o2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_0 "SM_AMIGA_nss_i_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_o2_1 "pos_clk.un34_as_030_d1_i_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_o2_2 "pos_clk.un34_as_030_d1_i_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_o2_3 "pos_clk.un34_as_030_d1_i_i_o2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_o2_4 "pos_clk.un34_as_030_d1_i_i_o2_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_o2 "pos_clk.un34_as_030_d1_i_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un15_clk_000_d_i_i_o2_1 "pos_clk.un15_clk_000_d_i_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un15_clk_000_d_i_i_o2_2 "pos_clk.un15_clk_000_d_i_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un15_clk_000_d_i_i_o2 "pos_clk.un15_clk_000_d_i_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2_0_1 "pos_clk.un34_as_030_d0_i_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2_0_2 "pos_clk.un34_as_030_d0_i_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2_0_3 "pos_clk.un34_as_030_d0_i_a2_0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2_0_4 "pos_clk.un34_as_030_d0_i_a2_0_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2_0_5 "pos_clk.un34_as_030_d0_i_a2_0_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_o2_1 "pos_clk.un34_as_030_d0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_o2_2 "pos_clk.un34_as_030_d0_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_o2_3 "pos_clk.un34_as_030_d0_i_o2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_o2 "pos_clk.un34_as_030_d0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_1 "SM_AMIGA_srsts_i_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1 "SM_AMIGA_srsts_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_6 "SM_AMIGA_srsts_i_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_6 "SM_AMIGA_srsts_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_1_4 "SM_AMIGA_srsts_i_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_i "pos_clk.RW_000_INT_5_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_14_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_254_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_263_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_256_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_277_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_i "pos_clk.un34_as_030_d0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_o2_i "pos_clk.un34_as_030_d0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un15_clk_000_d_i_i_o2_i "pos_clk.un15_clk_000_d_i_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un5_bgack_030_int_d_i_0 "pos_clk.un5_bgack_030_int_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_DMA_3_i "pos_clk.RW_000_DMA_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_13_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_DMA_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_DS_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_i "pos_clk.un9_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_182_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_181_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_260_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_259_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_162_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_3 "cpu_est_2_0_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_149_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_i_3 "cpu_est_2_0_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_1 "SM_AMIGA_srsts_i_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_130_i_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a3_i_i "pos_clk.un6_bg_030_0_a3_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_190_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_191_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_266_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_186_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_185_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_183_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_184_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_268_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_6 "SM_AMIGA_srsts_i_0_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_2 "SM_AMIGA_srsts_i_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_DS_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_203_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_201_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_202_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_274_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_0_i "pos_clk.un6_bgack_000_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0_0_i "pos_clk.RW_000_INT_5_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_o2_i "pos_clk.un34_as_030_d1_i_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_0 "SM_AMIGA_srsts_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_11_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_5_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i_i "pos_clk.un34_as_030_d1_i_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_180_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_262_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_amiga_bus_data_dir_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un12_amiga_bus_data_dir_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_111_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un4_bgack_000_i "pos_clk.un4_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_i "pos_clk.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_7_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un1_bgack_030_int_i "pos_clk.un1_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_121_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_111_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un31_clk_000_ne_i_0 "pos_clk.un31_clk_000_ne_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_112_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_113_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_255_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_257_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_i_2 "cpu_est_2_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_258_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_259_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_i_1 "cpu_est_2_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_262_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_261_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_i "pos_clk.un9_clk_000_pe_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_o2_i_3 "cpu_est_2_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_0_o3_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_0_sqmuxa_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_4 "SM_AMIGA_srsts_i_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_2 "SM_AMIGA_srsts_i_o3_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_i_6 "SM_AMIGA_srsts_i_o3_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_166_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o4_i_i_1 "SM_AMIGA_srsts_i_o4_i_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_PE_0_o3_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_23_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_13_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_i_0 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_rst_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_0_i "pos_clk.as_000_dma6_i_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_DS_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_199_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_208 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_a2 "pos_clk.CYCLE_DMA_5_0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_207 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un3_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un2_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_99 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_EXP_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_91 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_D1_0_r "AS_030_D1_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_D1_0_m "AS_030_D1_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_D1_0_n "AS_030_D1_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_D1_0_p "AS_030_D1_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a4_3 "SM_AMIGA_srsts_i_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a4_2 "SM_AMIGA_srsts_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a4_1 "SM_AMIGA_srsts_i_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_124 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_PE_0_o3_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o4_i_1 "SM_AMIGA_srsts_i_o4_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_6 "SM_AMIGA_srsts_i_o3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_2 "SM_AMIGA_srsts_i_o3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o3_4 "SM_AMIGA_srsts_i_o3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_0_sqmuxa_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a4_6 "SM_AMIGA_srsts_i_a4[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a4_4 "SM_AMIGA_srsts_i_a4[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_a4_0_3 "SM_AMIGA_srsts_i_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_a3_3 "cpu_est_2_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance I_220 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_o4_i_a2_1 "SM_AMIGA_srsts_i_o4_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a2_0 "SM_AMIGA_nss_i_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a2_0_0 "SM_AMIGA_nss_i_i_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_5 "SM_AMIGA_srsts_i_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_NE_0_o3_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_o2_3 "cpu_est_2_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_1 "cpu_est_2_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_2 "cpu_est_2_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a3_1 "cpu_est_2_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a3_2 "cpu_est_2_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_a3_0_3 "cpu_est_2_i_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e1_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_rst_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_0_i_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_5 "SM_AMIGA_srsts_i_0_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un31_clk_000_ne "pos_clk.un31_clk_000_ne") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0 "SM_AMIGA_srsts_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i "pos_clk.un34_as_030_d1_i_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_dsack1_0_o3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DSACK1_INT_1_i_a2_0_a2 "pos_clk.DSACK1_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_210 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AS_000_INT_1_i_a2_0_a2 "pos_clk.AS_000_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0 "SM_AMIGA_nss_i_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_6 "SM_AMIGA_srsts_i_0_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_berr_0_a3_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_6 "SM_AMIGA_srsts_i_0_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0_0_o2 "pos_clk.RW_000_INT_5_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0 "SM_AMIGA_srsts_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0_0 "pos_clk.RW_000_INT_5_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_1 "SM_AMIGA_srsts_i_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_3 "cpu_est_2_0_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0_o2 "pos_clk.un9_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_0_2 "cpu_est_2_0_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_0 "pos_clk.un9_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_DS_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_3 "cpu_est_2_0_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_0 "pos_clk.SIZE_DMA_6_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_1 "pos_clk.SIZE_DMA_6_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_0_0 "cpu_est_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_130_i_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_2 "SM_AMIGA_srsts_i_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_4 "SM_AMIGA_srsts_i_0_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_0 "SM_AMIGA_nss_i_i_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_0_a2_0 "cpu_est_0_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_0_a2_0_0 "cpu_est_0_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_214 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_215 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_212 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_213 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_105 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_106 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_107 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_1 "SM_AMIGA_srsts_i_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_1 "SM_AMIGA_srsts_i_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_DS_0_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_0_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a2_1 "cpu_est_2_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a2_3 "cpu_est_2_0_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_187_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_188_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_189_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_218 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_219 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_216 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_217 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -681,171 +733,6 @@ (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_132_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_132_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un4_bgack_000 "pos_clk.un4_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un3_ahigh (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un2_as_030_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_rw_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_as_030_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un31_clk_000_ne_1_i_m2_r "pos_clk.un31_clk_000_ne_1_i_m2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un31_clk_000_ne_1_i_m2_m "pos_clk.un31_clk_000_ne_1_i_m2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un31_clk_000_ne_1_i_m2_n "pos_clk.un31_clk_000_ne_1_i_m2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un31_clk_000_ne_1_i_m2_p "pos_clk.un31_clk_000_ne_1_i_m2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0 "SM_AMIGA_srsts_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CLK_030_PE_4_1 "pos_clk.CLK_030_PE_4_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rst_2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rst_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_DS_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_223 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un4_rw_000_i "pos_clk.un4_rw_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_222 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_030_PE_i_1 "CLK_030_PE_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_95 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_101 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_103 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_111 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_116 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_121 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_97 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance un7_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un13_bgack_030_int "pos_clk.un13_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un1_bgack_030_int "pos_clk.un1_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un3_clk_out_int_i "pos_clk.un3_clk_out_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rst_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0 "pos_clk.CYCLE_DMA_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CLK_030_PE_4_0 "pos_clk.CLK_030_PE_4_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un12_amiga_bus_data_dir_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_EXP_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un3_clk_out_int "pos_clk.un3_clk_out_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i "pos_clk.as_000_dma6_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_96 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance G_102 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_226 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_227 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_224 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_225 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RW_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_DS_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_DMA_3 "pos_clk.RW_000_DMA_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_230 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_231 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_228 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_229 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i "pos_clk.un34_as_030_d0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d0_i_a2 "pos_clk.un34_as_030_d0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un13_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_DS_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AS_000_INT_1_i_a2 "pos_clk.AS_000_INT_1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DSACK1_INT_1_i_a2 "pos_clk.DSACK1_INT_1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_122 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_123 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_o4_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rst_2_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_245_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_274_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -854,44 +741,46 @@ (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance un7_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un13_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance un3_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_175_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un2_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_UDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d)) - (portRef I0 (instanceRef un12_amiga_bus_data_dir_m)) + (portRef I0 (instanceRef un1_dsack1_0_o3_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) (portRef I0 (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef un1_as_000_0)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2_1)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0_1)) (portRef I0 (instanceRef BGACK_030)) + (portRef OE (instanceRef VMA)) )) (net VCC (joined (portRef I0 (instanceRef AVEC)) )) - (net VMA_INT (joined - (portRef Q (instanceRef VMA_INT)) - (portRef I0 (instanceRef VMA_INT_0_n)) - (portRef I0 (instanceRef VMA_INT_i)) - (portRef I0 (instanceRef VMA)) + (net un5_e (joined + (portRef O (instanceRef un5_e_0_0_i)) + (portRef I0 (instanceRef E)) )) (net GND (joined (portRef I0 (instanceRef AHIGH_24)) @@ -904,104 +793,97 @@ (portRef I0 (instanceRef AHIGH_31)) (portRef I0 (instanceRef AMIGA_ADDR_ENABLE)) (portRef I0 (instanceRef BERR)) - (portRef I0 (instanceRef DTACK)) )) (net un1_amiga_bus_enable_low (joined (portRef O (instanceRef un1_amiga_bus_enable_low)) (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) )) - (net un7_as_030 (joined - (portRef O (instanceRef un7_as_030)) - (portRef I0 (instanceRef un7_as_030_i)) - )) - (net un1_LDS_000_INT (joined - (portRef O (instanceRef un1_LDS_000_INT_i)) - (portRef I0 (instanceRef LDS_000)) + (net un3_as_030 (joined + (portRef O (instanceRef un3_as_030)) + (portRef I0 (instanceRef un3_as_030_i)) )) (net un1_UDS_000_INT (joined (portRef O (instanceRef un1_UDS_000_INT_i)) (portRef I0 (instanceRef UDS_000)) )) - (net un1_SM_AMIGA_0_sqmuxa_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_i)) - (portRef I1 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_r)) + (net un1_LDS_000_INT (joined + (portRef O (instanceRef un1_LDS_000_INT_i)) + (portRef I0 (instanceRef LDS_000)) + )) + (net un1_DS_000_ENABLE_0_sqmuxa (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2_i)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) )) (net un10_ciin (joined - (portRef O (instanceRef un10_ciin)) + (portRef O (instanceRef un13_ciin_i_0_0_a2)) (portRef I0 (instanceRef un10_ciin_i)) (portRef I0 (instanceRef CIIN)) )) (net un21_fpu_cs (joined - (portRef O (instanceRef un21_fpu_cs_0_a2)) + (portRef O (instanceRef un21_fpu_cs_0_a3_0_a2)) (portRef I0 (instanceRef un21_fpu_cs_i)) )) (net un21_berr (joined - (portRef O (instanceRef un21_berr_0_a2)) + (portRef O (instanceRef un21_berr_0_a3_0_a2)) (portRef OE (instanceRef BERR)) )) - (net un6_ds_030 (joined - (portRef O (instanceRef un6_ds_030)) - (portRef I0 (instanceRef un6_ds_030_i)) + (net un2_ds_030 (joined + (portRef O (instanceRef un2_ds_030)) + (portRef I0 (instanceRef un2_ds_030_i)) )) - (net un13_ciin (joined - (portRef O (instanceRef un13_ciin)) - (portRef I0 (instanceRef un13_ciin_i)) + (net (rename cpu_est_0 "cpu_est[0]") (joined + (portRef Q (instanceRef cpu_est_0)) + (portRef I1 (instanceRef cpu_est_0_0_0_a2_0_0)) + (portRef I0 (instanceRef cpu_est_i_0)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_1_1)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) (portRef I0 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_2_0_0_a3_1)) - (portRef I1 (instanceRef cpu_est_2_i_0_o2_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef un5_e_i_o2)) - (portRef I0 (instanceRef un5_e_i_a3_0)) + (portRef I0 (instanceRef un5_e_0_0_a2_0_1)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) (portRef I0 (instanceRef cpu_est_0_2__m)) - (portRef I1 (instanceRef un5_e_i_a3)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_3)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef cpu_est_2_i_0_a3_3)) + (portRef I1 (instanceRef un5_e_0_0_a2_0_1)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) (portRef I0 (instanceRef cpu_est_0_3__m)) + (portRef I1 (instanceRef un5_e_0_0_a2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_1_2)) - )) - (net (rename cpu_est_0 "cpu_est[0]") (joined - (portRef Q (instanceRef cpu_est_0)) - (portRef I0 (instanceRef cpu_est_2_i_0_a3_0_3)) - (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I0 (instanceRef cpu_est_2_i_0_o2_3)) - (portRef I1 (instanceRef cpu_est_0_0)) - (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1_1)) )) (net AMIGA_BUS_ENABLE_DMA_HIGH (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) )) (net AMIGA_BUS_ENABLE_DMA_LOW (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) (portRef I0 (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef I0 (instanceRef AS_030_D1_0_m)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_i_1)) + )) + (net AS_030_D1 (joined + (portRef Q (instanceRef AS_030_D1)) + (portRef I0 (instanceRef AS_030_D1_i)) + (portRef I0 (instanceRef AS_030_D1_0_n)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) - )) - (net BGACK_030_INT_D (joined - (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef pos_clk_un5_bgack_030_int_d)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) @@ -1013,10 +895,15 @@ (portRef I0 (instanceRef DS_000_DMA_0_m)) (portRef I0 (instanceRef DS_000_DMA_i)) )) + (net VMA_INT (joined + (portRef Q (instanceRef VMA_INT)) + (portRef I0 (instanceRef VMA_INT_0_n)) + (portRef I0 (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef VMA)) + )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) - (portRef I1 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_m)) - (portRef I0 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) (portRef I0 (instanceRef VPA_D_i)) )) (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined @@ -1028,34 +915,21 @@ (portRef Q (instanceRef DTACK_D0)) (portRef I0 (instanceRef DTACK_D0_i)) )) - (net RESET_OUT (joined - (portRef Q (instanceRef RESET_OUT)) - (portRef I1 (instanceRef un4_as_030_i_a2)) - (portRef I1 (instanceRef un1_rw_i_a2)) - (portRef I1 (instanceRef un1_as_000_0)) - (portRef I0 (instanceRef RESET_OUT_2_0_a2)) - )) - (net (rename CLK_030_PE_1 "CLK_030_PE[1]") (joined - (portRef Q (instanceRef CLK_030_PE_1)) - (portRef I1 (instanceRef G_121)) - (portRef I0 (instanceRef G_103)) - (portRef I0 (instanceRef CLK_030_PE_i_1)) - )) (net AMIGA_DS (joined (portRef Q (instanceRef AMIGA_DS)) (portRef I0 (instanceRef AMIGA_DS_i)) )) (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined (portRef Q (instanceRef CLK_000_D_1)) - (portRef I0 (instanceRef CLK_000_NE_0_o3_i_o2)) + (portRef I0 (instanceRef N_130_i_0_o2_i_o2)) (portRef I0 (instanceRef CLK_000_D_i_1)) (portRef D (instanceRef CLK_000_D_2)) )) (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined (portRef Q (instanceRef CLK_000_D_0)) - (portRef I0 (instanceRef CLK_000_PE_0_o3_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) (portRef I0 (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a3_i_1)) (portRef D (instanceRef CLK_000_D_1)) )) (net CLK_OUT_PRE_50 (joined @@ -1065,20 +939,20 @@ )) (net CLK_OUT_PRE_D (joined (portRef Q (instanceRef CLK_OUT_PRE_D)) - (portRef I1 (instanceRef pos_clk_un3_clk_out_int)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_1)) (portRef D (instanceRef CLK_OUT_INT)) )) (net (rename IPL_D0_0 "IPL_D0[0]") (joined (portRef Q (instanceRef IPL_D0_0)) - (portRef I0 (instanceRef G_122)) + (portRef I0 (instanceRef G_105)) )) (net (rename IPL_D0_1 "IPL_D0[1]") (joined (portRef Q (instanceRef IPL_D0_1)) - (portRef I0 (instanceRef G_123)) + (portRef I0 (instanceRef G_106)) )) (net (rename IPL_D0_2 "IPL_D0[2]") (joined (portRef Q (instanceRef IPL_D0_2)) - (portRef I0 (instanceRef G_124)) + (portRef I0 (instanceRef G_107)) )) (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined (portRef Q (instanceRef CLK_000_D_2)) @@ -1086,126 +960,93 @@ )) (net (rename CLK_000_D_4 "CLK_000_D[4]") (joined (portRef Q (instanceRef CLK_000_D_4)) - (portRef I0 (instanceRef pos_clk_un15_clk_000_d_i_i_o2_2)) - )) - (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) )) (net (rename pos_clk_ipl "pos_clk.ipl") (joined - (portRef O (instanceRef G_125)) + (portRef O (instanceRef G_108)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) (portRef I1 (instanceRef IPL_030_0_1__m)) (portRef I0 (instanceRef IPL_030_0_1__r)) (portRef I1 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__r)) )) - (net LDS_000_INT (joined - (portRef Q (instanceRef LDS_000_INT)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) - (portRef I0 (instanceRef LDS_000_INT_i)) + (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined + (portRef Q (instanceRef SIZE_DMA_0)) + (portRef I0 (instanceRef SIZE_0)) )) - (net DS_000_ENABLE (joined - (portRef Q (instanceRef DS_000_ENABLE)) - (portRef I0 (instanceRef un1_LDS_000_INT)) - (portRef I0 (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef un1_UDS_000_INT)) + (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined + (portRef Q (instanceRef SIZE_DMA_1)) + (portRef I0 (instanceRef SIZE_1)) + )) + (net A0_DMA (joined + (portRef Q (instanceRef A0_DMA)) + (portRef I0 (instanceRef A_0)) + )) + (net RW_000_DMA (joined + (portRef Q (instanceRef RW_000_DMA)) + (portRef I0 (instanceRef RW)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) (portRef I0 (instanceRef UDS_000_INT_0_n)) (portRef I0 (instanceRef UDS_000_INT_i)) )) + (net DS_000_ENABLE (joined + (portRef Q (instanceRef DS_000_ENABLE)) + (portRef I0 (instanceRef un1_LDS_000_INT)) + (portRef I0 (instanceRef un1_UDS_000_INT)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) + )) + (net LDS_000_INT (joined + (portRef Q (instanceRef LDS_000_INT)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + (portRef I0 (instanceRef LDS_000_INT_i)) + )) + (net BGACK_030_INT_D (joined + (portRef Q (instanceRef BGACK_030_INT_D)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_1)) + )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef DS_000_ENABLE_0_sqmuxa_1)) - )) - (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined - (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I0 (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3)) - )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - )) - (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined - (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I0 (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) - )) - (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined - (portRef Q (instanceRef SIZE_DMA_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_0)) - )) - (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined - (portRef Q (instanceRef SIZE_DMA_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_1)) - )) - (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined - (portRef Q (instanceRef CYCLE_DMA_0)) - (portRef I0 (instanceRef G_96)) - (portRef I0 (instanceRef G_111)) - (portRef I0 (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef G_95)) - )) - (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined - (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I0 (instanceRef G_97)) - (portRef I1 (instanceRef G_111)) - (portRef I0 (instanceRef CYCLE_DMA_i_1)) - )) - (net (rename CLK_030_PE_0 "CLK_030_PE[0]") (joined - (portRef Q (instanceRef CLK_030_PE_0)) - (portRef I0 (instanceRef G_102)) - (portRef I0 (instanceRef G_121)) - (portRef I0 (instanceRef G_101)) - (portRef I0 (instanceRef pos_clk_un4_rw_000_1)) )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) (portRef I0 (instanceRef RW_000_INT_0_n)) (portRef I0 (instanceRef RW_000)) )) - (net RW_000_DMA (joined - (portRef Q (instanceRef RW_000_DMA)) - (portRef I0 (instanceRef RW_000_DMA_0_n)) - (portRef I0 (instanceRef RW)) + (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined + (portRef Q (instanceRef SM_AMIGA_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) + (portRef I0 (instanceRef SM_AMIGA_i_4)) )) - (net (rename RST_DLY_0 "RST_DLY[0]") (joined - (portRef Q (instanceRef RST_DLY_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_a2)) - (portRef I0 (instanceRef RST_DLY_i_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_o2_0)) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) )) - (net (rename RST_DLY_1 "RST_DLY[1]") (joined - (portRef Q (instanceRef RST_DLY_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_o2_0)) - (portRef I0 (instanceRef RST_DLY_i_1)) + (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined + (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_i_0)) )) - (net (rename RST_DLY_2 "RST_DLY[2]") (joined - (portRef Q (instanceRef RST_DLY_2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_132_0_a2)) - (portRef I0 (instanceRef RST_DLY_i_2)) + (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined + (portRef Q (instanceRef CYCLE_DMA_0)) + (portRef I0 (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_a2_1)) + (portRef I1 (instanceRef G_90_1)) )) - (net A0_DMA (joined - (portRef Q (instanceRef A0_DMA)) - (portRef I0 (instanceRef A0_DMA_0_n)) - (portRef I0 (instanceRef A_0)) - )) - (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) + (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined + (portRef Q (instanceRef CYCLE_DMA_1)) + (portRef I0 (instanceRef G_91)) + (portRef I0 (instanceRef CYCLE_DMA_i_1)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_a2_1)) )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) @@ -1215,446 +1056,517 @@ (portRef Q (instanceRef AS_000_INT)) (portRef I0 (instanceRef AS_000_INT_i)) )) + (net (rename pos_clk_un9_clk_000_pe "pos_clk.un9_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_5)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_2)) (portRef I0 (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) (portRef I0 (instanceRef SM_AMIGA_i_2)) )) - (net (rename pos_clk_CYCLE_DMA_5_0 "pos_clk.CYCLE_DMA_5[0]") (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0)) - (portRef D (instanceRef CYCLE_DMA_0)) - )) (net (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5[1]") (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1)) (portRef D (instanceRef CYCLE_DMA_1)) )) - (net (rename pos_clk_CLK_030_PE_4_0 "pos_clk.CLK_030_PE_4[0]") (joined - (portRef O (instanceRef pos_clk_CLK_030_PE_4_0)) - (portRef D (instanceRef CLK_030_PE_0)) - )) - (net (rename pos_clk_CLK_030_PE_4_1 "pos_clk.CLK_030_PE_4[1]") (joined - (portRef O (instanceRef pos_clk_CLK_030_PE_4_1)) - (portRef D (instanceRef CLK_030_PE_1)) - )) - (net N_5 (joined - (portRef O (instanceRef SIZE_DMA_0_0__p)) - (portRef D (instanceRef SIZE_DMA_0)) - )) (net N_6 (joined - (portRef O (instanceRef SIZE_DMA_0_1__p)) - (portRef D (instanceRef SIZE_DMA_1)) + (portRef O (instanceRef DS_000_ENABLE_0_p)) + (portRef I0 (instanceRef DS_000_ENABLE_1)) )) - (net N_10 (joined + (net N_8 (joined (portRef O (instanceRef cpu_est_0_1__p)) (portRef D (instanceRef cpu_est_1)) )) - (net N_11 (joined + (net N_9 (joined (portRef O (instanceRef cpu_est_0_2__p)) (portRef D (instanceRef cpu_est_2)) )) - (net N_12 (joined + (net N_10 (joined (portRef O (instanceRef cpu_est_0_3__p)) (portRef D (instanceRef cpu_est_3)) )) + (net N_13 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef I0 (instanceRef N_13_i)) + )) (net N_14 (joined - (portRef O (instanceRef AS_030_000_SYNC_0_p)) - (portRef I0 (instanceRef N_14_i)) + (portRef O (instanceRef AS_030_D1_0_p)) + (portRef D (instanceRef AS_030_D1)) )) - (net N_15 (joined - (portRef O (instanceRef RW_000_INT_0_p)) - (portRef I0 (instanceRef N_15_i)) - )) - (net N_24 (joined + (net N_18 (joined (portRef O (instanceRef IPL_030_0_0__p)) - (portRef I0 (instanceRef N_24_i)) + (portRef I0 (instanceRef N_18_i)) )) - (net N_25 (joined + (net N_19 (joined (portRef O (instanceRef IPL_030_0_1__p)) - (portRef I0 (instanceRef N_25_i)) + (portRef I0 (instanceRef N_19_i)) )) - (net N_27 (joined + (net N_20 (joined + (portRef O (instanceRef IPL_030_0_2__p)) + (portRef I0 (instanceRef N_20_i)) + )) + (net N_21 (joined (portRef O (instanceRef IPL_030_1_i_0)) (portRef D (instanceRef IPL_030DFF_0)) )) - (net N_28 (joined + (net N_22 (joined (portRef O (instanceRef IPL_030_1_i_1)) (portRef D (instanceRef IPL_030DFF_1)) )) - (net N_29 (joined + (net N_23 (joined (portRef O (instanceRef IPL_030_1_i_2)) (portRef D (instanceRef IPL_030DFF_2)) )) - (net N_30 (joined - (portRef O (instanceRef BG_000_1_i)) - (portRef D (instanceRef BG_000DFF)) - )) - (net N_31 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) - (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) - )) - (net N_32 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) - (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) - )) - (net N_33 (joined + (net N_24 (joined (portRef O (instanceRef UDS_000_INT_1_i)) (portRef D (instanceRef UDS_000_INT)) )) - (net N_34 (joined - (portRef O (instanceRef A0_DMA_1_i)) - (portRef D (instanceRef A0_DMA)) + (net N_25 (joined + (portRef O (instanceRef BG_000_1_i)) + (portRef D (instanceRef BG_000DFF)) )) - (net N_35 (joined - (portRef O (instanceRef RW_000_DMA_1_i)) - (portRef D (instanceRef RW_000_DMA)) - )) - (net N_36 (joined - (portRef O (instanceRef VMA_INT_1_i)) - (portRef D (instanceRef VMA_INT)) - )) - (net N_38 (joined - (portRef O (instanceRef RW_000_INT_1_i)) - (portRef D (instanceRef RW_000_INT)) - )) - (net N_39 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_i)) - (portRef D (instanceRef AS_030_000_SYNC)) - )) - (net N_40 (joined + (net N_26 (joined (portRef O (instanceRef LDS_000_INT_1_i)) (portRef D (instanceRef LDS_000_INT)) )) - (net N_41 (joined + (net N_27 (joined + (portRef O (instanceRef VMA_INT_1_i)) + (portRef D (instanceRef VMA_INT)) + )) + (net N_28 (joined + (portRef O (instanceRef RW_000_INT_1_i)) + (portRef D (instanceRef RW_000_INT)) + )) + (net N_29 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_i)) + (portRef D (instanceRef AS_030_000_SYNC)) + )) + (net N_30 (joined (portRef O (instanceRef BGACK_030_INT_1_i)) (portRef D (instanceRef BGACK_030_INT)) )) - (net N_42 (joined + (net N_31 (joined (portRef O (instanceRef AS_000_DMA_1_i)) (portRef D (instanceRef AS_000_DMA)) )) - (net N_43 (joined + (net N_32 (joined (portRef O (instanceRef DS_000_DMA_1_i)) (portRef D (instanceRef DS_000_DMA)) )) - (net N_46 (joined - (portRef O (instanceRef AMIGA_DS_0_0_i)) + (net N_35 (joined + (portRef O (instanceRef AMIGA_DS_0_0_0_i)) (portRef D (instanceRef AMIGA_DS)) )) - (net N_48 (joined - (portRef O (instanceRef DTACK_D0_0_i)) - (portRef D (instanceRef DTACK_D0)) + (net N_36 (joined + (portRef O (instanceRef A0_DMA_0_0_0_i)) + (portRef D (instanceRef A0_DMA)) )) - (net N_49 (joined + (net N_38 (joined + (portRef O (instanceRef AS_030_D0_0_0_0_i)) + (portRef D (instanceRef AS_030_D0)) + )) + (net N_41 (joined (portRef O (instanceRef IPL_D0_0_i_0)) (portRef D (instanceRef IPL_D0_0)) )) - (net N_50 (joined + (net N_42 (joined (portRef O (instanceRef IPL_D0_0_i_1)) (portRef D (instanceRef IPL_D0_1)) )) - (net N_51 (joined + (net N_43 (joined (portRef O (instanceRef IPL_D0_0_i_2)) (portRef D (instanceRef IPL_D0_2)) )) - (net N_52 (joined + (net N_44 (joined (portRef O (instanceRef VPA_D_0_i)) (portRef D (instanceRef VPA_D)) )) - (net N_53 (joined - (portRef O (instanceRef RESET_OUT_2_0_i)) - (portRef D (instanceRef RESET_OUT)) + (net N_45 (joined + (portRef O (instanceRef DTACK_D0_0_i)) + (portRef D (instanceRef DTACK_D0)) )) - (net N_54 (joined + (net N_46 (joined (portRef O (instanceRef DS_000_ENABLE_1)) (portRef D (instanceRef DS_000_ENABLE)) )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef Q (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_o4_0)) + (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) (portRef I0 (instanceRef SM_AMIGA_i_i_7)) )) - (net N_76 (joined - (portRef O (instanceRef CLK_000_NE_0_o3_i_o2_i)) + (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) + (portRef D (instanceRef SIZE_DMA_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + (portRef D (instanceRef SIZE_DMA_1)) + )) + (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__n)) + )) + (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_2_3 "cpu_est_2[3]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__n)) + )) + (net N_187 (joined + (portRef O (instanceRef G_105)) + (portRef I0 (instanceRef N_187_i)) + )) + (net N_188 (joined + (portRef O (instanceRef G_106)) + (portRef I0 (instanceRef N_188_i)) + )) + (net N_189 (joined + (portRef O (instanceRef G_107)) + (portRef I0 (instanceRef N_189_i)) + )) + (net N_60 (joined + (portRef O (instanceRef un13_ciin_i_0_0_i)) + (portRef OE (instanceRef CIIN)) + )) + (net N_63 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_r)) + )) + (net N_126 (joined + (portRef O (instanceRef RW_000_DMA_0_i_a3_0_a2)) + (portRef I0 (instanceRef N_126_i)) + )) + (net N_150 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2)) + (portRef I0 (instanceRef N_150_i)) + )) + (net N_151 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2)) + (portRef I0 (instanceRef N_151_i)) + )) + (net N_219 (joined + (portRef O (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef N_219_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i_0_a2)) + )) + (net N_175 (joined + (portRef O (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef N_175_i)) + (portRef I0 (instanceRef AS_000_INT_0_i_0_a2)) + )) + (net N_220 (joined + (portRef O (instanceRef un1_rst_2_i_o2_i)) + (portRef D (instanceRef BGACK_030_INT_D)) + )) + (net N_59 (joined + (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_i_i)) + (portRef I1 (instanceRef pos_clk_un9_bg_030)) + )) + (net N_68 (joined + (portRef O (instanceRef N_130_i_0_o2_i_o2_i)) (portRef I1 (instanceRef cpu_est_0_3__m)) (portRef I0 (instanceRef cpu_est_0_3__r)) (portRef I1 (instanceRef cpu_est_0_2__m)) (portRef I0 (instanceRef cpu_est_0_2__r)) (portRef I1 (instanceRef cpu_est_0_1__m)) (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I0 (instanceRef RST_DLY_e2_i_a2_2)) - (portRef I0 (instanceRef RST_DLY_e1_i_a2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o4_i_a2_1)) - (portRef I0 (instanceRef cpu_est_0_0)) - (portRef I0 (instanceRef RST_DLY_e0_i_a2_0_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_5)) + (portRef I0 (instanceRef cpu_est_0_0_0_a2_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) )) - (net N_224 (joined - (portRef O (instanceRef G_122)) - (portRef I0 (instanceRef N_224_i)) + (net N_72 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) )) - (net N_225 (joined - (portRef O (instanceRef G_123)) - (portRef I0 (instanceRef N_225_i)) + (net N_80 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_3)) )) - (net N_226 (joined - (portRef O (instanceRef G_124)) - (portRef I0 (instanceRef N_226_i)) + (net N_93 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) )) - (net un1_rst_2_1 (joined - (portRef O (instanceRef un1_rst_2_1)) - (portRef I0 (instanceRef un1_rst_2_1_i)) - (portRef I1 (instanceRef un1_rst_2)) + (net N_98 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) )) - (net N_245 (joined - (portRef O (instanceRef cpu_est_0_0)) - (portRef I0 (instanceRef N_245_i)) + (net N_107 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2)) )) - (net N_64 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_i)) + (net N_128 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) + )) + (net N_131 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) + )) + (net N_134 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) + )) + (net N_135 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + )) + (net N_141 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) + (portRef I0 (instanceRef N_141_i)) + )) + (net N_142 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) + (portRef I0 (instanceRef N_142_i)) + )) + (net N_143 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) + (portRef I0 (instanceRef N_143_i)) + )) + (net N_144 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) + (portRef I0 (instanceRef N_144_i)) + )) + (net N_145 (joined + (portRef O (instanceRef AMIGA_DS_0_0_0_a2)) + (portRef I0 (instanceRef N_145_i)) + )) + (net N_146 (joined + (portRef O (instanceRef A0_DMA_0_0_0_a2)) + (portRef I0 (instanceRef N_146_i)) + )) + (net N_147 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I0 (instanceRef N_147_i)) + )) + (net N_148 (joined + (portRef O (instanceRef cpu_est_2_0_0_a2_0_1)) + (portRef I0 (instanceRef N_148_i)) + )) + (net N_149 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I0 (instanceRef N_149_i)) + )) + (net N_154 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_3)) + (portRef I0 (instanceRef N_154_i)) + )) + (net N_155 (joined + (portRef O (instanceRef un5_e_0_0_a2)) + (portRef I0 (instanceRef N_155_i)) + )) + (net N_162 (joined + (portRef O (instanceRef un5_e_0_0_a2_0)) + (portRef I0 (instanceRef N_162_i)) + )) + (net N_165 (joined + (portRef O (instanceRef un11_amiga_bus_enable_high_0_0_a2_0)) + (portRef I0 (instanceRef N_165_i)) + )) + (net N_259 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) + (portRef I0 (instanceRef N_259_i)) + )) + (net N_260 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) + (portRef I0 (instanceRef N_260_i)) + )) + (net N_181 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) + (portRef I0 (instanceRef N_181_i)) + )) + (net N_182 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) + (portRef I0 (instanceRef N_182_i)) + )) + (net N_183 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + (portRef I0 (instanceRef N_183_i)) + )) + (net N_184 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (portRef I0 (instanceRef N_184_i)) + )) + (net N_185 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + (portRef I0 (instanceRef N_185_i)) + )) + (net N_186 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + (portRef I0 (instanceRef N_186_i)) + )) + (net N_266 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) + (portRef I0 (instanceRef N_266_i)) + )) + (net N_267 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (portRef I0 (instanceRef N_267_i)) + )) + (net N_268 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) + (portRef I0 (instanceRef N_268_i)) + )) + (net N_190 (joined + (portRef O (instanceRef cpu_est_0_0_0_a2_0)) + (portRef I0 (instanceRef N_190_i)) + )) + (net N_191 (joined + (portRef O (instanceRef cpu_est_0_0_0_a2_0_0)) + (portRef I0 (instanceRef N_191_i)) + )) + (net N_201 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (portRef I0 (instanceRef N_201_i)) + )) + (net N_202 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (portRef I0 (instanceRef N_202_i)) + )) + (net N_203 (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) + (portRef I0 (instanceRef N_203_i)) + )) + (net N_208 (joined + (portRef O (instanceRef cpu_est_2_0_0_a2_0_2)) + (portRef I0 (instanceRef N_208_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) + )) + (net N_163 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2)) + (portRef I0 (instanceRef N_163_i)) + )) + (net N_282 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_2)) + )) + (net un21_berr_1 (joined + (portRef O (instanceRef un21_berr_0_a3_0_a2_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a3_0_a2_1)) + (portRef I0 (instanceRef un21_berr_0_a3_0_a2_1_0)) + )) + (net N_132 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) + )) + (net N_96 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + )) + (net N_129 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) + )) + (net un1_SM_AMIGA_0_sqmuxa_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) + )) + (net N_169 (joined + (portRef O (instanceRef AS_000_INT_0_i_0_a2)) + (portRef I0 (instanceRef N_169_i)) + )) + (net N_170 (joined + (portRef O (instanceRef AS_000_INT_0_i_0_a2_0)) + (portRef I0 (instanceRef N_170_i)) + )) + (net N_167 (joined + (portRef O (instanceRef DSACK1_INT_0_i_0_a2)) + (portRef I0 (instanceRef N_167_i)) + )) + (net N_168 (joined + (portRef O (instanceRef DSACK1_INT_0_i_0_a2_0)) + (portRef I0 (instanceRef N_168_i)) + )) + (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + )) + (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) + (net N_274 (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef N_274_i)) + )) + (net N_164 (joined + (portRef O (instanceRef un11_amiga_bus_enable_high_0_0_a2)) + (portRef I0 (instanceRef N_164_i)) + )) + (net N_244 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_i)) (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) - (net N_122 (joined - (portRef O (instanceRef pos_clk_AS_000_INT_1_i_a2)) - (portRef I0 (instanceRef N_122_i)) + (net N_5 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef I0 (instanceRef N_5_i)) )) - (net N_123 (joined - (portRef O (instanceRef pos_clk_DSACK1_INT_1_i_a2)) - (portRef I0 (instanceRef N_123_i)) + (net N_11 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_p)) + (portRef I0 (instanceRef N_11_i)) )) - (net N_132 (joined - (portRef O (instanceRef un4_as_030_i_a2)) - (portRef OE (instanceRef AS_030)) - (portRef OE (instanceRef A_0)) - (portRef OE (instanceRef DS_030)) + (net N_12 (joined + (portRef O (instanceRef RW_000_INT_0_p)) + (portRef I0 (instanceRef N_12_i)) )) - (net N_133 (joined - (portRef O (instanceRef un1_rw_i_a2)) - (portRef OE (instanceRef RW)) - )) - (net N_274 (joined - (portRef O (instanceRef AS_030_D0_0_i_a2)) - (portRef I0 (instanceRef N_274_i)) - (portRef I1 (instanceRef DSACK1_INT_0_i_a2)) - (portRef I1 (instanceRef AS_000_INT_0_i_a2)) - )) - (net N_276 (joined - (portRef O (instanceRef un2_as_030_i_a2)) - (portRef I0 (instanceRef un4_as_030_i_a2)) - (portRef I0 (instanceRef un3_ahigh)) - (portRef OE (instanceRef SIZE_0)) - (portRef OE (instanceRef SIZE_1)) - )) - (net N_77 (joined - (portRef O (instanceRef RST_DLY_e2_i_o2_0_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_a2_1)) - )) - (net N_79 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_6)) - )) - (net N_78 (joined - (portRef O (instanceRef CLK_000_PE_0_o3_i_o2_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o4_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_0)) - )) - (net N_263 (joined - (portRef O (instanceRef un5_e_i_a2)) - (portRef I0 (instanceRef N_263_i)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) - )) - (net N_108 (joined - (portRef O (instanceRef RST_DLY_e2_i_a2)) - (portRef I0 (instanceRef N_108_i)) - )) - (net N_114 (joined - (portRef O (instanceRef RST_DLY_e1_i_a2_1)) - (portRef I0 (instanceRef N_114_i)) - )) - (net N_85 (joined - (portRef O (instanceRef pos_clk_un15_clk_000_d_i_i_o2_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) - )) - (net N_104 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) - (portRef I0 (instanceRef N_104_i)) - )) - (net N_91 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_i)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2)) - )) - (net N_131 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2)) - (portRef I0 (instanceRef N_131_i)) - )) - (net N_277 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0)) - (portRef I0 (instanceRef N_277_i)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_1)) - (portRef I0 (instanceRef un21_berr_0_a2_1)) - )) - (net N_130 (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_a2_0)) - (portRef I0 (instanceRef N_130_i)) - )) - (net N_115 (joined - (portRef O (instanceRef RST_DLY_e0_i_a2)) - (portRef I0 (instanceRef N_115_i)) - )) - (net N_116 (joined - (portRef O (instanceRef RST_DLY_e0_i_a2_0)) - (portRef I0 (instanceRef N_116_i)) - )) - (net N_105 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_5)) - (portRef I0 (instanceRef N_105_i)) - )) - (net N_103 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) - (portRef I0 (instanceRef N_103_i)) - )) - (net N_101 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - (portRef I0 (instanceRef N_101_i)) - )) - (net N_259 (joined - (portRef O (instanceRef cpu_est_2_0_0_a3_0_1)) - (portRef I0 (instanceRef N_259_i)) - )) - (net N_255 (joined - (portRef O (instanceRef cpu_est_2_i_0_a3_3)) - (portRef I0 (instanceRef N_255_i)) - )) - (net N_256 (joined - (portRef O (instanceRef cpu_est_2_i_0_a3_0_3)) - (portRef I0 (instanceRef N_256_i)) - )) - (net N_254 (joined - (portRef O (instanceRef un5_e_i_a3)) - (portRef I0 (instanceRef N_254_i)) + (net N_15 (joined + (portRef O (instanceRef LDS_000_INT_0_p)) + (portRef I0 (instanceRef N_15_i)) )) (net N_16 (joined - (portRef O (instanceRef un5_e_i_a3_0)) + (portRef O (instanceRef BG_000_0_p)) (portRef I0 (instanceRef N_16_i)) )) - (net N_106 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I0 (instanceRef N_106_i)) + (net N_17 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef I0 (instanceRef N_17_i)) )) - (net N_86 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined + (portRef O (instanceRef pos_clk_un9_bg_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) )) - (net N_107 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) - (portRef I0 (instanceRef N_107_i)) - )) - (net N_117 (joined - (portRef O (instanceRef AMIGA_DS_0_0_a2)) - (portRef I0 (instanceRef N_117_i)) - )) - (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined - (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I0 (instanceRef A0_DMA_0_m)) - )) - (net N_129 (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_a2)) - (portRef I0 (instanceRef N_129_i)) - )) - (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) - (portRef I0 (instanceRef SIZE_DMA_0_1__n)) - )) - (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) - (portRef I0 (instanceRef SIZE_DMA_0_0__n)) - )) - (net (rename pos_clk_RW_000_DMA_3 "pos_clk.RW_000_DMA_3") (joined - (portRef O (instanceRef pos_clk_RW_000_DMA_3_i)) - (portRef I0 (instanceRef RW_000_DMA_0_m)) - )) - (net (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3") (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - )) - (net (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3") (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - )) - (net SIZE_DMA_3_sqmuxa (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa)) - (portRef I1 (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_0_0__r)) - (portRef I1 (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__r)) - )) - (net (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (joined - (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0)) - (portRef I1 (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - )) - (net N_18 (joined - (portRef O (instanceRef RW_000_DMA_0_p)) - (portRef I0 (instanceRef N_18_i)) - )) - (net N_19 (joined - (portRef O (instanceRef A0_DMA_0_p)) - (portRef I0 (instanceRef N_19_i)) - )) - (net N_21 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - (portRef I0 (instanceRef N_21_i)) - )) - (net N_22 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - (portRef I0 (instanceRef N_22_i)) - )) - (net un6_amiga_bus_data_dir (joined - (portRef O (instanceRef un6_amiga_bus_data_dir)) - (portRef I0 (instanceRef un6_amiga_bus_data_dir_i)) - )) - (net un12_amiga_bus_data_dir_m (joined - (portRef O (instanceRef un12_amiga_bus_data_dir_m)) - (portRef I0 (instanceRef un12_amiga_bus_data_dir_m_i)) - )) - (net (rename pos_clk_un3_clk_out_int "pos_clk.un3_clk_out_int") (joined - (portRef O (instanceRef pos_clk_un3_clk_out_int)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I0 (instanceRef pos_clk_un3_clk_out_int_i)) - (portRef I1 (instanceRef pos_clk_un13_clk_out_int)) + (net (rename un1_CYCLE_DMA_2 "un1_CYCLE_DMA[2]") (joined + (portRef O (instanceRef G_91)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1)) )) (net N_3 (joined (portRef O (instanceRef DS_000_DMA_0_p)) (portRef I0 (instanceRef N_3_i)) )) - (net (rename pos_clk_as_000_dma6 "pos_clk.as_000_dma6") (joined - (portRef O (instanceRef pos_clk_as_000_dma6)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I1 (instanceRef un1_rst_3)) - (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_1)) + (net N_205 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_i)) + (portRef I0 (instanceRef AS_000_DMA_0_n)) + (portRef I0 (instanceRef DS_000_DMA_0_n)) )) - (net DS_000_DMA_1_sqmuxa (joined - (portRef O (instanceRef DS_000_DMA_1_sqmuxa)) + (net AS_000_DMA_1_sqmuxa (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) (portRef I1 (instanceRef DS_000_DMA_0_m)) (portRef I0 (instanceRef DS_000_DMA_0_r)) )) @@ -1662,295 +1574,30 @@ (portRef O (instanceRef AS_000_DMA_0_p)) (portRef I0 (instanceRef N_4_i)) )) - (net AS_000_DMA_1_sqmuxa (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa)) - (portRef I1 (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_r)) - )) - (net un1_rst_2 (joined - (portRef O (instanceRef un1_rst_2)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0)) - )) - (net (rename un1_CYCLE_DMA_2 "un1_CYCLE_DMA[2]") (joined - (portRef O (instanceRef G_97)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1)) - )) (net N_199 (joined - (portRef O (instanceRef G_96)) - (portRef I1 (instanceRef G_97)) + (portRef O (instanceRef G_90)) + (portRef I1 (instanceRef G_91)) + (portRef I0 (instanceRef N_199_i)) )) - (net (rename pos_clk_un13_bgack_030_int "pos_clk.un13_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un13_bgack_030_int)) - (portRef I1 (instanceRef G_96)) - (portRef I1 (instanceRef G_95)) + (net (rename pos_clk_un2 "pos_clk.un2") (joined + (portRef O (instanceRef G_99_i)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_2)) )) - (net N_205 (joined - (portRef O (instanceRef G_102)) - (portRef I1 (instanceRef G_103)) - )) - (net (rename pos_clk_un13_clk_out_int "pos_clk.un13_clk_out_int") (joined - (portRef O (instanceRef pos_clk_un13_clk_out_int)) - (portRef I1 (instanceRef G_102)) - (portRef I1 (instanceRef G_101)) - )) - (net (rename pos_clk_un15_bgack_030_int "pos_clk.un15_bgack_030_int") (joined - (portRef O (instanceRef G_111_i)) - (portRef I1 (instanceRef pos_clk_un13_bgack_030_int)) - )) - (net (rename pos_clk_un3 "pos_clk.un3") (joined - (portRef O (instanceRef G_116_i)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_2)) - )) - (net (rename pos_clk_un12_clk_out_int "pos_clk.un12_clk_out_int") (joined - (portRef O (instanceRef G_121_i)) - (portRef I0 (instanceRef pos_clk_un13_clk_out_int_1)) - )) - (net (rename pos_clk_un1_bgack_030_int "pos_clk.un1_bgack_030_int") (joined - (portRef O (instanceRef pos_clk_un1_bgack_030_int_i)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_2)) - )) - (net DS_000_DMA_0_sqmuxa (joined - (portRef O (instanceRef DS_000_DMA_0_sqmuxa)) - (portRef I0 (instanceRef DS_000_DMA_0_sqmuxa_i)) - )) - (net un1_rst_3 (joined - (portRef O (instanceRef un1_rst_3)) - (portRef I1 (instanceRef pos_clk_CLK_030_PE_4_0)) - (portRef I1 (instanceRef pos_clk_CLK_030_PE_4_1)) - )) - (net (rename un1_CYCLE_DMA_1 "un1_CYCLE_DMA[1]") (joined - (portRef O (instanceRef G_95)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0)) - )) - (net (rename un1_CLK_030_PE_1_1 "un1_CLK_030_PE_1[1]") (joined - (portRef O (instanceRef G_101)) - (portRef I0 (instanceRef pos_clk_CLK_030_PE_4_0)) - )) - (net (rename un1_CLK_030_PE_1_2 "un1_CLK_030_PE_1[2]") (joined - (portRef O (instanceRef G_103)) - (portRef I0 (instanceRef pos_clk_CLK_030_PE_4_1)) - )) - (net (rename pos_clk_un4_rw_000 "pos_clk.un4_rw_000") (joined - (portRef O (instanceRef pos_clk_un4_rw_000)) - (portRef I0 (instanceRef pos_clk_un4_rw_000_i)) - )) - (net N_7 (joined - (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef I0 (instanceRef N_7_i)) - )) - (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) - )) - (net (rename pos_clk_un4_bgack_000 "pos_clk.un4_bgack_000") (joined - (portRef O (instanceRef pos_clk_un4_bgack_000)) - (portRef I0 (instanceRef pos_clk_un4_bgack_000_i)) - )) - (net N_265_2 (joined - (portRef O (instanceRef RST_DLY_e2_i_2_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_a2_0)) - )) - (net N_111 (joined - (portRef O (instanceRef RST_DLY_e2_i_a2_2)) - (portRef I0 (instanceRef N_111_i)) - )) - (net N_109 (joined - (portRef O (instanceRef RST_DLY_e2_i_a2_0)) - (portRef I0 (instanceRef N_109_i)) - )) - (net N_113 (joined - (portRef O (instanceRef RST_DLY_e1_i_a2_0)) - (portRef I0 (instanceRef N_113_i)) - )) - (net N_112 (joined - (portRef O (instanceRef RST_DLY_e1_i_a2)) - (portRef I0 (instanceRef N_112_i)) - )) - (net N_98 (joined - (portRef O (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_p)) - (portRef I0 (instanceRef N_98_i)) - )) - (net (rename pos_clk_un29_clk_000_ne_1 "pos_clk.un29_clk_000_ne_1") (joined - (portRef O (instanceRef pos_clk_un29_clk_000_ne_1)) - (portRef I0 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_n)) - )) - (net N_87 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - )) - (net N_270 (joined - (portRef O (instanceRef RST_DLY_e2_i_o2_i)) - (portRef I0 (instanceRef RST_DLY_e0_i_a2)) - )) - (net N_134 (joined - (portRef O (instanceRef RST_DLY_e2_i_a2_3)) - (portRef I1 (instanceRef RST_DLY_e1_i_a2)) - (portRef I0 (instanceRef N_134_i)) - )) - (net N_125 (joined - (portRef O (instanceRef RESET_OUT_2_0_a2_0)) - (portRef I0 (instanceRef N_125_i)) - )) - (net N_124 (joined - (portRef O (instanceRef RESET_OUT_2_0_a2)) - (portRef I0 (instanceRef N_124_i)) - )) - (net N_121 (joined - (portRef O (instanceRef DSACK1_INT_0_i_a2_0)) - (portRef I0 (instanceRef N_121_i)) - )) - (net N_120 (joined - (portRef O (instanceRef DSACK1_INT_0_i_a2)) - (portRef I0 (instanceRef N_120_i)) - )) - (net N_137 (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_132_0_a2)) - (portRef I0 (instanceRef N_137_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_a2_0)) - (portRef I1 (instanceRef RESET_OUT_2_0_a2_0_1)) - )) - (net (rename pos_clk_un31_clk_000_ne "pos_clk.un31_clk_000_ne") (joined - (portRef O (instanceRef pos_clk_un31_clk_000_ne_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_0_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_2)) - )) - (net N_17 (joined - (portRef O (instanceRef VMA_INT_0_p)) - (portRef I0 (instanceRef N_17_i)) - )) - (net (rename pos_clk_un9_clk_000_pe "pos_clk.un9_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) - )) - (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) - )) - (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) - )) - (net N_261 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3)) - (portRef I0 (instanceRef N_261_i)) + (net N_140 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_a2)) + (portRef I0 (instanceRef N_140_i)) )) (net N_262 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) (portRef I0 (instanceRef N_262_i)) )) - (net N_251 (joined - (portRef O (instanceRef cpu_est_2_i_0_o2_i_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_a3_3)) + (net N_198 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) + (portRef I0 (instanceRef N_198_i)) )) - (net N_252 (joined - (portRef O (instanceRef un5_e_i_o2_i)) - (portRef I0 (instanceRef un5_e_i_a3)) - )) - (net N_258 (joined - (portRef O (instanceRef cpu_est_2_0_0_a3_1)) - (portRef I0 (instanceRef N_258_i)) - )) - (net N_257 (joined - (portRef O (instanceRef cpu_est_2_0_0_a3_2)) - (portRef I0 (instanceRef N_257_i)) - )) - (net DS_000_ENABLE_1_sqmuxa (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa)) - (portRef I1 (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef DS_000_ENABLE_0_r)) - )) - (net un1_DS_000_ENABLE_0_sqmuxa (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_i_0)) - (portRef I0 (instanceRef DS_000_ENABLE_0_n)) - )) - (net N_102 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o4_i_a2_1)) - (portRef I0 (instanceRef N_102_i)) - )) - (net N_118 (joined - (portRef O (instanceRef AS_000_INT_0_i_a2)) - (portRef I0 (instanceRef N_118_i)) - )) - (net N_119 (joined - (portRef O (instanceRef AS_000_INT_0_i_a2_0)) - (portRef I0 (instanceRef N_119_i)) - )) - (net N_264 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o4_i_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_1)) - )) - (net DS_000_ENABLE_0_sqmuxa_1 (joined - (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_1)) - (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_1_i)) - )) - (net N_164 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a4_1)) - (portRef I0 (instanceRef N_164_i)) - )) - (net N_170 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a4_6)) - (portRef I0 (instanceRef N_170_i)) - )) - (net N_168 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a4_4)) - (portRef I0 (instanceRef N_168_i)) - )) - (net N_166 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a4_3)) - (portRef I0 (instanceRef N_166_i)) - )) - (net N_167 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a4_0_3)) - (portRef I0 (instanceRef N_167_i)) - )) - (net N_165 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_a4_2)) - (portRef I0 (instanceRef N_165_i)) - )) - (net N_162 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a4_6)) - )) - (net N_161 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a4_2)) - )) - (net N_160 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_i_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a4_4)) - )) - (net N_157 (joined - (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3_i)) - (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a4_3)) - )) - (net N_26 (joined - (portRef O (instanceRef IPL_030_0_2__p)) - (portRef I0 (instanceRef N_26_i)) - )) - (net N_13 (joined - (portRef O (instanceRef LDS_000_INT_0_p)) - (portRef I0 (instanceRef N_13_i)) - )) - (net N_20 (joined - (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef I0 (instanceRef N_20_i)) - )) - (net N_23 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef I0 (instanceRef N_23_i)) - )) - (net N_8 (joined - (portRef O (instanceRef DS_000_ENABLE_0_p)) - (portRef I0 (instanceRef DS_000_ENABLE_1)) - )) - (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined - (portRef O (instanceRef pos_clk_un9_bg_030_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) + (net N_180 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) + (portRef I0 (instanceRef N_180_i)) )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) @@ -1960,338 +1607,288 @@ (portRef O (instanceRef un21_fpu_cs_i)) (portRef I0 (instanceRef FPU_CS)) )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o4_i_a2_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_2)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a4_1)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_3)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_4)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_a4_6)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_5)) - )) - (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined - (portRef O (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef CLK_000_NE_0_o3_i_o2)) - )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2)) - (portRef I0 (instanceRef AS_000_INT_0_i_a2)) - )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a2_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o3_6)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2_2)) - )) - (net AS_030_i (joined - (portRef O (instanceRef I_220)) - (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2)) - (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2)) - (portRef I0 (instanceRef AS_030_D0_0_i_a2)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_1)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_a2_0)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef cpu_est_2_i_0_a3_0_3)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_2)) - (portRef I0 (instanceRef un5_e_i_a2)) - (portRef I1 (instanceRef un5_e_i_a3_0)) - (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_1_1)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) - (portRef I1 (instanceRef pos_clk_un29_clk_000_ne_1_2)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef un5_e_i_a2)) - (portRef I1 (instanceRef un5_e_i_o2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1_1)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) - (portRef I1 (instanceRef pos_clk_un29_clk_000_ne_1)) - )) - (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined - (portRef O (instanceRef CLK_000_D_i_1)) - (portRef I1 (instanceRef CLK_000_PE_0_o3_i_o2)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) - )) - (net VMA_INT_i (joined - (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef pos_clk_un29_clk_000_ne_1_1)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - )) - (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined - (portRef O (instanceRef RST_DLY_i_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_a2_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_a2)) - )) - (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined - (portRef O (instanceRef RST_DLY_i_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_a2_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_a2_1)) - )) - (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined - (portRef O (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_a2_0_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_a2_1_1)) - )) - (net DSACK1_INT_i (joined - (portRef O (instanceRef DSACK1_INT_i)) - (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2)) - (portRef I0 (instanceRef DSACK1_INT_0_i_a2)) - )) - (net N_137_i_0 (joined - (portRef O (instanceRef N_137_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_a2_3)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_132_0)) - )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_m)) + (net AS_000_i (joined + (portRef O (instanceRef I_207)) + (portRef I0 (instanceRef un2_ds_030)) + (portRef I1 (instanceRef un3_as_030)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) )) (net BGACK_030_INT_i (joined (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_a2)) - (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3)) - (portRef I0 (instanceRef pos_clk_RW_000_DMA_3)) + (portRef I0 (instanceRef A0_DMA_0_0_0_a2)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0_a2)) + (portRef I0 (instanceRef un1_rst_2_i_o2)) (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I0 (instanceRef un1_rst_2_1)) - (portRef I0 (instanceRef un1_rw_i_a2)) - (portRef I0 (instanceRef un2_as_030_i_a2)) - (portRef I1 (instanceRef un6_amiga_bus_data_dir_1)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) + (portRef OE (instanceRef AHIGH_24)) + (portRef OE (instanceRef AHIGH_25)) + (portRef OE (instanceRef AHIGH_26)) + (portRef OE (instanceRef AHIGH_27)) + (portRef OE (instanceRef AHIGH_28)) + (portRef OE (instanceRef AHIGH_29)) + (portRef OE (instanceRef AHIGH_30)) + (portRef OE (instanceRef AHIGH_31)) + (portRef OE (instanceRef AS_030)) + (portRef OE (instanceRef A_0)) + (portRef OE (instanceRef DS_030)) + (portRef OE (instanceRef RW)) + (portRef OE (instanceRef SIZE_0)) + (portRef OE (instanceRef SIZE_1)) )) (net nEXP_SPACE_i (joined (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef un13_ciin)) - (portRef I1 (instanceRef un2_as_030_i_a2)) - (portRef I1 (instanceRef un6_amiga_bus_data_dir_2)) - )) - (net AS_000_DMA_i (joined - (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef un7_as_030)) - (portRef I1 (instanceRef pos_clk_un13_clk_out_int_1)) - (portRef OE (instanceRef DTACK)) - )) - (net RW_000_i (joined - (portRef O (instanceRef I_222)) - (portRef I1 (instanceRef pos_clk_RW_000_DMA_3)) - (portRef I1 (instanceRef un12_amiga_bus_data_dir_m)) - (portRef I0 (instanceRef pos_clk_un1_bgack_030_int)) - (portRef I1 (instanceRef pos_clk_un4_rw_000_2)) - )) - (net (rename CLK_030_PE_i_1 "CLK_030_PE_i[1]") (joined - (portRef O (instanceRef CLK_030_PE_i_1)) - (portRef I1 (instanceRef pos_clk_un4_rw_000_1)) - )) - (net DS_000_DMA_0_sqmuxa_i (joined - (portRef O (instanceRef DS_000_DMA_0_sqmuxa_i)) - (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_1)) - )) - (net (rename pos_clk_un4_rw_000_i "pos_clk.un4_rw_000_i") (joined - (portRef O (instanceRef pos_clk_un4_rw_000_i)) - (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_223)) - (portRef I0 (instanceRef un6_ds_030)) - (portRef I1 (instanceRef un7_as_030)) - (portRef I0 (instanceRef un1_rst_2)) - (portRef I0 (instanceRef un6_amiga_bus_data_dir_1)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_1)) - )) - (net AMIGA_DS_i (joined - (portRef O (instanceRef AMIGA_DS_i)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_1)) - )) - (net (rename pos_clk_un3_clk_out_int_i "pos_clk.un3_clk_out_int_i") (joined - (portRef O (instanceRef pos_clk_un3_clk_out_int_i)) - (portRef I1 (instanceRef DS_000_DMA_0_sqmuxa)) + (portRef I0 (instanceRef un13_ciin_i_0_0)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) )) (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined (portRef O (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef G_116)) + (portRef I0 (instanceRef G_99)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) )) - (net (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (joined - (portRef O (instanceRef CYCLE_DMA_i_1)) - (portRef I1 (instanceRef G_116)) - )) - (net (rename pos_clk_as_000_dma6_i "pos_clk.as_000_dma6_i") (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i)) - (portRef I0 (instanceRef AS_000_DMA_0_n)) - (portRef I0 (instanceRef DS_000_DMA_0_n)) - )) - (net DS_000_DMA_i (joined - (portRef O (instanceRef DS_000_DMA_i)) - (portRef I1 (instanceRef un6_ds_030)) + (net RW_000_i (joined + (portRef O (instanceRef I_208)) + (portRef I1 (instanceRef RW_000_DMA_0_i_a3_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_a2)) )) (net CLK_EXP_i (joined (portRef O (instanceRef CLK_EXP_i)) - (portRef I0 (instanceRef pos_clk_un3_clk_out_int)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_1)) + )) + (net (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (joined + (portRef O (instanceRef CYCLE_DMA_i_1)) + (portRef I1 (instanceRef G_99)) + (portRef I1 (instanceRef G_90)) + )) + (net DS_000_DMA_i (joined + (portRef O (instanceRef DS_000_DMA_i)) + (portRef I1 (instanceRef un2_ds_030)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef un3_as_030)) + )) + (net (rename A_i_1 "A_i[1]") (joined + (portRef O (instanceRef A_i_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2)) )) (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) (portRef I0 (instanceRef un1_amiga_bus_enable_low)) )) - (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined - (portRef O (instanceRef I_224)) - (portRef I1 (instanceRef un10_ciin_1)) - )) - (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined - (portRef O (instanceRef I_225)) - (portRef I0 (instanceRef un10_ciin_1)) - )) - (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined - (portRef O (instanceRef I_226)) - (portRef I1 (instanceRef un10_ciin_2)) - )) - (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined - (portRef O (instanceRef I_227)) - (portRef I0 (instanceRef un10_ciin_2)) - )) - (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined - (portRef O (instanceRef I_228)) - (portRef I1 (instanceRef un10_ciin_3)) - )) - (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined - (portRef O (instanceRef I_229)) - (portRef I0 (instanceRef un10_ciin_3)) - )) - (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined - (portRef O (instanceRef I_230)) - (portRef I1 (instanceRef un10_ciin_4)) - )) - (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined - (portRef O (instanceRef I_231)) - (portRef I0 (instanceRef un10_ciin_4)) - )) - (net (rename A_i_1 "A_i[1]") (joined - (portRef O (instanceRef A_i_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3)) - )) - (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_a2)) - )) - (net AS_030_D0_i (joined - (portRef O (instanceRef AS_030_D0_i)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_2)) - (portRef I1 (instanceRef un10_ciin_5)) - )) - (net un10_ciin_i (joined - (portRef O (instanceRef un10_ciin_i)) - (portRef I1 (instanceRef un13_ciin)) - )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2)) - )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef pos_clk_un15_clk_000_d_i_i_o2_1)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_a2_0_1)) - )) - (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined - (portRef O (instanceRef A_DECODE_i_16)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_2)) + (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined + (portRef O (instanceRef A_DECODE_i_19)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_3)) )) (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined (portRef O (instanceRef A_DECODE_i_18)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_3)) )) - (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined - (portRef O (instanceRef A_DECODE_i_19)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_3)) + (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined + (portRef O (instanceRef A_DECODE_i_16)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_2)) )) - (net N_224_i (joined - (portRef O (instanceRef N_224_i)) - (portRef I1 (instanceRef G_125_1)) + (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0_a2)) )) - (net N_225_i (joined - (portRef O (instanceRef N_225_i)) - (portRef I1 (instanceRef G_125)) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) )) - (net N_226_i (joined - (portRef O (instanceRef N_226_i)) - (portRef I0 (instanceRef G_125_1)) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) + )) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_2)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_210)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I0 (instanceRef AS_030_D0_0_0_0)) + (portRef I0 (instanceRef un21_berr_0_a3_0_a2_1)) + (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0)) + )) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) + )) + (net DSACK1_INT_i (joined + (portRef O (instanceRef DSACK1_INT_i)) + (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I1 (instanceRef un21_fpu_cs_0_a3_0_a2_1)) + )) + (net AS_030_D1_i (joined + (portRef O (instanceRef AS_030_D1_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_1)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I1 (instanceRef cpu_est_0_0_0_a2_0)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_3)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_1)) + (portRef I1 (instanceRef un5_e_0_0_a2_0)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_1_1)) + )) + (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined + (portRef O (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef N_130_i_0_o2_i_o2)) + )) + (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined + (portRef O (instanceRef CLK_000_D_i_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) + )) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_5)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0_1)) + )) + (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined + (portRef O (instanceRef I_212)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_4)) + )) + (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined + (portRef O (instanceRef I_213)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_4)) + )) + (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined + (portRef O (instanceRef I_214)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_3)) + )) + (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined + (portRef O (instanceRef I_215)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_3)) + )) + (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined + (portRef O (instanceRef I_216)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_2)) + )) + (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined + (portRef O (instanceRef I_217)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_2)) + )) + (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined + (portRef O (instanceRef I_218)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_1)) + )) + (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined + (portRef O (instanceRef I_219)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_1)) + )) + (net N_187_i (joined + (portRef O (instanceRef N_187_i)) + (portRef I1 (instanceRef G_108_1)) + )) + (net N_188_i (joined + (portRef O (instanceRef N_188_i)) + (portRef I1 (instanceRef G_108)) + )) + (net N_189_i (joined + (portRef O (instanceRef N_189_i)) + (portRef I0 (instanceRef G_108_1)) )) (net CLK_OUT_PRE_50_i (joined (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net un1_rst_2_1_i (joined - (portRef O (instanceRef un1_rst_2_1_i)) - (portRef D (instanceRef BGACK_030_INT_D)) + (net N_150_i (joined + (portRef O (instanceRef N_150_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) )) - (net N_274_i (joined - (portRef O (instanceRef N_274_i)) - (portRef D (instanceRef AS_030_D0)) + (net N_126_i (joined + (portRef O (instanceRef N_126_i)) + (portRef D (instanceRef RW_000_DMA)) )) - (net N_245_i (joined - (portRef O (instanceRef N_245_i)) - (portRef D (instanceRef cpu_est_0)) + (net N_151_i (joined + (portRef O (instanceRef N_151_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) )) - (net un13_ciin_i (joined - (portRef O (instanceRef un13_ciin_i)) - (portRef OE (instanceRef CIIN)) - )) - (net un6_ds_030_i (joined - (portRef O (instanceRef un6_ds_030_i)) + (net un2_ds_030_i (joined + (portRef O (instanceRef un2_ds_030_i)) (portRef I0 (instanceRef DS_030)) )) - (net N_123_i (joined - (portRef O (instanceRef N_123_i)) + (net N_219_i (joined + (portRef O (instanceRef N_219_i)) (portRef I0 (instanceRef DSACK1)) )) - (net N_122_i (joined - (portRef O (instanceRef N_122_i)) + (net N_175_i (joined + (portRef O (instanceRef N_175_i)) (portRef I0 (instanceRef AS_000)) )) - (net un7_as_030_i (joined - (portRef O (instanceRef un7_as_030_i)) + (net un3_as_030_i (joined + (portRef O (instanceRef un3_as_030_i)) (portRef I0 (instanceRef AS_030)) )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) - (portRef I0 (instanceRef I_220)) + (portRef I0 (instanceRef I_210)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) (net AS_030 (joined (portRef AS_030) @@ -2299,8 +1896,8 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef I_223)) - (portRef I0 (instanceRef pos_clk_un4_bgack_000)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef I_207)) )) (net AS_000 (joined (portRef AS_000) @@ -2308,9 +1905,8 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef DS_000_DMA_0_sqmuxa)) - (portRef I0 (instanceRef I_222)) - (portRef I0 (instanceRef un6_amiga_bus_data_dir_2)) + (portRef I0 (instanceRef I_208)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -2322,8 +1918,8 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2)) - (portRef I1 (instanceRef AMIGA_DS_0_0_a2)) + (portRef I1 (instanceRef A0_DMA_0_0_0_a2)) + (portRef I1 (instanceRef AMIGA_DS_0_0_0_a2)) (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined @@ -2332,7 +1928,7 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef AMIGA_DS_0_0_a2)) + (portRef I0 (instanceRef AMIGA_DS_0_0_0_a2)) (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined @@ -2357,7 +1953,7 @@ )) (net (rename AHIGH_c_24 "AHIGH_c[24]") (joined (portRef O (instanceRef AHIGH_24)) - (portRef I0 (instanceRef I_225)) + (portRef I0 (instanceRef I_218)) )) (net (rename AHIGH_24 "AHIGH[24]") (joined (portRef IO (instanceRef AHIGH_24)) @@ -2365,7 +1961,7 @@ )) (net (rename AHIGH_c_25 "AHIGH_c[25]") (joined (portRef O (instanceRef AHIGH_25)) - (portRef I0 (instanceRef I_224)) + (portRef I0 (instanceRef I_219)) )) (net (rename AHIGH_25 "AHIGH[25]") (joined (portRef IO (instanceRef AHIGH_25)) @@ -2373,7 +1969,7 @@ )) (net (rename AHIGH_c_26 "AHIGH_c[26]") (joined (portRef O (instanceRef AHIGH_26)) - (portRef I0 (instanceRef I_227)) + (portRef I0 (instanceRef I_216)) )) (net (rename AHIGH_26 "AHIGH[26]") (joined (portRef IO (instanceRef AHIGH_26)) @@ -2381,7 +1977,7 @@ )) (net (rename AHIGH_c_27 "AHIGH_c[27]") (joined (portRef O (instanceRef AHIGH_27)) - (portRef I0 (instanceRef I_226)) + (portRef I0 (instanceRef I_217)) )) (net (rename AHIGH_27 "AHIGH[27]") (joined (portRef IO (instanceRef AHIGH_27)) @@ -2389,7 +1985,7 @@ )) (net (rename AHIGH_c_28 "AHIGH_c[28]") (joined (portRef O (instanceRef AHIGH_28)) - (portRef I0 (instanceRef I_229)) + (portRef I0 (instanceRef I_214)) )) (net (rename AHIGH_28 "AHIGH[28]") (joined (portRef IO (instanceRef AHIGH_28)) @@ -2397,7 +1993,7 @@ )) (net (rename AHIGH_c_29 "AHIGH_c[29]") (joined (portRef O (instanceRef AHIGH_29)) - (portRef I0 (instanceRef I_228)) + (portRef I0 (instanceRef I_215)) )) (net (rename AHIGH_29 "AHIGH[29]") (joined (portRef IO (instanceRef AHIGH_29)) @@ -2405,7 +2001,7 @@ )) (net (rename AHIGH_c_30 "AHIGH_c[30]") (joined (portRef O (instanceRef AHIGH_30)) - (portRef I0 (instanceRef I_231)) + (portRef I0 (instanceRef I_212)) )) (net (rename AHIGH_30 "AHIGH[30]") (joined (portRef IO (instanceRef AHIGH_30)) @@ -2413,7 +2009,7 @@ )) (net (rename AHIGH_c_31 "AHIGH_c[31]") (joined (portRef O (instanceRef AHIGH_31)) - (portRef I0 (instanceRef I_230)) + (portRef I0 (instanceRef I_213)) )) (net (rename AHIGH_31 "AHIGH[31]") (joined (portRef (member ahigh 0)) @@ -2527,7 +2123,7 @@ )) (net (rename A_DECODE_c_17 "A_DECODE_c[17]") (joined (portRef O (instanceRef A_DECODE_17)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_2)) )) (net (rename A_DECODE_17 "A_DECODE[17]") (joined (portRef (member a_decode 6)) @@ -2551,7 +2147,7 @@ )) (net (rename A_DECODE_c_20 "A_DECODE_c[20]") (joined (portRef O (instanceRef A_DECODE_20)) - (portRef I0 (instanceRef un10_ciin_6)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_6)) )) (net (rename A_DECODE_20 "A_DECODE[20]") (joined (portRef (member a_decode 3)) @@ -2559,7 +2155,7 @@ )) (net (rename A_DECODE_c_21 "A_DECODE_c[21]") (joined (portRef O (instanceRef A_DECODE_21)) - (portRef I1 (instanceRef un10_ciin_6)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_6)) )) (net (rename A_DECODE_21 "A_DECODE[21]") (joined (portRef (member a_decode 2)) @@ -2567,7 +2163,7 @@ )) (net (rename A_DECODE_c_22 "A_DECODE_c[22]") (joined (portRef O (instanceRef A_DECODE_22)) - (portRef I1 (instanceRef un10_ciin_11)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_11)) )) (net (rename A_DECODE_22 "A_DECODE[22]") (joined (portRef (member a_decode 1)) @@ -2575,7 +2171,7 @@ )) (net (rename A_DECODE_c_23 "A_DECODE_c[23]") (joined (portRef O (instanceRef A_DECODE_23)) - (portRef I0 (instanceRef un10_ciin_5)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_5)) )) (net (rename A_DECODE_23 "A_DECODE[23]") (joined (portRef (member a_decode 0)) @@ -2592,8 +2188,8 @@ )) (net (rename A_c_1 "A_c[1]") (joined (portRef O (instanceRef A_1)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3)) (portRef I0 (instanceRef A_i_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2)) )) (net (rename A_1 "A[1]") (joined (portRef (member a 0)) @@ -2601,11 +2197,10 @@ )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) + (portRef I1 (instanceRef un1_dsack1_0_o3_0)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2)) - (portRef I1 (instanceRef pos_clk_un15_clk_000_d_i_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_1)) - (portRef OE (instanceRef DSACK1)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a3_i)) )) (net nEXP_SPACE (joined (portRef nEXP_SPACE) @@ -2613,7 +2208,7 @@ )) (net BERR_c (joined (portRef O (instanceRef BERR)) - (portRef I0 (instanceRef pos_clk_un31_clk_000_ne)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) )) (net BERR (joined (portRef BERR) @@ -2643,10 +2238,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0)) + (portRef I1 (instanceRef un21_berr_0_a3_0_a2_1)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000)) - (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) - (portRef I1 (instanceRef un21_berr_0_a2_1)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -2654,7 +2248,6 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I0 (instanceRef pos_clk_un4_rw_000_2)) )) (net CLK_030 (joined (portRef CLK_030) @@ -2678,6 +2271,7 @@ (portRef CLK (instanceRef AS_000_INT)) (portRef CLK (instanceRef AS_030_000_SYNC)) (portRef CLK (instanceRef AS_030_D0)) + (portRef CLK (instanceRef AS_030_D1)) (portRef CLK (instanceRef BGACK_030_INT)) (portRef CLK (instanceRef BGACK_030_INT_D)) (portRef CLK (instanceRef BG_000DFF)) @@ -2686,8 +2280,6 @@ (portRef CLK (instanceRef CLK_000_D_2)) (portRef CLK (instanceRef CLK_000_D_3)) (portRef CLK (instanceRef CLK_000_D_4)) - (portRef CLK (instanceRef CLK_030_PE_0)) - (portRef CLK (instanceRef CLK_030_PE_1)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE_50)) (portRef CLK (instanceRef CLK_OUT_PRE_D)) @@ -2704,10 +2296,6 @@ (portRef CLK (instanceRef IPL_D0_1)) (portRef CLK (instanceRef IPL_D0_2)) (portRef CLK (instanceRef LDS_000_INT)) - (portRef CLK (instanceRef RESET_OUT)) - (portRef CLK (instanceRef RST_DLY_0)) - (portRef CLK (instanceRef RST_DLY_1)) - (portRef CLK (instanceRef RST_DLY_2)) (portRef CLK (instanceRef RW_000_DMA)) (portRef CLK (instanceRef RW_000_INT)) (portRef CLK (instanceRef SIZE_DMA_0)) @@ -2753,7 +2341,7 @@ (net FPU_SENSE_c (joined (portRef O (instanceRef FPU_SENSE)) (portRef I0 (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_berr_0_a2)) + (portRef I1 (instanceRef un21_berr_0_a3_0_a2_1_0)) )) (net FPU_SENSE (joined (portRef FPU_SENSE) @@ -2789,7 +2377,7 @@ (net (rename IPL_c_0 "IPL_c[0]") (joined (portRef O (instanceRef IPL_0)) (portRef I0 (instanceRef IPL_030_0_0__m)) - (portRef I1 (instanceRef G_122)) + (portRef I1 (instanceRef G_105)) (portRef I0 (instanceRef IPL_c_i_0)) )) (net (rename IPL_0 "IPL[0]") (joined @@ -2799,7 +2387,7 @@ (net (rename IPL_c_1 "IPL_c[1]") (joined (portRef O (instanceRef IPL_1)) (portRef I0 (instanceRef IPL_030_0_1__m)) - (portRef I1 (instanceRef G_123)) + (portRef I1 (instanceRef G_106)) (portRef I0 (instanceRef IPL_c_i_1)) )) (net (rename IPL_1 "IPL[1]") (joined @@ -2809,7 +2397,7 @@ (net (rename IPL_c_2 "IPL_c[2]") (joined (portRef O (instanceRef IPL_2)) (portRef I0 (instanceRef IPL_030_0_2__m)) - (portRef I1 (instanceRef G_124)) + (portRef I1 (instanceRef G_107)) (portRef I0 (instanceRef IPL_c_i_2)) )) (net (rename IPL_2 "IPL[2]") (joined @@ -2826,7 +2414,7 @@ )) (net DTACK (joined (portRef DTACK) - (portRef IO (instanceRef DTACK)) + (portRef I0 (instanceRef DTACK)) )) (net AVEC (joined (portRef O (instanceRef AVEC)) @@ -2850,53 +2438,45 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) + (portRef I1 (instanceRef IPL_D0_0_0)) + (portRef I1 (instanceRef DTACK_D0_0)) + (portRef I0 (instanceRef VPA_D_0)) + (portRef I1 (instanceRef VMA_INT_1)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef IPL_030_1_2)) (portRef I1 (instanceRef IPL_030_1_1)) (portRef I1 (instanceRef IPL_030_1_0)) + (portRef I1 (instanceRef IPL_D0_0_2)) (portRef I1 (instanceRef IPL_D0_0_1)) - (portRef I1 (instanceRef IPL_D0_0_0)) - (portRef I1 (instanceRef AS_030_000_SYNC_1)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + (portRef I1 (instanceRef A0_DMA_0_0_0)) + (portRef I1 (instanceRef AMIGA_DS_0_0_0)) + (portRef I1 (instanceRef AS_030_D0_0_0_0)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0)) (portRef I1 (instanceRef RW_000_INT_1)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa)) - (portRef I1 (instanceRef AMIGA_DS_0_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I1 (instanceRef A0_DMA_1)) - (portRef I1 (instanceRef RW_000_DMA_1)) + (portRef I1 (instanceRef AS_030_000_SYNC_1)) + (portRef I1 (instanceRef BGACK_030_INT_1)) + (portRef I1 (instanceRef DSACK1_INT_0_i_0_a2)) + (portRef I1 (instanceRef DSACK1_INT_0_i_0_a2_0)) + (portRef I1 (instanceRef AS_000_INT_0_i_0_a2)) + (portRef I1 (instanceRef AS_000_INT_0_i_0_a2_0)) + (portRef I1 (instanceRef un1_rst_2_i_o2)) + (portRef I1 (instanceRef AS_030_D1_0_m)) + (portRef I0 (instanceRef AS_030_D1_0_r)) + (portRef I1 (instanceRef UDS_000_INT_1)) + (portRef I1 (instanceRef BG_000_1)) + (portRef I1 (instanceRef LDS_000_INT_1)) (portRef I1 (instanceRef DS_000_DMA_1)) (portRef I1 (instanceRef AS_000_DMA_1)) - (portRef I0 (instanceRef un1_rst_3)) - (portRef I1 (instanceRef BGACK_030_INT_1)) - (portRef I1 (instanceRef un1_rst_2_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_2)) - (portRef I0 (instanceRef VPA_D_0)) - (portRef I1 (instanceRef DTACK_D0_0)) - (portRef I1 (instanceRef DSACK1_INT_0_i_a2_0)) - (portRef I1 (instanceRef RESET_OUT_2_0_a2)) - (portRef I1 (instanceRef AS_030_D0_0_i_a2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_132_0)) - (portRef I1 (instanceRef RST_DLY_e2_i_o2)) - (portRef I1 (instanceRef VMA_INT_1)) - (portRef I1 (instanceRef AS_000_INT_0_i_a2_0)) - (portRef I1 (instanceRef BG_000_1)) - (portRef I1 (instanceRef UDS_000_INT_1)) - (portRef I1 (instanceRef LDS_000_INT_1)) - (portRef I1 (instanceRef IPL_D0_0_2)) - (portRef I1 (instanceRef IPL_030_1_2)) - (portRef I1 (instanceRef DS_000_ENABLE_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_4)) - (portRef I1 (instanceRef RST_DLY_e0_i_a2_0)) - (portRef I1 (instanceRef RESET_OUT_2_0_a2_0)) - (portRef I1 (instanceRef RST_DLY_e0_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_5)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) )) (net RST (joined (portRef RST) @@ -2904,7 +2484,6 @@ )) (net RESET_c (joined (portRef O (instanceRef RESET)) - (portRef I1 (instanceRef un3_ahigh)) )) (net RESET (joined (portRef RESET) @@ -2912,8 +2491,8 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) (portRef I0 (instanceRef RW_c_i)) - (portRef I1 (instanceRef DS_000_ENABLE_0_sqmuxa_1_1)) )) (net RW (joined (portRef IO (instanceRef RW)) @@ -2921,7 +2500,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_5)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_1)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -2929,7 +2508,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_3)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_1)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -2940,7 +2519,7 @@ (portRef AMIGA_ADDR_ENABLE) )) (net AMIGA_BUS_DATA_DIR_c (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) (net AMIGA_BUS_DATA_DIR (joined @@ -2959,73 +2538,127 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) + (net N_205_i (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_i)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) + )) + (net N_140_i (joined + (portRef O (instanceRef N_140_i)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_2)) + )) + (net AMIGA_DS_i (joined + (portRef O (instanceRef AMIGA_DS_i)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_1)) + )) + (net N_66_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + (portRef D (instanceRef CYCLE_DMA_0)) + )) + (net N_199_i (joined + (portRef O (instanceRef N_199_i)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + )) + (net N_198_i (joined + (portRef O (instanceRef N_198_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + )) + (net N_180_i (joined + (portRef O (instanceRef N_180_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) + )) + (net N_262_i (joined + (portRef O (instanceRef N_262_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_i)) + )) + (net (rename pos_clk_un2_i "pos_clk.un2_i") (joined + (portRef O (instanceRef G_99)) + (portRef I0 (instanceRef G_99_i)) + )) + (net N_3_i (joined + (portRef O (instanceRef N_3_i)) + (portRef I0 (instanceRef DS_000_DMA_1)) + )) + (net N_32_0 (joined + (portRef O (instanceRef DS_000_DMA_1)) + (portRef I0 (instanceRef DS_000_DMA_1_i)) + )) + (net N_4_i (joined + (portRef O (instanceRef N_4_i)) + (portRef I0 (instanceRef AS_000_DMA_1)) + )) + (net N_31_0 (joined + (portRef O (instanceRef AS_000_DMA_1)) + (portRef I0 (instanceRef AS_000_DMA_1_i)) + )) + (net N_220_i (joined + (portRef O (instanceRef un1_rst_2_i_o2)) + (portRef I0 (instanceRef RW_000_DMA_0_i_a3_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2)) + (portRef I0 (instanceRef un1_rst_2_i_o2_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_1)) + )) (net BG_030_c_i (joined (portRef O (instanceRef BG_030_c_i)) (portRef I0 (instanceRef pos_clk_un9_bg_030)) )) - (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_i)) - (portRef I1 (instanceRef pos_clk_un9_bg_030)) - )) (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined (portRef O (instanceRef pos_clk_un9_bg_030)) (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) )) - (net UDS_000_INT_i (joined - (portRef O (instanceRef UDS_000_INT_i)) - (portRef I1 (instanceRef un1_UDS_000_INT)) - )) - (net un1_UDS_000_INT_0 (joined - (portRef O (instanceRef un1_UDS_000_INT)) - (portRef I0 (instanceRef un1_UDS_000_INT_i)) - )) - (net LDS_000_INT_i (joined - (portRef O (instanceRef LDS_000_INT_i)) - (portRef I1 (instanceRef un1_LDS_000_INT)) - )) - (net un1_LDS_000_INT_0 (joined - (portRef O (instanceRef un1_LDS_000_INT)) - (portRef I0 (instanceRef un1_LDS_000_INT_i)) - )) - (net N_23_i (joined - (portRef O (instanceRef N_23_i)) - (portRef I0 (instanceRef BG_000_1)) - )) - (net N_30_0 (joined - (portRef O (instanceRef BG_000_1)) - (portRef I0 (instanceRef BG_000_1_i)) - )) - (net N_20_i (joined - (portRef O (instanceRef N_20_i)) + (net N_17_i (joined + (portRef O (instanceRef N_17_i)) (portRef I0 (instanceRef UDS_000_INT_1)) )) - (net N_33_0 (joined + (net N_24_0 (joined (portRef O (instanceRef UDS_000_INT_1)) (portRef I0 (instanceRef UDS_000_INT_1_i)) )) - (net N_13_i (joined - (portRef O (instanceRef N_13_i)) + (net N_16_i (joined + (portRef O (instanceRef N_16_i)) + (portRef I0 (instanceRef BG_000_1)) + )) + (net N_25_0 (joined + (portRef O (instanceRef BG_000_1)) + (portRef I0 (instanceRef BG_000_1_i)) + )) + (net N_15_i (joined + (portRef O (instanceRef N_15_i)) (portRef I0 (instanceRef LDS_000_INT_1)) )) - (net N_40_0 (joined + (net N_26_0 (joined (portRef O (instanceRef LDS_000_INT_1)) (portRef I0 (instanceRef LDS_000_INT_1_i)) )) - (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined - (portRef O (instanceRef IPL_c_i_2)) - (portRef I0 (instanceRef IPL_D0_0_2)) + (net N_12_i (joined + (portRef O (instanceRef N_12_i)) + (portRef I0 (instanceRef RW_000_INT_1)) )) - (net N_51_0 (joined - (portRef O (instanceRef IPL_D0_0_2)) - (portRef I0 (instanceRef IPL_D0_0_i_2)) + (net N_28_0 (joined + (portRef O (instanceRef RW_000_INT_1)) + (portRef I0 (instanceRef RW_000_INT_1_i)) )) - (net N_26_i (joined - (portRef O (instanceRef N_26_i)) - (portRef I0 (instanceRef IPL_030_1_2)) + (net N_11_i (joined + (portRef O (instanceRef N_11_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1)) )) (net N_29_0 (joined - (portRef O (instanceRef IPL_030_1_2)) - (portRef I0 (instanceRef IPL_030_1_i_2)) + (portRef O (instanceRef AS_030_000_SYNC_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) + )) + (net N_5_i (joined + (portRef O (instanceRef N_5_i)) + (portRef I0 (instanceRef BGACK_030_INT_1)) + )) + (net N_30_0 (joined + (portRef O (instanceRef BGACK_030_INT_1)) + (portRef I0 (instanceRef BGACK_030_INT_1_i)) )) (net (rename A_c_i_0 "A_c_i[0]") (joined (portRef O (instanceRef A_c_i_0)) @@ -3039,592 +2672,438 @@ (portRef O (instanceRef pos_clk_un10_sm_amiga)) (portRef I0 (instanceRef LDS_000_INT_0_m)) )) - (net DS_000_ENABLE_0_sqmuxa_1_i (joined - (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa)) + (net un1_dsack1_i (joined + (portRef O (instanceRef un1_dsack1_0_o3_0)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2)) + (portRef OE (instanceRef DSACK1)) )) - (net un1_DS_000_ENABLE_0_sqmuxa_i (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_i_0)) - )) - (net N_157_i (joined - (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3)) - (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3_i)) - )) - (net N_160_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_4)) - )) - (net N_161_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_2)) - )) - (net N_162_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o3_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_i_6)) - )) - (net N_165_i (joined - (portRef O (instanceRef N_165_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_2)) - )) - (net N_140_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_2)) - (portRef D (instanceRef SM_AMIGA_2)) - )) - (net N_167_i (joined - (portRef O (instanceRef N_167_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_3)) - )) - (net N_166_i (joined - (portRef O (instanceRef N_166_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_3)) - )) - (net N_142_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_3)) - (portRef D (instanceRef SM_AMIGA_3)) - )) - (net N_168_i (joined - (portRef O (instanceRef N_168_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_4)) - )) - (net N_144_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_4)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_170_i (joined - (portRef O (instanceRef N_170_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_6)) - )) - (net N_148_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_6)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net N_164_i (joined - (portRef O (instanceRef N_164_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1_1)) - )) - (net N_138_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net N_102_i (joined - (portRef O (instanceRef N_102_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_o4_i_1)) - )) - (net N_264_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_o4_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o4_i_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_1_2)) - )) - (net N_79_i (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2)) - (portRef I0 (instanceRef AS_000_INT_0_i_a2_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2_i)) - )) - (net N_78_i (joined - (portRef O (instanceRef CLK_000_PE_0_o3_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a2_0_0)) - (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_0_o3)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_o3_i_o2)) - (portRef I0 (instanceRef CLK_000_PE_0_o3_i_o2_i)) - (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_1_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) - )) - (net N_119_i (joined - (portRef O (instanceRef N_119_i)) - (portRef I1 (instanceRef AS_000_INT_0_i)) - )) - (net N_118_i (joined - (portRef O (instanceRef N_118_i)) - (portRef I0 (instanceRef AS_000_INT_0_i)) - )) - (net N_268_i (joined - (portRef O (instanceRef AS_000_INT_0_i)) - (portRef D (instanceRef AS_000_INT)) - )) - (net N_255_i (joined - (portRef O (instanceRef N_255_i)) - (portRef I0 (instanceRef cpu_est_2_0_0_2)) - (portRef I0 (instanceRef cpu_est_2_i_0_1_3)) - )) - (net N_257_i (joined - (portRef O (instanceRef N_257_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_2)) - )) - (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_i_2)) - )) - (net N_258_i (joined - (portRef O (instanceRef N_258_i)) - (portRef I0 (instanceRef cpu_est_2_0_0_1)) - )) - (net N_259_i (joined - (portRef O (instanceRef N_259_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_1)) - )) - (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_i_1)) - )) - (net N_262_i (joined - (portRef O (instanceRef N_262_i)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0)) - )) - (net N_261_i (joined - (portRef O (instanceRef N_261_i)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0)) - )) - (net (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_i)) - )) - (net N_251_i (joined - (portRef O (instanceRef cpu_est_2_i_0_o2_3)) - (portRef I0 (instanceRef cpu_est_2_0_0_a3_2)) - (portRef I0 (instanceRef cpu_est_2_i_0_o2_i_3)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) - )) - (net N_252_0 (joined - (portRef O (instanceRef un5_e_i_o2)) - (portRef I0 (instanceRef un5_e_i_o2_i)) - )) - (net N_76_i (joined - (portRef O (instanceRef CLK_000_NE_0_o3_i_o2)) - (portRef I0 (instanceRef pos_clk_un13_bgack_030_int)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I1 (instanceRef pos_clk_un4_bgack_000)) - (portRef I0 (instanceRef RST_DLY_e2_i_a2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_a4_0_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_4)) - (portRef I0 (instanceRef CLK_000_NE_0_o3_i_o2_i)) - (portRef I0 (instanceRef RESET_OUT_2_0_a2_0_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) - )) - (net N_17_i (joined - (portRef O (instanceRef N_17_i)) - (portRef I0 (instanceRef VMA_INT_1)) - )) - (net N_36_0 (joined - (portRef O (instanceRef VMA_INT_1)) - (portRef I0 (instanceRef VMA_INT_1_i)) - )) - (net N_98_i (joined - (portRef O (instanceRef N_98_i)) - (portRef I1 (instanceRef pos_clk_un31_clk_000_ne)) - )) - (net (rename pos_clk_un31_clk_000_ne_i "pos_clk.un31_clk_000_ne_i") (joined - (portRef O (instanceRef pos_clk_un31_clk_000_ne)) - (portRef I0 (instanceRef pos_clk_un31_clk_000_ne_i_0)) - )) - (net N_228_i (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_132_0)) - (portRef I0 (instanceRef RST_DLY_e1_i_a2_1_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_a2_1)) - )) - (net N_121_i (joined - (portRef O (instanceRef N_121_i)) - (portRef I1 (instanceRef DSACK1_INT_0_i)) - )) - (net N_120_i (joined - (portRef O (instanceRef N_120_i)) - (portRef I0 (instanceRef DSACK1_INT_0_i)) - )) - (net N_269_i (joined - (portRef O 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(instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) - )) - (net N_112_i (joined - (portRef O (instanceRef N_112_i)) - (portRef I0 (instanceRef RST_DLY_e1_i_1)) - )) - (net N_113_i (joined - (portRef O (instanceRef N_113_i)) - (portRef I0 (instanceRef RST_DLY_e1_i_2)) - )) - (net N_114_i (joined - (portRef O (instanceRef N_114_i)) - (portRef I1 (instanceRef RST_DLY_e1_i_2)) - )) - (net N_266_i (joined - (portRef O (instanceRef RST_DLY_e1_i)) - (portRef D (instanceRef RST_DLY_1)) - )) - (net N_109_i (joined - (portRef O (instanceRef N_109_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_1)) - )) - (net N_108_i (joined - (portRef O (instanceRef N_108_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_1)) - )) - (net N_111_i (joined - (portRef O (instanceRef N_111_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_2)) - )) - (net N_265_2_0 (joined - (portRef O (instanceRef RST_DLY_e2_i_2)) - (portRef I0 (instanceRef RST_DLY_e2_i_2_i)) - (portRef I1 (instanceRef RST_DLY_e2_i)) - )) - (net N_265_i (joined - (portRef O (instanceRef RST_DLY_e2_i)) - (portRef D (instanceRef RST_DLY_2)) - )) - (net un1_as_000_i (joined - (portRef O (instanceRef un1_as_000_0)) + (net N_69_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0)) (portRef OE (instanceRef AS_000)) (portRef OE (instanceRef LDS_000)) (portRef OE (instanceRef RW_000)) (portRef OE (instanceRef UDS_000)) )) - (net VPA_c_i (joined - (portRef O (instanceRef VPA_c_i)) - (portRef I1 (instanceRef VPA_D_0)) + (net N_163_i (joined + (portRef O (instanceRef N_163_i)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i)) )) - (net N_52_0 (joined - (portRef O (instanceRef VPA_D_0)) - (portRef I0 (instanceRef VPA_D_0_i)) + (net N_244_0 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_i)) )) - (net DTACK_c_i (joined - (portRef O (instanceRef DTACK_c_i)) - (portRef I0 (instanceRef DTACK_D0_0)) + (net N_164_i (joined + (portRef O (instanceRef N_164_i)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0)) )) - (net N_48_0 (joined - (portRef O (instanceRef DTACK_D0_0)) - (portRef I0 (instanceRef DTACK_D0_0_i)) - )) - (net un3_ahigh_i (joined - (portRef O (instanceRef un3_ahigh)) - (portRef OE (instanceRef AHIGH_24)) - (portRef OE (instanceRef AHIGH_25)) - (portRef OE (instanceRef AHIGH_26)) - (portRef OE (instanceRef AHIGH_27)) - (portRef OE (instanceRef AHIGH_28)) - (portRef OE (instanceRef AHIGH_29)) - (portRef OE (instanceRef AHIGH_30)) - (portRef OE (instanceRef AHIGH_31)) - )) - (net (rename pos_clk_un4_bgack_000_i "pos_clk.un4_bgack_000_i") (joined - (portRef O (instanceRef pos_clk_un4_bgack_000_i)) - (portRef I1 (instanceRef pos_clk_un6_bgack_000)) - )) - (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_i)) - )) - (net N_7_i (joined - (portRef O (instanceRef N_7_i)) - (portRef I0 (instanceRef BGACK_030_INT_1)) - )) - (net N_41_0 (joined - (portRef O (instanceRef BGACK_030_INT_1)) - (portRef I0 (instanceRef BGACK_030_INT_1_i)) - )) - (net (rename pos_clk_un1_bgack_030_int_0 "pos_clk.un1_bgack_030_int_0") (joined - (portRef O (instanceRef pos_clk_un1_bgack_030_int)) - (portRef I0 (instanceRef pos_clk_un1_bgack_030_int_i)) - )) - (net (rename pos_clk_un12_clk_out_int_0 "pos_clk.un12_clk_out_int_0") (joined - (portRef O (instanceRef G_121)) - (portRef I0 (instanceRef G_121_i)) - )) - (net (rename pos_clk_un3_0 "pos_clk.un3_0") (joined - (portRef O (instanceRef G_116)) - (portRef I0 (instanceRef G_116_i)) - )) - (net (rename pos_clk_un15_bgack_030_int_i "pos_clk.un15_bgack_030_int_i") (joined - (portRef O (instanceRef G_111)) - (portRef I1 (instanceRef pos_clk_un1_bgack_030_int)) - (portRef I0 (instanceRef G_111_i)) - )) - (net N_3_i (joined - (portRef O (instanceRef N_3_i)) - (portRef I0 (instanceRef DS_000_DMA_1)) - )) - (net N_43_0 (joined - (portRef O (instanceRef DS_000_DMA_1)) - (portRef I0 (instanceRef DS_000_DMA_1_i)) - )) - (net N_4_i (joined - (portRef O (instanceRef N_4_i)) - (portRef I0 (instanceRef AS_000_DMA_1)) - )) - (net N_42_0 (joined - (portRef O (instanceRef AS_000_DMA_1)) - (portRef I0 (instanceRef AS_000_DMA_1_i)) - )) - (net un6_amiga_bus_data_dir_i (joined - (portRef O (instanceRef un6_amiga_bus_data_dir_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv)) - )) - (net un12_amiga_bus_data_dir_m_i (joined - (portRef O (instanceRef un12_amiga_bus_data_dir_m_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv)) - )) - (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_i)) - )) - (net N_22_i (joined - (portRef O (instanceRef N_22_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - )) - (net N_31_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) - )) - (net N_21_i (joined - (portRef O (instanceRef N_21_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - )) - (net N_32_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) - )) - (net N_19_i (joined - (portRef O (instanceRef N_19_i)) - (portRef I0 (instanceRef A0_DMA_1)) - )) - (net N_34_0 (joined - (portRef O (instanceRef A0_DMA_1)) - (portRef I0 (instanceRef A0_DMA_1_i)) - )) - (net N_18_i (joined - (portRef O (instanceRef N_18_i)) - (portRef I0 (instanceRef RW_000_DMA_1)) - )) - (net N_35_0 (joined - (portRef O (instanceRef RW_000_DMA_1)) - (portRef I0 (instanceRef RW_000_DMA_1_i)) - )) - (net (rename pos_clk_un5_bgack_030_int_d_i "pos_clk.un5_bgack_030_int_d_i") (joined - (portRef O (instanceRef pos_clk_un5_bgack_030_int_d)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa)) - (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0)) - )) - (net (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_0 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_0") (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i)) - )) - (net (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_0 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_0") (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i)) - )) - (net (rename pos_clk_RW_000_DMA_3_0 "pos_clk.RW_000_DMA_3_0") (joined - (portRef O (instanceRef pos_clk_RW_000_DMA_3)) - (portRef I0 (instanceRef pos_clk_RW_000_DMA_3_i)) - )) - (net UDS_000_c_i (joined - (portRef O (instanceRef UDS_000_c_i)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) - )) - (net LDS_000_c_i (joined - (portRef O (instanceRef LDS_000_c_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) - )) - (net N_86_i (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) - )) - (net N_129_i (joined - (portRef O (instanceRef N_129_i)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0)) - )) - (net N_130_i (joined - (portRef O (instanceRef N_130_i)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0)) + (net N_165_i (joined + (portRef O (instanceRef N_165_i)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0)) )) (net un11_amiga_bus_enable_high_i (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0)) + (portRef O (instanceRef un11_amiga_bus_enable_high_0_0)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) )) - (net N_117_i (joined - (portRef O (instanceRef N_117_i)) - (portRef I0 (instanceRef AMIGA_DS_0_0)) + (net un10_ciin_i (joined + (portRef O (instanceRef un10_ciin_i)) + (portRef I1 (instanceRef un13_ciin_i_0_0)) )) - (net N_46_0 (joined - (portRef O (instanceRef AMIGA_DS_0_0)) - (portRef I0 (instanceRef AMIGA_DS_0_0_i)) + (net N_60_0 (joined + (portRef O (instanceRef un13_ciin_i_0_0)) + (portRef I0 (instanceRef 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(net N_91_0 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_i)) - )) - (net N_159_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_o4_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5)) - )) - (net N_85_i (joined - (portRef O (instanceRef pos_clk_un15_clk_000_d_i_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_o3_6)) - (portRef I0 (instanceRef pos_clk_un15_clk_000_d_i_i_o2_i)) - )) - (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_i)) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_i)) )) (net RW_c_i (joined (portRef O (instanceRef RW_c_i)) - (portRef I1 (instanceRef pos_clk_RW_000_INT_5)) + (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0_0)) )) (net (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_i)) + (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0_i)) + )) + (net N_168_i (joined + (portRef O (instanceRef N_168_i)) + (portRef I1 (instanceRef DSACK1_INT_0_i_0)) + )) + (net N_167_i (joined + (portRef O (instanceRef N_167_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i_0)) + )) + (net N_206_i (joined + (portRef O (instanceRef DSACK1_INT_0_i_0)) + (portRef D (instanceRef DSACK1_INT)) + )) + (net N_170_i (joined + (portRef O (instanceRef N_170_i)) + (portRef I1 (instanceRef AS_000_INT_0_i_0)) + )) + (net N_169_i (joined + (portRef O (instanceRef N_169_i)) + (portRef I0 (instanceRef AS_000_INT_0_i_0)) + )) + (net N_48_i (joined + (portRef O (instanceRef AS_000_INT_0_i_0)) + (portRef D (instanceRef AS_000_INT)) + )) + (net N_38_0 (joined + (portRef O (instanceRef AS_030_D0_0_0_0)) + (portRef I0 (instanceRef AS_030_D0_0_0_0_i)) + )) + (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) + )) + (net N_282_0 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_i)) + (portRef I1 (instanceRef un21_berr_0_a3_0_a2)) + (portRef I1 (instanceRef un21_fpu_cs_0_a3_0_a2)) )) (net (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (joined (portRef O (instanceRef CLK_000_D_i_3)) - (portRef I1 (instanceRef pos_clk_un15_clk_000_d_i_i_o2_2)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) )) - (net N_25_i (joined - (portRef O (instanceRef N_25_i)) + (net N_96_0 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) + )) + (net N_129_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I0 (instanceRef DSACK1_INT_0_i_0_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0)) + )) + (net N_268_i (joined + (portRef O (instanceRef N_268_i)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + )) + (net N_246_i (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) + )) + (net N_132_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) + )) + (net N_113_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_142_i (joined + (portRef O (instanceRef N_142_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) + )) + (net N_141_i (joined + (portRef O (instanceRef N_141_i)) + (portRef I1 (instanceRef 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(portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) + )) + (net N_203_i (joined + (portRef O (instanceRef N_203_i)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2)) + )) + (net un1_DS_000_ENABLE_0_sqmuxa_0 (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2_i)) + )) + (net N_201_i (joined + (portRef O (instanceRef N_201_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) + )) + (net N_202_i (joined + (portRef O (instanceRef N_202_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) + )) + (net N_98_i (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) + )) + (net N_93_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) + (portRef I0 (instanceRef AS_000_INT_0_i_0_a2_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i)) + )) + (net N_82_i (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I0 (instanceRef un5_e_0_0_a2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) + )) + (net N_80_i (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) + )) + (net N_72_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) + )) + (net N_68_i (joined + (portRef O (instanceRef N_130_i_0_o2_i_o2)) + (portRef I0 (instanceRef cpu_est_0_0_0_a2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef N_130_i_0_o2_i_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) + (portRef I0 (instanceRef G_90_1)) + )) + (net N_59_i (joined + (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_i)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_i_i)) + )) + (net N_190_i (joined + (portRef O (instanceRef N_190_i)) + (portRef I0 (instanceRef cpu_est_0_0_0_0)) + )) + (net N_191_i (joined + (portRef O (instanceRef N_191_i)) + (portRef I1 (instanceRef cpu_est_0_0_0_0)) + )) + (net N_200_i (joined + (portRef O (instanceRef cpu_est_0_0_0_0)) + (portRef D (instanceRef cpu_est_0)) + )) + (net N_267_i (joined + (portRef O (instanceRef N_267_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + )) + (net N_127_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_0)) + (portRef D (instanceRef SM_AMIGA_i_7)) + )) + (net N_266_i (joined + (portRef O (instanceRef N_266_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) + )) + (net N_123_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_6)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net N_186_i (joined + (portRef O (instanceRef N_186_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) + )) + (net N_121_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_185_i (joined + (portRef O (instanceRef N_185_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) + )) + (net N_119_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net N_183_i (joined + (portRef O (instanceRef N_183_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + )) + (net N_184_i (joined + (portRef O (instanceRef N_184_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + )) + (net N_117_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_3)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net N_182_i (joined + (portRef O (instanceRef N_182_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) + )) + (net N_115_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2)) + (portRef D (instanceRef SM_AMIGA_2)) + )) + (net N_181_i (joined + (portRef O (instanceRef N_181_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + )) + (net N_111_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_0)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_260_i (joined + (portRef O (instanceRef N_260_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + )) + (net N_259_i (joined + (portRef O (instanceRef N_259_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) + )) + (net N_63_0 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + )) + (net N_155_i (joined + (portRef O (instanceRef N_155_i)) + (portRef I0 (instanceRef un5_e_0_0)) + )) + (net N_162_i (joined + (portRef O (instanceRef N_162_i)) + (portRef I1 (instanceRef un5_e_0_0)) + )) + (net un5_e_0 (joined + (portRef O (instanceRef un5_e_0_0)) + (portRef I0 (instanceRef un5_e_0_0_i)) + )) + (net N_154_i (joined + (portRef O (instanceRef N_154_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_3)) + )) + (net (rename cpu_est_2_0_3 "cpu_est_2_0[3]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_3)) + )) + (net N_149_i (joined + (portRef O (instanceRef N_149_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_2)) + )) + (net N_208_i (joined + (portRef O (instanceRef N_208_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_2)) + )) + (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2)) + )) + (net N_147_i (joined + (portRef O (instanceRef N_147_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_1)) + )) + (net N_148_i (joined + (portRef O (instanceRef N_148_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_1)) + )) + (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1)) + )) + (net N_146_i (joined + (portRef O (instanceRef N_146_i)) + (portRef I0 (instanceRef A0_DMA_0_0_0)) + )) + (net N_36_0 (joined + (portRef O (instanceRef A0_DMA_0_0_0)) + (portRef I0 (instanceRef A0_DMA_0_0_0_i)) + )) + (net N_145_i (joined + (portRef O (instanceRef N_145_i)) + (portRef I0 (instanceRef AMIGA_DS_0_0_0)) + )) + (net N_35_0 (joined + (portRef O (instanceRef AMIGA_DS_0_0_0)) + (portRef I0 (instanceRef AMIGA_DS_0_0_0_i)) + )) + (net N_143_i (joined + (portRef O (instanceRef N_143_i)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0)) + )) + (net N_144_i (joined + (portRef O (instanceRef N_144_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0)) + )) + (net (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) + )) + (net N_20_i (joined + (portRef O (instanceRef N_20_i)) + (portRef I0 (instanceRef IPL_030_1_2)) + )) + (net N_23_0 (joined + (portRef O (instanceRef IPL_030_1_2)) + (portRef I0 (instanceRef IPL_030_1_i_2)) + )) + (net N_19_i (joined + (portRef O (instanceRef N_19_i)) (portRef I0 (instanceRef IPL_030_1_1)) )) - (net N_28_0 (joined + (net N_22_0 (joined (portRef O (instanceRef IPL_030_1_1)) (portRef I0 (instanceRef IPL_030_1_i_1)) )) - (net N_24_i (joined - (portRef O (instanceRef N_24_i)) + (net N_18_i (joined + (portRef O (instanceRef N_18_i)) (portRef I0 (instanceRef IPL_030_1_0)) )) - (net N_27_0 (joined + (net N_21_0 (joined (portRef O (instanceRef IPL_030_1_0)) (portRef I0 (instanceRef IPL_030_1_i_0)) )) + (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined + (portRef O (instanceRef IPL_c_i_2)) + (portRef I0 (instanceRef IPL_D0_0_2)) + )) + (net N_43_0 (joined + (portRef O (instanceRef IPL_D0_0_2)) + (portRef I0 (instanceRef IPL_D0_0_i_2)) + )) (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined (portRef O (instanceRef IPL_c_i_1)) (portRef I0 (instanceRef IPL_D0_0_1)) )) - (net N_50_0 (joined + (net N_42_0 (joined (portRef O (instanceRef IPL_D0_0_1)) (portRef I0 (instanceRef IPL_D0_0_i_1)) )) @@ -3632,285 +3111,293 @@ (portRef O (instanceRef IPL_c_i_0)) (portRef I0 (instanceRef IPL_D0_0_0)) )) - (net N_49_0 (joined + (net N_41_0 (joined (portRef O (instanceRef IPL_D0_0_0)) (portRef I0 (instanceRef IPL_D0_0_i_0)) )) - (net N_14_i (joined - (portRef O (instanceRef N_14_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_1)) + (net DTACK_c_i (joined + (portRef O (instanceRef DTACK_c_i)) + (portRef I0 (instanceRef DTACK_D0_0)) )) - (net N_39_0 (joined - (portRef O (instanceRef AS_030_000_SYNC_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) + (net N_45_0 (joined + (portRef O (instanceRef DTACK_D0_0)) + (portRef I0 (instanceRef DTACK_D0_0_i)) )) - (net N_15_i (joined - (portRef O (instanceRef N_15_i)) - (portRef I0 (instanceRef RW_000_INT_1)) + (net VPA_c_i (joined + (portRef O (instanceRef VPA_c_i)) + (portRef I1 (instanceRef VPA_D_0)) )) - (net N_38_0 (joined - (portRef O (instanceRef RW_000_INT_1)) - (portRef I0 (instanceRef RW_000_INT_1_i)) + (net N_44_0 (joined + (portRef O (instanceRef VPA_D_0)) + (portRef I0 (instanceRef VPA_D_0_i)) )) - (net N_91_0_1 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2_3)) + (net N_13_i (joined + (portRef O (instanceRef N_13_i)) + (portRef I0 (instanceRef VMA_INT_1)) )) - (net N_91_0_2 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_2)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_o2_3)) + (net N_27_0 (joined + (portRef O (instanceRef VMA_INT_1)) + (portRef I0 (instanceRef VMA_INT_1_i)) )) - (net N_91_0_3 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_o2_3)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_o2)) + (net LDS_000_INT_i (joined + (portRef O (instanceRef LDS_000_INT_i)) + (portRef I1 (instanceRef un1_LDS_000_INT)) )) - (net N_265_i_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_1)) - (portRef I0 (instanceRef RST_DLY_e2_i)) + (net un1_LDS_000_INT_0 (joined + (portRef O (instanceRef un1_LDS_000_INT)) + (portRef I0 (instanceRef un1_LDS_000_INT_i)) )) - (net N_266_i_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_1)) - (portRef I0 (instanceRef RST_DLY_e1_i)) + (net UDS_000_INT_i (joined + (portRef O (instanceRef UDS_000_INT_i)) + (portRef I1 (instanceRef un1_UDS_000_INT)) )) - (net N_266_i_2 (joined - (portRef O (instanceRef RST_DLY_e1_i_2)) - (portRef I1 (instanceRef RST_DLY_e1_i)) + (net un1_UDS_000_INT_0 (joined + (portRef O (instanceRef un1_UDS_000_INT)) + (portRef I0 (instanceRef un1_UDS_000_INT_i)) )) - (net N_138_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_1)) + (net N_96_0_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) )) - (net N_148_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_6)) + (net N_96_0_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) )) - (net N_144_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_4)) + (net N_282_0_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_4)) )) - (net N_142_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_3)) + (net N_282_0_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_4)) )) - (net N_140_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_2)) + (net N_282_0_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_3)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2)) + )) + (net N_282_0_4 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_4)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2)) )) (net (rename pos_clk_un10_sm_amiga_i_1 "pos_clk.un10_sm_amiga_i_1") (joined (portRef O (instanceRef pos_clk_un10_sm_amiga_1)) (portRef I0 (instanceRef pos_clk_un10_sm_amiga)) )) - (net N_85_i_1 (joined - (portRef O (instanceRef pos_clk_un15_clk_000_d_i_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un15_clk_000_d_i_i_o2)) - )) - (net N_85_i_2 (joined - (portRef O (instanceRef pos_clk_un15_clk_000_d_i_i_o2_2)) - (portRef I1 (instanceRef pos_clk_un15_clk_000_d_i_i_o2)) - )) - (net N_277_1 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_4)) - )) - (net N_277_2 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_4)) - )) - (net N_277_3 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_3)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0_5)) - )) - (net N_277_4 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_4)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d0_i_a2_0)) - )) - (net N_277_5 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d0_i_a2_0_5)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d0_i_a2_0)) - )) (net un10_ciin_1 (joined - (portRef O (instanceRef un10_ciin_1)) - (portRef I0 (instanceRef un10_ciin_7)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_1)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_7)) )) (net un10_ciin_2 (joined - (portRef O (instanceRef un10_ciin_2)) - (portRef I1 (instanceRef un10_ciin_7)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_2)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_7)) )) (net un10_ciin_3 (joined - (portRef O (instanceRef un10_ciin_3)) - (portRef I0 (instanceRef un10_ciin_8)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_3)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_8)) )) (net un10_ciin_4 (joined - (portRef O (instanceRef un10_ciin_4)) - (portRef I1 (instanceRef un10_ciin_8)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_4)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_8)) )) (net un10_ciin_5 (joined - (portRef O (instanceRef un10_ciin_5)) - (portRef I0 (instanceRef un10_ciin_9)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_5)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_9)) )) (net un10_ciin_6 (joined - (portRef O (instanceRef un10_ciin_6)) - (portRef I1 (instanceRef un10_ciin_9)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_6)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_9)) )) (net un10_ciin_7 (joined - (portRef O (instanceRef un10_ciin_7)) - (portRef I0 (instanceRef un10_ciin_10)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_7)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_10)) )) (net un10_ciin_8 (joined - (portRef O (instanceRef un10_ciin_8)) - (portRef I1 (instanceRef un10_ciin_10)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_8)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2_10)) )) (net un10_ciin_9 (joined - (portRef O (instanceRef un10_ciin_9)) - (portRef I0 (instanceRef un10_ciin_11)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_9)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2_11)) )) (net un10_ciin_10 (joined - (portRef O (instanceRef un10_ciin_10)) - (portRef I0 (instanceRef un10_ciin)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_10)) + (portRef I0 (instanceRef un13_ciin_i_0_0_a2)) )) (net un10_ciin_11 (joined - (portRef O (instanceRef un10_ciin_11)) - (portRef I1 (instanceRef un10_ciin)) + (portRef O (instanceRef un13_ciin_i_0_0_a2_11)) + (portRef I1 (instanceRef un13_ciin_i_0_0_a2)) )) - (net un6_amiga_bus_data_dir_1 (joined - (portRef O (instanceRef un6_amiga_bus_data_dir_1)) - (portRef I0 (instanceRef un6_amiga_bus_data_dir)) + (net N_201_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) )) - (net un6_amiga_bus_data_dir_2 (joined - (portRef O (instanceRef un6_amiga_bus_data_dir_2)) - (portRef I1 (instanceRef un6_amiga_bus_data_dir)) + (net N_201_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) )) - (net (rename pos_clk_as_000_dma6_1 "pos_clk.as_000_dma6_1") (joined - (portRef O (instanceRef pos_clk_as_000_dma6_1)) - (portRef I0 (instanceRef pos_clk_as_000_dma6)) + (net N_131_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) )) - (net (rename pos_clk_as_000_dma6_2 "pos_clk.as_000_dma6_2") (joined - (portRef O (instanceRef pos_clk_as_000_dma6_2)) - (portRef I1 (instanceRef pos_clk_as_000_dma6)) + (net N_134_0_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) )) - (net DS_000_DMA_1_sqmuxa_1 (joined - (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1)) - (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa)) + (net N_113_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1)) )) - (net (rename pos_clk_un4_rw_000_1 "pos_clk.un4_rw_000_1") (joined - (portRef O (instanceRef pos_clk_un4_rw_000_1)) - (portRef I0 (instanceRef pos_clk_un4_rw_000)) + (net N_113_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1)) )) - (net (rename pos_clk_un4_rw_000_2 "pos_clk.un4_rw_000_2") (joined - (portRef O (instanceRef pos_clk_un4_rw_000_2)) - (portRef I1 (instanceRef pos_clk_un4_rw_000)) + (net N_144_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) )) - (net (rename pos_clk_un13_clk_out_int_1 "pos_clk.un13_clk_out_int_1") (joined - (portRef O (instanceRef pos_clk_un13_clk_out_int_1)) - (portRef I0 (instanceRef pos_clk_un13_clk_out_int)) + (net N_144_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) )) - (net N_125_1 (joined - (portRef O (instanceRef RESET_OUT_2_0_a2_0_1)) - (portRef I0 (instanceRef RESET_OUT_2_0_a2_0)) + (net N_143_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) )) - (net N_116_1 (joined - (portRef O (instanceRef RST_DLY_e0_i_a2_0_1)) - (portRef I0 (instanceRef RST_DLY_e0_i_a2_0)) + (net N_143_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) )) - (net (rename pos_clk_un29_clk_000_ne_1_1 "pos_clk.un29_clk_000_ne_1_1") (joined - (portRef O (instanceRef pos_clk_un29_clk_000_ne_1_1)) - (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_1_3)) + (net N_163_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_3)) )) - (net (rename pos_clk_un29_clk_000_ne_1_2 "pos_clk.un29_clk_000_ne_1_2") (joined - (portRef O (instanceRef pos_clk_un29_clk_000_ne_1_2)) - (portRef I1 (instanceRef pos_clk_un29_clk_000_ne_1_3)) + (net N_163_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_3)) )) - (net (rename pos_clk_un29_clk_000_ne_1_3 "pos_clk.un29_clk_000_ne_1_3") (joined - (portRef O (instanceRef pos_clk_un29_clk_000_ne_1_3)) - (portRef I0 (instanceRef pos_clk_un29_clk_000_ne_1)) - )) - (net N_261_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3)) - )) - (net N_261_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3)) - )) - (net N_262_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) - )) - (net N_262_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) - )) - (net DS_000_ENABLE_0_sqmuxa_1_1 (joined - (portRef O (instanceRef DS_000_ENABLE_0_sqmuxa_1_1)) - (portRef I0 (instanceRef DS_000_ENABLE_0_sqmuxa_1)) - )) - (net N_259_1 (joined - (portRef O (instanceRef cpu_est_2_0_0_a3_0_1_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1)) - )) - (net N_250_i_1 (joined - (portRef O (instanceRef un5_e_i_1)) - (portRef I0 (instanceRef un5_e_i)) - )) - (net N_189_i_1 (joined - (portRef O (instanceRef cpu_est_2_i_0_1_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_3)) - )) - (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2)) - )) - (net N_108_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_a2_1)) - (portRef I0 (instanceRef RST_DLY_e2_i_a2)) - )) - (net N_114_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_a2_1_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_a2_1)) - )) - (net un21_berr_1 (joined - (portRef O (instanceRef un21_berr_0_a2_1)) - (portRef I0 (instanceRef un21_berr_0_a2)) + (net N_163_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2_3)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2)) )) (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2)) + (portRef O (instanceRef un21_fpu_cs_0_a3_0_a2_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a3_0_a2)) )) - (net N_130_1 (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_a2_0_1)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_a2_0)) + (net un21_berr_1_0 (joined + (portRef O (instanceRef un21_berr_0_a3_0_a2_1_0)) + (portRef I0 (instanceRef un21_berr_0_a3_0_a2)) )) - (net N_136_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0)) + (net (rename pos_clk_CYCLE_DMA_5_1_1 "pos_clk.CYCLE_DMA_5_1[1]") (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1)) )) - (net N_152_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0)) + (net N_199_1 (joined + (portRef O (instanceRef G_90_1)) + (portRef I0 (instanceRef G_90)) )) - (net N_146_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_5)) + (net AS_000_DMA_1_sqmuxa_1 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_1)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa)) )) - (net N_267_i_1 (joined - (portRef O (instanceRef RST_DLY_e0_i_1)) - (portRef I0 (instanceRef RST_DLY_e0_i)) + (net N_140_1 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_a2)) + )) + (net N_66_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + )) + (net N_66_i_2 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + )) + (net N_205_i_1 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_1)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0)) + )) + (net N_205_i_2 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_2)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0)) + )) + (net N_180_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) + )) + (net N_180_2 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) + )) + (net N_59_i_1 (joined + (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_i_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_i)) + )) + (net N_127_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) + )) + (net N_123_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_6)) + )) + (net N_121_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5)) + )) + (net N_119_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4)) + )) + (net N_117_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) + )) + (net N_115_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2)) + )) + (net N_111_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_0)) + )) + (net N_165_1 (joined + (portRef O (instanceRef un11_amiga_bus_enable_high_0_0_a2_0_1)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0)) + )) + (net N_162_1 (joined + (portRef O (instanceRef un5_e_0_0_a2_0_1)) + (portRef I0 (instanceRef un5_e_0_0_a2_0)) + )) + (net N_148_1 (joined + (portRef O (instanceRef cpu_est_2_0_0_a2_0_1_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_1)) )) (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined - (portRef O (instanceRef G_125_1)) - (portRef I0 (instanceRef G_125)) + (portRef O (instanceRef G_108_1)) + (portRef I0 (instanceRef G_108)) )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) )) (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined (portRef O (instanceRef UDS_000_INT_0_r)) @@ -3924,6 +3411,18 @@ (portRef O (instanceRef UDS_000_INT_0_n)) (portRef I1 (instanceRef UDS_000_INT_0_p)) )) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) + )) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) + )) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined (portRef O (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef LDS_000_INT_0_n)) @@ -3936,41 +3435,53 @@ (portRef O (instanceRef LDS_000_INT_0_n)) (portRef I1 (instanceRef LDS_000_INT_0_p)) )) - (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined - (portRef O (instanceRef DS_000_ENABLE_0_r)) - (portRef I1 (instanceRef DS_000_ENABLE_0_n)) + (net (rename AS_030_D1_0_un3 "AS_030_D1_0.un3") (joined + (portRef O (instanceRef AS_030_D1_0_r)) + (portRef I1 (instanceRef AS_030_D1_0_n)) )) - (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined - (portRef O (instanceRef DS_000_ENABLE_0_m)) - (portRef I0 (instanceRef DS_000_ENABLE_0_p)) + (net (rename AS_030_D1_0_un1 "AS_030_D1_0.un1") (joined + (portRef O (instanceRef AS_030_D1_0_m)) + (portRef I0 (instanceRef AS_030_D1_0_p)) )) - (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined - (portRef O (instanceRef DS_000_ENABLE_0_n)) - (portRef I1 (instanceRef DS_000_ENABLE_0_p)) + (net (rename AS_030_D1_0_un0 "AS_030_D1_0.un0") (joined + (portRef O (instanceRef AS_030_D1_0_n)) + (portRef I1 (instanceRef AS_030_D1_0_p)) )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) + )) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined (portRef O (instanceRef cpu_est_0_1__r)) @@ -4008,126 +3519,6 @@ (portRef O (instanceRef cpu_est_0_3__n)) (portRef I1 (instanceRef cpu_est_0_3__p)) )) - (net (rename pos_clk_un31_clk_000_ne_1_i_m2_un3 "pos_clk.un31_clk_000_ne_1_i_m2.un3") (joined - (portRef O (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_r)) - (portRef I1 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_n)) - )) - (net (rename pos_clk_un31_clk_000_ne_1_i_m2_un1 "pos_clk.un31_clk_000_ne_1_i_m2.un1") (joined - (portRef O (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_m)) - (portRef I0 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_p)) - )) - (net (rename pos_clk_un31_clk_000_ne_1_i_m2_un0 "pos_clk.un31_clk_000_ne_1_i_m2.un0") (joined - (portRef O (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_n)) - (portRef I1 (instanceRef pos_clk_un31_clk_000_ne_1_i_m2_p)) - )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) - )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) - )) - (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined - (portRef O (instanceRef DS_000_DMA_0_r)) - (portRef I1 (instanceRef DS_000_DMA_0_n)) - )) - (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined - (portRef O (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_p)) - )) - (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined - (portRef O (instanceRef DS_000_DMA_0_n)) - (portRef I1 (instanceRef DS_000_DMA_0_p)) - )) - (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined - (portRef O (instanceRef AS_000_DMA_0_r)) - (portRef I1 (instanceRef AS_000_DMA_0_n)) - )) - (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined - (portRef O (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_p)) - )) - (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined - (portRef O (instanceRef AS_000_DMA_0_n)) - (portRef I1 (instanceRef AS_000_DMA_0_p)) - )) - (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_1__r)) - (portRef I1 (instanceRef SIZE_DMA_0_1__n)) - )) - (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__p)) - )) - (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_1__n)) - (portRef I1 (instanceRef SIZE_DMA_0_1__p)) - )) - (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_0__r)) - (portRef I1 (instanceRef SIZE_DMA_0_0__n)) - )) - (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_0_0__p)) - )) - (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_0__n)) - (portRef I1 (instanceRef SIZE_DMA_0_0__p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - )) - (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined - (portRef O (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef A0_DMA_0_n)) - )) - (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined - (portRef O (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_p)) - )) - (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined - (portRef O (instanceRef A0_DMA_0_n)) - (portRef I1 (instanceRef A0_DMA_0_p)) - )) - (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined - (portRef O (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef RW_000_DMA_0_n)) - )) - (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined - (portRef O (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_p)) - )) - (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined - (portRef O (instanceRef RW_000_DMA_0_n)) - (portRef I1 (instanceRef RW_000_DMA_0_p)) - )) (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined (portRef O (instanceRef IPL_030_0_0__r)) (portRef I1 (instanceRef IPL_030_0_0__n)) @@ -4152,29 +3543,41 @@ (portRef O (instanceRef IPL_030_0_1__n)) (portRef I1 (instanceRef IPL_030_0_1__p)) )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) )) - (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined - (portRef O (instanceRef RW_000_INT_0_r)) - (portRef I1 (instanceRef RW_000_INT_0_n)) + (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined + (portRef O (instanceRef DS_000_ENABLE_0_r)) + (portRef I1 (instanceRef DS_000_ENABLE_0_n)) )) - (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined - (portRef O (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_p)) + (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined + (portRef O (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_p)) )) - (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined - (portRef O (instanceRef RW_000_INT_0_n)) - (portRef I1 (instanceRef RW_000_INT_0_p)) + (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined + (portRef O (instanceRef DS_000_ENABLE_0_n)) + (portRef I1 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) )) ) (property orig_inst_of (string "BUS68030")) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index aa37a1c..f631b3a 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {7132381321} onehot +fsm_encoding {7133381331} onehot -fsm_state_encoding {7132381321} idle_p {00000000} +fsm_state_encoding {7133381331} idle_p {00000000} -fsm_state_encoding {7132381321} idle_n {00000011} +fsm_state_encoding {7133381331} idle_n {00000011} -fsm_state_encoding {7132381321} as_set_p {00000101} +fsm_state_encoding {7133381331} as_set_p {00000101} -fsm_state_encoding {7132381321} as_set_n {00001001} +fsm_state_encoding {7133381331} as_set_n {00001001} -fsm_state_encoding {7132381321} sample_dtack_p {00010001} +fsm_state_encoding {7133381331} sample_dtack_p {00010001} -fsm_state_encoding {7132381321} data_fetch_n {00100001} +fsm_state_encoding {7133381331} data_fetch_n {00100001} -fsm_state_encoding {7132381321} data_fetch_p {01000001} +fsm_state_encoding {7133381331} data_fetch_p {01000001} -fsm_state_encoding {7132381321} end_cycle_n {10000001} +fsm_state_encoding {7133381331} end_cycle_n {10000001} -fsm_registers {7132381321} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} +fsm_registers {7133381331} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 3c00fbe..8fee42f 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj -#-- Written on Thu Dec 29 16:01:42 2016 +#-- Written on Sat Dec 30 00:43:20 2017 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index bd62af7..cc82f41 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -187,7 +187,7 @@ NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\l\NH\oN\sEN8sINCOEN \#\ndUjj -0\H\o0LEk\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj +POR3DMCNk#b_0.Cb_l0HC3RjjUcn(;6j RNP3CODNbMk_C#0b04_HRlCj43j66n.jN; P#R30Dl0H0#0HRlCjj3jjjjj;P NRHFsoM_H#F0_VAR"zU1nj"dj;P @@ -201,8 +201,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#4RU4 -.;N3PR#_$MD HMC8sHR6"{jBw.7- qgcg6-(cg g-q 7j-(A476g(dd}Bc"N; +RNP3M#$_lMkOsEN#gRnn +j;N3PR#_$MD HMC8sHR "{j((dd-Uc.Bcw-7c w(-g6Aq-nBd(w.cAj}Ug"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -316,12 +316,10 @@ HCR38NHVs$sNMCNlRb'HDd_jj 4;N3HRs_0DFosHMCNlR1"7q4Bi"N; H#R3DsbFHHo8sHR"M0Fk"N; HbR3FNs0Ds8HRk"F0 -";L@R@(c:c:c4:c::67BaqiaR7q;Bi +";H@R@(c:c:c4:c::67BaqiaR7q;Bi RNH3Ds0_HFsolMNC7R"aiqB"N; -H$R#Ms_0HN#004CR;b -oRq7aB -i;N#bR$bM_FVs0D#NoR -U;F@R@(6:c:c4:6::cqBe R qeBN; +HFR3s8HoH'sRHkMF0 +';F@R@(6:c:c4:6::cqBe R qeBN; HsR30FD_sMHoNRlC" qeB ";F@R@(n:c:c4:n::4 ;R RNH3Ds0_HFsolMNC R""H; @@ -354,79 +352,85 @@ F@:@(64U:::6UcQ:BQBhRQ;Qh RNH3Ds0_HFsolMNCBR"Q"Qh;L oR4qr9N; LLR3HF0bsH08s;R4 -RoMk_M4NolHNk_L#M_CNCLD_IDF;M -NRN3#PMC_CV0_D#No46R.no; -MMRk(#_N_jjd;M +RoMk_M6CN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRMN4_lNHo_#Lk_NCML_DCD;FI +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRdkM__N#j;dj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4kM_1z7_jjj_aQh;M NRN3#PMC_CV0_D#No46R.no; MMRk47_p1j_jjh_QaN; M#R3N_PCM_C0VoDN#.4R6 -n;okMRMz4_7j1_jQj_h -a;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_M41qv_vqQt_#j_JGlkN;_4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4kMjH_OH -M;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk4M._kVb_;O# -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.kM4C_Ls -s;N3MR#CNP_0MC_NVDoR#4.;6n -RoMk_Mn8j#_d -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMkdM4_HOHMN; +n;okMRM74_1j_jjh_ q Ap_#j_JGlkNN; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRM_4jOMHH;M +NRN3#PMC_CV0_D#No46R.no; +MMRk.V4_bOk_#N; +M#R3N_PCM_C0VoDN#.4R6 +n;okMRM_.4LsCs;M +NRN3#PMC_CV0_D#No46R.no; +MMRk.#_8_jjd;M +NRN3#PMC_CV0_D#No46R.no; +M_RhnN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_n +U;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_g RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_jN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;44 +n;ohMR_;4d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_.N; +oR4h_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4c +n;ohMR_;4U RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_6N; +oR4h_gN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.j +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_4N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.. +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_dN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;.c RNM3P#NCC_M0D_VN4o#Rn.6;M oR.h_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.( +n;ohMR_;.n RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_UN; +oR.h_(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.g +n;ohMR_;.U RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_jN; +oR.h_gN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;d4 +n;ohMR_;dj RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_.N; +oRdh_4N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;dd +n;ohMR_;d. RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_cN; +oRdh_6N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;d6 +n;ohMR_;dn RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_nN; +oRdh_UN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;dU +n;ohMR_;c4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRdh_gN; +oRch_.N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cj +n;ohMR_;cd RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_4N; +oRch_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;c. +n;ohMR_;c6 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_dN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;cn -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRch_UN; +oRch_nN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;cg RNM3P#NCC_M0D_VN4o#Rn.6;M @@ -440,45 +444,53 @@ n;ohMR_;6d RNM3P#NCC_M0D_VN4o#Rn.6;M oR6h_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;nU +n;ohMR_;66 RNM3P#NCC_M0D_VN4o#Rn.6;M -oRnh_gN; +oR6h_nN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(j -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_4N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(. -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_dN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;(c -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR(h_6N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_c..;M +n;ohMR_(4U;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;.6 +M_Rh4;UU RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_. -n;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhc_.6N; +oR4h_U +g;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh4_.gN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_c.(;M +n;ohMR_j..;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;(n +M_Rh.;6g RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_Atj_jjjM3kdN; +oR.h_n +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhn_.nN; M#R3N_PCM_C0VoDN#.4R6 -n;oAMRtj_jj3_jk;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_Atj_jjjM3kjN; -M#R3N_PCM_C0VoDN#.4R6 -n;ozMR7j1_jQj_hja_3dkM;M +n;ohMR_(.n;M NRN3#PMC_CV0_D#No46R.no; -M7Rz1j_jjh_Qa3_jk;M4 +M_Rh.;nU +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_71j_jj7_vqjM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;o7MR1j_jjv_7q3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_71j_jj7_vqjM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMR1j_jjv_7q3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_q1j_jj7_vqjM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMR1j_jjv_7q3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M oR1z7_jjj_aQh_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMz_71j_jjQ_hajM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;ozMR7j1_jQj_hja_3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MtRA_jjj_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMAjt_jjj_34kM;M +NRN3#PMC_CV0_D#No46R.no; +MtRA_jjj_kj3M j;N3MR#CNP_0MC_NVDoR#4.;6n RoMp_71j_jjQ_hajM3kdN; M#R3N_PCM_C0VoDN#.4R6 @@ -486,101 +498,47 @@ n;opMR7j1_jQj_hja_34kM;M NRN3#PMC_CV0_D#No46R.no; M7Rp1j_jjh_Qa3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_71j_jj Ahqpj _3dkM;M +oR_q1j_dj7j4_3dkM;M NRN3#PMC_CV0_D#No46R.no; -M1R7_jjj_q hA_p jM3k4N; +M1Rq_jjd__74jM3k4N; M#R3N_PCM_C0VoDN#.4R6 -n;o7MR1j_jjh_ q Ap_kj3M +n;oqMR1d_jj4_7_kj3M j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMQ_upj_djj__.3dkM;M +RoM)jW_jQj_hja_3dkM;M NRN3#PMC_CV0_D#No46R.no; -MuRQpd_jj__j.k_3M +MWR)_jjj_aQh_kj3M 4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMQ_upj_djj__.3jkM;M +RoM)jW_jQj_hja_3jkM;M NRN3#PMC_CV0_D#No46R.no; -MvReqh_Qa3_jk;Md +M1Rq_jjd_jjj_h1YB3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqev_aQh_kj3M +oR_q1j_djj_jj1BYh_kj3M 4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMe_vqQ_hajM3kjN; +RoMqj1_djj_j1j_Y_hBjM3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__34_k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_4j__M3k4N; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__34_k;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_.j__M3kdN; -M#R3N_PCM_C0VoDN#.4R6 -n;oOMRbCk_#j0__3._k;M4 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRkOb_0C#_.j__M3kjN; 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-R:fjjNRlOQERhbeRsRHlh(_.c -_HShm=_c.(_SH -Qhj=_c.(;R -sfjj:ROlNEhRQesRbHQlRujp_djj__3j_sm -S=pQu_jjd_jj__M3kdQ -SjF=b#D_O H\3b -D;sjRf:ljRNROEq.h7RHbsluRQpd_jj__jjl_3 -=SmQ_upj_djj__j34kM -jSQ=pQu_jOr9Q -S4F=b#D_O H\3b -D;sjRf:ljRNROEq.h7RHbsluRQpd_jj__jjM_3 -=SmQ_upj_djj__j3jkM -jSQ=pQu_jjd_jOr9Q -S4u=Qpd_jj__jjk_3M -d;sjRf:ljRNROEmR).blsHRpQu_jjd_jj__ -3bShm=_ -.cS=QjQ_upj_djj__j34kM -4SQ=pQu_jjd_jj__M3kjs; -R:fjjNRlOQERhbeRsRHlQ_upj_djj__43Ss -mu=Qpd_jj__j4k_3MSd -Qbj=FO#_D3 \H;bD -fsRjR:jlENOR7qh.sRbHQlRujp_djj__34_lm -S=pQu_jjd_4j__M3k4Q -Sju=Qpr_O4S9 -Qb4=FO#_D3 \H;bD -fsRjR:jlENOR7qh.sRbHQlRujp_djj__34_Mm -S=pQu_jjd_4j__M3kjQ -Sju=Qpd_jjr_O4S9 -QQ4=ujp_djj__34_k;Md -fsRjR:jlENOR.m)RHbsluRQpd_jj__j4b_3 -=Smh6_. -jSQ=pQu_jjd_4j__M3k4Q -S4u=Qpd_jj__j4k_3M -j;sjRf:ljRNROEQRheblsHR(kM__N#j_djHm -S=(kM__N#j_djHQ -SjM=k(#_N_jjd;R -sfjj:ROlNEhRQesRbHhlR_.4._SH -m_=h4_..HQ -Sj_=h4;.. -fsRjR:jlENOReQhRHbsl_Rh4_.dHm -S=4h_.Hd_ -jSQ=4h_. -d;sjRf:ljRNROEQRheblsHRnkM__8#j_djHm -S=nkM__8#j_djHQ -SjM=kn#_8_jjd;R -sfjj:ROlNEhRQesRbHklRM_4dOMHH_SH -mM=k4Od_H_HMHQ -SjM=k4Od_H;HM -fsRjR:jlENOReQhRHbsl1Rq_jjd_jjj_h1YB3_jsm -S=_q1j_djj_jj1BYh_kj3MSd -Qhj=_;nc -fsRjR:jlENOR7qh.sRbHqlR1d_jjj_jjY_1hjB_3Sl -m1=q_jjd_jjj_h1YB3_jk -M4S=Qjqj1_djj_j1j_Y -hBS=Q4hc_n;R -sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hBj -3MSqm=1d_jjj_jjY_1hjB_3jkM -jSQ=_q1j_djOQ -S41=q_jjd_jjj_h1YB3_jk;Md -fsRjR:jlENOR.m)RHbsl1Rq_jjd_jjj_h1YB3_jbm -S=4h_cQ -Sj1=q_jjd_jjj_h1YB3_jk -M4S=Q4qj1_djj_j1j_Y_hBjM3kjs; -R:fjjNRlOQERhbeRsRHl)jW_jQj_hja_3Ss -mW=)_jjj_aQh_kj3MSd -Qkj=M14_vv_qQ_tqjJ_#lNkG_ -4;sjRf:ljRNROEq.h7RHbslWR)_jjj_aQh_lj3 -=Sm)jW_jQj_hja_34kM -jSQ=#bF_ OD\W3)_jjj_aQh_S6 -Qk4=M14_vv_qQ_tqjJ_#lNkG_ -4;sjRf:ljRNROEq.h7RHbslWR)_jjj_aQh_Mj3 -=Sm)jW_jQj_hja_3jkM -jSQ=_)Wj_jjQ -haS=Q4)jW_jQj_hja_3dkM;R -sfjj:ROlNE)Rm.sRbH)lRWj_jjh_Qa3_jbm -S=4h_6Q -SjW=)_jjj_aQh_kj3MS4 -Q)4=Wj_jjh_Qa3_jk;Mj -fsRjR:jlENOR7qh.sRbH)lRWj_jjh_Qa -_4Shm=__dUjQ -Sj_=h4H6_ -4SQ=a)1_ -O;sjRf:ljRNROEq.h7RHbsl1Rq_jjd_jjj_h1YB -_4Shm=__dgjQ -Sj_=h4Hc_ -4SQ=a)1_ -O;sjRf:ljRNROEq.h7RHbsluRQpj_7_jjr9m -S=ch_g -_jS=QjQ_upOr_HjS9 -Q)4=1Oa_;R -sfjj:ROlNEhRq7b.RsRHlQ_up7jj_r -49Shm=__6jjQ -Sju=Qp__OH9r4 -4SQ=a)1_ -O;sjRf:ljRNROEq.h7RHbsluRQpd_jjr_4jS9 -m_=h.j(_ -jSQ=.h_c -_HS=Q4)_1aOs; -R:fjjNRlOqERhR7.blsHRpQu_jjd_44r9m -S=.h_U -_jS=Qjh6_._SH -Q)4=1Oa_; - - - @ diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index d27def8..b56015a 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Thu Dec 29 16:01:49 2016 +#Sat Dec 30 00:43:29 2017 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -20,18 +20,22 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vh @N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral @N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e @N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000 -@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven -@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:7:133:15|Signal clk_030_h is undriven +@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:7:130:17|Signal clk_out_pre is undriven +@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":134:7:134:15|Signal clk_030_h is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register AS_000_D0_3 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register nEXP_SPACE_D0_3 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning register BGACK_030_INT_PRE_2 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2 -@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register DTACK_DMA_4 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register CLK_030_PE_2(1 downto 0) +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register AS_000_D0_3 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register RESET_OUT_4 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register RST_DLY_6(2 downto 0) +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register nEXP_SPACE_D0_3 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register BGACK_030_INT_PRE_2 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:36:128:38|Pruning register CLK_OUT_PRE_25_3 +@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":158:2:158:3|Pruning register CLK_030_D0_2 +@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... +@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -42,14 +46,16 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Trying to extract state machine for register cpu_est @W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused +@W: CL159 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":34:1:34:7|Input CLK_030 is unused +@W: CL158 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":50:1:50:5|Inout RESET is unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 29 16:01:49 2016 +# Sat Dec 30 00:43:29 2017 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -59,7 +65,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 29 16:01:50 2016 +# Sat Dec 30 00:43:31 2017 ###########################################################] Map & Optimize Report @@ -68,7 +74,6 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:38:132:40|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -83,15 +88,15 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 57 uses -BI_DIR 19 uses -BUFTH 3 uses -IBUF 38 uses -OBUF 15 uses -AND2 277 uses -INV 236 uses -OR2 23 uses -XOR2 8 uses +DFF 52 uses +BI_DIR 18 uses +BUFTH 4 uses +IBUF 39 uses +OBUF 14 uses +AND2 221 uses +INV 203 uses +OR2 17 uses +XOR2 4 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -101,6 +106,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 29 16:01:51 2016 +# Sat Dec 30 00:43:31 2017 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index bc001f9..3bae7cf 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index af14317..d56682f 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -19,8 +19,8 @@ 0 C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed - 12/29/16 15:52:11 - 0x82ED + 02/24/17 22:00:28 + 0x1D0F Erase,Program,Verify